WO2024057165A1 - Storage device - Google Patents

Storage device Download PDF

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Publication number
WO2024057165A1
WO2024057165A1 PCT/IB2023/058969 IB2023058969W WO2024057165A1 WO 2024057165 A1 WO2024057165 A1 WO 2024057165A1 IB 2023058969 W IB2023058969 W IB 2023058969W WO 2024057165 A1 WO2024057165 A1 WO 2024057165A1
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WIPO (PCT)
Prior art keywords
insulator
conductor
opening
oxide
transistor
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PCT/IB2023/058969
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French (fr)
Japanese (ja)
Inventor
宮入秀和
松木充弘
Original Assignee
株式会社半導体エネルギー研究所
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Publication of WO2024057165A1 publication Critical patent/WO2024057165A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one embodiment of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer and a module.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are examples of semiconductor devices.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits, imaging devices, electronic devices, and the like can be said to include semiconductor devices.
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.
  • a CPU is an assembly of semiconductor elements, including a semiconductor integrated circuit (at least a transistor and a capacitor) formed into a chip by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.
  • a technology that constructs a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention.
  • the transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are attracting attention as other materials.
  • Patent Document 1 discloses a CPU with low power consumption that takes advantage of the low leakage current of a transistor using an oxide semiconductor.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a small leakage current.
  • Patent Document 3 and Non-Patent Document 1 a plurality of memory cells are provided in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film. discloses a technique for increasing the density of integrated circuits.
  • Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.
  • JP2012-257187A JP2011-151383A International Publication No. 2021/053473 JP2013-211537A
  • An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.
  • one of the challenges is to provide a storage device with high operating speed.
  • one of the challenges is to provide a storage device having good electrical characteristics.
  • one of the challenges is to provide a storage device with good reliability.
  • one of the challenges is to provide a storage device with a large on-state current.
  • one of the challenges is to provide a storage device with low power consumption.
  • one of the challenges is to provide a new storage device.
  • one of the objectives is to provide a method for manufacturing a new storage device.
  • One embodiment of the present invention is a memory device that includes a first memory cell, a second memory cell, a first insulator, and a second insulator over the first insulator.
  • the first memory cell includes a first capacitive element and a first transistor on the first capacitive element.
  • the second memory cell includes a second capacitive element and a second transistor on the second capacitive element.
  • the interval between the first capacitive element and the second capacitive element matches the interval between the first transistor and the second transistor.
  • the first insulator has a first opening and a second opening. At least a portion of the first capacitive element is arranged in the first opening. At least a portion of the second capacitive element is arranged in the second opening.
  • the second insulator has a third opening and a fourth opening. At least a portion of the first transistor is arranged in the third opening. At least a portion of the second transistor is arranged in the fourth opening.
  • the first opening has a region that overlaps with the third opening.
  • the second opening has a region that overlaps with the fourth opening.
  • the first opening and the third opening have different maximum widths.
  • the second opening and the fourth opening have different maximum widths.
  • the maximum width of the first opening may be larger than the maximum width of the third opening, and the maximum width of the second opening may be larger than the maximum width of the fourth opening. preferable.
  • the channel length of the first transistor is preferably smaller than the channel width of the first transistor
  • the channel length of the second transistor is preferably smaller than the channel width of the second transistor
  • each of the first transistor and the second transistor includes an oxide semiconductor in the semiconductor layer, and the oxide semiconductor includes one or more selected from In, Ga, and Zn. It is preferable to have.
  • each of the first capacitive element and the second capacitive element includes a first conductor, a third insulator on the first conductor, and a third insulator on the third insulator.
  • the third insulator may include a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide. preferable.
  • the memory device has a plurality of layers including a first memory cell and a second memory cell, and the plurality of layers are stacked.
  • One embodiment of the present invention provides a memory device including a first conductor, a memory cell on the first conductor, a first insulator on the first conductor, and a second insulator. It is.
  • the memory cell includes a capacitor and a transistor on the capacitor.
  • the capacitive element includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator.
  • the first insulator is provided with a first opening that reaches the first conductor. At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening.
  • a second insulator is disposed on the second conductor, the third insulator, and the third conductor.
  • the transistor includes a third conductor, a fourth conductor on a second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor.
  • the second insulator and the fourth conductor are provided with a second opening that reaches the third conductor. At least a portion of the oxide semiconductor is disposed in the second opening.
  • the oxide semiconductor includes at least a region in contact with the top surface of the third conductor in the second opening, a region in contact with the side surface of the fourth conductor in the second opening, and a region in contact with the top surface of the fourth conductor in the second opening. It has a region that touches a part of it.
  • the fourth insulator is disposed on the oxide semiconductor so that at least a portion thereof is located in the second opening.
  • the fifth conductor is disposed on the fourth insulator such that at least a portion thereof is located in the second opening.
  • the first opening and the second opening have different maximum widths.
  • the maximum width of the first opening is preferably larger than the maximum width of the second opening.
  • the second opening has a region that overlaps with the first opening.
  • the channel length of the transistor is preferably smaller than the channel width of the transistor.
  • the third insulator preferably includes a material that can have ferroelectricity.
  • the third insulator preferably includes first zirconium oxide, aluminum oxide on the first zirconium oxide, and second zirconium oxide on the aluminum oxide.
  • the oxide semiconductor preferably contains one or more selected from In, Ga, and Zn.
  • the first insulator includes a laminate
  • the laminate includes a first layer
  • the first layer includes:
  • the second layer contains silicon and nitrogen
  • the second layer contains silicon and oxygen.
  • a fifth insulator is provided between the side surface of the first insulator in the first opening and the second conductor, and the fifth insulator is made of silicon and nitrogen. It is preferable to have the following.
  • the fifth conductor is provided extending in the first direction
  • the fourth conductor is provided extending in the second direction
  • the fifth conductor is provided extending in the first direction and the fourth conductor is provided extending in the second direction. It is preferable that the second direction is perpendicular to the second direction.
  • the above memory device preferably has a plurality of layers including memory cells, and the plurality of layers are preferably stacked.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a storage device with high operating speed can be provided.
  • a highly reliable storage device can be provided.
  • a memory device with less variation in the electrical characteristics of transistors can be provided.
  • a storage device with good electrical characteristics can be provided.
  • a storage device with a large on-state current can be provided.
  • a storage device with low power consumption can be provided.
  • new storage devices can be provided.
  • a method for manufacturing a new storage device can be provided.
  • FIG. 1A is a plan view showing an example of a storage device.
  • FIG. 1B and FIG. 1C are cross-sectional views showing an example of a storage device.
  • FIG. 1D is a circuit diagram for explaining an example of the configuration of a storage device.
  • FIG. 2A is a plan view showing an example of a storage device.
  • 2B and 2C are cross-sectional views showing an example of a storage device.
  • FIG. 3A is a plan view showing an example of a storage device.
  • 3B and 3C are cross-sectional views showing an example of a storage device.
  • 4A and 4B are plan views showing an example of a storage device.
  • FIG. 5A is a plan view showing an example of a storage device.
  • FIG. 5B and 5C are cross-sectional views showing an example of a storage device.
  • 6A to 6D are cross-sectional views showing an example of a storage device.
  • FIG. 7A is a plan view showing an example of a storage device.
  • 7B and 7C are cross-sectional views showing an example of a storage device.
  • FIG. 8A is a plan view showing an example of a storage device.
  • 8B and 8C are cross-sectional views showing an example of a storage device.
  • FIG. 9A is a plan view showing an example of a storage device.
  • 9B and 9C are cross-sectional views showing an example of a storage device.
  • FIG. 10A is a plan view showing an example of a storage device.
  • 10B and 10C are cross-sectional views showing an example of a storage device.
  • FIG. 11A is a plan view showing an example of a storage device.
  • 11B and 11C are cross-sectional views showing an example of a storage device.
  • 12A to 12D are cross-sectional views showing an example of a storage device.
  • FIG. 13A is a cross-sectional view showing an example of a storage device.
  • FIG. 13B is a cross-sectional view showing an example of a storage device.
  • 14A to 14D are cross-sectional views showing an example of a storage device.
  • FIG. 15A is a plan view showing an example of a storage device.
  • 15B and 15C are cross-sectional views showing an example of a storage device.
  • 16A and 16B are cross-sectional views showing an example of a storage device.
  • FIG. 17A to 17D are cross-sectional views showing an example of a storage device.
  • 18A and 18B are cross-sectional views showing an example of a storage device.
  • FIG. 19A is a plan view showing an example of a storage device.
  • 19B and 19C are cross-sectional views showing an example of a storage device.
  • FIG. 20A is a plan view showing an example of a storage device.
  • 20B and 20C are cross-sectional views showing an example of a storage device.
  • FIG. 21A is a plan view showing an example of a storage device.
  • 21B and 21C are cross-sectional views showing an example of a storage device.
  • FIG. 22A is a plan view illustrating an example of a method for manufacturing a storage device.
  • FIG. 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 23A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 24A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 25A is a plan view showing an example of a method for manufacturing a storage device.
  • 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • 26A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 27A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 28A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 29A is a plan view illustrating an example of a method for manufacturing a storage device.
  • FIG. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 30A is a plan view showing an example of a method for manufacturing a storage device.
  • 30B and 30C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 31A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 31B and 31C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 32A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 32B and 32C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 30A is a plan view showing an example of a method for manufacturing a storage device.
  • 30B and 30C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 31A is a plan view
  • 33A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 33B and 33C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 34A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 34B and 34C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 35A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 35B and 35C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 36A is a plan view illustrating an example of a method for manufacturing a storage device.
  • FIG. 36B and 36C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 37A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 37B and 37C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 38A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 38B and 38C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 39A is a plan view showing an example of a storage device.
  • FIG. 39B is a cross-sectional view showing an example of a storage device.
  • FIG. 40A is a plan view showing an example of a storage device.
  • FIG. 40A is a plan view showing an example of a storage device.
  • FIG. 40B is a cross-sectional view showing an example of a storage device.
  • FIG. 41A is a plan view showing an example of a storage device.
  • FIG. 41B is a cross-sectional view showing an example of a storage device.
  • 42A to 42C are planar layouts showing an example of a storage device.
  • 43A to 43C are planar layouts showing an example of a storage device.
  • FIG. 44 is a cross-sectional view showing an example of a storage device.
  • FIG. 45 is a block diagram showing an example of a storage device.
  • 46A and 46B are schematic diagrams showing an example of a storage device.
  • 47A to 47D are circuit diagrams showing an example of a storage device.
  • FIG. 48 is a circuit diagram showing an example of a storage device.
  • 49A and 49B are diagrams showing an example of an electronic component.
  • 50A and 50B are diagrams illustrating an example of an electronic device.
  • FIGS. 50C to 50E are diagrams showing an example of a large-sized computer.
  • FIG. 51 is a diagram showing an example of space equipment.
  • FIG. 52 is a diagram illustrating an example of a storage system applicable to a data center.
  • the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.
  • a layer or a resist mask may be unintentionally reduced due to a process such as etching, but this may not be reflected in the diagram for ease of understanding.
  • the same reference numerals are used for the same parts or parts having similar functions in different drawings, and repeated explanations thereof may be omitted.
  • the hatching pattern may be the same and no particular reference numeral may be attached.
  • ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by replacing “first” with “second” or “third” as appropriate. Furthermore, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected means that X and Y are electrically connected.
  • X and Y are electrically connected refers to an object (a switch, a transistor element, an element such as a diode, or a circuit including the element and wiring) between X and Y.
  • X and Y are electrically connected refers to an object (a switch, a transistor element, an element such as a diode, or a circuit including the element and wiring) between X and Y.
  • X and Y are electrically connected refers to an object (a switch, a transistor element, an element such as a diode, or a circuit including the element and wiring) between X and Y.
  • X and Y are electrically connected refers to an object (a switch, a transistor element, an element such as a diode, or a circuit including the element and wiring) between X and Y.
  • X and Y are directly connected means that electrical signals are transmitted between X and Y via wiring (or electrode
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode). A current can be passed between the source and the drain through the formation region.
  • a channel formation region refers to a region through which current mainly flows.
  • the function of the source or drain may be swapped if transistors with different polarities are used, or if the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain may be used interchangeably.
  • impurity of a semiconductor refers to, for example, something other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic % can be considered an impurity.
  • the inclusion of impurities may cause, for example, an increase in the defect level density of the semiconductor, a decrease in crystallinity, and the like.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and the oxide semiconductor.
  • transition metals other than the main components such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • oxynitride refers to a composition containing more oxygen than nitrogen.
  • examples of the oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.
  • the nitrided oxide has a composition containing more nitrogen than oxygen.
  • examples of the nitride oxide include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.
  • the term “insulator” can be translated as an insulating film or an insulating layer. Further, the term “conductor” can be translated as a conductive film or a conductive layer. Further, the term “semiconductor” can be translated as a semiconductor film or a semiconductor layer.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included.
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included.
  • substantially perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • Voltage refers to a potential difference from a reference potential.
  • the reference potential is a ground potential (earth potential)
  • “voltage” can be translated into “potential.” Note that the ground potential does not necessarily mean 0V.
  • potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to circuits, etc., the potential output from circuits, etc. also change.
  • the code when the same code is used for multiple elements, especially when it is necessary to distinguish between them, the code may include an identification such as "_1", “[n]", or "[m,n]". In some cases, a special code may be added to the description.
  • the heights match refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • a reference surface for example, a flat surface such as a substrate surface
  • the surface of a single layer or a plurality of layers may be exposed by performing a planarization process (typically a CMP (Chemical Mechanical Polishing) process).
  • CMP Chemical Mechanical Polishing
  • the surfaces to be subjected to CMP processing have the same height from the reference surface.
  • the heights of the plurality of layers may differ depending on the processing apparatus, processing method, or material of the surface to be processed during CMP processing.
  • the heights match In this specification, this case is also treated as "the heights match.”
  • the height of the top surface of the first layer and the height of the second layer are Even if the difference from the height of the top surface of the layer is 20 nm or less, it is also said that the heights match.
  • the ends coincide means that at least a portion of the outlines of the stacked layers overlap in plan view. For example, this includes a case where the upper layer and the lower layer are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours do not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. "Concordance”.
  • match includes both a complete match and a general match.
  • normally-on characteristics refer to a state in which a channel exists and current flows through the transistor even without applying a potential to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • off-state current may refer to, for example, a current flowing between a source and a drain when a transistor is in an off state.
  • a memory device that is one embodiment of the present invention includes one or more memory cells. Further, the memory cell includes a transistor and a capacitor.
  • FIG. 1A to 1C are a plan view and a cross-sectional view of a memory device having a memory cell 150.
  • FIG. 1A is a plan view of the storage device.
  • FIGS. 1B and 1C are cross-sectional views of the storage device.
  • FIG. 1B is a sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. Note that in the plan view of FIG. 1A, some elements are omitted for clarity.
  • arrows indicating the X direction, Y direction, and Z direction may be attached.
  • the "X direction” refers to the direction along the X axis, and the forward direction and reverse direction may not be distinguished unless explicitly stated.
  • the X direction, the Y direction, and the Z direction are directions that intersect with each other.
  • the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other.
  • one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction” or a “first direction.”
  • the other one may be called a "second direction” or a “second direction”.
  • the remaining one may be referred to as a "third direction” or "third direction.”
  • the memory device shown in FIGS. 1A to 1C includes an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 on the conductor 110, and an insulator on the conductor 110.
  • the memory cell includes a body 180, an insulator 280 on the insulator 180, and an insulator 283 on the memory cell 150. Insulator 140, insulator 180, insulator 280, and insulator 283 function as interlayer films.
  • the conductor 110 functions as a wiring.
  • the memory cell 150 includes a capacitive element 100 on a conductor 110 and a transistor 200 on the capacitive element 100.
  • the capacitive element 100 includes a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130.
  • the conductor 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductor 115 functions as the other of a pair of electrodes (sometimes called a lower electrode)
  • the insulator 130 functions as a dielectric. functions as In other words, the capacitive element 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.
  • the insulator 180 is provided with an opening 190 that reaches the conductor 110. At least a portion of the capacitive element 100 is arranged in the opening 190. Specifically, at least a portion of the conductor 115 , at least a portion of the insulator 130 , and at least a portion of the conductor 120 are arranged in the opening 190 . Note that the conductor 115 has a region in contact with the top surface of the conductor 110 at the opening 190, a region in contact with the side surface of the insulator 180 in the opening 190, and a region in contact with at least a part of the top surface of the insulator 180. have Further, the conductor 120 is preferably provided so as to fill the opening 190, as shown in FIGS. 1B and 1C.
  • the capacitive element 100 has a structure in which the upper electrode and the lower electrode face each other with a dielectric interposed not only on the bottom surface but also on the side surface of the opening 190, and the capacitance per unit area can be increased. can. Therefore, as the depth of the opening 190 is increased, the capacitance of the capacitive element 100 can be increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, the read operation of the storage device can be stabilized. Further, it is possible to promote miniaturization or higher integration of storage devices.
  • the side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. At this time, the opening 190 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • the opening 190 is circular in plan view, but the present invention is not limited to this.
  • the opening 190 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • the maximum width of the opening 190 may be calculated as appropriate depending on the shape of the top of the opening 190.
  • the maximum width of the opening 190 may be the length of the diagonal line at the top of the opening 190.
  • the conductor 115, the insulator 130, and the portion of the conductor 120 arranged in the opening 190 are provided to reflect the shape of the opening 190. Therefore, the conductor 115 is provided to cover the bottom and side walls of the opening 190, the insulator 130 is provided to cover the conductor 115, and the recess of the insulator 130 that reflects the shape of the opening 190 is filled. A conductor 120 is provided.
  • a conductor 115 and an insulator 130 are laminated along the side wall of the opening 190 and the top surface of the conductor 110. Further, a conductor 120 is provided on the insulator 130 so as to fill the opening 190.
  • the capacitive element 100 having such a configuration may be called a trench-type capacitor or a trench capacitor.
  • An insulator 280 is placed on the capacitive element 100. That is, the insulator 280 is placed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is placed under the insulator 280.
  • the transistor 200 includes a conductor 120, a conductor 240 over an insulator 280, an oxide semiconductor 230, an insulator 250 over the oxide semiconductor 230, and a conductor 260 over the insulator 250.
  • the oxide semiconductor 230 functions as a semiconductor layer
  • the conductor 260 functions as a gate electrode
  • the insulator 250 functions as a gate insulator
  • the conductor 120 functions as one of a source electrode and a drain electrode
  • the conductor 240 functions as a source electrode and a drain electrode. functions as the other of the source electrode and the drain electrode.
  • the insulator 280 and the conductor 240 are provided with an opening 290 that reaches the conductor 120. That is, the opening 290 is composed of an opening provided in the insulator 280 and an opening provided in the conductor 240. At this time, it is preferable that the side edge of the opening provided in the insulator 280 and the side edge of the opening provided in the conductor 240 coincide with each other.
  • At least a portion of the oxide semiconductor 230 is arranged in the opening 290.
  • the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 at the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a part of the top surface of the conductor 240. has.
  • Insulator 250 is arranged such that at least a portion thereof is located in opening 290 .
  • the conductor 260 is arranged so that at least a portion thereof is located in the opening 290.
  • the conductor 260 is preferably provided so as to fill the opening 290, as shown in FIGS. 1B and 1C.
  • the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the upper surface of the conductor 240. In this way, since the oxide semiconductor 230 is in contact with not only the side surface but also the top surface of the conductor 240, the area in which the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
  • the transistor 200 is provided so as to overlap the capacitive element 100. Further, the opening 290 in which a part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which a part of the structure of the capacitor 100 is provided. Further, since the conductor 120 has a function as one of a source electrode and a drain electrode of the transistor 200 and a function as an upper electrode of the capacitor 100, the transistor 200 and the capacitor 100 share a part of the structure. I will do it. With such a configuration, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in plan view. As a result, the area occupied by the memory cells 150 can be reduced, so the memory cells 150 can be arranged with high density and the storage capacity of the memory device can be increased. In other words, the storage device can be highly integrated.
  • FIG. 1D A circuit diagram of the memory device shown in this embodiment is shown in FIG. 1D.
  • the configuration shown in FIGS. 1A to 1C functions as a memory cell of a storage device.
  • the memory cell includes a transistor Tr and a capacitive element C.
  • the transistor Tr corresponds to the transistor 200
  • the capacitive element C corresponds to the capacitive element 100.
  • One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitive element C.
  • the other of the source and drain of the transistor Tr is connected to the wiring BL.
  • the gate of the transistor Tr is connected to the wiring WL.
  • the other of the pair of electrodes of the capacitive element C is connected to the wiring PL.
  • the wiring BL corresponds to the conductor 240
  • the wiring WL corresponds to the conductor 260
  • the wiring PL corresponds to the conductor 110.
  • the conductor 260 is preferably provided to extend in the Y direction
  • the conductor 240 is preferably provided to extend in the X direction.
  • the wiring BL and the wiring WL are provided to intersect with each other. By intersecting the wiring BL and the wiring WL, the area of the region where the wiring BL and the wiring WL overlap becomes smaller, and the parasitic capacitance generated between the wiring BL and the wiring WL can be reduced. Further, in FIG.
  • the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited to this.
  • the wiring PL may be provided parallel to the wiring WL (conductor 260) or may be provided parallel to the wiring BL (conductor 240).
  • FIGS. 2A to 2C show a configuration in which the conductor 110 is provided extending in the Y direction. At this time, the conductor 110 is provided parallel to the conductor 260. Further, the conductor 110 is orthogonal to the conductor 240.
  • FIGS. 3A to 3C show a configuration in which the conductor 110 is provided extending in the X direction. At this time, the conductor 110 is provided parallel to the conductor 240. Further, the conductor 110 is perpendicular to the conductor 260.
  • FIG. 1B shows a configuration in which the conductor 115 is divided in the X direction
  • the present invention is not limited to this.
  • the conductor 115 may be provided extending in the X direction.
  • the conductor 110 is provided in a planar shape
  • the conductor 115 may be provided extending in the X direction and the Y direction.
  • the memory device of one embodiment of the present invention preferably includes a plurality of memory cells 150 arranged in a matrix.
  • 4A and 4B show, as an example, a memory device in which 2 ⁇ 2 memory cells 150 are arranged in a matrix in the X direction and the Y direction.
  • FIG. 4A is a plan view of a region including four transistors (transistors 200p to 200s). Note that FIG. 4A selectively shows the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290 that each transistor has. Note that openings 290 provided in the insulator 280 and the conductor 240 are shown by dotted lines. Further, in FIG. 4A, the insulator 280 is not illustrated.
  • the conductor 240 and the insulator 280 have an opening 290p, an opening 290q, an opening 290r, and an opening 290s. At least part of the transistor 200p is arranged in the opening 290p, at least part of the transistor 200q is arranged in the opening 290q, at least part of the transistor 200r is arranged in the opening 290r, and at least part of the transistor 200r is arranged in the opening 290s. At least a portion of the transistor 200s is arranged.
  • FIG. 4B is a plan view of a region including four capacitive elements (capacitive elements 100p to 100s). Note that FIG. 4B shows an excerpt of the conductor 110, the conductor 115, the conductor 120, and the opening 190 that each capacitive element has. Note that the opening 190 provided in the insulator 180 is shown by a dotted line. Further, in FIG. 4B, the insulator 180 is not illustrated.
  • the insulator 180 has an opening 190p, an opening 190q, an opening 190r, and an opening 190s. At least a part of the capacitive element 100p is arranged in the opening 190p, at least a part of the capacitive element 100q is arranged in the opening 190q, at least a part of the capacitive element 100r is arranged in the opening 190r, and At least a part of the capacitive element 100s is arranged at 190s.
  • One memory cell is configured by the transistor 200p and the capacitive element 100p, one memory cell is configured by the transistor 200q and the capacitive element 100q, one memory cell is configured by the transistor 200r and the capacitive element 100r, and one memory cell is configured by the transistor 200s and the capacitive element.
  • One memory cell is configured by 100 seconds.
  • the opening 190p has a region overlapping with the opening 290p
  • the opening 190q has a region overlapping with the opening 290q
  • the opening 190r has a region overlapping with the opening 290r
  • the opening 190s has a region overlapping with the opening 290r. It has an area that overlaps with 290s.
  • the above description of the transistor 200 can be referred to for the configurations of the transistors 200p to 200s. Further, for the configurations of the capacitive elements 100p to 100s, the description of the capacitive element 100 described above can be referred to. Further, items common to the openings 190p to 190s may be referred to as the openings 190 for explanation. Furthermore, items common to the openings 290p to 290s may be referred to as the openings 290 in the description.
  • FIG. 4A shows the maximum width Dt of the opening 290 with a solid double-headed arrow. Note that when the opening is circular in plan view, the maximum width of the opening can be rephrased as the maximum diameter of the opening. Further, FIG. 4B shows the maximum width Dc of the opening 190 with a solid double-headed arrow.
  • the distance GPt between transistors adjacent in the X direction is indicated by a two-dot chain double-headed arrow.
  • the distance GPt is the interval at which the transistors 200 are arranged in the X direction.
  • the distance GPt is the distance between the transistor 200p and the transistor 200q.
  • the distance GPt can be said to be the distance between the centers of adjacent openings 290 in the X direction.
  • the distance GPt is the interval at which the conductors 260 functioning as the wiring WL are arranged. Therefore, the distance GPt can be rephrased as a gate pitch. Further, in FIG.
  • the distance GPc between adjacent capacitive elements in the X direction is indicated by a two-dot chain double-headed arrow.
  • the distance GPc is the interval at which the capacitive elements 100 are arranged in the X direction.
  • the distance GPc is the interval between the capacitive element 100p and the capacitive element 100q.
  • the distance GPc can be said to be the distance between the centers of adjacent openings 190 in the X direction.
  • the distance MPt between adjacent transistors in the Y direction is shown by a double-dotted chain arrow.
  • the distance MPt is the interval at which the transistors 200 are arranged in the Y direction.
  • the distance MPt is the interval between the transistor 200p and the transistor 200r.
  • the distance MPt is the distance between the centers of adjacent openings 290 in the Y direction.
  • the distance MPt is the interval at which the conductors 240 functioning as the wiring BL are arranged. Therefore, the distance MPt can be rephrased as metal pitch.
  • the distance MPc between adjacent capacitive elements in the Y direction is indicated by a double-dotted chain arrow.
  • the distance MPc is the interval at which the capacitive elements 100 are arranged in the Y direction. Further, the distance MPc is the interval between the capacitive element 100p and the capacitive element 100r. Here, it can be said that the distance MPc is the distance between the centers of adjacent openings 190 in the Y direction.
  • the opening 290 is provided to overlap the conductor 120. Furthermore, as shown in FIG. 4B, the opening 190 is provided so as to overlap the conductor 110.
  • the opening 190 and the opening 290 have different maximum widths.
  • the maximum width Dc of the opening 190 is preferably different from the maximum width Dt of the opening 290.
  • the maximum width Dc of the opening 190 is preferably larger than the maximum width Dt of the opening 290.
  • the capacitance of the capacitive element 100 can be increased.
  • the conductor 115, the insulator 130, and the conductor 120 can be reliably embedded in the opening 190, and a highly reliable storage device can be provided.
  • the area of the conductor 120 in plan view can be increased, and the alignment accuracy of the opening 290 can be relaxed. Therefore, it is possible to reduce the difficulty level in manufacturing fine memory cells.
  • the distance GPc matches the distance GPt.
  • the distance MPc matches the distance MPt.
  • distance A and distance B match means that the value obtained by dividing the absolute value of the difference between distance A and distance B by distance A is 0.1 or less. Alternatively, it means that the value obtained by dividing the absolute value of the difference between distance A and distance B by distance B is 0.1 or less.
  • the conductor 260 is, for example, a continuous film provided in common to the transistors 200 arranged in the Y direction. Further, the conductor 240 is, for example, a continuous film provided in common to the transistors 200 arranged in the X direction.
  • the maximum width of the opening 190 is larger than the maximum width of the opening 290.
  • the maximum width of the opening 190 is preferably different from the maximum width of the opening 290, so the maximum width of the opening 190 may be smaller than the maximum width of the opening 290.
  • the maximum width of opening 290 may be greater than the maximum width of opening 190.
  • 5A to 5C show an example in which the maximum width of the opening 290 is larger than the maximum width of the opening 190.
  • Capacitive element 100 includes a conductor 115, an insulator 130, and a conductor 120. Furthermore, a conductor 110 is provided below the conductor 115 . The conductor 115 has a region in contact with the conductor 110.
  • the conductor 110 is provided on the insulator 140.
  • the conductor 110 functions as a wiring PL, and can be provided in a planar shape, for example.
  • the conductor 110 the conductors described in the section [Conductor] described below can be used in a single layer or a laminated structure.
  • a highly conductive material such as tungsten can be used as the conductor 110. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved and the conductor 110 can sufficiently function as the wiring PL.
  • the conductor 115 is preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen, in a single layer or a laminate.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen in a single layer or a laminate.
  • titanium nitride or indium tin oxide with added silicon may be used.
  • a structure in which titanium nitride is laminated on tungsten may be used.
  • a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used.
  • the conductor 110 can be prevented from being oxidized by the insulator 130. Also, when an oxide insulator is used for the insulator 180, the conductor 110 can be prevented from being oxidized by the insulator 180.
  • the insulator 130 is provided on the conductor 115.
  • the insulator 130 is provided so as to be in contact with the top and side surfaces of the conductor 115. That is, it is preferable that the insulator 130 has a structure that covers the side end portions of the conductor 110. This can prevent short-circuiting between the conductor 115 and the conductor 120.
  • the insulator 130 it is preferable to use a material with a high dielectric constant, a so-called high-k material, described in the section [Insulator] described below.
  • a high-k material as the insulator 130, the insulator 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently secured.
  • the insulator 130 is used by laminating insulating layers made of a high-k material, and is made of a material having a high dielectric constant (high-k) and a material having a dielectric strength higher than that of the high-k material.
  • a laminated structure is used.
  • the insulator 130 an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulator having a relatively high dielectric strength, such as aluminum oxide the dielectric strength is improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulator 130.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • element J1 here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.
  • hafnium oxide examples include added materials.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set as appropriate.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 may be set to 1:1 or around 1:1.
  • element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Added materials, etc.
  • the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set as appropriate.
  • the ratio of the number of atoms of zirconium to the number of atoms of element J2 may be set to 1:1 or around 1:1.
  • lead titanate PbTiO x
  • barium strontium titanate BST
  • strontium titanate PZT
  • strontium bismuthate tantalate SBT
  • Piezoelectric ceramics having a perovskite structure such as bismuth ferrite (BFO) and barium titanate, may also be used.
  • examples of materials that can have ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen.
  • the element M1 is one or more selected from aluminum, gallium, indium, and the like.
  • the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate.
  • a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2.
  • materials that can have ferroelectricity include materials in which element M3 is added to the metal nitride described above.
  • the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.
  • examples of materials that can have ferroelectricity include perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a ⁇ alumina structure.
  • metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto.
  • a metal oxynitride obtained by adding nitrogen to the above-mentioned metal oxide, or a metal nitride obtained by adding oxygen to the above-mentioned metal nitride, etc. may be used.
  • the material that can have ferroelectricity for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used.
  • the insulator 130 can have a laminated structure made of a plurality of materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above may change not only due to film formation conditions but also due to various processes, so in this specification, only materials that exhibit ferroelectricity will be referred to. It is not only called a ferroelectric material, but also a material that can have ferroelectric properties.
  • a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even when processed into a thin film of several nanometers.
  • the film thickness of the insulator 130 can be set to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).
  • the film thickness is preferably 8 nm or more and 12 nm or less.
  • a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
  • a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a minute area.
  • the area (occupied area) of the ferroelectric layer when viewed from above is 100 ⁇ m 2 or less, 10 ⁇ m 2 or less, 1 ⁇ m 2 or less, or 0.1 ⁇ m 2 or less, it can have ferroelectricity.
  • the thickness is 10000 nm 2 or less, or 1000 nm 2 or less, it may have ferroelectricity.
  • a ferroelectric material is an insulator, and has the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be formed using a capacitive element using this material as a dielectric (hereinafter sometimes referred to as a ferroelectric capacitor).
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like.
  • a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the storage device described in this embodiment functions as a ferroelectric memory.
  • ferroelectricity is said to be developed when oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by an external electric field. Furthermore, the development of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, it is preferable for the insulator 130 to include a crystal having a rectangular crystal structure because ferroelectricity is exhibited. Note that the crystal structure of the crystal contained in the insulator 130 may be one or more selected from cubic, tetragonal, rectangular, monoclinic, and hexagonal. good. Further, the insulator 130 may have an amorphous structure. At this time, the insulator 130 may have a composite structure having an amorphous structure and a crystal structure.
  • the conductor 120 is provided in contact with a part of the upper surface of the insulator 130. Further, as shown in FIG. 4B, the side end portion of the conductor 120 is preferably located inside the side end portion of the conductor 115 in both the X direction and the Y direction. Note that in a structure in which the insulator 130 covers the side end portion of the conductor 115, the side end portion of the conductor 120 may be located outside the side end portion of the conductor 115.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a conductive material that is difficult to oxidize a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230.
  • the conductor 120 may have a structure in which tungsten is laminated on titanium nitride, for example.
  • the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described below.
  • a conductive material containing oxygen as the conductor 120, conductivity can be maintained even if the conductor 120 absorbs oxygen.
  • an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is suitable because it can maintain conductivity.
  • the conductor 120 for example, a single layer or a stack of indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used indium tin
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. At this time, the insulator 180b includes at least silicon and oxygen.
  • the insulator 180 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 180 may have a laminated structure.
  • the insulator 180 may have a laminated structure of an insulator 180a and an insulator 180b on the insulator 180a.
  • the insulator 180b it is preferable to use an insulating material that is applicable to the insulator 180 described above.
  • the insulator 180a it is preferable to use an insulator having barrier properties against oxygen, as described in the [Insulator] section below.
  • the oxygen contained in the insulator 180b may oxidize the conductor 110, increasing its resistance.
  • impurities such as hydrogen When impurities such as hydrogen are mixed into the insulator 130, leakage current generated between the upper electrode and the lower electrode may increase. Furthermore, when a material that can have ferroelectricity is used as the insulator 130, impurities such as hydrogen may be mixed into the material that can have ferroelectricity, which may reduce the crystallinity of the material that can have ferroelectricity. There is a risk of deterioration. Therefore, it is preferable to prevent impurities such as hydrogen from entering the insulator 130.
  • the insulator 180a it is preferable to use an insulator having barrier properties against hydrogen, which is described in the section [Insulator] described later. This can suppress hydrogen from diffusing into the insulator 130 from below the capacitive element 100 via the insulator 180b.
  • Silicon nitride and silicon nitride oxide can be suitably used for the insulator 180a because they each release less impurities (for example, water and hydrogen) from themselves and are less permeable to oxygen and hydrogen.
  • the insulator 180a includes at least silicon and nitrogen.
  • the insulator 180a it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced.
  • the insulator 180a magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 180a.
  • FIGS. 6A and 6B show a structure in which the insulator 180 has a two-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulator 180 may have a laminated structure of three or more layers.
  • an insulator may be provided between the conductor 115 and the insulator 130 and the insulator 180b in addition to the insulator 180a and the insulator 180b.
  • an insulator applicable to the insulator 180a can be used. This can suppress hydrogen from diffusing into the insulator 130 via the insulator 180b.
  • the insulator 185 is provided so as to be in contact with the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115.
  • the insulator 185 it is preferable to use an insulator that has barrier properties against hydrogen and is described in the section [Insulator] described below. This can suppress hydrogen from diffusing into the insulator 130 from outside the capacitive element 100 via the insulator 180.
  • silicon nitride or silicon nitride oxide can be used as the insulator 185.
  • the insulator 185 includes at least silicon and nitrogen.
  • the insulator 185 it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced.
  • the insulator 185 magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 185.
  • the insulator 185 is provided so as to be in contact with the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited to this. It's not something you can do.
  • the insulator 185 may be provided so as to be in contact with a part of the upper surface of the insulator 180a and the side surface of the insulator 180b at the opening 190.
  • FIGS. 1B and 1C show a configuration in which the conductor 115 has a region in contact with the upper surface of the insulator 180
  • the present invention is not limited to this.
  • the top surface of the conductor 115 may be level with the top surface of the insulator 180.
  • the side end of the conductor 120 may be located outside the side end of the conductor 115. Note that the side end of the conductor 120 may coincide with the side end of the conductor 115 or may be located inside the side end of the conductor 115.
  • FIGS. 7A to 7C show a configuration in which the height of the top surface of the conductor 120 is higher than the height of the top surface of the insulator 130
  • the present invention is not limited to this.
  • the height of the top surface of the conductor 120 may match the height of the top surface of the insulator 130, or may be lower than the height of the top surface of the insulator 130.
  • FIG. 8A is a plan view showing an example of a storage device.
  • FIGS. 8B and 8C are cross-sectional views of the storage device.
  • FIG. 8B is a sectional view of a portion shown by a dashed line A1-A2 in FIG. 8A.
  • FIG. 8C is a cross-sectional view of the portion shown by the dashed line A3-A4 in FIG. 8A. Note that in the plan view of FIG. 8A, some elements are omitted for clarity.
  • the memory device shown in FIGS. 8A to 8C differs from the memory device shown in FIGS. 7A to 7C mainly in the shape of the conductor 120.
  • the larger the maximum width of the opening 190 the smaller the distance between the side surfaces of adjacent conductors 120. The smaller the distance, the more difficult it becomes to separate adjacent conductors 120. If adjacent conductors 120 are provided in common between adjacent capacitive elements 100 without being separated, leakage current will flow between the capacitive elements 100.
  • the height of the top surface of the conductor 120 is configured to be lower than the height of the top surface of the insulator 130. Therefore, adjacent conductors 120 can be reliably separated. Therefore, even when the maximum width of the opening 190 is increased, leakage current between the capacitive elements 100 can be suppressed.
  • the height of the top surface of the conductor 120 is preferably lower than the height of the top surface of the insulator 130 and is near the height of the top surface of the conductor 115 or coincides with the height of the top surface of the conductor 115. With such a configuration, a decrease in the capacitance of the capacitive element 100 can be suppressed.
  • FIGS. 8A to 8C show a structure in which the conductor 120 has a region in contact with the lower surface of the oxide semiconductor 230
  • the present invention is not limited to this.
  • a conductor may be provided between the conductor 120 and the oxide semiconductor 230.
  • FIGS. 9A to 9C show a structure in which a conductor 122 is provided between the conductor 120 and the oxide semiconductor 230. That is, the memory devices shown in FIGS. 9A to 9C mainly differ from the memory devices shown in FIGS. 8A to 8C in that they include the conductor 122.
  • a conductor 122 is provided on the conductor 120, and an oxide semiconductor 230 is provided on the conductor 122.
  • the conductor 122 has a region in contact with at least a portion of the upper surface of the conductor 120 and a region in contact with at least a portion of the lower surface of the oxide semiconductor 230. Further, as shown in FIGS. 9B and 9C, the conductor 122 is preferably provided so as to be embedded in the insulator 182. At this time, the top surface of the conductor 122 and the top surface of the insulator 182 have the same height.
  • the width of the conductor 122 in cross-sectional view is preferably smaller than the maximum width of the opening 190. With such a configuration, the distance between adjacent conductors 122 can be increased, and parasitic capacitance between adjacent conductors 122 can be suppressed.
  • the width of the conductor 122 in cross-sectional view is preferably the same as the maximum width of the opening 290 or larger than the maximum width of the opening 290.
  • the same mask is used in the anisotropic etching performed when forming the opening where the conductor 122 is provided and the opening 290. can be used. Thereby, the number of masks can be reduced, and the cost of the storage device can be reduced.
  • the width of the conductor 122 in a cross-sectional view is made larger than the maximum width of the opening 290, the alignment accuracy of the opening 290 is relaxed. Therefore, it is possible to reduce the difficulty level in manufacturing fine memory cells.
  • the conductor 122 has a region that is electrically connected to the capacitive element 100 and the transistor 200 and functions as a plug. Further, the conductor 122 has a region that functions as one of a source electrode and a drain electrode of the transistor 200.
  • the transistor 200 can be suitably formed on the capacitive element 100 even when the upper surface of the conductor 120 is not sufficiently flattened.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • the conductor 122 it is preferable to use a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, titanium nitride is in contact with the conductor 120 and the insulator 182, and tantalum nitride is in contact with the oxide semiconductor 230.
  • the conductor 122 may have a structure in which tungsten is laminated on titanium nitride, for example.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator applicable to the insulator 180 can be used as the insulator 182 .
  • each of the conductor 120 and the conductor 122 is shown as a single layer in FIGS. 9B and 9C, each of the conductor 120 and the conductor 122 may have a laminated structure.
  • the conductor 120 may have a two-layer stacked structure, and the conductor 122 may have a two-layer stacked structure.
  • each of the conductor 120 and the conductor 122 may have a structure in which tantalum nitride is laminated on titanium nitride, for example.
  • a structure in which tungsten is laminated on titanium nitride may be used.
  • a configuration may be adopted in which a conductor 121 is provided on a conductor 120.
  • the conductor 121 has a region in contact with a part of the upper surface of the conductor 120 and a region in contact with a part of the side surface of the insulator 130. Further, the conductor 121 has a region facing the conductor 115 with the insulator 130 in between. At this time, the conductor 120 and the conductor 121 function as one of the pair of electrodes of the capacitive element 100. That is, in the configuration shown in FIGS. 10A to 10C, the capacitive element 100 includes a conductor 121 in addition to the conductor 115, the insulator 130, and the conductor 120.
  • FIGS. 9A to 9C show a configuration in which the conductor 122 is provided between the conductor 120 and the oxide semiconductor 230, the present invention is not limited to this.
  • a conductor may be further provided between the conductor 122 and the oxide semiconductor 230.
  • FIGS. 11A to 11C show a structure in which a conductor 125 is provided between the conductor 122 and the oxide semiconductor 230.
  • the memory devices shown in FIGS. 11A to 11C mainly differ from the memory devices shown in FIGS. 9A to 9C in that they include the conductor 125.
  • the main difference from the memory device shown in FIGS. 8A to 8C is that it includes a conductor 122 and a conductor 125.
  • a conductor 125 is provided on the conductor 122, and an oxide semiconductor 230 is provided on the conductor 125.
  • the conductor 125 has a region in contact with the upper surface of the conductor 122 and a region in contact with at least a portion of the lower surface of the oxide semiconductor 230.
  • the conductor 122 has a region that is electrically connected to the capacitive element 100 and the transistor 200 and functions as a plug.
  • the conductor 125 has a region that functions as one of a source electrode and a drain electrode of the transistor 200. Materials applicable to the conductor 125 will be described later.
  • the width of the conductor 125 in cross-sectional view is preferably larger than the width of the conductor 122. Further, the width of the conductor 125 in cross-sectional view is preferably larger than the maximum width of the opening 290. With such a configuration, the alignment accuracy of the opening 290 is relaxed. Therefore, it is possible to reduce the difficulty level in manufacturing fine memory cells.
  • the conductor 120 is located inside the conductor 115 via the insulator 130, but the present invention is not limited to this.
  • the conductor 120 may be located outside the conductor 115 with the insulator 130 in between.
  • the insulator 130 is disposed on the outer side surface of the conductor 115 in addition to a region in contact with the inside of the recess of the conductor 115 and a region in contact with the upper surface of the conductor 115. It has an area located in .
  • the conductor 120 is provided so as to fill the recessed portion of the conductor 115 with the insulator 130 in between. Furthermore, the conductor 120 has a region that faces a part of the outer side surface of the conductor 115 with the insulator 130 in between.
  • the capacitance per unit area can be increased.
  • an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulators 130 and 180.
  • an insulator 182 may be provided on the conductor 120 and the insulator 130. Further, it is preferable that the insulator 182 be subjected to a planarization treatment so that the upper surface of the conductor 120 is exposed. By performing planarization treatment on the insulator 182, the transistor 200 can be suitably formed over the capacitor 100.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator applicable to the insulator 180 can be used as the insulator 182 .
  • the insulator A configuration may be adopted in which 180b is not provided.
  • the storage device shown in FIGS. 12C and 12D differs from the storage device shown in FIGS. 12A and 12B in that an insulator 180b is not provided. By not providing the insulator 180b, the manufacturing process of the memory device can be simplified.
  • the transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an upper surface of the conductor 120 exposed in an opening 290, and an insulator 280 in the opening 290. , the side surface of the conductor 240 in the opening 290, and the oxide semiconductor 230 provided in contact with at least a portion of the top surface of the conductor 240; and the insulator 250 provided in contact with the top surface of the oxide semiconductor 230. and a conductor 260 provided in contact with the upper surface of the insulator 250.
  • the bottom of the opening 290 is the top surface of the conductor 120
  • the sidewalls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.
  • the side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. At this time, the opening 290 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • the opening 290 is circular in plan view, but the present invention is not limited to this.
  • the opening 290 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • the maximum width of the opening 290 may be calculated as appropriate depending on the shape of the top of the opening 290.
  • the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.
  • the portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided to cover the oxide semiconductor 230, and a recessed portion of the insulator 250 that reflects the shape of the opening 290 is formed. A conductor 260 is provided so as to be buried therein.
  • FIG. 13A shows an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 1B.
  • FIG. 13B is a cross-sectional view of the portion shown by the dashed line B1-B2 in FIG. 13A, and is also a cross-sectional view in the XY plane including the conductor 240.
  • the oxide semiconductor 230 includes a region 230i, a region 230na, and a region 230nb.
  • the region 230na is a region of the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na functions as one of a source region and a drain region of the transistor 200.
  • the region 230nb is a region of the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb functions as the other of the source region and the drain region of the transistor 200.
  • the conductor 240 is in contact with the entire outer periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 can be formed over the entire outer periphery of a portion of the oxide semiconductor 230 that is formed in the same layer as the conductor 240.
  • At least a portion of the region 230i is located between the region 230na and the region 230nb of the oxide semiconductor 230. At least a portion of the region 230i functions as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or a region near the region.
  • a channel formation region of a transistor using an oxide semiconductor for a semiconductor layer preferably has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or a metal element than the source and drain regions.
  • hydrogen near oxygen vacancies may form defects in which hydrogen is present in oxygen vacancies (hereinafter sometimes referred to as V O H), and generate electrons that become carriers.
  • V O H oxygen vacancies
  • V OH are also preferably reduced.
  • the channel formation region of the transistor is a high resistance region with low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.
  • the source region and drain region of a transistor using an oxide semiconductor for the semiconductor layer have more oxygen vacancies, more V O H, or a higher concentration of impurities such as hydrogen, nitrogen, and metal elements than the channel formation region.
  • the insulator 280 of the oxide semiconductor 230 can be removed by heat treatment.
  • excess oxygen an insulator containing oxygen that is desorbed by heating
  • the insulator 280 of the oxide semiconductor 230 can be removed by heat treatment.
  • oxygen contained in the insulator 280 can be supplied to a region of the oxide semiconductor 230 in contact with the insulator 250 through the insulator 250, thereby reducing oxygen vacancies and V OH in the region. Therefore, as shown in FIGS. 13A and 13B, the region 230i, which has fewer oxygen vacancies than the region 230na and the region 230nb, is located near the insulator 280 and the insulator 250.
  • the oxide semiconductor 230 and the conductor 120 come into contact, a metal compound or an oxygen vacancy is formed, and the resistance of the region 230na of the oxide semiconductor 230 is reduced.
  • the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced.
  • the oxide semiconductor 230 and the conductor 240 are in contact with each other, the resistance of the region 230nb of the oxide semiconductor 230 is reduced. Therefore, contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the ranges of the region 230na and the region 230nb change depending on the degree of resistance reduction in the region 230na and the region 230nb and the amount of oxygen supplied from the insulator 280 via the insulator 250. For example, when the degree of resistance reduction in the region 230na and the region 230nb is large, or when the amount of oxygen supplied from the insulator 280 via the insulator 250 is small, the region 230na and the region 230nb reach the interface with the insulator 250. It may expand.
  • the channel length of the transistor 200 is the distance between the source and drain. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120.
  • FIG. 13A shows the channel length L of the transistor 200 with a dashed double-headed arrow.
  • the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact with each other and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact in a cross-sectional view. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the thickness of the insulator 280. Therefore, the channel length of the transistor 200 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell 150 can be improved, so that a memory device with high operating speed can be provided.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the oxide semiconductor 230 in the opening 290.
  • the area occupied by the transistor 200 can be reduced compared to a planar transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane. This allows the storage device to be highly integrated, thereby increasing the storage capacity per unit area.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically, similarly to FIG. 13B. Therefore, the side surface of the conductor 260 provided at the center faces the side surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. That is, in plan view, the entire circumference of the oxide semiconductor 230 becomes a channel formation region.
  • the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. In other words, the channel width of the transistor 200 can be said to be determined by the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular in plan view). In FIGS.
  • the maximum width Dt of the opening 290 is indicated by a two-dot chain double-headed arrow.
  • the channel width W of the transistor 200 is indicated by a dot-dash double-headed arrow.
  • the maximum width Dt of the opening 290 is set by the exposure limit of the photolithography. Further, the maximum width Dt of the opening 290 is set by the respective film thicknesses of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290.
  • the maximum width Dt of the opening 290 is, for example, 1 nm or more, 5 nm or more, or 10 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less. Note that when the opening 290 is circular in plan view, the maximum width Dt of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D ⁇ ".
  • the channel length L of the transistor 200 is preferably smaller than at least the channel width W of the transistor 200.
  • the channel length L of the transistor 200 according to one embodiment of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W of the transistor 200. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically. Accordingly, the distance between the conductor 260 and the oxide semiconductor 230 becomes approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.
  • the distance from the interface between the conductor 240 and the oxide semiconductor 230 in the opening 290 to the side end of the conductor 240 in the Y direction is preferably small.
  • the distance is preferably 1 nm or more, 1.5 nm or more, or 2 nm or more, and 20 nm or less, 10 nm or less, 5 nm or less, or 3 nm or less.
  • the opening 290 is provided so that the side wall of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this.
  • the sidewalls of opening 290 may be tapered.
  • FIGS. 14A and 14B has a configuration in which the side wall of the opening 290 is tapered. Note that FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 14A and 14B.
  • the angle between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, there is a region where the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as a taper angle) is less than 90 degrees.
  • the side surfaces of the structure and the substrate surface do not necessarily have to be completely flat, and may be substantially planar with minute curvatures or substantially planar with minute irregularities.
  • the shape of the opening 290 shown in FIGS. 14A and 14B is a truncated cone shape.
  • the opening 290 is circular in plan view, and trapezoidal in cross-section.
  • the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big.
  • the maximum diameter of the opening 290 may be calculated based on the upper base surface of the truncated cone shape.
  • the channel length can be set by the thickness of the insulator 280 and the angle ⁇ 1 between the side surface of the insulator 280 and the top surface of the conductor 120 in the opening 290. Further, the length of the outer periphery of the oxide semiconductor 230 may be determined, for example, at a region facing the conductor 240 or at a position half the thickness of the insulator 280. Note that the length of the circumference at any position of the opening 290 may be used as the channel width of the transistor 200, if necessary. For example, the length of the circumference at the bottom of the opening 290 may be set as the channel width, or the length of the circumference at the top of the opening 290 may be set as the channel width.
  • FIGS. 14A and 14B show a configuration in which the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 match
  • the present invention is not limited to this.
  • the side surface of the conductor 240 at the opening 290 and the side surface of the insulator 280 at the opening 290 may be discontinuous.
  • the slope of the side surface of the conductor 240 at the opening 290 and the slope of the side surface of the insulator 280 at the opening 290 may be different from each other.
  • the angle between the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 120 is preferably smaller than the angle ⁇ 1.
  • the bottom of the conductor 260 located in the opening 290 has a flat region.
  • the maximum width of the opening 290 the maximum diameter when the opening 290 is circular in plan view
  • the thickness of the insulator 280 corresponding to the depth of the opening 290
  • the thickness of the oxide semiconductor 230 may not have a flat area.
  • the bottom of the conductor 260 located in the opening 290 may have a needle-like shape.
  • FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 14C and 14D.
  • the term acicular refers to a shape that becomes thinner toward the tip (closer to the bottom of the conductor 260 located in the opening 290).
  • the needle-like tip may have an acute angle or may have a downwardly convex curved shape.
  • a shape having an acute angle at the tip may be referred to as a V-shape.
  • a region of the conductor 260 located in the opening 290 that faces the oxide semiconductor 230 with the insulator 250 in between functions as a gate electrode. Therefore, the conductor 260 that fills the opening 290 and has a needle-like bottom shape may be referred to as a needle-shaped gate. Further, as shown in FIGS. 14A and 14B, even if the conductor 260 has a flat bottom region, it may be called a needle-shaped gate.
  • the opening 190 is provided so that the side wall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this.
  • the sidewall of opening 190 may be tapered or reverse tapered.
  • the angle between the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • the bottom of the conductor 120 located in the opening 190 has a flat region.
  • the maximum width of the opening 190 the maximum diameter when the opening 190 is circular in plan view
  • the film thickness of the insulator 180 corresponding to the depth of the opening 190
  • the film of the conductor 115 the film of the conductor 115
  • the bottom of the conductor 120 located in the opening 190 may not have a flat area.
  • the bottom of the conductor 120 located in the opening 190 may have a needle-like shape.
  • FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 14C and 14D.
  • the angle ⁇ 1 and the angle ⁇ 2 match or approximately match.
  • the angle ⁇ 1 and the angle ⁇ 2 may be different depending on the materials used for the insulator 180 and the insulator 280, the method for forming the opening 190 and the opening 290, and the like.
  • the angle ⁇ 1 may be larger than the angle ⁇ 2, or may be smaller than the angle ⁇ 2.
  • one of the angle ⁇ 1 and the angle ⁇ 2 may be 90 degrees or a value close to 90 degrees.
  • one or both of the side walls of the opening 290 and the side wall of the opening 190 may have an inverted tapered shape.
  • the inverted tapered shape is a shape that has a side portion or an upper portion that protrudes from the bottom portion in a direction parallel to the substrate.
  • the shape of the opening 290 is a truncated cone shape.
  • the opening 290 is circular in plan view, and trapezoidal in cross-section.
  • the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big. With such a structure, the area in which the oxide semiconductor 230 and the conductor 120 are in contact can be increased.
  • FIGS. 1B and 1C a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240.
  • FIG. 1B shows a configuration in which the oxide semiconductor 230 is divided in the X direction
  • the present invention is not limited to this.
  • the oxide semiconductor 230 may be provided extending in the X direction.
  • the oxide semiconductor 230 is divided in the Y direction (see FIG. 15C).
  • FIG. 1C shows a configuration in which the side end portion of the oxide semiconductor 230 is located inside the side end portion of the conductor 240.
  • the present invention is not limited to this.
  • a structure may be adopted in which the side edges of the oxide semiconductor 230 and the side edges of the conductor 240 coincide in the Y direction.
  • a structure may be employed in which the side end portion of the oxide semiconductor 230 is located outside the side end portion of the conductor 240.
  • the band gap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more.
  • a metal oxide with a large band gap as the oxide semiconductor 230 off-state current of the transistor can be reduced.
  • a transistor with a small off-state current in a memory cell it is possible to retain stored contents for a long period of time. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced.
  • the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec.
  • the refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
  • oxide semiconductor 230 a metal oxide described in the section [Metal oxide] described below can be used in a single layer or in a stacked layer.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the element M it is preferable to use gallium.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS Inductively Coupled Plasma-Mass Spectrometry
  • ICP-AES Inductively Coupled Plasma-Atomi c Emission Spectrometry
  • analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • a sputtering method or an atomic layer deposition (ALD) method can be suitably used to form the metal oxide.
  • the composition of the formed metal oxide may be different from the composition of the sputtering target.
  • the content of zinc in the metal oxide after formation may be reduced to about 50% compared to the sputtering target.
  • the oxide semiconductor 230 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), and polycrystalline oxide semiconductors. Examples include semiconductors, single crystal oxide semiconductors, and the like.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • nc-OS nanocrystalline oxide semiconductor
  • polycrystalline oxide semiconductors examples include semiconductors, single crystal oxide semiconductors, and the like.
  • the CAAC-OS has a plurality of layered crystal regions, and the c-axis is oriented in the normal direction of the surface on which it is formed.
  • the oxide semiconductor 230 preferably has a layered crystal that is approximately parallel to the sidewall of the opening 290, particularly the sidewall of the insulator 280. With this structure, the layered crystal of the oxide semiconductor 230 is formed approximately parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (for example, oxygen vacancies).
  • heat treatment at a temperature that does not polycrystallize the metal oxide (e.g., 400°C or higher and 600°C or lower) allows CAAC-OS to have a more highly crystalline and dense structure. It can be done. In this way, by further increasing the density of the CAAC-OS, it is possible to further reduce the diffusion of impurities or oxygen in the CAAC-OS.
  • CAAC-OS it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Therefore, the metal oxide with CAAC-OS has stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.
  • the oxide semiconductor 230 Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode can be suppressed. As a result, even if heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so the transistor 200 is stable against high temperatures (so-called thermal budget) during the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 230 can be determined by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). ) can be analyzed. Alternatively, analysis may be performed by combining two or more of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 230 may have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure may be adopted in which a plurality of metal oxides selected from the above metal oxides are laminated as appropriate.
  • the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b over the oxide semiconductor 230a.
  • the conductivity of the material used for the oxide semiconductor 230a is preferably different from the conductivity of the material used for the oxide semiconductor 230b.
  • a material with higher conductivity than the oxide semiconductor 230b can be used for the oxide semiconductor 230a.
  • a material with high conductivity for the oxide semiconductor 230a that is in contact with the conductor 120 and the conductor 240 that function as a source electrode or a drain electrode the contact resistance between the oxide semiconductor 230 and the conductor 120 and the oxide semiconductor 230 can be reduced.
  • the contact resistance between the conductor 240 and the conductor 240 can be reduced, and a transistor with a large on-state current can be obtained.
  • the threshold voltage of the transistor shifts, and the drain current (hereinafter referred to as (also referred to as cut-off current) may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as normally off.
  • the oxide semiconductor 230 in a stacked structure and using a material with higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, it is possible to provide a storage device that has both low power consumption and high performance.
  • the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b.
  • the conductivity increases, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the transistor can have a large on-current.
  • the carrier concentration of the oxide semiconductor 230b By lowering the carrier concentration of the oxide semiconductor 230b, the conductivity is lowered, and a normally-off transistor can be obtained.
  • a material having higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a; however, one embodiment of the present invention is not limited to this.
  • a material having lower conductivity than the oxide semiconductor 230b may be used for the oxide semiconductor 230a.
  • the carrier concentration of the oxide semiconductor 230a can be lower than the carrier concentration of the oxide semiconductor 230b.
  • the band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the bandgap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the bandgap of the second metal oxide used for the oxide semiconductor 230b. Accordingly, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with high on-state current can be obtained. Further, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor 200 can be a normally-off transistor.
  • the band gap of the first metal oxide is smaller than the band gap of the second metal oxide
  • one embodiment of the present invention is not limited to this.
  • the first metal oxide may have a larger band gap than the second metal oxide.
  • the bandgap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the bandgap of the second metal oxide used for the oxide semiconductor 230b.
  • the composition of the first metal oxide is different from the composition of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxide
  • the first metal oxide used for the oxide semiconductor 230a can be an In-Zn oxide
  • the second metal oxide used for the oxide semiconductor 230b can be an In-M-Zn oxide
  • the first metal oxide can be an In-Zn oxide
  • the second metal oxide can be an In-Ga-Zn oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the content rates of elements other than element M may be different.
  • the film thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer constituting the oxide semiconductor 230 may be determined so that the thickness of the oxide semiconductor 230 falls within the above range.
  • the thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within the desired range.
  • the thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor is within a desired range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.
  • FIGS. 16A and 16B show a structure in which the oxide semiconductor 230 has a two-layer stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b, the present invention is not limited to this.
  • the oxide semiconductor 230 may have a stacked structure of three or more layers.
  • the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with little variation can be achieved.
  • the insulators described in the section [Insulator] described below can be used in a single layer or in a laminated manner.
  • the insulator 250 it is preferable to use an insulator that easily transmits oxygen. With such a configuration, oxygen contained in the insulator 280 can be supplied to the region 230i via the insulator 250. Further, the insulator 250 may be an insulator containing excess oxygen. With such a configuration, oxygen contained in the insulator 250 can be supplied to the region 230i.
  • silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250 a material with a high dielectric constant described in the section [Insulator] described below, a so-called high-k material, may be used.
  • hafnium oxide or aluminum oxide may be used.
  • the film thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less.
  • the insulator 250 only needs to have a region with the thickness described above at least in part.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • a portion of the insulator 250 is located outside the opening 290, that is, above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 cover the side edges of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. Further, it is preferable that the insulator 250 covers the side end portions of the conductor 240. This can prevent short-circuiting between the conductor 260 and the conductor 240.
  • the insulator 250 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure.
  • the insulator 250 may have a laminated structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. .
  • the insulator 250b it is preferable to use a material with a low dielectric constant described in the section [Insulator] described below.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250b contains at least oxygen and silicon. With such a configuration, the parasitic capacitance between the conductor 260 and the conductor 240 can be reduced. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.
  • the insulator 250a it is preferable to use an insulator having barrier properties against oxygen as described in the section [Insulator] described below.
  • the insulator 250a has a region in contact with the oxide semiconductor 230. Since the insulator 250a has barrier properties against oxygen, desorption of oxygen from the oxide semiconductor 230 can be suppressed when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. Thereby, the electrical characteristics of the transistor 200 can be improved and reliability can be improved.
  • aluminum oxide may be used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.
  • the insulator 250c is preferably an insulator having a barrier property against hydrogen as described in the [Insulator] section below. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has a high hydrogen barrier property and is therefore suitable as the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.
  • the insulator 250c may further have barrier properties against oxygen. Insulator 250c is provided between insulator 250b and conductor 260. Therefore, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Further, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.
  • an insulator may be provided between the insulator 250b and the insulator 250c.
  • the insulator it is preferable to use an insulator having a function of capturing or fixing hydrogen as described in the section [Insulator] described below.
  • the insulator hydrogen contained in the oxide semiconductor 230 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • hafnium oxide may be used as the insulator.
  • the insulator contains at least oxygen and hafnium.
  • the insulator may have an amorphous structure.
  • the film thicknesses of the insulators 250a to 250c are preferably thin, and preferably within the above-mentioned range.
  • the film thicknesses of the insulator 250a, the insulator 250b, the insulator having a function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • FIGS. 16A and 16B show a configuration in which the insulator 250 has a three-layer stacked structure of insulators 250a to 250c, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure of two layers, or four or more layers. At this time, each layer included in the insulator 250 may be appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.
  • the conductor 260 the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a highly conductive material such as tungsten can be used as the conductor 260.
  • the conductor 260 it is preferable to use a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • the conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride), a conductive material containing oxygen (for example, ruthenium oxide, etc.), and the like. Thereby, it is possible to suppress the conductivity of the conductor 260 from decreasing.
  • the conductor 260 may have a laminated structure.
  • the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a.
  • titanium nitride may be used as the conductor 260a
  • tungsten may be used as the conductor 260b.
  • FIGS. 16A and 16B show a configuration in which the conductor 260 has a two-layer stacked structure of a conductor 260a and a conductor 260b, the present invention is not limited to this.
  • the conductor 260 may have a laminated structure of three or more layers.
  • the conductor 260 is provided to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the recess may be located in the opening 290.
  • the recess may be filled with an inorganic insulating material or the like.
  • a portion of the conductor 260 is located outside the opening 290, that is, above the conductor 240 and the insulator 280.
  • the side end portion of the conductor 260 is preferably located inside the side end portion of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
  • the side end portion of the conductor 260 may coincide with the side end portion of the oxide semiconductor 230, or may be located outside the side end portion of the oxide semiconductor 230.
  • the conductor 120 may be provided as described in the section of [Capacitive element 100].
  • FIGS. 1B and 1C show a configuration in which the upper surface of the conductor 120 is flat
  • the present invention is not limited to this.
  • a configuration may be adopted in which a recessed portion overlapping the opening 290 is formed on the upper surface of the conductor 120.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a highly conductive material such as tungsten can be used as the conductor 240.
  • the conductor 240 is also preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion.
  • titanium nitride or tantalum nitride can be used. With such a structure, excessive oxidation of the conductor 240 by the oxide semiconductor 230 can be suppressed.
  • a structure in which tungsten is laminated on titanium nitride may be used. By layering tungsten in this way, the conductivity of the conductor 240 can be improved and it can function sufficiently as the wiring BL.
  • the conductor 240 has a structure in which a first conductor and a second conductor are laminated
  • the first conductor is formed using a conductive material with high conductivity
  • the second conductor is formed using a conductive material with high conductivity.
  • the conductor may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the second conductor of the conductor 240 in contact with the insulator 250, it is possible to suppress oxygen in the insulator 250 from diffusing into the first conductor of the conductor 240.
  • tungsten may be used as the first conductor of the conductor 240
  • indium tin oxide added with silicon may be used as the second conductor of the conductor 240.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant which is described in the section [Insulator] described later, can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • an insulator containing excess oxygen as the insulator 280 disposed near the channel formation region.
  • oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced. Thereby, the electrical characteristics of the transistor 200 can be stabilized and reliability can be improved.
  • an insulator having a function of capturing or fixing hydrogen which is described in the section [Insulator] described later, may be used. With such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • the insulator 280 magnesium oxide, aluminum oxide, or the like can be used.
  • the insulator 280 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 280 may have a laminated structure.
  • the insulator 280 may have a laminated structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b. .
  • the insulator 280b preferably has a region containing more oxygen than at least one of the insulators 280a and 280c. In particular, it is preferable that the insulator 280b has a region with a higher oxygen content than each of the insulators 280a and 280c. By increasing the oxygen content of the insulator 280b, an i-type region can be easily formed in a region of the oxide semiconductor 230 that is in contact with the insulator 280b and in the vicinity thereof.
  • the insulator 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, so that oxygen can be supplied to the oxide semiconductor 230.
  • oxygen vacancies and V O H in the oxide semiconductor 230 can be reduced, and good electrical characteristics can be achieved. A highly reliable transistor can be obtained.
  • oxygen can be supplied to the insulator 280b by performing heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen.
  • oxygen may be supplied by forming an oxide film on the upper surface of the insulator 280b in an oxygen atmosphere by a sputtering method. After that, the oxide film may be removed.
  • the insulator 280b is preferably formed by a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability.
  • oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability.
  • insulator having barrier properties against oxygen as described in the section [Insulator] described later for each of the insulator 280a and the insulator 280c.
  • oxygen contained in the insulator 280b can be prevented from diffusing to the substrate side via the insulator 280a and to the insulator 250 side via the insulator 280c due to heating.
  • oxygen contained in the insulator 280b can be confined. Thereby, oxygen can be effectively supplied to the oxide semiconductor 230.
  • the insulator 280c is applied to the region of the oxide semiconductor 230 that is in contact with the insulator 250 via the insulator 250.
  • the amount of oxygen supplied from the At this time as shown in FIGS. 17A and 17B, the region 230na and the region 230nb may extend toward the insulator 250.
  • the conductor 120 and the conductor 240 may be oxidized by the oxygen contained in the insulator 280b, resulting in increased resistance.
  • the insulator 280a between the insulator 280b and the conductor 120 it is possible to prevent the conductor 120 from being oxidized and increasing its resistance.
  • the insulator 280c between the insulator 280b and the conductor 240 it is possible to suppress the conductor 240 from being oxidized and increasing its resistance.
  • the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and oxygen vacancies in the oxide semiconductor 230 can be reduced.
  • the amount of oxygen supplied to the region of the oxide semiconductor 230 in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in the region in contact with the insulator 280b. Therefore, a region of the oxide semiconductor 230 in contact with the insulator 280a and a region in contact with the insulator 280c may have low resistance. That is, by adjusting the film thickness of the insulator 280a, the range of the region 230na that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb functioning as the other of the source region and the drain region can be controlled.
  • the source region and the drain region can be controlled by the film thicknesses of the insulator 280a and the insulator 280c, so the film thicknesses of the insulator 280a and the insulator 280c can be adjusted according to the characteristics required for the transistor 200. You can set it as appropriate.
  • the thickness of the insulator 280c and the thickness of the insulator 280a may be the same or approximately the same.
  • the thickness of the insulator 280a may be greater than the thickness of the insulator 280c.
  • FIGS. 17C and 17D show a configuration in which an insulator 280c is provided on a flattened insulator 280b
  • the present invention is not limited to this.
  • the insulator 280c may be formed without performing planarization treatment on the insulator 280b. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased. Further, the insulator 280a, the insulator 280b, and the insulator 280c can be continuously formed without being exposed to the atmospheric environment.
  • the film By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to prevent impurities or moisture from adhering to the insulators 280a to 280c.
  • the vicinity of the interface between the insulator 280b and the insulator 280c can be kept clean.
  • an insulator having barrier properties against hydrogen as described in the section [Insulator] described later for each of the insulator 280a and the insulator 280c.
  • hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 280a or the insulator 280c.
  • a silicon nitride film and a silicon nitride oxide film are suitable for the insulator 280a and the insulator 280c because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. It can be used for.
  • the insulator 280a and the insulator 280c may be made of the same material or different materials.
  • the insulator 280a it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later.
  • a structure suppresses hydrogen from diffusing into the oxide semiconductor 230 from below the insulator 280a, and further captures or fixes hydrogen in the oxide semiconductor 230 to reduce the hydrogen concentration in the oxide semiconductor 230. Can be reduced. Further, it is possible to suppress hydrogen from diffusing into the insulator 130 from above the insulator 280a, and further capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130.
  • the insulator 280a magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 280a.
  • the film thickness of the insulator 280a is preferably smaller than the film thickness of the insulator 280b. Further, the thickness of the insulator 280c is preferably smaller than the thickness of the insulator 280b.
  • the thickness of the insulator 280a and the insulator 280c is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and even more preferably 3 nm or more and 5 nm or less.
  • the thickness of the insulator 280b is preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 7 nm or more and 15 nm or less.
  • each of the insulator 280a and the insulator 280c includes at least silicon and nitrogen.
  • the insulator 280b includes at least silicon and oxygen.
  • FIGS. 17A and 17B show a structure in which the insulator 280 has a three-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulator 280 may have a laminated structure of two layers or four or more layers.
  • the insulator 283 it is preferable to use an insulator that has barrier properties against hydrogen and is described in the section [Insulator] described below. Thereby, hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 250.
  • a silicon nitride film and a silicon nitride oxide film are suitable for use as the insulator 283 because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. can.
  • the insulator 283 it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With this structure, hydrogen is prevented from diffusing into the oxide semiconductor 230 from above the insulator 283, and hydrogen in the oxide semiconductor 230 is captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230. Can be reduced.
  • magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 283.
  • FIGS. 1B and 1C show a structure in which the upper surface of the conductor 120 and the lower surface of the oxide semiconductor 230 are in contact with each other, the present invention is not limited to this.
  • a conductor may be provided between the conductor 120 and the oxide semiconductor 230.
  • a structure may be adopted in which a conductor 125 is provided between the conductor 120 and the oxide semiconductor 230.
  • the conductor 125 it is preferable to use an oxygen-containing conductive material described in the "Conductor" section below.
  • a conductive material containing oxygen as the conductor 125, conductivity can be maintained even if the conductor 125 absorbs oxygen. Furthermore, diffusion of oxygen in the oxide semiconductor 230 into the conductor 120 can be suppressed.
  • the conductor 125 for example, indium tin oxide, silicon-added indium tin oxide, indium zinc oxide, or the like can be used in a single layer or in a stacked layer.
  • FIGS. 18A and 18B a structure may be adopted in which the side end of the insulator 130 and the side end of the conductor 115 coincide.
  • the insulator 130 and the conductor 115 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.
  • FIGS. 1B and 1C show a configuration in which the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the upper surface of the conductor 240. Note that the present invention is not limited to this.
  • the oxide semiconductor 230 may have a region in contact with the conductor 240 in the opening 290.
  • the height of the top surface of the oxide semiconductor 230 matches the height of the top surface of the conductor 240.
  • the distance from the interface between the conductor 240 and the oxide semiconductor 230 in the opening 290 to the side end of the conductor 240 in the Y direction can be reduced. Therefore, the width of the conductor 240 in the Y direction can be reduced, and the intervals at which the conductors 240 are arranged can be reduced. Therefore, the storage device can be miniaturized or highly integrated.
  • FIG. 19A is a plan view of the storage device shown in FIGS. 19B and 19C.
  • FIGS. 1B and 1C show a configuration in which the conductor 240 is provided on an insulator 280. Further, a configuration is shown in which a region of the insulator 250 that does not overlap with the conductor 240 has a region in contact with the upper surface of the insulator 280. Note that the present invention is not limited to this.
  • an insulator 281 may be provided on an insulator 280, and a conductor 240 may be provided so as to be embedded in the insulator 281.
  • the height of the top surface of the conductor 240 preferably matches the height of the top surface of the insulator 281. With this configuration, it is possible to increase the physical distance from the conductor 260 to the conductor 240 (particularly the side ends of the conductor 240), and to prevent short circuits between the conductor 260 and the conductor 240.
  • FIG. 20A is a plan view of the storage device shown in FIGS. 20B and 20C.
  • the insulator 281 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form.
  • the conductor 260 is extended to function as a wiring. Further, the conductor 260 is shared by a plurality of transistors. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor that functions as a wiring is provided on the conductor 260.
  • a conductor 265 may be provided on the conductor 260.
  • one conductor 260 is provided for each transistor. Note that it is not necessarily necessary to provide one conductor 260 for each transistor.
  • the conductor 260 may be shared by a plurality of transistors.
  • the conductor 260 is preferably provided so as to be embedded in the insulator 287. At this time, it is preferable that the height of the top surface of the conductor 260 and the height of the top surface of the insulator 287 match. With such a configuration, short circuit between the conductor 260 and the conductor 240 can be prevented.
  • the conductor 265 functions as a wiring WL that is electrically connected to the gate of the transistor 200.
  • the conductor described in the above-mentioned [Conductor] item can be used in a single layer or a laminated form.
  • a highly conductive material such as tungsten can be used as the conductor 265.
  • the conductor 265 is preferably provided so as to be embedded in the insulator 289. At this time, it is preferable that the height of the top surface of the conductor 265 and the height of the top surface of the insulator 289 match.
  • the insulator 287 and the insulator 289 function as interlayer films, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant which is described in the above-mentioned [Insulator] section, can be used in a single layer or in a stacked layer.
  • the side end of the conductor 265 coincides with the side end of the conductor 260, but the present invention is not limited thereto.
  • the side end portion of the conductor 265 may be located outside the side end portion of the conductor 260, or may be located inside the side end portion of the conductor 260.
  • an insulating substrate for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the semiconductor substrate described above such as an SOI (Silicon On Insulator) substrate.
  • the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • substrates containing metal nitrides, substrates containing metal oxides, and the like there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided.
  • these substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.
  • high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, and oxides containing aluminum and hafnium.
  • examples include nitride, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, and nitride containing silicon and hafnium.
  • materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and resins such as acrylic. Can be mentioned.
  • inorganic insulating materials having a low dielectric constant include, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. Further, for example, silicon oxide having pores may be used. Note that these silicon oxides may contain nitrogen.
  • insulators having the function of suppressing permeation of impurities and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, Insulators including neodymium, hafnium, or tantalum can be used in single layers or in stacks.
  • insulators that have the function of suppressing the permeation of impurities and oxygen include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc.
  • Metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • an insulator such as a gate insulator that is in contact with the semiconductor layer or an insulator provided near the semiconductor layer is an insulator that has a region containing excess oxygen.
  • oxygen vacancies in the semiconductor layer can be reduced by providing a structure in which an insulator having a region containing excess oxygen is in contact with the semiconductor layer or in the vicinity of the semiconductor layer.
  • insulators that can easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • Insulators with barrier properties against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, and indium gallium. Examples include zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulators having barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to be an insulator that has a barrier property against one or both of oxygen and hydrogen.
  • examples of the insulator having the function of capturing or fixing hydrogen include an oxide containing magnesium, or an oxide containing one or both of aluminum and hafnium. Moreover, it is more preferable that these oxides have an amorphous structure. In an oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may capture or fix hydrogen. Note that these metal oxides preferably have an amorphous structure, but a crystalline region may be formed in part.
  • barrier insulating film refers to an insulating film having barrier properties.
  • barrier property refers to the property that the corresponding substance is difficult to diffuse (also referred to as the property that the corresponding substance is difficult to permeate, the property that the corresponding substance has low permeability, or the ability to suppress the diffusion of the corresponding substance). do.
  • the function of capturing or fixing a corresponding substance can be referred to as barrier property.
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities described as corresponding substances refer to impurities in the channel forming region or semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, oxidation Refers to at least one of nitrogen molecules ( N2O , NO, NO2, etc.), copper atoms, etc.
  • oxygen refers to at least one of, for example, an oxygen atom or an oxygen molecule.
  • the barrier property against oxygen refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is difficult to diffuse.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the following, an alloy containing the above-mentioned metal elements as a component, an alloy containing a combination of the above-mentioned metal elements, or the like. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used.
  • tantalum nitride titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. It is preferable. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • nitrides containing tantalum nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, etc.
  • a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen is preferable.
  • conductive materials containing oxygen indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium Examples include zinc oxide and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.
  • conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a plurality of conductive layers formed of the above materials may be stacked and used.
  • a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor that functions as the gate electrode has a stacked structure that combines a material containing the aforementioned metal element and a conductive material containing oxygen. It is preferable. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as the gate electrode.
  • a conductive material containing the aforementioned metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • one or more of the added indium tin oxides may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include atomic vacancies, point defects such as foreign atoms, line defects such as dislocations, planar defects such as crystal grain boundaries, and volume defects such as voids.
  • factors for the generation of lattice defects include a deviation in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms), impurities, and the like.
  • the metal oxide used for the semiconductor layer of the transistor preferably has few lattice defects.
  • the channel forming region in the metal oxide has a reduced carrier concentration and is made i-type (intrinsic) or substantially i-type.
  • the type of lattice defects that are likely to exist in a metal oxide and the amount of lattice defects that exist vary depending on the structure of the metal oxide, the method of forming a metal oxide film, etc.
  • the structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure).
  • non-single crystal structures include a CAAC structure, a polycrystalline structure, a nc structure, an amorphous-like (a-like) structure, and an amorphous structure.
  • the a-like structure has a structure between an nc structure and an amorphous structure. Note that the classification of crystal structures will be described later.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have cavities or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Further, a metal oxide having an a-like structure has a higher hydrogen concentration than a metal oxide having an nc structure and a metal oxide having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a highly crystalline metal oxide for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using the metal oxide in a transistor, a transistor with good electrical characteristics can be realized. Furthermore, a highly reliable transistor can be realized.
  • a metal oxide that increases the on-state current of the transistor for the channel formation region of the transistor.
  • the crystal has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). At this time, the c-axis of the crystal is oriented in the direction in which a plurality of layers are stacked.
  • metal oxides having such crystals include single-crystal oxide semiconductors, CAAC-OS, and the like.
  • the c-axis of the crystal is oriented in the normal direction to the surface on which the metal oxide is formed or the film surface.
  • the plurality of layers are arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. That is, the multiple layers extend in the channel length direction.
  • the three-layered crystal structure described above has the following structure.
  • the first layer has an octahedral atomic coordination structure of oxygen in which the metal of the first layer is located at the center.
  • the second layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the second layer exists at the center.
  • the third layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the third layer exists at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first to third layers is preferably composed of one metal element or a plurality of metal elements having the same valence and oxygen.
  • the valence of one or more metal elements forming the first layer is the same as the valence of one or more metal elements forming the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of one or more metal elements forming the first layer is different from the valence of one or more metal elements forming the third layer.
  • the crystallinity of the metal oxide can be improved and the carrier mobility of the metal oxide can be increased. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable.
  • the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements” described in this specification and the like may include semimetal elements.
  • Examples of the metal oxide semiconductor of one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), Indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (also written as Al-Zn oxide, AZO), indium aluminum zinc oxide (also written as In-Al-Zn oxide, IAZO), indium tin zinc oxide (In -Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In -Ga-Sn-Zn oxide (also referred to as IGZTO), indium gallium aluminum zinc oxide (In-G
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements.
  • the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large periodic number in the periodic table of elements, it may be possible to increase the field effect mobility of the transistor. Examples of metal elements with large period numbers in the periodic table of elements include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal element examples include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more types of nonmetallic elements.
  • the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. . Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • an In-Ga-Zn oxide may be used as an example of the metal oxide.
  • the method for forming a metal oxide film of one embodiment of the present invention uses an ALD method, it is easy to form a metal oxide having the above-described layered crystal structure.
  • Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.
  • a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy
  • PEALD plasma enhanced ALD
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with high aspect ratios, to form films with few defects such as pinholes, and to improve coverage. It has advantages such as being able to form an excellent film and being able to form a film at a low temperature. Further, the PEALD method may be preferable because it can form a film at a lower temperature by using plasma. Note that some precursors used in the ALD method include elements such as carbon or chlorine. For this reason, a film formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that these elements can be quantified using XPS or secondary ion mass spectrometry (SIMS).
  • the method for forming a metal oxide film of one embodiment of the present invention uses an ALD method
  • one or both of the conditions of high substrate temperature during film formation and the implementation of impurity removal treatment may be applied.
  • the amount of carbon and chlorine contained in the film may be smaller than when ALD is used without applying these.
  • the ALD method is a film-forming method in which a film is formed by a reaction on the surface of an object, unlike a film-forming method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as sputtering or CVD, which have a high film formation rate.
  • a method may be used in which a first metal oxide is deposited using a sputtering method, and a second metal oxide is deposited on the first metal oxide using an ALD method.
  • the second metal oxide may grow crystals using the crystal part as a nucleus.
  • the composition of the resulting film can be controlled by the amount of raw material gas introduced.
  • the amount of raw material gas introduced it is possible to form a film of any composition by adjusting the amount of raw material gas introduced, the number of times it is introduced (also called the number of pulses), the time required for one pulse (also called pulse time), etc. can.
  • the ALD method by changing the raw material gas during film formation, it is possible to form a film whose composition changes continuously.
  • the time required for film formation can be shortened by eliminating the time required for transport and pressure adjustment. can. Therefore, it may be possible to increase the productivity of the storage device.
  • a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
  • the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • Si transistors As transistors become smaller, a short channel effect (also referred to as SCE) occurs. Therefore, it is difficult to miniaturize Si transistors.
  • SCE short channel effect
  • silicon has a small band gap.
  • an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed. In other words, an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • the characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
  • the OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
  • the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less.
  • the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n ⁇ /n + storage type non-junction transistor structure.
  • the OS transistor By making the OS transistor have the above structure, it can have good electrical characteristics even if the memory device is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
  • the high frequency characteristics of the transistor can be improved.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
  • OS transistors have superior effects compared to Si transistors, such as lower off-state current and the ability to manufacture transistors with shorter channel lengths.
  • the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms /cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 3 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 1 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, still more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , even more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 230 can be referred to as a semiconductor layer including a channel formation region of a transistor.
  • Semiconductor materials that can be used for the semiconductor layer are not limited to the metal oxides mentioned above.
  • a semiconductor material having a band gap semiconductor material that is not a zero-gap semiconductor may be used as the semiconductor layer.
  • a layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds that are weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of single element semiconductors that can be used as semiconductor materials include silicon and germanium.
  • Examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • Boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • Boron arsenide that can be used in the semiconductor layer preferably contains crystals with a cubic crystal structure.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • a chalcogenide is a compound containing chalcogen.
  • chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • examples of the chalcogenide include transition metal chalcogenides, group 13 chalcogenides, and the like.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as a semiconductor layer include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), Tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically Examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • Example 1 of manufacturing method of storage device a method for manufacturing the storage device shown in FIGS. 1A to 1C, which is one embodiment of the present invention, will be described with reference to FIGS. 22A to 32C.
  • a in each figure indicates a plan view.
  • B in each figure is a sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure.
  • C in each figure is a sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure.
  • some elements are omitted for clarity of the figure.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is used by sputtering method, CVD method, molecular beam epitaxy (MBE).
  • the film can be formed using an appropriate method such as epitaxy method, pulsed laser deposition (PLD) method, or ALD method.
  • sputtering methods include an RF sputtering method that uses a high frequency power source as a sputtering power source, a DC sputtering method that uses a DC power source, and a pulsed DC sputtering method that changes the voltage applied to the electrode in a pulsed manner.
  • the RF sputtering method is mainly used when forming an insulating film
  • the DC sputtering method is mainly used when forming a metal conductive film.
  • the pulsed DC sputtering method is mainly used when forming a film of a compound such as an oxide, nitride, or carbide by a reactive sputtering method.
  • the CVD method can be classified into a plasma CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD (Photo CVD) method that uses light, etc. Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.
  • PECVD plasma CVD
  • TCVD thermal CVD
  • Photo CVD Photo CVD
  • MCVD metal CVD
  • MOCVD metal organic CVD
  • the plasma CVD method can obtain high-quality films at relatively low temperatures. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the memory device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of memory devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.
  • the ALD method a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, a PEALD method in which a plasma-excited reactant is used, etc. can be used.
  • the CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.
  • a film of any composition can be formed by changing the flow rate ratio of source gases.
  • the flow rate ratio of source gases by changing the flow rate ratio of source gases during film formation, it is possible to form a film whose composition changes continuously.
  • the time required for film formation is reduced because it does not require time for transport or pressure adjustment. can do. Therefore, it may be possible to increase the productivity of the storage device.
  • a film of any composition can be formed by simultaneously introducing a plurality of different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • a substrate (not shown) is prepared, and an insulator 140 is formed on the substrate (see FIGS. 22A to 22C).
  • an insulator 140 any of the above-mentioned insulating materials may be used as appropriate.
  • the insulator 140 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductor 110 is formed on the insulator 140.
  • the above-mentioned conductive material may be used as appropriate.
  • the conductor 110 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a stacked film of tungsten and titanium nitride may be formed in this order using a CVD method.
  • the conductor 110 may be processed into a shape that extends in the X direction or the Y direction.
  • the conductor 110 may be processed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication. By performing this processing, the side end portions of the conductor 110 are covered with an insulator 130 that will be formed later.
  • a resist mask is formed by removing or leaving the exposed area using a developer.
  • a conductor, semiconductor, insulator, or the like can be processed into a desired shape.
  • a resist mask may be formed by exposing a resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by performing dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as the dry etching device.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high frequency voltage is applied to one electrode of the parallel plate electrodes.
  • a configuration may be adopted in which a plurality of different high frequency voltages are applied to one electrode of a parallel plate type electrode.
  • a configuration may be adopted in which a high frequency voltage of the same frequency is applied to each of the parallel plate type electrodes.
  • a configuration may be adopted in which high frequency voltages having different frequencies are applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • the dry etching device having a high-density plasma source for example, an inductively coupled plasma (ICP) etching device or the like can be used.
  • ICP inductively coupled plasma
  • an insulator 180 is formed on the conductor 110 (see FIGS. 22A to 22C).
  • the insulating material described above may be used as appropriate for the insulator 180.
  • the insulator 180 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 180 is preferably subjected to CMP (Chemical Mechanical Polishing) treatment after film formation to flatten the upper surface. Note that there are cases where it is not necessary to perform CMP processing. At this time, the upper surface of the insulator 180 has an upwardly convex curved shape. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased.
  • CMP Chemical Mechanical Polishing
  • the film thickness of the insulator 180 corresponds to the capacitance of the capacitive element 100
  • the film thickness of the insulator 180 may be appropriately set according to the design value of the capacitance of the capacitive element 100.
  • the hydrogen concentration in the insulator 180 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas.
  • the opening 190 may be formed using a lithography method.
  • the shape of the opening 190 is circular in plan view, it is not limited to this.
  • the shape of the opening 190 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners when viewed from above.
  • the side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Note that the side wall of the opening 190 may have a tapered shape. By tapering the side wall of the opening 190, the coverage of a conductive film, which will be described later as a conductor 115, can be improved, and defects such as holes can be reduced.
  • the maximum width (maximum diameter when the opening 190 is circular in plan view) of the opening 190 is minute.
  • the maximum width of the opening 190 is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, and preferably 5 nm or more, or 10 nm or more.
  • the opening 190 has a large aspect ratio, it is preferable to process a part of the insulator 180 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing.
  • the maximum width of opening 190 is larger than the maximum width of opening 290, so when forming opening 190 and opening 290 using anisotropic etching, it is not possible to use the same mask. Have difficulty. Therefore, the opening 190 may be formed by processing a part of the insulator 180 using anisotropic etching to form an opening, and then widening the width of the opening using isotropic etching. good. When forming the opening 190 through such a process, the same mask can be used in anisotropic etching performed when forming the opening 190 and the opening 290. Thereby, the number of masks can be reduced, and the cost of the storage device can be reduced.
  • a conductive film that will become the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180.
  • a conductor that can be used as the conductor 115 described above may be used as appropriate.
  • the conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductive film is preferably formed in contact with the bottom and sidewalls of the opening 190 having a large aspect ratio.
  • a film forming method with good coverage it is preferable to use a CVD method, an ALD method, or the like.
  • a titanium nitride film may be formed as the conductive film using a CVD method.
  • the conductive film that will become the conductor 115 is processed using lithography to form the conductor 115 (see Figures 24A to 24C). As a result, a part of the conductor 115 is formed in the opening 190. The conductor 115 also contacts a part of the side and top surface of the insulator 180.
  • the insulator 130 is formed on the conductor 115 and the insulator 180 (see FIGS. 25A to 25C).
  • the above-mentioned high-k material or a material capable of having ferroelectricity may be used as appropriate.
  • the insulator 130 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a laminated film of zirconium oxide, aluminum oxide, and zirconium oxide may be formed in this order using an ALD method.
  • a conductive film 120A is formed on the insulator 130 (see FIGS. 25A to 25C).
  • the conductive material described above may be used for the conductive film 120A.
  • the conductive film 120A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a stacked film of titanium nitride and tantalum nitride may be formed in this order using a CVD method.
  • a stacked film in which titanium nitride and tungsten are deposited in this order may be formed using a CVD method.
  • the upper surface of the conductive film 120A may be planarized using a CMP method or the like. By performing the planarization treatment on the conductive film 120A, the upper surface of the conductor 120 formed by processing the conductive film 120A is flattened, and the transistor 200 can be suitably formed over the capacitor 100.
  • the conductive film 120A is processed to form the conductor 120 (see FIGS. 26A to 26C).
  • the conductor 120 may be formed using a lithography method.
  • a dry etching method or a wet etching method can be used to process the conductive film 120A. Processing by dry etching is suitable for microfabrication.
  • the capacitive element 100 including the conductor 115, the insulator 130, and the conductor 120 can be formed.
  • an insulator 280 is formed on the insulator 130 and the conductor 120 (see FIGS. 27A to 27C).
  • the insulating material described above may be used as appropriate for the insulator 280.
  • the insulator 280 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 280 is preferably subjected to CMP treatment after film formation to flatten the upper surface. By performing planarization treatment on the insulator 280, the conductor 240 functioning as a wiring can be suitably formed.
  • CMP treatment may be performed until the insulator 280 is reached.
  • the surface of the insulator 280 can be flattened and smoothed.
  • the upper surface of the insulator 280 has an upwardly convex curved shape. By not performing the planarization process, it is possible to reduce manufacturing costs and increase production yields.
  • the film thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200
  • the film thickness of the insulator 280 may be appropriately set according to the design value of the channel length of the transistor 200. .
  • the insulator 280 by forming the insulator 280 by a sputtering method in an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. By forming the insulator 280 in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced.
  • a conductive film 240A is formed on the insulator 280 (see FIGS. 27A to 27C).
  • the conductive material described above may be used as appropriate for the conductive film 240A.
  • the conductive film 240A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the opening 290 is preferably formed to have a region overlapping with the opening 190.
  • the opening 290 may be formed using a lithography method. Note that although the shape of the opening 290 shown in FIG. 28A is circular in plan view, the shape is not limited to this.
  • the shape of the opening 290 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners in a plan view.
  • the side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Further, the side wall of the opening 290 may have a tapered shape. By tapering the sidewall of the opening 290, coverage of an oxide semiconductor film or the like that becomes the oxide semiconductor 230 (described later) can be improved, and defects such as holes can be reduced.
  • the maximum width (maximum diameter when the opening 290 is circular in plan view) of the opening 290 is minute.
  • the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the opening 290 has a large aspect ratio, it is preferable to process a part of the conductive film 240A and a part of the insulator 280 using anisotropic etching. In particular, processing by dry etching is preferred because it is suitable for fine processing. Further, the processing may be performed under different conditions. Note that depending on the conditions for processing a portion of the conductive film 240A and a portion of the insulator 280, as described above, the slope of the side surface of the conductor 240 at the opening 290 and the slope of the insulator 280 at the opening 290 may vary. The slopes of the sides may differ from each other.
  • the heat treatment may be performed at 250° C. to 650° C., preferably 300° C. to 500° C., more preferably 320° C. to 450° C.
  • the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the oxygen gas may be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.
  • an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductive film 240A.
  • a metal oxide that can be used for the oxide semiconductor 230 described above may be used as appropriate.
  • the oxide semiconductor film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the oxide semiconductor film is preferably formed in contact with the bottom and sidewalls of the opening 290 having a large aspect ratio.
  • an In-Ga-Zn oxide may be formed using an ALD method.
  • precursors containing indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)indium, cyclopentadienylindium, indium (III) acetylacetonate, ( Organic precursors such as 3-(dimethylamino)propyl)dimethylindium can be used.
  • trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)gallium organic precursors such as dimethylchlorogallium, diethylchlorogallium, dimethylgallium isopropoxide, etc. can be used.
  • organic precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedioic acid)zinc, zinc acetate, etc. can be used.
  • the precursor used for the film formation has a high decomposition temperature.
  • the decomposition temperature of the precursor is preferably 200°C or more and 700°C or less, more preferably 300°C or more and 600°C or less.
  • an inorganic precursor that does not contain hydrocarbons. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if film formation is performed while heating the substrate as described above, the precursors are difficult to decompose.
  • halogen-based indium compounds such as indium trichloride, indium tribromide, and indium triiodide can be used.
  • inorganic precursor containing gallium halogen-based gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide can be used.
  • inorganic precursor containing zinc halogen-based zinc compounds such as zinc dichloride, zinc dibromide, and zinc diiodide can be used.
  • precursors include one or both of carbon and chlorine in addition to metal elements.
  • a film formed using a precursor containing carbon may contain carbon.
  • a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.
  • Ozone, oxygen, water, etc. can be used as the oxidizing agent.
  • the oxide semiconductor film that becomes the oxide semiconductor 230 is not limited to the case where the CVD method or the ALD method is used.
  • a sputtering method may be used.
  • the deposition methods for each layer included in the oxide semiconductor 230 may be the same or different.
  • the lower layer of the oxide semiconductor film may be formed by a sputtering method
  • the upper layer of the oxide semiconductor film may be formed by an ALD method.
  • An oxide semiconductor film formed using a sputtering method tends to have crystallinity. Therefore, by providing an oxide semiconductor film having crystallinity as a lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved.
  • the oxide semiconductor film formed by the ALD method which has good coverage, can cover the overlapping portions. It can be closed with the upper layer of
  • the oxide semiconductor film serving as the oxide semiconductor 230 covers the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the side surface of the conductor 240 in the opening 290. Preferably, it is formed in contact with the upper surface.
  • the oxide semiconductor film in contact with the conductor 120 the conductor 120 functions as one of a source electrode and a drain electrode of the transistor 200.
  • the conductor 240 functions as the other of the source electrode and the drain electrode of the transistor 200.
  • the heat treatment may be performed at a temperature range in which the oxide semiconductor film does not become polycrystalline, and may be performed at a temperature of 250° C. or more and 650° C. or less, preferably 400° C. or more and 600° C. or less.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the oxygen gas content may be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the heat treatment is preferably performed while the insulator 280 containing excess oxygen is provided in contact with the oxide semiconductor film.
  • oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced.
  • an oxide semiconductor film is formed using an ALD method
  • impurities such as hydrogen or carbon contained in the oxide semiconductor film
  • carbon in the oxide semiconductor film can be released as CO 2 and CO
  • hydrogen in the oxide semiconductor film can be released as H 2 O.
  • metal atoms and oxygen atoms are rearranged, and crystallinity can be improved. Therefore, the oxide semiconductor 230 having a layered crystal structure with high crystallinity can be formed.
  • heat treatment was performed after forming the oxide semiconductor film, but the present invention is not limited to this. A configuration may also be adopted in which heat treatment is performed in a later step.
  • microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated.
  • oxygen that acts on the oxide semiconductor film has various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also referred to as O radicals; atoms, molecules, or ions with unpaired electrons). Note that the oxygen that acts on the oxide semiconductor film may be any one or more of the forms described above, and oxygen radicals are particularly preferable.
  • heating the substrate when performing the microwave treatment in the above-mentioned oxygen-containing atmosphere is preferable because the impurity concentration in the oxide semiconductor film can be further reduced.
  • the temperature at which the above-mentioned substrate is heated may be 100°C or more and 650°C or less, preferably 200°C or more and 600°C or less, and more preferably 300°C or more and 450°C or less.
  • the carbon concentration in the metal oxide obtained by SIMS can be reduced to less than 1 ⁇ 10 20 atoms/cm 3 , preferably 1 ⁇ 10 19 It can be less than 1 ⁇ 10 18 atoms/cm 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • microwave treatment may be performed on an insulating film, more specifically a silicon oxide film, located near an oxide semiconductor in an atmosphere containing oxygen.
  • microwave treatment may be performed after the insulator 250 is formed.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (see FIGS. 29A to 29C). As a result, part of the oxide semiconductor 230 is formed in the opening 290. Further, the oxide semiconductor 230 is in contact with a part of the side surface and the top surface of the conductor 240. Therefore, the area of the region where the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
  • the conductive film 240A is processed to form the conductor 240 (see FIGS. 30A to 30C).
  • the conductor 240 may be formed using a lithography method.
  • a dry etching method or a wet etching method can be used to process the conductive film 240A. Processing by dry etching is suitable for microfabrication.
  • the method is the same as described above until the conductive film 240A shown in FIGS. 27A to 27C is formed.
  • the conductive film 240A is processed to form the conductor 240.
  • the above description can be referred to.
  • a part of the conductor 240 and a part of the insulator 280 are processed to form an opening 290 that reaches the conductor 120.
  • the above description can be referred to.
  • heat treatment may be performed.
  • the conditions of the heat treatment, etc. the above explanation can be referred to.
  • an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductor 240. At this time, the oxide semiconductor film has a region in contact with the upper surface of the insulator 280.
  • the above description can be referred to.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (see FIGS. 30A to 30C).
  • an insulator 250 is formed over the oxide semiconductor 230, the conductor 240, and the insulator 280 (see FIGS. 31A to 31C).
  • the insulator 250 any of the above-mentioned insulating materials may be used as appropriate.
  • the insulator 250 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290 with a large aspect ratio.
  • the insulator 250 it is preferable to use a film forming method that provides good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • silicon oxide may be formed as the insulator 250 using an ALD method.
  • the film formation of the insulator 250 is not limited to the case where the CVD method or the ALD method is used.
  • a sputtering method may be used.
  • the side edges of the oxide semiconductor 230 are covered with the insulator 250. Therefore, short circuit between the oxide semiconductor 230 and the conductor 260 can be prevented. Furthermore, with the above configuration, the side end portions of the conductor 240 are covered with the insulator 250. Therefore, short circuit between the conductor 240 and the conductor 260 can be prevented.
  • a conductive film 260A is formed to fill the recesses of the insulator 250 (see FIGS. 31A to 31C).
  • the conductive material described above may be used as appropriate for the conductive film 260A.
  • the conductive film 260A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductive film 260A is preferably formed in contact with the insulator 250 provided in the opening 290 having a large aspect ratio.
  • the conductive film 260A it is preferable to use a film forming method that provides good coverage or embeddability, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a CVD method an ALD method
  • titanium nitride may be formed as the conductive film 260A using a CVD method or an ALD method.
  • the conductive film 260A is formed using the CVD method, the average surface roughness of the upper surface of the conductive film 260A may become large. In this case, it is preferable to planarize the conductive film 260A using a CMP method. At this time, before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed over the conductive film 260A, and the CMP treatment may be performed until the silicon oxide film or silicon oxynitride film is removed.
  • the conductive film 260A is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductive film 260A.
  • the recess may be filled with an inorganic insulating material or the like.
  • the conductor 260 is processed to form the conductor 260 (see FIGS. 32A to 32C).
  • the conductor 260 may be formed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication.
  • the side end portion of the conductor 260 is located inside the side end portion of the oxide semiconductor 230 in plan view. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
  • the transistor 200 including the conductor 120, the conductor 240, the oxide semiconductor 230, the insulator 250, and the conductor 260 can be formed.
  • an insulator 283 is formed to cover the conductor 260 and the insulator 250.
  • the above-mentioned insulating material may be used as appropriate.
  • the insulator 283 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a memory device having the memory cell 150 shown in FIGS. 1A to 1D can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 illustrated in FIGS. 1A to 1D can be manufactured.
  • Example 2 of manufacturing method of storage device> Next, a method for manufacturing a memory device shown in FIGS. 10A to 10C, which is one embodiment of the present invention, will be described. Note that for the steps up to forming the insulator 180, the description in ⁇ Example 1 of manufacturing method of memory device> described above can be referred to.
  • a part of the insulator 180 is processed to form an opening 190 that reaches the conductor 120 (see FIGS. 33A to 33C).
  • the above description can be referred to.
  • a conductive film that will become the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180.
  • the above description can be referred to.
  • CMP treatment is performed. By performing the CMP treatment, the conductor 115 can be formed (see FIGS. 34A to 34C). At this time, the top surface of the conductor 115 and the top surface of the insulator 180 are at the same height.
  • the insulator 130 is formed on the conductor 115 and the insulator 180 (see FIGS. 35A to 35C).
  • the above description can be referred to.
  • a conductive film that will become the conductor 120 is formed on the insulator 130.
  • the description of the conductive film 120A described above can be referred to.
  • the conductive film a stacked film of titanium nitride and tungsten may be formed in this order using a CVD method.
  • a part of the conductive film that will become the conductor 120 is removed, and the insulator 130 is exposed. As a result, the conductor 120 remains only in the opening 190. Note that a portion of the insulator 130 may be removed by the CMP process. Note that a portion of the conductive film that will become the conductor 120 may be removed using a method other than CMP treatment.
  • etching is performed to remove the upper part of the conductor 120 (see FIGS. 35A to 35C). As a result, the top surface of the conductor 120 is lower than the top surface of the insulator 130.
  • dry etching or wet etching may be used for etching the conductor 120, it is preferable to use dry etching for fine processing.
  • a conductive film 121A is formed on the insulator 130 and the conductor 120 (see FIGS. 36A to 36C).
  • titanium nitride is formed as the conductive film 121A using a CVD method or an ALD method.
  • the conductive film 121A is anisotropically etched to form the conductor 121 in contact with the side surface of the insulator 130 in the opening 190 (see FIGS. 37A to 37C).
  • the anisotropic etching of the conductive film 121A may be performed using, for example, a dry etching method. Note that if the lower layer of the conductor 120 and the conductor 121 are formed of the same material, it may be difficult to clearly detect the boundary between the lower layer of the conductor 120 and the conductor 121.
  • the capacitive element 100 including the conductor 115, the insulator 130, the conductor 120, and the conductor 121 can be formed.
  • the insulator 130, the conductor 121, and the insulator 182 are formed on the conductor 120 (see FIGS. 37A to 37C).
  • any of the above-mentioned insulating materials may be used as appropriate.
  • the insulator 182 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 182 is preferably subjected to CMP treatment after film formation to flatten the upper surface.
  • an opening reaching the conductor 120 is formed in the insulator 182.
  • the opening may be formed using a lithography method. Further, a dry etching method or a wet etching method can be used for etching the opening. Processing by dry etching is suitable for microfabrication.
  • a conductive film that will become the conductor 122 is formed so as to fill the opening formed in the insulator 182.
  • the above-mentioned conductive material may be appropriately used for the conductive film.
  • the conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a laminated film in which tantalum nitride and tungsten are deposited in this order may be formed using a sputtering method.
  • the conductor 122 may be formed by performing CMP treatment on the conductive film until the upper surface of the insulator 182 is exposed.
  • an insulator 280 is formed on the insulator 182 and the conductor 120.
  • the above description can be referred to.
  • a memory device having the memory cell 150 shown in FIGS. 10A to 10C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 10A to 10C can be manufactured.
  • Example 3 of manufacturing method of storage device> a method for manufacturing a memory device shown in FIGS. 20A to 20C, which is one embodiment of the present invention, will be described. Note that for the steps up to forming the insulator 280, the description in ⁇ Example 1 of manufacturing method of memory device> described above can be referred to.
  • An insulator 281 is formed on the insulator 280.
  • the above-mentioned insulating material may be used as appropriate.
  • the insulator 281 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 281 is preferably subjected to CMP treatment after film formation to flatten the upper surface.
  • an opening reaching the insulator 280 is formed in the insulator 281. Since the conductor 240 functioning as a wiring is formed inside the opening, the opening may be provided extending in the X direction.
  • the opening may be formed using a lithography method. Further, a dry etching method or a wet etching method can be used for etching the opening. Processing by dry etching is suitable for microfabrication.
  • the insulator 280 may have a laminated structure, and an insulator functioning as an etching stopper film may be provided on the uppermost surface of the insulator 280.
  • the insulator corresponds to the insulator 280c in the configuration shown in FIG. 17.
  • silicon oxide or silicon oxynitride is used for the insulator 281 forming the opening
  • silicon nitride, aluminum oxide, hafnium oxide, or the like may be used as the etching stopper film.
  • a conductive film that will become the conductor 240 is formed so as to fill the opening formed in the insulator 281.
  • the above-mentioned conductive material may be appropriately used for the conductive film.
  • the conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a laminated film in which tantalum nitride and tungsten are deposited in this order may be formed using a sputtering method.
  • the conductor 240 may be formed by performing CMP treatment on the conductive film until the upper surface of the insulator 281 is exposed.
  • a memory device having the memory cell 150 shown in FIGS. 20A to 20C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 20A to 20C can be manufactured.
  • a new transistor, a new semiconductor device, and a new memory device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a storage device with good frequency characteristics can be provided.
  • a storage device with high operating speed can be provided.
  • a highly reliable storage device can be provided.
  • a storage device with low power consumption can be provided.
  • a memory device including a transistor with a large on-state current can be provided.
  • a memory device with less variation in transistor characteristics can be provided.
  • a storage device with good electrical characteristics can be provided.
  • the memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a small off-state current, it is possible to retain stored contents for a long period of time by using the transistor 200 in a memory device. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced. Further, since the transistor 200 has high frequency characteristics, reading and writing to the memory device can be performed at high speed.
  • FIG. 39A is a plan view of the storage device.
  • FIG. 39B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 39A. Note that in the plan view of FIG. 39A, some elements are omitted for clarity.
  • each of the memory cell 150a and the memory cell 150b shown in FIGS. 39A and 39B has the same configuration as the memory cell 150.
  • the memory cell 150a includes a capacitor 100a and a transistor 200a
  • the memory cell 150b includes a capacitor 100b and a transistor 200b. Therefore, in the storage devices shown in FIGS. 39A and 39B, structures having the same functions as the structures configuring the storage device shown in FIG. 1 are given the same reference numerals. Note that also in this item, the materials described in detail in ⁇ Example of configuration of storage device> can be used as the constituent materials of the storage device.
  • the conductor 260 functioning as the wiring WL is provided in the memory cell 150a and the memory cell 150b, respectively. Further, a conductor 240 that functions as a part of the wiring BL is provided in common to the memory cell 150a and the memory cell 150b. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.
  • the memory device shown in FIGS. 39A and 39B includes a conductor 245 and a conductor 246 that are electrically connected to the memory cell 150a and the memory cell 150b and function as a plug (also referred to as a connection electrode).
  • the conductor 245 is disposed within the openings formed in the insulator 180, the insulator 130, the insulator 280, and the insulator 140, and is in contact with the lower surface of the conductor 240.
  • the conductor 246 is disposed within the openings formed in the insulator 287, the insulator 283, and the insulator 250, and is in contact with the upper surface of the conductor 240. Note that for the conductor 245 and the conductor 246, a conductive material that can be used for the conductor 240 can be used.
  • the dielectric constant is low.
  • an insulator containing a material with a low dielectric constant described in the above-mentioned [Insulator] item can be used in a single layer or a laminated form.
  • the concentration of impurities such as water and hydrogen in the insulator 287 is reduced. Thereby, impurities such as water and hydrogen can be suppressed from entering the channel formation region of the oxide semiconductor 230.
  • the conductor 245 and the conductor 246 electrically connect the memory cell 150a and the memory cell 150b to circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistance elements, and diodes. Acts as a plug or wiring for.
  • a conductor 245 is electrically connected to a sense amplifier (not shown) provided below the storage device shown in FIG. 39, and a conductor 246 is provided above the storage device shown in FIG. It can be configured to be electrically connected to a similar storage device (not shown).
  • the conductor 245 and the conductor 246 function as part of the wiring BL. In this way, by providing a storage device or the like above or below the storage device shown in FIG. 39, the storage capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150b have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged in line-symmetrical positions with the conductor 245 and the conductor 246 in between.
  • the conductor 240 has a function as the other of the source electrode and the drain electrode of the transistor 200a, and a function as the other of the source electrode and the drain electrode of the transistor 200b.
  • the transistor 200a and the transistor 200b share a conductor 245 and a conductor 246 that function as a plug. In this way, by connecting the two transistors and the plug to the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
  • the conductor 110 functioning as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in common in the memory cell 150a and the memory cell 150b. However, as shown in FIG. 39B, the conductor 110 is provided apart from the conductor 245 to prevent short circuit between the conductor 110 and the conductor 245.
  • a memory cell array can be configured by arranging the memory cells 150 three-dimensionally in a matrix.
  • FIGS. 40A and 40B show an example of a memory device in which 4 ⁇ 2 ⁇ 4 memory cells 150 are arranged in the X direction, Y direction, and Z direction.
  • FIG. 40A is a plan view of the storage device.
  • FIG. 40B is a cross-sectional view of the portion shown by the dashed line A1-A2 in FIG. 40A. Note that in the plan view of FIG. 40A, some elements are omitted for clarity.
  • each of the memory cells 150a to 150d shown in FIGS. 40A and 40B has the same configuration as the memory cell 150.
  • the memory cell 150a includes a capacitor 100a and a transistor 200a
  • the memory cell 150b includes a capacitor 100b and a transistor 200b
  • the memory cell 150c includes a capacitor 100c and a transistor 200c
  • the memory cell 150d includes: It has a capacitive element 100d and a transistor 200d. Therefore, in the storage devices shown in FIGS. 40A and 40B, structures having the same functions as the structures configuring the storage device shown in FIG. 1 are given the same reference numerals. Note that also in this item, the materials described in detail in ⁇ Example of configuration of storage device> can be used as the constituent materials of the storage device.
  • FIGS. 40A and 40B includes memory units 160[1,1] to 160[2,4].
  • the memory units 160[1,1] to 160[2,4] may be collectively referred to as the memory unit 160.
  • Memory unit 160[1,2] is provided on memory unit 160[1,1]
  • memory unit 160[1,3] is provided on memory unit 160[1,2]
  • memory unit 160[1,3] is provided on memory unit 160[1,2].
  • 1,4] are provided on the memory unit 160[1,3].
  • Memory unit 160[2,1] is provided adjacent to memory unit 160[1,1] in the Y direction.
  • Memory unit 160[2,2] is provided above memory unit 160[2,1]
  • memory unit 160[2,3] is provided above memory unit 160[2,2]
  • memory unit 160[2,3] is provided above memory unit 160[2,2].
  • 160[2,4] is provided above memory unit 160[2,3].
  • a memory cell 150c is arranged outside the memory cell 150a, and a memory cell 150d is arranged outside the memory cell 150b, with the conductor 245 at the center.
  • the memory cell 150c is provided adjacent to the memory cell 150a, and the memory cell 150d is provided adjacent to the memory cell 150b.
  • the conductor 260 functioning as the wiring WL is shared by memory cells 150 adjacent to each other in the Y direction. Furthermore, the conductor 240 that functions as part of the wiring BL is shared within the same memory unit. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of each of the memory cells 150a to 150d.
  • a conductor 245 is provided between conductors 240 of memory units adjacent in the Z direction.
  • the conductor 245 is provided in contact with the upper surface of the conductor 240 of the memory unit 160[1,1] and the lower surface of the conductor 240 of the memory unit 160[1,2].
  • the wiring BL is formed by the conductor 240 and the conductor 245 provided in each memory unit 160.
  • the conductor 245 is electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. In this way, in the storage device shown in FIG. 40, by stacking a plurality of memory units, the storage capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150c, and the memory cell 150b and the memory cell 150d have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200c, and the transistor 200b and the transistor 200d are also arranged in line-symmetrical positions with the conductor 245 in between.
  • the conductor 240 functions as the other of the source electrode and drain electrode of each of the transistors 200a to 200d.
  • the transistors 200a to 200d share a conductor 245 that functions as a plug. In this way, by connecting the four transistors and the plugs in the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
  • FIG. 40 by stacking a plurality of memory cells, cells can be arranged in an integrated manner without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be configured. Note that although FIG. 40 illustrates a configuration in which four layers each having two memory units are stacked, the present invention is not limited to this.
  • the memory device may have one layer having at least one memory cell 150, or may have two or more layers stacked.
  • FIG. 40 shows a configuration in which a conductor 245 functioning as a plug is arranged between memory cells 150.
  • a configuration is shown in which the conductor 245 functioning as a plug is arranged inside the memory unit 160.
  • Electrical conductor 245 may be placed outside the memory unit.
  • FIGS. 41A and 41B show an example of a memory device in which 3 ⁇ 3 ⁇ 4 memory cells 150 are arranged in the X direction, Y direction, and Z direction.
  • FIG. 41A is a plan view of the storage device.
  • FIG. 41B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 41A. Note that in the plan view of FIG. 41A, some elements are omitted for clarity.
  • the memory device shown in FIGS. 41A and 41B has a structure in which m (m is an integer of 2 or more) layers including the memory cell 150 are laminated.
  • m is an integer of 2 or more
  • the above layer provided as the first layer (bottom) is referred to as layer 170[1]
  • the above layer provided as the second layer is referred to as layer 170[2]
  • the (m-1) layer is referred to as layer 170[1].
  • FIG. 41B shows the provided layer as a layer 170 [m-1], and the m-th (top) layer as a layer 170 [m].
  • the memory device of one embodiment of the present invention may have a plurality of layers including the memory cell 150, and may have a structure in which the plurality of layers are stacked.
  • the conductor 245 may be provided outside the memory unit. Further, the conductor 245 may be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in layer 170[1] is electrically connected to the wiring provided in layer 170[2]. Note that the wiring provided in layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[2]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 41 shows a configuration in which the conductor 245 is electrically connected to wiring provided in the upper layer of the layer containing the conductor 245, the present invention is not limited to this.
  • the conductor 245 may be electrically connected to wiring provided in a layer including the conductor 245.
  • the conductor 245 provided in the layer 170[1] may be electrically connected to the wiring provided in the layer 170[1].
  • the wiring provided in layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 42A the planar layout of the storage device shown in FIG. 41A is shown in FIG. 42A.
  • the planar layout of FIG. 42A shows a region including 4 ⁇ 4 memory cells 150.
  • a conductor 260 functioning as the wiring WL a conductor 240 functioning as the wiring BL, and an opening 290 are illustrated.
  • the memory cell 150 is provided in a region where the conductor 260, the conductor 240, and the opening 290 overlap.
  • the opening 290 is provided in a region of the conductor 240 where the conductor 240 and the conductor 260 intersect.
  • FIG. 42A shows a configuration in which memory cells 150 are arranged in a matrix. Further, a configuration is shown in which the openings 290 are arranged in a matrix. Further, a configuration is shown in which a conductor 260 is provided extending in the Y direction, and a conductor 240 is provided extending in the X direction. In other words, a configuration is shown in which the conductor 260 and the conductor 240 are perpendicular to each other. Further, the width of the conductor 260 in the direction (X direction) perpendicular to the direction in which the conductor 260 extends is uniform, and the width of the conductor 260 in the direction (Y direction) perpendicular to the direction in which the conductor 240 extends is uniform. This shows a configuration in which the width of the area is uniform. Note that the present invention is not limited to this.
  • FIG. 42B is another example of the planar layout of the storage device.
  • the planar layout of FIG. 42B illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 42A.
  • the memory device shown in FIG. 42B differs from the memory device shown in FIG. 42A mainly in the arrangement of the memory cells 150 (openings 290), the shape of the conductors 240, and the direction in which the conductors 260 extend.
  • the memory cells 150 may be arranged such that the odd-numbered rows and the even-numbered rows are shifted by half of the repeating unit of the memory cells 150 (openings 290). Furthermore, the memory cells 150 (openings 290) may be arranged so as to be shifted by half of the repeating unit between odd-numbered columns and even-numbered columns.
  • a memory cell adjacent to the first memory cell in the X direction is a second memory cell
  • a memory cell adjacent to the first memory cell and the second memory cell in the Y direction is a third memory cell.
  • Cell For example, the center of the third memory cell may be located on a straight line that passes between the first memory cell and the second memory cell and is parallel to the Y direction. At this time, it can be said that the third memory cell is located at a position shifted by half in the X direction from the first memory cell and the second memory cell.
  • the conductor 240 has a first region and a second region.
  • the first region is the opening 290 and its vicinity, and the width of the first region in the Y direction is defined as the first width.
  • the first region can be said to have a shape of a quadrilateral with rounded corners.
  • the second region is a region between adjacent openings 290 in one conductor 240, and the width in the Y direction in the second region is defined as the second width.
  • the second width is preferably smaller than the first width.
  • the extending direction of the conductor 260 is arranged at an angle with respect to the Y direction. That is, depending on the arrangement of the memory cells 150 (openings 290), the extending direction of the conductor 260 may not be orthogonal to the extending direction of the conductor 240. In other words, the conductor 260 may intersect with the conductor 240.
  • FIG. 42C is another example of the planar layout of the storage device.
  • the planar layout of FIG. 42C illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similarly to FIG. 42B.
  • the memory device shown in FIG. 42C differs from the memory device shown in FIG. 42B mainly in the shape of the first region of the conductor 240.
  • the first region of the conductor 240 shown in FIG. 42B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X direction or the Y direction.
  • the first region of the conductor 240 shown in FIG. 42C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X direction or the Y direction.
  • FIGS. 42B and 42C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in plan view, the present invention is not limited to this.
  • FIG. 43A is another example of the planar layout of the storage device.
  • the planar layout of FIG. 43A illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 42B.
  • the memory device shown in FIG. 43A differs from the memory device shown in FIG. 42B or 42C mainly in the shape of the first region of the conductor 240.
  • the first region of the conductor 240 shown in FIG. 43A has a circular shape in plan view.
  • the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
  • the first region of the conductor 240 in plan view is not limited to the shape described above.
  • the first region of the conductor 240 in plan view may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • FIG. 43A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, the present invention is not limited to this.
  • FIG. 43B is another example of the planar layout of the storage device.
  • the planar layout of FIG. 43B illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 43A.
  • the memory device shown in FIG. 43B differs from the memory device shown in FIG. 43A mainly in the shape of the conductor 260.
  • the conductor 260 shown in FIG. 43B has a first region and a second region.
  • the first region is the opening 290 and its vicinity, and is circular in plan view.
  • the second region is a region between adjacent openings 290 in one conductor 260. Note that the first region of the conductor 260 overlaps with the first region of the conductor 240.
  • FIG. 43C is another example of the planar layout of the storage device.
  • the planar layout of FIG. 43C illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 43A.
  • the memory device shown in FIG. 43C differs from the memory device shown in FIG. 43A mainly in the shape and stretching direction of the conductor 260.
  • the conductor 260 shown in FIG. 43C has a meandering shape like a triangular wave in plan view, and is provided extending in the Y direction. With this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved. Note that the conductor 260 in plan view is not limited to the above, and may have a meander shape or the like.
  • one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, and the storage device can be miniaturized and highly integrated.
  • FIG. 44 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked on a layer in which a drive circuit including a sense amplifier is provided.
  • the capacitor 100 is provided above the transistor 300, and the transistor 200 is provided above the transistor 300 and the capacitor 100.
  • the transistor 300 is one of the transistors included in the sense amplifier.
  • the configuration of the memory cell 150 (transistor 200 and capacitor 100) shown in FIG. 44 is as described above.
  • the bit line can be shortened. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell.
  • the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as fluctuation in threshold voltage and increase in parasitic resistance, and increase in variation in electrical characteristics due to deterioration of electrical characteristics can be suppressed.
  • the storage device shown in FIG. 44 can correspond to the storage device 80 described in Embodiment 2.
  • transistor 300 corresponds to a transistor included in sense amplifier 46 in memory device 80.
  • the memory cell 150 corresponds to the memory cell 32
  • the transistor 200 corresponds to the transistor 37
  • the capacitor 100 corresponds to the capacitor 38.
  • the transistor 300 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and functions as a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b. Transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate.
  • an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 shown in FIG. 44 is an example, and the structure is not limited, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Here, a plurality of structures of a conductor functioning as a plug or a wiring may be given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided as interlayer films. Further, a conductor 328 is embedded in the insulator 320 and the insulator 322, and a conductor 330 is embedded in the insulator 324 and the insulator 326. Note that the conductor 328 and the conductor 330 function as a plug or wiring.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape underneath.
  • the upper surface of the insulator 322 may be flattened by a flattening process using a CMP method or the like to improve flatness.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or wiring.
  • the above-mentioned insulators that can be used in memory devices can be used.
  • the conductor that functions as a plug or wiring for example, the conductor 328, the conductor 330, the conductor 356, etc., the conductors described in the above [Conductor] can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • the conductor 240 of the transistor 200 connects to the source of the transistor 300 via a conductor 643, a conductor 642, a conductor 644, a conductor 645, a conductor 646, a conductor 356, a conductor 330, and a conductor 328. It is electrically connected to a low resistance region 314b that functions as a region or a drain region.
  • the conductor 643 is embedded in the insulator 280.
  • the conductor 642 is provided on the insulator 130 and embedded in the insulator 641.
  • the conductor 642 can be manufactured using the same material and the same process as the conductor 120.
  • the conductor 644 is embedded in the insulator 180 and the insulator 130.
  • the conductor 645 is embedded in the insulator 647.
  • the conductor 645 can be manufactured using the same material and the same process as the conductor 110.
  • a conductor 646 is embedded in an insulator 648.
  • the transistor 300 and the conductor 110 are electrically insulated by the insulator 648.
  • a novel transistor, a semiconductor device, and a memory device can be provided.
  • a transistor, a semiconductor device, and a memory device that can be miniaturized or highly integrated can be provided.
  • a highly reliable transistor, semiconductor device, and memory device can be provided.
  • a transistor with a large on-state current, a semiconductor device including the transistor, and a memory device can be provided.
  • a semiconductor device and a memory device with less variation in transistor characteristics can be provided.
  • a transistor with good electrical characteristics, and a semiconductor device and a memory device including the transistor can be provided.
  • a semiconductor device and a memory device with low power consumption can be provided.
  • a storage device with good frequency characteristics can be provided.
  • a storage device with high operating speed can be provided.
  • Embodiment 2 a storage device according to one embodiment of the present invention will be described with reference to FIGS. 45 to 48.
  • a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a drive circuit including a sense amplifier is provided will be described.
  • FIG. 45 shows a block diagram illustrating a configuration example of a storage device 80 according to one aspect of the present invention.
  • a storage device 80 shown in FIG. 45 includes a layer 20 and a stacked layer 70.
  • the layer 20 is a layer having a Si transistor.
  • element layers 30[1] to 30[m] (m is an integer of 2 or more) are stacked.
  • the element layers 30[1] to 30[m] are layers including OS transistors.
  • the layer 70 in which layers having OS transistors are stacked can be provided in a stack on the layer 20 .
  • FIG. 45 shows an example in which a plurality of memory cells 32 are arranged in a matrix of m rows and n columns (n is an integer of 2 or more) in the element layers 30[1] to 30[m]. .
  • the memory cell 32 in the first row and first column is shown as a memory cell 32[1,1] and the memory cell 32 in the mth row and nth column is shown as a memory cell 32[m,n].
  • the memory cell 32 in the mth row and nth column is shown as a memory cell 32[m,n].
  • i line when indicating an arbitrary line, it may be written as i line.
  • column j when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the memory cell 32 in the i-th row and j-th column is referred to as a memory cell 32[i,j].
  • m wirings WL extending in the row direction m wirings PL extending in the row direction, n wirings BL extending in the column direction are illustrated. ing.
  • the wiring WL provided in the first (first row) is referred to as wiring WL[1]
  • the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m].
  • the first wiring PL (first row) is designated as wiring PL[1]
  • the mth wiring PL (mth row) is designated as wiring PL[m].
  • wiring BL provided in the first (first column) is referred to as wiring BL[1]
  • wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
  • the number of element layers 30[1] to 30[m] and the number of wirings WL (and wirings PL) may not be the same.
  • the plurality of memory cells 32 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • the plurality of memory cells 32 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling on or off (conductive state or non-conductive state) of an access transistor functioning as a switch.
  • the wiring PL has a function as a constant potential line connected to the capacitor. Note that a wiring CL (not shown) can be provided separately as a wiring for transmitting the back gate potential.
  • the memory cells 32 each of the element layers 30[1] to 30[m] have are connected to the sense amplifier 46 via the wiring BL.
  • the wiring BL can be arranged horizontally and vertically on the surface of the substrate on which the layer 20 is provided.
  • the length of the wiring between the element layer 30 and the sense amplifier 46 can be shortened. Since the signal propagation distance between the memory cell and the sense amplifier can be shortened, and the bit line resistance and parasitic capacitance can be significantly reduced, power consumption and signal delay can be reduced. Therefore, the power consumption and signal delay of the storage device 80 can be reduced. Furthermore, it is possible to operate the memory cell 32 even if the capacitance of the capacitor is reduced. Therefore, the storage device 80 can be made smaller.
  • the layer 20 includes a PSW 71 (power switch), a PSW 72, and a peripheral circuit 22.
  • the peripheral circuit 22 includes a drive circuit 40, a control circuit 73, and a voltage generation circuit 74. Note that each circuit included in the layer 20 is a circuit including a Si transistor.
  • each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • the signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 73.
  • the control circuit 73 is a logic circuit that has a function of controlling the overall operation of the storage device 80. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 80. Alternatively, the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.
  • the control circuit 73 performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 80.
  • the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.
  • the voltage generation circuit 74 has a function of generating a negative voltage.
  • Signal WAKE has a function of controlling input of signal CLK to voltage generation circuit 74. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 74, and the voltage generation circuit 74 generates a negative voltage.
  • the drive circuit 40 is a circuit for writing and reading data to and from the memory cells 32.
  • the drive circuit 40 includes the above-described sense amplifier 46 in addition to a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48.
  • the row decoder 42 and column decoder 44 have a function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying a row to be accessed
  • the column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has a function of writing data into the memory cell 32, a function of reading data from the memory cell 32, a function of holding the read data, and the like.
  • the input circuit 47 has a function of holding the signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written into the memory cell 32.
  • the data (Dout) read from the memory cell 32 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 80.
  • the data output from the output circuit 48 is the signal RDA.
  • the PSW 71 has a function of controlling the supply of VDD to the peripheral circuit 22.
  • the PSW 72 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 80 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD.
  • the signal PON1 controls on/off of the PSW 71
  • the signal PON2 controls the on/off of the PSW 72.
  • the number of power domains to which VDD is supplied is one, but it may be plural. In this case, a power switch may be provided for each power domain.
  • the element layer 30 provided in the first layer is shown as an element layer 30[1]
  • the element layer 30 provided in the second layer is shown as an element layer 30[2]
  • the element layer 30 provided in the fifth layer is shown as an element layer 30[2].
  • the element layer 30 is shown as an element layer 30[5].
  • a wiring WL and a wiring PL provided extending in the X direction a wiring BL and a wiring BLB provided extending in the Y direction and the Z direction (direction perpendicular to the surface of the substrate on which the drive circuit is provided
  • the wiring BLB is an inverted bit line. Note that, in order to make the drawing easier to read, some descriptions of the wiring WL and the wiring PL included in each of the element layers 30 are omitted.
  • FIG. 46B shows the structure of the sense amplifier 46 connected to the wiring BL and the wiring BLB illustrated in FIG. 46A, and the memory cell 32 included in the element layers 30[1] to 30[5] connected to the wiring BL and the wiring BLB.
  • a schematic diagram illustrating an example is shown. Note that a configuration in which a plurality of memory cells (memory cells 32) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string.”
  • FIG. 46B illustrates an example of the circuit configuration of the memory cell 32 connected to the wiring BLB.
  • the memory cell 32 includes a transistor 37 and a capacitor 38.
  • the transistor 37, the capacitor 38, and each wiring (BL, WL, etc.) for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL.
  • the memory cell 150 illustrated in the previous embodiment can be applied to the memory cell 32. That is, the transistor 200 can be used as the transistor 37, and the capacitor 100 can be used as the capacitor 38. Further, as the transistor included in the sense amplifier 46, a transistor 300 (see FIG. 44) can be used.
  • one of the source and drain of the transistor 37 is connected to the wiring BL.
  • the other of the source and drain of the transistor 37 is connected to one electrode of the capacitive element 38.
  • the other electrode of the capacitive element 38 is connected to the wiring PL.
  • the gate of the transistor 37 is connected to the wiring WL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitive element 38.
  • the number of wires can be reduced by connecting the plurality of wires PL as one wire.
  • the OS transistors are provided in a stacked manner, and a wiring functioning as a bit line is arranged in a direction perpendicular to the surface of the substrate on which the layer 20 is provided.
  • the transistor 37 and the capacitive element 38 included in the memory cell 32 are arranged side by side in the direction perpendicular to the substrate surface on which the layer 20 is provided.
  • FIGS. 47A and 47B show a circuit diagram corresponding to the above-described memory cell 32 and a diagram illustrating a circuit block corresponding to the circuit diagram.
  • the memory cells 32 may be represented as blocks in drawings and the like. Note that the wiring BL illustrated in FIGS. 47A and 47B can be similarly represented even when replaced with the wiring BLB.
  • FIGS. 47C and 47D show a circuit diagram corresponding to the above-described sense amplifier 46 and a diagram illustrating a circuit block corresponding to the circuit diagram.
  • the sense amplifier 46 includes a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85.
  • a wiring SA_OUT and a wiring SA_OUTB that output signals to be read are also illustrated.
  • the switch circuit 82 includes, for example, n-channel transistors 82_1 and 82_2.
  • the transistors 82_1 and 82_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.
  • the precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3, as shown in FIG. 47C.
  • the precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD/2 in response to the signal EQ.
  • the precharge circuit 84 is composed of p-channel transistors 84_1 to 84_3, as shown in FIG. 47C.
  • the precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD/2 in response to the signal EQB.
  • the amplifier circuit 85 includes p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4, which are connected to the wiring SAP or the wiring SAN.
  • the wiring SAP or the wiring SAN is a wiring that has a function of providing VDD or VSS.
  • Transistors 85_1 to 85_4 are transistors forming an inverter loop.
  • FIG. 47D shows a diagram illustrating a circuit block corresponding to the sense amplifier 46 described in FIG. 47C and the like. As illustrated in FIG. 47D, the sense amplifier 46 may be represented as a block in drawings, etc.
  • FIG. 48 is a circuit diagram of the storage device 80 of FIG. 45.
  • FIG. 48 is illustrated using the circuit blocks described in FIGS. 47A to 47D.
  • the layer 70 including the element layer 30[m] has the memory cell 32.
  • the memory cell 32 illustrated in FIG. 48 is connected to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2], as an example.
  • the memory cell 32 connected to the wiring BL is a memory cell into which data is written or read.
  • the wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 46[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 46[2].
  • the sense amplifier 46[1] and the sense amplifier 46[2] can read data in response to the various signals described with reference to FIG. 47C.
  • a semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic equipment, large computers, space equipment, and data centers (also referred to as DCs). Electronic components, electronic equipment, large computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving higher performance such as lower power consumption.
  • FIG. 49A A perspective view of a board (mounted board 704) on which electronic component 700 is mounted is shown in FIG. 49A.
  • An electronic component 700 shown in FIG. 49A has a semiconductor device 710 within a mold 711. In FIG. 49A, some descriptions are omitted to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to semiconductor device 710 via wire 714.
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
  • the semiconductor device 710 includes a drive circuit layer 715 and a memory layer 716.
  • the storage layer 716 has a structure in which a plurality of memory cell arrays are stacked.
  • the structure in which the drive circuit layer 715 and the memory layer 716 are stacked can be a monolithic stacked structure.
  • each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • connection wiring etc. can be made smaller compared to technology using through-hole electrodes such as TSV, so it is also possible to increase the number of connection pins.
  • through-hole electrodes such as TSV
  • parallel operation becomes possible, thereby making it possible to improve the memory bandwidth (also referred to as memory bandwidth).
  • the plurality of memory cell arrays included in the storage layer 716 be formed using OS transistors, and the plurality of memory cell arrays be monolithically stacked.
  • OS transistors the plurality of memory cell arrays be monolithically stacked.
  • bandwidth is the amount of data transferred per unit time
  • access latency is the time from access to the start of data exchange.
  • the semiconductor device 710 may be referred to as a die.
  • a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also referred to as a wafer) and cutting it into dice in the semiconductor chip manufacturing process.
  • semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also referred to as a silicon wafer
  • a silicon die is sometimes referred to as a silicon die.
  • the electronic component 730 is an example of SiP (System in Package) or MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.
  • the semiconductor device 710 is used as a high bandwidth memory (HBM).
  • the semiconductor device 735 can be used for an integrated circuit such as a CPU, a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).
  • a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used, for example.
  • the interposer 731 for example, a silicon interposer or a resin interposer can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches.
  • the plurality of wirings are provided in a single layer or in multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732.
  • interposers are sometimes called "rewiring boards" or “intermediate boards.”
  • a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode.
  • TSV can also be used as the through electrode.
  • HBM In HBM, it is necessary to connect many wires to achieve a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
  • a silicon interposer in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to the difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
  • 2.5D package 2.5-dimensional packaging
  • a monolithic stacked structure using OS transistors is preferable. It may also be a composite structure in which a memory cell array stacked using TSVs and a memory cell array stacked monolithically are combined.
  • a heat sink may be provided overlapping the electronic component 730.
  • a heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the heights of the semiconductor device 710 and the semiconductor device 735 are the same.
  • an electrode 733 may be provided on the bottom of the package board 732.
  • FIG. 49B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of implementation methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), and QFJ (Quad Flat J-lead). package), and QFN (Quad Flat Non-leaded package) can be mentioned.
  • FIG. 50A a perspective view of electronic device 6500 is shown in FIG. 50A.
  • Electronic device 6500 shown in FIG. 50A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • An electronic device 6600 shown in FIG. 50B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that it is preferable to use the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 because power consumption can be reduced.
  • FIG. 50C a perspective view of large computer 5600 is shown in FIG. 50C.
  • a plurality of rack-mount computers 5620 are stored in a rack 5610.
  • the large computer 5600 may be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view shown in FIG. 50D.
  • a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • a PC card 5621 shown in FIG. 50E is an example of a processing board that includes a CPU, a GPU, a storage device, and the like.
  • PC card 5621 has a board 5622.
  • the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 50E illustrates semiconductor devices other than the semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, these semiconductor devices are described below. The description of the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621.
  • the respective standards of the connection terminal 5623, connection terminal 5624, and connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Can be mentioned.
  • the respective standards include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 are electrically connected. can be connected to.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • an electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the large computer 5600 can also function as a parallel computer. By using the large-scale computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence learning and inference.
  • a semiconductor device of one embodiment of the present invention can be suitably used for space equipment.
  • a semiconductor device of one embodiment of the present invention includes an OS transistor.
  • OS transistors have small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident.
  • OS transistors can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor configuring a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • the radiation include X-rays and neutron beams.
  • outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.
  • FIG. 51 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that in FIG. 51, a planet 6804 is illustrated in outer space.
  • the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit. It is preferable to use an OS transistor in the battery management system or the battery control circuit described above because it has low power consumption and high reliability even in outer space.
  • BMS battery management system
  • OS transistor an OS transistor in the battery management system or the battery control circuit described above because it has low power consumption and high reliability even in outer space.
  • outer space is an environment with more than 100 times higher radiation levels than on the ground.
  • radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
  • the electric power necessary for the operation of the artificial satellite 6800 is generated.
  • the power necessary for satellite 6800 to operate may not be generated.
  • the solar panel is sometimes called a solar cell module.
  • the satellite 6800 can generate signals.
  • the signal is transmitted via antenna 6803 and can be received by a ground-based receiver or other satellite, for example.
  • a ground-based receiver or other satellite for example.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • OS transistors Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
  • the artificial satellite 6800 can be configured to include a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface.
  • the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
  • OS transistors have superior effects compared to Si transistors, such as being able to realize a wide memory bandwidth and having high radiation resistance.
  • a semiconductor device can be suitably used in, for example, a storage system applied to a data center or the like.
  • Data centers are required to perform long-term data management, including ensuring data immutability.
  • it is necessary to install storage and servers to store huge amounts of data, secure a stable power supply to retain data, or secure cooling equipment required to retain data, etc. due to the large size of the building. ization is required.
  • the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, the power required to hold data can be reduced and the semiconductor device that holds data can be made smaller. Therefore, it is possible to downsize the storage system, downsize the power supply for holding data, downsize the cooling equipment, and so on. Therefore, it is possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • FIG. 52 shows a storage system applicable to data centers.
  • the storage system 7000 shown in FIG. 52 has a plurality of servers 7001sb as hosts 7001 (shown as Host Computer). It also includes a plurality of storage devices 7003md as storage 7003 (shown as Storage).
  • a host 7001 and a storage 7003 are shown connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (Storage Controller).
  • SAN Storage Area Network
  • Storage Controller Storage Controller
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • the storage 7003 uses flash memory to shorten the data access speed, that is, the time required to store and output data, this time is the same as the time required by DRAM, which can be used as a cache memory in the storage. It is much longer than .
  • a cache memory is usually provided in the storage to shorten the time required to store and output data.
  • the cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the storage control circuit 7002 and the cache memory in the storage 7003, and then output to the host 7001 or the storage 7003.
  • an OS transistor as a transistor for storing data in the cache memory described above and maintaining a potential according to the data, the frequency of refreshing can be reduced and power consumption can be reduced. Further, size reduction is possible by using a structure in which memory cell arrays are stacked.
  • the semiconductor device of one embodiment of the present invention by applying the semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, power consumption can be reduced. There is expected. Therefore, as energy demand is expected to increase due to higher performance or higher integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention will reduce the greenhouse effect typified by carbon dioxide (CO 2 ). It also becomes possible to reduce the amount of gas discharged. Further, since the semiconductor device of one embodiment of the present invention has low power consumption, it is effective as a countermeasure against global warming.
  • CO 2 carbon dioxide
  • BL wiring, PL: wiring, Tr: transistor, WL: wiring, 20: layer, 22: peripheral circuit, 30: element layer, 32: memory cell, 37: transistor, 38: capacitive element, 40: drive circuit, 42 : row decoder, 43: row driver, 44: column decoder, 45: column driver, 46 [1]: sense amplifier, 46 [2]: sense amplifier, 46: sense amplifier, 47: input circuit, 48: output circuit, 70: layer, 71: PSW, 72: PSW, 73: control circuit, 74: voltage generation circuit, 80: memory device, 82_1: transistor, 82_2: transistor, 82: switch circuit, 83_1: transistor, 83_3: transistor, 83 : precharge circuit, 84_1: transistor, 84_3: transistor, 84: precharge circuit, 85_1: transistor, 85_2: transistor, 85_3: transistor, 85_4: transistor, 85: amplifier circuit, 100a: capacitor, 100b: capacitor, 100c: capacitive element, 100d

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Abstract

Provided is a storage device which can be micro-fabricated or highly integrated. This storage device has a plurality of memory cells, a first insulator, and a second insulator disposed on the first insulator. Each of the memory cells has a capacitance element and a transistor disposed on the capacitance element. At least a part of the capacitance element is disposed in a first opening provided in the first insulator. At least a part of the transistor is disposed in a second opening provided on the second insulator. The first opening has a region overlapping with the second opening. The diameter of the first opening is larger than the diameter of the second opening. In the adjacent memory cells, the interval at which capacitance elements are arranged coincides with the interval at which transistors are arranged.

Description

記憶装置Storage device
　本発明の一態様は、トランジスタ、半導体装置、記憶装置、および電子機器に関する。または、本発明の一態様は、記憶装置、または半導体装置の作製方法に関する。または、本発明の一態様は、半導体ウエハ、およびモジュールに関する。 One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one embodiment of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer and a module.
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能し得る装置全般を指す。トランジスタなどの半導体素子をはじめ、半導体回路、演算装置、記憶装置は、半導体装置の一態様である。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、電子機器などは、半導体装置を有すると言える場合がある。 Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are examples of semiconductor devices. Display devices (liquid crystal display devices, light emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, and the like can be said to include semiconductor devices.
　なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様は、物、方法、または、製造方法に関するものである。また、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.
　近年、半導体装置の開発が進められ、ＬＳＩ（Ｌａｒｇｅ　Ｓｃａｌｅ　Ｉｎｔｅｇｒａｔｉｏｎ）、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、メモリなどが主に半導体装置に用いられている。ＣＰＵは、半導体ウエハを加工し、チップ化された半導体集積回路（少なくともトランジスタ及び容量）を有し、接続端子である電極が形成された半導体素子の集合体である。 In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, and the like are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements, including a semiconductor integrated circuit (at least a transistor and a capacitor) formed into a chip by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.
　ＬＳＩ、ＣＰＵ、メモリなどの半導体回路（ＩＣチップ）は、回路基板、例えばプリント配線基板に実装され、様々な電子機器の部品の一つとして用いられる。 Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.
　また、絶縁表面を有する基板上に形成された半導体薄膜を用いてトランジスタを構成する技術が注目されている。該トランジスタは集積回路（ＩＣ）、画像表示装置（単に表示装置とも表記する）のような電子デバイスに広く応用されている。トランジスタに適用可能な半導体材料としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。 Additionally, a technology that constructs a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are attracting attention as other materials.
　また、酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいことが知られている。例えば、特許文献１には、酸化物半導体を用いたトランジスタのリーク電流が小さいという特性を応用した低消費電力のＣＰＵなどが開示されている。また、例えば、特許文献２には、酸化物半導体を用いたトランジスタのリーク電流が小さいという特性を応用して、長期にわたり記憶内容を保持することができる記憶装置などが、開示されている。 Furthermore, it is known that a transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that takes advantage of the low leakage current of a transistor using an oxide semiconductor. Further, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a small leakage current.
　また、近年では電子機器の小型化、軽量化に伴い、集積回路のさらなる高密度化への要求が高まっている。また、集積回路を含む半導体装置の生産性の向上が求められている。例えば、特許文献３及び非特許文献１では、酸化物半導体膜を用いる第１のトランジスタと、酸化物半導体膜を用いる第２のトランジスタとを積層させることで、メモリセルを複数重畳して設けることにより、集積回路の高密度化を図る技術が開示されている。 Additionally, in recent years, as electronic devices have become smaller and lighter, there has been an increasing demand for higher density integrated circuits. Additionally, there is a demand for improved productivity of semiconductor devices including integrated circuits. For example, in Patent Document 3 and Non-Patent Document 1, a plurality of memory cells are provided in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film. discloses a technique for increasing the density of integrated circuits.
　さらに、トランジスタを縦型とすることができれば、集積回路の高密度化を図ることができる。例えば、特許文献４には、酸化物半導体の側面が、ゲート絶縁体を介してゲート電極に覆われている縦型のトランジスタが開示されている。 Furthermore, if the transistor can be made vertical, it is possible to increase the density of the integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.
特開２０１２−２５７１８７号公報JP2012-257187A 特開２０１１−１５１３８３号公報JP2011-151383A 国際公開第２０２１／０５３４７３号International Publication No. 2021/053473 特開２０１３−２１１５３７号公報JP2013-211537A
　本発明の一態様は、微細化または高集積化が可能な記憶装置を提供することを課題の一つとする。または、動作速度が速い記憶装置を提供することを課題の一つとする。または、良好な電気特性を有する記憶装置を提供することを課題の一つとする。または、トランジスタの電気特性のばらつきが少ない記憶装置を提供することを課題の一つとする。または、信頼性が良好な記憶装置を提供することを課題の一つとする。または、オン電流が大きい記憶装置を提供することを課題の一つとする。または、低消費電力の記憶装置を提供することを課題の一つとする。または、新規の記憶装置を提供することを課題の一つとする。または、新規の記憶装置の作製方法を提供することを課題の一つとする。 An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Alternatively, one of the challenges is to provide a storage device with high operating speed. Alternatively, one of the challenges is to provide a storage device having good electrical characteristics. Alternatively, it is an object of the present invention to provide a memory device with less variation in the electrical characteristics of transistors. Alternatively, one of the challenges is to provide a storage device with good reliability. Alternatively, one of the challenges is to provide a storage device with a large on-state current. Alternatively, one of the challenges is to provide a storage device with low power consumption. Alternatively, one of the challenges is to provide a new storage device. Alternatively, one of the objectives is to provide a method for manufacturing a new storage device.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 Note that the description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. Note that issues other than these will naturally become clear from the description, drawings, claims, etc., and it is possible to extract issues other than these from the description, drawings, claims, etc. It is.
　本発明の一態様は、第１のメモリセルと、第２のメモリセルと、第１の絶縁体と、第１の絶縁体上の第２の絶縁体と、を有する記憶装置である。第１のメモリセルは、第１の容量素子と、第１の容量素子上の第１のトランジスタと、を有する。第２のメモリセルは、第２の容量素子と、第２の容量素子上の第２のトランジスタと、を有する。第１の容量素子と第２の容量素子が配置される間隔は、第１のトランジスタと第２のトランジスタが配置される間隔と一致する。第１の絶縁体は、第１の開口部と、第２の開口部と、を有する。第１の開口部には、第１の容量素子の少なくとも一部が配置される。第２の開口部には、第２の容量素子の少なくとも一部が配置される。第２の絶縁体は、第３の開口部と、第４の開口部と、を有する。第３の開口部には、第１のトランジスタの少なくとも一部が配置される。第４の開口部には、第２のトランジスタの少なくとも一部が配置される。第１の開口部は、第３の開口部と重なる領域を有する。第２の開口部は、第４の開口部と重なる領域を有する。第１の開口部と、第３の開口部とは、最大幅が互いに異なる。第２の開口部と、第４の開口部とは、最大幅が互いに異なる。 One embodiment of the present invention is a memory device that includes a first memory cell, a second memory cell, a first insulator, and a second insulator over the first insulator. The first memory cell includes a first capacitive element and a first transistor on the first capacitive element. The second memory cell includes a second capacitive element and a second transistor on the second capacitive element. The interval between the first capacitive element and the second capacitive element matches the interval between the first transistor and the second transistor. The first insulator has a first opening and a second opening. At least a portion of the first capacitive element is arranged in the first opening. At least a portion of the second capacitive element is arranged in the second opening. The second insulator has a third opening and a fourth opening. At least a portion of the first transistor is arranged in the third opening. At least a portion of the second transistor is arranged in the fourth opening. The first opening has a region that overlaps with the third opening. The second opening has a region that overlaps with the fourth opening. The first opening and the third opening have different maximum widths. The second opening and the fourth opening have different maximum widths.
　上記記憶装置において、第１の開口部の最大幅は、第３の開口部の最大幅よりも大きく、第２の開口部の最大幅は、第４の開口部の最大幅よりも大きいことが好ましい。 In the above storage device, the maximum width of the first opening may be larger than the maximum width of the third opening, and the maximum width of the second opening may be larger than the maximum width of the fourth opening. preferable.
　上記記憶装置において、第１のトランジスタのチャネル長は、第１のトランジスタのチャネル幅よりも小さく、第２のトランジスタのチャネル長は、第２のトランジスタのチャネル幅よりも小さいことが好ましい。 In the above memory device, the channel length of the first transistor is preferably smaller than the channel width of the first transistor, and the channel length of the second transistor is preferably smaller than the channel width of the second transistor.
　上記記憶装置において、第１のトランジスタ、及び第２のトランジスタのそれぞれは、半導体層に酸化物半導体を有し、酸化物半導体は、Ｉｎ、Ｇａ、及びＺｎの中から選ばれるいずれか一または複数を有することが好ましい。 In the above storage device, each of the first transistor and the second transistor includes an oxide semiconductor in the semiconductor layer, and the oxide semiconductor includes one or more selected from In, Ga, and Zn. It is preferable to have.
　上記記憶装置において、第１の容量素子、及び第２の容量素子のそれぞれは、第１の導電体と、第１の導電体上の第３の絶縁体と、第３の絶縁体上の第２の導電体と、を有し、第３の絶縁体は、第１の酸化ジルコニウムと、第１の酸化ジルコニウム上の酸化アルミニウムと、酸化アルミニウム上の第２の酸化ジルコニウムと、を有することが好ましい。 In the above storage device, each of the first capacitive element and the second capacitive element includes a first conductor, a third insulator on the first conductor, and a third insulator on the third insulator. The third insulator may include a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide. preferable.
　上記記憶装置において、第１のメモリセルと、第２のメモリセルと、を含む層を複数有し、複数の層は、積層されていることが好ましい。 Preferably, the memory device has a plurality of layers including a first memory cell and a second memory cell, and the plurality of layers are stacked.
　本発明の一態様は、第１の導電体と、第１の導電体上のメモリセルと、第１の導電体上の第１の絶縁体と、第２の絶縁体と、を有する記憶装置である。メモリセルは、容量素子と、容量素子上のトランジスタと、を有する。容量素子は、第２の導電体と、第２の導電体上の第３の絶縁体と、第３の絶縁体上の第３の導電体と、を有する。第１の絶縁体には、第１の導電体に達する第１の開口部が設けられる。第２の導電体の少なくとも一部、第３の絶縁体の少なくとも一部、及び、第３の導電体の少なくとも一部は、第１の開口部に配置される。第２の導電体、第３の絶縁体、及び第３の導電体の上に、第２の絶縁体が配置される。トランジスタは、第３の導電体と、第２の絶縁体上の第４の導電体と、酸化物半導体と、第４の絶縁体と、第５の導電体と、を有する。第２の絶縁体及び第４の導電体には、第３の導電体に達する第２の開口部が設けられる。酸化物半導体の少なくとも一部は、第２の開口部に配置される。酸化物半導体は、第２の開口部において第３の導電体の上面に接する領域と、第２の開口部において第４の導電体の側面に接する領域と、第４の導電体の上面の少なくとも一部に接する領域と、を有する。第４の絶縁体は、少なくとも一部が第２の開口部に位置するように、酸化物半導体上に配置される。第５の導電体は、少なくとも一部が第２の開口部に位置するように、第４の絶縁体上に配置される。第１の開口部と、第２の開口部とは、最大幅が互いに異なる。 One embodiment of the present invention provides a memory device including a first conductor, a memory cell on the first conductor, a first insulator on the first conductor, and a second insulator. It is. The memory cell includes a capacitor and a transistor on the capacitor. The capacitive element includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator. The first insulator is provided with a first opening that reaches the first conductor. At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening. A second insulator is disposed on the second conductor, the third insulator, and the third conductor. The transistor includes a third conductor, a fourth conductor on a second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor. The second insulator and the fourth conductor are provided with a second opening that reaches the third conductor. At least a portion of the oxide semiconductor is disposed in the second opening. The oxide semiconductor includes at least a region in contact with the top surface of the third conductor in the second opening, a region in contact with the side surface of the fourth conductor in the second opening, and a region in contact with the top surface of the fourth conductor in the second opening. It has a region that touches a part of it. The fourth insulator is disposed on the oxide semiconductor so that at least a portion thereof is located in the second opening. The fifth conductor is disposed on the fourth insulator such that at least a portion thereof is located in the second opening. The first opening and the second opening have different maximum widths.
　上記記憶装置において、第１の開口部の最大幅は、第２の開口部の最大幅よりも大きいことが好ましい。 In the above storage device, the maximum width of the first opening is preferably larger than the maximum width of the second opening.
　上記記憶装置において、第２の開口部は、第１の開口部と重なる領域を有することが好ましい。 In the above storage device, it is preferable that the second opening has a region that overlaps with the first opening.
　上記記憶装置において、トランジスタのチャネル長は、トランジスタのチャネル幅よりも小さいことが好ましい。 In the above memory device, the channel length of the transistor is preferably smaller than the channel width of the transistor.
　上記記憶装置において、第３の絶縁体は、強誘電性を有しうる材料を含むことが好ましい。 In the above memory device, the third insulator preferably includes a material that can have ferroelectricity.
　上記記憶装置において、第３の絶縁体は、第１の酸化ジルコニウムと、第１の酸化ジルコニウム上の酸化アルミニウムと、酸化アルミニウム上の第２の酸化ジルコニウムと、を有することが好ましい。 In the above storage device, the third insulator preferably includes first zirconium oxide, aluminum oxide on the first zirconium oxide, and second zirconium oxide on the aluminum oxide.
　上記記憶装置において、酸化物半導体は、Ｉｎ、Ｇａ、及びＺｎの中から選ばれるいずれか一または複数を有することが好ましい。 In the above memory device, the oxide semiconductor preferably contains one or more selected from In, Ga, and Zn.
　上記記憶装置において、第１の絶縁体は、積層体を有し、積層体は、第１の層と、第１の層上の第２の層と、を有し、第１の層は、シリコンと、窒素と、を有し、第２の層は、シリコンと、酸素と、を有することが好ましい。 In the above storage device, the first insulator includes a laminate, the laminate includes a first layer, and a second layer on the first layer, and the first layer includes: Preferably, the second layer contains silicon and nitrogen, and the second layer contains silicon and oxygen.
　上記記憶装置において、第１の開口部における第１の絶縁体の側面と、第２の導電体との間に、第５の絶縁体が設けられ、第５の絶縁体は、シリコンと、窒素と、を有することが好ましい。 In the above storage device, a fifth insulator is provided between the side surface of the first insulator in the first opening and the second conductor, and the fifth insulator is made of silicon and nitrogen. It is preferable to have the following.
　上記記憶装置において、第５の導電体は、第１の方向に延在して設けられ、第４の導電体は、第２の方向に延在して設けられ、第１の方向と、第２の方向とは、直交することが好ましい。 In the above storage device, the fifth conductor is provided extending in the first direction, the fourth conductor is provided extending in the second direction, and the fifth conductor is provided extending in the first direction and the fourth conductor is provided extending in the second direction. It is preferable that the second direction is perpendicular to the second direction.
　上記記憶装置において、メモリセルを含む層を複数有し、複数の層は、積層されていることが好ましい。 The above memory device preferably has a plurality of layers including memory cells, and the plurality of layers are preferably stacked.
　本発明の一態様により、微細化または高集積化が可能な記憶装置を提供できる。または、動作速度が速い記憶装置を提供できる。または、信頼性が良好な記憶装置を提供できる。または、トランジスタの電気特性のばらつきが少ない記憶装置を提供できる。または、良好な電気特性を有する記憶装置を提供できる。または、オン電流が大きい記憶装置を提供できる。または、低消費電力の記憶装置を提供できる。または、新規の記憶装置を提供できる。または、新規の記憶装置の作製方法を提供できる。 According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a storage device with high operating speed can be provided. Alternatively, a highly reliable storage device can be provided. Alternatively, a memory device with less variation in the electrical characteristics of transistors can be provided. Alternatively, a storage device with good electrical characteristics can be provided. Alternatively, a storage device with a large on-state current can be provided. Alternatively, a storage device with low power consumption can be provided. Alternatively, new storage devices can be provided. Alternatively, a method for manufacturing a new storage device can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become obvious from the description, drawings, claims, etc., and effects other than these can be extracted from the description, drawings, claims, etc. It is.
図１Ａは、記憶装置の一例を示す平面図である。図１Ｂ及び図１Ｃは、記憶装置の一例を示す断面図である。図１Ｄは、記憶装置の構成の一例を説明するための回路図である。
図２Ａは、記憶装置の一例を示す平面図である。図２Ｂ及び図２Ｃは、記憶装置の一例を示す断面図である。
図３Ａは、記憶装置の一例を示す平面図である。図３Ｂ及び図３Ｃは、記憶装置の一例を示す断面図である。
図４Ａ及び図４Ｂは、記憶装置の一例を示す平面図である。
図５Ａは、記憶装置の一例を示す平面図である。図５Ｂ及び図５Ｃは、記憶装置の一例を示す断面図である。
図６Ａ乃至図６Ｄは、記憶装置の一例を示す断面図である。
図７Ａは、記憶装置の一例を示す平面図である。図７Ｂ及び図７Ｃは、記憶装置の一例を示す断面図である。
図８Ａは、記憶装置の一例を示す平面図である。図８Ｂ及び図８Ｃは、記憶装置の一例を示す断面図である。
図９Ａは、記憶装置の一例を示す平面図である。図９Ｂ及び図９Ｃは、記憶装置の一例を示す断面図である。
図１０Ａは、記憶装置の一例を示す平面図である。図１０Ｂ及び図１０Ｃは、記憶装置の一例を示す断面図である。
図１１Ａは、記憶装置の一例を示す平面図である。図１１Ｂ及び図１１Ｃは、記憶装置の一例を示す断面図である。
図１２Ａ乃至図１２Ｄは、記憶装置の一例を示す断面図である。
図１３Ａは、記憶装置の一例を示す断面図である。図１３Ｂは、記憶装置の一例を示す断面図である。
図１４Ａ乃至図１４Ｄは、記憶装置の一例を示す断面図である。
図１５Ａは、記憶装置の一例を示す平面図である。図１５Ｂ及び図１５Ｃは、記憶装置の一例を示す断面図である。
図１６Ａ及び図１６Ｂは、記憶装置の一例を示す断面図である。
図１７Ａ乃至図１７Ｄは、記憶装置の一例を示す断面図である。
図１８Ａ及び図１８Ｂは、記憶装置の一例を示す断面図である。
図１９Ａは、記憶装置の一例を示す平面図である。図１９Ｂ及び図１９Ｃは、記憶装置の一例を示す断面図である。
図２０Ａは、記憶装置の一例を示す平面図である。図２０Ｂ及び図２０Ｃは、記憶装置の一例を示す断面図である。
図２１Ａは、記憶装置の一例を示す平面図である。図２１Ｂ及び図２１Ｃは、記憶装置の一例を示す断面図である。
図２２Ａは、記憶装置の作製方法の一例を示す平面図である。図２２Ｂ及び図２２Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２３Ａは、記憶装置の作製方法の一例を示す平面図である。図２３Ｂ及び図２３Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２４Ａは、記憶装置の作製方法の一例を示す平面図である。図２４Ｂ及び図２４Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２５Ａは、記憶装置の作製方法の一例を示す平面図である。図２５Ｂ及び図２５Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２６Ａは、記憶装置の作製方法の一例を示す平面図である。図２６Ｂ及び図２６Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２７Ａは、記憶装置の作製方法の一例を示す平面図である。図２７Ｂ及び図２７Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２８Ａは、記憶装置の作製方法の一例を示す平面図である。図２８Ｂ及び図２８Ｃは、記憶装置の作製方法の一例を示す断面図である。
図２９Ａは、記憶装置の作製方法の一例を示す平面図である。図２９Ｂ及び図２９Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３０Ａは、記憶装置の作製方法の一例を示す平面図である。図３０Ｂ及び図３０Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３１Ａは、記憶装置の作製方法の一例を示す平面図である。図３１Ｂ及び図３１Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３２Ａは、記憶装置の作製方法の一例を示す平面図である。図３２Ｂ及び図３２Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３３Ａは、記憶装置の作製方法の一例を示す平面図である。図３３Ｂ及び図３３Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３４Ａは、記憶装置の作製方法の一例を示す平面図である。図３４Ｂ及び図３４Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３５Ａは、記憶装置の作製方法の一例を示す平面図である。図３５Ｂ及び図３５Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３６Ａは、記憶装置の作製方法の一例を示す平面図である。図３６Ｂ及び図３６Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３７Ａは、記憶装置の作製方法の一例を示す平面図である。図３７Ｂ及び図３７Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３８Ａは、記憶装置の作製方法の一例を示す平面図である。図３８Ｂ及び図３８Ｃは、記憶装置の作製方法の一例を示す断面図である。
図３９Ａは、記憶装置の一例を示す平面図である。図３９Ｂは、記憶装置の一例を示す断面図である。
図４０Ａは、記憶装置の一例を示す平面図である。図４０Ｂは、記憶装置の一例を示す断面図である。
図４１Ａは、記憶装置の一例を示す平面図である。図４１Ｂは、記憶装置の一例を示す断面図である。
図４２Ａ乃至図４２Ｃは、記憶装置の一例を示す平面レイアウトである。
図４３Ａ乃至図４３Ｃは、記憶装置の一例を示す平面レイアウトである。
図４４は、記憶装置の一例を示す断面図である。
図４５は、記憶装置の一例を示すブロック図である。
図４６Ａ及び図４６Ｂは、記憶装置の一例を示す模式図である。
図４７Ａ乃至図４７Ｄは、記憶装置の一例を示す回路図である。
図４８は、記憶装置の一例を示す回路図である。
図４９Ａ及び図４９Ｂは、電子部品の一例を示す図である。
図５０Ａ及び図５０Ｂは、電子機器の一例を示す図である。図５０Ｃ乃至図５０Ｅは、大型計算機の一例を示す図である。
図５１は、宇宙用機器の一例を示す図である。
図５２は、データセンターに適用可能なストレージシステムの一例を示す図である。 FIG. 1A is a plan view showing an example of a storage device. FIG. 1B and FIG. 1C are cross-sectional views showing an example of a storage device. FIG. 1D is a circuit diagram for explaining an example of the configuration of a storage device.
FIG. 2A is a plan view showing an example of a storage device. 2B and 2C are cross-sectional views showing an example of a storage device.
FIG. 3A is a plan view showing an example of a storage device. 3B and 3C are cross-sectional views showing an example of a storage device.
4A and 4B are plan views showing an example of a storage device.
FIG. 5A is a plan view showing an example of a storage device. 5B and 5C are cross-sectional views showing an example of a storage device.
6A to 6D are cross-sectional views showing an example of a storage device.
FIG. 7A is a plan view showing an example of a storage device. 7B and 7C are cross-sectional views showing an example of a storage device.
FIG. 8A is a plan view showing an example of a storage device. 8B and 8C are cross-sectional views showing an example of a storage device.
FIG. 9A is a plan view showing an example of a storage device. 9B and 9C are cross-sectional views showing an example of a storage device.
FIG. 10A is a plan view showing an example of a storage device. 10B and 10C are cross-sectional views showing an example of a storage device.
FIG. 11A is a plan view showing an example of a storage device. 11B and 11C are cross-sectional views showing an example of a storage device.
12A to 12D are cross-sectional views showing an example of a storage device.
FIG. 13A is a cross-sectional view showing an example of a storage device. FIG. 13B is a cross-sectional view showing an example of a storage device.
14A to 14D are cross-sectional views showing an example of a storage device.
FIG. 15A is a plan view showing an example of a storage device. 15B and 15C are cross-sectional views showing an example of a storage device.
16A and 16B are cross-sectional views showing an example of a storage device.
17A to 17D are cross-sectional views showing an example of a storage device.
18A and 18B are cross-sectional views showing an example of a storage device.
FIG. 19A is a plan view showing an example of a storage device. 19B and 19C are cross-sectional views showing an example of a storage device.
FIG. 20A is a plan view showing an example of a storage device. 20B and 20C are cross-sectional views showing an example of a storage device.
FIG. 21A is a plan view showing an example of a storage device. 21B and 21C are cross-sectional views showing an example of a storage device.
FIG. 22A is a plan view illustrating an example of a method for manufacturing a storage device. 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 23A is a plan view illustrating an example of a method for manufacturing a storage device. 23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 24A is a plan view illustrating an example of a method for manufacturing a storage device. 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 25A is a plan view showing an example of a method for manufacturing a storage device. 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 26A is a plan view illustrating an example of a method for manufacturing a storage device. 26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 27A is a plan view illustrating an example of a method for manufacturing a storage device. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 28A is a plan view illustrating an example of a method for manufacturing a storage device. 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 29A is a plan view illustrating an example of a method for manufacturing a storage device. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 30A is a plan view showing an example of a method for manufacturing a storage device. 30B and 30C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 31A is a plan view illustrating an example of a method for manufacturing a storage device. 31B and 31C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 32A is a plan view illustrating an example of a method for manufacturing a storage device. 32B and 32C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 33A is a plan view illustrating an example of a method for manufacturing a storage device. 33B and 33C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 34A is a plan view illustrating an example of a method for manufacturing a storage device. 34B and 34C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 35A is a plan view illustrating an example of a method for manufacturing a storage device. 35B and 35C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 36A is a plan view illustrating an example of a method for manufacturing a storage device. 36B and 36C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 37A is a plan view illustrating an example of a method for manufacturing a storage device. 37B and 37C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 38A is a plan view illustrating an example of a method for manufacturing a storage device. 38B and 38C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 39A is a plan view showing an example of a storage device. FIG. 39B is a cross-sectional view showing an example of a storage device.
FIG. 40A is a plan view showing an example of a storage device. FIG. 40B is a cross-sectional view showing an example of a storage device.
FIG. 41A is a plan view showing an example of a storage device. FIG. 41B is a cross-sectional view showing an example of a storage device.
42A to 42C are planar layouts showing an example of a storage device.
43A to 43C are planar layouts showing an example of a storage device.
FIG. 44 is a cross-sectional view showing an example of a storage device.
FIG. 45 is a block diagram showing an example of a storage device.
46A and 46B are schematic diagrams showing an example of a storage device.
47A to 47D are circuit diagrams showing an example of a storage device.
FIG. 48 is a circuit diagram showing an example of a storage device.
49A and 49B are diagrams showing an example of an electronic component.
50A and 50B are diagrams illustrating an example of an electronic device. FIGS. 50C to 50E are diagrams showing an example of a large-sized computer.
FIG. 51 is a diagram showing an example of space equipment.
FIG. 52 is a diagram illustrating an example of a storage system applicable to a data center.
　以下、実施の形態について図面を参照しながら説明する。ただし、実施の形態は多くの異なる態様で実施することが可能であり、趣旨およびその範囲から逸脱することなくその形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。したがって、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways and that the form and details thereof can be changed in various ways without departing from the spirit and scope thereof. Ru. Therefore, the present invention should not be construed as being limited to the contents described in the following embodiments.
　また、図面において、大きさ、層の厚さ、または領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。なお、図面は、理想的な例を模式的に示したものであり、図面に示す形状または値などに限定されない。例えば、実際の製造工程において、エッチングなどの処理により層、またはレジストマスクなどが意図せずに目減りすることがあるが、理解を容易とするため、図に反映しないことがある。また、図面において、同一部分または同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する場合がある。また、同様の機能を指す場合には、ハッチングパターンを同じくし、特に符号を付さない場合がある。 In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally reduced due to a process such as etching, but this may not be reflected in the diagram for ease of understanding. In addition, in the drawings, the same reference numerals are used for the same parts or parts having similar functions in different drawings, and repeated explanations thereof may be omitted. Furthermore, when referring to similar functions, the hatching pattern may be the same and no particular reference numeral may be attached.
　また、特に平面図（「上面図」ともいう）、または斜視図などにおいて、発明の理解を容易とするため、一部の構成要素の記載を省略する場合がある。また、一部の隠れ線の記載を省略する場合がある。 Further, in order to make the invention easier to understand, particularly in a plan view (also referred to as a "top view") or a perspective view, the description of some components may be omitted. In addition, description of some hidden lines may be omitted.
　また、本明細書等において、第１、第２等として付される序数詞は便宜上用いるものであり、工程順または積層順を示すものではない。そのため、例えば、「第１の」を「第２の」または「第３の」などと適宜置き換えて説明することができる。また、本明細書等に記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。 Furthermore, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by replacing "first" with "second" or "third" as appropriate. Furthermore, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
　また、本明細書等において、「上に」、「下に」などの配置を示す語句は、構成要素同士の位置関係を、図面を参照して説明するために、便宜上用いている。また、構成要素同士の位置関係は、各構成要素を描写する方向に応じて適宜変化するものである。したがって、明細書で説明した語句に限定されず、状況に応じて適切に言い換えることができる。 Furthermore, in this specification and the like, words indicating placement such as "above" and "below" are used for convenience in order to explain the positional relationship between constituent elements with reference to the drawings. Further, the positional relationship between the constituent elements changes as appropriate depending on the direction in which each constituent element is depicted. Therefore, the words and phrases are not limited to those explained in the specification, and can be appropriately rephrased depending on the situation.
　例えば、本明細書等において、ＸとＹとが接続されている、とは、ＸとＹとが電気的に接続されているものをいう。ここで、ＸとＹとが電気的に接続されているとは、ＸとＹとの間で対象物（スイッチ、トランジスタ素子、またはダイオード等の素子、あるいは当該素子および配線を含む回路等を指す）が存在する場合にＸとＹとの電気信号の伝達が可能である接続をいう。なおＸとＹとが電気的に接続されている場合には、ＸとＹとが直接接続されている場合を含む。ここで、ＸとＹとが直接接続されているとは、上記対象物を介することなく、ＸとＹとの間で配線（または電極）等を介してＸとＹとの電気信号の伝達が可能である接続をいう。換言すれば、直接接続とは、等価回路で表した際に同じ回路図として見なせる接続をいう。 For example, in this specification and the like, "X and Y are connected" means that X and Y are electrically connected. Here, "X and Y are electrically connected" refers to an object (a switch, a transistor element, an element such as a diode, or a circuit including the element and wiring) between X and Y. ) is a connection that allows transmission of electrical signals between X and Y. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected. Here, "X and Y are directly connected" means that electrical signals are transmitted between X and Y via wiring (or electrodes), etc., without going through the above object. A connection that is possible. In other words, direct connection refers to a connection that can be viewed as the same circuit diagram when expressed as an equivalent circuit.
　また、本明細書等において、トランジスタとは、ゲートと、ドレインと、ソースとを含む少なくとも三つの端子を有する素子である。そして、ドレイン（ドレイン端子、ドレイン領域またはドレイン電極）とソース（ソース端子、ソース領域またはソース電極）の間にチャネルが形成される領域（以下、チャネル形成領域ともいう）を有しており、チャネル形成領域を介して、ソースとドレインとの間に電流を流すことができるものである。なお、本明細書等において、チャネル形成領域とは、電流が主として流れる領域をいう。 Further, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode). A current can be passed between the source and the drain through the formation region. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.
　また、ソース、またはドレインの機能は、異なる極性のトランジスタを採用する場合、または回路動作において電流の方向が変化する場合などには入れ替わることがある。このため、本明細書等においては、ソース、またはドレインの用語は、入れ替えて用いることができる場合がある。 Furthermore, the function of the source or drain may be swapped if transistors with different polarities are used, or if the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain may be used interchangeably.
　なお、半導体の不純物とは、例えば、半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物と言える。不純物が含まれることにより、例えば、半導体の欠陥準位密度が高くなること、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第１族元素、第２族元素、第１３族元素、第１４族元素、第１５族元素、酸化物半導体の主成分以外の遷移金属などがあり、例えば、水素、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。なお、水も不純物として機能する場合がある。また、例えば不純物の混入によって、酸化物半導体に酸素欠損（ＶＯ：ｏｘｙｇｅｎ　ｖａｃａｎｃｙともいう）が形成される場合がある。 Note that the term "impurity of a semiconductor" refers to, for example, something other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities may cause, for example, an increase in the defect level density of the semiconductor, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and the oxide semiconductor. There are transition metals other than the main components, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. Furthermore, oxygen vacancies (also referred to as V O ) may be formed in the oxide semiconductor due to, for example, mixing of impurities.
　なお、本明細書等において、酸化窒化物とは、その組成として、窒素よりも酸素の含有量が多いものである。酸化窒化物としては、酸化窒化シリコン、酸化窒化アルミニウム、及び、酸化窒化ハフニウムなどが挙げられる。また、窒化酸化物とは、その組成として、酸素よりも窒素の含有量が多いものである。窒化酸化物としては、窒化酸化シリコン、窒化酸化アルミニウム、及び、窒化酸化ハフニウムなどが挙げられる。 Note that in this specification and the like, oxynitride refers to a composition containing more oxygen than nitrogen. Examples of the oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. Furthermore, the nitrided oxide has a composition containing more nitrogen than oxygen. Examples of the nitride oxide include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.
　また、本明細書等において、「絶縁体」という用語を、絶縁膜または絶縁層と言い換えることができる。また、「導電体」という用語を、導電膜または導電層と言い換えることができる。また、「半導体」という用語を、半導体膜または半導体層と言い換えることができる。 Additionally, in this specification and the like, the term "insulator" can be translated as an insulating film or an insulating layer. Further, the term "conductor" can be translated as a conductive film or a conductive layer. Further, the term "semiconductor" can be translated as a semiconductor film or a semiconductor layer.
　また、本明細書等において、「平行」とは、二つの直線が−１０度以上１０度以下の角度で配置されている状態をいう。したがって、−５度以上５度以下の場合も含まれる。また、「概略平行」とは、二つの直線が−３０度以上３０度以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０度以上１００度以下の角度で配置されている状態をいう。したがって、８５度以上９５度以下の場合も含まれる。また、「概略垂直」とは、二つの直線が６０度以上１２０度以下の角度で配置されている状態をいう。 Furthermore, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included. Moreover, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Moreover, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included. Moreover, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
　また、本明細書等において、「電圧」と「電位」は、適宜言い換えることができる。「電圧」は、基準となる電位からの電位差のことであり、例えば基準となる電位をグラウンド電位（接地電位）とすると、「電圧」を「電位」に言い換えることができる。なお、グラウンド電位は必ずしも０Ｖを意味するとは限らない。また、電位は相対的なものであり、基準となる電位が変わることによって、配線に与えられる電位、回路などに印加される電位、回路などから出力される電位なども変化する。 Furthermore, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential. For example, if the reference potential is a ground potential (earth potential), "voltage" can be translated into "potential." Note that the ground potential does not necessarily mean 0V. Further, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to circuits, etc., the potential output from circuits, etc. also change.
　本明細書等において、複数の要素に同じ符号を用いる場合、特に、それらを区別する必要があるときには、符号に“＿１”、“［ｎ］”、または“［ｍ，ｎ］”等の識別用の符号を付記して記載する場合がある。 In this specification, etc., when the same code is used for multiple elements, especially when it is necessary to distinguish between them, the code may include an identification such as "_1", "[n]", or "[m,n]". In some cases, a special code may be added to the description.
　なお、本明細書等において、「高さが一致」とは、断面視において、基準となる面（例えば、基板表面などの平坦な面）からの高さが等しい構成を示す。例えば、記憶装置の製造プロセスにおいて、平坦化処理（代表的にはＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）処理）を行うことで、単層または複数の層の表面を露出する場合がある。この場合、ＣＭＰ処理の被処理面は、基準となる面からの高さが等しい構成となる。ただし、ＣＭＰ処理の際の処理装置、処理方法、または被処理面の材料によって、複数の層の高さが異なる場合がある。本明細書等においては、この場合も「高さが一致」として扱う。例えば、基準面に対して、２つの高さを有する層（ここでは第１の層と、第２の層とする）を有する場合であって、第１の層の上面の高さと、第２の層の上面の高さとの差が、２０ｎｍ以下である場合も、「高さが一致」という。 Note that in this specification and the like, "the heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in the manufacturing process of a storage device, the surface of a single layer or a plurality of layers may be exposed by performing a planarization process (typically a CMP (Chemical Mechanical Polishing) process). In this case, the surfaces to be subjected to CMP processing have the same height from the reference surface. However, the heights of the plurality of layers may differ depending on the processing apparatus, processing method, or material of the surface to be processed during CMP processing. In this specification, this case is also treated as "the heights match." For example, in the case of having a layer having two heights (here, referred to as a first layer and a second layer) with respect to a reference plane, the height of the top surface of the first layer and the height of the second layer are Even if the difference from the height of the top surface of the layer is 20 nm or less, it is also said that the heights match.
　なお、本明細書等において、「端部が一致」とは、平面視において、積層した層と層との間で少なくとも輪郭の一部が重なることをいう。例えば、上層と下層とが、同一のマスクパターン、または一部が同一のマスクパターンにより加工された場合を含む。ただし、厳密には輪郭が重ならず、上層の輪郭が下層の輪郭より内側に位置すること、または、上層の輪郭が下層の輪郭より外側に位置することもあり、この場合も「端部が一致」という。 Note that in this specification and the like, "the ends coincide" means that at least a portion of the outlines of the stacked layers overlap in plan view. For example, this includes a case where the upper layer and the lower layer are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours do not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. "Concordance".
　なお、一般に、「完全一致」と「概略一致」の差を明確に区分けするのは困難である。このため、本明細書等において「一致」とは、完全に一致している場合と、概略一致している場合のいずれも含むものとする。 Note that, in general, it is difficult to clearly distinguish between "perfect match" and "approximate match." Therefore, in this specification and the like, "match" includes both a complete match and a general match.
　なお、本明細書等において、ノーマリーオン特性とは、ゲートに電位を印加しなくてもチャネルが存在し、トランジスタに電流が流れてしまう状態のことをいう。また、ノーマリーオフ特性とは、ゲートに電位を印加しない、またはゲートに接地電位を与えたときに、トランジスタに電流が流れない状態のことをいう。 Note that in this specification and the like, normally-on characteristics refer to a state in which a channel exists and current flows through the transistor even without applying a potential to the gate. The normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
　また、本明細書等では、オフ電流と同じ意味で、リーク電流と記載する場合がある。また、本明細書等において、オフ電流とは、例えば、トランジスタがオフ状態にあるときに、ソースとドレインとの間に流れる電流を指す場合がある。 In addition, in this specification and the like, it may be described as leak current, which has the same meaning as off-state current. Further, in this specification and the like, off-state current may refer to, for example, a current flowing between a source and a drain when a transistor is in an off state.
（実施の形態１）
　本実施の形態では、図１乃至図４４を用いて、本発明の一態様である記憶装置の一例、およびその作製方法について説明する。本発明の一態様である記憶装置は、１つ又は複数のメモリセルを有する。また、当該メモリセルは、トランジスタ及び容量素子を有する。 (Embodiment 1)
In this embodiment, an example of a memory device that is one embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1 to 44. A memory device that is one embodiment of the present invention includes one or more memory cells. Further, the memory cell includes a transistor and a capacitor.
＜記憶装置の構成例＞
　図１を用いて、本発明の一態様である記憶装置の構成を説明する。図１Ａ乃至図１Ｃは、メモリセル１５０を有する記憶装置の平面図および断面図である。図１Ａは、当該記憶装置の平面図である。また、図１Ｂ及び図１Ｃは、当該記憶装置の断面図である。ここで、図１Ｂは、図１ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図１Ｃは、図１ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。なお、図１Ａの平面図では、図の明瞭化のために一部の要素を省いている。 <Example of storage device configuration>
The configuration of a storage device that is one embodiment of the present invention will be described using FIG. 1. 1A to 1C are a plan view and a cross-sectional view of a memory device having a memory cell 150. FIG. 1A is a plan view of the storage device. Further, FIGS. 1B and 1C are cross-sectional views of the storage device. Here, FIG. 1B is a sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A. Further, FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. Note that in the plan view of FIG. 1A, some elements are omitted for clarity.
　なお、本明細書に係る図面等において、Ｘ方向、Ｙ方向、及びＺ方向を示す矢印を付す場合がある。なお、本明細書等において、「Ｘ方向」とはＸ軸に沿う方向であり、明示する場合を除き順方向と逆方向を区別しない場合がある。「Ｙ方向」及び「Ｚ方向」についても同様である。また、Ｘ方向、Ｙ方向、及びＺ方向は、それぞれが互いに交差する方向である。例えば、Ｘ方向、Ｙ方向、及びＺ方向は、それぞれが互いに直交する方向である。本明細書等では、Ｘ方向、Ｙ方向、又はＺ方向の１つを「第１方向」又は「第１の方向」と呼ぶ場合がある。また、他の１つを「第２方向」又は「第２の方向」と呼ぶ場合がある。また、残りの１つを「第３方向」又は「第３の方向」と呼ぶ場合がある。 Note that in the drawings and the like related to this specification, arrows indicating the X direction, Y direction, and Z direction may be attached. Note that in this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction". Further, the X direction, the Y direction, and the Z direction are directions that intersect with each other. For example, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction" or a "first direction." Moreover, the other one may be called a "second direction" or a "second direction". Further, the remaining one may be referred to as a "third direction" or "third direction."
　図１Ａ乃至図１Ｃに示す記憶装置は、基板（図示せず）上の絶縁体１４０と、絶縁体１４０上の導電体１１０と、導電体１１０上のメモリセル１５０と、導電体１１０上の絶縁体１８０と、絶縁体１８０上の絶縁体２８０と、メモリセル１５０上の絶縁体２８３と、を有する。絶縁体１４０、絶縁体１８０、絶縁体２８０、及び絶縁体２８３は、層間膜として機能する。導電体１１０は、配線として機能する。 The memory device shown in FIGS. 1A to 1C includes an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 on the conductor 110, and an insulator on the conductor 110. The memory cell includes a body 180, an insulator 280 on the insulator 180, and an insulator 283 on the memory cell 150. Insulator 140, insulator 180, insulator 280, and insulator 283 function as interlayer films. The conductor 110 functions as a wiring.
　メモリセル１５０は、導電体１１０上の容量素子１００と、容量素子１００上のトランジスタ２００と、を有する。 The memory cell 150 includes a capacitive element 100 on a conductor 110 and a transistor 200 on the capacitive element 100.
　容量素子１００は、導電体１１０上の導電体１１５と、導電体１１５上の絶縁体１３０と、絶縁体１３０上の導電体１２０と、を有する。導電体１２０は一対の電極の一方（上部電極と呼ぶ場合がある）として機能し、導電体１１５は一対の電極の他方（下部電極と呼ぶ場合がある）として機能し、絶縁体１３０は誘電体として機能する。つまり、容量素子１００は、ＭＩＭ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ）容量を構成している。 The capacitive element 100 includes a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130. The conductor 120 functions as one of a pair of electrodes (sometimes called an upper electrode), the conductor 115 functions as the other of a pair of electrodes (sometimes called a lower electrode), and the insulator 130 functions as a dielectric. functions as In other words, the capacitive element 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.
　図１Ｂ及び図１Ｃに示すように、絶縁体１８０には、導電体１１０に達する開口部１９０が設けられている。容量素子１００の少なくとも一部は、開口部１９０に配置されている。具体的には、導電体１１５の少なくとも一部、絶縁体１３０の少なくとも一部、及び導電体１２０の少なくとも一部は、開口部１９０に配置されている。なお、導電体１１５は、開口部１９０において導電体１１０の上面に接する領域と、開口部１９０において絶縁体１８０の側面に接する領域と、絶縁体１８０の上面の少なくとも一部に接する領域と、を有する。また、導電体１２０は、図１Ｂ及び図１Ｃに示すように、開口部１９０を埋め込むように設けることが好ましい。 As shown in FIGS. 1B and 1C, the insulator 180 is provided with an opening 190 that reaches the conductor 110. At least a portion of the capacitive element 100 is arranged in the opening 190. Specifically, at least a portion of the conductor 115 , at least a portion of the insulator 130 , and at least a portion of the conductor 120 are arranged in the opening 190 . Note that the conductor 115 has a region in contact with the top surface of the conductor 110 at the opening 190, a region in contact with the side surface of the insulator 180 in the opening 190, and a region in contact with at least a part of the top surface of the insulator 180. have Further, the conductor 120 is preferably provided so as to fill the opening 190, as shown in FIGS. 1B and 1C.
　容量素子１００は、開口部１９０において、底面だけでなく、側面においても上部電極と下部電極とが誘電体を挟んで対向する構成となっており、単位面積当たりの静電容量を大きくすることができる。よって、開口部１９０の深さを深くするほど、容量素子１００の静電容量を大きくすることができる。このように容量素子１００の単位面積当たりの静電容量を大きくすることにより、記憶装置の読み出し動作を安定にすることができる。また、記憶装置の微細化または高集積化を推し進めることができる。 The capacitive element 100 has a structure in which the upper electrode and the lower electrode face each other with a dielectric interposed not only on the bottom surface but also on the side surface of the opening 190, and the capacitance per unit area can be increased. can. Therefore, as the depth of the opening 190 is increased, the capacitance of the capacitive element 100 can be increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, the read operation of the storage device can be stabilized. Further, it is possible to promote miniaturization or higher integration of storage devices.
　開口部１９０の側壁は、導電体１１０の上面に対して垂直であることが好ましい。このとき、開口部１９０は円筒形状を有する。このような構成にすることで、記憶装置の微細化または高集積化を図ることができる。 The side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. At this time, the opening 190 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
　また、本実施の形態では、平面視において開口部１９０が円形である例について示したが、本発明はこれに限られるものではない。例えば、平面視において開口部１９０が、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。このとき、開口部１９０の最大幅は、開口部１９０の最上部の形状に合わせて適宜算出するとよい。例えば、平面視において開口部が四角形である場合、開口部１９０の最大幅は、開口部１９０の最上部の対角線の長さとするとよい。 Further, in this embodiment, an example is shown in which the opening 190 is circular in plan view, but the present invention is not limited to this. For example, in plan view, the opening 190 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners. At this time, the maximum width of the opening 190 may be calculated as appropriate depending on the shape of the top of the opening 190. For example, when the opening is square in plan view, the maximum width of the opening 190 may be the length of the diagonal line at the top of the opening 190.
　導電体１１５、絶縁体１３０、及び導電体１２０の開口部１９０に配置される部分は、開口部１９０の形状を反映して設けられる。よって、開口部１９０の底部及び側壁を覆うように導電体１１５が設けられ、導電体１１５を覆うように絶縁体１３０が設けられ、開口部１９０の形状を反映した絶縁体１３０の凹部を埋め込むように導電体１２０が設けられる。 The conductor 115, the insulator 130, and the portion of the conductor 120 arranged in the opening 190 are provided to reflect the shape of the opening 190. Therefore, the conductor 115 is provided to cover the bottom and side walls of the opening 190, the insulator 130 is provided to cover the conductor 115, and the recess of the insulator 130 that reflects the shape of the opening 190 is filled. A conductor 120 is provided.
　開口部１９０の側壁及び導電体１１０の上面に沿って導電体１１５及び絶縁体１３０が積層して設けられている。また、開口部１９０を埋めるように、絶縁体１３０上に導電体１２０が設けられている。このような構成を有する容量素子１００は、トレンチ型容量またはトレンチ容量と呼称してもよい。 A conductor 115 and an insulator 130 are laminated along the side wall of the opening 190 and the top surface of the conductor 110. Further, a conductor 120 is provided on the insulator 130 so as to fill the opening 190. The capacitive element 100 having such a configuration may be called a trench-type capacitor or a trench capacitor.
　容量素子１００上に、絶縁体２８０が配置されている。つまり、導電体１１５、絶縁体１３０、及び導電体１２０の上に、絶縁体２８０が配置されている。別言すると、絶縁体２８０の下に、導電体１２０が配置されている。 An insulator 280 is placed on the capacitive element 100. That is, the insulator 280 is placed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is placed under the insulator 280.
　トランジスタ２００は、導電体１２０と、絶縁体２８０上の導電体２４０と、酸化物半導体２３０と、酸化物半導体２３０上の絶縁体２５０と、絶縁体２５０上の導電体２６０と、を有する。酸化物半導体２３０は半導体層として機能し、導電体２６０はゲート電極として機能し、絶縁体２５０はゲート絶縁体として機能し、導電体１２０はソース電極及びドレイン電極の一方として機能し、導電体２４０はソース電極及びドレイン電極の他方として機能する。 The transistor 200 includes a conductor 120, a conductor 240 over an insulator 280, an oxide semiconductor 230, an insulator 250 over the oxide semiconductor 230, and a conductor 260 over the insulator 250. The oxide semiconductor 230 functions as a semiconductor layer, the conductor 260 functions as a gate electrode, the insulator 250 functions as a gate insulator, the conductor 120 functions as one of a source electrode and a drain electrode, and the conductor 240 functions as a source electrode and a drain electrode. functions as the other of the source electrode and the drain electrode.
　図１Ｂ及び図１Ｃに示すように、絶縁体２８０及び導電体２４０には、導電体１２０に達する開口部２９０が設けられている。つまり、開口部２９０は、絶縁体２８０に設けられる開口部、及び導電体２４０に設けられる開口部から構成される。このとき、絶縁体２８０に設けられる開口部の側端部と、導電体２４０に設けられる開口部の側端部とは、一致することが好ましい。 As shown in FIGS. 1B and 1C, the insulator 280 and the conductor 240 are provided with an opening 290 that reaches the conductor 120. That is, the opening 290 is composed of an opening provided in the insulator 280 and an opening provided in the conductor 240. At this time, it is preferable that the side edge of the opening provided in the insulator 280 and the side edge of the opening provided in the conductor 240 coincide with each other.
　酸化物半導体２３０の少なくとも一部は、開口部２９０に配置されている。なお、酸化物半導体２３０は、開口部２９０において導電体１２０の上面に接する領域と、開口部２９０において導電体２４０の側面に接する領域と、導電体２４０の上面の少なくとも一部に接する領域と、を有する。絶縁体２５０は、少なくとも一部が開口部２９０に位置するように配置されている。導電体２６０は、少なくとも一部が開口部２９０に位置するように配置されている。なお、導電体２６０は、図１Ｂ及び図１Ｃに示すように、開口部２９０を埋め込むように設けることが好ましい。 At least a portion of the oxide semiconductor 230 is arranged in the opening 290. Note that the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 at the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a part of the top surface of the conductor 240. has. Insulator 250 is arranged such that at least a portion thereof is located in opening 290 . The conductor 260 is arranged so that at least a portion thereof is located in the opening 290. Note that the conductor 260 is preferably provided so as to fill the opening 290, as shown in FIGS. 1B and 1C.
　酸化物半導体２３０は、開口部２９０における導電体２４０の側面と接する領域と、導電体２４０の上面の一部と接する領域と、を有する。このように、酸化物半導体２３０が導電体２４０の側面だけでなく上面にも接することで、酸化物半導体２３０と導電体２４０とが接する面積を大きくすることができる。 The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the upper surface of the conductor 240. In this way, since the oxide semiconductor 230 is in contact with not only the side surface but also the top surface of the conductor 240, the area in which the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
　図１Ａ乃至図１Ｃに示すように、トランジスタ２００は、容量素子１００と重なるように設けられる。また、トランジスタ２００の構造の一部が設けられる開口部２９０は、容量素子１００の構造の一部が設けられる開口部１９０と重なる領域を有する。また、導電体１２０は、トランジスタ２００のソース電極及びドレイン電極の一方としての機能と、容量素子１００の上部電極としての機能とを有するため、トランジスタ２００と容量素子１００は、構造の一部を共有することになる。このような構成にすることで、平面視において、占有面積を大きく増加させることなく、トランジスタ２００及び容量素子１００を設けることができる。これにより、メモリセル１５０の占有面積を低減できるため、メモリセル１５０を高密度に配置し、記憶装置の記憶容量を大きくすることができる。言い換えると、記憶装置を高集積化することができる。 As shown in FIGS. 1A to 1C, the transistor 200 is provided so as to overlap the capacitive element 100. Further, the opening 290 in which a part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which a part of the structure of the capacitor 100 is provided. Further, since the conductor 120 has a function as one of a source electrode and a drain electrode of the transistor 200 and a function as an upper electrode of the capacitor 100, the transistor 200 and the capacitor 100 share a part of the structure. I will do it. With such a configuration, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in plan view. As a result, the area occupied by the memory cells 150 can be reduced, so the memory cells 150 can be arranged with high density and the storage capacity of the memory device can be increased. In other words, the storage device can be highly integrated.
　本実施の形態に示す記憶装置の回路図を図１Ｄに示す。図１Ｄに示すように、図１Ａ乃至図１Ｃに示す構成は、記憶装置のメモリセルとして機能する。メモリセルは、トランジスタＴｒと、容量素子Ｃと、を有する。ここで、トランジスタＴｒはトランジスタ２００に対応し、容量素子Ｃは容量素子１００に対応する。 A circuit diagram of the memory device shown in this embodiment is shown in FIG. 1D. As shown in FIG. 1D, the configuration shown in FIGS. 1A to 1C functions as a memory cell of a storage device. The memory cell includes a transistor Tr and a capacitive element C. Here, the transistor Tr corresponds to the transistor 200, and the capacitive element C corresponds to the capacitive element 100.
　トランジスタＴｒのソース及びドレインの一方は、容量素子Ｃの一対の電極の一方に接続される。トランジスタＴｒのソース及びドレインの他方は、配線ＢＬに接続される。トランジスタＴｒのゲートは、配線ＷＬに接続される。容量素子Ｃの一対の電極の他方は、配線ＰＬに接続される。 One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitive element C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitive element C is connected to the wiring PL.
　ここで、配線ＢＬは導電体２４０に対応し、配線ＷＬは導電体２６０に対応し、配線ＰＬは導電体１１０に対応する。図１Ａ乃至図１Ｃに示すように、導電体２６０はＹ方向に延在して設けられ、導電体２４０はＸ方向に延在して設けられることが好ましい。このような構成にすることで、配線ＢＬと、配線ＷＬは互いに交差して設けられる。配線ＢＬと配線ＷＬとが互いに交差することで、配線ＢＬと配線ＷＬとが重なる領域の面積が小さくなり、配線ＢＬと配線ＷＬとの間に生じる寄生容量を低減できる。また、図１Ａでは、配線ＰＬ（導電体１１０）が面状に設けられているが、本発明はこれに限られるものではない。例えば、配線ＰＬは、配線ＷＬ（導電体２６０）に平行に設けられてもよいし、配線ＢＬ（導電体２４０）に平行に設けられてもよい。 Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 260, and the wiring PL corresponds to the conductor 110. As shown in FIGS. 1A to 1C, the conductor 260 is preferably provided to extend in the Y direction, and the conductor 240 is preferably provided to extend in the X direction. With this configuration, the wiring BL and the wiring WL are provided to intersect with each other. By intersecting the wiring BL and the wiring WL, the area of the region where the wiring BL and the wiring WL overlap becomes smaller, and the parasitic capacitance generated between the wiring BL and the wiring WL can be reduced. Further, in FIG. 1A, the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited to this. For example, the wiring PL may be provided parallel to the wiring WL (conductor 260) or may be provided parallel to the wiring BL (conductor 240).
　図２Ａ乃至図２Ｃには、導電体１１０がＹ方向に延在して設けられている構成を示している。このとき、導電体１１０は、導電体２６０と平行に設けられている。また、導電体１１０は、導電体２４０と直交する。 FIGS. 2A to 2C show a configuration in which the conductor 110 is provided extending in the Y direction. At this time, the conductor 110 is provided parallel to the conductor 260. Further, the conductor 110 is orthogonal to the conductor 240.
　図３Ａ乃至図３Ｃには、導電体１１０がＸ方向に延在して設けられている構成を示している。このとき、導電体１１０は、導電体２４０と平行に設けられている。また、導電体１１０は、導電体２６０と直交する。 FIGS. 3A to 3C show a configuration in which the conductor 110 is provided extending in the X direction. At this time, the conductor 110 is provided parallel to the conductor 240. Further, the conductor 110 is perpendicular to the conductor 260.
　図１Ｂでは、導電体１１５が、Ｘ方向において分断される構成を示しているが、本発明はこれに限られない。例えば、図３Ａ及び図３Ｂに示すように、導電体１１５は、Ｘ方向に延在して設けられてもよい。また、導電体１１０が面状に設けられる構成においては、導電体１１５は、Ｘ方向及びＹ方向に延在して設けられてもよい。 Although FIG. 1B shows a configuration in which the conductor 115 is divided in the X direction, the present invention is not limited to this. For example, as shown in FIGS. 3A and 3B, the conductor 115 may be provided extending in the X direction. Further, in a configuration in which the conductor 110 is provided in a planar shape, the conductor 115 may be provided extending in the X direction and the Y direction.
　なお、メモリセルについては、後の実施の形態で詳細に説明する。 Note that the memory cell will be described in detail in a later embodiment.
　なお、本発明の一態様の記憶装置は、マトリクス状に配置された複数のメモリセル１５０を有することが好ましい。図４Ａ及び図４Ｂに、一例として、Ｘ方向及びＹ方向に、２×２個のメモリセル１５０をマトリクス状に配置した記憶装置の例を示す。 Note that the memory device of one embodiment of the present invention preferably includes a plurality of memory cells 150 arranged in a matrix. 4A and 4B show, as an example, a memory device in which 2×2 memory cells 150 are arranged in a matrix in the X direction and the Y direction.
　図４Ａは、４個のトランジスタ（トランジスタ２００ｐ乃至トランジスタ２００ｓ）を含む領域の平面図である。なお、図４Ａには、各トランジスタが有する、導電体１２０、酸化物半導体２３０、導電体２４０、導電体２６０、及び開口部２９０を抜粋して示す。なお、絶縁体２８０及び導電体２４０に設けられる開口部２９０は点線で示している。また、図４Ａでは、絶縁体２８０を図示していない。 FIG. 4A is a plan view of a region including four transistors (transistors 200p to 200s). Note that FIG. 4A selectively shows the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290 that each transistor has. Note that openings 290 provided in the insulator 280 and the conductor 240 are shown by dotted lines. Further, in FIG. 4A, the insulator 280 is not illustrated.
　図４Ａにおいて、導電体２４０及び絶縁体２８０は、開口部２９０ｐと、開口部２９０ｑと、開口部２９０ｒと、開口部２９０ｓと、を有する。開口部２９０ｐにはトランジスタ２００ｐの少なくとも一部が配置され、開口部２９０ｑにはトランジスタ２００ｑの少なくとも一部が配置され、開口部２９０ｒにはトランジスタ２００ｒの少なくとも一部が配置され、開口部２９０ｓにはトランジスタ２００ｓの少なくとも一部が配置される。 In FIG. 4A, the conductor 240 and the insulator 280 have an opening 290p, an opening 290q, an opening 290r, and an opening 290s. At least part of the transistor 200p is arranged in the opening 290p, at least part of the transistor 200q is arranged in the opening 290q, at least part of the transistor 200r is arranged in the opening 290r, and at least part of the transistor 200r is arranged in the opening 290s. At least a portion of the transistor 200s is arranged.
　図４Ｂは、４個の容量素子（容量素子１００ｐ乃至容量素子１００ｓ）を含む領域の平面図である。なお、図４Ｂには、各容量素子が有する、導電体１１０、導電体１１５、導電体１２０、及び開口部１９０を抜粋して示す。なお、絶縁体１８０に設けられる開口部１９０は点線で示している。また、図４Ｂでは、絶縁体１８０を図示していない。 FIG. 4B is a plan view of a region including four capacitive elements (capacitive elements 100p to 100s). Note that FIG. 4B shows an excerpt of the conductor 110, the conductor 115, the conductor 120, and the opening 190 that each capacitive element has. Note that the opening 190 provided in the insulator 180 is shown by a dotted line. Further, in FIG. 4B, the insulator 180 is not illustrated.
　図４Ｂにおいて、絶縁体１８０は、開口部１９０ｐと、開口部１９０ｑと、開口部１９０ｒと、開口部１９０ｓと、を有する。開口部１９０ｐには容量素子１００ｐの少なくとも一部が配置され、開口部１９０ｑには容量素子１００ｑの少なくとも一部が配置され、開口部１９０ｒには容量素子１００ｒの少なくとも一部が配置され、開口部１９０ｓには容量素子１００ｓの少なくとも一部が配置される。 In FIG. 4B, the insulator 180 has an opening 190p, an opening 190q, an opening 190r, and an opening 190s. At least a part of the capacitive element 100p is arranged in the opening 190p, at least a part of the capacitive element 100q is arranged in the opening 190q, at least a part of the capacitive element 100r is arranged in the opening 190r, and At least a part of the capacitive element 100s is arranged at 190s.
　トランジスタ２００ｐと容量素子１００ｐにより１つのメモリセルが構成され、トランジスタ２００ｑと容量素子１００ｑにより１つのメモリセルが構成され、トランジスタ２００ｒと容量素子１００ｒにより１つのメモリセルが構成され、トランジスタ２００ｓと容量素子１００ｓにより１つのメモリセルが構成される。また、開口部１９０ｐは開口部２９０ｐと重なる領域を有し、開口部１９０ｑは開口部２９０ｑと重なる領域を有し、開口部１９０ｒは開口部２９０ｒと重なる領域を有し、開口部１９０ｓは開口部２９０ｓと重なる領域を有する。 One memory cell is configured by the transistor 200p and the capacitive element 100p, one memory cell is configured by the transistor 200q and the capacitive element 100q, one memory cell is configured by the transistor 200r and the capacitive element 100r, and one memory cell is configured by the transistor 200s and the capacitive element. One memory cell is configured by 100 seconds. Further, the opening 190p has a region overlapping with the opening 290p, the opening 190q has a region overlapping with the opening 290q, the opening 190r has a region overlapping with the opening 290r, and the opening 190s has a region overlapping with the opening 290r. It has an area that overlaps with 290s.
　なお、トランジスタ２００ｐ乃至トランジスタ２００ｓの構成は、上述したトランジスタ２００の説明を参照できる。また、容量素子１００ｐ乃至容量素子１００ｓの構成は、上述した容量素子１００の説明を参照できる。また、開口部１９０ｐ乃至開口部１９０ｓに共通する事項は、開口部１９０と呼称して説明する場合がある。また、開口部２９０ｐ乃至開口部２９０ｓに共通する事項は、開口部２９０と呼称して説明する場合がある。 Note that the above description of the transistor 200 can be referred to for the configurations of the transistors 200p to 200s. Further, for the configurations of the capacitive elements 100p to 100s, the description of the capacitive element 100 described above can be referred to. Further, items common to the openings 190p to 190s may be referred to as the openings 190 for explanation. Furthermore, items common to the openings 290p to 290s may be referred to as the openings 290 in the description.
　図４Ａは、開口部２９０の最大幅Ｄｔを実線の両矢印で示している。なお、平面視において開口部が円形である場合、開口部の最大幅は、開口部の最大径と言い換えることができる。また、図４Ｂは、開口部１９０の最大幅Ｄｃを実線の両矢印で示している。 FIG. 4A shows the maximum width Dt of the opening 290 with a solid double-headed arrow. Note that when the opening is circular in plan view, the maximum width of the opening can be rephrased as the maximum diameter of the opening. Further, FIG. 4B shows the maximum width Dc of the opening 190 with a solid double-headed arrow.
　また、図４Ａは、Ｘ方向に隣接するトランジスタ間の距離ＧＰｔを二点鎖線の両矢印で示している。例えば、距離ＧＰｔは、トランジスタ２００がＸ方向に配置される間隔である。また、距離ＧＰｔは、トランジスタ２００ｐとトランジスタ２００ｑとの間の距離である。ここで、距離ＧＰｔは、Ｘ方向に隣接する開口部２９０の中心間距離であると言える。また、距離ＧＰｔは、配線ＷＬとして機能する導電体２６０が配置される間隔であると言える。よって、距離ＧＰｔは、ゲートピッチと言い換えることができる。また、図４Ｂは、Ｘ方向に隣接する容量素子間の距離ＧＰｃを二点鎖線の両矢印で示している。例えば、距離ＧＰｃは、容量素子１００がＸ方向に配置される間隔である。また、距離ＧＰｃは、容量素子１００ｐと容量素子１００ｑが配置される間隔である。ここで、距離ＧＰｃは、Ｘ方向に隣接する開口部１９０の中心間距離であると言える。 Further, in FIG. 4A, the distance GPt between transistors adjacent in the X direction is indicated by a two-dot chain double-headed arrow. For example, the distance GPt is the interval at which the transistors 200 are arranged in the X direction. Further, the distance GPt is the distance between the transistor 200p and the transistor 200q. Here, the distance GPt can be said to be the distance between the centers of adjacent openings 290 in the X direction. Further, it can be said that the distance GPt is the interval at which the conductors 260 functioning as the wiring WL are arranged. Therefore, the distance GPt can be rephrased as a gate pitch. Further, in FIG. 4B, the distance GPc between adjacent capacitive elements in the X direction is indicated by a two-dot chain double-headed arrow. For example, the distance GPc is the interval at which the capacitive elements 100 are arranged in the X direction. Further, the distance GPc is the interval between the capacitive element 100p and the capacitive element 100q. Here, the distance GPc can be said to be the distance between the centers of adjacent openings 190 in the X direction.
　また、図４Ａは、Ｙ方向に隣接するトランジスタ間の距離ＭＰｔを一点鎖線の両矢印で示している。例えば、距離ＭＰｔは、トランジスタ２００がＹ方向に配置される間隔である。また、距離ＭＰｔは、トランジスタ２００ｐとトランジスタ２００ｒが配置される間隔である。ここで、距離ＭＰｔは、Ｙ方向に隣接する開口部２９０の中心間距離であると言える。また、距離ＭＰｔは、配線ＢＬとして機能する導電体２４０が配置される間隔であると言える。よって、距離ＭＰｔは、メタルピッチと言い換えることができる。また、図４Ｂは、Ｙ方向に隣接する容量素子間の距離ＭＰｃを一点鎖線の両矢印で示している。例えば、距離ＭＰｃは、容量素子１００がＹ方向に配置される間隔である。また、距離ＭＰｃは、容量素子１００ｐと容量素子１００ｒが配置される間隔である。ここで、距離ＭＰｃは、Ｙ方向に隣接する開口部１９０の中心間距離であると言える。 Further, in FIG. 4A, the distance MPt between adjacent transistors in the Y direction is shown by a double-dotted chain arrow. For example, the distance MPt is the interval at which the transistors 200 are arranged in the Y direction. Further, the distance MPt is the interval between the transistor 200p and the transistor 200r. Here, it can be said that the distance MPt is the distance between the centers of adjacent openings 290 in the Y direction. Further, it can be said that the distance MPt is the interval at which the conductors 240 functioning as the wiring BL are arranged. Therefore, the distance MPt can be rephrased as metal pitch. Further, in FIG. 4B, the distance MPc between adjacent capacitive elements in the Y direction is indicated by a double-dotted chain arrow. For example, the distance MPc is the interval at which the capacitive elements 100 are arranged in the Y direction. Further, the distance MPc is the interval between the capacitive element 100p and the capacitive element 100r. Here, it can be said that the distance MPc is the distance between the centers of adjacent openings 190 in the Y direction.
　図４Ａに示すように、開口部２９０は、導電体１２０と重なるように設けられている。また、図４Ｂに示すように、開口部１９０は、導電体１１０と重なるように設けられている。 As shown in FIG. 4A, the opening 290 is provided to overlap the conductor 120. Furthermore, as shown in FIG. 4B, the opening 190 is provided so as to overlap the conductor 110.
　開口部１９０と、開口部２９０とは、最大幅が互いに異なることが好ましい。具体的には、開口部１９０の最大幅Ｄｃは、開口部２９０の最大幅Ｄｔと異なることが好ましい。特に、開口部１９０の最大幅Ｄｃは、開口部２９０の最大幅Ｄｔよりも大きいことが好ましい。このような構成にすることで、容量素子１００の静電容量を大きくすることができる。また、開口部１９０の最大幅Ｄｃを大きくすることで、導電体１１５、絶縁体１３０、及び導電体１２０を、開口部１９０に確実に埋め込むことができ、信頼性が良好な記憶装置を提供できる。また、平面視における導電体１２０の面積を大きくでき、開口部２９０の位置合わせ精度が緩和される。よって、微細なメモリセルを作る上での難易度を下げることが可能となる。 It is preferable that the opening 190 and the opening 290 have different maximum widths. Specifically, the maximum width Dc of the opening 190 is preferably different from the maximum width Dt of the opening 290. In particular, the maximum width Dc of the opening 190 is preferably larger than the maximum width Dt of the opening 290. With such a configuration, the capacitance of the capacitive element 100 can be increased. Furthermore, by increasing the maximum width Dc of the opening 190, the conductor 115, the insulator 130, and the conductor 120 can be reliably embedded in the opening 190, and a highly reliable storage device can be provided. . Furthermore, the area of the conductor 120 in plan view can be increased, and the alignment accuracy of the opening 290 can be relaxed. Therefore, it is possible to reduce the difficulty level in manufacturing fine memory cells.
　上記に加えて、距離ＧＰｃは、距離ＧＰｔと一致することが好ましい。また、距離ＭＰｃは、距離ＭＰｔと一致することが好ましい。このような構成にすることで、メモリセルの占有面積を大きくすることなく、静電容量を大きくすることができる。したがって、記憶装置の読み出し動作を安定にすることができる。また、微細化または高集積化が可能な記憶装置を提供できる。 In addition to the above, it is preferable that the distance GPc matches the distance GPt. Moreover, it is preferable that the distance MPc matches the distance MPt. With such a configuration, the capacitance can be increased without increasing the area occupied by the memory cell. Therefore, the read operation of the storage device can be stabilized. Furthermore, a memory device that can be miniaturized or highly integrated can be provided.
　なお本明細書等において距離Ａと距離Ｂが一致するとは、距離Ａと距離Ｂとの差の絶対値を、距離Ａで除した値が０．１以下であることをいう。または、距離Ａと距離Ｂとの差の絶対値を、距離Ｂで除した値が０．１以下であることをいう。 Note that in this specification and the like, distance A and distance B match means that the value obtained by dividing the absolute value of the difference between distance A and distance B by distance A is 0.1 or less. Alternatively, it means that the value obtained by dividing the absolute value of the difference between distance A and distance B by distance B is 0.1 or less.
　なお、距離ＧＰｃと距離ＧＰｔとが一致し、距離ＭＰｃと距離ＭＰｔとが一致すればよく、距離ＧＰｃと距離ＭＰｃとは一致しなくてもよい。同様に、距離ＧＰｔと距離ＭＰｔとは一致しなくてもよい。 Note that it is only necessary that the distance GPc and the distance GPt match, and the distance MPc and the distance MPt match, and the distance GPc and the distance MPc do not need to match. Similarly, the distance GPt and the distance MPt do not have to match.
　導電体２６０は、一例として、Ｙ方向に配列するトランジスタ２００に共通して設けられる一続きの膜である。また、導電体２４０は、一例として、Ｘ方向に配列するトランジスタ２００に共通して設けられる一続きの膜である。 The conductor 260 is, for example, a continuous film provided in common to the transistors 200 arranged in the Y direction. Further, the conductor 240 is, for example, a continuous film provided in common to the transistors 200 arranged in the X direction.
　上記では、開口部１９０の最大幅が開口部２９０の最大幅よりも大きい場合の例を示した。ところで、本発明の一態様において、開口部１９０の最大幅は、開口部２９０の最大幅と異なることが好ましいことから、開口部１９０の最大幅は、開口部２９０の最大幅よりも小さくてもよい場合がある。言い換えると、開口部２９０の最大幅は、開口部１９０の最大幅よりも大きくてもよい場合がある。図５Ａ乃至図５Ｃには、開口部２９０の最大幅が、開口部１９０の最大幅よりも大きい場合の例を示している。開口部２９０の最大幅を大きくすることで、単位面積当たりのチャネル幅を大きくし、オン電流を大きくすることができる。よって、メモリセル１５０の読み出し速度及び書き込み速度を向上させることができるため、動作速度が速い記憶装置を提供できる。 In the above example, the maximum width of the opening 190 is larger than the maximum width of the opening 290. By the way, in one aspect of the present invention, the maximum width of the opening 190 is preferably different from the maximum width of the opening 290, so the maximum width of the opening 190 may be smaller than the maximum width of the opening 290. Sometimes it's good. In other words, the maximum width of opening 290 may be greater than the maximum width of opening 190. 5A to 5C show an example in which the maximum width of the opening 290 is larger than the maximum width of the opening 190. By increasing the maximum width of the opening 290, the channel width per unit area can be increased and the on-state current can be increased. Therefore, the read speed and write speed of the memory cell 150 can be improved, so that a memory device with high operating speed can be provided.
［容量素子１００］
　容量素子１００は、導電体１１５と、絶縁体１３０と、導電体１２０と、を有する。また、導電体１１５の下方に導電体１１０が設けられている。導電体１１５は、導電体１１０と接する領域を有する。 [Capacitive element 100]
Capacitive element 100 includes a conductor 115, an insulator 130, and a conductor 120. Furthermore, a conductor 110 is provided below the conductor 115 . The conductor 115 has a region in contact with the conductor 110.
　導電体１１０は、絶縁体１４０上に設けられる。導電体１１０は、配線ＰＬとして機能し、例えば、面状に設けることができる。導電体１１０としては、後述する［導電体］の項目に記載の導電体を、単層または積層で用いることができる。例えば、導電体１１０として、タングステンなどの、導電性が高い導電性材料を用いることができる。このように導電性が高い導電性材料を用いることで、導電体１１０の導電性を向上させ、配線ＰＬとして十分に機能させることができる。 The conductor 110 is provided on the insulator 140. The conductor 110 functions as a wiring PL, and can be provided in a planar shape, for example. As the conductor 110, the conductors described in the section [Conductor] described below can be used in a single layer or a laminated structure. For example, as the conductor 110, a highly conductive material such as tungsten can be used. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved and the conductor 110 can sufficiently function as the wiring PL.
　導電体１１５は、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料などを、単層または積層で用いることが好ましい。例えば、窒化チタン、又はシリコンを添加したインジウム錫酸化物などを用いてもよい。又は、例えば、タングステンの上に窒化チタンを積層した構造にしてもよい。又は、例えば、第１の窒化チタンの上にタングステンを積層し、当該タングステンの上に第２の窒化チタンを積層した構造にしてもよい。このような構造にすることで、絶縁体１３０に酸化物絶縁体を用いる場合、絶縁体１３０によって導電体１１０が酸化されるのを抑制できる。また、絶縁体１８０に酸化物絶縁体を用いる場合、絶縁体１８０によって導電体１１０が酸化されるのを抑制できる。 The conductor 115 is preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen, in a single layer or a laminate. For example, titanium nitride or indium tin oxide with added silicon may be used. Alternatively, for example, a structure in which titanium nitride is laminated on tungsten may be used. Alternatively, for example, a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used. By using such a structure, when an oxide insulator is used for the insulator 130, the conductor 110 can be prevented from being oxidized by the insulator 130. Also, when an oxide insulator is used for the insulator 180, the conductor 110 can be prevented from being oxidized by the insulator 180.
　絶縁体１３０は、導電体１１５上に設けられる。絶縁体１３０は、導電体１１５の上面及び側面に接するように設けられる。つまり、絶縁体１３０は、導電体１１０の側端部を覆う構造にすることが好ましい。これにより、導電体１１５と導電体１２０がショートするのを防ぐことができる。 The insulator 130 is provided on the conductor 115. The insulator 130 is provided so as to be in contact with the top and side surfaces of the conductor 115. That is, it is preferable that the insulator 130 has a structure that covers the side end portions of the conductor 110. This can prevent short-circuiting between the conductor 115 and the conductor 120.
　絶縁体１３０として、後述する［絶縁体］の項目に記載の比誘電率が高い材料、所謂ｈｉｇｈ−ｋ材料を用いることが好ましい。絶縁体１３０としてｈｉｇｈ−ｋ材料を用いることで、リーク電流を抑制できる程度に絶縁体１３０を厚くし、且つ容量素子１００の静電容量を十分確保することができる。 As the insulator 130, it is preferable to use a material with a high dielectric constant, a so-called high-k material, described in the section [Insulator] described below. By using a high-k material as the insulator 130, the insulator 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently secured.
　また、絶縁体１３０は、ｈｉｇｈ−ｋ材料からなる絶縁層を積層して用いることが好ましく、比誘電率が高い（ｈｉｇｈ−ｋ）材料と、当該ｈｉｇｈ−ｋ材料より絶縁耐力が大きい材料との積層構造を用いることが好ましい。例えば、絶縁体１３０として、酸化ジルコニウム、酸化アルミニウム、酸化ジルコニウムの順番で積層された絶縁膜を用いることができる。また、例えば、酸化ジルコニウム、酸化アルミニウム、酸化ジルコニウム、酸化アルミニウムの順番で積層された絶縁膜を用いることができる。また、例えば、ハフニウムジルコニウム酸化物、酸化アルミニウム、ハフニウムジルコニウム酸化物、酸化アルミニウムの順番で積層された絶縁膜を用いることができる。酸化アルミニウムのような、比較的絶縁耐力が大きい絶縁体を積層して用いることで、絶縁耐力が向上し、容量素子１００の静電破壊を抑制できる。 Further, it is preferable that the insulator 130 is used by laminating insulating layers made of a high-k material, and is made of a material having a high dielectric constant (high-k) and a material having a dielectric strength higher than that of the high-k material. Preferably, a laminated structure is used. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used. Furthermore, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Furthermore, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By stacking and using an insulator having a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
　また、絶縁体１３０として、強誘電性を有しうる材料を用いてもよい。強誘電性を有しうる材料としては、酸化ハフニウム、酸化ジルコニウム、ＨｆＺｒＯＸ（Ｘは０よりも大きい実数とする）などの金属酸化物が挙げられる。また、強誘電性を有しうる材料としては、酸化ハフニウムに元素Ｊ１（ここでの元素Ｊ１は、ジルコニウム、シリコン、アルミニウム、ガドリニウム、イットリウム、ランタン、ストロンチウムなどから選ばれた一つまたは複数）を添加した材料が挙げられる。ここで、ハフニウムの原子数と元素Ｊ１の原子数の比は適宜設定することができ、例えば、ハフニウムの原子数と元素Ｊ１の原子数の比を１：１またはその近傍にすればよい。また、強誘電性を有しうる材料としては、酸化ジルコニウムに元素Ｊ２（ここでの元素Ｊ２は、ハフニウム、シリコン、アルミニウム、ガドリニウム、イットリウム、ランタン、ストロンチウムなどから選ばれた一つまたは複数）を添加した材料、などが挙げられる。また、ジルコニウムの原子数と元素Ｊ２の原子数の比は適宜設定することができ、例えば、ジルコニウムの原子数と元素Ｊ２の原子数の比を１：１またはその近傍にすればよい。また、強誘電性を有しうる材料として、チタン酸鉛（ＰｂＴｉＯＸ）、チタン酸バリウムストロンチウム（ＢＳＴ）、チタン酸ストロンチウム、チタン酸ジルコン酸鉛（ＰＺＴ）、タンタル酸ビスマス酸ストロンチウム（ＳＢＴ）、ビスマスフェライト（ＢＦＯ）、チタン酸バリウム、などのペロブスカイト構造を有する圧電性セラミックスを用いてもよい。 Further, as the insulator 130, a material that can have ferroelectricity may be used. Examples of materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0). In addition, as a material that can have ferroelectricity, element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Examples include added materials. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set as appropriate. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 may be set to 1:1 or around 1:1. In addition, as a material that can have ferroelectricity, element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Added materials, etc. Further, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set as appropriate. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 may be set to 1:1 or around 1:1. In addition, as materials that can have ferroelectricity, lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), Piezoelectric ceramics having a perovskite structure, such as bismuth ferrite (BFO) and barium titanate, may also be used.
　また、強誘電性を有しうる材料としては、元素Ｍ１と、元素Ｍ２と、窒素と、を有する金属窒化物が挙げられる。ここで、元素Ｍ１は、アルミニウム、ガリウム、インジウムなどから選ばれた一つまたは複数である。また、元素Ｍ２は、ホウ素、スカンジウム、イットリウム、ランタン、セリウム、ネオジム、ユーロピウム、チタン、ジルコニウム、ハフニウム、バナジウム、ニオブ、タンタル、クロムなどから選ばれた一つまたは複数である。なお、元素Ｍ１の原子数と元素Ｍ２の原子数の比は適宜設定することができる。また、元素Ｍ１と、窒素と、を有する金属酸化物は、元素Ｍ２を含まなくても、強誘電性を有する場合がある。また、強誘電性を有しうる材料としては、上記金属窒化物に元素Ｍ３が添加された材料が挙げられる。なお、元素Ｍ３は、マグネシウム、カルシウム、ストロンチウム、亜鉛、カドミウムなどから選ばれた一つまたは複数である。ここで、元素Ｍ１の原子数、元素Ｍ２の原子数、および元素Ｍ３の原子数の比は適宜設定することができる。 Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, and the like. Further, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate. Further, a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2. In addition, examples of materials that can have ferroelectricity include materials in which element M3 is added to the metal nitride described above. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.
　また、強誘電性を有しうる材料としては、ＳｒＴａＯ２Ｎ、ＢａＴａＯ２Ｎなどのペロブスカイト型酸窒化物、κアルミナ型構造のＧａＦｅＯ３などが挙げられる。 Furthermore, examples of materials that can have ferroelectricity include perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a κ alumina structure.
　なお、上記の説明においては、金属酸化物、及び金属窒化物について例示したがこれに限定されない。例えば、上述の金属酸化物に窒素が添加された金属酸窒化物、または上述の金属窒化物に酸素が添加された金属窒酸化物などを用いてもよい。 Note that in the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, a metal oxynitride obtained by adding nitrogen to the above-mentioned metal oxide, or a metal nitride obtained by adding oxygen to the above-mentioned metal nitride, etc. may be used.
　また、強誘電性を有しうる材料としては、例えば、上記に列挙した材料から選ばれた複数の材料からなる混合物または化合物を用いることができる。または、絶縁体１３０を、上記に列挙した材料から選ばれた複数の材料からなる積層構造とすることができる。ところで、上記に列挙した材料などは、成膜条件だけでなく、各種プロセスなどによっても結晶構造（特性）が変わり得る可能性があるため、本明細書等では強誘電性を発現する材料のみを強誘電体と呼ぶだけでなく、強誘電性を有しうる材料とも呼んでいる。 Furthermore, as the material that can have ferroelectricity, for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator 130 can have a laminated structure made of a plurality of materials selected from the materials listed above. By the way, the crystal structure (characteristics) of the materials listed above may change not only due to film formation conditions but also due to various processes, so in this specification, only materials that exhibit ferroelectricity will be referred to. It is not only called a ferroelectric material, but also a material that can have ferroelectric properties.
　ハフニウム及びジルコニウムの一方又は両方を含む金属酸化物は、数ｎｍといった薄膜に加工しても強誘電性を有しうることができるため、好ましい。ここで、絶縁体１３０の膜厚は、１００ｎｍ以下、好ましくは５０ｎｍ以下、より好ましくは２０ｎｍ以下、さらに好ましくは１０ｎｍ以下（代表的には、２ｎｍ以上９ｎｍ以下）にすることができる。例えば、膜厚を、８ｎｍ以上１２ｎｍ以下にすることが好ましい。薄膜化することができる強誘電体層とすることで、容量素子１００を、微細化されたトランジスタなどの半導体素子に組み合わせて半導体装置を形成することができる。なお、本明細書等において、強誘電性を有しうる材料を層状にしたものを指して、強誘電体層、金属酸化物膜、または金属窒化物膜と呼ぶ場合がある。また、このような、強誘電体層、金属酸化物膜、または金属窒化物膜を有する装置を、本明細書等において、強誘電体デバイスと呼ぶ場合がある。 A metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even when processed into a thin film of several nanometers. Here, the film thickness of the insulator 130 can be set to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). For example, the film thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be made thin, a semiconductor device can be formed by combining the capacitor 100 with a semiconductor element such as a miniaturized transistor. Note that in this specification and the like, a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
　また、ハフニウム及びジルコニウムの一方又は両方を含む金属酸化物は、微小な面積でも強誘電性を有しうることができるため、好ましい。例えば、強誘電体層の上面視における面積（占有面積）が、１００μｍ２以下、１０μｍ２以下、１μｍ２以下、又は０．１μｍ２以下であっても、強誘電性を有することができる。また、１００００ｎｍ２以下、又は１０００ｎｍ２以下であっても、強誘電性を有する場合がある。面積が小さい強誘電体層とすることで、容量素子１００の占有面積を小さくすることができる。 Further, a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a minute area. For example, even if the area (occupied area) of the ferroelectric layer when viewed from above is 100 μm 2 or less, 10 μm 2 or less, 1 μm 2 or less, or 0.1 μm 2 or less, it can have ferroelectricity. Further, even if the thickness is 10000 nm 2 or less, or 1000 nm 2 or less, it may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitive element 100 can be reduced.
　強誘電体は、絶縁体であって、外部から電場を与えることによって内部に分極が生じ、かつ当該電場をゼロにしても分極が残る性質を有する。このため、当該材料を誘電体として用いた容量素子（以下、強誘電体キャパシタと呼ぶ場合がある）を用いて、不揮発性の記憶素子を形成することができる。強誘電体キャパシタを用いた、不揮発性の記憶素子は、ＦｅＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、強誘電体メモリなどと呼ばれることがある。例えば、強誘電体メモリは、トランジスタと、強誘電体キャパシタを有し、トランジスタのソースおよびドレインの一方が、強誘電体キャパシタの一方の端子に電気的に接続された構成を有する。よって、容量素子１００として強誘電体キャパシタを用いる場合、本実施の形態で示す記憶装置は、強誘電体メモリとして機能する。 A ferroelectric material is an insulator, and has the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be formed using a capacitive element using this material as a dielectric (hereinafter sometimes referred to as a ferroelectric capacitor). A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the storage device described in this embodiment functions as a ferroelectric memory.
　なお、強誘電性は、外部電場により強誘電体層に含まれる結晶の酸素又は窒素が変位することで、発現するとされている。また、強誘電性の発現は、強誘電体層に含まれる結晶の結晶構造に依存すると推定される。よって、絶縁体１３０が強誘電性を発現するには、絶縁体１３０は結晶を含む必要がある。特に絶縁体１３０は、直方晶系の結晶構造を有する結晶を含むと、強誘電性が発現するため好ましい。なお、絶縁体１３０に含まれる結晶の結晶構造としては、立方晶系、正方晶系、直方晶系、単斜晶系、及び六方晶系の中から選ばれるいずれか一または複数であってもよい。また、絶縁体１３０は、アモルファス構造を有していてもよい。このとき、絶縁体１３０は、アモルファス構造と、結晶構造とを有する複合構造としてもよい。 Note that ferroelectricity is said to be developed when oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by an external electric field. Furthermore, the development of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, it is preferable for the insulator 130 to include a crystal having a rectangular crystal structure because ferroelectricity is exhibited. Note that the crystal structure of the crystal contained in the insulator 130 may be one or more selected from cubic, tetragonal, rectangular, monoclinic, and hexagonal. good. Further, the insulator 130 may have an amorphous structure. At this time, the insulator 130 may have a composite structure having an amorphous structure and a crystal structure.
　導電体１２０は、絶縁体１３０の上面の一部に接して設けられる。また、図４Ｂに示すように、導電体１２０の側端部は、Ｘ方向及びＹ方向のいずれにおいても、導電体１１５の側端部よりも内側に位置することが好ましい。なお、絶縁体１３０が導電体１１５の側端部を覆う構造においては、導電体１２０の側端部は、導電体１１５の側端部よりも外側に位置してもよい。 The conductor 120 is provided in contact with a part of the upper surface of the insulator 130. Further, as shown in FIG. 4B, the side end portion of the conductor 120 is preferably located inside the side end portion of the conductor 115 in both the X direction and the Y direction. Note that in a structure in which the insulator 130 covers the side end portion of the conductor 115, the side end portion of the conductor 120 may be located outside the side end portion of the conductor 115.
　導電体１２０としては、後述する［導電体］の項目に記載の導電体を、単層または積層で用いることができる。導電体１２０として、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料などを用いることが好ましい。例えば、窒化チタンまたは窒化タンタルなどを用いることができる。また、例えば、窒化チタンの上に窒化タンタルを積層した構造にしてもよい。この場合、窒化チタンが絶縁体１３０に接し、窒化タンタルが酸化物半導体２３０に接する。このような構造にすることで、酸化物半導体２３０によって導電体１２０が過剰に酸化されるのを抑制できる。また、絶縁体１３０に酸化物絶縁体を用いる場合、絶縁体１３０によって導電体１２０が過剰に酸化されるのを抑制できる。又は、導電体１２０として、例えば、窒化チタンの上にタングステンを積層した構造にしてもよい。 As the conductor 120, the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner. As the conductor 120, it is preferable to use a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or the like. For example, titanium nitride or tantalum nitride can be used. Further, for example, a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230. With such a structure, excessive oxidation of the conductor 120 by the oxide semiconductor 230 can be suppressed. Further, when an oxide insulator is used for the insulator 130, the conductor 120 can be prevented from being excessively oxidized by the insulator 130. Alternatively, the conductor 120 may have a structure in which tungsten is laminated on titanium nitride, for example.
　また、導電体１２０は、酸化物半導体２３０と接する領域を有するため、後述する［導電体］の項目に記載の酸素を含む導電性材料を用いることが好ましい。導電体１２０として酸素を含む導電性材料を用いることで、導電体１２０が酸素を吸収しても導電性を維持することができる。また、絶縁体１３０として酸化ジルコニウムなどの酸素を含む絶縁体を用いる場合においても、導電体１２０は導電性を維持できるため好適である。導電体１２０として、例えば、インジウム錫酸化物（ＩＴＯともいう）、シリコンを添加したインジウム錫酸化物（ＩＴＳＯともいう）、インジウム亜鉛酸化物（ＩＺＯ（登録商標）ともいう）などを単層または積層で用いることができる。 Further, since the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described below. By using a conductive material containing oxygen as the conductor 120, conductivity can be maintained even if the conductor 120 absorbs oxygen. Further, even when an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is suitable because it can maintain conductivity. As the conductor 120, for example, a single layer or a stack of indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used in
　絶縁体１８０は層間膜として機能するため、比誘電率が低いことが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体１８０としては、後述する［絶縁体］の項目に記載の、比誘電率が低い材料を含む絶縁体を、単層または積層で用いることができる。酸化シリコン、及び酸化窒化シリコンは、熱的に安定であるため好ましい。このとき、絶縁体１８０ｂは、少なくともシリコンと、酸素と、を有する。 Since the insulator 180 functions as an interlayer film, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 180, an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. At this time, the insulator 180b includes at least silicon and oxygen.
　なお、図１Ｂ及び図１Ｃでは、絶縁体１８０を単層で示したが、本発明はこれに限られるものではない。絶縁体１８０は、積層構造であってもよい。 Note that although the insulator 180 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this. The insulator 180 may have a laminated structure.
　例えば、図６Ａ及び図６Ｂに示すように、絶縁体１８０は、絶縁体１８０ａと、絶縁体１８０ａ上の絶縁体１８０ｂとの積層構造を有してもよい。 For example, as shown in FIGS. 6A and 6B, the insulator 180 may have a laminated structure of an insulator 180a and an insulator 180b on the insulator 180a.
　絶縁体１８０ｂとしては、上述した絶縁体１８０に適用可能な絶縁性材料を用いるとよい。 As the insulator 180b, it is preferable to use an insulating material that is applicable to the insulator 180 described above.
　絶縁体１８０ａには、後述する［絶縁体］の項目に記載の、酸素に対するバリア性を有する絶縁体を用いることが好ましい。絶縁体１８０ｂに含まれる酸素によって、導電体１１０が酸化され、抵抗が高くなってしまう場合がある。絶縁体１８０ｂと導電体１１０との間に絶縁体１８０ａを設けることにより、導電体１１０が酸化され、抵抗が高くなることを抑制できる。 For the insulator 180a, it is preferable to use an insulator having barrier properties against oxygen, as described in the [Insulator] section below. The oxygen contained in the insulator 180b may oxidize the conductor 110, increasing its resistance. By providing the insulator 180a between the insulator 180b and the conductor 110, it is possible to prevent the conductor 110 from being oxidized and its resistance from increasing.
　絶縁体１３０に水素などの不純物が混入すると、上部電極と下部電極の間に生じるリーク電流が増加する場合がある。また、絶縁体１３０として強誘電性を有しうる材料を用いる場合、強誘電性を有しうる材料中に水素などの不純物が混入することで、強誘電性を有しうる材料の結晶性を低下させる恐れがある。そこで、絶縁体１３０に、水素などの不純物が混入するのを抑制することが好ましい。 When impurities such as hydrogen are mixed into the insulator 130, leakage current generated between the upper electrode and the lower electrode may increase. Furthermore, when a material that can have ferroelectricity is used as the insulator 130, impurities such as hydrogen may be mixed into the material that can have ferroelectricity, which may reduce the crystallinity of the material that can have ferroelectricity. There is a risk of deterioration. Therefore, it is preferable to prevent impurities such as hydrogen from entering the insulator 130.
　そこで、絶縁体１８０ａには、後述する［絶縁体］の項目に記載の、水素に対するバリア性を有する絶縁体を用いることが好ましい。これにより、容量素子１００の下方から絶縁体１８０ｂを介して、絶縁体１３０に水素が拡散することを抑制できる。窒化シリコン、及び窒化酸化シリコンは、それぞれ、自身からの不純物（例えば、水及び水素）の放出が少なく、酸素及び水素が透過しにくい特徴を有するため、絶縁体１８０ａに好適に用いることができる。このとき、絶縁体１８０ａは、少なくともシリコンと、窒素と、を有する。 Therefore, as the insulator 180a, it is preferable to use an insulator having barrier properties against hydrogen, which is described in the section [Insulator] described later. This can suppress hydrogen from diffusing into the insulator 130 from below the capacitive element 100 via the insulator 180b. Silicon nitride and silicon nitride oxide can be suitably used for the insulator 180a because they each release less impurities (for example, water and hydrogen) from themselves and are less permeable to oxygen and hydrogen. At this time, the insulator 180a includes at least silicon and nitrogen.
　また、絶縁体１８０ａとして、後述する［絶縁体］の項目に記載の、水素を捕獲するまたは水素を固着する機能を有する絶縁体を用いることが好ましい。このような構成にすることで、絶縁体１３０の水素を捕獲または固着し、絶縁体１３０の水素濃度を低減できる。絶縁体１８０ａとしては、酸化マグネシウム、酸化アルミニウム、又は酸化ハフニウムなどを用いることができる。また、例えば、絶縁体１８０ａとして、酸化アルミニウムと、当該酸化アルミニウム上の窒化シリコンの積層膜を用いてもよい。 Further, as the insulator 180a, it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced. As the insulator 180a, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 180a.
　なお、図６Ａ及び図６Ｂでは絶縁体１８０が２層の積層構造である構成を示しているが、本発明の一態様はこれに限られない。絶縁体１８０は、３層以上の積層構造であってもよい。 Note that although FIGS. 6A and 6B show a structure in which the insulator 180 has a two-layer stacked structure, one embodiment of the present invention is not limited to this. The insulator 180 may have a laminated structure of three or more layers.
　例えば、絶縁体１８０を３層積層構造とする場合、絶縁体１８０ａ及び絶縁体１８０ｂに加えて、導電体１１５及び絶縁体１３０と絶縁体１８０ｂとの間に絶縁体を設けるとよい。当該絶縁体として、絶縁体１８０ａに適用可能な絶縁体を用いることができる。これにより、絶縁体１８０ｂを介して、絶縁体１３０に水素が拡散することを抑制できる。 For example, when the insulator 180 has a three-layer laminated structure, an insulator may be provided between the conductor 115 and the insulator 130 and the insulator 180b in addition to the insulator 180a and the insulator 180b. As the insulator, an insulator applicable to the insulator 180a can be used. This can suppress hydrogen from diffusing into the insulator 130 via the insulator 180b.
　また、図６Ａ及び図６Ｂに示すように、導電体１１５と絶縁体１８０との間に絶縁体１８５を設けることが好ましい。また、絶縁体１８５は、開口部１９０における絶縁体１８０の側面に接するように設けられることが好ましい。つまり、絶縁体１８５は、開口部１９０における絶縁体１８０の側面と、導電体１１５との間に設けられることが好ましい。 Furthermore, as shown in FIGS. 6A and 6B, it is preferable to provide an insulator 185 between the conductor 115 and the insulator 180. Further, it is preferable that the insulator 185 is provided so as to be in contact with the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115.
　絶縁体１８５には、後述する［絶縁体］の項目に記載の、水素に対するバリア性を有する絶縁体を用いることが好ましい。これにより、容量素子１００の外から絶縁体１８０を介して、絶縁体１３０に水素が拡散することを抑制できる。例えば、絶縁体１８５として、窒化シリコン、又は窒化酸化シリコンを用いることができる。このとき、絶縁体１８５は、少なくともシリコンと、窒素と、を有する。 As the insulator 185, it is preferable to use an insulator that has barrier properties against hydrogen and is described in the section [Insulator] described below. This can suppress hydrogen from diffusing into the insulator 130 from outside the capacitive element 100 via the insulator 180. For example, silicon nitride or silicon nitride oxide can be used as the insulator 185. At this time, the insulator 185 includes at least silicon and nitrogen.
　また、絶縁体１８５として、後述する［絶縁体］の項目に記載の、水素を捕獲するまたは水素を固着する機能を有する絶縁体を用いることが好ましい。このような構成にすることで、絶縁体１３０の水素を捕獲または固着し、絶縁体１３０の水素濃度を低減できる。絶縁体１８５としては、酸化マグネシウム、酸化アルミニウム、又は酸化ハフニウムなどを用いることができる。また、例えば、絶縁体１８５として、酸化アルミニウムと、当該酸化アルミニウム上の窒化シリコンの積層膜を用いてもよい。 Further, as the insulator 185, it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced. As the insulator 185, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 185.
　なお、図６Ａ及び図６Ｂでは、開口部１９０における絶縁体１８０ａの側面、及び開口部１９０における絶縁体１８０ｂの側面と接するように、絶縁体１８５が設けられているが、本発明はこれに限られるものではない。例えば図６Ｃ及び図６Ｄに示すように、絶縁体１８５は、絶縁体１８０ａの上面の一部、及び開口部１９０における絶縁体１８０ｂの側面と接するように設けられてもよい。 Note that in FIGS. 6A and 6B, the insulator 185 is provided so as to be in contact with the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited to this. It's not something you can do. For example, as shown in FIGS. 6C and 6D, the insulator 185 may be provided so as to be in contact with a part of the upper surface of the insulator 180a and the side surface of the insulator 180b at the opening 190.
　なお、図１Ｂ及び図１Ｃでは、導電体１１５が絶縁体１８０の上面と接する領域を有する構成を示しているが、本発明はこれに限られるものではない。例えば、図７Ｂ及び図７Ｃに示すように、導電体１１５の上面は、絶縁体１８０の上面と高さが一致してもよい。このとき、図７Ａ乃至図７Ｃに示すように、導電体１２０の側端部は、導電体１１５の側端部よりも外側に位置してもよい。なお、導電体１２０の側端部は、導電体１１５の側端部と一致してもよいし、導電体１１５の側端部の内側に位置してもよい。 Note that although FIGS. 1B and 1C show a configuration in which the conductor 115 has a region in contact with the upper surface of the insulator 180, the present invention is not limited to this. For example, as shown in FIGS. 7B and 7C, the top surface of the conductor 115 may be level with the top surface of the insulator 180. At this time, as shown in FIGS. 7A to 7C, the side end of the conductor 120 may be located outside the side end of the conductor 115. Note that the side end of the conductor 120 may coincide with the side end of the conductor 115 or may be located inside the side end of the conductor 115.
　なお、図７Ａ乃至図７Ｃでは、導電体１２０の上面の高さが、絶縁体１３０の上面の高さよりも高い構成を示しているが、本発明はこれに限られるものではない。例えば、導電体１２０の上面の高さは、絶縁体１３０の上面の高さと一致してもよいし、絶縁体１３０の上面の高さよりも低くてもよい。 Note that although FIGS. 7A to 7C show a configuration in which the height of the top surface of the conductor 120 is higher than the height of the top surface of the insulator 130, the present invention is not limited to this. For example, the height of the top surface of the conductor 120 may match the height of the top surface of the insulator 130, or may be lower than the height of the top surface of the insulator 130.
　図７Ａ乃至図７Ｃに示す構成と異なる記憶装置の一例を図８Ａ乃至図８Ｃに示す。図８Ａは、記憶装置の一例を示す平面図である。また、図８Ｂ及び図８Ｃは、当該記憶装置の断面図である。ここで、図８Ｂは、図８ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図８Ｃは、図８ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。なお、図８Ａの平面図では、図の明瞭化のために一部の要素を省いている。 An example of a storage device different from the configuration shown in FIGS. 7A to 7C is shown in FIGS. 8A to 8C. FIG. 8A is a plan view showing an example of a storage device. Further, FIGS. 8B and 8C are cross-sectional views of the storage device. Here, FIG. 8B is a sectional view of a portion shown by a dashed line A1-A2 in FIG. 8A. Further, FIG. 8C is a cross-sectional view of the portion shown by the dashed line A3-A4 in FIG. 8A. Note that in the plan view of FIG. 8A, some elements are omitted for clarity.
　図８Ａ乃至図８Ｃに示す記憶装置は、導電体１２０の形状が、図７Ａ乃至図７Ｃに示す記憶装置と主に異なる。 The memory device shown in FIGS. 8A to 8C differs from the memory device shown in FIGS. 7A to 7C mainly in the shape of the conductor 120.
　図７Ａ乃至図７Ｃに示す記憶装置において、開口部１９０の最大幅を大きくするほど、隣接する導電体１２０の側面間の距離が小さくなる。当該距離が小さいほど、隣接する導電体１２０の分離が困難となる。隣接する導電体１２０が、分離されずに隣接する容量素子１００間で共通して設けられると、容量素子１００間にリーク電流が流れてしまう。 In the storage devices shown in FIGS. 7A to 7C, the larger the maximum width of the opening 190, the smaller the distance between the side surfaces of adjacent conductors 120. The smaller the distance, the more difficult it becomes to separate adjacent conductors 120. If adjacent conductors 120 are provided in common between adjacent capacitive elements 100 without being separated, leakage current will flow between the capacitive elements 100.
　そこで、図８Ｂ及び図８Ｃに示すように、導電体１２０の上面の高さが、絶縁体１３０の上面の高さよりも低い構成にする。これにより、隣接する導電体１２０を確実に分離することができる。したがって、開口部１９０の最大幅を大きくする場合においても、容量素子１００間のリーク電流を抑制できる。 Therefore, as shown in FIGS. 8B and 8C, the height of the top surface of the conductor 120 is configured to be lower than the height of the top surface of the insulator 130. Thereby, adjacent conductors 120 can be reliably separated. Therefore, even when the maximum width of the opening 190 is increased, leakage current between the capacitive elements 100 can be suppressed.
　なお、導電体１２０の上面の高さは、絶縁体１３０の上面の高さよりも低く、導電体１１５の上面の高さ近傍又は導電体１１５の上面の高さと一致することが好ましい。このような構成にすることで、容量素子１００の静電容量の減少を抑制できる。 Note that the height of the top surface of the conductor 120 is preferably lower than the height of the top surface of the insulator 130 and is near the height of the top surface of the conductor 115 or coincides with the height of the top surface of the conductor 115. With such a configuration, a decrease in the capacitance of the capacitive element 100 can be suppressed.
　なお、図８Ａ乃至図８Ｃでは、導電体１２０が酸化物半導体２３０の下面と接する領域を有する構成を示しているが、本発明はこれに限られるものではない。例えば、導電体１２０と酸化物半導体２３０との間に導電体を設けてもよい。 Note that although FIGS. 8A to 8C show a structure in which the conductor 120 has a region in contact with the lower surface of the oxide semiconductor 230, the present invention is not limited to this. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230.
　図９Ａ乃至図９Ｃには、導電体１２０と酸化物半導体２３０との間に導電体１２２が設けられる構成を示している。つまり、図９Ａ乃至図９Ｃに示す記憶装置は、導電体１２２を有する点で、図８Ａ乃至図８Ｃに示す記憶装置と主に異なる。 9A to 9C show a structure in which a conductor 122 is provided between the conductor 120 and the oxide semiconductor 230. That is, the memory devices shown in FIGS. 9A to 9C mainly differ from the memory devices shown in FIGS. 8A to 8C in that they include the conductor 122.
　導電体１２０上に導電体１２２が設けられ、導電体１２２上に酸化物半導体２３０が設けられる。導電体１２２は、導電体１２０の上面の少なくとも一部と接する領域と、酸化物半導体２３０の下面の少なくとも一部と接する領域と、を有する。また、図９Ｂ及び図９Ｃに示すように、導電体１２２は絶縁体１８２に埋め込まれるように設けられることが好ましい。このとき、導電体１２２の上面と絶縁体１８２の上面は、高さが一致する。 A conductor 122 is provided on the conductor 120, and an oxide semiconductor 230 is provided on the conductor 122. The conductor 122 has a region in contact with at least a portion of the upper surface of the conductor 120 and a region in contact with at least a portion of the lower surface of the oxide semiconductor 230. Further, as shown in FIGS. 9B and 9C, the conductor 122 is preferably provided so as to be embedded in the insulator 182. At this time, the top surface of the conductor 122 and the top surface of the insulator 182 have the same height.
　図９Ｂ及び図９Ｃに示すように、断面視における導電体１２２の幅は、開口部１９０の最大幅よりも小さいことが好ましい。このような構成にすることで、隣接する導電体１２２間の距離を大きくでき、隣接する導電体１２２間の寄生容量を抑制できる。 As shown in FIGS. 9B and 9C, the width of the conductor 122 in cross-sectional view is preferably smaller than the maximum width of the opening 190. With such a configuration, the distance between adjacent conductors 122 can be increased, and parasitic capacitance between adjacent conductors 122 can be suppressed.
　さらに、断面視における導電体１２２の幅は、開口部２９０の最大幅と同じ、又は開口部２９０の最大幅よりも大きいことが好ましい。例えば、断面視における導電体１２２の幅を、開口部２９０の最大幅と同じにする場合、導電体１２２を設ける開口部、及び開口部２９０を形成する際に行う異方性エッチングにおいて、同じマスクを用いることができる。これにより、マスク数を減らすことができ、記憶装置の低コスト化を図ることができる。また、例えば、断面視における導電体１２２の幅を、開口部２９０の最大幅よりも大きくする場合、開口部２９０の位置合わせ精度が緩和される。よって、微細なメモリセルを作る上での難易度を下げることが可能となる。 Furthermore, the width of the conductor 122 in cross-sectional view is preferably the same as the maximum width of the opening 290 or larger than the maximum width of the opening 290. For example, if the width of the conductor 122 in a cross-sectional view is the same as the maximum width of the opening 290, the same mask is used in the anisotropic etching performed when forming the opening where the conductor 122 is provided and the opening 290. can be used. Thereby, the number of masks can be reduced, and the cost of the storage device can be reduced. Further, for example, when the width of the conductor 122 in a cross-sectional view is made larger than the maximum width of the opening 290, the alignment accuracy of the opening 290 is relaxed. Therefore, it is possible to reduce the difficulty level in manufacturing fine memory cells.
　導電体１２２は、容量素子１００とトランジスタ２００と電気的に接続してプラグとして機能する領域を有する。また、導電体１２２は、トランジスタ２００のソース電極及びドレイン電極の一方として機能する領域を有する。 The conductor 122 has a region that is electrically connected to the capacitive element 100 and the transistor 200 and functions as a plug. Further, the conductor 122 has a region that functions as one of a source electrode and a drain electrode of the transistor 200.
　上記のような構成にすることで、導電体１２０の上面が十分に平坦化されていない場合においても、容量素子１００上にトランジスタ２００を好適に形成することができる。 With the above configuration, the transistor 200 can be suitably formed on the capacitive element 100 even when the upper surface of the conductor 120 is not sufficiently flattened.
　導電体１２２としては、後述する［導電体］の項目に記載の導電体を、単層または積層で用いることができる。導電体１２２として、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料などを用いることが好ましい。例えば、窒化チタンまたは窒化タンタルなどを用いることができる。また、例えば、窒化チタンの上に窒化タンタルを積層した構造にしてもよい。この場合、窒化チタンが導電体１２０及び絶縁体１８２に接し、窒化タンタルが酸化物半導体２３０に接する。このような構造にすることで、酸化物半導体２３０によって導電体１２２が過剰に酸化されるのを抑制できる。また、絶縁体１８２によって導電体１２２が過剰に酸化されるのを抑制できる。又は、導電体１２２として、例えば、窒化チタンの上にタングステンを積層した構造にしてもよい。 As the conductor 122, the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner. As the conductor 122, it is preferable to use a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or the like. For example, titanium nitride or tantalum nitride can be used. Further, for example, a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, titanium nitride is in contact with the conductor 120 and the insulator 182, and tantalum nitride is in contact with the oxide semiconductor 230. With such a structure, excessive oxidation of the conductor 122 by the oxide semiconductor 230 can be suppressed. Further, the insulator 182 can prevent the conductor 122 from being excessively oxidized. Alternatively, the conductor 122 may have a structure in which tungsten is laminated on titanium nitride, for example.
　絶縁体１８２は、層間膜として機能するため、比誘電率が低いことが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体１８２としては、絶縁体１８０に適用可能な絶縁体を用いることができる。 Since the insulator 182 functions as an interlayer film, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 182, an insulator applicable to the insulator 180 can be used.
　図９Ｂ及び図９Ｃでは、導電体１２０及び導電体１２２のそれぞれを単層で示したが、導電体１２０及び導電体１２２のそれぞれは積層構造を有してもよい。例えば、図１０Ａ乃至図１０Ｃに示すように、導電体１２０は２層積層構造を有し、導電体１２２は２層積層構造を有してもよい。 Although each of the conductor 120 and the conductor 122 is shown as a single layer in FIGS. 9B and 9C, each of the conductor 120 and the conductor 122 may have a laminated structure. For example, as shown in FIGS. 10A to 10C, the conductor 120 may have a two-layer stacked structure, and the conductor 122 may have a two-layer stacked structure.
　上述したように、導電体１２０及び導電体１２２のそれぞれとして、例えば、窒化チタンの上に窒化タンタルを積層した構造にしてもよい。又は、例えば、窒化チタンの上にタングステンを積層した構造にしてもよい。 As described above, each of the conductor 120 and the conductor 122 may have a structure in which tantalum nitride is laminated on titanium nitride, for example. Alternatively, for example, a structure in which tungsten is laminated on titanium nitride may be used.
　なお、図１０Ａ乃至図１０Ｃに示すように、導電体１２０上に導電体１２１を設ける構成にしてもよい。導電体１２１は、導電体１２０の上面の一部と接する領域と、絶縁体１３０の側面の一部と接する領域と、を有する。また、導電体１２１は、絶縁体１３０を介して、導電体１１５と対向する領域を有する。このとき、導電体１２０及び導電体１２１は、容量素子１００の一対の電極の一方として機能する。つまり、図１０Ａ乃至図１０Ｃに示す構成において、容量素子１００は、導電体１１５、絶縁体１３０、及び導電体１２０に加えて、導電体１２１を有する。 Note that, as shown in FIGS. 10A to 10C, a configuration may be adopted in which a conductor 121 is provided on a conductor 120. The conductor 121 has a region in contact with a part of the upper surface of the conductor 120 and a region in contact with a part of the side surface of the insulator 130. Further, the conductor 121 has a region facing the conductor 115 with the insulator 130 in between. At this time, the conductor 120 and the conductor 121 function as one of the pair of electrodes of the capacitive element 100. That is, in the configuration shown in FIGS. 10A to 10C, the capacitive element 100 includes a conductor 121 in addition to the conductor 115, the insulator 130, and the conductor 120.
　上記の構成にすることで、導電体１２０の上面の高さが導電体１１５の上面の高さよりも低い場合であっても、容量素子１００の静電容量を十分に確保できる。 With the above configuration, even if the height of the top surface of the conductor 120 is lower than the height of the top surface of the conductor 115, a sufficient electrostatic capacity of the capacitive element 100 can be ensured.
　図９Ａ乃至図９Ｃでは、導電体１２０と酸化物半導体２３０の間に導電体１２２が設けられる構成を示しているが、本発明はこれに限られるものではない。例えば、導電体１２２と酸化物半導体２３０との間にさらに導電体を設けてもよい。 Although FIGS. 9A to 9C show a configuration in which the conductor 122 is provided between the conductor 120 and the oxide semiconductor 230, the present invention is not limited to this. For example, a conductor may be further provided between the conductor 122 and the oxide semiconductor 230.
　図１１Ａ乃至図１１Ｃには、導電体１２２と酸化物半導体２３０との間に導電体１２５が設けられる構成を示している。つまり、図１１Ａ乃至図１１Ｃに示す記憶装置は、導電体１２５を有する点で、図９Ａ乃至図９Ｃに示す記憶装置と主に異なる。また、導電体１２２及び導電体１２５を有する点で、図８Ａ乃至図８Ｃに示す記憶装置と主に異なる。 FIGS. 11A to 11C show a structure in which a conductor 125 is provided between the conductor 122 and the oxide semiconductor 230. In other words, the memory devices shown in FIGS. 11A to 11C mainly differ from the memory devices shown in FIGS. 9A to 9C in that they include the conductor 125. Further, the main difference from the memory device shown in FIGS. 8A to 8C is that it includes a conductor 122 and a conductor 125.
　導電体１２２上に導電体１２５が設けられ、導電体１２５上に酸化物半導体２３０が設けられる。導電体１２５は、導電体１２２の上面と接する領域と、酸化物半導体２３０の下面の少なくとも一部と接する領域を有する。 A conductor 125 is provided on the conductor 122, and an oxide semiconductor 230 is provided on the conductor 125. The conductor 125 has a region in contact with the upper surface of the conductor 122 and a region in contact with at least a portion of the lower surface of the oxide semiconductor 230.
　導電体１２２は、容量素子１００とトランジスタ２００と電気的に接続してプラグとして機能する領域を有する。導電体１２５は、トランジスタ２００のソース電極及びドレイン電極の一方として機能する領域を有する。導電体１２５に適用可能な材料等については、後述する。 The conductor 122 has a region that is electrically connected to the capacitive element 100 and the transistor 200 and functions as a plug. The conductor 125 has a region that functions as one of a source electrode and a drain electrode of the transistor 200. Materials applicable to the conductor 125 will be described later.
　また、図１１Ｂ及び図１１Ｃに示すように、断面視における導電体１２５の幅は導電体１２２の幅よりも大きいことが好ましい。また、断面視における導電体１２５の幅は、開口部２９０の最大幅よりも大きいことが好ましい。このような構成にすることで、開口部２９０の位置合わせ精度が緩和される。よって、微細なメモリセルを作る上での難易度を下げることが可能となる。 Furthermore, as shown in FIGS. 11B and 11C, the width of the conductor 125 in cross-sectional view is preferably larger than the width of the conductor 122. Further, the width of the conductor 125 in cross-sectional view is preferably larger than the maximum width of the opening 290. With such a configuration, the alignment accuracy of the opening 290 is relaxed. Therefore, it is possible to reduce the difficulty level in manufacturing fine memory cells.
　なお、図１Ｂ及び図１Ｃでは導電体１２０は、絶縁体１３０を介して導電体１１５の内側に位置しているが、本発明はこれに限られるものではない。例えば、導電体１２０は、絶縁体１３０を介して導電体１１５の外側に位置してもよい。 Note that in FIGS. 1B and 1C, the conductor 120 is located inside the conductor 115 via the insulator 130, but the present invention is not limited to this. For example, the conductor 120 may be located outside the conductor 115 with the insulator 130 in between.
　例えば、図１２Ａ及び図１２Ｂに示すように、絶縁体１３０は、導電体１１５が有する凹部の内側と接する領域、及び導電体１１５の上面と接する領域に加えて、導電体１１５の外側の側面側に位置する領域を有する。 For example, as shown in FIGS. 12A and 12B, the insulator 130 is disposed on the outer side surface of the conductor 115 in addition to a region in contact with the inside of the recess of the conductor 115 and a region in contact with the upper surface of the conductor 115. It has an area located in .
　導電体１２０は、絶縁体１３０を介して、導電体１１５が有する凹部を埋め込むように設けられている。さらに、導電体１２０は、絶縁体１３０を介して、導電体１１５の外側の側面の一部と対向する領域を有する。 The conductor 120 is provided so as to fill the recessed portion of the conductor 115 with the insulator 130 in between. Furthermore, the conductor 120 has a region that faces a part of the outer side surface of the conductor 115 with the insulator 130 in between.
　上記のような構成にすることで、単位面積当たりの静電容量をより大きくすることができる。 With the above configuration, the capacitance per unit area can be increased.
　なお、図１２Ａ及び図１２Ｂに示すように、導電体１１５の外側の側面と、絶縁体１３０及び絶縁体１８０との間に、絶縁体１３５を設けてもよい。 Note that as shown in FIGS. 12A and 12B, an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulators 130 and 180.
　また、導電体１２０、及び絶縁体１３０上に絶縁体１８２を設けてもよい。また、絶縁体１８２は、導電体１２０の上面が露出するように平坦化処理を行うことが好ましい。絶縁体１８２の平坦化処理を行うことで、容量素子１００上にトランジスタ２００を好適に形成することができる。 Furthermore, an insulator 182 may be provided on the conductor 120 and the insulator 130. Further, it is preferable that the insulator 182 be subjected to a planarization treatment so that the upper surface of the conductor 120 is exposed. By performing planarization treatment on the insulator 182, the transistor 200 can be suitably formed over the capacitor 100.
　絶縁体１８２は、層間膜として機能するため、比誘電率が低いことが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体１８２としては、絶縁体１８０に適用可能な絶縁体を用いることができる。 Since the insulator 182 functions as an interlayer film, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 182, an insulator applicable to the insulator 180 can be used.
　なお、図１２Ａ及び図１２Ｂに示すように、導電体１１５の内側及び外側に面して導電体１２０が設けられる構成にすることで、メモリセルとして十分な静電容量を確保できる場合、絶縁体１８０ｂを設けない構成にしてもよい。 Note that, as shown in FIGS. 12A and 12B, if sufficient capacitance can be secured as a memory cell by providing a configuration in which the conductor 120 is provided facing inside and outside of the conductor 115, the insulator A configuration may be adopted in which 180b is not provided.
　図１２Ｃ及び図１２Ｄに示す記憶装置は、絶縁体１８０ｂを設けない点で、図１２Ａ及び図１２Ｂに示す記憶装置とは異なる。絶縁体１８０ｂを設けないことで、記憶装置の作製工程を簡略化することができる。 The storage device shown in FIGS. 12C and 12D differs from the storage device shown in FIGS. 12A and 12B in that an insulator 180b is not provided. By not providing the insulator 180b, the manufacturing process of the memory device can be simplified.
［トランジスタ２００］
　図１Ａ乃至図１Ｃに示すように、トランジスタ２００は、導電体１２０と、絶縁体２８０上の導電体２４０と、開口部２９０において露出している導電体１２０の上面、開口部２９０における絶縁体２８０の側面、開口部２９０における導電体２４０の側面、及び導電体２４０の上面の少なくとも一部に接して設けられた酸化物半導体２３０と、酸化物半導体２３０の上面に接して設けられた絶縁体２５０と、絶縁体２５０の上面に接して設けられた導電体２６０と、を有する構成にすることができる。 [Transistor 200]
As shown in FIGS. 1A to 1C, the transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an upper surface of the conductor 120 exposed in an opening 290, and an insulator 280 in the opening 290. , the side surface of the conductor 240 in the opening 290, and the oxide semiconductor 230 provided in contact with at least a portion of the top surface of the conductor 240; and the insulator 250 provided in contact with the top surface of the oxide semiconductor 230. and a conductor 260 provided in contact with the upper surface of the insulator 250.
　トランジスタ２００の構成要素の少なくとも一部は、開口部２９０に配置される。ここで、開口部２９０の底部は、導電体１２０の上面であり、開口部２９０の側壁は、絶縁体２８０の側面、及び導電体２４０の側面である。 At least some of the components of the transistor 200 are arranged in the opening 290. Here, the bottom of the opening 290 is the top surface of the conductor 120, and the sidewalls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.
　開口部２９０の側壁は、導電体１２０の上面に対して垂直であることが好ましい。このとき、開口部２９０は円筒形状を有する。このような構成にすることで、記憶装置の微細化または高集積化を図ることができる。 The side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. At this time, the opening 290 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
　また、本実施の形態では、平面視において開口部２９０が円形である例について示したが、本発明はこれに限られるものではない。例えば、平面視において開口部２９０が、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。このとき、開口部２９０の最大幅は、開口部２９０の最上部の形状に合わせて適宜算出するとよい。例えば、平面視において開口部が四角形である場合、開口部２９０の最大幅は、開口部２９０の最上部の対角線の長さとするとよい。 Further, in this embodiment, an example is shown in which the opening 290 is circular in plan view, but the present invention is not limited to this. For example, in plan view, the opening 290 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners. At this time, the maximum width of the opening 290 may be calculated as appropriate depending on the shape of the top of the opening 290. For example, when the opening is square in plan view, the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.
　酸化物半導体２３０、絶縁体２５０、及び導電体２６０の開口部２９０に配置される部分は、開口部２９０の形状を反映して設けられる。よって、開口部２９０の底部及び側壁を覆うように酸化物半導体２３０が設けられ、酸化物半導体２３０を覆うように絶縁体２５０が設けられ、開口部２９０の形状を反映した絶縁体２５０の凹部を埋め込むように導電体２６０が設けられる。 The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided to cover the oxide semiconductor 230, and a recessed portion of the insulator 250 that reflects the shape of the opening 290 is formed. A conductor 260 is provided so as to be buried therein.
　ここで、図１Ｂにおける酸化物半導体２３０及びその近傍の拡大図を図１３Ａに示す。図１３Ｂは、図１３ＡにＢ１−Ｂ２の一点鎖線で示す部位の断面図であり、導電体２４０を含む、ＸＹ平面における断面図でもある。 Here, FIG. 13A shows an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 1B. FIG. 13B is a cross-sectional view of the portion shown by the dashed line B1-B2 in FIG. 13A, and is also a cross-sectional view in the XY plane including the conductor 240.
　図１３Ａに示すように、酸化物半導体２３０は、領域２３０ｉと、領域２３０ｎａと、領域２３０ｎｂと、を有する。 As shown in FIG. 13A, the oxide semiconductor 230 includes a region 230i, a region 230na, and a region 230nb.
　領域２３０ｎａは、酸化物半導体２３０の導電体１２０と接する領域である。領域２３０ｎａの少なくとも一部は、トランジスタ２００のソース領域及びドレイン領域の一方として機能する。領域２３０ｎｂは、酸化物半導体２３０の導電体２４０と接する領域である。領域２３０ｎｂの少なくとも一部は、トランジスタ２００のソース領域及びドレイン領域の他方として機能する。図１３Ｂに示すように、導電体２４０は酸化物半導体２３０の外周全体に接する。よって、トランジスタ２００のソース領域及びドレイン領域の他方は、酸化物半導体２３０の、導電体２４０と同じ層に形成される部分の外周全体に形成されうる。 The region 230na is a region of the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na functions as one of a source region and a drain region of the transistor 200. The region 230nb is a region of the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb functions as the other of the source region and the drain region of the transistor 200. As shown in FIG. 13B, the conductor 240 is in contact with the entire outer periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 can be formed over the entire outer periphery of a portion of the oxide semiconductor 230 that is formed in the same layer as the conductor 240.
　領域２３０ｉの少なくとも一部は、酸化物半導体２３０の、領域２３０ｎａと領域２３０ｎｂの間に位置する。領域２３０ｉの少なくとも一部が、トランジスタ２００のチャネル形成領域として機能する。つまり、トランジスタ２００のチャネル形成領域は、酸化物半導体２３０の、導電体１２０と導電体２４０の間の領域に位置する。また、トランジスタ２００のチャネル形成領域は、酸化物半導体２３０の、絶縁体２８０と接する領域またはその近傍の領域に位置する、ということもできる。 At least a portion of the region 230i is located between the region 230na and the region 230nb of the oxide semiconductor 230. At least a portion of the region 230i functions as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or a region near the region.
　半導体層に酸化物半導体を用いるトランジスタのチャネル形成領域は、ソース領域及びドレイン領域よりも、酸素欠損が少ない、または水素、窒素、金属元素などの不純物濃度が低いことが好ましい。また、酸素欠損近傍の水素が、酸素欠損に水素が入った欠陥（以下、ＶＯＨと呼ぶ場合がある）を形成し、キャリアとなる電子を生成する場合があるため、チャネル形成領域においては、ＶＯＨも低減されていることが好ましい。このように、トランジスタのチャネル形成領域は、キャリア濃度が低い高抵抗領域である。よってトランジスタのチャネル形成領域は、ｉ型（真性）または実質的にｉ型であるということができる。 A channel formation region of a transistor using an oxide semiconductor for a semiconductor layer preferably has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or a metal element than the source and drain regions. In addition, hydrogen near oxygen vacancies may form defects in which hydrogen is present in oxygen vacancies (hereinafter sometimes referred to as V O H), and generate electrons that become carriers. , V OH are also preferably reduced. In this way, the channel formation region of the transistor is a high resistance region with low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.
　また、半導体層に酸化物半導体を用いるトランジスタのソース領域及びドレイン領域は、チャネル形成領域よりも、酸素欠損が多い、ＶＯＨが多い、または水素、窒素、金属元素などの不純物濃度が高い、ことでキャリア濃度が増加し、低抵抗化した領域である。すなわち、トランジスタのソース領域及びドレイン領域は、チャネル形成領域と比較して、キャリア濃度が高く、低抵抗なｎ型の領域である。 In addition, the source region and drain region of a transistor using an oxide semiconductor for the semiconductor layer have more oxygen vacancies, more V O H, or a higher concentration of impurities such as hydrogen, nitrogen, and metal elements than the channel formation region. This is a region where the carrier concentration increases and the resistance decreases. That is, the source region and drain region of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.
　詳細は後述するが、絶縁体２８０として加熱により脱離する酸素（以下、過剰酸素と呼ぶ場合がある）を含む絶縁体を用いる場合、熱処理を行うことで、酸化物半導体２３０の絶縁体２８０と接する領域に、絶縁体２８０から酸素を供給し、当該領域の酸素欠損及びＶＯＨの低減を図ることができる。また、酸化物半導体２３０の絶縁体２５０と接する領域に、絶縁体２８０に含まれる酸素を絶縁体２５０を介して供給し、当該領域の酸素欠損及びＶＯＨの低減を図ることができる。よって、図１３Ａ及び図１３Ｂに示すように、領域２３０ｎａ及び領域２３０ｎｂよりも酸素欠損が少ない領域２３０ｉは、絶縁体２８０近傍及び絶縁体２５０近傍に位置する。 Although the details will be described later, when an insulator containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen) is used as the insulator 280, the insulator 280 of the oxide semiconductor 230 can be removed by heat treatment. By supplying oxygen from the insulator 280 to the contacting region, it is possible to reduce oxygen vacancies and V O H in the region. Furthermore, oxygen contained in the insulator 280 can be supplied to a region of the oxide semiconductor 230 in contact with the insulator 250 through the insulator 250, thereby reducing oxygen vacancies and V OH in the region. Therefore, as shown in FIGS. 13A and 13B, the region 230i, which has fewer oxygen vacancies than the region 230na and the region 230nb, is located near the insulator 280 and the insulator 250.
　酸化物半導体２３０と導電体１２０とが接することで、金属化合物、または酸素欠損が形成され、酸化物半導体２３０の領域２３０ｎａが低抵抗化する。導電体１２０と接する酸化物半導体２３０が低抵抗化することで、酸化物半導体２３０と導電体１２０との接触抵抗を低減できる。同様に、酸化物半導体２３０と導電体２４０とが接することで、酸化物半導体２３０の領域２３０ｎｂが低抵抗化する。したがって、酸化物半導体２３０と導電体２４０との接触抵抗を低減できる。 When the oxide semiconductor 230 and the conductor 120 come into contact, a metal compound or an oxygen vacancy is formed, and the resistance of the region 230na of the oxide semiconductor 230 is reduced. By reducing the resistance of the oxide semiconductor 230 in contact with the conductor 120, the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced. Similarly, since the oxide semiconductor 230 and the conductor 240 are in contact with each other, the resistance of the region 230nb of the oxide semiconductor 230 is reduced. Therefore, contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
　なお、領域２３０ｎａ及び領域２３０ｎｂの低抵抗化の度合い、及び、絶縁体２５０を介した絶縁体２８０からの酸素供給量によって、領域２３０ｎａ及び領域２３０ｎｂの範囲は変化する。例えば、領域２３０ｎａ及び領域２３０ｎｂの低抵抗化の度合いが大きい、又は、絶縁体２５０を介した絶縁体２８０からの酸素供給量が少ない場合、領域２３０ｎａ及び領域２３０ｎｂが、絶縁体２５０との界面まで伸長する場合がある。 Note that the ranges of the region 230na and the region 230nb change depending on the degree of resistance reduction in the region 230na and the region 230nb and the amount of oxygen supplied from the insulator 280 via the insulator 250. For example, when the degree of resistance reduction in the region 230na and the region 230nb is large, or when the amount of oxygen supplied from the insulator 280 via the insulator 250 is small, the region 230na and the region 230nb reach the interface with the insulator 250. It may expand.
　トランジスタ２００のチャネル長は、ソースとドレインの間の距離となる。つまり、トランジスタ２００のチャネル長は、導電体１２０上の絶縁体２８０の厚さによって決定される、ということができる。図１３Ａは、トランジスタ２００のチャネル長Ｌを破線の両矢印で示している。チャネル長Ｌは、断面視において、酸化物半導体２３０と導電体１２０が接する領域の端部と、酸化物半導体２３０と導電体２４０が接する領域の端部との距離となる。つまり、チャネル長Ｌは、断面視における絶縁体２８０の開口部２９０側の側面の長さに相当する。 The channel length of the transistor 200 is the distance between the source and drain. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120. FIG. 13A shows the channel length L of the transistor 200 with a dashed double-headed arrow. The channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact with each other and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact in a cross-sectional view. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in cross-sectional view.
　プレーナ型のトランジスタでは、チャネル長がフォトリソグラフィの露光限界で設定されていたが、本発明においては、絶縁体２８０の膜厚でチャネル長を設定することができる。よって、トランジスタ２００のチャネル長を、フォトリソグラフィの露光限界以下の非常に微細な構造（例えば、６０ｎｍ以下、５０ｎｍ以下、４０ｎｍ以下、３０ｎｍ以下、２０ｎｍ以下、または１０ｎｍ以下であって、１ｎｍ以上、または５ｎｍ以上）にすることができる。これにより、トランジスタ２００のオン電流が大きくなり、周波数特性の向上を図ることができる。よって、メモリセル１５０の読み出し速度及び書き込み速度を向上させることができるため、動作速度が速い記憶装置を提供できる。 In a planar transistor, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the thickness of the insulator 280. Therefore, the channel length of the transistor 200 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell 150 can be improved, so that a memory device with high operating speed can be provided.
　さらに、上記のように、開口部２９０における酸化物半導体２３０に、チャネル形成領域、ソース領域、及びドレイン領域を形成することができる。これにより、チャネル形成領域、ソース領域、及びドレイン領域が、ＸＹ平面上に別々に設けられていた、プレーナ型のトランジスタと比較して、トランジスタ２００の占有面積を低減できる。これにより、記憶装置を高集積化することができるため、単位面積当たりの記憶容量を大きくすることができる。 Further, as described above, a channel formation region, a source region, and a drain region can be formed in the oxide semiconductor 230 in the opening 290. As a result, the area occupied by the transistor 200 can be reduced compared to a planar transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane. This allows the storage device to be highly integrated, thereby increasing the storage capacity per unit area.
　また、酸化物半導体２３０のチャネル形成領域を含むＸＹ平面においても、図１３Ｂと同様に、酸化物半導体２３０、絶縁体２５０、及び導電体２６０は、同心円状に設けられる。よって、中心に設けられた導電体２６０の側面は、絶縁体２５０を介して、酸化物半導体２３０の側面と対向する。つまり、平面視において、酸化物半導体２３０の周全体がチャネル形成領域になる。このとき、例えば、酸化物半導体２３０の外周の長さによって、トランジスタ２００のチャネル幅が決まる。つまり、トランジスタ２００のチャネル幅は、開口部２９０の最大幅（平面視において開口部２９０が円形である場合は最大径）の大きさによって決定される、ということができる。図１３Ａ及び図１３Ｂは、開口部２９０の最大幅Ｄｔを二点鎖線の両矢印で示している。図１３Ｂは、トランジスタ２００のチャネル幅Ｗを一点鎖線の両矢印で示している。開口部２９０の最大幅Ｄｔの大きさを大きくすることで、単位面積当たりのチャネル幅を大きくし、オン電流を大きくすることができる。 Furthermore, in the XY plane including the channel formation region of the oxide semiconductor 230, the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically, similarly to FIG. 13B. Therefore, the side surface of the conductor 260 provided at the center faces the side surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. That is, in plan view, the entire circumference of the oxide semiconductor 230 becomes a channel formation region. At this time, for example, the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. In other words, the channel width of the transistor 200 can be said to be determined by the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular in plan view). In FIGS. 13A and 13B, the maximum width Dt of the opening 290 is indicated by a two-dot chain double-headed arrow. In FIG. 13B, the channel width W of the transistor 200 is indicated by a dot-dash double-headed arrow. By increasing the maximum width Dt of the opening 290, the channel width per unit area can be increased and the on-state current can be increased.
　フォトリソグラフィ法を用いて開口部２９０を形成する場合、開口部２９０の最大幅Ｄｔはフォトリソグラフィの露光限界で設定される。また、開口部２９０の最大幅Ｄｔは、開口部２９０に設ける、酸化物半導体２３０、絶縁体２５０、及び導電体２６０それぞれの膜厚によって設定される。開口部２９０の最大幅Ｄｔは、例えば、１ｎｍ以上、５ｎｍ以上、又は１０ｎｍ以上であって、１００ｎｍ以下、６０ｎｍ以下、５０ｎｍ以下、４０ｎｍ以下、３０ｎｍ以下、又は２０ｎｍ以下が好ましい。なお、平面視において開口部２９０が円形である場合、開口部２９０の最大幅Ｄｔは開口部２９０の直径に相当し、チャネル幅Ｗは“Ｄ×π”と算出することができる。 When forming the opening 290 using a photolithography method, the maximum width Dt of the opening 290 is set by the exposure limit of the photolithography. Further, the maximum width Dt of the opening 290 is set by the respective film thicknesses of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width Dt of the opening 290 is, for example, 1 nm or more, 5 nm or more, or 10 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less. Note that when the opening 290 is circular in plan view, the maximum width Dt of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D×π".
　また、本発明の一態様の記憶装置においては、トランジスタ２００のチャネル長Ｌは、少なくともトランジスタ２００のチャネル幅Ｗよりも小さいことが好ましい。本発明の一態様に係るトランジスタ２００のチャネル長Ｌは、トランジスタ２００のチャネル幅Ｗに対し、０．１倍以上０．９９倍以下、好ましくは０．５倍以上０．８倍以下である。このような構成にすることで、良好な電気特性及び高い信頼性を有するトランジスタを実現できる。 Further, in the memory device of one embodiment of the present invention, the channel length L of the transistor 200 is preferably smaller than at least the channel width W of the transistor 200. The channel length L of the transistor 200 according to one embodiment of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W of the transistor 200. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
　また、平面視で円形になるように開口部２９０を形成することで、酸化物半導体２３０、絶縁体２５０、及び導電体２６０は、同心円状に設けられる。これにより、導電体２６０と酸化物半導体２３０の距離が概略均一になるため、酸化物半導体２３０にゲート電界を概略均一に印加することができる。 Furthermore, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically. Accordingly, the distance between the conductor 260 and the oxide semiconductor 230 becomes approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.
　開口部２９０における導電体２４０と酸化物半導体２３０の界面から、導電体２４０のＹ方向の側端部までの距離は小さいことが好ましい。当該距離は、１ｎｍ以上、１．５ｎｍ以上、又は２ｎｍ以上であって、２０ｎｍ以下、１０ｎｍ以下、５ｎｍ以下、又は３ｎｍ以下であることが好ましい。このような構成にすることで、導電体２４０のＹ方向の幅を小さくすることができ、導電体２４０が配置される間隔を小さくすることができる。したがって、記憶装置の微細化または高集積化を図ることができる。 The distance from the interface between the conductor 240 and the oxide semiconductor 230 in the opening 290 to the side end of the conductor 240 in the Y direction is preferably small. The distance is preferably 1 nm or more, 1.5 nm or more, or 2 nm or more, and 20 nm or less, 10 nm or less, 5 nm or less, or 3 nm or less. With such a configuration, the width of the conductor 240 in the Y direction can be reduced, and the intervals at which the conductors 240 are arranged can be reduced. Therefore, the storage device can be miniaturized or highly integrated.
　なお、図１Ｂ及び図１Ｃでは、開口部２９０の側壁が導電体１１０の上面に対して垂直となるように、開口部２９０を設けているが、本発明はこれに限られるものではない。例えば、開口部２９０の側壁は、テーパー形状になってもよい。 Note that in FIGS. 1B and 1C, the opening 290 is provided so that the side wall of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this. For example, the sidewalls of opening 290 may be tapered.
　図１４Ａ及び図１４Ｂに示す記憶装置は、開口部２９０の側壁がテーパー形状である構成を有する。なお、図１４Ａ及び図１４Ｂに示す記憶装置の平面図は、図１Ａを参照できる。 The storage device shown in FIGS. 14A and 14B has a configuration in which the side wall of the opening 290 is tapered. Note that FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 14A and 14B.
　開口部２９０の側壁をテーパー形状にすることで、酸化物半導体２３０、又は絶縁体２５０などの被覆性が向上し、鬆などの欠陥を低減できる。例えば、開口部２９０における絶縁体２８０の側面と、導電体１２０の上面とがなす角度（図１４Ａに示す角度θ１）は、４５度以上であって、９０度未満であることが好ましい。または、４５度以上であって、７５度以下であることが好ましい。または、４５度以上であって、６５度以下であることが好ましい。 By tapering the sidewall of the opening 290, the coverage of the oxide semiconductor 230, the insulator 250, etc. can be improved, and defects such as holes can be reduced. For example, the angle between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 (angle θ1 shown in FIG. 14A) is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
　なお、本明細書等において、テーパー形状とは、構造の側面の少なくとも一部が、基板面または被形成面に対して傾斜して設けられている形状のことを指す。例えば、傾斜した側面と基板面とがなす角（以下、テーパー角と呼ぶ場合がある）が９０度未満である領域を有する。なお、構造の側面及び基板面は、必ずしも完全に平坦である必要はなく、微細な曲率を有する略平面状、または微細な凹凸を有する略平面状であってもよい。 Note that in this specification and the like, a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, there is a region where the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as a taper angle) is less than 90 degrees. Note that the side surfaces of the structure and the substrate surface do not necessarily have to be completely flat, and may be substantially planar with minute curvatures or substantially planar with minute irregularities.
　図１４Ａ及び図１４Ｂに示す開口部２９０の形状は、円錐台形状である。この場合、平面視において開口部２９０は円形であり、断面視において開口部２９０は台形になる。また、円錐台形状の上底面（例えば、導電体２４０に設けられた開口部）の面積は、円錐台形状の下底面（開口部２９０において露出している導電体１２０の上面）の面積よりも大きい。このとき、開口部２９０の最大径は、円錐台形状の上底面をもとに算出するとよい。 The shape of the opening 290 shown in FIGS. 14A and 14B is a truncated cone shape. In this case, the opening 290 is circular in plan view, and trapezoidal in cross-section. Further, the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big. At this time, the maximum diameter of the opening 290 may be calculated based on the upper base surface of the truncated cone shape.
　開口部２９０の側壁がテーパー形状である場合、絶縁体２８０の膜厚と、開口部２９０における絶縁体２８０の側面と導電体１２０の上面とがなす角度θ１でチャネル長を設定することができる。また、酸化物半導体２３０の外周の長さは、例えば、導電体２４０と対向する領域、又は絶縁体２８０の膜厚の半分の位置で求めればよい。なお、必要に応じて、開口部２９０の任意の位置の周の長さを、トランジスタ２００のチャネル幅としてもよい。例えば、開口部２９０の最下部の周の長さをチャネル幅としてもよいし、開口部２９０の最上部の周の長さをチャネル幅としてもよい。 When the side wall of the opening 290 is tapered, the channel length can be set by the thickness of the insulator 280 and the angle θ1 between the side surface of the insulator 280 and the top surface of the conductor 120 in the opening 290. Further, the length of the outer periphery of the oxide semiconductor 230 may be determined, for example, at a region facing the conductor 240 or at a position half the thickness of the insulator 280. Note that the length of the circumference at any position of the opening 290 may be used as the channel width of the transistor 200, if necessary. For example, the length of the circumference at the bottom of the opening 290 may be set as the channel width, or the length of the circumference at the top of the opening 290 may be set as the channel width.
　図１４Ａ及び図１４Ｂでは、開口部２９０における導電体２４０の側面と、開口部２９０における絶縁体２８０の側面とが一致する構成を示しているが、本発明はこれに限られない。例えば、開口部２９０における導電体２４０の側面と、開口部２９０における絶縁体２８０の側面とが不連続になってもよい。また、開口部２９０における導電体２４０の側面の傾きと、開口部２９０における絶縁体２８０の側面の傾きとが互いに異なってもよい。また例えば、開口部２９０における導電体２４０の側面と、導電体１２０の上面とがなす角度は、角度θ１よりも小さいことが好ましい。このような構成にすることで、開口部２９０における導電体２４０の側面への、酸化物半導体２３０の被覆性が向上し、鬆などの欠陥を低減できる。 Although FIGS. 14A and 14B show a configuration in which the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 match, the present invention is not limited to this. For example, the side surface of the conductor 240 at the opening 290 and the side surface of the insulator 280 at the opening 290 may be discontinuous. Furthermore, the slope of the side surface of the conductor 240 at the opening 290 and the slope of the side surface of the insulator 280 at the opening 290 may be different from each other. Further, for example, the angle between the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 120 is preferably smaller than the angle θ1. With this structure, the coverage of the oxide semiconductor 230 on the side surface of the conductor 240 in the opening 290 is improved, and defects such as holes can be reduced.
　図１４Ａ及び図１４Ｂに示すように、開口部２９０に位置する導電体２６０の底部は、平坦な領域を有する。なお、開口部２９０の最大幅（平面視において開口部２９０が円形である場合は最大径）の大きさ、絶縁体２８０の膜厚（開口部２９０の深さに相当）、酸化物半導体２３０の膜厚、及び絶縁体２５０の膜厚などによっては、開口部２９０に位置する導電体２６０の底部は平坦な領域を有さない場合がある。例えば、図１４Ｃ及び図１４Ｄに示すように、開口部２９０に位置する導電体２６０の底部の形状は、針状となることがある。なお、図１４Ｃ及び図１４Ｄに示す記憶装置の平面図は、図１Ａを参照できる。 As shown in FIGS. 14A and 14B, the bottom of the conductor 260 located in the opening 290 has a flat region. Note that the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular in plan view), the thickness of the insulator 280 (corresponding to the depth of the opening 290), and the thickness of the oxide semiconductor 230 Depending on the film thickness and the film thickness of the insulator 250, the bottom of the conductor 260 located in the opening 290 may not have a flat area. For example, as shown in FIGS. 14C and 14D, the bottom of the conductor 260 located in the opening 290 may have a needle-like shape. Note that FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 14C and 14D.
　ここで、針状とは、先端になる（開口部２９０に位置する導電体２６０の底部に近づく）ほど細くなる形状を指す。なお、針状の先端は、鋭角であってもよいし、下に凸の曲面形状であってもよい。なお、針状のうち、先端が鋭角である形状を、Ｖ字形状と呼んでもよい。 Here, the term acicular refers to a shape that becomes thinner toward the tip (closer to the bottom of the conductor 260 located in the opening 290). Note that the needle-like tip may have an acute angle or may have a downwardly convex curved shape. Note that among the needle shapes, a shape having an acute angle at the tip may be referred to as a V-shape.
　開口部２９０に位置する導電体２６０のうち、絶縁体２５０を介して酸化物半導体２３０と対向する領域はゲート電極として機能する。よって、開口部２９０を埋め込み、底部の形状が針状である導電体２６０を、針状ゲートと呼称してもよい。また、図１４Ａ及び図１４Ｂに示すように、導電体２６０の底部が平坦な領域を有する形状であっても、針状ゲートと呼称してもよい場合がある。 A region of the conductor 260 located in the opening 290 that faces the oxide semiconductor 230 with the insulator 250 in between functions as a gate electrode. Therefore, the conductor 260 that fills the opening 290 and has a needle-like bottom shape may be referred to as a needle-shaped gate. Further, as shown in FIGS. 14A and 14B, even if the conductor 260 has a flat bottom region, it may be called a needle-shaped gate.
　図１Ｂ及び図１Ｃでは、開口部１９０の側壁が導電体１１０の上面に対して垂直となるように、開口部１９０を設けているが、本発明はこれに限られるものではない。例えば、開口部２９０と同様に、開口部１９０の側壁は、テーパー形状になってもよいし、逆テーパー形状になってもよい。 In FIGS. 1B and 1C, the opening 190 is provided so that the side wall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this. For example, similar to opening 290, the sidewall of opening 190 may be tapered or reverse tapered.
　開口部１９０の側壁をテーパー形状にすることで、導電体１１５、又は絶縁体１３０などの被覆性が向上し、鬆などの欠陥を低減できる。例えば、開口部１９０における絶縁体１８０の側面と、導電体１１０の上面とがなす角度（図１４Ａに示す角度θ２）は、４５度以上であって、９０度未満であることが好ましい。または、４５度以上であって、７５度以下であることが好ましい。または、４５度以上であって、６５度以下であることが好ましい。 By tapering the side wall of the opening 190, the coverage of the conductor 115 or the insulator 130 is improved, and defects such as holes can be reduced. For example, the angle between the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 (angle θ2 shown in FIG. 14A) is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
　図１４Ａ及び図１４Ｂに示すように、開口部１９０に位置する導電体１２０の底部は、平坦な領域を有する。なお、開口部１９０の最大幅（平面視において開口部１９０が円形である場合は最大径）の大きさ、絶縁体１８０の膜厚（開口部１９０の深さに相当）、導電体１１５の膜厚、及び絶縁体１３０の膜厚などによっては、開口部１９０に位置する導電体１２０の底部は平坦な領域を有さない場合がある。例えば、図１４Ｃ及び図１４Ｄに示すように、開口部１９０に位置する導電体１２０の底部の形状は、針状となることがある。なお、図１４Ｃ及び図１４Ｄに示す記憶装置の平面図は、図１Ａを参照できる。 As shown in FIGS. 14A and 14B, the bottom of the conductor 120 located in the opening 190 has a flat region. Note that the maximum width of the opening 190 (the maximum diameter when the opening 190 is circular in plan view), the film thickness of the insulator 180 (corresponding to the depth of the opening 190), and the film of the conductor 115 Depending on the thickness and the film thickness of the insulator 130, the bottom of the conductor 120 located in the opening 190 may not have a flat area. For example, as shown in FIGS. 14C and 14D, the bottom of the conductor 120 located in the opening 190 may have a needle-like shape. Note that FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 14C and 14D.
　また、絶縁体１８０及び絶縁体２８０が互いに同じ材料を用いる場合、角度θ１と角度θ２は、一致又は概略一致する。なお、絶縁体１８０及び絶縁体２８０のそれぞれに用いる材料、開口部１９０及び開口部２９０のそれぞれの形成方法などによっては、角度θ１と角度θ２とは異なってもよい。例えば、角度θ１が、角度θ２よりも大きくてもよいし、角度θ２よりも小さくてもよい。また、角度θ１及び角度θ２の一方が９０度又はその近傍値であってもよい。 Further, when the insulator 180 and the insulator 280 are made of the same material, the angle θ1 and the angle θ2 match or approximately match. Note that the angle θ1 and the angle θ2 may be different depending on the materials used for the insulator 180 and the insulator 280, the method for forming the opening 190 and the opening 290, and the like. For example, the angle θ1 may be larger than the angle θ2, or may be smaller than the angle θ2. Further, one of the angle θ1 and the angle θ2 may be 90 degrees or a value close to 90 degrees.
　または、例えば、開口部２９０の側壁及び開口部１９０の側壁の一方又は両方は、逆テーパー形状になっていてもよい。 Alternatively, for example, one or both of the side walls of the opening 290 and the side wall of the opening 190 may have an inverted tapered shape.
　ここで、逆テーパー形状とは、底部よりも基板に平行な方向にせり出した側部、または上部を有した形状である。このとき、開口部２９０の形状は、円錐台形状である。この場合、平面視において開口部２９０は円形であり、断面視において開口部２９０は台形になる。また、円錐台形状の上底面（例えば、導電体２４０に設けられた開口部）の面積は、円錐台形状の下底面（開口部２９０において露出している導電体１２０の上面）の面積よりも大きい。このような構成にすることで、酸化物半導体２３０と導電体１２０とが接する面積を大きくすることができる。 Here, the inverted tapered shape is a shape that has a side portion or an upper portion that protrudes from the bottom portion in a direction parallel to the substrate. At this time, the shape of the opening 290 is a truncated cone shape. In this case, the opening 290 is circular in plan view, and trapezoidal in cross-section. Further, the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big. With such a structure, the area in which the oxide semiconductor 230 and the conductor 120 are in contact can be increased.
　図１Ｂ及び図１Ｃに示すように、酸化物半導体２３０の一部は、開口部２９０の外、つまり、導電体２４０の上に位置する。なお、図１Ｂでは、酸化物半導体２３０が、Ｘ方向において分断される構成を示しているが、本発明はこれに限られない。例えば、図１５Ａ及び図１５Ｂに示すように、酸化物半導体２３０は、Ｘ方向に延在して設けられてもよい。なお、図１５Ａ及び図１５Ｂに示す構成においても、酸化物半導体２３０は、Ｙ方向において分断される（図１５Ｃ参照）。 As shown in FIGS. 1B and 1C, a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240. Note that although FIG. 1B shows a configuration in which the oxide semiconductor 230 is divided in the X direction, the present invention is not limited to this. For example, as shown in FIGS. 15A and 15B, the oxide semiconductor 230 may be provided extending in the X direction. Note that also in the structures shown in FIGS. 15A and 15B, the oxide semiconductor 230 is divided in the Y direction (see FIG. 15C).
　また、図１Ｃでは、酸化物半導体２３０の側端部が、導電体２４０の側端部より内側に位置する構成を示している。なお、本発明はこれに限られるものではない。例えば、Ｙ方向において、酸化物半導体２３０の側端部と導電体２４０の側端部が一致する構造にしてもよい。又は、酸化物半導体２３０の側端部が、導電体２４０の側端部より外側に位置する構造にしてもよい。 Further, FIG. 1C shows a configuration in which the side end portion of the oxide semiconductor 230 is located inside the side end portion of the conductor 240. Note that the present invention is not limited to this. For example, a structure may be adopted in which the side edges of the oxide semiconductor 230 and the side edges of the conductor 240 coincide in the Y direction. Alternatively, a structure may be employed in which the side end portion of the oxide semiconductor 230 is located outside the side end portion of the conductor 240.
　酸化物半導体２３０として用いる金属酸化物のバンドギャップは、２ｅＶ以上が好ましく、２．５ｅＶ以上がより好ましい。酸化物半導体２３０としてバンドギャップの大きい金属酸化物を用いることで、トランジスタのオフ電流を低減できる。オフ電流が小さいトランジスタをメモリセルに用いることにより長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、または、リフレッシュ動作の頻度が極めて少ないため、記憶装置の消費電力を十分に低減できる。なお、一般的なＤＲＡＭにおいては、リフレッシュ動作の頻度を約１回／６０ｍｓｅｃとする必要があるが、本発明の一態様の記憶装置においては、リフレッシュ動作の頻度を約１回／１０ｓｅｃと、１０倍以上または１００倍以上のリフレッシュ動作の頻度とすることができる。なお、本発明の一態様の記憶装置とすることで、リフレッシュ動作は、１ｓｅｃ以上１００ｓｅｃ以下、好ましくは、５ｓｅｃ以上５０ｓｅｃ以下に１回の頻度とすることができる。 The band gap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a large band gap as the oxide semiconductor 230, off-state current of the transistor can be reduced. By using a transistor with a small off-state current in a memory cell, it is possible to retain stored contents for a long period of time. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced. Note that in a general DRAM, the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec. The refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
　なお、酸化物半導体２３０としては、後述する［金属酸化物］の項目に記載の金属酸化物を、単層または積層で用いることができる。 Note that as the oxide semiconductor 230, a metal oxide described in the section [Metal oxide] described below can be used in a single layer or in a stacked layer.
　酸化物半導体２３０として、具体的には、Ｉｎ：Ｍ：Ｚｎ＝１：３：２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：３：４［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：０．５［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：２［原子数比］もしくはその近傍の組成、またはＩｎ：Ｍ：Ｚｎ＝４：２：３［原子数比］もしくはその近傍の組成の金属酸化物を用いればよい。なお、近傍の組成とは、所望の原子数比の±３０％の範囲を含む。また、元素Ｍとして、ガリウムを用いることが好ましい。 Specifically, the oxide semiconductor 230 has a composition of In:M:Zn=1:3:2 [atomic ratio] or a nearby composition, In:M:Zn=1:3:4 [atomic ratio], or Composition near it, In:M:Zn=1:1:0.5 [atomic ratio] or a composition near it, In:M:Zn=1:1:1 [atomic ratio] or a composition near it , In:M:Zn=1:1:1.2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn=1:1:2 [atomic ratio] or a composition in the vicinity thereof, or In: A metal oxide having a composition of M:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof may be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. Further, as the element M, it is preferable to use gallium.
　なお、金属酸化物をスパッタリング法により成膜する場合、上記の原子数比は、成膜された金属酸化物の原子数比に限られず、金属酸化物の成膜に用いるスパッタリングターゲットの原子数比であってもよい。 In addition, when forming a metal oxide film by sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
　酸化物半導体２３０に用いる金属酸化物の組成の分析には、例えば、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）、Ｘ線光電子分光法（ＸＰＳ：Ｘ−ｒａｙ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）、誘導結合プラズマ質量分析法（ＩＣＰ−ＭＳ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ−Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）、または誘導結合高周波プラズマ発光分光法（ＩＣＰ−ＡＥＳ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ−Ａｔｏｍｉｃ　Ｅｍｉｓｓｉｏｎ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）を用いることができる。または、これらの手法を複数組み合わせて分析を行なってもよい。なお、含有率が低い元素は、分析精度の影響により、実際の含有率と分析によって得られた含有率が異なる場合がある。例えば、元素Ｍの含有率が低い場合、分析によって得られた元素Ｍの含有率が、実際の含有率より低くなる場合がある。 For analyzing the composition of the metal oxide used in the oxide semiconductor 230, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), etc. ) , Inductively Coupled Plasma-Mass Spectrometry (ICP-MS), or Inductively Coupled Plasma-Atomi (ICP-AES) c Emission Spectrometry) can be used. Alternatively, analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
　金属酸化物の形成には、スパッタリング法、または原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を好適に用いることができる。なお、金属酸化物をスパッタリング法で形成する場合、形成後の金属酸化物の組成はスパッタリングターゲットの組成と異なる場合がある。特に、亜鉛は、形成後の金属酸化物における含有率が、スパッタリングターゲットと比較して５０％程度にまで減少する場合がある。 A sputtering method or an atomic layer deposition (ALD) method can be suitably used to form the metal oxide. Note that when forming a metal oxide by a sputtering method, the composition of the formed metal oxide may be different from the composition of the sputtering target. In particular, the content of zinc in the metal oxide after formation may be reduced to about 50% compared to the sputtering target.
　酸化物半導体２３０は、結晶性を有することが好ましい。結晶性を有する酸化物半導体として、ＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、ｎｃ−ＯＳ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、多結晶酸化物半導体、単結晶酸化物半導体等が挙げられる。酸化物半導体２３０として、ＣＡＡＣ−ＯＳ又はｎｃ−ＯＳを用いることが好ましく、ＣＡＡＣ−ＯＳを用いることが特に好ましい。 The oxide semiconductor 230 preferably has crystallinity. Examples of oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), and polycrystalline oxide semiconductors. Examples include semiconductors, single crystal oxide semiconductors, and the like. As the oxide semiconductor 230, it is preferable to use CAAC-OS or nc-OS, and it is particularly preferable to use CAAC-OS.
　ＣＡＡＣ−ＯＳは、複数の層状の結晶領域を有し、ｃ軸が被形成面の法線方向に配向していることが好ましい。例えば、酸化物半導体２３０は、開口部２９０の側壁、特に絶縁体２８０の側面に対して、概略平行な層状の結晶を有することが好ましい。このような構成にすることで、トランジスタ２００のチャネル長方向に対して、酸化物半導体２３０の層状の結晶が概略平行に形成されるため、トランジスタのオン電流を大きくすることができる。 It is preferable that the CAAC-OS has a plurality of layered crystal regions, and the c-axis is oriented in the normal direction of the surface on which it is formed. For example, the oxide semiconductor 230 preferably has a layered crystal that is approximately parallel to the sidewall of the opening 290, particularly the sidewall of the insulator 280. With this structure, the layered crystal of the oxide semiconductor 230 is formed approximately parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.
　ＣＡＡＣ−ＯＳは、結晶性の高い、緻密な構造を有しており、不純物および欠陥（例えば、酸素欠損など）が少ない金属酸化物である。特に、金属酸化物の形成後に、金属酸化物が多結晶化しない程度の温度（例えば、４００℃以上６００℃以下）で加熱処理することで、ＣＡＡＣ−ＯＳをより結晶性の高い、緻密な構造にすることができる。このようにして、ＣＡＡＣ−ＯＳの密度をより高めることで、当該ＣＡＡＣ−ＯＳ中の不純物または酸素の拡散をより低減することができる。 CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (for example, oxygen vacancies). In particular, after the formation of the metal oxide, heat treatment at a temperature that does not polycrystallize the metal oxide (e.g., 400°C or higher and 600°C or lower) allows CAAC-OS to have a more highly crystalline and dense structure. It can be done. In this way, by further increasing the density of the CAAC-OS, it is possible to further reduce the diffusion of impurities or oxygen in the CAAC-OS.
　また、ＣＡＡＣ−ＯＳは、明確な結晶粒界を確認することが難しいため、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。したがって、ＣＡＡＣ−ＯＳを有する金属酸化物は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する金属酸化物は熱に強く、信頼性が高い。 Furthermore, in CAAC-OS, it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Therefore, the metal oxide with CAAC-OS has stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.
　また、酸化物半導体２３０としてＣＡＡＣ−ＯＳなどの結晶性を有する酸化物を用いることで、ソース電極またはドレイン電極による、酸化物半導体２３０からの酸素の引き抜きを抑制できる。これにより、熱処理を行なっても、酸化物半導体２３０から酸素が引き抜かれることを抑制できるため、トランジスタ２００は、製造工程における高い温度（所謂サーマルバジェット）に対して安定である。 Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode can be suppressed. As a result, even if heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so the transistor 200 is stable against high temperatures (so-called thermal budget) during the manufacturing process.
　酸化物半導体２３０の結晶性は、例えば、Ｘ線回折（ＸＲＤ：ＸＲａｙ　Ｄｉｆｆｒａｃｔｉｏｎ）、透過型電子顕微鏡（ＴＥＭ：Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）、または電子線回折（ＥＤ：Ｅｌｅｃｔｒｏｎ　Ｄｉｆｆｒａｃｔｉｏｎ）により解析できる。または、これらの手法を複数組み合わせて分析を行なってもよい。 The crystallinity of the oxide semiconductor 230 can be determined by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). ) can be analyzed. Alternatively, analysis may be performed by combining two or more of these methods.
　なお、図１Ｂ及び図１Ｃでは、酸化物半導体２３０を単層で示したが、本発明はこれに限られるものではない。酸化物半導体２３０は、化学組成が異なる複数の酸化物層の積層構造を有してもよい。例えば、上記金属酸化物から選ばれる複数種を適宜積層する構造にしてもよい。 Note that although the oxide semiconductor 230 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited thereto. The oxide semiconductor 230 may have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure may be adopted in which a plurality of metal oxides selected from the above metal oxides are laminated as appropriate.
　例えば、図１６Ａ及び図１６Ｂに示すように、酸化物半導体２３０は、酸化物半導体２３０ａと、酸化物半導体２３０ａ上の酸化物半導体２３０ｂとの積層構造を有してもよい。 For example, as shown in FIGS. 16A and 16B, the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b over the oxide semiconductor 230a.
　酸化物半導体２３０ａに用いる材料の導電率は、酸化物半導体２３０ｂに用いる材料の導電率と異なることが好ましい。 The conductivity of the material used for the oxide semiconductor 230a is preferably different from the conductivity of the material used for the oxide semiconductor 230b.
　例えば、酸化物半導体２３０ａには、酸化物半導体２３０ｂより導電率の高い材料を用いることができる。ソース電極又はドレイン電極として機能する導電体１２０及び導電体２４０と接する酸化物半導体２３０ａに導電率の高い材料を用いることにより、酸化物半導体２３０と導電体１２０との接触抵抗、及び酸化物半導体２３０と導電体２４０との接触抵抗を低くすることができ、オン電流が大きいトランジスタとすることができる。 For example, a material with higher conductivity than the oxide semiconductor 230b can be used for the oxide semiconductor 230a. By using a material with high conductivity for the oxide semiconductor 230a that is in contact with the conductor 120 and the conductor 240 that function as a source electrode or a drain electrode, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the oxide semiconductor 230 can be reduced. The contact resistance between the conductor 240 and the conductor 240 can be reduced, and a transistor with a large on-state current can be obtained.
　ここで、ゲート電極として機能する導電体２６０側に設けられる酸化物半導体２３０ｂに導電率の高い材料を用いる場合、トランジスタのしきい値電圧がシフトし、ゲート電圧が０Ｖ時に流れるドレイン電流（以下、カットオフ電流とも記す）が大きくなってしまう場合がある。具体的には、トランジスタ２００がｎチャネル型のトランジスタである場合、しきい値電圧が低くなってしまう場合がある。したがって、酸化物半導体２３０ｂには、酸化物半導体２３０ａより導電率の低い材料を用いることが好ましい。これにより、トランジスタ２００がｎチャネル型のトランジスタである場合はしきい値電圧を高くすることができ、カットオフ電流が小さいトランジスタとすることができる。なお、カットオフ電流が小さいことをノーマリオフと記す場合がある。 Here, when a material with high conductivity is used for the oxide semiconductor 230b provided on the conductor 260 side that functions as a gate electrode, the threshold voltage of the transistor shifts, and the drain current (hereinafter referred to as (also referred to as cut-off current) may become large. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b. Thus, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as normally off.
　前述したように酸化物半導体２３０を積層構造とし、酸化物半導体２３０ａには、酸化物半導体２３０ｂより導電率の高い材料を用いることにより、ノーマリオフ、かつオン電流が大きいトランジスタとすることができる。したがって、低い消費電力と高い性能を両立した記憶装置とすることができる。 As described above, by forming the oxide semiconductor 230 in a stacked structure and using a material with higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, it is possible to provide a storage device that has both low power consumption and high performance.
　なお、酸化物半導体２３０ａのキャリア濃度は、酸化物半導体２３０ｂのキャリア濃度より高いことが好ましい。酸化物半導体２３０ａのキャリア濃度を高くすることにより導電率が高くなり、酸化物半導体２３０と導電体１２０との接触抵抗、及び酸化物半導体２３０と導電体２４０との接触抵抗を低くすることができ、オン電流が大きいトランジスタとすることができる。酸化物半導体２３０ｂのキャリア濃度を低くすることにより導電率が低くなり、ノーマリオフのトランジスタとすることができる。 Note that the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b. By increasing the carrier concentration of the oxide semiconductor 230a, the conductivity increases, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced. , the transistor can have a large on-current. By lowering the carrier concentration of the oxide semiconductor 230b, the conductivity is lowered, and a normally-off transistor can be obtained.
　ここでは、酸化物半導体２３０ａに酸化物半導体２３０ｂより導電率の高い材料を用いる例を示したが、本発明の一態様はこれに限られない。酸化物半導体２３０ａに、酸化物半導体２３０ｂより導電率の低い材料を用いてもよい。酸化物半導体２３０ａのキャリア濃度が、酸化物半導体２３０ｂのキャリア濃度より低い構成とすることができる。 Here, an example is shown in which a material having higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a; however, one embodiment of the present invention is not limited to this. A material having lower conductivity than the oxide semiconductor 230b may be used for the oxide semiconductor 230a. The carrier concentration of the oxide semiconductor 230a can be lower than the carrier concentration of the oxide semiconductor 230b.
　酸化物半導体２３０ａに用いる第１の金属酸化物のバンドギャップは、酸化物半導体２３０ｂに用いる第２の金属酸化物のバンドギャップと異なることが好ましい。例えば、第１の金属酸化物のバンドギャップと第２の金属酸化物のバンドギャップの差は、０．１ｅＶ以上が好ましく、さらには０．２ｅＶ以上が好ましく、さらには０．３ｅＶ以上が好ましい。 The band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
　酸化物半導体２３０ａに用いる第１の金属酸化物のバンドギャップは、酸化物半導体２３０ｂに用いる第２の金属酸化物のバンドギャップより小さい構成とすることができる。これにより、酸化物半導体２３０と導電体１２０との接触抵抗、及び酸化物半導体２３０と導電体２４０との接触抵抗を低くすることができ、オン電流が大きいトランジスタとすることができる。また、トランジスタ２００がｎチャネル型のトランジスタである場合はしきい値電圧を高くすることができ、ノーマリオフのトランジスタとすることができる。 The bandgap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the bandgap of the second metal oxide used for the oxide semiconductor 230b. Accordingly, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with high on-state current can be obtained. Further, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor 200 can be a normally-off transistor.
　ここでは、第１の金属酸化物のバンドギャップが、第２の金属酸化物のバンドギャップより小さい例を示したが、本発明の一態様はこれに限られない。第１の金属酸化物のバンドギャップが、第２の金属酸化物のバンドギャップより大きい構成とすることができる。 Although an example is shown here in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide, one embodiment of the present invention is not limited to this. The first metal oxide may have a larger band gap than the second metal oxide.
　前述したように、酸化物半導体２３０ａに用いる第１の金属酸化物のバンドギャップは、酸化物半導体２３０ｂに用いる第２の金属酸化物のバンドギャップより小さい構成とすることができる。第１の金属酸化物の組成は、第２の金属酸化物の組成と異なることが好ましい。第１の金属酸化物と第２の金属酸化物の組成を異ならせることで、バンドギャップを制御できる。例えば、第１の金属酸化物の元素Ｍの含有率は、第２の金属酸化物の元素Ｍの含有率より低いことが好ましい。具体的には、第１の金属酸化物及び第２の金属酸化物をＩｎ−Ｍ−Ｚｎ酸化物とする場合、第１の金属酸化物はＩｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］またはその近傍の組成、第２の金属酸化物はＩｎ：Ｍ：Ｚｎ＝１：３：２［原子数比］またはその近傍とすることができる。元素Ｍとして、ガリウム、アルミニウム、及び錫の一または複数を用いることが特に好ましい。 As described above, the bandgap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the bandgap of the second metal oxide used for the oxide semiconductor 230b. Preferably, the composition of the first metal oxide is different from the composition of the second metal oxide. By making the compositions of the first metal oxide and the second metal oxide different, the band gap can be controlled. For example, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. Specifically, when the first metal oxide and the second metal oxide are In-M-Zn oxide, the first metal oxide has In:M:Zn=1:1:1 [atomic The second metal oxide can have a composition of In:M:Zn=1:3:2 [atomic ratio] or around it. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M.
　第１の金属酸化物が元素Ｍを含まない構成としてもよい。例えば、酸化物半導体２３０ａに用いる第１の金属酸化物をＩｎ−Ｚｎ酸化物とし、酸化物半導体２３０ｂに用いる第２の金属酸化物をＩｎ−Ｍ−Ｚｎ酸化物とすることができる。具体的には、第１の金属酸化物をＩｎ−Ｚｎ酸化物とし、第２の金属酸化物をＩｎ−Ｇａ−Ｚｎ酸化物とすることができる。さらに具体的には、第１の金属酸化物はＩｎ：Ｚｎ＝１：１［原子数比］またはその近傍の組成、もしくはＩｎ：Ｚｎ＝４：１［原子数比］またはその近傍の組成とし、第２の金属酸化物はＩｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］またはその近傍の組成とすることができる。 A structure in which the first metal oxide does not contain the element M may also be used. For example, the first metal oxide used for the oxide semiconductor 230a can be an In-Zn oxide, and the second metal oxide used for the oxide semiconductor 230b can be an In-M-Zn oxide. Specifically, the first metal oxide can be an In-Zn oxide, and the second metal oxide can be an In-Ga-Zn oxide. More specifically, the first metal oxide has a composition of In:Zn=1:1 [atomic ratio] or its vicinity, or a composition of In:Zn=4:1 [atomic ratio] or its vicinity. , the second metal oxide can have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or around it.
　ここでは、第１の金属酸化物の元素Ｍの含有率は、第２の金属酸化物の元素Ｍの含有率より低い例を示したが、本発明の一態様はこれに限られない。第１の金属酸化物の元素Ｍの含有率は、第２の金属酸化物の元素Ｍの含有率より高い構成としてもよい。なお、第１の金属酸化物と第２の金属酸化物で組成が異なればよく、元素Ｍ以外の元素の含有率が異なってもよい。 Here, an example is shown in which the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this. The content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the content rates of elements other than element M may be different.
　酸化物半導体２３０の膜厚は、１ｎｍ以上、３ｎｍ以上、または５ｎｍ以上であって、２０ｎｍ以下、１５ｎｍ以下、１２ｎｍ以下、または１０ｎｍ以下であることが好ましい。 The film thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
　酸化物半導体２３０を構成する各層（ここでは、酸化物半導体２３０ａ及び酸化物半導体２３０ｂ）の膜厚は、酸化物半導体２３０の膜厚が前述の範囲となるように決めればよい。酸化物半導体２３０ａと導電体１２０との接触抵抗、及び酸化物半導体２３０ａと導電体２４０との接触抵抗が求められる範囲になるように、酸化物半導体２３０ａの膜厚を決めることができる。また、トランジスタのしきい値電圧が求められる範囲になるように、酸化物半導体２３０ｂの膜厚を決めることができる。なお、酸化物半導体２３０ａの膜厚は、酸化物半導体２３０ｂの膜厚と同じであってもよく、異なってもよい。 The thickness of each layer constituting the oxide semiconductor 230 (here, the oxide semiconductor 230a and the oxide semiconductor 230b) may be determined so that the thickness of the oxide semiconductor 230 falls within the above range. The thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within the desired range. Further, the thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor is within a desired range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.
　図１６Ａ及び図１６Ｂには、酸化物半導体２３０が、酸化物半導体２３０ａと酸化物半導体２３０ｂの２層の積層構造である構成を示しているが、本発明はこれに限られるものではない。酸化物半導体２３０は、３層以上の積層構造としてもよい。 Although FIGS. 16A and 16B show a structure in which the oxide semiconductor 230 has a two-layer stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b, the present invention is not limited to this. The oxide semiconductor 230 may have a stacked structure of three or more layers.
　酸化物半導体２３０を３層積層構造とする場合、例えば、導電体１２０側から順に、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］またはその近傍の組成である金属酸化物、Ｉｎ：Ｚｎ＝１：１［原子数比］またはその近傍の組成、もしくはＩｎ：Ｚｎ＝４：１［原子数比］またはその近傍の組成である金属酸化物、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］またはその近傍の組成である金属酸化物が設けられた構成としてもよい。このような構成にすることで、トランジスタ２００のオン電流を大きくし、且つ、ばらつきが少なく信頼性の高いトランジスタ構造とすることができる。 When the oxide semiconductor 230 has a three-layer stacked structure, for example, in order from the conductor 120 side, a metal oxide with a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a nearby composition, In : Zn = 1:1 [atomic ratio] or a composition close to that, or In:Zn = 4:1 [atomic ratio] or a metal oxide with a composition close to that, In:Ga:Zn = 1:1 :1 [atomic ratio] or a composition in the vicinity thereof may be provided. With this structure, the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with little variation can be achieved.
　絶縁体２５０としては、後述する［絶縁体］の項目に記載の絶縁体を、単層または積層で用いることができる。例えば、絶縁体２５０は、酸素を透過しやすい絶縁体を用いることが好ましい。このような構成にすることで、絶縁体２８０に含まれる酸素を、絶縁体２５０を介して領域２３０ｉに供給できる。また、絶縁体２５０は、過剰酸素を含む絶縁体を用いてもよい。このような構成にすることで、絶縁体２５０に含まれる酸素を領域２３０ｉに供給できる。一例として、絶縁体２５０として、酸化シリコン又は酸化窒化シリコンを用いることができる。酸化シリコン、及び酸化窒化シリコンは熱に対し安定であるため好ましい。 As the insulator 250, the insulators described in the section [Insulator] described below can be used in a single layer or in a laminated manner. For example, as the insulator 250, it is preferable to use an insulator that easily transmits oxygen. With such a configuration, oxygen contained in the insulator 280 can be supplied to the region 230i via the insulator 250. Further, the insulator 250 may be an insulator containing excess oxygen. With such a configuration, oxygen contained in the insulator 250 can be supplied to the region 230i. As an example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferable because they are stable against heat.
　また、絶縁体２５０として、後述する［絶縁体］の項目に記載の比誘電率が高い材料、所謂ｈｉｇｈ−ｋ材料を用いてもよい。例えば、酸化ハフニウムまたは酸化アルミニウムなどを用いてもよい。 Furthermore, as the insulator 250, a material with a high dielectric constant described in the section [Insulator] described below, a so-called high-k material, may be used. For example, hafnium oxide or aluminum oxide may be used.
　絶縁体２５０の膜厚は、０．５ｎｍ以上１５ｎｍ以下とすることが好ましく、０．５ｎｍ以上１２ｎｍ以下とすることがより好ましく、０．５ｎｍ以上１０ｎｍ以下とすることがさらに好ましい。絶縁体２５０は、少なくとも一部において、上記のような膜厚の領域を有していればよい。 The film thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. The insulator 250 only needs to have a region with the thickness described above at least in part.
　絶縁体２５０中の水、水素などの不純物濃度は低減されていることが好ましい。これにより、酸化物半導体２３０のチャネル形成領域への、水、水素などの不純物の混入を抑制できる。 It is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
　図１Ｂ及び図１Ｃに示すように、絶縁体２５０の一部は、開口部２９０の外、つまり、導電体２４０及び絶縁体２８０の上に位置する。このとき、絶縁体２５０は、酸化物半導体２３０の側端部を覆うことが好ましい。これにより、導電体２６０と酸化物半導体２３０がショートするのを防ぐことができる。また、絶縁体２５０は、導電体２４０の側端部を覆うことが好ましい。これにより、導電体２６０と導電体２４０がショートするのを防ぐことができる。 As shown in FIGS. 1B and 1C, a portion of the insulator 250 is located outside the opening 290, that is, above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 cover the side edges of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. Further, it is preferable that the insulator 250 covers the side end portions of the conductor 240. This can prevent short-circuiting between the conductor 260 and the conductor 240.
　なお、図１Ｂ及び図１Ｃでは、絶縁体２５０を単層で示したが、本発明はこれに限られるものではない。絶縁体２５０は、積層構造であってもよい。 Note that although the insulator 250 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this. The insulator 250 may have a laminated structure.
　例えば、図１６Ａ及び図１６Ｂに示すように、絶縁体２５０は、絶縁体２５０ａと、絶縁体２５０ａ上の絶縁体２５０ｂと、絶縁体２５０ｂ上の絶縁体２５０ｃとの積層構造を有してもよい。 For example, as shown in FIGS. 16A and 16B, the insulator 250 may have a laminated structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. .
　絶縁体２５０ｂは、後述する［絶縁体］の項目に記載の比誘電率が低い材料を用いることが好ましい。特に、酸化シリコン、及び酸化窒化シリコンは熱に対し安定であるため好ましい。この場合、絶縁体２５０ｂは、少なくとも酸素と、シリコンと、を有する。このような構成にすることで、導電体２６０と導電体２４０の間の寄生容量を低減できる。また、絶縁体２５０ｂ中の、水、水素などの不純物の濃度は低減されていることが好ましい。 For the insulator 250b, it is preferable to use a material with a low dielectric constant described in the section [Insulator] described below. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 250b contains at least oxygen and silicon. With such a configuration, the parasitic capacitance between the conductor 260 and the conductor 240 can be reduced. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.
　絶縁体２５０ａは、後述する［絶縁体］の項目に記載の酸素に対するバリア性を有する絶縁体を用いることが好ましい。絶縁体２５０ａは、酸化物半導体２３０と接する領域を有する。絶縁体２５０ａが酸素に対するバリア性を有することで、熱処理などを行った際に、酸化物半導体２３０から酸素が脱離することを抑制できる。よって、酸化物半導体２３０に酸素欠損が形成されることを抑制できる。これにより、トランジスタ２００の電気特性を良好にし、信頼性を向上させることができる。絶縁体２５０ａとして、例えば、酸化アルミニウムを用いるとよい。この場合、絶縁体２５０ａは、少なくとも酸素と、アルミニウムと、を有する。 As the insulator 250a, it is preferable to use an insulator having barrier properties against oxygen as described in the section [Insulator] described below. The insulator 250a has a region in contact with the oxide semiconductor 230. Since the insulator 250a has barrier properties against oxygen, desorption of oxygen from the oxide semiconductor 230 can be suppressed when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. Thereby, the electrical characteristics of the transistor 200 can be improved and reliability can be improved. For example, aluminum oxide may be used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.
　絶縁体２５０ｃは、後述する［絶縁体］の項目に記載の水素に対するバリア性を有する絶縁体を用いることが好ましい。これにより、導電体２６０に含まれる不純物の、酸化物半導体２３０への拡散を抑制できる。窒化シリコンは水素バリア性が高いため、絶縁体２５０ｃとして好適である。この場合、絶縁体２５０ｃは、少なくとも窒素と、シリコンと、を有する。 The insulator 250c is preferably an insulator having a barrier property against hydrogen as described in the [Insulator] section below. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has a high hydrogen barrier property and is therefore suitable as the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.
　絶縁体２５０ｃは、さらに酸素に対するバリア性を有してもよい。絶縁体２５０ｃは、絶縁体２５０ｂと導電体２６０の間に設けられている。したがって、絶縁体２５０ｂに含まれる酸素の導電体２６０への拡散を防ぎ、導電体２６０の酸化を抑制できる。また、領域２３０ｉへ供給する酸素量の減少を抑制できる。 The insulator 250c may further have barrier properties against oxygen. Insulator 250c is provided between insulator 250b and conductor 260. Therefore, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Further, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.
　また、絶縁体２５０ｂと絶縁体２５０ｃの間に絶縁体を設けてもよい。当該絶縁体は、後述する［絶縁体］の項目に記載の水素を捕獲する又は固着する機能を有する絶縁体を用いることが好ましい。当該絶縁体を設けることで、酸化物半導体２３０に含まれる水素を、より効果的に捕獲させる又は固着させることができる。よって、酸化物半導体２３０中の水素濃度を低減できる。当該絶縁体して、例えば、酸化ハフニウムを用いるとよい。この場合、当該絶縁体は、少なくとも酸素と、ハフニウムと、を有する。また、当該絶縁体は、アモルファス構造を有してもよい。 Furthermore, an insulator may be provided between the insulator 250b and the insulator 250c. As the insulator, it is preferable to use an insulator having a function of capturing or fixing hydrogen as described in the section [Insulator] described below. By providing the insulator, hydrogen contained in the oxide semiconductor 230 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced. For example, hafnium oxide may be used as the insulator. In this case, the insulator contains at least oxygen and hafnium. Further, the insulator may have an amorphous structure.
　トランジスタ２００の微細化を図るにあたって、絶縁体２５０ａ乃至絶縁体２５０ｃの膜厚は薄いことが好ましく、前述の範囲内にすることが好ましい。代表的には、絶縁体２５０ａ、絶縁体２５０ｂ、水素を捕獲する又は固着する機能を有する絶縁体、及び絶縁体２５０ｃの膜厚をそれぞれ、１ｎｍ、２ｎｍ、２ｎｍ、及び１ｎｍとする。このような構成にすることで、トランジスタ２００を微細化または高集積化しても良好な電気特性を有することができる。 In attempting to miniaturize the transistor 200, the film thicknesses of the insulators 250a to 250c are preferably thin, and preferably within the above-mentioned range. Typically, the film thicknesses of the insulator 250a, the insulator 250b, the insulator having a function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor 200 can have good electrical characteristics even if it is miniaturized or highly integrated.
　図１６Ａ及び図１６Ｂには、絶縁体２５０が、絶縁体２５０ａ乃至絶縁体２５０ｃの３層の積層構造である構成を示しているが、本発明はこれに限られるものではない。絶縁体２５０は、２層、又は４層以上の積層構造としてもよい。このとき、絶縁体２５０に含まれる各層は、絶縁体２５０ａ乃至絶縁体２５０ｃ及び水素を捕獲する又は固着する機能を有する絶縁体から適宜選択するとよい。 Although FIGS. 16A and 16B show a configuration in which the insulator 250 has a three-layer stacked structure of insulators 250a to 250c, the present invention is not limited to this. The insulator 250 may have a laminated structure of two layers, or four or more layers. At this time, each layer included in the insulator 250 may be appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.
　導電体２６０としては、後述する［導電体］の項目に記載の導電体を、単層または積層で用いることができる。例えば、導電体２６０として、タングステンなどの導電性が高い導電性材料を用いることができる。 As the conductor 260, the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner. For example, as the conductor 260, a highly conductive material such as tungsten can be used.
　また、導電体２６０として、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料などを用いることが好ましい。当該導電性材料として、窒素を含む導電性材料（例えば、窒化チタンまたは窒化タンタルなど）、および酸素を含む導電性材料（例えば、酸化ルテニウムなど）などが挙げられる。これにより、導電体２６０の導電率が低下するのを抑制できる。 Furthermore, as the conductor 260, it is preferable to use a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or the like. Examples of the conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride), a conductive material containing oxygen (for example, ruthenium oxide, etc.), and the like. Thereby, it is possible to suppress the conductivity of the conductor 260 from decreasing.
　なお、図１Ｂ及び図１Ｃでは、導電体２６０を単層で示したが、本発明はこれに限られるものではない。導電体２６０は、積層構造であってもよい。例えば、図１６Ａ及び図１６Ｂに示すように、導電体２６０は、導電体２６０ａと、導電体２６０ａ上の導電体２６０ｂとの積層構造を有してもよい。このとき、例えば、導電体２６０ａとして窒化チタンを用い、導電体２６０ｂとしてタングステンを用いてもよい。このようにタングステンを積層して設けることで、導電体２６０の導電性を向上させ、配線ＷＬとして十分に機能させることができる。 Note that although the conductor 260 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this. The conductor 260 may have a laminated structure. For example, as shown in FIGS. 16A and 16B, the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a. At this time, for example, titanium nitride may be used as the conductor 260a, and tungsten may be used as the conductor 260b. By layering tungsten in this way, the conductivity of the conductor 260 can be improved and it can function sufficiently as the wiring WL.
　図１６Ａ及び図１６Ｂには、導電体２６０が、導電体２６０ａと導電体２６０ｂの２層の積層構造である構成を示しているが、本発明はこれに限られるものではない。導電体２６０は、３層以上の積層構造としてもよい。 Although FIGS. 16A and 16B show a configuration in which the conductor 260 has a two-layer stacked structure of a conductor 260a and a conductor 260b, the present invention is not limited to this. The conductor 260 may have a laminated structure of three or more layers.
　図１Ｂ及び図１Ｃでは、導電体２６０が開口部２９０を埋め込むように設けられているが、本発明はこれに限られるものではない。例えば、導電体２６０の中央部に、開口部２９０の形状を反映した凹部が形成され、当該凹部の一部が開口部２９０に位置する場合がある。このとき、当該凹部を無機絶縁材料などで充填する構成にしてもよい。 In FIGS. 1B and 1C, the conductor 260 is provided to fill the opening 290, but the present invention is not limited to this. For example, a recess reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the recess may be located in the opening 290. At this time, the recess may be filled with an inorganic insulating material or the like.
　また、図１Ｂ及び図１Ｃに示すように、導電体２６０の一部は、開口部２９０の外、つまり、導電体２４０及び絶縁体２８０の上に位置する。このとき、図１Ｂに示すように、導電体２６０の側端部は、酸化物半導体２３０の側端部より内側に位置することが好ましい。これにより、導電体２６０と酸化物半導体２３０がショートするのを防ぐことができる。なお、導電体２６０の側端部は、酸化物半導体２３０の側端部と一致してもよいし、酸化物半導体２３０の側端部より外側に位置してもよい。 Further, as shown in FIGS. 1B and 1C, a portion of the conductor 260 is located outside the opening 290, that is, above the conductor 240 and the insulator 280. At this time, as shown in FIG. 1B, the side end portion of the conductor 260 is preferably located inside the side end portion of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. Note that the side end portion of the conductor 260 may coincide with the side end portion of the oxide semiconductor 230, or may be located outside the side end portion of the oxide semiconductor 230.
　導電体１２０は、［容量素子１００］の項目で説明した通りに設ければよい。 The conductor 120 may be provided as described in the section of [Capacitive element 100].
　また、図１Ｂ及び図１Ｃでは、導電体１２０の上面が平坦である構成を示しているが、本発明はこれに限られるものではない。例えば、導電体１２０の上面に、開口部２９０と重なる凹部が形成される構成にしてもよい。当該凹部を埋め込むように、酸化物半導体２３０、絶縁体２５０、及び導電体２６０の少なくとも一部が形成される構成にすることで、酸化物半導体２３０の導電体１２０近傍まで、導電体２６０のゲート電界を印加しやすくすることができる。 Further, although FIGS. 1B and 1C show a configuration in which the upper surface of the conductor 120 is flat, the present invention is not limited to this. For example, a configuration may be adopted in which a recessed portion overlapping the opening 290 is formed on the upper surface of the conductor 120. By forming at least part of the oxide semiconductor 230, the insulator 250, and the conductor 260 so as to fill the recess, the gate of the conductor 260 is formed in the oxide semiconductor 230 to the vicinity of the conductor 120. It is possible to easily apply an electric field.
　導電体２４０としては、後述する［導電体］の項目に記載の導電体を、単層または積層で用いることができる。例えば、導電体２４０として、タングステンなどの、導電性が高い導電性材料を用いることができる。 As the conductor 240, the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner. For example, as the conductor 240, a highly conductive material such as tungsten can be used.
　導電体２４０も導電体２６０と同様に、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料などを用いることが好ましい。例えば、窒化チタンまたは窒化タンタルなどを用いることができる。このような構成にすることで、酸化物半導体２３０によって導電体２４０が過剰に酸化されるのを抑制できる。 Similarly to the conductor 260, the conductor 240 is also preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. With such a structure, excessive oxidation of the conductor 240 by the oxide semiconductor 230 can be suppressed.
　また、例えば、窒化チタンの上にタングステンを積層した構造にしてもよい。このようにタングステンを積層して設けることで、導電体２４０の導電性を向上させ、配線ＢＬとして十分に機能させることができる。 Alternatively, for example, a structure in which tungsten is laminated on titanium nitride may be used. By layering tungsten in this way, the conductivity of the conductor 240 can be improved and it can function sufficiently as the wiring BL.
　また、導電体２４０を第１の導電体と第２の導電体とを積層する構成とする場合、例えば、第１の導電体を導電性が高い導電性材料を用いて形成し、第２の導電体を酸素を含む導電性材料を用いて形成してもよい。絶縁体２５０と接する導電体２４０の第２の導電体として酸素を含む導電性材料を用いることで、絶縁体２５０中の酸素が導電体２４０の第１の導電体に拡散するのを抑制できる。例えば、導電体２４０の第１の導電体としてタングステンを用い、導電体２４０の第２の導電体としてシリコンを添加したインジウム錫酸化物を用いるとよい。 Further, when the conductor 240 has a structure in which a first conductor and a second conductor are laminated, for example, the first conductor is formed using a conductive material with high conductivity, and the second conductor is formed using a conductive material with high conductivity. The conductor may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductor of the conductor 240 in contact with the insulator 250, it is possible to suppress oxygen in the insulator 250 from diffusing into the first conductor of the conductor 240. For example, tungsten may be used as the first conductor of the conductor 240, and indium tin oxide added with silicon may be used as the second conductor of the conductor 240.
　絶縁体１４０及び絶縁体２８０は層間膜として機能するため、比誘電率が低いことが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体１４０及び絶縁体２８０としては、後述する［絶縁体］の項目に記載の、比誘電率が低い材料を含む絶縁体を、単層または積層で用いることができる。酸化シリコン、及び酸化窒化シリコンは、熱的に安定であるため好ましい。 Since the insulator 140 and the insulator 280 function as interlayer films, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 140 and the insulator 280, an insulator containing a material with a low dielectric constant, which is described in the section [Insulator] described later, can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
　また、絶縁体１４０及び絶縁体２８０中の水、水素などの不純物濃度は低減されていることが好ましい。これにより、酸化物半導体２３０のチャネル形成領域への、水、水素などの不純物の混入を抑制できる。 Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
　また、チャネル形成領域近傍に配置される絶縁体２８０は、過剰酸素を含む絶縁体を用いることが好ましい。過剰酸素を含む絶縁体２８０に熱処理を行うことで、絶縁体２８０から酸化物半導体２３０のチャネル形成領域に酸素を供給し、酸素欠損及びＶＯＨの低減を図ることができる。これにより、トランジスタ２００の電気特性を安定にし、信頼性の向上を図ることができる。 Further, it is preferable to use an insulator containing excess oxygen as the insulator 280 disposed near the channel formation region. By performing heat treatment on the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced. Thereby, the electrical characteristics of the transistor 200 can be stabilized and reliability can be improved.
　また、絶縁体２８０として、後述する［絶縁体］の項目に記載の、水素を捕獲するまたは水素を固着する機能を有する絶縁体を用いてもよい。このような構成にすることで、酸化物半導体２３０の水素を捕獲または固着し、酸化物半導体２３０の水素濃度を低減できる。絶縁体２８０としては、酸化マグネシウム、又は酸化アルミニウムなどを用いることができる。 Further, as the insulator 280, an insulator having a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later, may be used. With such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 230 can be reduced. As the insulator 280, magnesium oxide, aluminum oxide, or the like can be used.
　なお、図１Ｂ及び図１Ｃでは、絶縁体２８０を単層で示したが、本発明はこれに限られるものではない。絶縁体２８０は、積層構造であってもよい。 Note that although the insulator 280 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this. The insulator 280 may have a laminated structure.
　例えば、図１７Ａ及び図１７Ｂに示すように、絶縁体２８０は、絶縁体２８０ａと、絶縁体２８０ａ上の絶縁体２８０ｂと、絶縁体２８０ｂ上の絶縁体２８０ｃとの積層構造を有してもよい。 For example, as shown in FIGS. 17A and 17B, the insulator 280 may have a laminated structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b. .
　絶縁体２８０ｂには、酸素を含む絶縁体を用いることが好ましい。絶縁体２８０ｂは、絶縁体２８０ａ及び絶縁体２８０ｃの少なくとも一つと比べて、酸素の含有量が多い領域を有することが好ましい。特に、絶縁体２８０ｂは、絶縁体２８０ａ及び絶縁体２８０ｃのそれぞれと比べて、酸素の含有量が多い領域を有することが好ましい。絶縁体２８０ｂの酸素の含有量を多くすることにより、酸化物半導体２３０における絶縁体２８０ｂと接する領域とその近傍に、ｉ型の領域を形成することが容易となる。 It is preferable to use an insulator containing oxygen for the insulator 280b. The insulator 280b preferably has a region containing more oxygen than at least one of the insulators 280a and 280c. In particular, it is preferable that the insulator 280b has a region with a higher oxygen content than each of the insulators 280a and 280c. By increasing the oxygen content of the insulator 280b, an i-type region can be easily formed in a region of the oxide semiconductor 230 that is in contact with the insulator 280b and in the vicinity thereof.
　絶縁体２８０ｂには、加熱により酸素を放出する膜を用いるとより好ましい。トランジスタ２００の作製工程中にかかる熱により、絶縁体２８０ｂが酸素を放出することで、酸化物半導体２３０に酸素を供給することができる。絶縁体２８０ｂから酸化物半導体２３０、特に酸化物半導体２３０のチャネル形成領域に酸素を供給することで、酸化物半導体２３０中の酸素欠損及びＶＯＨの低減を図ることができ、良好な電気特性を示し、かつ信頼性の高いトランジスタとすることができる。 It is more preferable to use a film that releases oxygen when heated as the insulator 280b. The insulator 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, so that oxygen can be supplied to the oxide semiconductor 230. By supplying oxygen from the insulator 280b to the oxide semiconductor 230, particularly the channel formation region of the oxide semiconductor 230, oxygen vacancies and V O H in the oxide semiconductor 230 can be reduced, and good electrical characteristics can be achieved. A highly reliable transistor can be obtained.
　例えば、酸素を含む雰囲気下における加熱処理、または、酸素を含む雰囲気下におけるプラズマ処理を行うことで、絶縁体２８０ｂに酸素を供給することができる。また、絶縁体２８０ｂの上面に、スパッタリング法により、酸素雰囲気下で酸化物膜を成膜することで酸素を供給してもよい。その後、当該酸化物膜を除去してもよい。 For example, oxygen can be supplied to the insulator 280b by performing heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen. Alternatively, oxygen may be supplied by forming an oxide film on the upper surface of the insulator 280b in an oxygen atmosphere by a sputtering method. After that, the oxide film may be removed.
　絶縁体２８０ｂは、スパッタリング法、またはプラズマ化学気相堆積（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などの成膜方法で形成することが好ましい。特に、スパッタリング法を用い、成膜ガスに水素ガスを用いない成膜方法で成膜することで、水素の含有量の極めて少ない膜とすることができる。そのため、酸化物半導体２３０に水素が供給されることを抑制し、トランジスタ２００の電気特性の安定化を図ることができる。 The insulator 280b is preferably formed by a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method. In particular, by forming a film using a sputtering method that does not use hydrogen gas as a film forming gas, a film with an extremely low hydrogen content can be obtained. Therefore, supply of hydrogen to the oxide semiconductor 230 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized.
　トランジスタ２００のチャネル長が短い場合、チャネル形成領域の酸素欠損及びＶＯＨの電気特性及び信頼性への影響が特に大きくなる。絶縁体２８０ｂから酸化物半導体２３０に酸素を供給することにより、少なくとも酸化物半導体２３０の絶縁体２８０ｂと接する領域で酸素欠損及びＶＯＨが増加することを抑制できる。したがって、良好な電気特性及び高い信頼性を有するチャネル長の短いトランジスタを実現できる。 When the channel length of the transistor 200 is short, oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability. By supplying oxygen from the insulator 280b to the oxide semiconductor 230, an increase in oxygen vacancies and V OH can be suppressed at least in the region of the oxide semiconductor 230 that is in contact with the insulator 280b. Therefore, a transistor with a short channel length and good electrical characteristics and high reliability can be realized.
　絶縁体２８０ａ及び絶縁体２８０ｃにはそれぞれ、後述する［絶縁体］の項目に記載の、酸素に対するバリア性を有する絶縁体を用いることが好ましい。これにより、絶縁体２８０ｂに含まれる酸素が、加熱により絶縁体２８０ａを介して基板側に拡散すること、及び、絶縁体２８０ｃを介して絶縁体２５０側に拡散することを抑制できる。言い換えると、酸素が拡散しにくい絶縁体２８０ａ及び絶縁体２８０ｃで絶縁体２８０ｂの上下を挟持することで、絶縁体２８０ｂに含まれる酸素を閉じ込めることができる。これにより、酸化物半導体２３０に効果的に酸素を供給することができる。 It is preferable to use an insulator having barrier properties against oxygen as described in the section [Insulator] described later for each of the insulator 280a and the insulator 280c. Thereby, oxygen contained in the insulator 280b can be prevented from diffusing to the substrate side via the insulator 280a and to the insulator 250 side via the insulator 280c due to heating. In other words, by sandwiching the upper and lower sides of the insulator 280b between the insulator 280a and the insulator 280c, in which oxygen is difficult to diffuse, oxygen contained in the insulator 280b can be confined. Thereby, oxygen can be effectively supplied to the oxide semiconductor 230.
　また、絶縁体２８０ｃに酸素に対するバリア性を有する絶縁体を用いることで、熱処理などを行った際に、酸化物半導体２３０の絶縁体２５０と接する領域への、絶縁体２５０を介した絶縁体２８０からの酸素供給量が減少する。このとき、図１７Ａ及び図１７Ｂに示すように、領域２３０ｎａ及び領域２３０ｎｂが、絶縁体２５０側に伸長する場合がある。 Furthermore, by using an insulator that has barrier properties against oxygen as the insulator 280c, when heat treatment or the like is performed, the insulator 280c is applied to the region of the oxide semiconductor 230 that is in contact with the insulator 250 via the insulator 250. The amount of oxygen supplied from the At this time, as shown in FIGS. 17A and 17B, the region 230na and the region 230nb may extend toward the insulator 250.
　また、絶縁体２８０ｂに含まれる酸素によって、導電体１２０、及び導電体２４０が酸化され、抵抗が高くなってしまう場合がある。絶縁体２８０ｂと導電体１２０との間に絶縁体２８０ａを設けることにより、導電体１２０が酸化され、抵抗が高くなることを抑制できる。また、絶縁体２８０ｂと導電体２４０との間に絶縁体２８０ｃを設けることにより、導電体２４０が酸化され、抵抗が高くなることを抑制できる。それとともに、絶縁体２８０ｂから酸化物半導体２３０へ供給される酸素の量が増え、酸化物半導体２３０中の酸素欠損を低減できる。 Furthermore, the conductor 120 and the conductor 240 may be oxidized by the oxygen contained in the insulator 280b, resulting in increased resistance. By providing the insulator 280a between the insulator 280b and the conductor 120, it is possible to prevent the conductor 120 from being oxidized and increasing its resistance. Further, by providing the insulator 280c between the insulator 280b and the conductor 240, it is possible to suppress the conductor 240 from being oxidized and increasing its resistance. At the same time, the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and oxygen vacancies in the oxide semiconductor 230 can be reduced.
　また、酸化物半導体２３０の、絶縁体２８０ａに接する領域、及び絶縁体２８０ｃに接する領域は、絶縁体２８０ｂに接する領域と比較して、供給される酸素の量が少ない。よって、酸化物半導体２３０の、絶縁体２８０ａに接する領域、及び絶縁体２８０ｃに接する領域は、低抵抗化する場合がある。つまり、絶縁体２８０ａの膜厚を調整することで、ソース領域及びドレイン領域の一方として機能する領域２３０ｎａの範囲を制御できる。同様に、絶縁体２８０ｃの膜厚を調整することで、ソース領域及びドレイン領域の他方として機能する領域２３０ｎｂの範囲を制御できる。 Further, the amount of oxygen supplied to the region of the oxide semiconductor 230 in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in the region in contact with the insulator 280b. Therefore, a region of the oxide semiconductor 230 in contact with the insulator 280a and a region in contact with the insulator 280c may have low resistance. That is, by adjusting the film thickness of the insulator 280a, the range of the region 230na that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb functioning as the other of the source region and the drain region can be controlled.
　上述のように、ソース領域及びドレイン領域は、絶縁体２８０ａ及び絶縁体２８０ｃの膜厚で制御可能であるため、絶縁体２８０ａ及び絶縁体２８０ｃの膜厚は、トランジスタ２００に求める特性に合わせて、適宜設定すればよい。 As described above, the source region and the drain region can be controlled by the film thicknesses of the insulator 280a and the insulator 280c, so the film thicknesses of the insulator 280a and the insulator 280c can be adjusted according to the characteristics required for the transistor 200. You can set it as appropriate.
　例えば、図１７Ａ及び図１７Ｂに示すように、絶縁体２８０ｃの膜厚と、絶縁体２８０ａの膜厚とは、同じ又は概略同じであってもよい。又は、例えば、図１７Ｃ及び図１７Ｄに示すように、絶縁体２８０ａの膜厚が、絶縁体２８０ｃの膜厚よりも大きくてもよい。図１７Ｃ及び図１７Ｄに示す構成にすることで、領域２３０ｎａを、開口部２９０における導電体２６０の底部に近づけることができる。このとき、領域２３０ｉの範囲が狭まる構成ともいえる。これにより、トランジスタ２００のオン電流を向上させることができる。 For example, as shown in FIGS. 17A and 17B, the thickness of the insulator 280c and the thickness of the insulator 280a may be the same or approximately the same. Alternatively, for example, as shown in FIGS. 17C and 17D, the thickness of the insulator 280a may be greater than the thickness of the insulator 280c. With the configuration shown in FIGS. 17C and 17D, the region 230na can be brought close to the bottom of the conductor 260 in the opening 290. At this time, it can be said that the range of the region 230i is narrowed. Thereby, the on-state current of the transistor 200 can be improved.
　また、図１７Ｃ及び図１７Ｄでは、平坦化された絶縁体２８０ｂ上に、絶縁体２８０ｃを設ける構成を示しているが、本発明はこれに限られるものではない。例えば、絶縁体２８０ｂの平坦化処理を行うことなく、絶縁体２８０ｃを成膜してもよい。平坦化処理を行わないことにより、製造コストを低くできるとともに、生産歩留まりを高めることができる。また、絶縁体２８０ａ、絶縁体２８０ｂ、及び絶縁体２８０ｃを、大気環境に曝さずに連続して成膜することができる。大気開放せずに成膜することで、絶縁体２８０ａ乃至絶縁体２８０ｃ上に大気環境からの不純物または水分が付着することを防ぐことができ、絶縁体２８０ａと絶縁体２８０ｂとの界面近傍、及び絶縁体２８０ｂと絶縁体２８０ｃとの界面近傍を清浄に保つことができる。 Furthermore, although FIGS. 17C and 17D show a configuration in which an insulator 280c is provided on a flattened insulator 280b, the present invention is not limited to this. For example, the insulator 280c may be formed without performing planarization treatment on the insulator 280b. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased. Further, the insulator 280a, the insulator 280b, and the insulator 280c can be continuously formed without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to prevent impurities or moisture from adhering to the insulators 280a to 280c. The vicinity of the interface between the insulator 280b and the insulator 280c can be kept clean.
　絶縁体２８０ａ及び絶縁体２８０ｃにはそれぞれ、後述する［絶縁体］の項目に記載の、水素に対するバリア性を有する絶縁体を用いることが好ましい。これにより、トランジスタの外から絶縁体２８０ａ又は絶縁体２８０ｃを介して、酸化物半導体２３０に水素が拡散することを抑制できる。窒化シリコン膜、及び窒化酸化シリコン膜は、それぞれ、自身からの不純物（例えば、水及び水素）の放出が少なく、酸素及び水素が透過しにくい特徴を有するため、絶縁体２８０ａ及び絶縁体２８０ｃに好適に用いることができる。なお、絶縁体２８０ａ及び絶縁体２８０ｃは、互いに同じ材料を用いてもよく、異なる材料を用いてもよい。 It is preferable to use an insulator having barrier properties against hydrogen as described in the section [Insulator] described later for each of the insulator 280a and the insulator 280c. Thereby, hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 280a or the insulator 280c. A silicon nitride film and a silicon nitride oxide film are suitable for the insulator 280a and the insulator 280c because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. It can be used for. Note that the insulator 280a and the insulator 280c may be made of the same material or different materials.
　また、絶縁体２８０ａとして、後述する［絶縁体］の項目に記載の、水素を捕獲するまたは水素を固着する機能を有する絶縁体を用いることが好ましい。このような構成にすることで、絶縁体２８０ａの下方から酸化物半導体２３０に水素が拡散することを抑制し、さらに酸化物半導体２３０の水素を捕獲または固着し、酸化物半導体２３０の水素濃度を低減できる。また、絶縁体２８０ａの上方から絶縁体１３０に水素が拡散することを抑制し、さらに絶縁体１３０の水素を捕獲または固着し、絶縁体１３０の水素濃度を低減できる。絶縁体２８０ａとしては、酸化マグネシウム、酸化アルミニウム、又は酸化ハフニウムなどを用いることができる。また、例えば、絶縁体２８０ａとして、酸化アルミニウムと、当該酸化アルミニウム上の窒化シリコンの積層膜を用いてもよい。 Further, as the insulator 280a, it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. Such a structure suppresses hydrogen from diffusing into the oxide semiconductor 230 from below the insulator 280a, and further captures or fixes hydrogen in the oxide semiconductor 230 to reduce the hydrogen concentration in the oxide semiconductor 230. Can be reduced. Further, it is possible to suppress hydrogen from diffusing into the insulator 130 from above the insulator 280a, and further capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130. As the insulator 280a, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 280a.
　絶縁体２８０ａの膜厚は、絶縁体２８０ｂの膜厚より小さいことが好ましい。また、絶縁体２８０ｃの膜厚は、絶縁体２８０ｂの膜厚より小さいことが好ましい。絶縁体２８０ａ及び絶縁体２８０ｃの膜厚はそれぞれ、１ｎｍ以上１５ｎｍ以下が好ましく、２ｎｍ以上１０ｎｍ以下がより好ましく、３ｎｍ以上７ｎｍ以下がより好ましく、さらには３ｎｍ以上５ｎｍ以下が好ましい。絶縁体２８０ｂの膜厚は、３ｎｍ以上３０ｎｍ以下が好ましく、５ｎｍ以上２０ｎｍ以下がより好ましく、７ｎｍ以上１５ｎｍ以下がより好ましい。絶縁体２８０ａ乃至絶縁体２８０ｃの膜厚を前述の範囲とすることで、酸化物半導体２３０中、特にチャネル形成領域の酸素欠損を低減できる。 The film thickness of the insulator 280a is preferably smaller than the film thickness of the insulator 280b. Further, the thickness of the insulator 280c is preferably smaller than the thickness of the insulator 280b. The thickness of the insulator 280a and the insulator 280c is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and even more preferably 3 nm or more and 5 nm or less. The thickness of the insulator 280b is preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 7 nm or more and 15 nm or less. By setting the film thicknesses of the insulators 280a to 280c within the above range, oxygen vacancies in the oxide semiconductor 230, particularly in the channel formation region, can be reduced.
　例えば、絶縁体２８０ａ及び絶縁体２８０ｃに窒化シリコンを用い、絶縁体２８０ｂに酸化シリコンを用いることが好ましい。このとき、絶縁体２８０ａ及び絶縁体２８０ｃのそれぞれは、少なくともシリコンと、窒素と、を有する。また、絶縁体２８０ｂは、少なくともシリコンと、酸素と、を有する。 For example, it is preferable to use silicon nitride for the insulator 280a and the insulator 280c, and to use silicon oxide for the insulator 280b. At this time, each of the insulator 280a and the insulator 280c includes at least silicon and nitrogen. Further, the insulator 280b includes at least silicon and oxygen.
　なお、図１７Ａ及び図１７Ｂでは絶縁体２８０が３層の積層構造である構成を示しているが、本発明の一態様はこれに限られない。絶縁体２８０は、２層、または４層以上の積層構造であってもよい。 Note that although FIGS. 17A and 17B show a structure in which the insulator 280 has a three-layer stacked structure, one embodiment of the present invention is not limited to this. The insulator 280 may have a laminated structure of two layers or four or more layers.
　絶縁体２８３には、後述する［絶縁体］の項目に記載の、水素に対するバリア性を有する絶縁体を用いることが好ましい。これにより、トランジスタの外から絶縁体２５０を介して、酸化物半導体２３０に水素が拡散することを抑制できる。窒化シリコン膜、及び窒化酸化シリコン膜は、それぞれ、自身からの不純物（例えば、水及び水素）の放出が少なく、酸素及び水素が透過しにくい特徴を有するため、絶縁体２８３に好適に用いることができる。 As the insulator 283, it is preferable to use an insulator that has barrier properties against hydrogen and is described in the section [Insulator] described below. Thereby, hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 250. A silicon nitride film and a silicon nitride oxide film are suitable for use as the insulator 283 because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. can.
　また、絶縁体２８３として、後述する［絶縁体］の項目に記載の、水素を捕獲するまたは水素を固着する機能を有する絶縁体を用いることが好ましい。このような構成にすることで、絶縁体２８３の上方から酸化物半導体２３０に水素が拡散することを抑制し、さらに酸化物半導体２３０の水素を捕獲または固着し、酸化物半導体２３０の水素濃度を低減できる。絶縁体２８３としては、酸化マグネシウム、酸化アルミニウム、又は酸化ハフニウムなどを用いることができる。また、例えば、絶縁体２８３として、酸化アルミニウムと、当該酸化アルミニウム上の窒化シリコンの積層膜を用いてもよい。 Furthermore, as the insulator 283, it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With this structure, hydrogen is prevented from diffusing into the oxide semiconductor 230 from above the insulator 283, and hydrogen in the oxide semiconductor 230 is captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230. Can be reduced. As the insulator 283, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 283.
　図１Ｂ及び図１Ｃには、導電体１２０の上面と酸化物半導体２３０の下面とが接する領域を有する構成を示しているが、本発明はこれに限られるものではない。例えば、導電体１２０と酸化物半導体２３０との間に導電体を設けてもよい。 Although FIGS. 1B and 1C show a structure in which the upper surface of the conductor 120 and the lower surface of the oxide semiconductor 230 are in contact with each other, the present invention is not limited to this. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230.
　例えば、図１８Ａ及び図１８Ｂに示すように、導電体１２０と酸化物半導体２３０との間に導電体１２５を設ける構成にしてもよい。導電体１２５として、後述する［導電体］の項目に記載の酸素を含む導電性材料を用いることが好ましい。導電体１２５として酸素を含む導電性材料を用いることで、導電体１２５が酸素を吸収しても導電性を維持することができる。また、酸化物半導体２３０中の酸素が導電体１２０に拡散するのを抑制できる。導電体１２５として、例えば、インジウム錫酸化物、シリコンを添加したインジウム錫酸化物、インジウム亜鉛酸化物などを単層または積層で用いることができる。 For example, as shown in FIGS. 18A and 18B, a structure may be adopted in which a conductor 125 is provided between the conductor 120 and the oxide semiconductor 230. As the conductor 125, it is preferable to use an oxygen-containing conductive material described in the "Conductor" section below. By using a conductive material containing oxygen as the conductor 125, conductivity can be maintained even if the conductor 125 absorbs oxygen. Furthermore, diffusion of oxygen in the oxide semiconductor 230 into the conductor 120 can be suppressed. As the conductor 125, for example, indium tin oxide, silicon-added indium tin oxide, indium zinc oxide, or the like can be used in a single layer or in a stacked layer.
　また、図１８Ａ及び図１８Ｂに示すように、絶縁体１３０の側端部と導電体１１５の側端部が一致する構造にしてもよい。このような構造にすることで、絶縁体１３０と導電体１１５を同一のマスクを用いて形成することができ、記憶装置の作製工程を簡略化することができる。 Alternatively, as shown in FIGS. 18A and 18B, a structure may be adopted in which the side end of the insulator 130 and the side end of the conductor 115 coincide. With this structure, the insulator 130 and the conductor 115 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.
　図１Ｂ及び図１Ｃでは、酸化物半導体２３０が、開口部２９０における導電体２４０の側面に接する領域と、導電体２４０の上面の一部に接する領域と、を有する構成を示している。なお、本発明はこれに限られるものではない。 FIGS. 1B and 1C show a configuration in which the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the upper surface of the conductor 240. Note that the present invention is not limited to this.
　例えば、図１９Ｂ及び図１９Ｃに示すように、酸化物半導体２３０は、開口部２９０における導電体２４０と接する領域を有する構成にしてもよい。このとき、酸化物半導体２３０の上面の高さは、導電体２４０の上面の高さと一致する。このような構成にすることで、開口部２９０における導電体２４０と酸化物半導体２３０の界面から、導電体２４０のＹ方向の側端部までの距離を小さくすることができる。よって、導電体２４０のＹ方向の幅を小さくすることができ、導電体２４０が配置される間隔を小さくすることができる。したがって、記憶装置の微細化または高集積化を図ることができる。なお、図１９Ａは、図１９Ｂ及び図１９Ｃに示す記憶装置の平面図である。 For example, as shown in FIGS. 19B and 19C, the oxide semiconductor 230 may have a region in contact with the conductor 240 in the opening 290. At this time, the height of the top surface of the oxide semiconductor 230 matches the height of the top surface of the conductor 240. With this configuration, the distance from the interface between the conductor 240 and the oxide semiconductor 230 in the opening 290 to the side end of the conductor 240 in the Y direction can be reduced. Therefore, the width of the conductor 240 in the Y direction can be reduced, and the intervals at which the conductors 240 are arranged can be reduced. Therefore, the storage device can be miniaturized or highly integrated. Note that FIG. 19A is a plan view of the storage device shown in FIGS. 19B and 19C.
　図１Ｂ及び図１Ｃでは、導電体２４０が、絶縁体２８０上に設けられる構成を示している。また、絶縁体２５０の導電体２４０と重ならない領域が、絶縁体２８０の上面と接する領域を有する構成を示している。なお、本発明はこれに限られるものではない。 FIGS. 1B and 1C show a configuration in which the conductor 240 is provided on an insulator 280. Further, a configuration is shown in which a region of the insulator 250 that does not overlap with the conductor 240 has a region in contact with the upper surface of the insulator 280. Note that the present invention is not limited to this.
　例えば、図２０Ｂ及び図２０Ｃに示すように、絶縁体２８０上に絶縁体２８１を設け、絶縁体２８１に埋め込まれるように導電体２４０を設ける構成にしてもよい。このとき、導電体２４０の上面の高さは、絶縁体２８１の上面の高さと一致することが好ましい。このような構成にすることで、導電体２６０から導電体２４０（特に導電体２４０の側端部）までの物理距離を大きくでき、導電体２６０と導電体２４０のショートを防ぐことができる。なお、図２０Ａは、図２０Ｂ及び図２０Ｃに示す記憶装置の平面図である。 For example, as shown in FIGS. 20B and 20C, an insulator 281 may be provided on an insulator 280, and a conductor 240 may be provided so as to be embedded in the insulator 281. At this time, the height of the top surface of the conductor 240 preferably matches the height of the top surface of the insulator 281. With this configuration, it is possible to increase the physical distance from the conductor 260 to the conductor 240 (particularly the side ends of the conductor 240), and to prevent short circuits between the conductor 260 and the conductor 240. Note that FIG. 20A is a plan view of the storage device shown in FIGS. 20B and 20C.
　絶縁体２８１は、層間膜として機能するため、比誘電率が低い材料を用いることが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体２８１としては、後述する［絶縁体］の項目に記載の、比誘電率が低い材料を含む絶縁体を、単層または積層で用いることができる。 Since the insulator 281 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 281, an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form.
　なお、図１Ａ及び図１Ｃに示すように、導電体２６０は延在させて、配線としても機能させている。また、導電体２６０は複数のトランジスタで共有している。ただし、これに限られることなく、導電体２６０の上に、配線として機能する導電体を設ける構成にしてもよい。 Note that, as shown in FIGS. 1A and 1C, the conductor 260 is extended to function as a wiring. Further, the conductor 260 is shared by a plurality of transistors. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor that functions as a wiring is provided on the conductor 260.
　例えば、図２１Ａ乃至図２１Ｃに示すように、導電体２６０上に導電体２６５を設けてもよい。なお、図２１Ａ乃至図２１Ｃでは、導電体２６０は、各トランジスタに一個ずつ設けられている。なお、導電体２６０は、必ずしも各トランジスタに一個ずつ設ける必要はない。例えば、導電体２６０を複数のトランジスタで共有する構成にしてもよい。 For example, as shown in FIGS. 21A to 21C, a conductor 265 may be provided on the conductor 260. Note that in FIGS. 21A to 21C, one conductor 260 is provided for each transistor. Note that it is not necessarily necessary to provide one conductor 260 for each transistor. For example, the conductor 260 may be shared by a plurality of transistors.
　上記のような構成において、導電体２６０は、絶縁体２８７に埋め込まれるように設けられることが好ましい。このとき、導電体２６０の上面の高さと絶縁体２８７の上面の高さが一致することが好ましい。このような構成にすることで、導電体２６０と導電体２４０のショートを防ぐことができる。 In the above configuration, the conductor 260 is preferably provided so as to be embedded in the insulator 287. At this time, it is preferable that the height of the top surface of the conductor 260 and the height of the top surface of the insulator 287 match. With such a configuration, short circuit between the conductor 260 and the conductor 240 can be prevented.
　導電体２６５は、トランジスタ２００のゲートに電気的に接続される、配線ＷＬとして機能する。導電体２６５としては、前述した［導電体］の項目に記載の導電体を、単層または積層で用いることができる。例えば、導電体２６５として、タングステンなどの、導電性が高い導電性材料を用いることができる。 The conductor 265 functions as a wiring WL that is electrically connected to the gate of the transistor 200. As the conductor 265, the conductor described in the above-mentioned [Conductor] item can be used in a single layer or a laminated form. For example, as the conductor 265, a highly conductive material such as tungsten can be used.
　導電体２６５は、絶縁体２８９に埋め込まれるように設けることが好ましい。このとき、導電体２６５の上面の高さと絶縁体２８９の上面の高さが一致することが好ましい。 The conductor 265 is preferably provided so as to be embedded in the insulator 289. At this time, it is preferable that the height of the top surface of the conductor 265 and the height of the top surface of the insulator 289 match.
　絶縁体２８７及び絶縁体２８９は、層間膜として機能するため、比誘電率が低い材料を用いることが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体２８７及び絶縁体２８９としては、前述した［絶縁体］の項目に記載の、比誘電率が低い材料を含む絶縁体を、単層または積層で用いることができる。 Since the insulator 287 and the insulator 289 function as interlayer films, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 287 and the insulator 289, an insulator containing a material with a low dielectric constant, which is described in the above-mentioned [Insulator] section, can be used in a single layer or in a stacked layer.
　図２１Ｂにおいて、導電体２６５の側端部が導電体２６０の側端部と一致しているが、本発明はこれに限られるものではない。例えば、導電体２６５の側端部は、導電体２６０の側端部より外側に位置してもよいし、導電体２６０の側端部より内側に位置してもよい。 In FIG. 21B, the side end of the conductor 265 coincides with the side end of the conductor 260, but the present invention is not limited thereto. For example, the side end portion of the conductor 265 may be located outside the side end portion of the conductor 260, or may be located inside the side end portion of the conductor 260.
＜記憶装置の構成材料＞
　以下では、記憶装置に用いることができる構成材料について説明する。 <Materials of storage device>
Constituent materials that can be used for the storage device will be described below.
［基板］
　トランジスタ２００及び容量素子１００を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 [substrate]
As the substrate for forming the transistor 200 and the capacitor 100, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator) substrate. Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are substrates containing metal nitrides, substrates containing metal oxides, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
［絶縁体］
　絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 [Insulator]
Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.
　例えば、トランジスタの微細化、および高集積化が進むと、ゲート絶縁体の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁体として機能する絶縁体に、ｈｉｇｈ−ｋ材料を用いることで物理膜厚を保ちながら、トランジスタ動作時の低電圧化が可能となる。また、ゲート絶縁体として機能する絶縁体の等価酸化膜厚（ＥＯＴ：Ｅｑｕｉｖａｌｅｎｔ　Ｏｘｉｄｅ　Ｔｈｉｃｋｎｅｓｓ）の薄膜化が可能となる。一方、層間膜として機能する絶縁体には、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減できる。したがって、絶縁体の機能に応じて、材料を選択するとよい。なお、比誘電率が低い材料は、絶縁耐力が大きい材料でもある。 For example, as transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinning of gate insulators. By using a high-k material for the insulator that functions as a gate insulator, it is possible to maintain the physical film thickness and lower the voltage during transistor operation. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator. On the other hand, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring lines. Therefore, the material should be selected depending on the function of the insulator. Note that a material with a low dielectric constant is also a material with a high dielectric strength.
　比誘電率が高い（ｈｉｇｈ−ｋ）材料としては、例えば、酸化アルミニウム、酸化ガリウム、酸化ハフニウム、酸化タンタル、酸化ジルコニウム、ハフニウムジルコニウム酸化物、アルミニウム及びハフニウムを有する酸化物、アルミニウム及びハフニウムを有する酸化窒化物、シリコン及びハフニウムを有する酸化物、シリコン及びハフニウムを有する酸化窒化物、並びに、シリコン及びハフニウムを有する窒化物などが挙げられる。 Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, and oxides containing aluminum and hafnium. Examples include nitride, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, and nitride containing silicon and hafnium.
　比誘電率が低い材料としては、例えば、酸化シリコン、酸化窒化シリコン、及び窒化酸化シリコンなどの無機絶縁材料、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート、及びアクリルなどの樹脂が挙げられる。また、比誘電率が低い他の無機絶縁材料として、例えば、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、並びに、炭素及び窒素を添加した酸化シリコンなどが挙げられる。また、例えば、空孔を有する酸化シリコンが挙げられる。なお、これらの酸化シリコンは、窒素を含んでもよい。 Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and resins such as acrylic. Can be mentioned. Other inorganic insulating materials having a low dielectric constant include, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. Further, for example, silicon oxide having pores may be used. Note that these silicon oxides may contain nitrogen.
　また、金属酸化物を用いたトランジスタは、不純物及び酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。不純物及び酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム、またはタンタルを含む絶縁体を、単層で、または積層で用いることができる。具体的には、不純物及び酸素の透過を抑制する機能を有する絶縁体として、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、酸化タンタルなどの金属酸化物、窒化アルミニウム、窒化酸化シリコン、窒化シリコンなどの金属窒化物を用いることができる。 Further, by surrounding a transistor using a metal oxide with an insulator that has the function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators having the function of suppressing permeation of impurities and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, Insulators including neodymium, hafnium, or tantalum can be used in single layers or in stacks. Specifically, insulators that have the function of suppressing the permeation of impurities and oxygen include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
　また、ゲート絶縁体などの、半導体層と接する絶縁体、または半導体層の近傍に設ける絶縁体は、過剰酸素を含む領域を有する絶縁体であることが好ましい。例えば、過剰酸素を含む領域を有する絶縁体を半導体層と接する、または半導体層の近傍に設ける構造とすることで、半導体層が有する酸素欠損を低減することができる。過剰酸素を含む領域を形成しやすい絶縁体として、酸化シリコン、酸化窒化シリコン、または空孔を有する酸化シリコンなどが挙げられる。 Further, it is preferable that an insulator such as a gate insulator that is in contact with the semiconductor layer or an insulator provided near the semiconductor layer is an insulator that has a region containing excess oxygen. For example, oxygen vacancies in the semiconductor layer can be reduced by providing a structure in which an insulator having a region containing excess oxygen is in contact with the semiconductor layer or in the vicinity of the semiconductor layer. Examples of insulators that can easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
　また、酸素に対するバリア性を有する絶縁体としては、アルミニウム及びハフニウムの一方または両方を含む酸化物、ハフニウム及びシリコンを含む酸化物（ハフニウムシリケート）、酸化マグネシウム、酸化ガリウム、ガリウム亜鉛酸化物、インジウムガリウム亜鉛酸化物、窒化シリコン、並びに、窒化酸化シリコンなどが挙げられる。また、アルミニウム及びハフニウムの一方または両方を含む酸化物として、酸化アルミニウム、酸化ハフニウム、アルミニウム及びハフニウムを含む酸化物（ハフニウムアルミネート）、などが挙げられる。 Insulators with barrier properties against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, and indium gallium. Examples include zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
　また、水素に対するバリア性を有する絶縁体としては、酸化アルミニウム、酸化マグネシウム、酸化ハフニウム、酸化ガリウム、インジウムガリウム亜鉛酸化物、窒化シリコンまたは窒化酸化シリコン等が挙げられる。 Examples of insulators having barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
　酸素に対するバリア性を有する絶縁体、及び水素に対するバリア性を有する絶縁体は、酸素及び水素の一方または両方に対するバリア性を有する絶縁体といえる。 An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to be an insulator that has a barrier property against one or both of oxygen and hydrogen.
　また、水素を捕獲するまたは固着する機能を有する絶縁体として、マグネシウムを含む酸化物、またはアルミニウム及びハフニウムの一方または両方を含む酸化物が挙げられる。また、これらの酸化物は、アモルファス構造を有することがより好ましい。アモルファス構造を有する酸化物では、酸素原子がダングリングボンドを有しており、当該ダングリングボンドで水素を捕獲するまたは固着する性質を有する場合がある。なお、これらの金属酸化物は、アモルファス構造であることが好ましいが、一部に結晶領域が形成されていてもよい。 Further, examples of the insulator having the function of capturing or fixing hydrogen include an oxide containing magnesium, or an oxide containing one or both of aluminum and hafnium. Moreover, it is more preferable that these oxides have an amorphous structure. In an oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may capture or fix hydrogen. Note that these metal oxides preferably have an amorphous structure, but a crystalline region may be formed in part.
　なお、本明細書等において、バリア絶縁膜とは、バリア性を有する絶縁膜のことを指す。また、バリア性とは、対応する物質が拡散し難い性質（対応する物質が透過し難い性質、対応する物質の透過性が低い性質、または、対応する物質の拡散を抑制する機能ともいう）とする。なお、対応する物質を捕獲するまたは固着する（ゲッタリングともいう）機能を、バリア性と言い換えることができる。なお、対応する物質として記載される場合の水素は、例えば、水素原子、水素分子、並びに、水分子及びＯＨ−などの水素と結合した物質などの少なくとも一を指す。また、対応する物質として記載される場合の不純物は、特段の明示が無い限り、チャネル形成領域または半導体層における不純物を指し、例えば、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの少なくとも一を指す。また、対応する物質として記載される場合の酸素は、例えば、酸素原子、酸素分子などの少なくとも一を指す。具体的には、酸素に対するバリア性とは、酸素原子、酸素分子等の少なくとも一が拡散し難い性質を指す。 Note that in this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. In addition, barrier property refers to the property that the corresponding substance is difficult to diffuse (also referred to as the property that the corresponding substance is difficult to permeate, the property that the corresponding substance has low permeability, or the ability to suppress the diffusion of the corresponding substance). do. Note that the function of capturing or fixing a corresponding substance (also referred to as gettering) can be referred to as barrier property. Note that hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH − . In addition, unless otherwise specified, impurities described as corresponding substances refer to impurities in the channel forming region or semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, oxidation Refers to at least one of nitrogen molecules ( N2O , NO, NO2, etc.), copper atoms, etc. Further, when described as a corresponding substance, oxygen refers to at least one of, for example, an oxygen atom or an oxygen molecule. Specifically, the barrier property against oxygen refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is difficult to diffuse.
［導電体］
　導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または前述した金属元素を成分とする合金か、前述した金属元素を組み合わせた合金等を用いることが好ましい。前述した金属元素を成分とする合金として、当該合金の窒化物、または当該合金の酸化物を用いてもよい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 [conductor]
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the following, an alloy containing the above-mentioned metal elements as a component, an alloy containing a combination of the above-mentioned metal elements, or the like. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, use of tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. It is preferable. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
　また、タンタルを含む窒化物、チタンを含む窒化物、モリブデンを含む窒化物、タングステンを含む窒化物、ルテニウムを含む窒化物、タンタル及びアルミニウムを含む窒化物、またはチタン及びアルミニウムを含む窒化物などの窒素を含む導電性材料、酸化ルテニウム、ストロンチウム及びルテニウムを含む酸化物、またはランタン及びニッケルを含む酸化物などの酸素を含む導電性材料、チタン、タンタル、またはルテニウムなどの金属元素を含む材料は、酸化しにくい導電性材料、酸素の拡散を抑制する機能を有する導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。なお、酸素を含む導電性材料として、酸化タングステンを含むインジウム酸化物、酸化チタンを含むインジウム酸化物、インジウム錫酸化物、酸化チタンを含むインジウム錫酸化物、シリコンを添加したインジウム錫酸化物、インジウム亜鉛酸化物、及び、酸化タングステンを含むインジウム亜鉛酸化物などが挙げられる。本明細書等では、酸素を含む導電性材料を用いて成膜される導電膜を、酸化物導電膜と呼ぶことがある。 In addition, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, etc. Conductive materials containing nitrogen, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, materials containing metallic elements such as titanium, tantalum, or ruthenium. A conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen is preferable. In addition, as conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium Examples include zinc oxide and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.
　また、タングステン、銅、またはアルミニウムを主成分とする導電性材料は、導電性が高いため、好ましい。 Furthermore, conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
　また、上記の材料で形成される導電層を複数積層して用いてもよい。例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。 Furthermore, a plurality of conductive layers formed of the above materials may be stacked and used. For example, a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
　なお、トランジスタのチャネル形成領域に金属酸化物を用いる場合において、ゲート電極として機能する導電体には、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から脱離した酸素がチャネル形成領域に供給されやすくなる。 Note that when a metal oxide is used in the channel formation region of a transistor, the conductor that functions as the gate electrode has a stacked structure that combines a material containing the aforementioned metal element and a conductive material containing oxygen. It is preferable. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.
　特に、ゲート電極として機能する導電体として、チャネルが形成される金属酸化物に含まれる金属元素及び酸素を含む導電性材料を用いることが好ましい。また、前述した金属元素及び窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、及び、シリコンを添加したインジウム錫酸化物のうち一つまたは複数を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、チャネルが形成される金属酸化物に含まれる水素を捕獲することができる場合がある。または、外方の絶縁体などから混入する水素を捕獲することができる場合がある。 In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as the gate electrode. Further, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon. One or more of the added indium tin oxides may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed in from an external insulator or the like.
［金属酸化物］
　金属酸化物は、格子欠陥を有する場合がある。格子欠陥とは、原子空孔、異種原子などの点欠陥、転位などの線欠陥、結晶粒界などの面欠陥、空隙などの体積欠陥がある。また、格子欠陥の生成の要因としては、構成元素の原子数の比率のずれ（構成原子の過不足）、及び不純物などがある。 [Metal oxide]
Metal oxides may have lattice defects. Lattice defects include atomic vacancies, point defects such as foreign atoms, line defects such as dislocations, planar defects such as crystal grain boundaries, and volume defects such as voids. Furthermore, factors for the generation of lattice defects include a deviation in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms), impurities, and the like.
　金属酸化物をトランジスタの半導体層に用いる場合、金属酸化物中の格子欠陥は、キャリアの生成または捕獲などを引き起こす要因となりうる。よって、格子欠陥が多い金属酸化物をトランジスタの半導体層に用いると、当該トランジスタの電気特性が不安定となる恐れがある。よって、トランジスタの半導体層に用いる金属酸化物は、格子欠陥が少ないことが好ましい。 When a metal oxide is used in a semiconductor layer of a transistor, lattice defects in the metal oxide can be a factor that causes generation or trapping of carriers. Therefore, if a metal oxide with many lattice defects is used in a semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, the metal oxide used for the semiconductor layer of the transistor preferably has few lattice defects.
　金属酸化物を用いたトランジスタは、特に、金属酸化物中のチャネル形成領域に酸素欠損（ＶＯ）及び不純物が存在すると、電気特性が変動しやすく、信頼性が悪くなる場合がある。また、酸素欠損近傍の水素が、酸素欠損に水素が入った欠陥（ＶＯＨ）を形成し、キャリアとなる電子を生成する場合がある。このため、金属酸化物中のチャネル形成領域に酸素欠損が含まれていると、トランジスタはノーマリーオン特性となりやすい。したがって、金属酸化物中のチャネル形成領域では、酸素欠損及び不純物はできる限り低減されていることが好ましい。言い換えると、金属酸化物中のチャネル形成領域は、キャリア濃度が低減され、ｉ型化（真性化）または実質的にｉ型化されていることが好ましい。 In transistors using metal oxides, electrical characteristics tend to fluctuate and reliability may deteriorate, especially when oxygen vacancies (V O ) and impurities are present in a channel formation region in the metal oxide. Further, hydrogen near the oxygen vacancy may form a defect (V OH ) in which hydrogen is present in the oxygen vacancy, and generate electrons that become carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to exhibit normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel forming region in the metal oxide. In other words, it is preferable that the channel forming region in the metal oxide has a reduced carrier concentration and is made i-type (intrinsic) or substantially i-type.
　金属酸化物中に存在しやすい格子欠陥の種類、及び格子欠陥の存在量は、金属酸化物の構造または金属酸化物の成膜方法などによって異なる。 The type of lattice defects that are likely to exist in a metal oxide and the amount of lattice defects that exist vary depending on the structure of the metal oxide, the method of forming a metal oxide film, etc.
　金属酸化物の構造は、単結晶構造と、それ以外の構造（非単結晶の構造）と、に分けられる。非単結晶の構造としては、例えば、ＣＡＡＣ構造、多結晶（ｐｏｌｙｃｒｙｓｔａｌｌｉｎｅ）構造、ｎｃ構造、擬似非晶質（ａ−ｌｉｋｅ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ）構造、及び非晶質構造などがある。ａ−ｌｉｋｅ構造は、ｎｃ構造と非晶質構造との間の構造を有する。なお、結晶構造の分類については、後述する。 The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). Examples of non-single crystal structures include a CAAC structure, a polycrystalline structure, a nc structure, an amorphous-like (a-like) structure, and an amorphous structure. The a-like structure has a structure between an nc structure and an amorphous structure. Note that the classification of crystal structures will be described later.
　また、ａ−ｌｉｋｅ構造を有する金属酸化物、及び非晶質構造を有する金属酸化物は、鬆または低密度領域を有する。すなわち、ａ−ｌｉｋｅ構造を有する金属酸化物、及び非晶質構造を有する金属酸化物は、ｎｃ構造を有する金属酸化物及びＣＡＡＣ構造を有する金属酸化物と比べて、結晶性が低い。また、ａ−ｌｉｋｅ構造を有する金属酸化物は、ｎｃ構造を有する金属酸化物及びＣＡＡＣ構造を有する金属酸化物と比べて、金属酸化物中の水素濃度が高い。よって、ａ−ｌｉｋｅ構造を有する金属酸化物、及び非晶質構造を有する金属酸化物では、格子欠陥が生成されやすい。 Furthermore, metal oxides having an a-like structure and metal oxides having an amorphous structure have cavities or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Further, a metal oxide having an a-like structure has a higher hydrogen concentration than a metal oxide having an nc structure and a metal oxide having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
　よって、トランジスタの半導体層には、結晶性の高い金属酸化物を用いることが好ましい。例えば、ＣＡＡＣ構造を有する金属酸化物、または単結晶構造の金属酸化物を用いることが好ましい。当該金属酸化物をトランジスタに用いることで、良好な電気特性を有するトランジスタを実現できる。また、信頼性の高いトランジスタを実現できる。 Therefore, it is preferable to use a highly crystalline metal oxide for the semiconductor layer of the transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using the metal oxide in a transistor, a transistor with good electrical characteristics can be realized. Furthermore, a highly reliable transistor can be realized.
　また、トランジスタのチャネル形成領域には、当該トランジスタのオン電流が大きくなる金属酸化物を用いることが好ましい。当該トランジスタのオン電流を大きくするには、当該トランジスタに用いる金属酸化物のキャリア移動度を高くするとよい。金属酸化物のキャリア移動度を高くするには、キャリア（ｎチャネル型トランジスタの場合は、電子）の伝送を向上させる、または、キャリアの伝送に寄与する散乱因子を低減する必要がある。なお、キャリアは、チャネル形成領域を介して、ソースからドレインに流れる。よって、キャリアがチャネル長方向に流れやすいチャネル形成領域を設けることで、トランジスタのオン電流を大きくすることができる。 Further, it is preferable to use a metal oxide that increases the on-state current of the transistor for the channel formation region of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the carrier mobility of the metal oxide used in the transistor. In order to increase the carrier mobility of a metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or to reduce the scattering factors that contribute to the transmission of carriers. Note that carriers flow from the source to the drain via the channel formation region. Therefore, by providing a channel formation region in which carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.
　ここで、チャネル形成領域を含む金属酸化物に、結晶性の高い金属酸化物を用いることが好ましい。さらに、当該結晶は、複数の層（例えば、第１の層と、第２の層と、第３の層）が積層された結晶構造を有することが好ましい。つまり、当該結晶は、層状の結晶構造（層状結晶、層状構造ともいう）を有する。このとき、当該結晶のｃ軸の向きは、複数の層が積層される方向となる。当該結晶を有する金属酸化物には、例えば、単結晶酸化物半導体、ＣＡＡＣ−ＯＳなどが含まれる。 Here, it is preferable to use a highly crystalline metal oxide as the metal oxide containing the channel forming region. Furthermore, it is preferable that the crystal has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). At this time, the c-axis of the crystal is oriented in the direction in which a plurality of layers are stacked. Examples of metal oxides having such crystals include single-crystal oxide semiconductors, CAAC-OS, and the like.
　また、上記結晶のｃ軸を、金属酸化物の被形成面または膜表面に対する法線方向に配向することが好ましい。これにより、複数の層は、金属酸化物の被形成面または膜表面に対して、平行または概略平行に配置される。つまり、複数の層は、チャネル長方向に広がる。 Furthermore, it is preferable that the c-axis of the crystal is oriented in the normal direction to the surface on which the metal oxide is formed or the film surface. Thereby, the plurality of layers are arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. That is, the multiple layers extend in the channel length direction.
　例えば、上記のような３層の層状の結晶構造は、以下のような構造になる。第１の層は、当該第１の層が有する金属が中心に存在する酸素の八面体形の、原子の配位構造を有する。また、第２の層は、当該第２の層が有する金属が中心に存在する酸素の三方両錐形または四面体形の、原子の配位構造を有する。また、第３の層は、当該第３の層が有する金属が中心に存在する酸素の三方両錐形または四面体形の、原子の配位構造を有する。 For example, the three-layered crystal structure described above has the following structure. The first layer has an octahedral atomic coordination structure of oxygen in which the metal of the first layer is located at the center. Further, the second layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the second layer exists at the center. Further, the third layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the third layer exists at the center.
　上記結晶の結晶構造として、例えば、ＹｂＦｅ２Ｏ４型構造、Ｙｂ２Ｆｅ３Ｏ７型構造、これらの変形型構造などがある。 Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
　さらに、第１の層乃至第３の層のそれぞれは、一の金属元素、または、価数が同じである複数の金属元素と、酸素とで構成されることが好ましい。なお、第１の層を構成する一または複数の金属元素の価数と、第２の層を構成する一または複数の金属元素の価数と、は同じであることが好ましい。また、第１の層と、第２の層とは、同じ金属元素を有してもよい。また、第１の層を構成する一または複数の金属元素の価数と、第３の層を構成する一または複数の金属元素の価数と、は異なることが好ましい。 Further, each of the first to third layers is preferably composed of one metal element or a plurality of metal elements having the same valence and oxygen. Note that it is preferable that the valence of one or more metal elements forming the first layer is the same as the valence of one or more metal elements forming the second layer. Moreover, the first layer and the second layer may have the same metal element. Further, it is preferable that the valence of one or more metal elements forming the first layer is different from the valence of one or more metal elements forming the third layer.
　上記構成にすることで、金属酸化物の結晶性を向上し、当該金属酸化物のキャリア移動度を高くすることができる。よって、当該金属酸化物をトランジスタのチャネル形成領域に用いることで、トランジスタのオン電流が大きくなり、当該トランジスタの電気特性を向上させることができる。 With the above structure, the crystallinity of the metal oxide can be improved and the carrier mobility of the metal oxide can be increased. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
　本発明の一態様の金属酸化物として、例えば、インジウム酸化物、ガリウム酸化物、及び亜鉛酸化物が挙げられる。本発明の一態様の金属酸化物は、少なくともインジウム（Ｉｎ）または亜鉛（Ｚｎ）を含むことが好ましい。また、金属酸化物は、インジウムと、元素Ｍと、亜鉛と、の中から選ばれる二または三を有することが好ましい。なお、元素Ｍは、酸素との結合エネルギーが高い金属元素又は半金属元素であり、例えば、酸素との結合エネルギーがインジウムよりも高い金属元素又は半金属元素である。元素Ｍとして、具体的には、アルミニウム、ガリウム、錫、イットリウム、チタン、バナジウム、クロム、マンガン、鉄、コバルト、ニッケル、ジルコニウム、モリブデン、ハフニウム、タンタル、タングステン、ランタン、セリウム、ネオジム、マグネシウム、カルシウム、ストロンチウム、バリウム、ホウ素、シリコン、ゲルマニウム、及びアンチモンなどが挙げられる。金属酸化物が有する元素Ｍは、上記元素のいずれか一種または複数種であることが好ましく、アルミニウム、ガリウム、錫、及びイットリウムから選ばれた一種または複数種であることがより好ましく、ガリウムがさらに好ましい。金属酸化物が有する元素Ｍがガリウムである場合、本発明の一態様の金属酸化物は、インジウム、ガリウム、及び亜鉛の中から選ばれるいずれか一または複数を有することが好ましい。なお、本明細書等において、金属元素と半金属元素をまとめて「金属元素」と呼ぶことがあり、本明細書等に記載の「金属元素」には半金属元素が含まれることがある。 Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc. Note that the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium. Specifically, the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable. When the element M included in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include semimetal elements.
　本発明の一態様の金属酸化物半導体として、例えば、インジウム亜鉛酸化物（Ｉｎ−Ｚｎ酸化物）、インジウム錫酸化物（Ｉｎ−Ｓｎ酸化物）、インジウムチタン酸化物（Ｉｎ−Ｔｉ酸化物）、インジウムガリウム酸化物（Ｉｎ−Ｇａ酸化物）、インジウムガリウムアルミニウム酸化物（Ｉｎ−Ｇａ−Ａｌ酸化物）、インジウムガリウム錫酸化物（Ｉｎ−Ｇａ−Ｓｎ酸化物）、ガリウム亜鉛酸化物（Ｇａ−Ｚｎ酸化物、ＧＺＯとも記す）、アルミニウム亜鉛酸化物（Ａｌ−Ｚｎ酸化物、ＡＺＯとも記す）、インジウムアルミニウム亜鉛酸化物（Ｉｎ−Ａｌ−Ｚｎ酸化物、ＩＡＺＯとも記す）、インジウム錫亜鉛酸化物（Ｉｎ−Ｓｎ−Ｚｎ酸化物）、インジウムチタン亜鉛酸化物（Ｉｎ−Ｔｉ−Ｚｎ酸化物）、インジウムガリウム亜鉛酸化物（Ｉｎ−Ｇａ−Ｚｎ酸化物、ＩＧＺＯとも記す）、インジウムガリウム錫亜鉛酸化物（Ｉｎ−Ｇａ−Ｓｎ−Ｚｎ酸化物、ＩＧＺＴＯとも記す）、インジウムガリウムアルミニウム亜鉛酸化物（Ｉｎ−Ｇａ−Ａｌ−Ｚｎ酸化物、ＩＧＡＺＯまたはＩＡＧＺＯとも記す）などを用いることができる。または、シリコンを含むインジウム錫酸化物、ガリウム錫酸化物（Ｇａ−Ｓｎ酸化物）、アルミニウム錫酸化物（Ａｌ−Ｓｎ酸化物）などが挙げられる。 Examples of the metal oxide semiconductor of one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), Indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (also written as Al-Zn oxide, AZO), indium aluminum zinc oxide (also written as In-Al-Zn oxide, IAZO), indium tin zinc oxide (In -Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In -Ga-Sn-Zn oxide (also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. containing silicon may be used.
　金属酸化物に含まれる全ての金属元素の原子数の和に対するインジウムの原子数の割合を高くすることにより、トランジスタの電界効果移動度を高めることができる。 By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased.
　なお、金属酸化物は、インジウムに代えて、元素周期表における周期番号が大きい金属元素の一種または複数種を有してもよい。又は、金属酸化物は、インジウムに加えて、元素周期表における周期番号が大きい金属元素の一種または複数種を有してもよい。金属元素の軌道の重なりが大きいほど、金属酸化物におけるキャリア伝導は大きくなる傾向がある。よって、元素周期表における周期番号が大きい金属元素を含むことで、トランジスタの電界効果移動度を高めることができる場合がある。元素周期表における周期番号が大きい金属元素として、第５周期に属する金属元素、及び第６周期に属する金属元素などが挙げられる。当該金属元素として、具体的には、イットリウム、ジルコニウム、銀、カドミウム、錫、アンチモン、バリウム、鉛、ビスマス、ランタン、セリウム、プラセオジム、ネオジム、プロメチウム、サマリウム、及びユウロピウムなどが挙げられる。なお、ランタン、セリウム、プラセオジム、ネオジム、プロメチウム、サマリウム、及びユウロピウムは、軽希土類元素と呼ばれる。 Note that instead of indium, the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements. Alternatively, in addition to indium, the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large periodic number in the periodic table of elements, it may be possible to increase the field effect mobility of the transistor. Examples of metal elements with large period numbers in the periodic table of elements include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
　また、金属酸化物は、非金属元素の一種または複数種を有してもよい。金属酸化物が非金属元素を有することで、トランジスタの電界効果移動度を高めることができる場合がある。非金属元素として、例えば、炭素、窒素、リン、硫黄、セレン、フッ素、塩素、臭素、及び水素などが挙げられる。 Furthermore, the metal oxide may contain one or more types of nonmetallic elements. When the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
　また、金属酸化物に含まれる全ての金属元素の原子数の和に対する亜鉛の原子数の割合を高くすることにより、結晶性の高い金属酸化物となり、金属酸化物中の不純物の拡散を抑制できる。したがって、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。 In addition, by increasing the ratio of the number of zinc atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. . Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
　また、金属酸化物に含まれる全ての金属元素の原子数の和に対する元素Ｍの原子数の割合を高くすることにより、金属酸化物に酸素欠損が形成されるのを抑制できる。したがって、酸素欠損に起因するキャリア生成が抑制され、オフ電流の小さいトランジスタとすることができる。また、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。 Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with low off-state current can be obtained. Further, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
　また、金属酸化物に含まれる全ての金属元素の原子数の和に対するＩｎの原子数の割合を高くすることにより、トランジスタは大きいオン電流、及び高い周波数特性を得ることができる。 Furthermore, by increasing the ratio of the number of In atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the transistor can obtain a large on-current and high frequency characteristics.
　本実施の形態では、金属酸化物として、Ｉｎ−Ｇａ−Ｚｎ酸化物を例に挙げて説明する場合がある。 In this embodiment, an In-Ga-Zn oxide may be used as an example of the metal oxide.
　上記の層状の結晶構造を有する金属酸化物を形成するためには、一層ずつ原子を堆積することが好ましい。本発明の一態様の金属酸化物の成膜方法では、ＡＬＤ法を用いるため、上記の層状の結晶構造を有する金属酸化物を形成することが容易である。 In order to form a metal oxide having the above layered crystal structure, it is preferable to deposit atoms one layer at a time. Since the method for forming a metal oxide film of one embodiment of the present invention uses an ALD method, it is easy to form a metal oxide having the above-described layered crystal structure.
　ＡＬＤ法としては、プリカーサ及びリアクタントの反応を熱エネルギーのみで行う熱ＡＬＤ（Ｔｈｅｒｍａｌ　ＡＬＤ）法、及び、プラズマ励起されたリアクタントを用いるプラズマＡＬＤ（ＰＥＡＬＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＡＬＤ）法などが挙げられる。 Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.
　ＡＬＤ法は、一層ずつ原子を堆積することができるため、極薄の成膜が可能、アスペクト比の高い構造への成膜が可能、ピンホールなどの欠陥の少ない成膜が可能、被覆性に優れた成膜が可能、及び低温での成膜が可能、などの効果がある。また、ＰＥＡＬＤ法は、プラズマを利用することで、より低温での成膜が可能となり好ましい場合がある。なお、ＡＬＤ法で用いるプリカーサには炭素または塩素などの元素を含むものがある。このため、ＡＬＤ法により設けられた膜は、他の成膜法により設けられた膜と比較して、炭素または塩素などの元素を多く含む場合がある。なお、これらの元素の定量は、ＸＰＳまたは二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）を用いて行うことができる。なお、本発明の一態様の金属酸化物の成膜方法では、ＡＬＤ法を用いるが、成膜時の基板温度が高い条件の採用、及び、不純物除去処理の実施の一方または双方を適用するため、これらを適用せずにＡＬＤ法を用いる場合に比べて、膜中に含まれる炭素及び塩素の量が少ないことがある。 Since the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with high aspect ratios, to form films with few defects such as pinholes, and to improve coverage. It has advantages such as being able to form an excellent film and being able to form a film at a low temperature. Further, the PEALD method may be preferable because it can form a film at a lower temperature by using plasma. Note that some precursors used in the ALD method include elements such as carbon or chlorine. For this reason, a film formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that these elements can be quantified using XPS or secondary ion mass spectrometry (SIMS). Note that although the method for forming a metal oxide film of one embodiment of the present invention uses an ALD method, one or both of the conditions of high substrate temperature during film formation and the implementation of impurity removal treatment may be applied. , the amount of carbon and chlorine contained in the film may be smaller than when ALD is used without applying these.
　ＡＬＤ法は、ターゲットなどから放出される粒子が堆積する成膜方法とは異なり、被処理物の表面における反応により膜が形成される成膜方法である。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いスパッタリング法、またはＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。例えば、スパッタリング法を用いて、第１の金属酸化物を成膜し、当該第１の金属酸化物上にＡＬＤ法を用いて、第２の金属酸化物を成膜する方法などが挙げられる。例えば、上記第１の金属酸化物が結晶部を有する場合、上記第２の金属酸化物が当該結晶部を核として、結晶成長する場合がある。 The ALD method is a film-forming method in which a film is formed by a reaction on the surface of an object, unlike a film-forming method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as sputtering or CVD, which have a high film formation rate. For example, a method may be used in which a first metal oxide is deposited using a sputtering method, and a second metal oxide is deposited on the first metal oxide using an ALD method. For example, when the first metal oxide has a crystal part, the second metal oxide may grow crystals using the crystal part as a nucleus.
　ＡＬＤ法は、原料ガスの導入量によって、得られる膜の組成を制御することができる。例えば、ＡＬＤ法では、原料ガスの導入量、導入回数（パルス回数ともいう）、１パルスに要する時間（パルス時間ともいう）などを調節することによって、任意の組成の膜を成膜することができる。また、例えば、ＡＬＤ法では、成膜しながら原料ガスを変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスを変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送及び圧力調整に掛かる時間を要さない分、成膜に掛かる時間を短くすることができる。したがって、記憶装置の生産性を高めることができる場合がある。 In the ALD method, the composition of the resulting film can be controlled by the amount of raw material gas introduced. For example, in the ALD method, it is possible to form a film of any composition by adjusting the amount of raw material gas introduced, the number of times it is introduced (also called the number of pulses), the time required for one pulse (also called pulse time), etc. can. Furthermore, for example, in the ALD method, by changing the raw material gas during film formation, it is possible to form a film whose composition changes continuously. When forming a film while changing the raw material gas, compared to forming a film using multiple film formation chambers, the time required for film formation can be shortened by eliminating the time required for transport and pressure adjustment. can. Therefore, it may be possible to increase the productivity of the storage device.
［［金属酸化物を有するトランジスタ］］
　続いて、金属酸化物（酸化物半導体）をトランジスタに用いる場合について説明する。以下では、半導体層に酸化物半導体を用いたトランジスタをＯＳトランジスタと記し、半導体層にシリコンを用いたトランジスタをＳｉトランジスタと記す場合がある。 [[Transistor with metal oxide]]
Next, a case where a metal oxide (oxide semiconductor) is used in a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer may be referred to as an OS transistor, and a transistor using silicon for a semiconductor layer may be referred to as an Si transistor.
　本発明の一態様の金属酸化物（酸化物半導体）をトランジスタに用いることで、高い電界効果移動度のトランジスタを実現できる。また、信頼性の高いトランジスタを実現できる。また、微細化または高集積化されたトランジスタを実現できる。例えば、チャネル長が２ｎｍ以上３０ｎｍ以下のトランジスタを作製しうる。 By using the metal oxide (oxide semiconductor) of one embodiment of the present invention in a transistor, a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
　トランジスタのチャネル形成領域には、キャリア濃度の低い酸化物半導体を用いることが好ましい。例えば、酸化物半導体のチャネル形成領域のキャリア濃度は１×１０１８ｃｍ−３以下、好ましくは１×１０１７ｃｍ−３以下、より好ましくは１×１０１５ｃｍ−３以下、より好ましくは１×１０１３ｃｍ−３以下、より好ましくは１×１０１１ｃｍ−３以下、さらに好ましくは１×１０１０ｃｍ−３未満であり、１×１０−９ｃｍ−３以上である。なお、酸化物半導体膜のキャリア濃度を低くする場合においては、酸化物半導体膜中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性または実質的に高純度真性と言う。なお、キャリア濃度の低い酸化物半導体を、高純度真性または実質的に高純度真性な酸化物半導体と呼ぶ場合がある。 It is preferable to use an oxide semiconductor with a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm −3 or less, preferably 1×10 17 cm −3 or less, more preferably 1×10 15 cm −3 or less, more preferably 1× It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density. In this specification and the like, low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic. Note that an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
　また、高純度真性または実質的に高純度真性である酸化物半導体膜は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。 Further, since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect level density, the trap level density may also be low.
　また、酸化物半導体のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い酸化物半導体にチャネル形成領域が形成されるトランジスタは、電気特性が不安定となる場合がある。 Furthermore, charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
　従って、トランジスタの電気特性を安定にするためには、酸化物半導体中の不純物濃度を低減することが有効である。また、酸化物半導体中の不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、炭素、窒素などが挙げられる。なお、酸化物半導体中の不純物とは、例えば、酸化物半導体を構成する主成分以外をいう。例えば、濃度が０．１ａｔｏｍｉｃ％未満の元素は不純物といえる。 Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in an adjacent film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be considered an impurity.
　また、酸化物半導体のバンドギャップは、シリコンのバンドギャップ（代表的には１．１ｅＶ）よりも大きいことが好ましく、好ましくは２ｅＶ以上、より好ましくは２．５ｅＶ以上、さらに好ましくは３．０ｅＶ以上である。シリコンよりも、バンドギャップの大きい酸化物半導体を用いることで、トランジスタのオフ電流（Ｉｏｆｆとも呼称する）を低減できる。 Further, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is. By using an oxide semiconductor having a larger band gap than silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.
　また、Ｓｉトランジスタでは、トランジスタの微細化が進むにつれて、短チャネル効果（Ｓｈｏｒｔ　Ｃｈａｎｎｅｌ　Ｅｆｆｅｃｔ：ＳＣＥともいう）が発現する。そのため、Ｓｉトランジスタでは、微細化が困難となる。短チャネル効果が発現する要因の一つとして、シリコンのバンドギャップが小さいことが挙げられる。一方、ＯＳトランジスタは、バンドギャップの大きい半導体材料である、酸化物半導体を用いるため、短チャネル効果の抑制を図ることができる。別言すると、ＯＳトランジスタは、短チャネル効果がない、または短チャネル効果が極めて少ないトランジスタである。 Further, in Si transistors, as transistors become smaller, a short channel effect (also referred to as SCE) occurs. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the short channel effect is that silicon has a small band gap. On the other hand, since an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed. In other words, an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
　なお、短チャネル効果とは、トランジスタの微細化（チャネル長の縮小）に伴って顕在化する電気特性の劣化である。短チャネル効果の具体例としては、しきい値電圧の低下、サブスレッショルドスイング値（Ｓ値と表記することがある）の増大、漏れ電流の増大などがある。ここで、Ｓ値とは、ドレイン電圧一定にてドレイン電流を１桁変化させるサブスレッショルド領域でのゲート電圧の変化量をいう。 Note that the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length). Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
　また、短チャネル効果に対する耐性の指標として、特性長（Ｃｈａｒａｃｔｅｒｉｓｔｉｃ　Ｌｅｎｇｔｈ）が広く用いられている。特性長とは、チャネル形成領域のポテンシャルの曲がりやすさの指標である。特性長が小さいほどポテンシャルが急峻に立ち上がるため、短チャネル効果に強いといえる。 Additionally, characteristic length is widely used as an index of resistance to short channel effects. The characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
　ＯＳトランジスタは蓄積型のトランジスタであり、Ｓｉトランジスタは反転型のトランジスタである。したがって、Ｓｉトランジスタと比較して、ＯＳトランジスタは、ソース領域−チャネル形成領域間の特性長、及びドレイン領域−チャネル形成領域間の特性長が小さい。したがって、ＯＳトランジスタは、Ｓｉトランジスタよりも短チャネル効果に強い。すなわち、チャネル長の短いトランジスタを作製したい場合においては、ＯＳトランジスタは、Ｓｉトランジスタよりも好適である。 The OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
　チャネル形成領域がｉ型または実質的にｉ型となるまで、酸化物半導体のキャリア濃度を下げた場合においても、短チャネルのトランジスタではＣｏｎｄｕｃｔｉｏｎ−Ｂａｎｄ−Ｌｏｗｅｒｉｎｇ（ＣＢＬ）効果により、チャネル形成領域の伝導帯下端が下がるため、ソース領域またはドレイン領域と、チャネル形成領域との間の伝導帯下端のエネルギー差は、０．１ｅＶ以上０．２ｅＶ以下まで小さくなる可能性がある。これにより、ＯＳトランジスタは、チャネル形成領域がｎ−型の領域となり、ソース領域及びドレイン領域がｎ＋型の領域となる、ｎ＋／ｎ−／ｎ＋の蓄積型ｊｕｎｃｔｉｏｎ−ｌｅｓｓトランジスタ構造、または、ｎ＋／ｎ−／ｎ＋の蓄積型ｎｏｎ−ｊｕｎｃｔｉｏｎトランジスタ構造と、捉えることもできる。 Even when the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less. As a result, the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n − /n + storage type non-junction transistor structure.
　ＯＳトランジスタを、上記の構造とすることで、記憶装置を微細化または高集積化しても良好な電気特性を有することができる。例えば、ＯＳトランジスタのチャネル長又はゲート長が、２０ｎｍ以下、１５ｎｍ以下、１０ｎｍ以下、７ｎｍ以下、または６ｎｍ以下であって、１ｎｍ以上、３ｎｍ以上、または５ｎｍ以上であっても、良好な電気特性を得ることができる。一方で、Ｓｉトランジスタは、短チャネル効果が発現するため、２０ｎｍ以下、または１５ｎｍ以下のゲート長とすることが困難な場合がある。したがって、ＯＳトランジスタは、Ｓｉトランジスタと比較してチャネル長の短いトランジスタに好適に用いることができる。なお、ゲート長とは、トランジスタ動作時にキャリアがチャネル形成領域内部を移動する方向における、ゲート電極の長さである。 By making the OS transistor have the above structure, it can have good electrical characteristics even if the memory device is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
　また、ＯＳトランジスタを微細化することで、トランジスタの高周波特性を向上させることができる。具体的には、トランジスタの遮断周波数を向上させることができる。ＯＳトランジスタのゲート長が上記範囲のいずれかである場合、トランジスタの遮断周波数を、例えば室温環境下で、５０ＧＨｚ以上、好ましくは１００ＧＨｚ以上、さらに好ましくは１５０ＧＨｚ以上とすることができる。 Further, by miniaturizing the OS transistor, the high frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
　以上の説明の通り、ＯＳトランジスタは、Ｓｉトランジスタと比較し、オフ電流が小さいこと、チャネル長の短いトランジスタの作製が可能なこと、といった優れた効果を有する。 As explained above, OS transistors have superior effects compared to Si transistors, such as lower off-state current and the ability to manufacture transistors with shorter channel lengths.
［［金属酸化物中の不純物］］
　ここで、金属酸化物（酸化物半導体）中における各不純物の影響について説明する。 [[Impurities in metal oxides]]
Here, the influence of each impurity in the metal oxide (oxide semiconductor) will be explained.
　酸化物半導体において、第１４族元素の一つであるシリコンまたは炭素が含まれると、酸化物半導体において欠陥準位が形成される。このため、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域における炭素の濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下とする。また、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域におけるシリコンの濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下とする。 When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms/cm 3 or less, preferably 5×10 19 atoms/cm 3 or less, more preferably 3×10 19 atoms /cm 3 or less, more preferably 1×10 19 atoms/cm 3 or less, more preferably 3×10 18 atoms/cm 3 or less, even more preferably 1×10 18 atoms/cm 3 or less. Further, the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms/cm 3 or less, preferably 5×10 19 atoms/cm 3 or less, and more preferably 3×10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1×10 19 atoms/cm 3 or less, more preferably 3×10 18 atoms/cm 3 or less, even more preferably 1×10 18 atoms/cm 3 or less.
　また、酸化物半導体において、窒素が含まれると、キャリアである電子が生じ、キャリア濃度が増加し、ｎ型化しやすい。この結果、窒素が含まれている酸化物半導体を半導体に用いたトランジスタはノーマリーオン特性となりやすい。または、酸化物半導体において、窒素が含まれると、トラップ準位が形成される場合がある。この結果、トランジスタの電気特性が不安定となる場合がある。このため、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域における窒素濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 Further, when nitrogen is contained in an oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and the semiconductor becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when an oxide semiconductor contains nitrogen, a trap level may be formed in some cases. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms/cm 3 or less, preferably 5×10 19 atoms/cm 3 or less, and more preferably 1×10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5×10 18 atoms/cm 3 or less, more preferably 1×10 18 atoms/cm 3 or less, still more preferably 5×10 17 atoms/cm 3 or less.
　また、酸化物半導体に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。従って、水素が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、酸化物半導体のチャネル形成領域における水素はできる限り低減されていることが好ましい。具体的には、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域における水素濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３未満、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３未満、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３未満とする。 Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1×10 20 atoms/cm 3 , preferably less than 5×10 19 atoms/cm 3 , more preferably 1×10 19 atoms/cm 3 , more preferably less than 5×10 18 atoms/cm 3 , even more preferably less than 1×10 18 atoms/cm 3 .
　また、酸化物半導体にアルカリ金属またはアルカリ土類金属が含まれると、欠陥準位を形成し、キャリアを生成する場合がある。従って、アルカリ金属またはアルカリ土類金属が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域中のアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。 Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. Therefore, the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms/cm 3 or less, preferably 2×10 16 atoms/cm 3 or less. .
　不純物が十分に低減された酸化物半導体をトランジスタのチャネル形成領域に用いることで、安定した電気特性を付与することができる。 By using an oxide semiconductor with sufficiently reduced impurities for the channel formation region of the transistor, stable electrical characteristics can be imparted.
［その他の半導体材料］
　酸化物半導体２３０は、トランジスタのチャネル形成領域を含む半導体層と言い換えることができる。半導体層に用いることができる半導体材料は、上述の金属酸化物に限られない。半導体層として、バンドギャップを有する半導体材料（ゼロギャップ半導体ではない半導体材料）を用いてもよい。例えば、単体元素の半導体、化合物半導体、又は層状物質（原子層物質、２次元材料などともいう）などを半導体材料に用いることが好ましい。 [Other semiconductor materials]
The oxide semiconductor 230 can be referred to as a semiconductor layer including a channel formation region of a transistor. Semiconductor materials that can be used for the semiconductor layer are not limited to the metal oxides mentioned above. A semiconductor material having a band gap (semiconductor material that is not a zero-gap semiconductor) may be used as the semiconductor layer. For example, it is preferable to use a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, two-dimensional material, etc.) as the semiconductor material.
　ここで、本明細書等において、層状物質とは、層状の結晶構造を有する材料群の総称である。層状の結晶構造は、共有結合またはイオン結合によって形成される層が、ファンデルワールス力のような、共有結合またはイオン結合よりも弱い結合を介して積層している構造である。層状物質は、単位層内における電気伝導性が高く、つまり、２次元電気伝導性が高い。半導体として機能し、かつ、２次元電気伝導性の高い材料をチャネル形成領域に用いることで、オン電流の大きいトランジスタを提供できる。 Here, in this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds that are weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the channel formation region, a transistor with a large on-current can be provided.
　半導体材料に用いることができる単体元素の半導体として、シリコン、及びゲルマニウムなどが挙げられる。半導体層に用いることができるシリコンとして、単結晶シリコン、多結晶シリコン、微結晶シリコン、及び非晶質シリコンが挙げられる。多結晶シリコンとして、例えば、低温ポリシリコン（ＬＴＰＳ：Ｌｏｗ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｐｏｌｙ　Ｓｉｌｉｃｏｎ）が挙げられる。 Examples of single element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
　半導体材料に用いることができる化合物半導体として、炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、窒化ホウ素、及びヒ化ホウ素などが挙げられる。半導体層に用いることができる窒化ホウ素は、アモルファス構造を含むことが好ましい。半導体層に用いることができるヒ化ホウ素は、立方晶構造の結晶を含むことが好ましい。 Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure. Boron arsenide that can be used in the semiconductor layer preferably contains crystals with a cubic crystal structure.
　層状物質として、グラフェン、シリセン、炭窒化ホウ素、カルコゲン化物などがある。層状物質としての炭窒化ホウ素は、炭素原子、窒素原子、及びホウ素原子が平面上に六角形格子構造で配列している。カルコゲン化物は、カルコゲンを含む化合物である。また、カルコゲンは、第１６族に属する元素の総称であり、酸素、硫黄、セレン、テルル、ポロニウム、リバモリウムが含まれる。また、カルコゲン化物として、遷移金属カルコゲナイド、１３族カルコゲナイドなどが挙げられる。 Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. A chalcogenide is a compound containing chalcogen. Further, chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Furthermore, examples of the chalcogenide include transition metal chalcogenides, group 13 chalcogenides, and the like.
　半導体層として、例えば、半導体として機能する遷移金属カルコゲナイドを用いることが好ましい。半導体層として適用可能な遷移金属カルコゲナイドとして、具体的には、硫化モリブデン（代表的にはＭｏＳ２）、セレン化モリブデン（代表的にはＭｏＳｅ２）、モリブデンテルル（代表的にはＭｏＴｅ２）、硫化タングステン（代表的にはＷＳ２）、セレン化タングステン（代表的にはＷＳｅ２）、タングステンテルル（代表的にはＷＴｅ２）、硫化ハフニウム（代表的にはＨｆＳ２）、セレン化ハフニウム（代表的にはＨｆＳｅ２）、硫化ジルコニウム（代表的にはＺｒＳ２）、セレン化ジルコニウム（代表的にはＺｒＳｅ２）などが挙げられる。上述の遷移金属カルコゲナイドを、半導体層に適用することで、オン電流が大きい記憶装置を提供できる。 As the semiconductor layer, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specifically, transition metal chalcogenides that can be used as a semiconductor layer include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), Tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically Examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ). By applying the above transition metal chalcogenide to a semiconductor layer, a memory device with a large on-current can be provided.
＜記憶装置の作製方法例１＞
　次に、図１Ａ乃至図１Ｃに示す、本発明の一態様である記憶装置の作製方法を、図２２Ａ乃至図３２Ｃを用いて説明する。 <Example 1 of manufacturing method of storage device>
Next, a method for manufacturing the storage device shown in FIGS. 1A to 1C, which is one embodiment of the present invention, will be described with reference to FIGS. 22A to 32C.
　図２２Ａ乃至図３２Ｃにおいて、各図のＡは、平面図を示す。また、各図のＢはそれぞれ、各図のＡにＡ１−Ａ２の一点鎖線で示す部位に対応する断面図である。また、各図のＣはそれぞれ、各図のＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図である。なお、各図のＡの平面図では、図の明瞭化のために一部の要素を省いている。 In FIGS. 22A to 32C, A in each figure indicates a plan view. Further, B in each figure is a sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure. Further, C in each figure is a sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure. In addition, in the plan view A of each figure, some elements are omitted for clarity of the figure.
　以下において、絶縁体を形成するための絶縁性材料、導電体を形成するための導電性材料、または半導体を形成するための半導体材料は、スパッタリング法、ＣＶＤ法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法、パルスレーザー堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ法などを適宜用いて成膜することができる。 In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is used by sputtering method, CVD method, molecular beam epitaxy (MBE). The film can be formed using an appropriate method such as epitaxy method, pulsed laser deposition (PLD) method, or ALD method.
　なお、スパッタリング法にはスパッタリング用電源に高周波電源を用いるＲＦスパッタリング法、直流電源を用いるＤＣスパッタリング法、さらにパルス的に電極に印加する電圧を変化させるパルスＤＣスパッタリング法がある。ＲＦスパッタリング法は主に絶縁膜を成膜する場合に用いられ、ＤＣスパッタリング法は主に金属導電膜を成膜する場合に用いられる。また、パルスＤＣスパッタリング法は、主に、酸化物、窒化物、炭化物などの化合物をリアクティブスパッタリング法で成膜する際に用いられる。 Note that sputtering methods include an RF sputtering method that uses a high frequency power source as a sputtering power source, a DC sputtering method that uses a DC power source, and a pulsed DC sputtering method that changes the voltage applied to the electrode in a pulsed manner. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal conductive film. Further, the pulsed DC sputtering method is mainly used when forming a film of a compound such as an oxide, nitride, or carbide by a reactive sputtering method.
　なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ　ＣＶＤ）法などに分類できる。さらに用いる原料ガスによって金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　ＣＶＤ）法に分けることができる。 Note that the CVD method can be classified into a plasma CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD (Photo CVD) method that uses light, etc. Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.
　プラズマＣＶＤ法は、比較的低温で高品質の膜が得られる。また、熱ＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、記憶装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、記憶装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いない熱ＣＶＤ法の場合、こういったプラズマダメージが生じないため、記憶装置の歩留まりを高くすることができる。また、熱ＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 The plasma CVD method can obtain high-quality films at relatively low temperatures. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the memory device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of memory devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.
　また、ＡＬＤ法としては、プリカーサ及びリアクタントの反応を熱エネルギーのみで行う熱ＡＬＤ法、プラズマ励起されたリアクタントを用いるＰＥＡＬＤ法などを用いることができる。 Further, as the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, a PEALD method in which a plasma-excited reactant is used, etc. can be used.
　ＣＶＤ法およびＡＬＤ法は、ターゲットなどから放出される粒子が堆積するスパッタリング法とは異なる。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。 The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.
　また、ＣＶＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。例えば、ＣＶＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送または圧力調整に掛かる時間を要さない分、成膜に掛かる時間を短くすることができる。したがって、記憶装置の生産性を高めることができる場合がある。 Furthermore, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of source gases. For example, in the CVD method, by changing the flow rate ratio of source gases during film formation, it is possible to form a film whose composition changes continuously. When forming a film while changing the flow rate ratio of raw material gases, compared to forming a film using multiple film formation chambers, the time required for film formation is reduced because it does not require time for transport or pressure adjustment. can do. Therefore, it may be possible to increase the productivity of the storage device.
　また、ＡＬＤ法では、異なる複数種のプリカーサを同時に導入することで任意の組成の膜を成膜することができる。または、異なる複数種のプリカーサを導入する場合、各プリカーサのサイクル数を制御することで任意の組成の膜を成膜することができる。 Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing a plurality of different types of precursors. Alternatively, when a plurality of different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles for each precursor.
　まず、基板（図示しない）を準備し、当該基板上に絶縁体１４０を形成する（図２２Ａ乃至図２２Ｃ参照）。絶縁体１４０には、上述の絶縁性材料を適宜用いればよい。絶縁体１４０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。 First, a substrate (not shown) is prepared, and an insulator 140 is formed on the substrate (see FIGS. 22A to 22C). For the insulator 140, any of the above-mentioned insulating materials may be used as appropriate. The insulator 140 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
　次に、絶縁体１４０上に導電体１１０を形成する。導電体１１０には、上述の導電性材料を適宜用いればよい。導電体１１０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、導電体１１０として、ＣＶＤ法を用いて、タングステン、窒化チタンの順に成膜された積層膜を形成すればよい。 Next, the conductor 110 is formed on the insulator 140. For the conductor 110, the above-mentioned conductive material may be used as appropriate. The conductor 110 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the conductor 110, a stacked film of tungsten and titanium nitride may be formed in this order using a CVD method.
　なお、導電体１１０を加工して、Ｘ方向またはＹ方向に伸長する形状にしてもよい。導電体１１０の加工は、リソグラフィー法を用いて行えばよい。上記加工はドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。当該加工を行うことで、導電体１１０の側端部は、後に形成する絶縁体１３０によって覆われる。 Note that the conductor 110 may be processed into a shape that extends in the X direction or the Y direction. The conductor 110 may be processed using a lithography method. For the above processing, a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication. By performing this processing, the side end portions of the conductor 110 are covered with an insulator 130 that will be formed later.
　なお、リソグラフィー法では、まず、マスクを介してレジストを露光する。次に、露光された領域を、現像液を用いて除去または残存させてレジストマスクを形成する。次に、当該レジストマスクを介してエッチング処理することで導電体、半導体、または絶縁体などを所望の形状に加工することができる。例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ（Ｅｘｔｒｅｍｅ　Ｕｌｔｒａｖｉｏｌｅｔ）光などを用いて、レジストを露光することでレジストマスクを形成すればよい。また、基板と投影レンズとの間に液体（例えば水）を満たして露光する、液浸技術を用いてもよい。また、前述した光に代えて、電子ビームまたはイオンビームを用いてもよい。なお、電子ビームまたはイオンビームを用いる場合には、マスクは不要となる。なお、レジストマスクは、アッシングなどのドライエッチング処理を行う、ウェットエッチング処理を行う、ドライエッチング処理後にウェットエッチング処理を行う、またはウェットエッチング処理後にドライエッチング処理を行うことで、除去することができる。 Note that in the lithography method, the resist is first exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed area using a developer. Next, by etching through the resist mask, a conductor, semiconductor, insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing a resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Moreover, an electron beam or an ion beam may be used instead of the light described above. Note that when an electron beam or an ion beam is used, a mask is not required. Note that the resist mask can be removed by performing dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment.
　また、ドライエッチング装置としては、平行平板型電極を有する容量結合型プラズマ（ＣＣＰ：Ｃａｐａｃｉｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置を用いることができる。平行平板型電極を有する容量結合型プラズマエッチング装置は、平行平板型電極の一方の電極に高周波電圧を印加する構成でもよい。または平行平板型電極の一方の電極に複数の異なった高周波電圧を印加する構成でもよい。または平行平板型電極それぞれに同じ周波数の高周波電圧を印加する構成でもよい。または平行平板型電極それぞれに周波数の異なる高周波電圧を印加する構成でもよい。または高密度プラズマ源を有するドライエッチング装置を用いることができる。高密度プラズマ源を有するドライエッチング装置は、例えば、誘導結合型プラズマ（ＩＣＰ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置などを用いることができる。 Further, as the dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high frequency voltage is applied to one electrode of the parallel plate electrodes. Alternatively, a configuration may be adopted in which a plurality of different high frequency voltages are applied to one electrode of a parallel plate type electrode. Alternatively, a configuration may be adopted in which a high frequency voltage of the same frequency is applied to each of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which high frequency voltages having different frequencies are applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching device having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching device or the like can be used.
　次に、導電体１１０上に絶縁体１８０を形成する（図２２Ａ乃至図２２Ｃ参照）。絶縁体１８０には、上述の絶縁性材料を適宜用いればよい。絶縁体１８０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、絶縁体１８０として、スパッタリング法を用いて酸化シリコン膜を成膜すればよい。なお、絶縁体１８０は、成膜後にＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）処理を行なって、上面を平坦化させることが好ましい。なお、ＣＭＰ処理を行わなくてもよい場合がある。このとき、絶縁体１８０の上面は、上に凸の曲面形状を有する。平坦化処理を行わないことにより、製造コストを低くできるとともに、生産歩留まりを高めることができる。 Next, an insulator 180 is formed on the conductor 110 (see FIGS. 22A to 22C). The insulating material described above may be used as appropriate for the insulator 180. The insulator 180 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the insulator 180, a silicon oxide film may be formed using a sputtering method. Note that the insulator 180 is preferably subjected to CMP (Chemical Mechanical Polishing) treatment after film formation to flatten the upper surface. Note that there are cases where it is not necessary to perform CMP processing. At this time, the upper surface of the insulator 180 has an upwardly convex curved shape. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased.
　ここで、絶縁体１８０の膜厚は、容量素子１００の静電容量に対応するため、容量素子１００の静電容量の設計値に合わせて、絶縁体１８０の膜厚を適宜設定すればよい。 Here, since the film thickness of the insulator 180 corresponds to the capacitance of the capacitive element 100, the film thickness of the insulator 180 may be appropriately set according to the design value of the capacitance of the capacitive element 100.
　また、絶縁体１８０を、成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体１８０中の水素濃度を低減できる。 Furthermore, the hydrogen concentration in the insulator 180 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas.
　次に、絶縁体１８０の一部を加工して、導電体１２０に達する開口部１９０を形成する（図２３Ａ乃至図２３Ｃ参照）。開口部１９０の形成は、リソグラフィー法を用いて行えばよい。なお、開口部１９０の形状は、平面視において円形状にしているが、これに限られるものではない。例えば、開口部１９０の形状は、平面視において、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。 Next, a part of the insulator 180 is processed to form an opening 190 that reaches the conductor 120 (see FIGS. 23A to 23C). The opening 190 may be formed using a lithography method. Note that although the shape of the opening 190 is circular in plan view, it is not limited to this. For example, the shape of the opening 190 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners when viewed from above.
　前述したように、開口部１９０の側壁は、導電体１１０の上面に対して垂直であることが好ましい。このような構成にすることで、記憶装置の微細化または高集積化を図ることができる。なお、開口部１９０の側壁は、テーパー形状であってもよい。開口部１９０の側壁をテーパー形状にすることで、後述する導電体１１５となる導電膜などの被覆性が向上し、鬆などの欠陥を低減できる。 As mentioned above, the side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Note that the side wall of the opening 190 may have a tapered shape. By tapering the side wall of the opening 190, the coverage of a conductive film, which will be described later as a conductor 115, can be improved, and defects such as holes can be reduced.
　開口部１９０の最大幅（平面視において開口部１９０が円形である場合は最大径）の大きさは、微細であることが好ましい。例えば、開口部１９０の最大幅は、１００ｎｍ以下、６０ｎｍ以下、５０ｎｍ以下、４０ｎｍ以下、又は３０ｎｍ以下であって、５ｎｍ以上、又は１０ｎｍ以上であることが好ましい。このように、開口部１９０を微細に加工するには、ＥＵＶ光などの短波長の光、または電子ビームを用いたリソグラフィー法を用いることが好ましい。 It is preferable that the maximum width (maximum diameter when the opening 190 is circular in plan view) of the opening 190 is minute. For example, the maximum width of the opening 190 is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, and preferably 5 nm or more, or 10 nm or more. In order to finely process the opening 190 in this way, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.
　開口部１９０はアスペクト比が大きいため、異方性エッチングを用いて、絶縁体１８０の一部を加工することが好ましい。特に、ドライエッチング法による加工は、微細加工に適しているため好ましい。 Since the opening 190 has a large aspect ratio, it is preferable to process a part of the insulator 180 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing.
　上述したように、開口部１９０の最大幅は、開口部２９０の最大幅よりも大きいため、開口部１９０及び開口部２９０をそれぞれ異方性エッチングを用いて形成する場合、同じマスクを用いることは困難である。そこで、異方性エッチングを用いて絶縁体１８０の一部を加工して開口部を形成した後、等方性エッチングを用いて当該開口部の幅を広げることで開口部１９０を形成してもよい。このような工程で開口部１９０を形成する場合、開口部１９０及び開口部２９０を形成する際に行う異方性エッチングにおいて、同じマスクを用いることができる。これにより、マスク数を減らすことができ、記憶装置の低コスト化を図ることができる。 As described above, the maximum width of opening 190 is larger than the maximum width of opening 290, so when forming opening 190 and opening 290 using anisotropic etching, it is not possible to use the same mask. Have difficulty. Therefore, the opening 190 may be formed by processing a part of the insulator 180 using anisotropic etching to form an opening, and then widening the width of the opening using isotropic etching. good. When forming the opening 190 through such a process, the same mask can be used in anisotropic etching performed when forming the opening 190 and the opening 290. Thereby, the number of masks can be reduced, and the cost of the storage device can be reduced.
　次に、開口部１９０の底部及び側壁、並びに絶縁体１８０の上面の少なくとも一部に接して、導電体１１５となる導電膜を成膜する。当該導電膜には、上述の導電体１１５に適用可能な導電体を適宜用いればよい。当該導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。ここで、当該導電膜は、アスペクト比の大きい開口部１９０の底部及び側壁に接して形成されることが好ましい。よって、当該導電膜の成膜は、被覆性が良好な成膜方法を用いることが好ましく、ＣＶＤ法またはＡＬＤ法などを用いることがより好ましい。例えば、当該導電膜として、ＣＶＤ法を用いて、窒化チタン膜を成膜すればよい。 Next, a conductive film that will become the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180. For the conductive film, a conductor that can be used as the conductor 115 described above may be used as appropriate. The conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the conductive film is preferably formed in contact with the bottom and sidewalls of the opening 190 having a large aspect ratio. Therefore, for forming the conductive film, it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like. For example, a titanium nitride film may be formed as the conductive film using a CVD method.
　次に、導電体１１５となる導電膜を、リソグラフィー法を用いて加工し、導電体１１５を形成する（図２４Ａ乃至図２４Ｃ参照）。これにより、導電体１１５の一部が、開口部１９０に形成される。また、導電体１１５は、絶縁体１８０の側面及び上面の一部に接する。 Next, the conductive film that will become the conductor 115 is processed using lithography to form the conductor 115 (see Figures 24A to 24C). As a result, a part of the conductor 115 is formed in the opening 190. The conductor 115 also contacts a part of the side and top surface of the insulator 180.
　なお、図７Ａ乃至図７Ｃに示す記憶装置を作製する場合においては、導電体１１５となる導電膜を成膜した後に、ＣＭＰ処理を行うとよい。ＣＭＰ処理を行うことで、上面が絶縁体１８０の上面と高さが一致する導電体１１５を形成することができる。 Note that in the case of manufacturing the memory devices shown in FIGS. 7A to 7C, it is preferable to perform CMP treatment after forming a conductive film that will become the conductor 115. By performing the CMP process, it is possible to form the conductor 115 whose upper surface has the same height as the upper surface of the insulator 180.
　次に、導電体１１５、及び絶縁体１８０の上に、絶縁体１３０を成膜する（図２５Ａ乃至図２５Ｃ参照）。絶縁体１３０には、上述のＨｉｇｈ−ｋ材料又は強誘電性を有しうる材料を適宜用いればよい。絶縁体１３０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、絶縁体１３０として、ＡＬＤ法を用いて、酸化ジルコニウム、酸化アルミニウム、酸化ジルコニウムの順に成膜された積層膜を形成すればよい。 Next, the insulator 130 is formed on the conductor 115 and the insulator 180 (see FIGS. 25A to 25C). For the insulator 130, the above-mentioned high-k material or a material capable of having ferroelectricity may be used as appropriate. The insulator 130 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the insulator 130, a laminated film of zirconium oxide, aluminum oxide, and zirconium oxide may be formed in this order using an ALD method.
　次に、絶縁体１３０上に導電膜１２０Ａを成膜する（図２５Ａ乃至図２５Ｃ参照）。導電膜１２０Ａには、上述の導電性材料を用いればよい。導電膜１２０Ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、導電膜１２０Ａとして、ＣＶＤ法を用いて、窒化チタン、窒化タンタルの順に成膜された積層膜を形成すればよい。又は、例えば、導電膜１２０Ａとして、ＣＶＤ法を用いて、窒化チタン、タングステンの順に成膜された積層膜を形成すればよい。 Next, a conductive film 120A is formed on the insulator 130 (see FIGS. 25A to 25C). The conductive material described above may be used for the conductive film 120A. The conductive film 120A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the conductive film 120A, a stacked film of titanium nitride and tantalum nitride may be formed in this order using a CVD method. Alternatively, for example, as the conductive film 120A, a stacked film in which titanium nitride and tungsten are deposited in this order may be formed using a CVD method.
　なお、導電膜１２０Ａの上面を、ＣＭＰ法などを用いて平坦化してもよい。導電膜１２０Ａの平坦化処理を行うことで、導電膜１２０Ａを加工することで形成される導電体１２０の上面が平坦化し、容量素子１００上にトランジスタ２００を好適に形成することができる。 Note that the upper surface of the conductive film 120A may be planarized using a CMP method or the like. By performing the planarization treatment on the conductive film 120A, the upper surface of the conductor 120 formed by processing the conductive film 120A is flattened, and the transistor 200 can be suitably formed over the capacitor 100.
　次に、導電膜１２０Ａを加工して、導電体１２０を形成する（図２６Ａ乃至図２６Ｃ参照）。導電体１２０の形成は、リソグラフィー法を用いて行えばよい。導電膜１２０Ａの加工はドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 Next, the conductive film 120A is processed to form the conductor 120 (see FIGS. 26A to 26C). The conductor 120 may be formed using a lithography method. A dry etching method or a wet etching method can be used to process the conductive film 120A. Processing by dry etching is suitable for microfabrication.
　以上のようにして、導電体１１５、絶縁体１３０、及び導電体１２０を有する容量素子１００を形成することができる。 As described above, the capacitive element 100 including the conductor 115, the insulator 130, and the conductor 120 can be formed.
　次に、絶縁体１３０及び導電体１２０上に絶縁体２８０を形成する（図２７Ａ乃至図２７Ｃ参照）。絶縁体２８０には、上述の絶縁性材料を適宜用いればよい。絶縁体２８０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、絶縁体２８０として、スパッタリング法を用いて酸化シリコン膜を成膜すればよい。なお、絶縁体２８０は、成膜後にＣＭＰ処理を行なって、上面を平坦化させることが好ましい。絶縁体２８０の平坦化処理を行うことで、配線として機能する導電体２４０を好適に形成することができる。また、絶縁体２８０上に、例えば、スパッタリング法によって、酸化アルミニウムを成膜した後、絶縁体２８０に達するまで、ＣＭＰ処理を行なってもよい。当該ＣＭＰ処理を行うことで絶縁体２８０表面の平坦化および平滑化を行うことができる。当該酸化アルミニウムを絶縁体２８０上に配置してＣＭＰ処理を行うことで、ＣＭＰ処理の終点検出が容易となる。 Next, an insulator 280 is formed on the insulator 130 and the conductor 120 (see FIGS. 27A to 27C). The insulating material described above may be used as appropriate for the insulator 280. The insulator 280 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the insulator 280, a silicon oxide film may be formed using a sputtering method. Note that the insulator 280 is preferably subjected to CMP treatment after film formation to flatten the upper surface. By performing planarization treatment on the insulator 280, the conductor 240 functioning as a wiring can be suitably formed. Further, after aluminum oxide is formed on the insulator 280 by, for example, a sputtering method, CMP treatment may be performed until the insulator 280 is reached. By performing the CMP process, the surface of the insulator 280 can be flattened and smoothed. By arranging the aluminum oxide on the insulator 280 and performing the CMP process, it becomes easy to detect the end point of the CMP process.
　なお、ＣＭＰ処理を行わなくてもよい場合がある。このとき、絶縁体２８０の上面は、上に凸の曲面形状を有する。平坦化処理を行わないことにより、製造コストを低くできるとともに、生産歩留まりを高めることができる。 In some cases, it may not be necessary to perform the CMP process. In this case, the upper surface of the insulator 280 has an upwardly convex curved shape. By not performing the planarization process, it is possible to reduce manufacturing costs and increase production yields.
　ここで、導電体１２０上の絶縁体２８０の膜厚が、トランジスタ２００のチャネル長に対応するため、トランジスタ２００のチャネル長の設計値に合わせて、絶縁体２８０の膜厚を適宜設定すればよい。 Here, since the film thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200, the film thickness of the insulator 280 may be appropriately set according to the design value of the channel length of the transistor 200. .
　また、絶縁体２８０を、酸素を含む雰囲気で、スパッタリング法で成膜することで、過剰酸素を含む絶縁体２８０を形成することができる。また、成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体２８０中の水素濃度を低減できる。このように、絶縁体２８０を成膜することで、絶縁体２８０から酸化物半導体２３０のチャネル形成領域に酸素を供給し、酸素欠損及びＶＯＨの低減を図ることができる。 Further, by forming the insulator 280 by a sputtering method in an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. By forming the insulator 280 in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced.
　次に、絶縁体２８０上に導電膜２４０Ａを成膜する（図２７Ａ乃至図２７Ｃ参照）。導電膜２４０Ａには、上述の導電性材料を適宜用いればよい。導電膜２４０Ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。 Next, a conductive film 240A is formed on the insulator 280 (see FIGS. 27A to 27C). The conductive material described above may be used as appropriate for the conductive film 240A. The conductive film 240A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
　次に、導電膜２４０Ａの一部、及び絶縁体２８０の一部を加工して、導電体１２０に達する開口部２９０を形成する（図２８Ａ乃至図２８Ｃ参照）。図２８Ａに示すように、開口部２９０は、開口部１９０と重なる領域を有するように形成することが好ましい。開口部２９０の形成は、リソグラフィー法を用いて行えばよい。なお、図２８Ａに示す開口部２９０の形状は、平面視において円形状にしているが、これに限られるものではない。例えば、開口部２９０の形状は、平面視において、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。 Next, a part of the conductive film 240A and a part of the insulator 280 are processed to form an opening 290 that reaches the conductor 120 (see FIGS. 28A to 28C). As shown in FIG. 28A, the opening 290 is preferably formed to have a region overlapping with the opening 190. The opening 290 may be formed using a lithography method. Note that although the shape of the opening 290 shown in FIG. 28A is circular in plan view, the shape is not limited to this. For example, the shape of the opening 290 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners in a plan view.
　前述したように、開口部２９０の側壁は、導電体１２０の上面に対して垂直であることが好ましい。このような構成にすることで、記憶装置の微細化または高集積化を図ることができる。また、開口部２９０の側壁は、テーパー形状であってもよい。開口部２９０の側壁をテーパー形状にすることで、後述する酸化物半導体２３０となる酸化物半導体膜などの被覆性が向上し、鬆などの欠陥を低減できる。 As mentioned above, the side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 120. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Further, the side wall of the opening 290 may have a tapered shape. By tapering the sidewall of the opening 290, coverage of an oxide semiconductor film or the like that becomes the oxide semiconductor 230 (described later) can be improved, and defects such as holes can be reduced.
　開口部２９０の最大幅（平面視において開口部２９０が円形である場合は最大径）の大きさは、微細であることが好ましい。例えば、開口部２９０の最大幅は、６０ｎｍ以下、５０ｎｍ以下、４０ｎｍ以下、３０ｎｍ以下、又は２０ｎｍ以下であって、１ｎｍ以上、又は５ｎｍ以上であることが好ましい。このように、開口部２９０を微細に加工するには、ＥＵＶ光などの短波長の光、または電子ビームを用いたリソグラフィー法を用いることが好ましい。 It is preferable that the maximum width (maximum diameter when the opening 290 is circular in plan view) of the opening 290 is minute. For example, the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and preferably 1 nm or more, or 5 nm or more. In order to finely process the opening 290 in this way, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.
　開口部２９０はアスペクト比が大きいため、異方性エッチングを用いて、導電膜２４０Ａの一部、及び絶縁体２８０の一部を加工することが好ましい。特に、ドライエッチング法による加工は、微細加工に適しているため好ましい。また、当該加工は、それぞれ異なる条件で行なってもよい。なお、導電膜２４０Ａの一部、及び絶縁体２８０の一部の加工を行う条件によっては、前述したように、開口部２９０における導電体２４０の側面の傾きと、開口部２９０における絶縁体２８０の側面の傾きとが互いに異なることがある。 Since the opening 290 has a large aspect ratio, it is preferable to process a part of the conductive film 240A and a part of the insulator 280 using anisotropic etching. In particular, processing by dry etching is preferred because it is suitable for fine processing. Further, the processing may be performed under different conditions. Note that depending on the conditions for processing a portion of the conductive film 240A and a portion of the insulator 280, as described above, the slope of the side surface of the conductor 240 at the opening 290 and the slope of the insulator 280 at the opening 290 may vary. The slopes of the sides may differ from each other.
　続いて、加熱処理を行なってもよい。加熱処理は、２５０℃以上６５０℃以下、好ましくは３００℃以上５００℃以下、さらに好ましくは３２０℃以上４５０℃以下で行えばよい。なお、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。例えば、窒素ガスと酸素ガスの混合雰囲気で加熱処理をする場合、酸素ガスを２０％程度にすればよい。また、加熱処理は減圧状態で行なってもよい。または、窒素ガスもしくは不活性ガスの雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上、または１０％以上含む雰囲気で加熱処理を行なってもよい。以上のような加熱処理を行うことで、後述する酸化物半導体２３０となる酸化物半導体膜の成膜前に、絶縁体２８０などに含まれる、水などの不純物を低減できる。 Then, a heat treatment may be performed. The heat treatment may be performed at 250° C. to 650° C., preferably 300° C. to 500° C., more preferably 320° C. to 450° C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the heat treatment as described above, impurities such as water contained in the insulator 280 and the like can be reduced before the formation of an oxide semiconductor film that becomes the oxide semiconductor 230 described later.
　また、上記加熱処理で用いるガスは、高純度化されていることが好ましい。例えば、上記加熱処理で用いるガスに含まれる水分量が１ｐｐｂ以下、好ましくは０．１ｐｐｂ以下、より好ましくは０．０５ｐｐｂ以下にすればよい。高純度化されたガスを用いて加熱処理を行うことで、絶縁体２８０などに水分等が取り込まれることを可能な限り防ぐことができる。 Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 280 and the like as much as possible.
　次に、開口部２９０の底部及び側壁、並びに導電膜２４０Ａの上面の少なくとも一部に接して、酸化物半導体２３０となる酸化物半導体膜を成膜する。当該酸化物半導体膜には、上述の酸化物半導体２３０に適用可能な金属酸化物を適宜用いればよい。当該酸化物半導体膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。ここで、当該酸化物半導体膜は、アスペクト比の大きい開口部２９０の底部及び側壁に接して形成されることが好ましい。よって、当該酸化物半導体膜の成膜は、被覆性が良好な成膜方法を用いることが好ましく、ＣＶＤ法またはＡＬＤ法などを用いることがより好ましい。例えば、当該酸化物半導体膜として、ＡＬＤ法を用いて、Ｉｎ−Ｇａ−Ｚｎ酸化物を成膜すればよい。 Next, an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductive film 240A. For the oxide semiconductor film, a metal oxide that can be used for the oxide semiconductor 230 described above may be used as appropriate. The oxide semiconductor film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the oxide semiconductor film is preferably formed in contact with the bottom and sidewalls of the opening 290 having a large aspect ratio. Therefore, for forming the oxide semiconductor film, it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like. For example, as the oxide semiconductor film, an In-Ga-Zn oxide may be formed using an ALD method.
　インジウムを有するプリカーサとして、トリメチルインジウム、トリエチルインジウム、トリス（２，２，６，６−テトラメチル−３，５−ヘプタンジオン酸）インジウム、シクロペンタジエニルインジウム、インジウム（ＩＩＩ）アセチルアセトナート、（３−（ジメチルアミノ）プロピル）ジメチルインジウムなどの有機プリカーサを用いることができる。 Examples of precursors containing indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)indium, cyclopentadienylindium, indium (III) acetylacetonate, ( Organic precursors such as 3-(dimethylamino)propyl)dimethylindium can be used.
　ガリウムを有するプリカーサとして、トリメチルガリウム、トリエチルガリウム、トリス（ジメチルアミド）ガリウム、ガリウム（ＩＩＩ）アセチルアセトナート、トリス（２，２，６，６−テトラメチル−３，５−ヘプタンジオン酸）ガリウム、ジメチルクロロガリウム、ジエチルクロロガリウム、ジメチルガリウムイソプロポキシドなどの有機プリカーサを用いることができる。 As a precursor having gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)gallium, Organic precursors such as dimethylchlorogallium, diethylchlorogallium, dimethylgallium isopropoxide, etc. can be used.
　亜鉛を含むプリカーサとして、ジメチル亜鉛、ジエチル亜鉛、ビス（２，２，６，６−テトラメチル−３，５−ヘプタンジオン酸）亜鉛、酢酸亜鉛などの有機プリカーサを用いることができる。 As a precursor containing zinc, organic precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedioic acid)zinc, zinc acetate, etc. can be used.
　基板加熱しながらＡＬＤ法による成膜を行うために、上記成膜に用いるプリカーサは分解温度が高いことが好ましい。例えば、プリカーサの分解温度が、２００℃以上７００℃以下であることが好ましく、３００℃以上６００℃以下であることがより好ましい。このような分解温度が高いプリカーサとしては、炭化水素を有しない、無機プリカーサを用いることが好ましい。無機プリカーサは概して、有機プリカーサより、分解温度が高い傾向があるため、上記のように基板加熱をしながら成膜を行なっても、プリカーサが分解されにくい。 In order to perform film formation by the ALD method while heating the substrate, it is preferable that the precursor used for the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200°C or more and 700°C or less, more preferably 300°C or more and 600°C or less. As such a precursor having a high decomposition temperature, it is preferable to use an inorganic precursor that does not contain hydrocarbons. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if film formation is performed while heating the substrate as described above, the precursors are difficult to decompose.
　インジウムを有する無機プリカーサとして、三塩化インジウム、三臭化インジウム、三ヨウ化インジウムなどのハロゲン系のインジウム化合物を用いることができる。また、ガリウムを有する無機プリカーサとして、三塩化ガリウム、三臭化ガリウム、三ヨウ化ガリウムなどのハロゲン系のガリウム化合物を用いることができる。また、亜鉛を有する無機プリカーサとして、二塩化亜鉛、二臭化亜鉛、二ヨウ化亜鉛などのハロゲン系の亜鉛化合物を用いることができる。 As an inorganic precursor containing indium, halogen-based indium compounds such as indium trichloride, indium tribromide, and indium triiodide can be used. Further, as an inorganic precursor containing gallium, halogen-based gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide can be used. Further, as an inorganic precursor containing zinc, halogen-based zinc compounds such as zinc dichloride, zinc dibromide, and zinc diiodide can be used.
　なお、上記プリカーサには、金属元素の他に、炭素および塩素の一方または両方を含むものがある。炭素を含むプリカーサを用いて形成された膜には炭素が含まれる場合がある。また、塩素などのハロゲンを含むプリカーサを用いて形成された膜には塩素などのハロゲンが含まれる場合がある。 Note that some of the precursors include one or both of carbon and chlorine in addition to metal elements. A film formed using a precursor containing carbon may contain carbon. Further, a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.
　酸化剤として、オゾン、酸素、水などを用いることができる。 Ozone, oxygen, water, etc. can be used as the oxidizing agent.
　なお、開口部２９０の側壁がテーパー形状である場合、酸化物半導体２３０となる酸化物半導体膜の成膜は、ＣＶＤ法又はＡＬＤ法を用いる場合に限られない。例えば、スパッタリング法を用いてもよい。 Note that when the sidewall of the opening 290 has a tapered shape, the oxide semiconductor film that becomes the oxide semiconductor 230 is not limited to the case where the CVD method or the ALD method is used. For example, a sputtering method may be used.
　また、図１６Ａ及び図１６Ｂに示すように、酸化物半導体２３０を積層構造とする場合、酸化物半導体２３０に含まれる各層の成膜方法は同じであってもよいし、異なってもよい。例えば、酸化物半導体２３０を２層の積層構造とする場合、酸化物半導体膜の下層をスパッタリング法で成膜し、酸化物半導体膜の上層をＡＬＤ法で成膜してもよい。スパッタリング法を用いて成膜された酸化物半導体膜は結晶性を有しやすい。そこで、結晶性を有する酸化物半導体膜を酸化物半導体膜の下層として設けることで、酸化物半導体膜の上層の結晶性を高めることができる。また、スパッタリング法で成膜した酸化物半導体膜の下層にピンホールまたは段切れなどが形成されたとしても、それらと重畳する部分を、被覆性の良好なＡＬＤ法で成膜した酸化物半導体膜の上層で塞ぐことができる。 Further, as shown in FIGS. 16A and 16B, when the oxide semiconductor 230 has a stacked layer structure, the deposition methods for each layer included in the oxide semiconductor 230 may be the same or different. For example, when the oxide semiconductor 230 has a two-layer stacked structure, the lower layer of the oxide semiconductor film may be formed by a sputtering method, and the upper layer of the oxide semiconductor film may be formed by an ALD method. An oxide semiconductor film formed using a sputtering method tends to have crystallinity. Therefore, by providing an oxide semiconductor film having crystallinity as a lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. Furthermore, even if pinholes or step breaks are formed in the lower layer of the oxide semiconductor film formed by the sputtering method, the oxide semiconductor film formed by the ALD method, which has good coverage, can cover the overlapping portions. It can be closed with the upper layer of
　ここで、酸化物半導体２３０となる酸化物半導体膜は、開口部２９０における導電体１２０の上面、開口部２９０における絶縁体２８０の側面、開口部２９０における導電体２４０の側面、及び導電体２４０の上面に接して形成されることが好ましい。当該酸化物半導体膜を導電体１２０と接して形成することで、導電体１２０は、トランジスタ２００のソース電極及びドレイン電極の一方として機能する。また、当該酸化物半導体膜を導電体２４０と接して形成することで、導電体２４０は、トランジスタ２００のソース電極及びドレイン電極の他方として機能する。 Here, the oxide semiconductor film serving as the oxide semiconductor 230 covers the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the side surface of the conductor 240 in the opening 290. Preferably, it is formed in contact with the upper surface. By forming the oxide semiconductor film in contact with the conductor 120, the conductor 120 functions as one of a source electrode and a drain electrode of the transistor 200. Further, by forming the oxide semiconductor film in contact with the conductor 240, the conductor 240 functions as the other of the source electrode and the drain electrode of the transistor 200.
　次に、加熱処理を行うことが好ましい。加熱処理は、上記酸化物半導体膜が多結晶化しない温度範囲で行えばよく、２５０℃以上６５０℃以下、好ましくは４００℃以上６００℃以下で行えばよい。なお、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。例えば、窒素ガスと酸素ガスの混合雰囲気で加熱処理をする場合、酸素ガスを２０％程度にすればよい。また、加熱処理は減圧状態で行なってもよい。または、窒素ガスもしくは不活性ガスの雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上、または１０％以上含む雰囲気で加熱処理を行なってもよい。 Next, it is preferable to perform heat treatment. The heat treatment may be performed at a temperature range in which the oxide semiconductor film does not become polycrystalline, and may be performed at a temperature of 250° C. or more and 650° C. or less, preferably 400° C. or more and 600° C. or less. Note that the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content may be about 20%. Further, the heat treatment may be performed under reduced pressure. Alternatively, after heat treatment in a nitrogen gas or inert gas atmosphere, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
　また、上記加熱処理で用いるガスは、高純度化されていることが好ましい。例えば、上記加熱処理で用いるガスに含まれる水分量が１ｐｐｂ以下、好ましくは０．１ｐｐｂ以下、より好ましくは０．０５ｐｐｂ以下にすればよい。高純度化されたガスを用いて加熱処理を行うことで、上記酸化物半導体膜などに水分等が取り込まれることを可能な限り防ぐことができる。 Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using highly purified gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film or the like as much as possible.
　ここで、上記酸化物半導体膜に、過剰酸素を含む絶縁体２８０を接して設けた状態で、上記加熱処理を行うことが好ましい。このように加熱処理を行うことで、絶縁体２８０から酸化物半導体２３０のチャネル形成領域に酸素を供給し、酸素欠損及びＶＯＨの低減を図ることができる。 Here, the heat treatment is preferably performed while the insulator 280 containing excess oxygen is provided in contact with the oxide semiconductor film. By performing heat treatment in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced.
　また、ＡＬＤ法を用いて酸化物半導体膜を成膜する場合、上記加熱処理を行うことで、酸化物半導体膜に含まれる水素、または炭素などの不純物を除去することができる。例えば、酸化物半導体膜中の炭素をＣＯ２およびＣＯとして放出させ、酸化物半導体膜中の水素をＨ２Ｏとして放出させることができる。さらに、上記の不純物の除去と同時に、金属原子及び酸素原子の再配列が行われ、結晶性の向上を図ることができる。よって、結晶性の高い、層状の結晶構造の酸化物半導体２３０を形成することができる。 Further, when an oxide semiconductor film is formed using an ALD method, impurities such as hydrogen or carbon contained in the oxide semiconductor film can be removed by performing the above heat treatment. For example, carbon in the oxide semiconductor film can be released as CO 2 and CO, and hydrogen in the oxide semiconductor film can be released as H 2 O. Furthermore, simultaneously with the removal of the impurities, metal atoms and oxygen atoms are rearranged, and crystallinity can be improved. Therefore, the oxide semiconductor 230 having a layered crystal structure with high crystallinity can be formed.
　なお、上記においては、上記酸化物半導体膜の成膜後に加熱処理を行なったが、本発明はこれに限られるものではない。さらに後の工程で加熱処理を行う構成にしてもよい。 Note that in the above, heat treatment was performed after forming the oxide semiconductor film, but the present invention is not limited to this. A configuration may also be adopted in which heat treatment is performed in a later step.
　また、上記酸化物半導体膜の成膜後に、酸素を含む雰囲気でマイクロ波処理を行うことで、当該酸化物半導体膜中の不純物濃度を低減させる処理を行うと好ましい。なお、不純物としては、特に、水素、及び炭素が挙げられる。ここで、マイクロ波処理とは、例えばマイクロ波を用いて高密度プラズマを発生させる電源を有する装置を用いた処理のことを指す。 Further, after the formation of the oxide semiconductor film, it is preferable to perform microwave treatment in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor film. Note that impurities include hydrogen and carbon, in particular. Here, microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves.
　酸素を含む雰囲気でマイクロ波処理を行うことで、マイクロ波、またはＲＦ等の高周波を用いて酸素ガスをプラズマ化し、当該酸素プラズマを作用させることができる。また、酸化物半導体膜に作用する酸素は、酸素原子、酸素分子、酸素イオン、及び酸素ラジカル（Ｏラジカルともいう、不対電子をもつ原子、分子、またはイオン）など様々な形態がある。なお、酸化物半導体膜に作用する酸素は、上述の形態のいずれか一または複数であればよく、特に酸素ラジカルであると好適である。 By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. Further, oxygen that acts on the oxide semiconductor film has various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also referred to as O radicals; atoms, molecules, or ions with unpaired electrons). Note that the oxygen that acts on the oxide semiconductor film may be any one or more of the forms described above, and oxygen radicals are particularly preferable.
　また、上述の酸素を含む雰囲気でマイクロ波処理を行う際に、基板を加熱することで、酸化物半導体膜中の不純物濃度を、さらに低減させることができるため好適である。上述の基板を加熱する温度としては、１００℃以上６５０℃以下、好ましくは２００℃以上６００℃以下、さらに好ましくは３００℃以上４５０℃以下で行えばよい。 Furthermore, heating the substrate when performing the microwave treatment in the above-mentioned oxygen-containing atmosphere is preferable because the impurity concentration in the oxide semiconductor film can be further reduced. The temperature at which the above-mentioned substrate is heated may be 100°C or more and 650°C or less, preferably 200°C or more and 600°C or less, and more preferably 300°C or more and 450°C or less.
　上述の酸素を含む雰囲気でマイクロ波処理を行う際に基板を加熱することで、ＳＩＭＳにより得られる金属酸化物中の炭素濃度を、１×１０２０ａｔｏｍｓ／ｃｍ３未満、好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３未満、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３未満とすることができる。 By heating the substrate during microwave treatment in the above-mentioned oxygen-containing atmosphere, the carbon concentration in the metal oxide obtained by SIMS can be reduced to less than 1×10 20 atoms/cm 3 , preferably 1×10 19 It can be less than 1×10 18 atoms/cm 3 , more preferably less than 1×10 18 atoms/cm 3 .
　なお、上記においては、酸化物半導体膜に対して、酸素を含む雰囲気でマイクロ波処理を行う構成について例示したが、これに限定されない。例えば、酸化物半導体近傍に位置する、絶縁膜、より具体的には酸化シリコン膜に対して、酸素を含む雰囲気でマイクロ波処理を行なってもよい。例えば、後述する図３１に示す工程において、絶縁体２５０を成膜した後で、マイクロ波処理を行なってもよい。酸化シリコン膜に対して、酸素を含む雰囲気でマイクロ波処理を行うことで、当該酸化シリコン膜中に含まれる水素をＨ２Ｏとして、外部に放出させることができる。酸化物半導体近傍に位置する、酸化シリコン膜から水素を放出させることで、信頼性の高い記憶装置を提供することができる。 Note that although the above example illustrates a configuration in which the oxide semiconductor film is subjected to microwave treatment in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically a silicon oxide film, located near an oxide semiconductor in an atmosphere containing oxygen. For example, in the step shown in FIG. 31 described later, microwave treatment may be performed after the insulator 250 is formed. By performing microwave treatment on the silicon oxide film in an atmosphere containing oxygen, hydrogen contained in the silicon oxide film can be released to the outside as H 2 O. By releasing hydrogen from a silicon oxide film located near an oxide semiconductor, a highly reliable memory device can be provided.
　次に、酸化物半導体２３０となる酸化物半導体膜を、リソグラフィー法を用いて加工し、酸化物半導体２３０を形成する（図２９Ａ乃至図２９Ｃ参照）。これにより、酸化物半導体２３０の一部が、開口部２９０に形成される。また、酸化物半導体２３０は、導電体２４０の側面及び上面の一部に接する。したがって、酸化物半導体２３０と導電体２４０が接する領域の面積を大きくすることができる。 Next, the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (see FIGS. 29A to 29C). As a result, part of the oxide semiconductor 230 is formed in the opening 290. Further, the oxide semiconductor 230 is in contact with a part of the side surface and the top surface of the conductor 240. Therefore, the area of the region where the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
　次に、導電膜２４０Ａを加工して、導電体２４０を形成する（図３０Ａ乃至図３０Ｃ参照）。導電体２４０の形成は、リソグラフィー法を用いて行えばよい。導電膜２４０Ａの加工はドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 Next, the conductive film 240A is processed to form the conductor 240 (see FIGS. 30A to 30C). The conductor 240 may be formed using a lithography method. A dry etching method or a wet etching method can be used to process the conductive film 240A. Processing by dry etching is suitable for microfabrication.
　ここでは、導電体２４０及び酸化物半導体２３０の形成が上述と異なる方法について説明する。 Here, a method for forming the conductor 240 and the oxide semiconductor 230 that is different from the above method will be described.
　図２７Ａ乃至図２７Ｃに示す導電膜２４０Ａを成膜するまでは、上述と同様の方法である。 The method is the same as described above until the conductive film 240A shown in FIGS. 27A to 27C is formed.
　次に、導電膜２４０Ａを加工して、導電体２４０を形成する。導電体２４０の形成方法などは、前述した説明を参照できる。 Next, the conductive film 240A is processed to form the conductor 240. For the method of forming the conductor 240, etc., the above description can be referred to.
　次に、導電体２４０の一部、及び絶縁体２８０の一部を加工して、導電体１２０に達する開口部２９０を形成する。開口部２９０の形成方法などは、前述した説明を参照できる。 Next, a part of the conductor 240 and a part of the insulator 280 are processed to form an opening 290 that reaches the conductor 120. For the method of forming the opening 290, etc., the above description can be referred to.
　続いて、加熱処理を行なってもよい。加熱処理の条件などは、前述した説明を参照できる。 Subsequently, heat treatment may be performed. For the conditions of the heat treatment, etc., the above explanation can be referred to.
　次に、開口部２９０の底部及び側壁、並びに導電体２４０の上面の少なくとも一部に接して、酸化物半導体２３０となる酸化物半導体膜を成膜する。このとき、当該酸化物半導体膜は、絶縁体２８０の上面と接する領域を有する。当該酸化物半導体膜の成膜方法などは、前述した説明を参照できる。 Next, an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductor 240. At this time, the oxide semiconductor film has a region in contact with the upper surface of the insulator 280. For the method of forming the oxide semiconductor film, etc., the above description can be referred to.
　次に、加熱処理を行うことが好ましい。加熱処理の条件などは、前述した説明を参照できる。 Next, it is preferable to perform heat treatment. For the conditions of the heat treatment, etc., the above explanation can be referred to.
　次に、酸化物半導体２３０となる酸化物半導体膜を、リソグラフィー法を用いて加工し、酸化物半導体２３０を形成する（図３０Ａ乃至図３０Ｃ参照）。 Next, the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (see FIGS. 30A to 30C).
　これ以降の記憶装置の作製方法は、どちらも同様の方法で進めることができる。 Both of the subsequent manufacturing methods of the storage device can proceed in the same manner.
　次に、酸化物半導体２３０、導電体２４０、及び絶縁体２８０の上に、絶縁体２５０を成膜する（図３１Ａ乃至図３１Ｃ参照）。絶縁体２５０には、上述の絶縁性材料を適宜用いればよい。絶縁体２５０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。ここで、絶縁体２５０は、アスペクト比の大きい開口部２９０に設けられた酸化物半導体２３０に接して形成されることが好ましい。よって、絶縁体２５０の成膜は、被覆性が良好な成膜方法を用いることが好ましく、ＣＶＤ法またはＡＬＤ法などを用いることがより好ましい。例えば、絶縁体２５０として、ＡＬＤ法を用いて、酸化シリコンを成膜すればよい。 Next, an insulator 250 is formed over the oxide semiconductor 230, the conductor 240, and the insulator 280 (see FIGS. 31A to 31C). For the insulator 250, any of the above-mentioned insulating materials may be used as appropriate. The insulator 250 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290 with a large aspect ratio. Therefore, for forming the insulator 250, it is preferable to use a film forming method that provides good coverage, and it is more preferable to use a CVD method, an ALD method, or the like. For example, silicon oxide may be formed as the insulator 250 using an ALD method.
　なお、開口部２９０の側壁がテーパー形状である場合、絶縁体２５０の成膜は、ＣＶＤ法又はＡＬＤ法を用いる場合に限られない。例えば、スパッタリング法を用いてもよい。 Note that when the side wall of the opening 290 has a tapered shape, the film formation of the insulator 250 is not limited to the case where the CVD method or the ALD method is used. For example, a sputtering method may be used.
　酸化物半導体２３０を形成した後で、絶縁体２５０を成膜する構成にすることで、酸化物半導体２３０の側端部が絶縁体２５０で覆われる。したがって、酸化物半導体２３０と導電体２６０のショートを防ぐことができる。また、上記構成にすることで、導電体２４０の側端部が絶縁体２５０で覆われる。したがって、導電体２４０と導電体２６０のショートを防ぐことができる。 By forming the insulator 250 after forming the oxide semiconductor 230, the side edges of the oxide semiconductor 230 are covered with the insulator 250. Therefore, short circuit between the oxide semiconductor 230 and the conductor 260 can be prevented. Furthermore, with the above configuration, the side end portions of the conductor 240 are covered with the insulator 250. Therefore, short circuit between the conductor 240 and the conductor 260 can be prevented.
　次に、絶縁体２５０の凹部を埋めるように、導電膜２６０Ａを成膜する（図３１Ａ乃至図３１Ｃ参照）。導電膜２６０Ａには、上述の導電性材料を適宜用いればよい。導電膜２６０Ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。ここで、導電膜２６０Ａは、アスペクト比の大きい開口部２９０に設けられた絶縁体２５０に接して形成されることが好ましい。よって、導電膜２６０Ａの成膜は、被覆性または埋め込み性が良好な成膜方法を用いることが好ましく、ＣＶＤ法またはＡＬＤ法などを用いることがより好ましい。例えば、導電膜２６０Ａとして、ＣＶＤ法またはＡＬＤ法を用いて、窒化チタンを成膜すればよい。 Next, a conductive film 260A is formed to fill the recesses of the insulator 250 (see FIGS. 31A to 31C). The conductive material described above may be used as appropriate for the conductive film 260A. The conductive film 260A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the conductive film 260A is preferably formed in contact with the insulator 250 provided in the opening 290 having a large aspect ratio. Therefore, for forming the conductive film 260A, it is preferable to use a film forming method that provides good coverage or embeddability, and it is more preferable to use a CVD method, an ALD method, or the like. For example, titanium nitride may be formed as the conductive film 260A using a CVD method or an ALD method.
　なお、ＣＶＤ法を用いて導電膜２６０Ａを成膜した場合、導電膜２６０Ａの上面の平均面粗さが大きくなることがある。この場合、ＣＭＰ法を用いて、導電膜２６０Ａを平坦化することが好ましい。このとき、ＣＭＰ処理を行う前に、導電膜２６０Ａ上に酸化シリコン膜または酸化窒化シリコン膜を成膜し、当該酸化シリコン膜または酸化窒化シリコン膜を除去するまで、ＣＭＰ処理を行なってもよい。 Note that when the conductive film 260A is formed using the CVD method, the average surface roughness of the upper surface of the conductive film 260A may become large. In this case, it is preferable to planarize the conductive film 260A using a CMP method. At this time, before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed over the conductive film 260A, and the CMP treatment may be performed until the silicon oxide film or silicon oxynitride film is removed.
　また、上記においては、導電膜２６０Ａが開口部２９０を埋め込むように設けられているが、本発明はこれに限られるものではない。例えば、導電膜２６０Ａの中央部に、開口部２９０の形状を反映した凹部が形成される場合がある。また、当該凹部を無機絶縁材料などで充填する構成にしてもよい。 Furthermore, in the above, the conductive film 260A is provided so as to fill the opening 290, but the present invention is not limited to this. For example, a recess reflecting the shape of the opening 290 may be formed in the center of the conductive film 260A. Alternatively, the recess may be filled with an inorganic insulating material or the like.
　次に、導電膜２６０Ａを加工して、導電体２６０を形成する（図３２Ａ乃至図３２Ｃ参照）。導電体２６０の形成は、リソグラフィー法を用いて行えばよい。上記加工はドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 Next, the conductive film 260A is processed to form the conductor 260 (see FIGS. 32A to 32C). The conductor 260 may be formed using a lithography method. For the above processing, a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication.
　ここで、図１Ａ及び図１Ｂに示すように、導電体２６０の側端部が、平面視において、酸化物半導体２３０の側端部より内側に位置することが好ましい。これにより、導電体２６０と酸化物半導体２３０がショートするのを防ぐことができる。 Here, as shown in FIGS. 1A and 1B, it is preferable that the side end portion of the conductor 260 is located inside the side end portion of the oxide semiconductor 230 in plan view. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
　以上のようにして、導電体１２０、導電体２４０、酸化物半導体２３０、絶縁体２５０、及び導電体２６０を有するトランジスタ２００を形成することができる。 In the above manner, the transistor 200 including the conductor 120, the conductor 240, the oxide semiconductor 230, the insulator 250, and the conductor 260 can be formed.
　次に、導電体２６０及び絶縁体２５０を覆って、絶縁体２８３を成膜する。絶縁体２８３は、上述の絶縁性材料を適宜用いればよい。絶縁体２８３の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。 Next, an insulator 283 is formed to cover the conductor 260 and the insulator 250. For the insulator 283, the above-mentioned insulating material may be used as appropriate. The insulator 283 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
　以上により、図１Ａ乃至図１Ｄに示すメモリセル１５０を有する記憶装置を作製できる。また、図１Ａ乃至図１Ｄに示すトランジスタ２００及び容量素子１００を有する記憶装置を作製できる。 Through the above steps, a memory device having the memory cell 150 shown in FIGS. 1A to 1D can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 illustrated in FIGS. 1A to 1D can be manufactured.
＜記憶装置の作製方法例２＞
　次に、図１０Ａ乃至図１０Ｃに示す、本発明の一態様である記憶装置の作製方法を説明する。なお、絶縁体１８０を形成するまでの工程は、前述した＜記憶装置の作製方法例１＞の説明を参照できる。 <Example 2 of manufacturing method of storage device>
Next, a method for manufacturing a memory device shown in FIGS. 10A to 10C, which is one embodiment of the present invention, will be described. Note that for the steps up to forming the insulator 180, the description in <Example 1 of manufacturing method of memory device> described above can be referred to.
　次に、絶縁体１８０の一部を加工して、導電体１２０に達する開口部１９０を形成する（図３３Ａ乃至図３３Ｃ参照）。開口部１９０の形成方法は、前述した説明を参照できる。 Next, a part of the insulator 180 is processed to form an opening 190 that reaches the conductor 120 (see FIGS. 33A to 33C). For the method of forming the opening 190, the above description can be referred to.
　次に、開口部１９０の底部及び側壁、並びに絶縁体１８０の上面の少なくとも一部に接して、導電体１１５となる導電膜を成膜する。当該導電膜の成膜方法などは、前述した説明を参照できる。当該導電膜を成膜した後に、ＣＭＰ処理を行う。当該ＣＭＰ処理を行うことで、導電体１１５を形成することができる（図３４Ａ乃至図３４Ｃ参照）。このとき、導電体１１５の上面と、絶縁体１８０の上面とは、高さが一致する。 Next, a conductive film that will become the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180. For the method of forming the conductive film, etc., the above description can be referred to. After forming the conductive film, CMP treatment is performed. By performing the CMP treatment, the conductor 115 can be formed (see FIGS. 34A to 34C). At this time, the top surface of the conductor 115 and the top surface of the insulator 180 are at the same height.
　次に、導電体１１５、及び絶縁体１８０の上に、絶縁体１３０を成膜する（図３５Ａ乃至図３５Ｃ参照）。絶縁体１３０の成膜方法などは、前述した説明を参照できる。 Next, the insulator 130 is formed on the conductor 115 and the insulator 180 (see FIGS. 35A to 35C). For the method of forming the insulator 130, etc., the above description can be referred to.
　次に、絶縁体１３０上に導電体１２０となる導電膜を成膜する。当該導電膜の成膜方法などは、前述した導電膜１２０Ａの説明を参照できる。例えば、当該導電膜として、ＣＶＤ法を用いて、窒化チタン、タングステンの順に成膜された積層膜を形成すればよい。 Next, a conductive film that will become the conductor 120 is formed on the insulator 130. For the method of forming the conductive film, etc., the description of the conductive film 120A described above can be referred to. For example, as the conductive film, a stacked film of titanium nitride and tungsten may be formed in this order using a CVD method.
　次に、ＣＭＰ処理を行うことで、導電体１２０となる導電膜の一部を除去し、絶縁体１３０を露出する。その結果、開口部１９０のみに、導電体１２０が残存する。なお、当該ＣＭＰ処理により、絶縁体１３０の一部が除去される場合がある。なお、導電体１２０となる導電膜の一部の除去は、ＣＭＰ処理以外の方法を用いて行なってもよい。 Next, by performing a CMP process, a part of the conductive film that will become the conductor 120 is removed, and the insulator 130 is exposed. As a result, the conductor 120 remains only in the opening 190. Note that a portion of the insulator 130 may be removed by the CMP process. Note that a portion of the conductive film that will become the conductor 120 may be removed using a method other than CMP treatment.
　次に、エッチングを行なって、導電体１２０の上部を除去する（図３５Ａ乃至図３５Ｃ参照）。これにより、導電体１２０の上面は、絶縁体１３０の上面より低くなる。導電体１２０のエッチングには、ドライエッチングまたはウェットエッチングを用いればよいが、ドライエッチングを用いるほうが微細加工には好ましい。 Next, etching is performed to remove the upper part of the conductor 120 (see FIGS. 35A to 35C). As a result, the top surface of the conductor 120 is lower than the top surface of the insulator 130. Although dry etching or wet etching may be used for etching the conductor 120, it is preferable to use dry etching for fine processing.
　次に、絶縁体１３０及び導電体１２０の上に、導電膜１２１Ａを成膜する（図３６Ａ乃至図３６Ｃ参照）。例えば、導電膜１２１Ａとして、ＣＶＤ法又はＡＬＤ法を用いて窒化チタンを成膜する。 Next, a conductive film 121A is formed on the insulator 130 and the conductor 120 (see FIGS. 36A to 36C). For example, titanium nitride is formed as the conductive film 121A using a CVD method or an ALD method.
　次に、導電膜１２１Ａを異方性エッチングして、開口部１９０における絶縁体１３０の側面に接して導電体１２１を形成する（図３７Ａ乃至図３７Ｃ参照）。導電膜１２１Ａの異方性エッチングは、例えばドライエッチング法等を用いればよい。なお、導電体１２０の下層と導電体１２１とが同一の材料で形成される場合、導電体１２０の下層と導電体１２１との境界を明確に検出することが困難な場合がある。 Next, the conductive film 121A is anisotropically etched to form the conductor 121 in contact with the side surface of the insulator 130 in the opening 190 (see FIGS. 37A to 37C). The anisotropic etching of the conductive film 121A may be performed using, for example, a dry etching method. Note that if the lower layer of the conductor 120 and the conductor 121 are formed of the same material, it may be difficult to clearly detect the boundary between the lower layer of the conductor 120 and the conductor 121.
　以上のようにして、導電体１１５、絶縁体１３０、導電体１２０、及び導電体１２１を有する容量素子１００を形成することができる。 As described above, the capacitive element 100 including the conductor 115, the insulator 130, the conductor 120, and the conductor 121 can be formed.
　絶縁体１３０、導電体１２１、及び導電体１２０上に絶縁体１８２を形成する（図３７Ａ乃至図３７Ｃ参照）。絶縁体１８２は、上述の絶縁性材料を適宜用いればよい。絶縁体１８２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、絶縁体１８２として、スパッタリング法を用いて酸化シリコン膜を成膜すればよい。なお、絶縁体１８２は、成膜後にＣＭＰ処理を行なって、上面を平坦化させることが好ましい。 The insulator 130, the conductor 121, and the insulator 182 are formed on the conductor 120 (see FIGS. 37A to 37C). For the insulator 182, any of the above-mentioned insulating materials may be used as appropriate. The insulator 182 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the insulator 182, a silicon oxide film may be formed using a sputtering method. Note that the insulator 182 is preferably subjected to CMP treatment after film formation to flatten the upper surface.
　次に、絶縁体１８２に、導電体１２０に達する開口を形成する。当該開口の形成は、リソグラフィー法を用いて行えばよい。また、当該開口のエッチングにはドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 Next, an opening reaching the conductor 120 is formed in the insulator 182. The opening may be formed using a lithography method. Further, a dry etching method or a wet etching method can be used for etching the opening. Processing by dry etching is suitable for microfabrication.
　次に、絶縁体１８２に形成された開口を埋め込むように、導電体１２２となる導電膜を成膜する。当該導電膜には、上述の導電性材料を適宜用いればよい。当該導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、当該導電膜として、スパッタリング法を用いて、窒化タンタル、タングステンの順に成膜された積層膜を形成すればよい。 Next, a conductive film that will become the conductor 122 is formed so as to fill the opening formed in the insulator 182. The above-mentioned conductive material may be appropriately used for the conductive film. The conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the conductive film, a laminated film in which tantalum nitride and tungsten are deposited in this order may be formed using a sputtering method.
　次に、絶縁体１８２上の、導電体１２２となる導電膜の一部を除去して、絶縁体１８２の開口の内側に導電体１２２を形成する（図３８Ａ乃至図３８Ｃ参照）。導電体１２２の形成は、絶縁体１８２の上面が露出するまで、当該導電膜にＣＭＰ処理を行えばよい。 Next, a part of the conductive film on the insulator 182 that will become the conductor 122 is removed to form the conductor 122 inside the opening of the insulator 182 (see FIGS. 38A to 38C). The conductor 122 may be formed by performing CMP treatment on the conductive film until the upper surface of the insulator 182 is exposed.
　次に、絶縁体１８２及び導電体１２０上に絶縁体２８０を形成する。絶縁体２８０の成膜方法などは、前述した説明を参照できる。 Next, an insulator 280 is formed on the insulator 182 and the conductor 120. For the method of forming the insulator 280, etc., the above description can be referred to.
　なお、絶縁体２８０を形成した後の工程（導電膜２４０Ａの成膜工程以降）は、前述した＜記憶装置の作製方法例１＞の説明を参照できる。 Note that for the steps after forming the insulator 280 (after the step of forming the conductive film 240A), the description in <Example 1 of manufacturing method of memory device> described above can be referred to.
　以上により、図１０Ａ乃至図１０Ｃに示すメモリセル１５０を有する記憶装置を作製できる。また、図１０Ａ乃至図１０Ｃに示すトランジスタ２００及び容量素子１００を有する記憶装置を作製できる。 Through the above steps, a memory device having the memory cell 150 shown in FIGS. 10A to 10C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 10A to 10C can be manufactured.
＜記憶装置の作製方法例３＞
　次に、図２０Ａ乃至図２０Ｃに示す、本発明の一態様である記憶装置の作製方法を説明する。なお、絶縁体２８０を形成するまでの工程は、前述した＜記憶装置の作製方法例１＞の説明を参照できる。 <Example 3 of manufacturing method of storage device>
Next, a method for manufacturing a memory device shown in FIGS. 20A to 20C, which is one embodiment of the present invention, will be described. Note that for the steps up to forming the insulator 280, the description in <Example 1 of manufacturing method of memory device> described above can be referred to.
　絶縁体２８０上に絶縁体２８１を形成する。絶縁体２８１は、上述の絶縁性材料を適宜用いればよい。絶縁体２８１の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、絶縁体２８１として、スパッタリング法を用いて酸化シリコン膜を成膜すればよい。なお、絶縁体２８１は、成膜後にＣＭＰ処理を行なって、上面を平坦化させることが好ましい。 An insulator 281 is formed on the insulator 280. For the insulator 281, the above-mentioned insulating material may be used as appropriate. The insulator 281 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the insulator 281, a silicon oxide film may be formed using a sputtering method. Note that the insulator 281 is preferably subjected to CMP treatment after film formation to flatten the upper surface.
　次に、絶縁体２８１に、絶縁体２８０に達する開口を形成する。当該開口の内側に、配線として機能する導電体２４０が形成されるため、当該開口はＸ方向に伸長して設ければよい。当該開口の形成は、リソグラフィー法を用いて行えばよい。また、当該開口のエッチングにはドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 Next, an opening reaching the insulator 280 is formed in the insulator 281. Since the conductor 240 functioning as a wiring is formed inside the opening, the opening may be provided extending in the X direction. The opening may be formed using a lithography method. Further, a dry etching method or a wet etching method can be used for etching the opening. Processing by dry etching is suitable for microfabrication.
　なお、絶縁体２８０を積層構造にし、絶縁体２８０の最上面にエッチングストッパ膜として機能する絶縁体を設ける構成にしてもよい。当該絶縁体は、図１７に示す構成においては、絶縁体２８０ｃに対応する。例えば、上記開口を形成する絶縁体２８１に酸化シリコンまたは酸化窒化シリコンを用いた場合は、エッチングストッパ膜として、窒化シリコン、酸化アルミニウム、または酸化ハフニウムなどを用いるとよい。 Note that the insulator 280 may have a laminated structure, and an insulator functioning as an etching stopper film may be provided on the uppermost surface of the insulator 280. The insulator corresponds to the insulator 280c in the configuration shown in FIG. 17. For example, when silicon oxide or silicon oxynitride is used for the insulator 281 forming the opening, silicon nitride, aluminum oxide, hafnium oxide, or the like may be used as the etching stopper film.
　次に、絶縁体２８１に形成された開口を埋め込むように、導電体２４０となる導電膜を成膜する。当該導電膜には、上述の導電性材料を適宜用いればよい。当該導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いて行えばよい。例えば、当該導電膜として、スパッタリング法を用いて、窒化タンタル、タングステンの順に成膜された積層膜を形成すればよい。 Next, a conductive film that will become the conductor 240 is formed so as to fill the opening formed in the insulator 281. The above-mentioned conductive material may be appropriately used for the conductive film. The conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, as the conductive film, a laminated film in which tantalum nitride and tungsten are deposited in this order may be formed using a sputtering method.
　次に、絶縁体２８１上の、導電体２４０となる導電膜の一部を除去して、絶縁体２８１の開口の内側に導電体２４０を形成する。導電体２４０の形成は、絶縁体２８１の上面が露出するまで、当該導電膜にＣＭＰ処理を行えばよい。 Next, a part of the conductive film on the insulator 281 that will become the conductor 240 is removed to form the conductor 240 inside the opening of the insulator 281. The conductor 240 may be formed by performing CMP treatment on the conductive film until the upper surface of the insulator 281 is exposed.
　なお、導電体２４０を形成した後の工程（開口部２９０の形成工程以降）は、前述した＜記憶装置の作製方法例１＞の説明を参照できる。 Note that for the steps after forming the conductor 240 (after the step of forming the opening 290), the description in the above-mentioned <Example 1 of manufacturing method of memory device> can be referred to.
　以上により、図２０Ａ乃至図２０Ｃに示すメモリセル１５０を有する記憶装置を作製できる。また、図２０Ａ乃至図２０Ｃに示すトランジスタ２００及び容量素子１００を有する記憶装置を作製できる。 Through the above steps, a memory device having the memory cell 150 shown in FIGS. 20A to 20C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 20A to 20C can be manufactured.
　本発明の一態様により、新規のトランジスタ、新規の半導体装置、及び新規の記憶装置を提供できる。または、微細化または高集積化が可能な記憶装置を提供できる。または、周波数特性が良好な記憶装置を提供できる。または、動作速度が速い記憶装置を提供できる。または、信頼性が良好な記憶装置を提供できる。または、低消費電力の記憶装置を提供できる。または、オン電流が大きいトランジスタを有する記憶装置を提供できる。または、トランジスタ特性のばらつきが少ない記憶装置を提供できる。または、良好な電気特性を有する記憶装置を提供できる。 According to one embodiment of the present invention, a new transistor, a new semiconductor device, and a new memory device can be provided. Alternatively, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a storage device with good frequency characteristics can be provided. Alternatively, a storage device with high operating speed can be provided. Alternatively, a highly reliable storage device can be provided. Alternatively, a storage device with low power consumption can be provided. Alternatively, a memory device including a transistor with a large on-state current can be provided. Alternatively, a memory device with less variation in transistor characteristics can be provided. Alternatively, a storage device with good electrical characteristics can be provided.
　本実施の形態に示す、トランジスタ２００及び容量素子１００を有するメモリセル１５０は、記憶装置のメモリセルとして用いることができる。トランジスタ２００は、酸化物半導体を有する半導体層にチャネルが形成されるトランジスタである。トランジスタ２００は、オフ電流が小さいため、これを記憶装置に用いることにより長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、または、リフレッシュ動作の頻度が極めて少ないため、記憶装置の消費電力を十分に低減できる。また、トランジスタ２００の周波数特性が高いため、記憶装置の読み出し、および書き込みを高速に行うことができる。 The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a small off-state current, it is possible to retain stored contents for a long period of time by using the transistor 200 in a memory device. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced. Further, since the transistor 200 has high frequency characteristics, reading and writing to the memory device can be performed at high speed.
　また、２個のメモリセル１５０（以下、メモリセル１５０ａ及びメモリセル１５０ｂと呼ぶ）を共通の配線に接続する記憶装置の例について、図３９Ａ及び図３９Ｂを用いて説明する。図３９Ａは、記憶装置の平面図である。また、図３９Ｂは、図３９ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。なお、図３９Ａの平面図では、図の明瞭化のために一部の要素を省いている。 Furthermore, an example of a memory device in which two memory cells 150 (hereinafter referred to as memory cells 150a and 150b) are connected to a common wiring will be described with reference to FIGS. 39A and 39B. FIG. 39A is a plan view of the storage device. Further, FIG. 39B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 39A. Note that in the plan view of FIG. 39A, some elements are omitted for clarity.
　ここで、図３９Ａ及び図３９Ｂに示すメモリセル１５０ａ及びメモリセル１５０ｂのそれぞれは、メモリセル１５０と同様の構成を有する。メモリセル１５０ａは、容量素子１００ａ及びトランジスタ２００ａを有し、メモリセル１５０ｂは、容量素子１００ｂ及びトランジスタ２００ｂを有する。よって、図３９Ａ及び図３９Ｂに示す記憶装置において、図１に示した記憶装置を構成する構造と同機能を有する構造には、同符号を付記する。なお、本項目においても、記憶装置の構成材料については＜記憶装置の構成例＞で詳細に説明した材料を用いることができる。 Here, each of the memory cell 150a and the memory cell 150b shown in FIGS. 39A and 39B has the same configuration as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. Therefore, in the storage devices shown in FIGS. 39A and 39B, structures having the same functions as the structures configuring the storage device shown in FIG. 1 are given the same reference numerals. Note that also in this item, the materials described in detail in <Example of configuration of storage device> can be used as the constituent materials of the storage device.
　図３９Ａ及び図３９Ｂに示すように、配線ＷＬとして機能する導電体２６０は、メモリセル１５０ａ及びメモリセル１５０ｂに、それぞれ設けられる。また、配線ＢＬの一部として機能する導電体２４０は、メモリセル１５０ａ及びメモリセル１５０ｂに、共通に設けられる。つまり、導電体２４０は、メモリセル１５０ａの酸化物半導体２３０と、メモリセル１５０ｂの酸化物半導体２３０に接する。 As shown in FIGS. 39A and 39B, the conductor 260 functioning as the wiring WL is provided in the memory cell 150a and the memory cell 150b, respectively. Further, a conductor 240 that functions as a part of the wiring BL is provided in common to the memory cell 150a and the memory cell 150b. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.
　ここで、図３９Ａ及び図３９Ｂに示す記憶装置は、メモリセル１５０ａ及びメモリセル１５０ｂと電気的に接続してプラグ（接続電極とよぶこともできる）として機能する、導電体２４５及び導電体２４６を有する。導電体２４５は、絶縁体１８０、絶縁体１３０、絶縁体２８０、及び絶縁体１４０に形成された開口内に配置され、導電体２４０の下面に接する。また、導電体２４６は、絶縁体２８７、絶縁体２８３、及び絶縁体２５０に形成された開口内に配置され、導電体２４０の上面に接する。なお、導電体２４５及び導電体２４６は、導電体２４０に適用可能な導電性材料などを用いることができる。 Here, the memory device shown in FIGS. 39A and 39B includes a conductor 245 and a conductor 246 that are electrically connected to the memory cell 150a and the memory cell 150b and function as a plug (also referred to as a connection electrode). have The conductor 245 is disposed within the openings formed in the insulator 180, the insulator 130, the insulator 280, and the insulator 140, and is in contact with the lower surface of the conductor 240. Further, the conductor 246 is disposed within the openings formed in the insulator 287, the insulator 283, and the insulator 250, and is in contact with the upper surface of the conductor 240. Note that for the conductor 245 and the conductor 246, a conductive material that can be used for the conductor 240 can be used.
　絶縁体２８７は、層間膜として機能するため、比誘電率が低いことが好ましい。比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。絶縁体２８７としては、前述した［絶縁体］の項目に記載の、比誘電率が低い材料含む絶縁体を、単層または積層で用いることができる。 Since the insulator 287 functions as an interlayer film, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 287, an insulator containing a material with a low dielectric constant described in the above-mentioned [Insulator] item can be used in a single layer or a laminated form.
　また、絶縁体２８７中の水、水素などの不純物濃度は低減されていることが好ましい。これにより、酸化物半導体２３０のチャネル形成領域に、水、水素などの不純物が混入するのを抑制できる。 Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 287 is reduced. Thereby, impurities such as water and hydrogen can be suppressed from entering the channel formation region of the oxide semiconductor 230.
　導電体２４５及び導電体２４６は、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、およびダイオードなどの回路素子、配線、電極、または、端子と、メモリセル１５０ａ及びメモリセル１５０ｂを電気的に接続するためのプラグまたは配線として機能する。例えば、導電体２４５が、図３９に示す記憶装置の下に設けられたセンスアンプ（図示せず）に電気的に接続され、導電体２４６が、図３９に示す記憶装置の上に設けられた同様の記憶装置（図示せず）と電気的に接続される構成にすることができる。この場合、導電体２４５及び導電体２４６は、配線ＢＬの一部として機能する。このように、図３９に示す記憶装置の上または下に記憶装置などを設けることで、単位面積当たりの記憶容量を大きくすることができる。 The conductor 245 and the conductor 246 electrically connect the memory cell 150a and the memory cell 150b to circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistance elements, and diodes. Acts as a plug or wiring for. For example, a conductor 245 is electrically connected to a sense amplifier (not shown) provided below the storage device shown in FIG. 39, and a conductor 246 is provided above the storage device shown in FIG. It can be configured to be electrically connected to a similar storage device (not shown). In this case, the conductor 245 and the conductor 246 function as part of the wiring BL. In this way, by providing a storage device or the like above or below the storage device shown in FIG. 39, the storage capacity per unit area can be increased.
　また、メモリセル１５０ａとメモリセル１５０ｂは、一点鎖線Ａ１−Ａ２の垂直二等分線を対称軸とした線対称の構成となっている。よって、トランジスタ２００ａとトランジスタ２００ｂも、導電体２４５及び導電体２４６を挟んで、線対称の位置に配置される。ここで、導電体２４０は、トランジスタ２００ａのソース電極及びドレイン電極の他方としての機能と、トランジスタ２００ｂのソース電極及びドレイン電極の他方としての機能とを有する。また、トランジスタ２００ａ及びトランジスタ２００ｂは、プラグとして機能する導電体２４５及び導電体２４６を共有する。このように、２つのトランジスタと、プラグとの接続を上述の構成とすることで、微細化または高集積化が可能な記憶装置を提供できる。 Furthermore, the memory cell 150a and the memory cell 150b have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged in line-symmetrical positions with the conductor 245 and the conductor 246 in between. Here, the conductor 240 has a function as the other of the source electrode and the drain electrode of the transistor 200a, and a function as the other of the source electrode and the drain electrode of the transistor 200b. Further, the transistor 200a and the transistor 200b share a conductor 245 and a conductor 246 that function as a plug. In this way, by connecting the two transistors and the plug to the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
　なお、配線ＰＬとして機能する導電体１１０は、メモリセル１５０ａ及びメモリセル１５０ｂに、それぞれ設けてもよいし、メモリセル１５０ａ及びメモリセル１５０ｂに、共通に設けてもよい。ただし、図３９Ｂに示すように、導電体１１０は、導電体２４５と離隔して設け、導電体１１０と導電体２４５がショートしないようにする。 Note that the conductor 110 functioning as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in common in the memory cell 150a and the memory cell 150b. However, as shown in FIG. 39B, the conductor 110 is provided apart from the conductor 245 to prevent short circuit between the conductor 110 and the conductor 245.
　また、メモリセル１５０を３次元的にマトリクス状に配置することで、メモリセルアレイを構成することができる。メモリセルアレイの一例として、図４０Ａ及び図４０Ｂに、Ｘ方向、Ｙ方向、及びＺ方向に、４個×２個×４個のメモリセル１５０を配置した記憶装置の例を示す。図４０Ａは、記憶装置の平面図である。また、図４０Ｂは、図４０ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。なお、図４０Ａの平面図では、図の明瞭化のために一部の要素を省いている。 Furthermore, a memory cell array can be configured by arranging the memory cells 150 three-dimensionally in a matrix. As an example of a memory cell array, FIGS. 40A and 40B show an example of a memory device in which 4×2×4 memory cells 150 are arranged in the X direction, Y direction, and Z direction. FIG. 40A is a plan view of the storage device. Moreover, FIG. 40B is a cross-sectional view of the portion shown by the dashed line A1-A2 in FIG. 40A. Note that in the plan view of FIG. 40A, some elements are omitted for clarity.
　ここで、図４０Ａ及び図４０Ｂに示すメモリセル１５０ａ乃至メモリセル１５０ｄのそれぞれは、メモリセル１５０と同様の構成を有する。メモリセル１５０ａは、容量素子１００ａ及びトランジスタ２００ａを有し、メモリセル１５０ｂは、容量素子１００ｂ及びトランジスタ２００ｂを有し、メモリセル１５０ｃは、容量素子１００ｃ及びトランジスタ２００ｃを有し、メモリセル１５０ｄは、容量素子１００ｄ及びトランジスタ２００ｄを有する。よって、図４０Ａ及び図４０Ｂに示す記憶装置において、図１に示した記憶装置を構成する構造と同機能を有する構造には、同符号を付記する。なお、本項目においても、記憶装置の構成材料については＜記憶装置の構成例＞で詳細に説明した材料を用いることができる。 Here, each of the memory cells 150a to 150d shown in FIGS. 40A and 40B has the same configuration as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, the memory cell 150b includes a capacitor 100b and a transistor 200b, the memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes: It has a capacitive element 100d and a transistor 200d. Therefore, in the storage devices shown in FIGS. 40A and 40B, structures having the same functions as the structures configuring the storage device shown in FIG. 1 are given the same reference numerals. Note that also in this item, the materials described in detail in <Example of configuration of storage device> can be used as the constituent materials of the storage device.
　以下において、メモリセル１５０ａ乃至メモリセル１５０ｄからなる記憶装置をメモリユニットと呼ぶ。図４０Ａ及び図４０Ｂに示す記憶装置は、メモリユニット１６０［１，１］乃至メモリユニット１６０［２，４］を有する。なお、以下において、メモリユニット１６０［１，１］乃至メモリユニット１６０［２，４］をまとめて、メモリユニット１６０と呼ぶ場合がある。メモリユニット１６０［１，２］は、メモリユニット１６０［１，１］上に設けられ、メモリユニット１６０［１，３］は、メモリユニット１６０［１，２］上に設けられ、メモリユニット１６０［１，４］は、メモリユニット１６０［１，３］上に設けられる。メモリユニット１６０［２，１］は、メモリユニット１６０［１，１］のＹ方向に隣接して設けられる。メモリユニット１６０［２，２］は、メモリユニット１６０［２，１］の上に設けられ、メモリユニット１６０［２，３］は、メモリユニット１６０［２，２］の上に設けられ、メモリユニット１６０［２，４］は、メモリユニット１６０［２，３］の上に設けられる。 Hereinafter, a storage device made up of memory cells 150a to 150d will be referred to as a memory unit. The storage device shown in FIGS. 40A and 40B includes memory units 160[1,1] to 160[2,4]. Note that hereinafter, the memory units 160[1,1] to 160[2,4] may be collectively referred to as the memory unit 160. Memory unit 160[1,2] is provided on memory unit 160[1,1], memory unit 160[1,3] is provided on memory unit 160[1,2], and memory unit 160[1,3] is provided on memory unit 160[1,2]. 1,4] are provided on the memory unit 160[1,3]. Memory unit 160[2,1] is provided adjacent to memory unit 160[1,1] in the Y direction. Memory unit 160[2,2] is provided above memory unit 160[2,1], and memory unit 160[2,3] is provided above memory unit 160[2,2], and memory unit 160[2,3] is provided above memory unit 160[2,2]. 160[2,4] is provided above memory unit 160[2,3].
　メモリユニット１６０は、図４０Ｂに示すように、導電体２４５を中心にして、メモリセル１５０ａの外側にメモリセル１５０ｃが配置され、メモリセル１５０ｂの外側にメモリセル１５０ｄが配置されている。つまり、図３９に示す記憶装置において、メモリセル１５０ａに隣接してメモリセル１５０ｃを設け、メモリセル１５０ｂに隣接してメモリセル１５０ｄを設けた、記憶装置ともいえる。 As shown in FIG. 40B, in the memory unit 160, a memory cell 150c is arranged outside the memory cell 150a, and a memory cell 150d is arranged outside the memory cell 150b, with the conductor 245 at the center. In other words, in the memory device shown in FIG. 39, the memory cell 150c is provided adjacent to the memory cell 150a, and the memory cell 150d is provided adjacent to the memory cell 150b.
　図４０Ａ及び図４０Ｂに示すように、配線ＷＬとして機能する導電体２６０は、Ｙ方向に隣接するメモリセル１５０同士で共有されている。また、配線ＢＬの一部として機能する導電体２４０は、同一メモリユニット内で共有されている。つまり、導電体２４０は、メモリセル１５０ａ乃至メモリセル１５０ｄの、それぞれの酸化物半導体２３０に接する。 As shown in FIGS. 40A and 40B, the conductor 260 functioning as the wiring WL is shared by memory cells 150 adjacent to each other in the Y direction. Furthermore, the conductor 240 that functions as part of the wiring BL is shared within the same memory unit. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of each of the memory cells 150a to 150d.
　Ｚ方向に隣接するメモリユニットが有する導電体２４０の間に導電体２４５が設けられる。例えば、図４０Ｂに示すように、導電体２４５は、メモリユニット１６０［１，１］の導電体２４０の上面と、メモリユニット１６０［１，２］の導電体２４０の下面に接して設けられる。このように、各メモリユニット１６０に設けられた、導電体２４０と導電体２４５によって、配線ＢＬが形成される。導電体２４５は、図４０に示す記憶装置の下に設けられたセンスアンプ（図示せず）に電気的に接続される。このように、図４０に示す記憶装置において、複数のメモリユニットを積層することで、単位面積当たりの記憶容量を大きくすることができる。 A conductor 245 is provided between conductors 240 of memory units adjacent in the Z direction. For example, as shown in FIG. 40B, the conductor 245 is provided in contact with the upper surface of the conductor 240 of the memory unit 160[1,1] and the lower surface of the conductor 240 of the memory unit 160[1,2]. In this way, the wiring BL is formed by the conductor 240 and the conductor 245 provided in each memory unit 160. The conductor 245 is electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. In this way, in the storage device shown in FIG. 40, by stacking a plurality of memory units, the storage capacity per unit area can be increased.
　また、メモリセル１５０ａ及びメモリセル１５０ｃと、メモリセル１５０ｂ及びメモリセル１５０ｄとは、一点鎖線Ａ１−Ａ２の垂直二等分線を対称軸とした線対称の構成となっている。よって、トランジスタ２００ａ及びトランジスタ２００ｃと、トランジスタ２００ｂ及びトランジスタ２００ｄも、導電体２４５を挟んで、線対称の位置に配置される。ここで、導電体２４０は、トランジスタ２００ａ乃至トランジスタ２００ｄそれぞれのソース電極及びドレイン電極の他方としての機能を有する。また、トランジスタ２００ａ乃至トランジスタ２００ｄは、プラグとして機能する導電体２４５を共有する。このように、４つのトランジスタと、プラグとの接続を上述の構成とすることで、微細化または高集積化が可能な記憶装置を提供できる。 Furthermore, the memory cell 150a and the memory cell 150c, and the memory cell 150b and the memory cell 150d have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200c, and the transistor 200b and the transistor 200d are also arranged in line-symmetrical positions with the conductor 245 in between. Here, the conductor 240 functions as the other of the source electrode and drain electrode of each of the transistors 200a to 200d. Furthermore, the transistors 200a to 200d share a conductor 245 that functions as a plug. In this way, by connecting the four transistors and the plugs in the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
　図４０に示すように、複数のメモリセルを積層することにより、メモリセルアレイの占有面積を増やすことなく、セルを集積して配置することができる。つまり、３Ｄメモリセルアレイを構成することができる。なお、図４０では、２つのメモリユニットを有する層を４層積層する構成を例示したが、本発明はこれに限られるものではない。記憶装置は、少なくとも一つのメモリセル１５０を有する層を１層有してもよいし、２層以上積層してもよい。 As shown in FIG. 40, by stacking a plurality of memory cells, cells can be arranged in an integrated manner without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. Note that although FIG. 40 illustrates a configuration in which four layers each having two memory units are stacked, the present invention is not limited to this. The memory device may have one layer having at least one memory cell 150, or may have two or more layers stacked.
　図４０では、プラグとして機能する導電体２４５がメモリセル１５０間に配置される構成を示している。別言すると、プラグとして機能する導電体２４５がメモリユニット１６０の内側に配置される構成を示している。なお、本発明はこれに限られるものではない。導電体２４５は、メモリユニットの外側に配置されてもよい。 FIG. 40 shows a configuration in which a conductor 245 functioning as a plug is arranged between memory cells 150. In other words, a configuration is shown in which the conductor 245 functioning as a plug is arranged inside the memory unit 160. Note that the present invention is not limited to this. Electrical conductor 245 may be placed outside the memory unit.
　メモリセルアレイの一例として、図４１Ａ及び図４１Ｂに、Ｘ方向、Ｙ方向、及びＺ方向に、３個×３個×４個のメモリセル１５０を配置した記憶装置の例を示す。図４１Ａは、記憶装置の平面図である。また、図４１Ｂは、図４１ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。なお、図４１Ａの平面図では、図の明瞭化のために一部の要素を省いている。 As an example of a memory cell array, FIGS. 41A and 41B show an example of a memory device in which 3×3×4 memory cells 150 are arranged in the X direction, Y direction, and Z direction. FIG. 41A is a plan view of the storage device. Further, FIG. 41B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 41A. Note that in the plan view of FIG. 41A, some elements are omitted for clarity.
　図４１Ａ及び図４１Ｂに示す記憶装置は、メモリセル１５０を含む層がｍ（ｍは２以上の整数である）層積層された構成を有する。ここで、１層目（一番下）に設けられた上記層を層１７０［１］とし、２層目に設けられた上記層を層１７０［２］とし、（ｍ−１）層目に設けられた上記層を層１７０［ｍ−１］とし、ｍ層目（一番上）に設けられた上記層を層１７０［ｍ］として、図４１Ｂに図示している。つまり、本発明の一態様の記憶装置は、メモリセル１５０を含む層を複数有し、複数の層が積層されている構成を有してもよい。 The memory device shown in FIGS. 41A and 41B has a structure in which m (m is an integer of 2 or more) layers including the memory cell 150 are laminated. Here, the above layer provided as the first layer (bottom) is referred to as layer 170[1], the above layer provided as the second layer is referred to as layer 170[2], and the (m-1) layer is referred to as layer 170[1]. FIG. 41B shows the provided layer as a layer 170 [m-1], and the m-th (top) layer as a layer 170 [m]. In other words, the memory device of one embodiment of the present invention may have a plurality of layers including the memory cell 150, and may have a structure in which the plurality of layers are stacked.
　図４１Ａ及び図４１Ｂに示すように、導電体２４５は、メモリユニットの外側に設けられてもよい。また、導電体２４５は、当該導電体２４５を含む層の上層に設けられた配線と電気的に接続されてもよい。例えば、層１７０［１］に設けられている導電体２４５は、層１７０［２］に設けられている配線と電気的に接続されている。なお、層１７０［２］に設けられている当該配線は、層１７０［２］に含まれるメモリセル１５０の下部電極（導電体１１０）と同じ層に設けられている。つまり、当該配線は、導電体１１０と同じ工程で形成することができる。 As shown in FIGS. 41A and 41B, the conductor 245 may be provided outside the memory unit. Further, the conductor 245 may be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in layer 170[1] is electrically connected to the wiring provided in layer 170[2]. Note that the wiring provided in layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[2]. In other words, the wiring can be formed in the same process as the conductor 110.
　なお、図４１では、導電体２４５が、当該導電体２４５を含む層の上層に設けられた配線と電気的に接続される構成を示しているが、本発明はこれに限られるものではない。例えば、導電体２４５は、当該導電体２４５を含む層に設けられた配線と電気的に接続されてもよい。例えば、層１７０［１］に設けられている導電体２４５は、層１７０［１］に設けられている配線と電気的に接続されてもよい。なお、層１７０［１］に設けられている当該配線は、層１７０［１］に含まれるメモリセル１５０の下部電極（導電体１１０）と同じ層に設けられている。つまり、当該配線は、導電体１１０と同じ工程で形成することができる。 Note that although FIG. 41 shows a configuration in which the conductor 245 is electrically connected to wiring provided in the upper layer of the layer containing the conductor 245, the present invention is not limited to this. For example, the conductor 245 may be electrically connected to wiring provided in a layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] may be electrically connected to the wiring provided in the layer 170[1]. Note that the wiring provided in layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.
　ここで、図４１Ａに示す記憶装置の平面レイアウトを図４２Ａに示す。具体的には、図４２Ａの平面レイアウトでは、４個×４個のメモリセル１５０を含む領域を示している。また、配線ＷＬとして機能する導電体２６０、配線ＢＬとして機能する導電体２４０、及び開口部２９０を図示している。なお、導電体２６０、導電体２４０、及び開口部２９０が重なる領域にメモリセル１５０が設けられている。別言すると、開口部２９０は、導電体２４０の、導電体２４０と導電体２６０とが交差する領域に設けられる。 Here, the planar layout of the storage device shown in FIG. 41A is shown in FIG. 42A. Specifically, the planar layout of FIG. 42A shows a region including 4×4 memory cells 150. Further, a conductor 260 functioning as the wiring WL, a conductor 240 functioning as the wiring BL, and an opening 290 are illustrated. Note that the memory cell 150 is provided in a region where the conductor 260, the conductor 240, and the opening 290 overlap. In other words, the opening 290 is provided in a region of the conductor 240 where the conductor 240 and the conductor 260 intersect.
　図４２Ａでは、メモリセル１５０がマトリクス状に配置されている構成を示している。また、開口部２９０がマトリクス状に配置されている構成を示している。また、導電体２６０がＹ方向に延在して設けられ、導電体２４０がＸ方向に延在して設けられている構成を示している。別言すると、導電体２６０と導電体２４０とが直交する構成を示している。また、導電体２６０が延在する方向と垂直な方向（Ｘ方向）における導電体２６０の幅が一様であり、導電体２４０が延在する方向と垂直な方向（Ｙ方向）における導電体２４０の幅が一様である構成を示している。なお、本発明はこれに限られるものではない。 FIG. 42A shows a configuration in which memory cells 150 are arranged in a matrix. Further, a configuration is shown in which the openings 290 are arranged in a matrix. Further, a configuration is shown in which a conductor 260 is provided extending in the Y direction, and a conductor 240 is provided extending in the X direction. In other words, a configuration is shown in which the conductor 260 and the conductor 240 are perpendicular to each other. Further, the width of the conductor 260 in the direction (X direction) perpendicular to the direction in which the conductor 260 extends is uniform, and the width of the conductor 260 in the direction (Y direction) perpendicular to the direction in which the conductor 240 extends is uniform. This shows a configuration in which the width of the area is uniform. Note that the present invention is not limited to this.
　図４２Ｂは、記憶装置の平面レイアウトの別の一例である。図４２Ｂの平面レイアウトでは、図４２Ａと同様に、導電体２６０、導電体２４０、メモリセル１５０、及び開口部２９０を図示している。図４２Ｂに示す記憶装置は、メモリセル１５０（開口部２９０）の配置、導電体２４０の形状、及び、導電体２６０が延在する方向が、図４２Ａに示す記憶装置と主に異なる。 FIG. 42B is another example of the planar layout of the storage device. The planar layout of FIG. 42B illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 42A. The memory device shown in FIG. 42B differs from the memory device shown in FIG. 42A mainly in the arrangement of the memory cells 150 (openings 290), the shape of the conductors 240, and the direction in which the conductors 260 extend.
　図４２Ｂに示すように、メモリセル１５０（開口部２９０）は、奇数行と偶数行とで、メモリセル１５０（開口部２９０）の繰り返し単位の半分だけずれて配列されていてもよい。また、メモリセル１５０（開口部２９０）は、奇数列と偶数列とで、当該繰り返し単位の半分だけずれて配列されていてもよい。 As shown in FIG. 42B, the memory cells 150 (openings 290) may be arranged such that the odd-numbered rows and the even-numbered rows are shifted by half of the repeating unit of the memory cells 150 (openings 290). Furthermore, the memory cells 150 (openings 290) may be arranged so as to be shifted by half of the repeating unit between odd-numbered columns and even-numbered columns.
　図４２Ｂにおいて、第１のメモリセルとＸ方向に隣接するメモリセルを第２のメモリセルとし、第１のメモリセル及び第２のメモリセルとＹ方向に隣接するメモリセルを、第３のメモリセルとする。例えば、第１のメモリセルと第２のメモリセルの中間を通り、Ｙ方向に平行な直線上に、第３のメモリセルの中心が位置するとよい。このとき、第３のメモリセルは、第１のメモリセル及び第２のメモリセルとＸ方向に半分ずれた位置に位置するともいえる。 In FIG. 42B, a memory cell adjacent to the first memory cell in the X direction is a second memory cell, and a memory cell adjacent to the first memory cell and the second memory cell in the Y direction is a third memory cell. Cell. For example, the center of the third memory cell may be located on a straight line that passes between the first memory cell and the second memory cell and is parallel to the Y direction. At this time, it can be said that the third memory cell is located at a position shifted by half in the X direction from the first memory cell and the second memory cell.
　また、図４２Ｂに示すように、導電体２４０は、第１の領域と、第２の領域と、を有する。第１の領域は、開口部２９０及びその近傍の領域であり、第１の領域におけるＹ方向の幅を第１の幅とする。平面視において第１の領域は、四角形の角部を丸めた形状といえる。また、第２の領域は、１つの導電体２４０において隣接する開口部２９０の間の領域であり、第２の領域におけるＹ方向の幅を第２の幅とする。このとき、第２の幅は、第１の幅よりも小さいことが好ましい。このような構成にすることで、メモリセル１５０（開口部２９０）を、行及び列ごとに、繰り返し単位の半分ずらして配列する場合に、導電体２４０間の物理距離を小さくすることができる。よって、記憶装置の微細化及び高集積化を図ることができる。 Further, as shown in FIG. 42B, the conductor 240 has a first region and a second region. The first region is the opening 290 and its vicinity, and the width of the first region in the Y direction is defined as the first width. In plan view, the first region can be said to have a shape of a quadrilateral with rounded corners. Further, the second region is a region between adjacent openings 290 in one conductor 240, and the width in the Y direction in the second region is defined as the second width. At this time, the second width is preferably smaller than the first width. With this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
　また、図４２Ｂでは、導電体２６０の延伸方向が、Ｙ方向に対して傾けて配置されている。つまり、メモリセル１５０（開口部２９０）の配置によっては、導電体２６０の延伸方向は、導電体２４０の延伸方向と直交しない場合がある。別言すると、導電体２６０は、導電体２４０と交差するとよい。 Furthermore, in FIG. 42B, the extending direction of the conductor 260 is arranged at an angle with respect to the Y direction. That is, depending on the arrangement of the memory cells 150 (openings 290), the extending direction of the conductor 260 may not be orthogonal to the extending direction of the conductor 240. In other words, the conductor 260 may intersect with the conductor 240.
　図４２Ｃは、記憶装置の平面レイアウトの別の一例である。図４２Ｃの平面レイアウトでは、図４２Ｂと同様に、導電体２６０、導電体２４０、メモリセル１５０、及び開口部２９０を図示している。図４２Ｃに示す記憶装置は、導電体２４０の第１の領域の形状が、図４２Ｂに示す記憶装置と主に異なる。 FIG. 42C is another example of the planar layout of the storage device. The planar layout of FIG. 42C illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similarly to FIG. 42B. The memory device shown in FIG. 42C differs from the memory device shown in FIG. 42B mainly in the shape of the first region of the conductor 240.
　図４２Ｂに示す導電体２４０の第１の領域は、平面視において四角形の角部を丸めた形状であり、当該四角形の一辺がＸ方向又はＹ方向に平行となっている。一方、図４２Ｃに示す導電体２４０の第１の領域は、平面視において四角形の角部を丸めた形状であり、当該四角形の対角線がＸ方向又はＹ方向に平行となっている。このような構成にすることで、メモリセル１５０（開口部２９０）を、行及び列ごとに、繰り返し単位の半分ずらして配列する場合に、導電体２４０間の物理距離を小さくすることができる。よって、記憶装置の微細化及び高集積化を図ることができる。 The first region of the conductor 240 shown in FIG. 42B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X direction or the Y direction. On the other hand, the first region of the conductor 240 shown in FIG. 42C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X direction or the Y direction. With this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
　図４２Ｂ及び図４２Ｃでは、導電体２４０の第１の領域が、平面視において四角形の角部を丸めた形状である例を示しているが、本発明はこれに限られるものではない。 Although FIGS. 42B and 42C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in plan view, the present invention is not limited to this.
　図４３Ａは、記憶装置の平面レイアウトの別の一例である。図４３Ａの平面レイアウトでは、図４２Ｂと同様に、導電体２６０、導電体２４０、メモリセル１５０、及び開口部２９０を図示している。図４３Ａに示す記憶装置は、導電体２４０の第１の領域の形状が、図４２Ｂ又は図４２Ｃに示す記憶装置と主に異なる。 FIG. 43A is another example of the planar layout of the storage device. The planar layout of FIG. 43A illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 42B. The memory device shown in FIG. 43A differs from the memory device shown in FIG. 42B or 42C mainly in the shape of the first region of the conductor 240.
　図４３Ａに示す導電体２４０の第１の領域は、平面視において円形状である。このような構成にすることで、メモリセル１５０（開口部２９０）を、行及び列ごとに、繰り返し単位の半分ずらして配列する場合に、導電体２４０間の物理距離を小さくすることができる。よって、記憶装置の微細化及び高集積化を図ることができる。 The first region of the conductor 240 shown in FIG. 43A has a circular shape in plan view. With this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
　なお、平面視における導電体２４０の第１の領域は、前述した形状に限定されない。例えば、平面視における導電体２４０の第１の領域は、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。 Note that the first region of the conductor 240 in plan view is not limited to the shape described above. For example, the first region of the conductor 240 in plan view may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
　また、図４３Ａでは、導電体２６０が延在する方向と垂直な方向における導電体２６０の幅が一様である構成を示しているが、本発明はこれに限られるものではない。 Further, although FIG. 43A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, the present invention is not limited to this.
　図４３Ｂは、記憶装置の平面レイアウトの別の一例である。図４３Ｂの平面レイアウトでは、図４３Ａと同様に、導電体２６０、導電体２４０、メモリセル１５０、及び開口部２９０を図示している。図４３Ｂに示す記憶装置は、導電体２６０の形状が、図４３Ａに示す記憶装置と主に異なる。 FIG. 43B is another example of the planar layout of the storage device. The planar layout of FIG. 43B illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 43A. The memory device shown in FIG. 43B differs from the memory device shown in FIG. 43A mainly in the shape of the conductor 260.
　図４３Ｂに示す導電体２６０は、導電体２４０と同様に、第１の領域と、第２の領域と、を有する。第１の領域は、開口部２９０及びその近傍の領域であり、平面視において円形状である。また、第２の領域は、１つの導電体２６０において隣接する開口部２９０の間の領域である。なお、導電体２６０の第１の領域は、導電体２４０の第１の領域と重なる。このような構成にすることで、メモリセル１５０（開口部２９０）を、行及び列ごとに、繰り返し単位の半分ずらして配列する場合に、導電体２４０間の物理距離を小さくすることができる。よって、記憶装置の微細化及び高集積化を図ることができる。 Similarly to the conductor 240, the conductor 260 shown in FIG. 43B has a first region and a second region. The first region is the opening 290 and its vicinity, and is circular in plan view. Further, the second region is a region between adjacent openings 290 in one conductor 260. Note that the first region of the conductor 260 overlaps with the first region of the conductor 240. With this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
　図４３Ｃは、記憶装置の平面レイアウトの別の一例である。図４３Ｃの平面レイアウトでは、図４３Ａと同様に、導電体２６０、導電体２４０、メモリセル１５０、及び開口部２９０を図示している。図４３Ｃに示す記憶装置は、導電体２６０の形状及び延伸方向が、図４３Ａに示す記憶装置と主に異なる。 FIG. 43C is another example of the planar layout of the storage device. The planar layout of FIG. 43C illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 43A. The memory device shown in FIG. 43C differs from the memory device shown in FIG. 43A mainly in the shape and stretching direction of the conductor 260.
　図４３Ｃに示す導電体２６０は、平面視において三角波のような蛇行形状であり、Ｙ方向に延在して設けられている。このような構成にすることで、メモリセル１５０（開口部２９０）を、行及び列ごとに、繰り返し単位の半分ずらして配列する場合に、導電体２４０間の物理距離を小さくすることができる。よって、記憶装置の微細化及び高集積化を図ることができる。なお、平面視における導電体２６０は上記に限られず、ミアンダ形状などであってもよい。 The conductor 260 shown in FIG. 43C has a meandering shape like a triangular wave in plan view, and is provided extending in the Y direction. With this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (openings 290) are arranged in rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved. Note that the conductor 260 in plan view is not limited to the above, and may have a meander shape or the like.
　上記の構成にすることで、導電体２６０間の物理距離、及び導電体２４０間の物理距離の一方又は両方を小さくし、記憶装置の微細化及び高集積化を図ることができる。 With the above configuration, one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, and the storage device can be miniaturized and highly integrated.
　図４４に、センスアンプを含む駆動回路が設けられる層上に、メモリセルを有する層が積層して設けられた記憶装置の断面構成例を示す。 FIG. 44 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked on a layer in which a drive circuit including a sense amplifier is provided.
　図４４では、トランジスタ３００の上方に容量素子１００が設けられ、トランジスタ３００及び容量素子１００の上方にトランジスタ２００が設けられている。 In FIG. 44, the capacitor 100 is provided above the transistor 300, and the transistor 200 is provided above the transistor 300 and the capacitor 100.
　トランジスタ３００は、センスアンプが有するトランジスタの一つである。 The transistor 300 is one of the transistors included in the sense amplifier.
　図４４に示すメモリセル１５０（トランジスタ２００及び容量素子１００）の構成は、上述の通りである。 The configuration of the memory cell 150 (transistor 200 and capacitor 100) shown in FIG. 44 is as described above.
　図４４に示すように、メモリセル１５０と重なるように、センスアンプを設ける構成にすることで、ビット線を短くすることができる。これにより、ビット線容量が小さくなり、メモリセルの保持容量を低減することができる。 As shown in FIG. 44, by providing a sense amplifier so as to overlap the memory cell 150, the bit line can be shortened. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell.
　また、トランジスタ２００を容量素子１００の上方に設けることで、トランジスタ２００は、容量素子１００の作製時の熱処理の影響を受けない。したがって、トランジスタ２００において、しきい値電圧の変動、及び寄生抵抗の増大などの電気特性の劣化、並びに電気特性の劣化に伴う電気特性のばらつきの増大などを抑制することができる。 Further, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as fluctuation in threshold voltage and increase in parasitic resistance, and increase in variation in electrical characteristics due to deterioration of electrical characteristics can be suppressed.
　図４４に示す記憶装置は、実施の形態２で説明する記憶装置８０と対応させることができる。具体的には、トランジスタ３００は、記憶装置８０におけるセンスアンプ４６が有するトランジスタに相当する。また、メモリセル１５０は、メモリセル３２と対応し、トランジスタ２００は、トランジスタ３７に相当し、容量素子１００は、容量素子３８に相当する。 The storage device shown in FIG. 44 can correspond to the storage device 80 described in Embodiment 2. Specifically, transistor 300 corresponds to a transistor included in sense amplifier 46 in memory device 80. Further, the memory cell 150 corresponds to the memory cell 32, the transistor 200 corresponds to the transistor 37, and the capacitor 100 corresponds to the capacitor 38.
　トランジスタ３００は、基板３１１上に設けられ、ゲートとして機能する導電体３１６と、ゲート絶縁体として機能する絶縁体３１５と、基板３１１の一部からなる半導体領域３１３と、ソース領域またはドレイン領域として機能する低抵抗領域３１４ａ及び低抵抗領域３１４ｂと、を有する。トランジスタ３００は、ｐチャネル型またはｎチャネル型のいずれでもよい。 The transistor 300 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and functions as a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b. Transistor 300 may be either a p-channel type or an n-channel type.
　ここで、図４４に示すトランジスタ３００はチャネルが形成される半導体領域３１３（基板３１１の一部）が凸形状を有する。また、半導体領域３１３の側面及び上面を、絶縁体３１５を介して、導電体３１６が覆うように設けられている。なお、導電体３１６は仕事関数を調整する材料を用いてもよい。このようなトランジスタ３００は半導体基板の凸部を利用していることからＦＩＮ型トランジスタとも呼ばれる。なお、凸部の上部に接して、凸部を形成するためのマスクとして機能する絶縁体を有していてもよい。また、ここでは半導体基板の一部を加工して凸部を形成する場合を示したが、ＳＯＩ基板を加工して凸形状を有する半導体膜を形成してもよい。 Here, in the transistor 300 shown in FIG. 44, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. Furthermore, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate. Note that an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion. Furthermore, although a case is shown in which a portion of the semiconductor substrate is processed to form a convex portion, a semiconductor film having a convex shape may be formed by processing an SOI substrate.
　なお、図４４に示すトランジスタ３００は一例であり、その構造に限定されず、回路構成または駆動方法に応じて適切なトランジスタを用いることができる。 Note that the transistor 300 shown in FIG. 44 is an example, and the structure is not limited, and an appropriate transistor can be used depending on the circuit configuration or driving method.
　各構造体の間には、層間膜、配線、及びプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線として機能する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、及び導電体の一部がプラグとして機能する場合もある。 A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Here, a plurality of structures of a conductor functioning as a plug or a wiring may be given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
　例えば、トランジスタ３００上には、層間膜として、絶縁体３２０、絶縁体３２２、絶縁体３２４、及び絶縁体３２６が順に積層して設けられている。また、絶縁体３２０及び絶縁体３２２には導電体３２８が埋め込まれ、絶縁体３２４及び絶縁体３２６には導電体３３０が埋め込まれている。なお、導電体３２８及び導電体３３０はプラグ、または配線として機能する。 For example, on the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided as interlayer films. Further, a conductor 328 is embedded in the insulator 320 and the insulator 322, and a conductor 330 is embedded in the insulator 324 and the insulator 326. Note that the conductor 328 and the conductor 330 function as a plug or wiring.
　また、層間膜として機能する絶縁体は、その下方の凹凸形状を被覆する平坦化膜として機能してもよい。例えば、絶縁体３２２の上面は、平坦性を高めるためにＣＭＰ法等を用いた平坦化処理により平坦化されていてもよい。 Furthermore, the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape underneath. For example, the upper surface of the insulator 322 may be flattened by a flattening process using a CMP method or the like to improve flatness.
　絶縁体３２６及び導電体３３０上に、配線層を設けてもよい。例えば、図４４において、絶縁体３５０、絶縁体３５２、及び絶縁体３５４が順に積層して設けられている。また、絶縁体３５０、絶縁体３５２、及び絶縁体３５４には、導電体３５６が形成されている。導電体３５６は、プラグ、または配線として機能する。 A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 44, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.
　層間膜として機能する、絶縁体３５２、及び絶縁体３５４等は、前述の、記憶装置に用いることができる絶縁体を用いることができる。 As the insulator 352, insulator 354, etc. that function as interlayer films, the above-mentioned insulators that can be used in memory devices can be used.
　プラグ、または配線として機能する導電体、例えば、導電体３２８、導電体３３０、及び導電体３５６等としては、先の［導電体］に記載した導電体を用いることができる。耐熱性と導電性を両立するタングステン、モリブデンなどの高融点材料を用いることが好ましく、タングステンを用いることが好ましい。または、アルミニウム、銅などの低抵抗導電性材料で形成することが好ましい。低抵抗導電性材料を用いることで配線抵抗を低くすることができる。 As the conductor that functions as a plug or wiring, for example, the conductor 328, the conductor 330, the conductor 356, etc., the conductors described in the above [Conductor] can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
　トランジスタ２００が有する導電体２４０は、導電体６４３、導電体６４２、導電体６４４、導電体６４５、導電体６４６、導電体３５６、導電体３３０、及び、導電体３２８を介して、トランジスタ３００のソース領域またはドレイン領域として機能する低抵抗領域３１４ｂと、電気的に接続されている。 The conductor 240 of the transistor 200 connects to the source of the transistor 300 via a conductor 643, a conductor 642, a conductor 644, a conductor 645, a conductor 646, a conductor 356, a conductor 330, and a conductor 328. It is electrically connected to a low resistance region 314b that functions as a region or a drain region.
　導電体６４３は、絶縁体２８０に埋め込まれている。導電体６４２は、絶縁体１３０上に設けられ、絶縁体６４１に埋め込まれている。導電体６４２は、導電体１２０と同一の材料、及び、同一の工程で作製することができる。導電体６４４は、絶縁体１８０及び絶縁体１３０に埋め込まれている。導電体６４５は、絶縁体６４７に埋め込まれている。導電体６４５は、導電体１１０と同一の材料、及び、同一の工程で作製することができる。導電体６４６は、絶縁体６４８に埋め込まれている。絶縁体６４８によって、トランジスタ３００と、導電体１１０と、が電気的に絶縁されている。 The conductor 643 is embedded in the insulator 280. The conductor 642 is provided on the insulator 130 and embedded in the insulator 641. The conductor 642 can be manufactured using the same material and the same process as the conductor 120. The conductor 644 is embedded in the insulator 180 and the insulator 130. The conductor 645 is embedded in the insulator 647. The conductor 645 can be manufactured using the same material and the same process as the conductor 110. A conductor 646 is embedded in an insulator 648. The transistor 300 and the conductor 110 are electrically insulated by the insulator 648.
　本発明の一態様により、新規のトランジスタ、半導体装置、及び記憶装置を提供できる。または、微細化または高集積化が可能なトランジスタ、半導体装置、及び、記憶装置を提供できる。または、信頼性が良好なトランジスタ、半導体装置、及び、記憶装置を提供できる。または、オン電流が大きいトランジスタと、当該トランジスタを有する半導体装置、及び、記憶装置を提供できる。または、トランジスタ特性のばらつきが少ない半導体装置及び記憶装置を提供できる。または、電気特性が良好なトランジスタと、当該トランジスタを有する半導体装置及び記憶装置を提供できる。または、消費電力の低い半導体装置及び記憶装置を提供できる。または、周波数特性が良好な記憶装置を提供できる。または、動作速度が速い記憶装置を提供できる。 According to one embodiment of the present invention, a novel transistor, a semiconductor device, and a memory device can be provided. Alternatively, a transistor, a semiconductor device, and a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a highly reliable transistor, semiconductor device, and memory device can be provided. Alternatively, a transistor with a large on-state current, a semiconductor device including the transistor, and a memory device can be provided. Alternatively, a semiconductor device and a memory device with less variation in transistor characteristics can be provided. Alternatively, a transistor with good electrical characteristics, and a semiconductor device and a memory device including the transistor can be provided. Alternatively, a semiconductor device and a memory device with low power consumption can be provided. Alternatively, a storage device with good frequency characteristics can be provided. Alternatively, a storage device with high operating speed can be provided.
　本実施の形態は、他の実施の形態及び実施例と適宜組み合わせることができる。 This embodiment can be combined with other embodiments and examples as appropriate.
（実施の形態２）
　本実施の形態では、本発明の一態様の記憶装置について図４５乃至図４８を用いて説明する。本実施の形態では、センスアンプを含む駆動回路が設けられる層上に、メモリセルを有する層が積層して設けられた記憶装置の構成例について説明する。 (Embodiment 2)
In this embodiment, a storage device according to one embodiment of the present invention will be described with reference to FIGS. 45 to 48. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a drive circuit including a sense amplifier is provided will be described.
＜記憶装置の構成例３＞
　図４５に、本発明の一態様に係る記憶装置８０の構成例を示すブロック図を示す。図４５に示す記憶装置８０は、層２０と、積層された層７０と、を有する。 <Storage device configuration example 3>
FIG. 45 shows a block diagram illustrating a configuration example of a storage device 80 according to one aspect of the present invention. A storage device 80 shown in FIG. 45 includes a layer 20 and a stacked layer 70.
　層２０は、Ｓｉトランジスタを有する層である。積層された層７０では、素子層３０［１］乃至３０［ｍ］（ｍは２以上の整数である）が積層して設けられる。素子層３０［１］乃至３０［ｍ］は、ＯＳトランジスタを有する層である。ＯＳトランジスタを有する層が積層して設けられる層７０は、層２０上に積層して設けることができる。 The layer 20 is a layer having a Si transistor. In the stacked layer 70, element layers 30[1] to 30[m] (m is an integer of 2 or more) are stacked. The element layers 30[1] to 30[m] are layers including OS transistors. The layer 70 in which layers having OS transistors are stacked can be provided in a stack on the layer 20 .
　素子層３０［１］乃至３０［ｍ］が有するＯＳトランジスタ及び容量素子といった素子は、メモリセルを構成する。図４５では、素子層３０［１］乃至３０［ｍ］において、ｍ行ｎ列（ｎは２以上の整数である）のマトリクス状に配置された複数のメモリセル３２を有する例を示している。 Elements such as OS transistors and capacitive elements included in the element layers 30[1] to 30[m] constitute memory cells. FIG. 45 shows an example in which a plurality of memory cells 32 are arranged in a matrix of m rows and n columns (n is an integer of 2 or more) in the element layers 30[1] to 30[m]. .
　図４５では、１行１列目のメモリセル３２をメモリセル３２［１，１］と示し、ｍ行ｎ列目のメモリセル３２をメモリセル３２［ｍ，ｎ］と示している。また、本実施の形態などでは、任意の行を示す場合にｉ行と記す場合がある。また、任意の列を示す場合にｊ列と記す場合がある。よって、ｉは１以上ｍ以下の整数であり、ｊは１以上ｎ以下の整数である。また、本実施の形態などでは、ｉ行ｊ列目のメモリセル３２をメモリセル３２［ｉ，ｊ］と示している。なお、本実施の形態などにおいて、「ｉ＋α」（αは正または負の整数）と示す場合は、「ｉ＋α」は１を下回らず、ｍを超えない。同様に、「ｊ＋α」と示す場合は、「ｊ＋α」は１を下回らず、ｎを超えない。 In FIG. 45, the memory cell 32 in the first row and first column is shown as a memory cell 32[1,1], and the memory cell 32 in the mth row and nth column is shown as a memory cell 32[m,n]. Further, in this embodiment and the like, when indicating an arbitrary line, it may be written as i line. Furthermore, when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. Furthermore, in this embodiment and the like, the memory cell 32 in the i-th row and j-th column is referred to as a memory cell 32[i,j]. Note that in this embodiment and the like, when expressed as "i+α" (α is a positive or negative integer), "i+α" is not less than 1 and does not exceed m. Similarly, in the case of "j+α", "j+α" is not less than 1 and not more than n.
　また図４５では、一例として、行方向に延在するｍ本の配線ＷＬと、行方向に延在するｍ本の配線ＰＬと、列方向に延在するｎ本の配線ＢＬと、を図示している。本実施の形態などでは、１本目（１行目）に設けられた配線ＷＬを配線ＷＬ［１］と示し、ｍ本目（ｍ行目）に設けられた配線ＷＬを配線ＷＬ［ｍ］と示す。同様に、１本目（１行目）に設けられた配線ＰＬを配線ＰＬ［１］と示し、ｍ本目（ｍ行目）に設けられた配線ＰＬを配線ＰＬ［ｍ］と示す。同様に、１本目（１列目）に設けられた配線ＢＬを配線ＢＬ［１］と示し、ｎ本目（ｎ列目）に設けられた配線ＢＬを配線ＢＬ［ｎ］と示す。なお素子層３０［１］乃至３０［ｍ］の層数と、配線ＷＬ（及び配線ＰＬ）の本数は、同じでなくてもよい。 Further, in FIG. 45, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction are illustrated. ing. In this embodiment and the like, the wiring WL provided in the first (first row) is referred to as wiring WL[1], and the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m]. . Similarly, the first wiring PL (first row) is designated as wiring PL[1], and the mth wiring PL (mth row) is designated as wiring PL[m]. Similarly, the wiring BL provided in the first (first column) is referred to as wiring BL[1], and the wiring BL provided in the nth (nth column) is referred to as wiring BL[n]. Note that the number of element layers 30[1] to 30[m] and the number of wirings WL (and wirings PL) may not be the same.
　ｉ行目に設けられた複数のメモリセル３２は、ｉ行目の配線ＷＬ（配線ＷＬ［ｉ］）とｉ行目の配線ＰＬ（配線ＰＬ［ｉ］）に電気的に接続される。ｊ列目に設けられた複数のメモリセル３２は、ｊ列目の配線ＢＬ（配線ＢＬ［ｊ］）と電気的に接続される。 The plurality of memory cells 32 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]). The plurality of memory cells 32 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
　配線ＢＬは、データの書き込み及び読み出しを行うためのビット線として機能する。配線ＷＬは、スイッチとして機能するアクセストランジスタのオンまたはオフ（導通状態または非導通状態）を制御するためのワード線として機能する。配線ＰＬは、キャパシタに接続される定電位線としての機能を有する。なおバックゲート電位を伝える配線としては、配線ＣＬ（図示せず）を別途設けることができる。 The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling on or off (conductive state or non-conductive state) of an access transistor functioning as a switch. The wiring PL has a function as a constant potential line connected to the capacitor. Note that a wiring CL (not shown) can be provided separately as a wiring for transmitting the back gate potential.
　素子層３０［１］乃至３０［ｍ］がそれぞれ有するメモリセル３２は、配線ＢＬを介してセンスアンプ４６に接続される。配線ＢＬは、層２０が設けられる基板表面の水平方向及び垂直方向に配置することができる。素子層３０［１］乃至３０［ｍ］が有するメモリセル３２から延びて設けられる配線ＢＬを、基板表面の水平方向に配置される配線に加え、垂直方向に配置される配線で構成することで、素子層３０とセンスアンプ４６との間の配線の長さを短くできる。メモリセルとセンスアンプとの間の信号伝搬距離を短くでき、ビット線の抵抗及び寄生容量が大幅に削減されるため、消費電力及び信号遅延の低減が実現できる。そのため、記憶装置８０の消費電力及び信号遅延の低減が実現できる。またメモリセル３２が有するキャパシタの容量を小さくしても動作させることが可能となる。そのため、記憶装置８０の小型化が実現できる。 The memory cells 32 each of the element layers 30[1] to 30[m] have are connected to the sense amplifier 46 via the wiring BL. The wiring BL can be arranged horizontally and vertically on the surface of the substrate on which the layer 20 is provided. By configuring the wiring BL extending from the memory cells 32 of the element layers 30[1] to 30[m] by wiring arranged vertically in addition to the wiring arranged horizontally on the substrate surface. , the length of the wiring between the element layer 30 and the sense amplifier 46 can be shortened. Since the signal propagation distance between the memory cell and the sense amplifier can be shortened, and the bit line resistance and parasitic capacitance can be significantly reduced, power consumption and signal delay can be reduced. Therefore, the power consumption and signal delay of the storage device 80 can be reduced. Furthermore, it is possible to operate the memory cell 32 even if the capacitance of the capacitor is reduced. Therefore, the storage device 80 can be made smaller.
　層２０は、ＰＳＷ７１（パワースイッチ）、ＰＳＷ７２、及び周辺回路２２を有する。周辺回路２２は、駆動回路４０、コントロール回路７３（Ｃｏｎｔｒｏｌ　Ｃｉｒｃｕｉｔ）、及び電圧生成回路７４を有する。なお層２０が有する各回路は、Ｓｉトランジスタを有する回路である。 The layer 20 includes a PSW 71 (power switch), a PSW 72, and a peripheral circuit 22. The peripheral circuit 22 includes a drive circuit 40, a control circuit 73, and a voltage generation circuit 74. Note that each circuit included in the layer 20 is a circuit including a Si transistor.
　記憶装置８０において、各回路、各信号及び各電圧は、必要に応じて、適宜取捨することができる。あるいは、他の回路または他の信号を追加してもよい。信号ＢＷ、信号ＣＥ、信号ＧＷ、信号ＣＬＫ、信号ＷＡＫＥ、信号ＡＤＤＲ、信号ＷＤＡ、信号ＰＯＮ１、信号ＰＯＮ２は外部からの入力信号であり、信号ＲＤＡは外部への出力信号である。信号ＣＬＫはクロック信号である。 In the storage device 80, each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added. Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.
　また、信号ＢＷ、信号ＣＥ、及び信号ＧＷは制御信号である。信号ＣＥはチップイネーブル信号であり、信号ＧＷはグローバル書き込みイネーブル信号であり、信号ＢＷはバイト書き込みイネーブル信号である。信号ＡＤＤＲはアドレス信号である。信号ＷＤＡは書き込みデータであり、信号ＲＤＡは読み出しデータである。信号ＰＯＮ１、信号ＰＯＮ２は、パワーゲーティング制御用信号である。なお、信号ＰＯＮ１、信号ＰＯＮ２は、コントロール回路７３で生成してもよい。 Furthermore, the signal BW, the signal CE, and the signal GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 73.
　コントロール回路７３は、記憶装置８０の動作全般を制御する機能を有するロジック回路である。例えば、コントロール回路は、信号ＣＥ、信号ＧＷ及び信号ＢＷを論理演算して、記憶装置８０の動作モード（例えば、書き込み動作、読み出し動作）を決定する。または、コントロール回路７３は、この動作モードが実行されるように、駆動回路４０の制御信号を生成する。 The control circuit 73 is a logic circuit that has a function of controlling the overall operation of the storage device 80. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 80. Alternatively, the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.
　電圧生成回路７４は負電圧を生成する機能を有する。信号ＷＡＫＥは、信号ＣＬＫの電圧生成回路７４への入力を制御する機能を有する。例えば、信号ＷＡＫＥにＨレベルの信号が与えられると、信号ＣＬＫが電圧生成回路７４へ入力され、電圧生成回路７４は負電圧を生成する。 The voltage generation circuit 74 has a function of generating a negative voltage. Signal WAKE has a function of controlling input of signal CLK to voltage generation circuit 74. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 74, and the voltage generation circuit 74 generates a negative voltage.
　駆動回路４０は、メモリセル３２に対するデータの書き込み及び読み出しをするための回路である。駆動回路４０は、行デコーダ４２、列デコーダ４４、行ドライバ４３、列ドライバ４５、入力回路４７、出力回路４８に加え、前述したセンスアンプ４６を有する。 The drive circuit 40 is a circuit for writing and reading data to and from the memory cells 32. The drive circuit 40 includes the above-described sense amplifier 46 in addition to a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48.
　行デコーダ４２及び列デコーダ４４は、信号ＡＤＤＲをデコードする機能を有する。行デコーダ４２は、アクセスする行を指定するための回路であり、列デコーダ４４は、アクセスする列を指定するための回路である。行ドライバ４３は、行デコーダ４２が指定する配線ＷＬを選択する機能を有する。列ドライバ４５は、データをメモリセル３２に書き込む機能、メモリセル３２からデータを読み出す機能、読み出したデータを保持する機能等を有する。 The row decoder 42 and column decoder 44 have a function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has a function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has a function of writing data into the memory cell 32, a function of reading data from the memory cell 32, a function of holding the read data, and the like.
　入力回路４７は、信号ＷＤＡを保持する機能を有する。入力回路４７が保持するデータは、列ドライバ４５に出力される。入力回路４７の出力データが、メモリセル３２に書き込むデータ（Ｄｉｎ）である。列ドライバ４５がメモリセル３２から読み出したデータ（Ｄｏｕｔ）は、出力回路４８に出力される。出力回路４８は、Ｄｏｕｔを保持する機能を有する。また、出力回路４８は、Ｄｏｕｔを記憶装置８０の外部に出力する機能を有する。出力回路４８から出力されるデータが信号ＲＤＡである。 The input circuit 47 has a function of holding the signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written into the memory cell 32. The data (Dout) read from the memory cell 32 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 80. The data output from the output circuit 48 is the signal RDA.
　ＰＳＷ７１は周辺回路２２へのＶＤＤの供給を制御する機能を有する。ＰＳＷ７２は、行ドライバ４３へのＶＨＭの供給を制御する機能を有する。ここでは、記憶装置８０の高電源電圧がＶＤＤであり、低電源電圧はＧＮＤ（接地電位）である。また、ＶＨＭは、ワード線を高レベルにするために用いられる高電源電圧であり、ＶＤＤよりも高い。信号ＰＯＮ１によってＰＳＷ７１のオン・オフが制御され、信号ＰＯＮ２によってＰＳＷ７２のオン・オフが制御される。図４５では、周辺回路２２において、ＶＤＤが供給される電源ドメインの数を１としているが、複数にすることもできる。この場合、各電源ドメインに対してパワースイッチを設ければよい。 The PSW 71 has a function of controlling the supply of VDD to the peripheral circuit 22. The PSW 72 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 80 is VDD, and the low power supply voltage is GND (ground potential). Further, VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD. The signal PON1 controls on/off of the PSW 71, and the signal PON2 controls the on/off of the PSW 72. In FIG. 45, in the peripheral circuit 22, the number of power domains to which VDD is supplied is one, but it may be plural. In this case, a power switch may be provided for each power domain.
　素子層３０［１］乃至３０［ｍ］は、層２０上に重ねて設けることができる。図４６Ａに、層２０上に５層（ｍ＝５）の素子層３０［１］乃至３０［５］を重ねて設けられる様子を示す記憶装置８０の斜視図を示している。 The element layers 30[1] to 30[m] can be provided overlappingly on the layer 20. FIG. 46A shows a perspective view of the storage device 80 showing how five (m=5) element layers 30[1] to 30[5] are stacked on the layer 20.
　図４６Ａでは、１層目に設けられた素子層３０を素子層３０［１］と示し、２層目に設けられた素子層３０を素子層３０［２］と示し、５層目に設けられた素子層３０を素子層３０［５］と示している。また図４６Ａにおいて、Ｘ方向に延びて設けられる配線ＷＬ、及び配線ＰＬと、Ｙ方向及びＺ方向（駆動回路が設けられる基板表面に垂直な方向）に延びて設けられる配線ＢＬ及び配線ＢＬＢと、を図示している。配線ＢＬＢは、反転ビット線である。なお、図面を見やすくするため、素子層３０それぞれが有する配線ＷＬ及び配線ＰＬの記載を一部省略している。 In FIG. 46A, the element layer 30 provided in the first layer is shown as an element layer 30[1], the element layer 30 provided in the second layer is shown as an element layer 30[2], and the element layer 30 provided in the fifth layer is shown as an element layer 30[2]. The element layer 30 is shown as an element layer 30[5]. Further, in FIG. 46A, a wiring WL and a wiring PL provided extending in the X direction, a wiring BL and a wiring BLB provided extending in the Y direction and the Z direction (direction perpendicular to the surface of the substrate on which the drive circuit is provided), is illustrated. The wiring BLB is an inverted bit line. Note that, in order to make the drawing easier to read, some descriptions of the wiring WL and the wiring PL included in each of the element layers 30 are omitted.
　図４６Ｂに、図４６Ａで図示した配線ＢＬ及び配線ＢＬＢに接続されたセンスアンプ４６、及び配線ＢＬ及び配線ＢＬＢに接続された素子層３０［１］乃至３０［５］が有するメモリセル３２の構成例を説明する模式図を示す。なお、１つの配線ＢＬ及び配線ＢＬＢに複数のメモリセル（メモリセル３２）が電気的に接続される構成を「メモリストリング」ともいう。 FIG. 46B shows the structure of the sense amplifier 46 connected to the wiring BL and the wiring BLB illustrated in FIG. 46A, and the memory cell 32 included in the element layers 30[1] to 30[5] connected to the wiring BL and the wiring BLB. A schematic diagram illustrating an example is shown. Note that a configuration in which a plurality of memory cells (memory cells 32) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string."
　図４６Ｂでは、配線ＢＬＢに接続されるメモリセル３２の回路構成の一例を図示している。メモリセル３２は、トランジスタ３７及び容量素子３８を有する。トランジスタ３７、容量素子３８、及び各配線（ＢＬ、及びＷＬなど）についても、例えば配線ＢＬ［１］及び配線ＷＬ［１］を配線ＢＬ及び配線ＷＬなどのようにいう場合がある。メモリセル３２には、例えば、先の実施の形態で例示したメモリセル１５０を適用することができる。つまり、トランジスタ３７として、トランジスタ２００を用い、容量素子３８として、容量素子１００を用いることができる。また、センスアンプ４６が有するトランジスタとしては、トランジスタ３００（図４４参照）を用いることができる。 FIG. 46B illustrates an example of the circuit configuration of the memory cell 32 connected to the wiring BLB. The memory cell 32 includes a transistor 37 and a capacitor 38. Regarding the transistor 37, the capacitor 38, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL. For example, the memory cell 150 illustrated in the previous embodiment can be applied to the memory cell 32. That is, the transistor 200 can be used as the transistor 37, and the capacitor 100 can be used as the capacitor 38. Further, as the transistor included in the sense amplifier 46, a transistor 300 (see FIG. 44) can be used.
　メモリセル３２において、トランジスタ３７のソースまたはドレインの一方は配線ＢＬに接続される。トランジスタ３７のソースまたはドレインの他方は容量素子３８の一方の電極に接続される。容量素子３８の他方の電極は、配線ＰＬに接続される。トランジスタ３７のゲートは配線ＷＬに接続される。 In the memory cell 32, one of the source and drain of the transistor 37 is connected to the wiring BL. The other of the source and drain of the transistor 37 is connected to one electrode of the capacitive element 38. The other electrode of the capacitive element 38 is connected to the wiring PL. The gate of the transistor 37 is connected to the wiring WL.
　配線ＰＬは、容量素子３８の電位を保持するための定電位を与える配線である。複数の配線ＰＬ同士は、１つの配線として接続して設けることで配線数を削減することができる。 The wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitive element 38. The number of wires can be reduced by connecting the plurality of wires PL as one wire.
　本発明の一形態では、ＯＳトランジスタは積層して設けるとともに、ビット線として機能する配線を、層２０が設けられる基板表面の垂直方向に配置する。加えて、メモリセル３２が有するトランジスタ３７及び容量素子３８を、層２０が設けられる基板表面の垂直方向に並べて配置する。各素子及び各配線を基板表面の垂直方向に設けることで、素子層間の配線の長さを短くできるとともに、単位面積当たりに設けられる素子の密度を高めることができる。そのため、記憶容量及び消費電力の低減に優れた記憶装置とすることができる。 In one form of the present invention, the OS transistors are provided in a stacked manner, and a wiring functioning as a bit line is arranged in a direction perpendicular to the surface of the substrate on which the layer 20 is provided. In addition, the transistor 37 and the capacitive element 38 included in the memory cell 32 are arranged side by side in the direction perpendicular to the substrate surface on which the layer 20 is provided. By providing each element and each wiring in a direction perpendicular to the surface of the substrate, the length of wiring between element layers can be shortened, and the density of elements provided per unit area can be increased. Therefore, it is possible to provide a storage device with excellent reduction in storage capacity and power consumption.
［メモリセル３２、センスアンプ４６の構成例］
　図４７Ａ及び図４７Ｂには、上述したメモリセル３２に対応する回路図、及び当該回路図に対応する回路ブロックを説明する図を示す。図４７Ａ及び図４７Ｂに図示するように、メモリセル３２は図面等においてブロックとして表す場合がある。なお図４７Ａ及び図４７Ｂに図示する配線ＢＬは、配線ＢＬＢに置き換えた場合も同様に表すことができる。 [Configuration example of memory cell 32 and sense amplifier 46]
47A and 47B show a circuit diagram corresponding to the above-described memory cell 32 and a diagram illustrating a circuit block corresponding to the circuit diagram. As illustrated in FIGS. 47A and 47B, the memory cells 32 may be represented as blocks in drawings and the like. Note that the wiring BL illustrated in FIGS. 47A and 47B can be similarly represented even when replaced with the wiring BLB.
　また、図４７Ｃ及び図４７Ｄには、上述したセンスアンプ４６に対応する回路図、及び当該回路図に対応する回路ブロックを説明する図を示す。センスアンプ４６は、スイッチ回路８２、プリチャージ回路８３、プリチャージ回路８４、増幅回路８５を図示している。また、配線ＢＬ、配線ＢＬＢの他、読み出される信号を出力する配線ＳＡ＿ＯＵＴ、配線ＳＡ＿ＯＵＴＢを図示している。 Further, FIGS. 47C and 47D show a circuit diagram corresponding to the above-described sense amplifier 46 and a diagram illustrating a circuit block corresponding to the circuit diagram. The sense amplifier 46 includes a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85. In addition to the wiring BL and the wiring BLB, a wiring SA_OUT and a wiring SA_OUTB that output signals to be read are also illustrated.
　スイッチ回路８２は、図４７Ｃに図示するように、例えばｎチャネル型のトランジスタ８２＿１、８２＿２を有する。トランジスタ８２＿１、８２＿２は、信号ＣＳＥＬに応じて、配線ＳＡ＿ＯＵＴ、配線ＳＡ＿ＯＵＴＢの配線対と、配線ＢＬ、配線ＢＬＢの配線対と、の導通状態を切り替える。 As shown in FIG. 47C, the switch circuit 82 includes, for example, n-channel transistors 82_1 and 82_2. The transistors 82_1 and 82_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.
　プリチャージ回路８３は、図４７Ｃに図示するように、ｎチャネル型のトランジスタ８３＿１乃至８３＿３で構成される。プリチャージ回路８３は、信号ＥＱに応じて、配線ＢＬ及び配線ＢＬＢを電位ＶＤＤ／２に相当する中間電位ＶＰＲＥにプリチャージするための回路である。 The precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3, as shown in FIG. 47C. The precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD/2 in response to the signal EQ.
　プリチャージ回路８４は、図４７Ｃに図示するように、ｐチャネル型のトランジスタ８４＿１乃至８４＿３で構成される。プリチャージ回路８４は、信号ＥＱＢに応じて、配線ＢＬ及び配線ＢＬＢを電位ＶＤＤ／２に相当する中間電位ＶＰＲＥにプリチャージするための回路である。 The precharge circuit 84 is composed of p-channel transistors 84_1 to 84_3, as shown in FIG. 47C. The precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD/2 in response to the signal EQB.
　増幅回路８５は、図４７Ｃに図示するように、配線ＳＡＰまたは配線ＳＡＮに接続された、ｐチャネル型のトランジスタ８５＿１、８５＿２及びｎチャネル型のトランジスタ８５＿３、８５＿４で構成される。配線ＳＡＰまたは配線ＳＡＮは、ＶＤＤまたはＶＳＳを与える機能を有する配線である。トランジスタ８５＿１乃至８５＿４は、インバータループを構成するトランジスタである。 As shown in FIG. 47C, the amplifier circuit 85 includes p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4, which are connected to the wiring SAP or the wiring SAN. The wiring SAP or the wiring SAN is a wiring that has a function of providing VDD or VSS. Transistors 85_1 to 85_4 are transistors forming an inverter loop.
　また、図４７Ｄには図４７Ｃ等で説明したセンスアンプ４６に対応する回路ブロックを説明する図を示す。図４７Ｄに図示するように、センスアンプ４６は図面等においてブロックとして表す場合がある。 Further, FIG. 47D shows a diagram illustrating a circuit block corresponding to the sense amplifier 46 described in FIG. 47C and the like. As illustrated in FIG. 47D, the sense amplifier 46 may be represented as a block in drawings, etc.
　図４８は、図４５の記憶装置８０の回路図である。図４８では、図４７Ａ乃至図４７Ｄで説明した回路ブロックを用いて図示している。 FIG. 48 is a circuit diagram of the storage device 80 of FIG. 45. FIG. 48 is illustrated using the circuit blocks described in FIGS. 47A to 47D.
　図４８に図示するように素子層３０［ｍ］を含む層７０は、メモリセル３２を有する。図４８に図示するメモリセル３２は、一例として、対になる配線ＢＬ［１］及び配線ＢＬＢ［１］、または配線ＢＬ［２］及び配線ＢＬＢ［２］に接続される。配線ＢＬに接続されるメモリセル３２は、データの書き込みまたは読み出しがされるメモリセルである。 As shown in FIG. 48, the layer 70 including the element layer 30[m] has the memory cell 32. The memory cell 32 illustrated in FIG. 48 is connected to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2], as an example. The memory cell 32 connected to the wiring BL is a memory cell into which data is written or read.
　配線ＢＬ［１］及び配線ＢＬＢ［１］は、センスアンプ４６［１］に接続され、配線ＢＬ［２］及び配線ＢＬＢ［２］は、センスアンプ４６［２］に接続される。センスアンプ４６［１］及びセンスアンプ４６［２］は、図４７Ｃで説明した各種信号に応じてデータの読み出しを行うことができる。 The wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 46[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 46[2]. The sense amplifier 46[1] and the sense amplifier 46[2] can read data in response to the various signals described with reference to FIG. 47C.
　本実施の形態は、他の実施の形態及び実施例と適宜組み合わせることができる。 This embodiment can be combined with other embodiments and examples as appropriate.
（実施の形態３）
　本実施の形態では、本発明の一態様の半導体装置の応用例について図４９乃至図５２を用いて説明する。本発明の一態様の半導体装置は、例えば、電子部品、電子機器、大型計算機、宇宙用機器、及びデータセンター（Ｄａｔａ　Ｃｅｎｔｅｒ：ＤＣとも呼称する）に用いることができる。本発明の一態様の半導体装置を用いた、電子部品、電子機器、大型計算機、宇宙用機器、及びデータセンターは、低消費電力化といった高性能化に有効である。 (Embodiment 3)
In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 49 to 52. A semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic equipment, large computers, space equipment, and data centers (also referred to as DCs). Electronic components, electronic equipment, large computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving higher performance such as lower power consumption.
［電子部品］
　電子部品７００が実装された基板（実装基板７０４）の斜視図を、図４９Ａに示す。図４９Ａに示す電子部品７００は、モールド７１１内に半導体装置７１０を有している。図４９Ａは、電子部品７００の内部を示すために、一部の記載を省略している。電子部品７００は、モールド７１１の外側にランド７１２を有する。ランド７１２は電極パッド７１３と電気的に接続され、電極パッド７１３は半導体装置７１０とワイヤ７１４を介して電気的に接続されている。電子部品７００は、例えばプリント基板７０２に実装される。このような電子部品が複数組み合わされて、それぞれがプリント基板７０２上で電気的に接続されることで実装基板７０４が完成する。 [Electronic components]
A perspective view of a board (mounted board 704) on which electronic component 700 is mounted is shown in FIG. 49A. An electronic component 700 shown in FIG. 49A has a semiconductor device 710 within a mold 711. In FIG. 49A, some descriptions are omitted to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to semiconductor device 710 via wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. A mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
　また、半導体装置７１０は、駆動回路層７１５と、記憶層７１６と、を有する。なお、記憶層７１６は、複数のメモリセルアレイが積層された構成である。駆動回路層７１５と、記憶層７１６と、が積層された構成は、モノリシック積層の構成とすることができる。モノリシック積層の構成では、ＴＳＶ（Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）などの貫通電極技術、及び、Ｃｕ−Ｃｕ直接接合などの接合技術、を用いることなく、各層間を接続することができる。駆動回路層７１５と、記憶層７１６と、をモノリシックに積層することで、例えば、プロセッサ上にメモリが直接形成される、いわゆるオンチップメモリの構成とすることができる。オンチップメモリの構成とすることで、プロセッサと、メモリとのインターフェース部分の動作を高速にすることが可能となる。 Further, the semiconductor device 710 includes a drive circuit layer 715 and a memory layer 716. Note that the storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the drive circuit layer 715 and the memory layer 716 are stacked can be a monolithic stacked structure. In the monolithic laminated structure, each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the storage layer 716, it is possible to have a so-called on-chip memory structure in which memory is formed directly on the processor, for example. By using an on-chip memory configuration, it is possible to speed up the operation of the interface between the processor and the memory.
　また、オンチップメモリの構成とすることで、ＴＳＶなどの貫通電極を用いる技術と比較し、接続配線などのサイズを小さくできるため、接続ピン数を増加させることも可能となる。接続ピン数を増加させることで、並列動作が可能となるため、メモリのバンド幅（メモリバンド幅ともいう）を向上させることが可能となる。 Furthermore, by using an on-chip memory configuration, the size of connection wiring etc. can be made smaller compared to technology using through-hole electrodes such as TSV, so it is also possible to increase the number of connection pins. By increasing the number of connection pins, parallel operation becomes possible, thereby making it possible to improve the memory bandwidth (also referred to as memory bandwidth).
　また、記憶層７１６が有する、複数のメモリセルアレイを、ＯＳトランジスタを用いて形成し、当該複数のメモリセルアレイをモノリシックで積層することが好ましい。複数のメモリセルアレイをモノリシック積層の構成とすることで、メモリのバンド幅、及びメモリのアクセスレイテンシの一方または双方を向上させることができる。なお、バンド幅とは、単位時間あたりのデータ転送量であり、アクセスレイテンシとは、アクセスしてからデータのやり取りが始まるまでの時間である。なお、記憶層７１６にＳｉトランジスタを用いる構成の場合、ＯＳトランジスタと比較し、モノリシック積層の構成とすることが困難である。そのため、モノリシック積層の構成において、ＯＳトランジスタは、Ｓｉトランジスタよりも優れた構造であるといえる。 Furthermore, it is preferable that the plurality of memory cell arrays included in the storage layer 716 be formed using OS transistors, and the plurality of memory cell arrays be monolithically stacked. By forming a plurality of memory cell arrays into a monolithic stacked structure, one or both of memory bandwidth and memory access latency can be improved. Note that bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. Note that in the case of a structure in which a Si transistor is used for the memory layer 716, it is difficult to form a monolithic stacked structure compared to an OS transistor. Therefore, in a monolithic stacked structure, an OS transistor can be said to have a superior structure to a Si transistor.
　また、半導体装置７１０を、ダイと呼称してもよい。なお、本明細書等において、ダイとは、半導体チップの製造工程で、例えば円盤状の基板（ウエハともいう）などに回路パターンを形成し、さいの目状に切り分けて得られたチップ片を表す。なお、ダイに用いることのできる半導体材料として、例えば、シリコン（Ｓｉ）、炭化ケイ素（ＳｉＣ）、または窒化ガリウム（ＧａＮ）などが挙げられる。例えば、シリコン基板（シリコンウエハともいう）から得られたダイを、シリコンダイという場合がある。 Additionally, the semiconductor device 710 may be referred to as a die. Note that in this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also referred to as a wafer) and cutting it into dice in the semiconductor chip manufacturing process. Note that examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon die.
　次に、電子部品７３０の斜視図を図４９Ｂに示す。電子部品７３０は、ＳｉＰ（Ｓｙｓｔｅｍ　ｉｎ　Ｐａｃｋａｇｅ）またはＭＣＭ（Ｍｕｌｔｉ　Ｃｈｉｐ　Ｍｏｄｕｌｅ）の一例である。電子部品７３０は、パッケージ基板７３２（プリント基板）上にインターポーザ７３１が設けられ、インターポーザ７３１上に半導体装置７３５、及び複数の半導体装置７１０が設けられている。 Next, a perspective view of the electronic component 730 is shown in FIG. 49B. The electronic component 730 is an example of SiP (System in Package) or MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.
　電子部品７３０では、半導体装置７１０を広帯域メモリ（ＨＢＭ：Ｈｉｇｈ　Ｂａｎｄｗｉｄｔｈ　Ｍｅｍｏｒｙ）として用いる例を示している。また、半導体装置７３５は、ＣＰＵ、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、またはＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）等の集積回路に用いることができる。 In the electronic component 730, an example is shown in which the semiconductor device 710 is used as a high bandwidth memory (HBM). Further, the semiconductor device 735 can be used for an integrated circuit such as a CPU, a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).
　パッケージ基板７３２は、例えば、セラミックス基板、プラスチック基板、または、ガラスエポキシ基板を用いることができる。インターポーザ７３１は、例えば、シリコンインターポーザ、または樹脂インターポーザを用いることができる。 For the package substrate 732, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used, for example. As the interposer 731, for example, a silicon interposer or a resin interposer can be used.
　インターポーザ７３１は、複数の配線を有し、端子ピッチの異なる複数の集積回路を電気的に接続する機能を有する。複数の配線は、単層または多層で設けられる。また、インターポーザ７３１は、インターポーザ７３１上に設けられた集積回路をパッケージ基板７３２に設けられた電極と電気的に接続する機能を有する。これらのことから、インターポーザを「再配線基板」または「中間基板」と呼ぶ場合がある。また、インターポーザ７３１に貫通電極を設けて、当該貫通電極を用いて集積回路とパッケージ基板７３２を電気的に接続する場合もある。また、シリコンインターポーザでは、貫通電極として、ＴＳＶを用いることもできる。 The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. Further, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. For these reasons, interposers are sometimes called "rewiring boards" or "intermediate boards." Further, in some cases, a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode. Further, in the silicon interposer, TSV can also be used as the through electrode.
　ＨＢＭでは、広いメモリバンド幅を実現するために多くの配線を接続する必要がある。このため、ＨＢＭを実装するインターポーザには、微細かつ高密度の配線形成が求められる。よって、ＨＢＭを実装するインターポーザには、シリコンインターポーザを用いることが好ましい。 In HBM, it is necessary to connect many wires to achieve a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
　また、シリコンインターポーザを用いた、ＳｉＰ及びＭＣＭ等では、集積回路とインターポーザ間の膨張係数の違いによる信頼性の低下が生じにくい。また、シリコンインターポーザは表面の平坦性が高いため、シリコンインターポーザ上に設ける集積回路とシリコンインターポーザ間の接続不良が生じにくい。特に、インターポーザ上に複数の集積回路を横に並べて配置する２．５Ｄパッケージ（２．５次元実装）では、シリコンインターポーザを用いることが好ましい。 Furthermore, in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to the difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
　一方で、シリコンインターポーザ、及びＴＳＶなどを用いて端子ピッチの異なる複数の集積回路を電気的に接続する場合、当該端子ピッチの幅などのスペースが必要となる。そのため、電子部品７３０のサイズを小さくしようとした場合、上記の端子ピッチの幅が問題になり、広いメモリバンド幅を実現するために必要な多くの配線を設けることが、困難になる場合がある。そこで、前述したように、ＯＳトランジスタを用いたモノリシック積層の構成が好適である。ＴＳＶを用いて積層したメモリセルアレイと、モノリシック積層したメモリセルアレイと、を組み合わせた複合化構造としてもよい。 On the other hand, when electrically connecting a plurality of integrated circuits with different terminal pitches using a silicon interposer, TSV, etc., a space corresponding to the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 730, the above-mentioned terminal pitch width becomes a problem, and it may become difficult to provide the many wirings necessary to achieve a wide memory bandwidth. . Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. It may also be a composite structure in which a memory cell array stacked using TSVs and a memory cell array stacked monolithically are combined.
　また、電子部品７３０と重ねてヒートシンク（放熱板）を設けてもよい。ヒートシンクを設ける場合は、インターポーザ７３１上に設ける集積回路の高さを揃えることが好ましい。例えば、本実施の形態に示す電子部品７３０では、半導体装置７１０と半導体装置７３５の高さを揃えることが好ましい。 Additionally, a heat sink (heat sink) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same. For example, in the electronic component 730 shown in this embodiment, it is preferable that the heights of the semiconductor device 710 and the semiconductor device 735 are the same.
　電子部品７３０を他の基板に実装するため、パッケージ基板７３２の底部に電極７３３を設けてもよい。図４９Ｂでは、電極７３３を半田ボールで形成する例を示している。パッケージ基板７３２の底部に半田ボールをマトリクス状に設けることで、ＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）実装を実現できる。また、電極７３３を導電性のピンで形成してもよい。パッケージ基板７３２の底部に導電性のピンをマトリクス状に設けることで、ＰＧＡ（Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）実装を実現できる。 In order to mount the electronic component 730 on another board, an electrode 733 may be provided on the bottom of the package board 732. FIG. 49B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
　電子部品７３０は、ＢＧＡ及びＰＧＡに限らず様々な実装方法を用いて他の基板に実装することができる。実装方法としては、例えば、ＳＰＧＡ（Ｓｔａｇｇｅｒｅｄ　Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）、ＬＧＡ（Ｌａｎｄ　Ｇｒｉｄ　Ａｒｒａｙ）、ＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）、ＱＦＪ（Ｑｕａｄ　Ｆｌａｔ　Ｊ−ｌｅａｄｅｄ　ｐａｃｋａｇｅ）、及び、ＱＦＮ（Ｑｕａｄ　Ｆｌａｔ　Ｎｏｎ−ｌｅａｄｅｄ　ｐａｃｋａｇｅ）が挙げられる。 The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of implementation methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), and QFJ (Quad Flat J-lead). package), and QFN (Quad Flat Non-leaded package) can be mentioned.
［電子機器］
　次に、電子機器６５００の斜視図を図５０Ａに示す。図５０Ａに示す電子機器６５００は、スマートフォンとして用いることのできる携帯情報端末機である。電子機器６５００は、筐体６５０１、表示部６５０２、電源ボタン６５０３、ボタン６５０４、スピーカ６５０５、マイク６５０６、カメラ６５０７、光源６５０８、及び制御装置６５０９などを有する。なお、制御装置６５０９としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を有する。本発明の一態様の半導体装置は、表示部６５０２、制御装置６５０９などに適用することができる。 [Electronics]
Next, a perspective view of electronic device 6500 is shown in FIG. 50A. Electronic device 6500 shown in FIG. 50A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
　図５０Ｂに示す電子機器６６００は、ノート型パーソナルコンピュータとして用いることのできる情報端末機である。電子機器６６００は、筐体６６１１、キーボード６６１２、ポインティングデバイス６６１３、外部接続ポート６６１４、表示部６６１５、制御装置６６１６などを有する。なお、制御装置６６１６としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を有する。本発明の一態様の半導体装置は、表示部６６１５、制御装置６６１６などに適用することができる。なお、本発明の一態様の半導体装置を、前述の制御装置６５０９、及び制御装置６６１６に用いることで、消費電力を低減させることができるため好適である。 An electronic device 6600 shown in FIG. 50B is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that it is preferable to use the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 because power consumption can be reduced.
［大型計算機］
　次に、大型計算機５６００の斜視図を図５０Ｃに示す。図５０Ｃに示す大型計算機５６００には、ラック５６１０にラックマウント型の計算機５６２０が複数格納されている。なお、大型計算機５６００を、スーパーコンピュータと呼称してもよい。 [Large computer]
Next, a perspective view of large computer 5600 is shown in FIG. 50C. In the large computer 5600 shown in FIG. 50C, a plurality of rack-mount computers 5620 are stored in a rack 5610. Note that the large computer 5600 may be called a supercomputer.
　計算機５６２０は、例えば、図５０Ｄに示す斜視図の構成とすることができる。図５０Ｄにおいて、計算機５６２０は、マザーボード５６３０を有し、マザーボード５６３０は、複数のスロット５６３１、複数の接続端子を有する。スロット５６３１には、ＰＣカード５６２１が挿入されている。加えて、ＰＣカード５６２１は、接続端子５６２３、接続端子５６２４、接続端子５６２５を有し、それぞれ、マザーボード５６３０に接続されている。 For example, the computer 5620 can have the configuration shown in the perspective view shown in FIG. 50D. In FIG. 50D, a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
　図５０Ｅに示すＰＣカード５６２１は、ＣＰＵ、ＧＰＵ、記憶装置などを備えた処理ボードの一例である。ＰＣカード５６２１は、ボード５６２２を有する。また、ボード５６２２は、接続端子５６２３と、接続端子５６２４と、接続端子５６２５と、半導体装置５６２６と、半導体装置５６２７と、半導体装置５６２８と、接続端子５６２９と、を有する。なお、図５０Ｅには、半導体装置５６２６、半導体装置５６２７、及び半導体装置５６２８以外の半導体装置を図示しているが、それらの半導体装置については、以下に記載する半導体装置５６２６、半導体装置５６２７、及び半導体装置５６２８の説明を参照できる。 A PC card 5621 shown in FIG. 50E is an example of a processing board that includes a CPU, a GPU, a storage device, and the like. PC card 5621 has a board 5622. Further, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although FIG. 50E illustrates semiconductor devices other than the semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, these semiconductor devices are described below. The description of the semiconductor device 5628 can be referred to.
　接続端子５６２９は、マザーボード５６３０のスロット５６３１に挿入することができる形状を有しており、接続端子５６２９は、ＰＣカード５６２１とマザーボード５６３０とを接続するためのインターフェースとして機能する。接続端子５６２９の規格としては、例えば、ＰＣＩｅなどが挙げられる。 The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe.
　接続端子５６２３、接続端子５６２４、接続端子５６２５は、例えば、ＰＣカード５６２１に対して電力供給、信号入力などを行うためのインターフェースとすることができる。また、例えば、ＰＣカード５６２１によって計算された信号の出力などを行うためのインターフェースとすることができる。接続端子５６２３、接続端子５６２４、接続端子５６２５のそれぞれの規格としては、例えば、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＳＡＴＡ（Ｓｅｒｉａｌ　ＡＴＡ）、ＳＣＳＩ（Ｓｍａｌｌ　Ｃｏｍｐｕｔｅｒ　Ｓｙｓｔｅｍ　Ｉｎｔｅｒｆａｃｅ）などが挙げられる。また、接続端子５６２３、接続端子５６２４、接続端子５６２５から映像信号を出力する場合、それぞれの規格としては、ＨＤＭＩ（登録商標）などが挙げられる。 The connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621. The respective standards of the connection terminal 5623, connection terminal 5624, and connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Can be mentioned. Furthermore, when outputting video signals from the connection terminals 5623, 5624, and 5625, the respective standards include HDMI (registered trademark).
　半導体装置５６２６は、信号の入出力を行う端子（図示しない）を有しており、当該端子をボード５６２２が備えるソケット（図示しない）に対して差し込むことで、半導体装置５６２６とボード５６２２を電気的に接続することができる。 The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 are electrically connected. can be connected to.
　半導体装置５６２７は、複数の端子を有しており、当該端子をボード５６２２が備える配線に対して、例えば、リフロー方式のはんだ付けを行うことで、半導体装置５６２７とボード５６２２を電気的に接続することができる。半導体装置５６２７としては、例えば、ＦＰＧＡ、ＧＰＵ、ＣＰＵなどが挙げられる。半導体装置５６２７として、例えば、電子部品７３０を用いることができる。 The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, an electronic component 730 can be used as the semiconductor device 5627.
　半導体装置５６２８は、複数の端子を有しており、当該端子をボード５６２２が備える配線に対して、例えば、リフロー方式のはんだ付けを行うことで、半導体装置５６２８とボード５６２２を電気的に接続することができる。半導体装置５６２８としては、例えば、記憶装置などが挙げられる。半導体装置５６２８として、例えば、電子部品７００を用いることができる。 The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to. Examples of the semiconductor device 5628 include a storage device. For example, the electronic component 700 can be used as the semiconductor device 5628.
　大型計算機５６００は並列計算機としても機能できる。大型計算機５６００を並列計算機として用いることで、例えば、人工知能の学習、及び推論に必要な大規模の計算を行うことができる。 The large computer 5600 can also function as a parallel computer. By using the large-scale computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence learning and inference.
［宇宙用機器］
　本発明の一態様の半導体装置は、宇宙用機器に好適に用いることができる。 [Space equipment]
A semiconductor device of one embodiment of the present invention can be suitably used for space equipment.
　本発明の一態様の半導体装置は、ＯＳトランジスタを含む。ＯＳトランジスタは、放射線照射による電気特性の変動が小さい。つまり放射線に対する耐性が高いため、放射線が入射しうる環境において好適に用いることができる。例えば、ＯＳトランジスタは、宇宙空間にて使用する場合に好適に用いることができる。具体的には、ＯＳトランジスタを、スペースシャトル、人工衛星、または、宇宙探査機に設けられる半導体装置を構成するトランジスタに用いることができる。放射線として、例えば、Ｘ線、及び中性子線が挙げられる。なお、宇宙空間とは、例えば、高度１００ｋｍ以上を指すが、本明細書に記載の宇宙空間は、熱圏、中間圏、及び成層圏のうち一つまたは複数を含んでもよい。 A semiconductor device of one embodiment of the present invention includes an OS transistor. OS transistors have small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used when used in outer space. Specifically, the OS transistor can be used as a transistor configuring a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of the radiation include X-rays and neutron beams. Note that outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.
　図５１には、宇宙用機器の一例として、人工衛星６８００を示している。人工衛星６８００は、機体６８０１と、ソーラーパネル６８０２と、アンテナ６８０３と、二次電池６８０５と、制御装置６８０７と、を有する。なお、図５１においては、宇宙空間に惑星６８０４を例示している。 FIG. 51 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that in FIG. 51, a planet 6804 is illustrated in outer space.
　また、図５１には、図示していないが、二次電池６８０５に、バッテリマネジメントシステム（ＢＭＳともいう）、またはバッテリ制御回路を設けてもよい。前述のバッテリマネジメントシステム、またはバッテリ制御回路に、ＯＳトランジスタを用いると、消費電力が低く、且つ宇宙空間においても高い信頼性を有するため好適である。 Although not shown in FIG. 51, the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit. It is preferable to use an OS transistor in the battery management system or the battery control circuit described above because it has low power consumption and high reliability even in outer space.
　また、宇宙空間は、地上に比べて１００倍以上、放射線量の高い環境である。なお、放射線として、例えば、Ｘ線、及びガンマ線に代表される電磁波（電磁放射線）、並びにアルファ線、ベータ線、中性子線、陽子線、重イオン線、中間子線などに代表される粒子放射線が挙げられる。 Additionally, outer space is an environment with more than 100 times higher radiation levels than on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
　ソーラーパネル６８０２に太陽光が照射されることにより、人工衛星６８００が動作するために必要な電力が生成される。しかしながら、例えばソーラーパネルに太陽光が照射されない状況、またはソーラーパネルに照射される太陽光の光量が少ない状況では、生成される電力が少なくなる。よって、人工衛星６８００が動作するために必要な電力が生成されない可能性がある。生成される電力が少ない状況下であっても人工衛星６８００を動作させるために、人工衛星６８００に二次電池６８０５を設けるとよい。なお、ソーラーパネルは、太陽電池モジュールと呼ばれる場合がある。 By irradiating the solar panel 6802 with sunlight, the electric power necessary for the operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or in a situation where the amount of sunlight irradiated onto the solar panel is small, less electric power is generated. Therefore, the power necessary for satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even in a situation where generated power is small, it is preferable to provide the artificial satellite 6800 with a secondary battery 6805. Note that the solar panel is sometimes called a solar cell module.
　人工衛星６８００は、信号を生成することができる。当該信号は、アンテナ６８０３を介して送信され、例えば地上に設けられた受信機、または他の人工衛星が当該信号を受信することができる。人工衛星６８００が送信した信号を受信することにより、当該信号を受信した受信機の位置を測定することができる。以上より、人工衛星６８００は、衛星測位システムを構成することができる。 The satellite 6800 can generate signals. The signal is transmitted via antenna 6803 and can be received by a ground-based receiver or other satellite, for example. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.
　また、制御装置６８０７は、人工衛星６８００を制御する機能を有する。制御装置６８０７としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を用いて構成される。なお、制御装置６８０７には、本発明の一態様であるＯＳトランジスタを含む半導体装置を用いると好適である。ＯＳトランジスタは、Ｓｉトランジスタと比較し、放射線照射による電気特性の変動が小さい。つまり放射線が入射しうる環境においても信頼性が高く、好適に用いることができる。 Furthermore, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
　また、人工衛星６８００は、センサを有する構成とすることができる。例えば、可視光センサを有する構成とすることにより、人工衛星６８００は、地上に設けられている物体に当たって反射された太陽光を検出する機能を有することができる。または、熱赤外センサを有する構成とすることにより、人工衛星６８００は、地表から放出される熱赤外線を検出する機能を有することができる。以上より、人工衛星６８００は、例えば地球観測衛星としての機能を有することができる。 Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by having a configuration including a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground. Alternatively, by having a configuration including a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
　なお、本実施の形態においては、宇宙用機器の一例として、人工衛星について例示したがこれに限定されない。例えば、本発明の一態様の半導体装置は、宇宙船、宇宙カプセル、宇宙探査機などの宇宙用機器に好適に用いることができる。 Note that in this embodiment, an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this. For example, the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
　以上の説明の通り、ＯＳトランジスタは、Ｓｉトランジスタと比較し、広いメモリバンド幅の実現が可能なこと、放射線耐性が高いこと、といった優れた効果を有する。 As explained above, OS transistors have superior effects compared to Si transistors, such as being able to realize a wide memory bandwidth and having high radiation resistance.
［データセンター］
　本発明の一態様の半導体装置は、例えば、データセンターなどに適用されるストレージシステムに好適に用いることができる。データセンターは、データの不変性を保障するなど、データの長期的な管理を行うことが求められる。長期的なデータを管理する場合、膨大なデータを記憶するためのストレージ及びサーバの設置、データを保持するための安定した電源の確保、あるいはデータの保持に要する冷却設備の確保、など建屋の大型化が必要となる。 [Data center]
A semiconductor device according to one embodiment of the present invention can be suitably used in, for example, a storage system applied to a data center or the like. Data centers are required to perform long-term data management, including ensuring data immutability. When managing long-term data, it is necessary to install storage and servers to store huge amounts of data, secure a stable power supply to retain data, or secure cooling equipment required to retain data, etc. due to the large size of the building. ization is required.
　データセンターに適用されるストレージシステムに本発明の一態様の半導体装置を用いることにより、データの保持に要する電力の低減、データを保持する半導体装置の小型化を図ることができる。そのため、ストレージシステムの小型化、データを保持するための電源の小型化、冷却設備の小規模化、などを図ることができる。そのため、データセンターの省スペース化を図ることができる。 By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, the power required to hold data can be reduced and the semiconductor device that holds data can be made smaller. Therefore, it is possible to downsize the storage system, downsize the power supply for holding data, downsize the cooling equipment, and so on. Therefore, it is possible to save space in the data center.
　また、本発明の一態様の半導体装置は、消費電力が少ないため、回路からの発熱を低減することができる。よって、当該発熱によるその回路自体、周辺回路、及びモジュールへの悪影響を低減できる。また、本発明の一態様の半導体装置を用いることにより、高温環境下においても動作が安定したデータセンターを実現できる。よってデータセンターの信頼性を高めることができる。 Furthermore, since the semiconductor device of one embodiment of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
　図５２にデータセンターに適用可能なストレージシステムを示す。図５２に示すストレージシステム７０００は、ホスト７００１（Ｈｏｓｔ　Ｃｏｍｐｕｔｅｒと図示）として複数のサーバ７００１ｓｂを有する。また、ストレージ７００３（Ｓｔｏｒａｇｅと図示）として複数の記憶装置７００３ｍｄを有する。ホスト７００１とストレージ７００３とは、ストレージエリアネットワーク７００４（ＳＡＮ：Ｓｔｏｒａｇｅ　Ａｒｅａ　Ｎｅｔｗｏｒｋと図示）及びストレージ制御回路７００２（Ｓｔｏｒａｇｅ　Ｃｏｎｔｒｏｌｌｅｒと図示）を介して接続されている形態を図示している。 Figure 52 shows a storage system applicable to data centers. The storage system 7000 shown in FIG. 52 has a plurality of servers 7001sb as hosts 7001 (shown as Host Computer). It also includes a plurality of storage devices 7003md as storage 7003 (shown as Storage). A host 7001 and a storage 7003 are shown connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (Storage Controller).
　ホスト７００１は、ストレージ７００３に記憶されたデータにアクセスするコンピュータに相当する。ホスト７００１同士は、ネットワークで互いに接続されていてもよい。 The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.
　ストレージ７００３は、フラッシュメモリを用いることで、データのアクセススピード、つまりデータの記憶及び出力に要する時間を短くしているものの、当該時間は、ストレージ内のキャッシュメモリとして用いることのできるＤＲＡＭが要する時間に比べて格段に長い。ストレージシステムでは、ストレージ７００３のアクセススピードの長さの問題を解決するために、通常ストレージ内にキャッシュメモリを設けてデータの記憶及び出力に要する時間を短くしている。 Although the storage 7003 uses flash memory to shorten the data access speed, that is, the time required to store and output data, this time is the same as the time required by DRAM, which can be used as a cache memory in the storage. It is much longer than . In a storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is usually provided in the storage to shorten the time required to store and output data.
　前述のキャッシュメモリは、ストレージ制御回路７００２及びストレージ７００３内に用いられる。ホスト７００１とストレージ７００３との間でやり取りされるデータは、ストレージ制御回路７００２及びストレージ７００３内の当該キャッシュメモリに記憶されたのち、ホスト７００１またはストレージ７００３に出力される。 The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the storage control circuit 7002 and the cache memory in the storage 7003, and then output to the host 7001 or the storage 7003.
　前述のキャッシュメモリのデータを記憶するためのトランジスタとして、ＯＳトランジスタを用いてデータに応じた電位を保持する構成とすることで、リフレッシュする頻度を減らし、消費電力を小さくすることができる。またメモリセルアレイを積層する構成とすることで小型化が可能である。 By using an OS transistor as a transistor for storing data in the cache memory described above and maintaining a potential according to the data, the frequency of refreshing can be reduced and power consumption can be reduced. Further, size reduction is possible by using a structure in which memory cell arrays are stacked.
　なお、本発明の一態様の半導体装置を、電子部品、電子機器、大型計算機、宇宙用機器、及びデータセンターの中から選ばれるいずれか一または複数に適用することで、消費電力を低減させる効果が期待される。そのため、半導体装置の高性能化、または高集積化に伴うエネルギー需要の増加が見込まれる中、本発明の一態様の半導体装置を用いることで、二酸化炭素（ＣＯ２）に代表される、温室効果ガスの排出量を低減させることも可能となる。また、本発明の一態様の半導体装置は、低消費電力であるため地球温暖化対策としても有効である。 Note that by applying the semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, power consumption can be reduced. There is expected. Therefore, as energy demand is expected to increase due to higher performance or higher integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention will reduce the greenhouse effect typified by carbon dioxide (CO 2 ). It also becomes possible to reduce the amount of gas discharged. Further, since the semiconductor device of one embodiment of the present invention has low power consumption, it is effective as a countermeasure against global warming.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be combined with other embodiments as appropriate.
ＢＬ：配線、ＰＬ：配線、Ｔｒ：トランジスタ、ＷＬ：配線、２０：層、２２：周辺回路、３０：素子層、３２：メモリセル、３７：トランジスタ、３８：容量素子、４０：駆動回路、４２：行デコーダ、４３：行ドライバ、４４：列デコーダ、４５：列ドライバ、４６［１］：センスアンプ、４６［２］：センスアンプ、４６：センスアンプ、４７：入力回路、４８：出力回路、７０：層、７１：ＰＳＷ、７２：ＰＳＷ、７３：コントロール回路、７４：電圧生成回路、８０：記憶装置、８２＿１：トランジスタ、８２＿２：トランジスタ、８２：スイッチ回路、８３＿１：トランジスタ、８３＿３：トランジスタ、８３：プリチャージ回路、８４＿１：トランジスタ、８４＿３：トランジスタ、８４：プリチャージ回路、８５＿１：トランジスタ、８５＿２：トランジスタ、８５＿３：トランジスタ、８５＿４：トランジスタ、８５：増幅回路、１００ａ：容量素子、１００ｂ：容量素子、１００ｃ：容量素子、１００ｄ：容量素子、１００ｐ：容量素子、１００ｑ：容量素子、１００ｒ：容量素子、１００ｓ：容量素子、１００：容量素子、１１０：導電体、１１５：導電体、１２０Ａ：導電膜、１２０：導電体、１２１Ａ：導電膜、１２１：導電体、１２２：導電体、１２５：導電体、１３０：絶縁体、１３５：絶縁体、１４０：絶縁体、１５０ａ：メモリセル、１５０ｂ：メモリセル、１５０ｃ：メモリセル、１５０ｄ：メモリセル、１５０：メモリセル、１６０［１，１］：メモリユニット、１６０［１，２］：メモリユニット、１６０［１，３］：メモリユニット、１６０［１，４］：メモリユニット、１６０［２，１］：メモリユニット、１６０［２，２］：メモリユニット、１６０［２，３］：メモリユニット、１６０［２，４］：メモリユニット、１６０：メモリユニット、１７０［１］：層、１７０［２］：層、１７０［ｍ−１］：層、１７０［ｍ］：層、１８０ａ：絶縁体、１８０ｂ：絶縁体、１８０：絶縁体、１８２：絶縁体、１８５：絶縁体、１９０ｐ：開口部、１９０ｑ：開口部、１９０ｒ：開口部、１９０ｓ：開口部、１９０：開口部、２００ａ：トランジスタ、２００ｂ：トランジスタ、２００ｃ：トランジスタ、２００ｄ：トランジスタ、２００ｐ：トランジスタ、２００ｑ：トランジスタ、２００ｒ：トランジスタ、２００ｓ：トランジスタ、２００：トランジスタ、２３０ａ：酸化物半導体、２３０ｂ：酸化物半導体、２３０ｉ：領域、２３０ｎａ：領域、２３０ｎｂ：領域、２３０：酸化物半導体、２４０Ａ：導電膜、２４０：導電体、２４５：導電体、２４６：導電体、２５０ａ：絶縁体、２５０ｂ：絶縁体、２５０ｃ：絶縁体、２５０：絶縁体、２６０ａ：導電体、２６０Ａ：導電膜、２６０ｂ：導電体、２６０：導電体、２６５：導電体、２８０ａ：絶縁体、２８０ｂ：絶縁体、２８０ｃ：絶縁体、２８０：絶縁体、２８１：絶縁体、２８３：絶縁体、２８７：絶縁体、２８９：絶縁体、２９０ｐ：開口部、２９０ｑ：開口部、２９０ｒ：開口部、２９０ｓ：開口部、２９０：開口部、３００：トランジスタ、３１１：基板、３１３：半導体領域、３１４ａ：低抵抗領域、３１４ｂ：低抵抗領域、３１５：絶縁体、３１６：導電体、３２０：絶縁体、３２２：絶縁体、３２４：絶縁体、３２６：絶縁体、３２８：導電体、３３０：導電体、３５０：絶縁体、３５２：絶縁体、３５４：絶縁体、３５６：導電体、６４１：絶縁体、６４２：導電体、６４３：導電体、６４４：導電体、６４５：導電体、６４６：導電体、６４７：絶縁体、６４８：絶縁体、７００：電子部品、７０２：プリント基板、７０４：実装基板、７１０：半導体装置、７１１：モールド、７１２：ランド、７１３：電極パッド、７１４：ワイヤ、７１５：駆動回路層、７１６：記憶層、７３０：電子部品、７３１：インターポーザ、７３２：パッケージ基板、７３３：電極、７３５：半導体装置、５６００：大型計算機、５６１０：ラック、５６２０：計算機、５６２１：ＰＣカード、５６２２：ボード、５６２３：接続端子、５６２４：接続端子、５６２５：接続端子、５６２６：半導体装置、５６２７：半導体装置、５６２８：半導体装置、５６２９：接続端子、５６３０：マザーボード、５６３１：スロット、６５００：電子機器、６５０１：筐体、６５０２：表示部、６５０３：電源ボタン、６５０４：ボタン、６５０５：スピーカ、６５０６：マイク、６５０７：カメラ、６５０８：光源、６５０９：制御装置、６６００：電子機器、６６１１：筐体、６６１２：キーボード、６６１３：ポインティングデバイス、６６１４：外部接続ポート、６６１５：表示部、６６１６：制御装置、６８００：人工衛星、６８０１：機体、６８０２：ソーラーパネル、６８０３：アンテナ、６８０４：惑星、６８０５：二次電池、６８０７：制御装置、７０００：ストレージシステム、７００１ｓｂ：サーバ、７００１：ホスト、７００２：ストレージ制御回路、７００３ｍｄ：記憶装置、７００３：ストレージ、７００４：ストレージエリアネットワーク BL: wiring, PL: wiring, Tr: transistor, WL: wiring, 20: layer, 22: peripheral circuit, 30: element layer, 32: memory cell, 37: transistor, 38: capacitive element, 40: drive circuit, 42 : row decoder, 43: row driver, 44: column decoder, 45: column driver, 46 [1]: sense amplifier, 46 [2]: sense amplifier, 46: sense amplifier, 47: input circuit, 48: output circuit, 70: layer, 71: PSW, 72: PSW, 73: control circuit, 74: voltage generation circuit, 80: memory device, 82_1: transistor, 82_2: transistor, 82: switch circuit, 83_1: transistor, 83_3: transistor, 83 : precharge circuit, 84_1: transistor, 84_3: transistor, 84: precharge circuit, 85_1: transistor, 85_2: transistor, 85_3: transistor, 85_4: transistor, 85: amplifier circuit, 100a: capacitor, 100b: capacitor, 100c: capacitive element, 100d: capacitive element, 100p: capacitive element, 100q: capacitive element, 100r: capacitive element, 100s: capacitive element, 100: capacitive element, 110: conductor, 115: conductor, 120A: conductive film, 120: conductor, 121A: conductive film, 121: conductor, 122: conductor, 125: conductor, 130: insulator, 135: insulator, 140: insulator, 150a: memory cell, 150b: memory cell, 150c: memory cell, 150d: memory cell, 150: memory cell, 160[1,1]: memory unit, 160[1,2]: memory unit, 160[1,3]: memory unit, 160[1,4] ]: memory unit, 160[2,1]: memory unit, 160[2,2]: memory unit, 160[2,3]: memory unit, 160[2,4]: memory unit, 160: memory unit, 170 [1]: layer, 170 [2]: layer, 170 [m-1]: layer, 170 [m]: layer, 180a: insulator, 180b: insulator, 180: insulator, 182: insulator, 185: insulator, 190p: opening, 190q: opening, 190r: opening, 190s: opening, 190: opening, 200a: transistor, 200b: transistor, 200c: transistor, 200d: transistor, 200p: transistor, 200q: transistor, 200r: transistor, 200s: transistor, 200: transistor, 230a: oxide semiconductor, 230b: oxide semiconductor, 230i: region, 230na: region, 230nb: region, 230: oxide semiconductor, 240A: conductive film , 240: conductor, 245: conductor, 246: conductor, 250a: insulator, 250b: insulator, 250c: insulator, 250: insulator, 260a: conductor, 260A: conductive film, 260b: conductor , 260: conductor, 265: conductor, 280a: insulator, 280b: insulator, 280c: insulator, 280: insulator, 281: insulator, 283: insulator, 287: insulator, 289: insulator , 290p: opening, 290q: opening, 290r: opening, 290s: opening, 290: opening, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region , 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator , 354: insulator, 356: conductor, 641: insulator, 642: conductor, 643: conductor, 644: conductor, 645: conductor, 646: conductor, 647: insulator, 648: insulator , 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730 :Electronic component, 731: Interposer, 732: Package board, 733: Electrode, 735: Semiconductor device, 5600: Large computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624 : Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display part, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device , 6614: External connection port, 6615: Display unit, 6616: Control device, 6800: Satellite, 6801: Aircraft, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001sb: Server, 7001: Host, 7002: Storage control circuit, 7003md: Storage device, 7003: Storage, 7004: Storage area network

Claims (14)

  1. 　第１のメモリセルと、第２のメモリセルと、第１の絶縁体と、前記第１の絶縁体上の第２の絶縁体と、を有し、
    　前記第１のメモリセルは、第１の容量素子と、前記第１の容量素子上の第１のトランジスタと、を有し、
    　前記第２のメモリセルは、第２の容量素子と、前記第２の容量素子上の第２のトランジスタと、を有し、
    　前記第１の絶縁体は、第１の開口部と、第２の開口部と、を有し、
    　前記第１の開口部には、前記第１の容量素子の少なくとも一部が配置され、
    　前記第２の開口部には、前記第２の容量素子の少なくとも一部が配置され、
    　前記第２の絶縁体は、第３の開口部と、第４の開口部と、を有し、
    　前記第３の開口部には、前記第１のトランジスタの少なくとも一部が配置され、
    　前記第４の開口部には、前記第２のトランジスタの少なくとも一部が配置され、
    　前記第１の開口部は、前記第３の開口部と重なる領域を有し、
    　前記第２の開口部は、前記第４の開口部と重なる領域を有し、
    　前記第１の開口部と前記第２の開口部の中心間距離は、前記第３の開口部と前記第４の開口部の中心間距離と一致し、
    　前記第１の開口部と、前記第３の開口部とは、最大幅が互いに異なり、
    　前記第２の開口部と、前記第４の開口部とは、最大幅が互いに異なる、記憶装置。     comprising a first memory cell, a second memory cell, a first insulator, and a second insulator on the first insulator,
    The first memory cell includes a first capacitive element and a first transistor on the first capacitive element,
    The second memory cell includes a second capacitive element and a second transistor on the second capacitive element,
    The first insulator has a first opening and a second opening,
    At least a portion of the first capacitive element is arranged in the first opening,
    At least a portion of the second capacitive element is arranged in the second opening,
    The second insulator has a third opening and a fourth opening,
    At least a portion of the first transistor is disposed in the third opening,
    At least a portion of the second transistor is disposed in the fourth opening,
    The first opening has a region overlapping with the third opening,
    The second opening has a region that overlaps with the fourth opening,
    The distance between the centers of the first opening and the second opening matches the distance between the centers of the third opening and the fourth opening,
    The first opening and the third opening have different maximum widths,
    In the storage device, the second opening and the fourth opening have mutually different maximum widths.
  2. 　請求項１において、
    　前記第１の開口部の最大幅は、前記第３の開口部の最大幅よりも大きく、
    　前記第２の開口部の最大幅は、前記第４の開口部の最大幅よりも大きい、記憶装置。     In claim 1,
    The maximum width of the first opening is larger than the maximum width of the third opening,
    A maximum width of the second opening is larger than a maximum width of the fourth opening.
  3. 　請求項１において、
    　前記第１のトランジスタのチャネル長は、前記第１のトランジスタのチャネル幅よりも小さく、
    　前記第２のトランジスタのチャネル長は、前記第２のトランジスタのチャネル幅よりも小さい、記憶装置。     In claim 1,
    The channel length of the first transistor is smaller than the channel width of the first transistor,
    A memory device, wherein a channel length of the second transistor is smaller than a channel width of the second transistor.
  4. 　請求項１において、
    　前記第１のトランジスタ、及び前記第２のトランジスタのそれぞれは、半導体層に酸化物半導体を有し、
    　前記酸化物半導体は、Ｉｎ、Ｇａ、及びＺｎの中から選ばれるいずれか一または複数を有する、記憶装置。     In claim 1,
    Each of the first transistor and the second transistor includes an oxide semiconductor in a semiconductor layer,
    A storage device in which the oxide semiconductor includes one or more selected from In, Ga, and Zn.
  5. 　請求項１において、
    　前記第１の容量素子、及び前記第２の容量素子のそれぞれは、第１の導電体と、前記第１の導電体上の第３の絶縁体と、前記第３の絶縁体上の第２の導電体と、を有し、
    　前記第３の絶縁体は、第１の酸化ジルコニウムと、前記第１の酸化ジルコニウム上の酸化アルミニウムと、前記酸化アルミニウム上の第２の酸化ジルコニウムと、を有する、記憶装置。     In claim 1,
    Each of the first capacitive element and the second capacitive element includes a first conductor, a third insulator on the first conductor, and a second insulator on the third insulator. a conductor;
    The third insulator includes a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.
  6. 　請求項１乃至請求項５のいずれか一項において、
    　前記第１のメモリセルと、前記第２のメモリセルと、を含む層を複数有し、
    　複数の前記層は、積層されている、記憶装置。     In any one of claims 1 to 5,
    having a plurality of layers including the first memory cell and the second memory cell,
    A storage device in which the plurality of layers are stacked.
  7. 　第１の導電体と、前記第１の導電体上のメモリセルと、前記第１の導電体上の第１の絶縁体と、第２の絶縁体と、を有し、
    　前記メモリセルは、容量素子と、前記容量素子上のトランジスタと、を有し、
    　前記容量素子は、第２の導電体と、前記第２の導電体上の第３の絶縁体と、前記第３の絶縁体上の第３の導電体と、を有し、
    　前記第１の絶縁体には、前記第１の導電体に達する第１の開口部が設けられ、
    　前記第２の導電体の少なくとも一部、前記第３の絶縁体の少なくとも一部、及び、前記第３の導電体の少なくとも一部は、前記第１の開口部に配置され、
    　前記第２の導電体、前記第３の絶縁体、及び前記第３の導電体の上に、前記第２の絶縁体が配置され、
    　前記トランジスタは、前記第３の導電体と、前記第２の絶縁体上の第４の導電体と、酸化物半導体と、第４の絶縁体と、第５の導電体と、を有し、
    　前記第２の絶縁体及び前記第４の導電体には、前記第３の導電体に達する第２の開口部が設けられ、
    　前記酸化物半導体の少なくとも一部は、前記第２の開口部に配置され、
    　前記酸化物半導体は、前記第２の開口部において前記第３の導電体の上面に接する領域と、前記第２の開口部において前記第４の導電体の側面に接する領域と、前記第４の導電体の上面の少なくとも一部に接する領域と、を有し、
    　前記第４の絶縁体は、少なくとも一部が前記第２の開口部に位置するように、前記酸化物半導体上に配置され、
    　前記第５の導電体は、少なくとも一部が前記第２の開口部に位置するように、前記第４の絶縁体上に配置され、
    　前記第１の開口部と、前記第２の開口部とは、最大幅が互いに異なる、記憶装置。     a first conductor, a memory cell on the first conductor, a first insulator on the first conductor, and a second insulator,
    The memory cell includes a capacitive element and a transistor on the capacitive element,
    The capacitive element includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator,
    The first insulator is provided with a first opening that reaches the first conductor,
    At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening,
    The second insulator is arranged on the second conductor, the third insulator, and the third conductor,
    The transistor includes the third conductor, a fourth conductor on the second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor,
    The second insulator and the fourth conductor are provided with a second opening that reaches the third conductor,
    At least a portion of the oxide semiconductor is arranged in the second opening,
    The oxide semiconductor includes a region in contact with the top surface of the third conductor in the second opening, a region in contact with a side surface of the fourth conductor in the second opening, and a region in contact with the side surface of the fourth conductor in the second opening. a region in contact with at least a part of the upper surface of the conductor;
    the fourth insulator is disposed on the oxide semiconductor so that at least a portion thereof is located in the second opening;
    the fifth conductor is disposed on the fourth insulator such that at least a portion thereof is located in the second opening;
    In the storage device, the first opening and the second opening have mutually different maximum widths.
  8. 　請求項７において、
    　前記第１の開口部の最大幅は、前記第２の開口部の最大幅よりも大きい、記憶装置。     In claim 7,
    The storage device, wherein a maximum width of the first opening is larger than a maximum width of the second opening.
  9. 　請求項７において、
    　前記第２の開口部は、前記第１の開口部と重なる領域を有する、記憶装置。     In claim 7,
    The second opening has a region overlapping with the first opening.
  10. 　請求項７において、
    　前記トランジスタのチャネル長は、前記トランジスタのチャネル幅よりも小さい、記憶装置。     In claim 7,
    A memory device, wherein a channel length of the transistor is smaller than a channel width of the transistor.
  11. 　請求項７において、
    　前記第３の絶縁体は、第１の酸化ジルコニウムと、前記第１の酸化ジルコニウム上の酸化アルミニウムと、前記酸化アルミニウム上の第２の酸化ジルコニウムと、を有する、記憶装置。     In claim 7,
    The third insulator includes a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.
  12. 　請求項７において、
    　前記酸化物半導体は、Ｉｎ、Ｇａ、及びＺｎの中から選ばれるいずれか一または複数を有する、記憶装置。     In claim 7,
    A storage device in which the oxide semiconductor includes one or more selected from In, Ga, and Zn.
  13. 　請求項７乃至請求項１２のいずれか一項において、
    　前記第５の導電体は、第１の方向に延在して設けられ、
    　前記第４の導電体は、第２の方向に延在して設けられ、
    　前記第１の方向と、前記第２の方向とは、直交する、記憶装置。     In any one of claims 7 to 12,
    The fifth conductor is provided extending in the first direction,
    The fourth conductor is provided extending in the second direction,
    The first direction and the second direction are perpendicular to each other.
  14. 　請求項１３において、
    　前記メモリセルを含む層を複数有し、
    　複数の前記層は、積層されている、記憶装置。     In claim 13,
    having a plurality of layers including the memory cells;
    A storage device in which the plurality of layers are stacked.
PCT/IB2023/058969 2022-09-16 2023-09-11 Storage device WO2024057165A1 (en)

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JP2016149552A (en) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 Semiconductor device, and manufacturing method for the same
JP2020120116A (en) * 2019-01-25 2020-08-06 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device
JP2021114563A (en) * 2020-01-20 2021-08-05 キオクシア株式会社 Semiconductor storage device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149552A (en) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 Semiconductor device, and manufacturing method for the same
JP2020120116A (en) * 2019-01-25 2020-08-06 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device
JP2021114563A (en) * 2020-01-20 2021-08-05 キオクシア株式会社 Semiconductor storage device

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