WO2024078682A1 - Substrat d'accumulation pour bloc d'alimentation - Google Patents

Substrat d'accumulation pour bloc d'alimentation Download PDF

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Publication number
WO2024078682A1
WO2024078682A1 PCT/EP2022/078046 EP2022078046W WO2024078682A1 WO 2024078682 A1 WO2024078682 A1 WO 2024078682A1 EP 2022078046 W EP2022078046 W EP 2022078046W WO 2024078682 A1 WO2024078682 A1 WO 2024078682A1
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WIPO (PCT)
Prior art keywords
main surface
conductive pads
electrically conductive
substrate
build
Prior art date
Application number
PCT/EP2022/078046
Other languages
English (en)
Inventor
Lasse Petteri PALM
Gilberto Curatola
Original Assignee
Huawei Digital Power Technologies Co., Ltd.
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Filing date
Publication date
Application filed by Huawei Digital Power Technologies Co., Ltd. filed Critical Huawei Digital Power Technologies Co., Ltd.
Priority to PCT/EP2022/078046 priority Critical patent/WO2024078682A1/fr
Publication of WO2024078682A1 publication Critical patent/WO2024078682A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

Definitions

  • the disclosure relates to the field of advanced build up substrate and flip chip packaging technology for manufacturing power packages and assemblies.
  • the disclosure relates to a build-up substrate for a power package, a power package comprising such buildup substrate and methods for manufacturing such build-up substrates.
  • a build-up package for GaN with controlled isolation distance is disclosed.
  • GaN Gallium Nitride
  • PCB printed circuit board
  • FC flip chip
  • CSP chip scale packages
  • the FC on a laminate substrate can be used on multi-die packages e.g., as shown by US 10,074,597 B2, but the heat transfer from die to PCB and the current carrying capability is limited due to thin Cu routing and small size plated micro-vias and plated through-holes (PTH) that are used for connections through the laminate substrate.
  • PTH plated through-holes
  • This disclosure provides a solution for a high performance and low parasitic package that can be applied as single die GaN package as well as multi-die GaN package or for other lateral current flow or even vertical current flow power device package.
  • Embodiments presented in this disclosure offer similar electrical and thermal performance and are also footprint compatible with existing flip-chip on half-etched leadframe variants but have improved performance and reduced parasitic characteristics.
  • the embodiments provide an alternative and improved approach to manufacture low parasitic GaN (or for other lateral current flow power devices) package that has good thermal performance due to large cross sections routing lines and through vias between the top and bottom side of the package. Furthermore, they allow to properly address the multi-chip system in package integration, which is one of the most stringent limit of current leadframe-based approaches.
  • the package and manufacturing process described hereinafter may be based on using Flip Chip bonding on a build substrate and a simplified manufacturing process that allows to manufacture substrate with thick Cu routing and large cross section Cu vias through the package.
  • the embodiments presented in this disclosure allow production of complex, e.g., complicated multi-die packages such as half bridge with driver.
  • the embodiments presented in this disclosure are based on using build up substrates instead of leadframes. This provides the advantage that complicated routing can be performed on a substrate level. This allows to integrate several power dies and even driver die into the one package. Unlike in leadframes where all wiring (leads) are connected to the frame, e.g., no “floating” wires are allowed, the disclosed embodiments allow using such “floating wires” for connection between the dies. While in lead frame process, all leads are visible in the package edge, the disclosed embodiments allow using build up substrates where all side walls can be isolated to improve the creepage distance.
  • Another advantage of the disclosed solution is that the processing can be done in much larger panel sizes compared to leadframes. This allows panel level processing that lowers the manufacturing cost due to shorter process time in parallel processes and shorter process time per component in sequential processes due to shorter set up time, waiting time and start up time. Larger panel size also reduces the material waste because total handling area needed for processing of multiple small panels is larger than in case of one larger panel.
  • the additional integration of passive and other components is very simple.
  • the passives or other elements can be easily placed in ideal location of the package to guarantee the best possible electrical performance.
  • This disclosure presents a package, substrate and structure for manufacturing low parasitic single die or multi-die GaN package and methods to manufacture simplified build up substrate on which the GaN power die can be mounted by using flip chip technology.
  • the substrate can be manufactured by a buildup process using commercially available MIS (molded interconnection substrate), via bar technology or by a new and simplified build up substrate process as presented in more details hereinafter.
  • MIS molded interconnection substrate
  • the die back side can be exposed if needed to improve the thermal performance.
  • the disclosed embodiments can be used to manufacture both single and multi-die packages with or without integrated passives.
  • the examples presented with respect to the Figures below show structures in which the GaN die or dies have alternating source and gate pad structures. However, similar structures and ideas can also be used for other types of gate-source configurations.
  • the disclosed embodiments are primarily presented for packaging GaN dies they can also be used for other types of lateral current flow power dies or even vertical current flow dies, e.g., when using a Cu clip to realize the die back side connection.
  • Embodiments presented in this disclosure are: Single die GaN package; multi-die GaN package, e.g., half bridge with or without driver and/or passives; multi-die GaN package, e.g., paralleled dies with or without driver and/or passives; two simplified process flows to manufacture build up substrate.
  • the embodiments in this disclosure are not limited only to GaN dies or GaN design. It understands that also normal build up substrates can be used instead of simplified build up substrates described in the embodiments presented below.
  • chip embedding technologies are described.
  • the electronic components (chips, capacitors, resistors, etc.) are either placed inside an opening in a PCB core layer or soldered on a two or multilayer PCB board.
  • the actual embedding inside the final PCB board can be performed by laminating FR4 prepregs or other polymer sheets above and below the core layer that holds the components to be embedded.
  • the electrical connection between the embedded components and the PCB metal layers can be formed by soldering the component terminals to the inner laminate layers and subsequently laminating the PCB layers together.
  • the components can be electrically connected by galvanically filled micro vias which is more robust, since there is no remelting of solder inside the package or board, which has to be considered when mounting the other components to the outer layers of the PCB.
  • the micro vias are usually formed after lamination by laser drilling from the top surface through the thin laminate layer to the active chip pads or to the terminals of an embedded component package.
  • the disclosure relates to a build-up substrate for a power package, the build-up substrate comprising: an electrically insulating layer having a first main surface and an opposing second main surface; a plurality of electrically conductive pads encapsulated in the electrically insulating layer, the plurality of electrically conductive pads being arranged to form an interleaved structure, the electrically conductive pads extending through the electrically insulating layer from the first main surface to the second main surface, wherein the electrically conductive pads are aligned along a first major axis on the second main surface of the electrically insulating layer; and a plurality of parallel conductors mounted on the second main surface of the electrically insulating layer, wherein the parallel conductors are aligned along a second major axis on the second main surface of the electrically insulating layer; wherein the first major axis is substantially orthogonal to the second major axis at a location on the second main surface of the electrically insulating layer where
  • Substantially orthogonal means here that the first major axis and the second major axis are positioned under an angle of 90° with respect to each other including small positive or negative deviations from 90°, e.g., deviations below 0.1 °, 0.25°, 0.5°, 1 °, 2°, 3°, 4° or 5°.
  • Such build-up substrate has the advantage of a simple build-up structure, e.g., it can have 1.5 layers of which one layer has embedded preplated via bars, e.g., the electrically conductive pads. This results in a simplified structure with reduced manufacturing cost.
  • the design of a package with build-up substrate can be easily expanded to multi-die packages and different voltage classes in order to improve clearance and creepage distance.
  • the embedded large via bars through the package substrate also define the package footprint or pads for the component (depending on which side the routing is). This results in improved electrical and thermal performance compared to normal laminate structures.
  • the build-up substrate uses no leadframe but it can be seen as a leadframe-type package with isolated side walls. This provides the advantage that no Cu leads are exposed on the package side wall which reduces creepage distance.
  • the electrically conductive pads are arranged in an interdigitate pattern.
  • a respective pad of the plurality of electrically conductive pads is defined by a length and a width of the respective pad; wherein the length of the respective pad is longer than the width of the respective pad; and the first major axis is directed along the length of the respective pad.
  • the electrically conductive pads may have a thickness that is typically between 80 pm and 150 pm and lies in a range between about 40pm to 250pm. These electrically conductive pads may be made of preplated and embedded Cu bar, for example.
  • the plurality of electrically conductive pads form through vias through the electrically insulating layer of the build-up substrate.
  • the plurality of electrically conductive pads is formed according to a predetermined electrode pattern of at least one electronic chip included in the power package. This provides the advantage that the conductive pads of the build-up substrate are aligned with the electrode pattern of the chip. This results in a mapping of the electrode pattern to the footprint design of the package.
  • the plurality of electrically conductive pads and the plurality of parallel conductors are covered by the electrically insulating layer at edges of the build-up substrate to provide a lateral electrical insulation of the build-up substrate.
  • At least one pad of the plurality of electrically conductive pads is electrically isolated from at least one other pad of the plurality of electrically conductive pads by the electrically insulating layer; and/or at least one conductor of the plurality of conductors is electrically isolated from at least one other conductor of the plurality of conductors by the electrically insulating layer.
  • the build-up substrate can be used to manufacture both single and multi-die packages with or without integrated passives.
  • the build-up substrate can be used for one or more GaN dies having alternating source and gate pad structure.
  • the similar structures and same ideas can also be used for other types of gate-source configuration.
  • embodiments disclosed herein are primarily developed for packaging GaN dies they can also be used for other types of lateral current flow power dies or even vertical current flow dies, e.g., if a Cu clip is used to make the die back side connection.
  • the electrically insulating layer comprises at least one or a combination of lamination material or molding material; and/or the plurality of electrically conductive pads and the plurality of conductors comprise plated Cu structures.
  • the electrically conductive pads may have a thickness that is typically between 80 pm and 150 pm and lies in a range between about 40 pm to 250 pm. These electrically conductive pads may be made of preplated and embedded Cu bar, for example.
  • the conductors may have a thickness that is typically between 20 pm and 35 pm and lies in a range between about 10 pm to 150 pm. These conductors may be made of a Cu seed layer and plated Cu, for example.
  • the disclosure relates to a power package, comprising: a buildup substrate according to the first aspect; at least one electronic chip comprising a first main surface and a second main surface opposing the first main surface, the at least one electronic chip comprising at least one first terminal electrically connected to at least one pad of the plurality of electrically conductive pads and at least one second terminal electrically connected to at least one other pad of the plurality of electrically conductive pads; and an encapsulant encapsulating at least part of the at least one electronic chip; or an underfill attaching the at least one electronic chip to the build-up substrate.
  • the embedded large via bars through the package substrate also define the package footprint. This results in improved electrical and thermal performance compared to normal laminate structures.
  • the build-up substrate uses no leadframe but it can be seen as a leadframe-type package with isolated side walls. This provides the advantage that no Cu leads are exposed on the package side wall which reduces creepage distance.
  • the second main surface of the at least one electronic chip faces the first main surface of the electrically insulating layer; and the at least one first terminal and the at least one second terminal are arranged at the second main surface of the at least one electronic chip and mounted on respective pads of the plurality of electrically conductive pads.
  • the power package can be designed according to a first design option where the chip is placed on a first main surface of the buildup substrate that means on the first main surface of the electrically insulating layer.
  • the second main surface of the at least one electronic chip faces the second main surface of the electrically insulating layer; and the at least one first terminal and the at least one second terminal are arranged at the second main surface of the at least one electronic chip and mounted on respective conductors of the plurality of conductors.
  • the power package can be designed according to a second design option, also called flip-chip mounted, where the chip is placed on a second main surface of the build-up substrate that means on the second main surface of the electrically insulating layer.
  • the at least one electronic chip comprises a plurality of lateral faces arranged between the first main surface and the second main surface of the at least one electronic chip; wherein the encapsulant covers the first main surface and the lateral faces of the at least one electronic chip; or wherein the first main surface of the at least one electronic chip is uncovered by the encapsulant and the encapsulant at least partially covers the lateral faces of the at least one electronic chip; or wherein the first main surface of the at least one electronic chip is uncovered by the underfill and the underfill partially covers the lateral faces of the at least one electronic chip.
  • the design can be based on an overmolding process or an overmolding with exposed die back side process or an underfilling process.
  • the power package is forming a single die GaN package or a multidie GaN package in half bridge or parallel die configuration with or without driver and/or passives.
  • the power package comprises: at least one first solder layer arranged between the at least one first terminal and the at least one pad of the plurality of electrically conductive pads, the at least one first solder layer electrically connecting the at least one first terminal to the at least one pad of the plurality of electrically conductive pads; and/or at least one second solder layer arranged between the at least one second terminal and the at least one other pad of the plurality of electrically conductive pads, the at least one second solder layer electrically connecting the at least one second terminal to the at least one other pad of the plurality of electrically conductive pads.
  • solder layers can be efficiently used to attach and electrically connect the chip to the build-up substrate.
  • the power package is forming a lead frameless package.
  • the disclosure relates to a method for manufacturing a build-up substrate according to the first aspect for a power package, the method comprising: providing a carrier on which a metal layer is attached, the metal layer having a first main surface and an opposing second main surface facing the carrier; disposing a first photoresist layer onto the first main surface of the metal layer and forming openings in the first photoresist layer; metal plating the openings in the first photoresist layer; removing the first photoresist layer to form the plurality of electrically conductive pads; applying lamination or molding material over the first main surface of the metal layer and the metal plated plurality of electrically conductive pads; partially removing the lamination or molding material from the first main surface of the metal layer until the metal plated plurality of electrically conductive pads is exposed and removing the carrier from the second main surface of the metal layer; disposing a second photoresist layer onto the second main surface of the metal layer and forming openings in the second photoresist layer; and removing the
  • Such a method can be used for manufacturing a build-up substrate at reduced manufacturing cost.
  • the metal foil can be attached onto the carrier. Alternatively, this can be done by the foil manufacturer and a carrier covered with a metal foil is available in the first process step.
  • the disclosure relates to a method for manufacturing a build-up substrate according to the first aspect for a power package, the method comprising: providing a carrier on which a first metal layer is attached, the first metal layer having a first main surface and an opposing second main surface facing the carrier; disposing a first photoresist layer onto the first main surface of the first metal layer and forming openings in the first photoresist layer; metal plating the openings in the first photoresist layer; removing the first photoresist layer from the first metal layer to form the plurality of electrically conductive pads; applying lamination or molding material over the first main surface of the first metal layer and the metal plated plurality of electrically conductive pads and partially removing the lamination or molding material from the first main surface of the first metal layer until the metal plated plurality of electrically
  • Such a method can be used for manufacturing a build-up substrate at reduced manufacturing cost.
  • Embodiments described in this disclosure introduce a novel GaN package that differs from existing packages. Instead of half etched leadframe of usual laminate substrates, an advanced build-up substrate is applied as described in this disclosure.
  • Figure 1a shows a schematic cross section of a build-up substrate 110 for a power package 100 according to the disclosure
  • Figure 1b shows an exemplary package pad layout of the power package 100 shown in Figure 1a
  • Figure 1c shows an exemplary package footprint of the power package 100 shown in Figure 1a;
  • Figure 2a shows a schematic cross section of an overmolded power package 100 with buildup substrate 110 according to a first embodiment
  • Figure 2b shows a schematic cross section of an overmolded and exposed power package 100b with build-up substrate 110 according to a second embodiment
  • Figure 2c shows a schematic cross section of an underfilled power package 100c with buildup substrate 110 according to a third embodiment
  • Figure 2d shows a schematic cross section of an overmolded power package 100d with buildup substrate 110 according to a fourth embodiment
  • Figure 2e shows a schematic cross section of an overmolded and exposed power package 100e with build-up substrate 110 according to a fifth embodiment
  • Figure 2f shows a schematic cross section of an underfilled power package 10Of with build-up substrate 110 according to a sixth embodiment
  • Figures 3a-3f show schematic diagrams of an exemplary assembly process for manufacturing a power package by using a build-up substrate according to the disclosure
  • Figures 4a to 4c show schematic diagrams illustrating an exemplary die pad layout 400a, an exemplary package pad layout 400b and an exemplary package footprint 400c of a power package with build-up substrate according to the disclosure;
  • Figures 4d to 4f show schematic diagrams illustrating an alternative example of a die pad layout 400d, an alternative example of a package pad layout 400e and an alternative example of a package footprint 400f of the power package with build-up substrate;
  • Figures 4g and 4h show schematic diagrams illustrating exemplary footprints 400c, 400h of the power package with build-up substrate
  • Figure 5 shows a top view of a multi-die GaN package 500 in half-bridge configuration on buildup substrate according to an embodiment
  • Figures 6a and 6b show top views of the multi-die GaN package 500 of Figure 5 with Source and Drain connections in more detail (Fig. 6a) and the PGRD, VSWH and VIN connections in more detail (Fig. 6b);
  • Figure 7 shows a top view of a multi-die GaN package 700 with integrated driver and passives on buildup substrate according to an embodiment
  • Figure 8 shows a top view of a multi-die GaN package 800 in paralleled die configuration on buildup substrate according to an embodiment
  • FIGs 9a and 9b show top views of the multi-die GaN package 800 of Figure 8 with Drain connections in more detail (Fig. 9a) and Source connections in more detail (Fig. 9b);
  • Figures 10a-10h show schematic diagrams of an exemplary process flow for manufacturing a build-up substrate according to a first embodiment
  • Figures 11 a-11 k show schematic diagrams of an exemplary process flow for manufacturing a build-up substrate according to a second embodiment.
  • Figure 1a shows a schematic cross section of a build-up substrate 110 for a power package 100 according to the disclosure.
  • Figure 1b shows an exemplary package pad layout of the power package 100 and
  • Figure 1c shows an exemplary package footprint of the power package 100.
  • a build-up substrate 110 for the power package 100 is shown in Figure 1a.
  • the build-up substrate 110 comprises an electrically insulating layer 120, a plurality of electrically conductive pads 131a-e encapsulated in the electrically insulating layer 120 and a plurality of parallel conductors 132a-e.
  • the electrically insulating layer 120 has a first main surface 110a and an opposing second main surface 110b.
  • the plurality of electrically conductive pads 131a-e are arranged to form an interleaved structure.
  • the electrically conductive pads 131a-e are extending through the electrically insulating layer 120 from the first main surface 110a to the second main surface 110b.
  • the electrically conductive pads 131a-e are aligned along a first major axis on the second main surface 110b of the electrically insulating layer 120 as can be seen from the package pad layout shown in Figure 1b. This first major axis is shown as a vertical axis in the example of Figure 1b.
  • the plurality of parallel conductors 132a-e are mounted on the second main surface 110b of the electrically insulating layer 120.
  • the parallel conductors 132a-e are aligned along a second major axis on the second main surface 110b of the electrically insulating layer 120 as can be seen from the package footprint shown in Figure 1c. This second major axis is shown as a horizontal axis in the example of Figure 1c.
  • the first major axis is substantially orthogonal to the second major axis at a location on the second main surface 110b of the electrically insulating layer 120 where a respective pad 131a- e electrically connects a respective conductor 132a-e.
  • the electrically conductive pads 131a-e may be arranged in an interdigitate pattern as can be seen from Figure 1 b.
  • a respective pad of the plurality of electrically conductive pads 131a-e may be defined by a length and a width of the respective pad.
  • the length of the respective pad can be longer than the width of the respective pad as can be seen from Figure 1 b.
  • the first major axis may be directed along the length of the respective pad as can be seen from Figure 1 b.
  • the electrically conductive pads 131a-e may have a thickness that is typically between 80 pm and 150 pm and lies in a range between about 40pm to 250pm. These electrically conductive pads 131a-e may be made of preplated and embedded Cu bar, for example. Further details are described below with respect to Figures 4g and 4h.
  • the plurality of electrically conductive pads 131a-e may form through vias through the electrically insulating layer 120 of the build-up substrate 110 as can be seen from Figure 1a.
  • the plurality of electrically conductive pads 131a-e may be formed according to a predetermined electrode pattern of at least one electronic chip 140 included in the power package 100, e.g., as shown in Figures 2a to 2f below.
  • the plurality of electrically conductive pads 131a-e and the plurality of parallel conductors 132a-e may be covered by the electrically insulating layer 120 at edges of the build-up substrate 110 to provide a lateral electrical insulation of the build-up substrate, e.g., as shown in Figures 1 b and 1c.
  • embodiments according to the disclosure offer additional freedom:
  • the leads at the edge of the package can be exposed or can also be electrically insulated. On the other side, on conventional leadframe approaches, the leads are always exposed.
  • At least one pad of the plurality of electrically conductive pads 131a-e may be electrically isolated from at least one other pad of the plurality of electrically conductive pads 131a-e by the electrically insulating layer 120.
  • At least one conductor of the plurality of conductors 132a-e may be electrically isolated from at least one other conductor of the plurality of conductors 132a-e by the electrically insulating layer 120.
  • An additional solder mask can be formed on the second main surface 110b, e.g., as shown in Figures 10g and 10h. This additional solder mask may be opened only on the footprint area.
  • the build-up substrate can be used to manufacture both single and multi-die packages with or without integrated passives.
  • the build-up substrate can be used for one or more GaN dies having alternating source and gate pad structure.
  • the similar structures and same ideas can also be used for other types of gate-source configuration.
  • embodiments disclosed herein are primarily developed for packaging GaN dies they can also be used for other types of lateral current flow power dies or even vertical current flow dies, e.g., if a Cu clip is used to make the die back side connection.
  • the electrically insulating layer 120 may comprise at least one or a combination of lamination material or molding material.
  • the plurality of electrically conductive pads 131a-e and the plurality of conductors 132a-e may comprise plated Cu structures.
  • the electrically conductive pads 131a-e may have a thickness that is typically between 80 pm and 150 pm and lies in a range between about 40 pm to 250 pm. These electrically conductive pads 131a-e may be made of preplated and embedded Cu bar, for example. Further details are described below.
  • the conductors 132a-e may have a thickness that is typically between 20 pm and 35 pm and lies in a range between about 10 pm to 150 pm. These conductors 132a-e may be made of a Cu seed layer and plated Cu, for example. Further details are described below.
  • Figures 1a to 1c also show a power package 100 with buildup substrate 110.
  • the power package 100 comprises the build-up substrate 110 as described above, at least one electronic chip 140 and an encapsulant 150 encapsulating at least part of the at least one electronic chip 140 or an underfill 151 attaching the at least one electronic chip 140 to the build-up substrate 110, e.g., as shown below with respect to Figures 2a to 2f.
  • the at least one electronic chip 140 comprises a first main surface 140a and a second main surface 140b opposing the first main surface 140a.
  • the at least one electronic chip 140 comprises at least one first terminal 141 electrically connected to at least one pad 131a of the plurality of electrically conductive pads 131a-e and at least one second terminal 142 electrically connected to at least one other pad 131c of the plurality of electrically conductive pads 131a-e, e.g., as shown below with respect to Figures 2a to 2f.
  • the second main surface 140b of the at least one electronic chip 140 may face the first main surface 110a of the electrically insulating layer 120.
  • the at least one first terminal 141 and the at least one second terminal 142 may be arranged at the second main surface 140b of the at least one electronic chip 140 and may be mounted on respective pads of the plurality of electrically conductive pads 131a-e.
  • the second main surface 140b of the at least one electronic chip 140 may face the second main surface 110b of the electrically insulating layer 120.
  • the at least one first terminal 141 and the at least one second terminal 142 may be arranged at the second main surface 140b of the at least one electronic chip 140 and may be mounted on respective conductors of the plurality of conductors 132a-e.
  • the at least one electronic chip 140 may comprise a plurality of lateral faces arranged between the first main surface 140a and the second main surface 140b of the at least one electronic chip 140.
  • the encapsulant 150 may cover the first main surface 140a and the lateral faces of the at least one electronic chip 140.
  • the first main surface 140a of the at least one electronic chip 140 may be uncovered by the encapsulant 150 and the encapsulant 150 may at least partially cover the lateral faces of the at least one electronic chip 140.
  • the first main surface 140a of the at least one electronic chip 140 may be uncovered by the underfill 151 and the underfill 151 may partially cover the lateral faces of the at least one electronic chip 140.
  • the power package 100 may form a single die GaN package or a multidie GaN package, e.g., in half bridge or parallel die configuration with or without driver and/or passives.
  • the power package 100 may comprise at least one first solder layer 133a arranged between the at least one first terminal 141 and the at least one pad 131a of the plurality of electrically conductive pads 131a-e, e.g., as shown in Figures 2a to 2c.
  • the at least one first solder layer 133a may electrically connect the at least one first terminal 141 to the at least one pad 131a of the plurality of electrically conductive pads 131a-e.
  • the first solder layer 133a is not directly arranged between the first terminal 141 and the electrically conductive pad 131a but indirectly via conductor 132a.
  • the power package 100 may comprise at least one second solder layer 133c arranged between the at least one second terminal 142 and the at least one other pad 131c of the plurality of electrically conductive pads 131a-e, e.g., as shown in Figures 2a to 2f.
  • the at least one second solder layer 133c may electrically connect the at least one second terminal 142 to the at least one other pad 131 c of the plurality of electrically conductive pads 131 a-e.
  • the power package 100 may form a lead frameless package.
  • Layer 101 depicts a Cu metallization or Cu, Ni, etc. bump, for example. This layer 101 can have a thickness between about 8 pm and 12 pm or even between 3 pm and 80 pm, for example.
  • the layer 101 may be made of power metal on die or non-solderable bump on top of AICu, for example.
  • Layer 102 depicts a solder layer, for example. This layer 102 can have a thickness between about 20 pm and 80 pm or even between 10 pm and 150 pm, for example.
  • the layer 102 may be made of solder bump, solder bump and printed solder or printed solder, for example.
  • Layer 103 depicts the conductive pads 131a-e as referred to in this disclosure and layer 104 depicts the parallel conductors 132a-e as referred to in this disclosure.
  • layer 103 may also be referred to as via bars, e.g., Cu via bars (for flip chip pad) and layer 104 may also be referred to as pads (for the package footprint).
  • Layer 103 can have a thickness between about 80 pm and 150 pm or even between 40 pm and 250 pm, for example.
  • the layer 103 may be made of pre-plated and embedded Cu bar, for example.
  • Layer 104 can have a thickness between about 20 pm and 35 pm or even between 10 pm and 150 pm, for example.
  • the layer 104 may be made of Cu seed-layer and plated Cu, for example.
  • FIGs 2a to 2c and the Figures 2d to 2f three different types of molding or underfilling options are presented.
  • the protection of the dies can be done with overmolding as shown in Figures 2a and 2d, e.g., panel level overmolding or smaller size strip level over molding and if better top side cooling is needed, the die back side can be exposed e.g., by grinding, as shown in Figures 2b and 2e.
  • the overmolding can also be avoided if normal underfilling process is used, as shown in Figures 2c and 2f.
  • the overmolded power package 100 with build-up substrate 110 as shown in Figure 2a corresponds to the power package 100 described above with respect to Figure 1 .
  • the at least one electronic chip 140 is mounted on the build-up substrate 110 such that the second main surface 140b of the chip 140 faces the first main surface 110a of the build-up substrate 110.
  • the parallel conductors 132a-e are exposed at the bottom side of the package 100, 100b, 100c.
  • the opposite mounting technology e.g., flip-chip mounting is applied. That means, the at least one electronic chip 140 is mounted on the build-up substrate 110 such that the second main surface 140b of the chip 140 faces the second main surface 110b of the buildup substrate 110.
  • the parallel conductors 132a-e are embedded in the encapsulant 150 and the electrically conductive pads 131a-e are arranged and exposed at the bottom side of the package 100d, 100e, 100f.
  • Figures 3a-3f show schematic diagrams of an exemplary assembly process for manufacturing a power package by using a build-up substrate according to the disclosure.
  • the assembly process can be used to manufacture a single die GaN package, e.g., a power package 100d or 10Of as described above with respect to Figures 2d and 2e, that is using flip chip bonding and buildup substrate 110.
  • the process option described in Figures 3a-3f is using build up substrate 110 (see Figure 3a), where the footprint and the vias 131a-e through the substrate 110 are large area Cu bars that can be produced by a plating process before embedding those inside mold or laminate material.
  • soldering pads for the GaN die 140 are on top side of the package.
  • a solder 133a-e is printed or dispensed on a substrate 110 (see Figure 3b) and the die 140 pick and placed on top of the solder 13a-e (see Figure 3c) and the connection is done with normal reflow soldering (see Figure 3d). After soldering the dies 140 can be protected with over molding (see Figure 3e) or under filling (see Figure 3f).
  • the die 140 has either solder bump or solderable bumps 104.
  • Figures 4a to 4c show schematic diagrams illustrating an exemplary die pad layout 400a, an exemplary package pad layout 400b and an exemplary package footprint 400c of a power package with build-up substrate according to the disclosure.
  • Figures 4d to 4f show schematic diagrams illustrating an alternative example of a die pad layout 400d, an alternative example of a package pad layout 400e and an alternative example of a package footprint 400f of the power package with build-up substrate.
  • solder bump and package top and bottom side are presented.
  • the die in this variant has a structure where the source and drain lines are alternating.
  • the distance and width of the source and drain lines on the die is too small so that correct clearance distance or enough large pad size and space for soldering I final assembly on the PCB can be achieved.
  • Figures 4a to 4c show 2-layer designs 400a-c (substrate top and bottom) where the drain and source lines of the die are rotated 90 degree by using the package routing so that the clearance can be increased to meet the voltage class requirement.
  • substrate only routing layers calculated
  • the line space and clearance can be expanded without rotating the source and drain lines on the substrate with 90 degree.
  • Figures 4a to 4f are only for illustration and the die design and also the package footprint design can be modified, e.g., the size, shape, location and number of source and drain lines on die and package.
  • the figures also show a structure in which the GaN die or dies have alternating source and gate pad structure, but the similar package structures and same ideas can be used also for other types of gate-source configuration.
  • embodiments disclosed herein are primarily developed for packaging GaN dies they can also be used for other types of lateral current flow power dies or even vertical current flow dies, e.g., where a Cu clip is used to make the die back side connection.
  • Figures 4g and 4h show schematic diagrams illustrating exemplary footprints 400c, 400h of the power package with build-up substrate.
  • drain and source pads and also the gate pads of the package footprint can be arranged in lines as shown in Figure 4g or in individual pads as shown in Figure 4f.
  • Figure 4g a minimum number of 2 rows can be implemented.
  • Figure 4g shows a number of n rows.
  • the maximum number of rows may depend on the package size and the voltage class. For an example with 5x6mm package size and 50-150V, the maximum number of rows is 5.
  • an exemplary number of 5 rows and an exemplary number of 5 columns is shown.
  • a minimum number of 2 rows can be implemented.
  • the maximum number of rows may depend on the package size and the voltage class. For an example with 5x6mm package size and 50-150V, the maximum number of rows is 5.
  • a minimum number of 2 columns can be implemented.
  • the maximum number of columns may depend on the package size. For an example with 5x6mm package size, the maximum number of columns is 5.
  • Wi a denotes the source or drain line width when source or drain is in the same row with gate. Wi a may depend on the package width and the maximum package width.
  • W denotes the source or drain line width when source or drain is in line without gate. W may depend on the package width and the maximum package width. Typical values can be, for example 200-400pm smaller than the package width. An exemplary range for W can be between 0 and 600pm smaller than the package width.
  • W2 denotes the gate pad for 1 or 2 gate pads.
  • the pad location can be on corner or in the middle depending on the die design.
  • Typical values for W2 can be, for example 400- 600pm.
  • An exemplary range for W2 can be between 300 and 1200pm.
  • W3 denotes the pad width in the matrix, the pad can be square, rectangular or round.
  • Typical values for W3 can be, for example 400-600pm.
  • An exemplary range for W3 can be between 300 and 1200pm.
  • H denotes the pad height.
  • Typical values for H can be, for example 400- 600pm.
  • An exemplary range for H can be between 300 and 1200pm.
  • C denotes the clearance, that may depend on the voltage class. Typical values for C can be, for example 0,6 mm.
  • Figure 5 shows a top view of an exemplary multi-die GaN package 500 in half-bridge configuration on buildup substrate according to an embodiment.
  • the figure shows die metallization, solder bumps on a die (round) and package top metallization.
  • the HS and LS dies have the same size which is only an example. The locations and connections can be different and the die sizes and shapes can vary.
  • the multi-die GaN package 500 can also include drivers and/or passive components.
  • the manufacturing process and embodiments for multi die option are the same than used for single die.
  • Figure 5 shows the dies metallization, solder bumps and the package top metallization.
  • the right side die 501 is rotated by 180 degree with respect to the left side die 502 and the half bridge connection is done with package routing. From Figure 5, it can be seen how the source lines 502a of the left side die 502 are connected to the drain lines 501 b of the right side die 501 with solder bumps 503. Both dies 501 , 502 are using the same solder bump 503 design.
  • Figures 6a and 6b show top views of the multi-die GaN package 500 of Figure 5 with Source and Drain connections in more detail (Fig. 6a) and the PGRD, VSWH and VIN connections in more detail (Fig. 6b).
  • Figure 7 shows a top view of a multi-die GaN package 700 with integrated driver and passives on buildup substrate according to an embodiment.
  • the figure shows package top metallization 704, solder bumps 503 on a die (round) and package footprint metallization 703.
  • driver 701 can be integrated into the package 700.
  • the footprint of the package 700 is marked by 702.
  • Figure 8 shows a top view of a multi-die GaN package 800 in paralleled die configuration on buildup substrate according to an embodiment.
  • Figure 8 shows embodiments of this disclosure that can be used to manufacture package where the dies are paralleled. Paralleling the power dies allows to reduce the RDSon and to reduce the conduction losses. Paralleling also allows to reach higher currents in case the chip size is limited (e.g., SiC).
  • the manufacturing process and embodiments for multi die option are the same than used for single die.
  • Figure 8 shows the connections between the two dies 801 , 802. Like in half bridge package also in parallel die package the right-side die 801 is rotated with 180 degree with respect to the left-side die 802 and the connection between the dies is done with package routing.
  • Figure 8 shows how the source, drain and gate of both dies 801 , 802 can be connected to each other with short lines 803a, 803b, 803c. With a correct footprint design the gate, source and drain connections to the PCB can be balanced
  • Figures 9a and 9b show top views of the multi-die GaN package 800 of Figure 8 with Drain connections in more detail (Fig. 9a) and Source connections in more detail (Fig. 9b).
  • Figures 10a-10h show schematic diagrams of an exemplary process flow for manufacturing a build-up substrate 110 according to a first embodiment.
  • the figures describe the manufacturing and PCB structure to manufacture buildup substrate 110 for GaN with simplified and cost optimized manufacturing process.
  • the process flow represents a simple process that may use existing processes but compared to normal process flows all not necessary process steps are skipped to reduce the process time and process cost.
  • the process uses a carrier 1001 where Cu seed layer 1010 (having an exemplary thickness of about 1 to 150pm) is attached to a temporary carrier 1011 as shown in Figure 10a.
  • the first step after the carrier (temporary carrier 1011 + Cu foil 1010) manufacturing is photolithography process 1002 as shown in Figure 10b.
  • photolithography process large area openings 1013 are manufactured to the photoresist 1012. These large area openings 1013 are forming the vias through the package and the substrate footprint.
  • the plated Cu structures are exposed from top side with grinding or milling process as can be seen from Figure 10f.
  • the temporary carrier 1011 is removed 1006 as shown in Figure 10f and after a lithography step 1007 as shown in Figure 10g, the Cu carrier 1010 is etched 1008 to form the package top or bottom side as shown in Figure 10h.
  • Final step is the optional solder masking and surface finishing (solderable surface e.g., ENIG, etc.)
  • FIG. 10a-10h can be described by a method 1000 for manufacturing a build-up substrate 110 for a power package 100, e.g., as described above with respect to Figures 1 and 2a-f, the method 1000 comprising the following steps: Providing 1001 a carrier 1011 on which a metal layer 1010 is attached, the metal layer 1010 having a first main surface 1010a and an opposing second main surface 1010b facing the carrier;
  • the metal foil 1010 can be attached onto the carrier 1011. Alternatively, this can be done by the foil manufacturer and a carrier 1011 covered with a metal foil 1010 is available in the first process step 1001.
  • Figures 11 a-11 k show schematic diagrams of an exemplary process flow for manufacturing a build-up substrate according to a second embodiment.
  • the figures describe the manufacturing and PCB structure to manufacture buildup substrate 110 for GaN with simplified and cost optimized manufacturing process.
  • the process flow represents a simple process that may use existing processes but compared to normal process flows all not necessary process steps are skipped to reduce the process time and process cost.
  • the process shown in Figures 11a-k uses also carrier 1101 where the Cu seed layer 1110 is attached to a temporary carrier 1111.
  • the first step 1102 after the carrier (temporary carrier 1111 + Cu foil 1110) manufacturing 1101 is a photolithography process 1102.
  • photolithography process 1102 large area openings 1113 are manufactured to the photoresist 1112. These large area openings 1113 are forming the vias through the package and the substrate footprint.
  • a seed layer 1115 is sputtered 1106 on the exposed side of the panel as shown in Figure 11 f. This is followed by lithography process 1107, pattern plating process 1108, resist removal process 1109 and seed layer etching 1120 process.
  • solderable surface e.g. ENIG, etc.
  • the temporary Cu carrier 1111 is removed 1121 as shown in Figure 11 k and the seed layer is etched or structured 1120 as shown in Figure 11j.
  • FIG. 11a-k The process flow shown in Figures 11a-k can be described by a method 1100 for manufacturing a build-up substrate 110 for a power package 100, e.g., as described above with respect to Figures 1 and 2a-f, the method 1100 comprising the following steps: Providing 1101 a carrier 1111 on which a first metal layer 1110 is attached, the first metal layer having a first main surface and an opposing second main surface facing the carrier 1111 ;
  • the carrier and the first metal layer can also remain at least partially in the final structure, e.g., by applying photolithography and etching process. This can be the same process as described above with respect to Figures 10g and 10h. While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include”, “have”, “with”, or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise”.

Abstract

L'invention concerne un substrat d'accumulation (110) pour un bloc d'alimentation (100). Le substrat d'accumulation (110) comprend une couche électriquement isolante (120) et une pluralité de plots électriquement conducteurs (131a-e) encapsulés dans la couche électriquement isolante (120). Les plots électriquement conducteurs (131a-e) sont agencés pour former une structure entrelacée. Les plots électriquement conducteurs s'étendent à travers la couche électriquement isolante (120) d'une première surface principale (110a) à une deuxième surface principale (110b) de la couche isolante (120). Les plots électriquement conducteurs (131a-e) sont alignés le long d'un premier axe principal sur la deuxième surface principale (110b). Le substrat d'accumulation (110) comprend une pluralité de conducteurs parallèles (132a-e) montés sur la deuxième surface principale (110b) de la couche électriquement isolante (120). Les conducteurs parallèles (132a-e) sont alignés le long d'un deuxième axe principal sur la deuxième surface principale (110b) de la couche électriquement isolante (120). Le premier axe principal est sensiblement orthogonal au deuxième axe principal à un emplacement sur la deuxième surface principale (110b) de la couche électriquement isolante (120) où un plot respectif (131a-e) connecte électriquement un conducteur respectif (132a-e).
PCT/EP2022/078046 2022-10-10 2022-10-10 Substrat d'accumulation pour bloc d'alimentation WO2024078682A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3355351A1 (fr) * 2017-01-20 2018-08-01 Infineon Technologies Austria AG Dispositif interdigital sur leadframe pour écoulement de courant réparti uniformément
US20220102263A1 (en) * 2020-09-28 2022-03-31 Infineon Technologies Ag Semiconductor package having a chip carrier with a pad offset feature

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3355351A1 (fr) * 2017-01-20 2018-08-01 Infineon Technologies Austria AG Dispositif interdigital sur leadframe pour écoulement de courant réparti uniformément
US10074597B2 (en) 2017-01-20 2018-09-11 Infineon Technologies Austria Ag Interdigit device on leadframe for evenly distributed current flow
US20220102263A1 (en) * 2020-09-28 2022-03-31 Infineon Technologies Ag Semiconductor package having a chip carrier with a pad offset feature

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