WO2024077892A1 - 模型设计方法、装置、设备及计算机可读存储介质 - Google Patents

模型设计方法、装置、设备及计算机可读存储介质 Download PDF

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Publication number
WO2024077892A1
WO2024077892A1 PCT/CN2023/086003 CN2023086003W WO2024077892A1 WO 2024077892 A1 WO2024077892 A1 WO 2024077892A1 CN 2023086003 W CN2023086003 W CN 2023086003W WO 2024077892 A1 WO2024077892 A1 WO 2024077892A1
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Prior art keywords
model
design
simulation
design method
device model
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PCT/CN2023/086003
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English (en)
French (fr)
Inventor
王健
周国华
黎嘉勇
陈奎莅
周坤
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深圳市中兴微电子技术有限公司
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Publication of WO2024077892A1 publication Critical patent/WO2024077892A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/373—Design optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

  • the embodiments of the present application relate to the field of integrated circuit technology, and in particular to model design methods, devices, equipment, and computer-readable storage media.
  • ring oscillator is often used in design technology co-optimization (DTCO) research, and the results can be applied to device structure optimization, circuit design margin tightening and S2S (Spice to Silicon, model and test data) calibration, ultimately achieving PPAC (Power Performance Area Cost) benefits in design.
  • DTCO design technology co-optimization
  • the device models provided by existing ring oscillator design solutions generally only include one ring oscillator design method. With the introduction of advanced processes, this single device model often cannot fully cover the design and use requirements. In addition, there are certain errors between the simulation results and the production and manufacturing test results of these solutions, which seriously affects the improvement of circuit performance.
  • the main purpose of the embodiments of the present application is to provide a model design method, device, equipment and computer-readable storage medium, aiming to promote the integration of model simulation and actual production and manufacturing, and ultimately realize a ring oscillator with wide coverage, strong manufacturability, high reliability and high precision.
  • the present invention provides a model design method, which includes:
  • tape-out is performed based on the device model to obtain an actual chip including each of the ring oscillators;
  • the device model is iteratively optimized based on the hardware test results and the model simulation results.
  • the embodiment of the present application further provides a model design device, the model design device comprising:
  • a model design module configured to design a device model including a plurality of ring oscillators based on a preset process library model, wherein the basic structure of each ring oscillator is different;
  • a simulation verification module configured to perform simulation verification based on the device model to obtain a model simulation result
  • a trial production module configured to tape out the device model to obtain an actual chip including each of the ring oscillators if the model simulation result meets a preset standard
  • a hardware testing module configured to perform hardware testing based on the actual chip to obtain a hardware testing result
  • the iterative optimization module is configured to iteratively optimize the device model based on the hardware test results and the model simulation results.
  • an embodiment of the present application also provides a model design device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the computer program is executed by the processor, the model design method as described above is implemented.
  • an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the model design method as described above is implemented.
  • the present application embodiment provides a model design method, device, equipment and computer-readable storage medium.
  • a plurality of ring oscillators are designed based on a preset process library model.
  • the device model of the device has different basic structures of the ring oscillators, which overcomes the technical defect that the device model in the prior art cannot fully cover the design and use requirements, significantly expands the applicable scenarios of the device model, and the device model is a circuit design performed by digital PR (Place and Route, layout and wiring) means, and the circuit wiring is automatically generated by software, so that the designed circuit can be closer to the digital design environment, and the test chip results are closer to the actual digital circuit results, and the coupling between the experimental circuit and the digital circuit is strengthened; the embodiment of the present application simulates and verifies the device model, and compares the model simulation results of the ring oscillator with the actual tape-out test results.
  • digital PR Picture and Route, layout and wiring
  • FIG1 is a schematic diagram of a flow chart of a model design method provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of transistor layout designs of different structures designed by a model design method provided in an embodiment of the present application
  • FIG3 is a schematic diagram of a ring oscillator layout design involved in a model design method provided in an embodiment of the present application
  • FIG4 is a schematic diagram of the structure of a model design device provided in one embodiment of the present application.
  • FIG5 is a schematic diagram of the hardware structure of a model design device provided in an embodiment of the present application.
  • references to “one embodiment” or “some embodiments” described in the specification of the embodiments of the present application mean that one or more embodiments of the embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment.
  • the statements “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean “one or more but not all embodiments", unless otherwise specifically emphasized in other ways.
  • the terms “including”, “comprising”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized in other ways.
  • ring oscillators In the design of digital IC (Integrated Circuit Chip), the design margin problem of advanced processes has become increasingly prominent.
  • ring oscillators RO are often used in the study of design and process co-optimization, and the results can be applied to device structure optimization, circuit design margin tightening and S2S calibration, ultimately achieving PPAC benefits in design.
  • the device models provided by existing ring oscillator design solutions generally only include one ring oscillator design method, and with the introduction of advanced processes, this single device model often cannot fully cover the design requirements; in addition, there are certain errors between the simulation results and the production and manufacturing test results of these solutions, which seriously affect the improvement of circuit performance.
  • a device model including multiple ring oscillators is designed based on a preset process library model.
  • the basic structures of each ring oscillator are different, which overcomes the technical defect that the device model in the prior art cannot fully cover the design and use requirements, and significantly expands the applicable scenarios of the device model.
  • the device model is a circuit design performed by digital layout and wiring means, and the circuit wiring is automatically generated by software, so that the designed circuit can be closer to the digital design environment, and the test chip results can be closer to the actual digital circuit results, thereby strengthening the coupling between the experimental circuit and the digital circuit.
  • the embodiments of the present application simulate and verify the device model, and compare the model simulation results of the ring oscillator with the actual tape-out test results. By analyzing the comparison results, iterative optimization of the device model is achieved, ensuring that the device model is consistent with the production and manufacturing results, and promoting the integration of model simulation and actual production and manufacturing processes. Continuously improve circuit performance and ultimately achieve a ring oscillator with wide coverage, strong manufacturability, high reliability and high precision.
  • model design method, device, equipment and computer-readable storage medium provided in the embodiments of the present application are specifically illustrated through the following embodiments. First, the model design method in the embodiments of the present application is described.
  • Figure 1 is a flow chart of a model design method provided in an embodiment of the present application.
  • the model design method can be applied to a model design device.
  • the model design method provided in this embodiment includes steps S10 to S50.
  • Step S10 designing a device model including a plurality of ring oscillators based on a preset process library model, wherein the basic structure of each ring oscillator is different;
  • the preset process library model comes from the process factory. Before the circuit simulation design of the ring oscillator is performed in this embodiment, the process library model provided by the process factory needs to be imported first, and the ring oscillator is designed into a variety of basic structures based on the process library model according to the types of gate circuits in the ring oscillator and the different input paths.
  • the ring oscillator of each basic structure is composed of an odd number of levels (for example, 201 levels) of inverting logic gates, wherein the inverting logic gate can be a NAND gate, an INV inversion matrix or a NOR gate.
  • the circuit structure of each ring oscillator in the device model is realized by digital PR means.
  • the structure design realizes the selection of specific links through registers and selectors to meet different usage requirements; the design of different Type links is realized by exchanging the input ports. Based on the requirements of advanced processes, the influence of factors such as FIN (fin), NF (Finger Number) and POWER (power, power, performance) on the ring oscillator is considered to ensure that the design covers common standard units; the layout is realized by using adjacent layout, overall mirroring and S-shaped arrangement to save device space and reduce power wiring, thereby maximizing PPAC benefits.
  • Step S20 performing simulation verification based on the device model to obtain a model simulation result
  • the present embodiment verifies and post-simulates the device model, and confirms whether the device model meets the design requirements based on the verification and post-simulation results.
  • Step S30 if the model simulation result meets the preset standard, tape out is performed based on the device model to obtain an actual chip including each ring oscillator;
  • the preset standard can be a design standard given by the process factory, or it can be a design requirement obtained by the designer after adjusting the given design standard.
  • the GDSII a database file format used for data conversion of integrated circuit layout
  • the chip obtained by the process factory based on GDSII tape-out can be obtained, which includes the multi-channel ring oscillator in the device model.
  • model simulation results do not meet the preset standards, there is no need to proceed to the subsequent tape-out steps, and the circuit and layout design of the device model needs to be re-performed based on the model simulation results.
  • Step S40 performing hardware testing based on the actual chip to obtain hardware test results
  • an RO (Ring Oscillator) in the chip is powered on by an external power supply, and the parameters of the power supply are set to the design values of the corresponding ring oscillator in the device model.
  • the output data (such as output current, frequency or phase noise, etc.) is read through the output port of the chip, and then other ROs are replaced to perform the same operation until all ROs in the chip are tested. All test data read from the output port of the chip can be used as hardware test results.
  • Step S50 iteratively optimizing the device model based on the hardware test results and the model simulation results.
  • the device model is improved by adjusting the model parameters until the error between the model simulation results and the actual test results is less than the set value.
  • the designed ring oscillator model has achieved the expected goal under the actual advanced process and can be applied to actual production.
  • the oscillator is the core module of the clock generation circuit, and its own performance greatly affects the performance of the entire clock generation circuit.
  • CMOS Complementary Metal Oxide Semiconductor
  • the implementation structure of CMOS (Complementary Metal Oxide Semiconductor) oscillators is often concentrated in two types: LC (inductor L, capacitor C) oscillators and ring oscillators.
  • LC induct L, capacitor C
  • ring oscillator is mainly composed of a number of cascaded delay units. When the output signal of a unit passes through the entire loop and returns to the input of the unit, the signal flips, causing the circuit to generate a periodic oscillation signal. Since the ring oscillator does not have a high-quality filter, the phase noise is greatly affected by PVT (process, voltage, temperature).
  • this embodiment simulates and tapes out different types of inverting gate circuits composed of odd-numbered stages (for example, 201, which can also be changed to other odd values according to the actual needs of the circuit) based on the advanced process of TSMC (TSMC, Taiwan Semiconductor Manufacturing Co., Ltd.).
  • TSMC Taiwan Semiconductor Manufacturing Co., Ltd.
  • the ring oscillator is used to verify the process library model.
  • This embodiment proposes a model design method, which designs a device model including multiple ring oscillators based on a preset process library model.
  • the basic structures of each ring oscillator are different, which overcomes the technical defect that the device model in the prior art cannot fully cover the design and use requirements, and significantly expands the applicable scenarios of the device model.
  • the device model is a circuit design performed by digital layout and wiring means, and the circuit wiring is automatically generated by software, so that the designed circuit can be closer to the digital design environment, and the test chip results can be closer to the actual digital circuit results, thereby strengthening the coupling between the experimental circuit and the digital circuit.
  • the embodiment of the present application simulates and verifies the device model, and compares the model simulation results of the ring oscillator with the actual tape-out test results. By analyzing the comparison results, iterative optimization of the device model is achieved, ensuring that the device model is consistent with the production and manufacturing results, promoting the integration of model simulation and actual production and manufacturing processes, and being able to continuously improve circuit performance, and ultimately achieving a ring oscillator with wide coverage, strong manufacturability, high reliability, and high precision.
  • step S10 may include but is not limited to the following steps:
  • Step S11 designing a plurality of ring oscillators based on a preset process library model, wherein the basic structure of each ring oscillator is different;
  • Step S12 expanding each ring oscillator to obtain multiple design methods
  • Step S13 instantiating a plurality of units to be verified based on each design method, each unit to be verified corresponds to a ring oscillator;
  • Step S14 generating a device model including a plurality of ring oscillators based on each unit to be verified.
  • each ring oscillator includes multiple components, and step S12 may include but is not limited to the following steps:
  • Step S121 changing the type and quantity of each component, and recombining the changed components to obtain a variety of design methods covering a preset standard cell library.
  • the ring oscillator is divided into several types according to the gate circuit type (not gate, NAND gate 1, NAND gate 2, NOR gate 1, NOR gate 2) and the number of fingers in the FinFET (Fin Field-Effect Transistor) structure under advanced process and the threshold voltage (Vt) of the MOS tube.
  • These oscillator units can almost cover the common standard unit types; the basic structure of each ring oscillator can include but is not limited to using NAND+INV, NAND, and INV+NOR to design the ring oscillator link respectively, considering the difference between NAND and NOR in actual operation.
  • This embodiment also introduces a multi-gate finger structure.
  • TSMC's advanced process can customize the number of gates and fins (FIN) according to needs.
  • This embodiment introduces a multi-gate finger structure to simulate the simulation situation under different gate numbers.
  • the multi-gate finger structure device enhances the ability to control current by increasing the number of gates.
  • Metal is a metal material
  • Poly is a polysilicon material
  • G, D, and S correspond to the gate, drain, and source respectively;
  • This embodiment designs the threshold voltage Vt to ULVT (Ultra-Low Voltage Threshold), SVT (Standard Value Threshold), LVT (Low Voltage Threshold), and ELVT (Extra-Low Voltage Threshold).
  • Threshold, ultra-low threshold voltage), LVTLL, ULVTLL and other types so there are multiple types of ring oscillators; instantiate each oscillator as a module (i.e., the unit to be verified), for example, instantiate each RO as a Cell (unit) and name it.
  • FIN When FIN is equal to 2, define RO_FIN2_NFx_TYPEy_VTz as the RO name, where x, y, z need to be replaced with the actual device Finger Number, circuit type, and Vt type.
  • the input pin of Cell is defined as IN_FIN2_NFx_TYPEy_VTz, where x, y, z need to be replaced with the actual device Finger Number, circuit type, and Vt type.
  • ZN_FIN2_NFx_TYPEy_VTz is the output pin definition, where x, y, z need to be replaced with the actual device Finger Number, circuit type, and Vt type; through the combination of Type, Fin, NF, and Vt, a variety of design methods are formed, thereby covering common standard units in the back-end settings. It should be noted that, based on the various design methods provided in this embodiment, technical solutions for optimizing the ring oscillator by adjusting the link type, the number of logic gates, Fin, NF and Vt should all be included in the protection scope of this embodiment.
  • step S14 may include but is not limited to the following steps:
  • a device model containing multiple ring oscillators is generated based on each ring oscillator layout.
  • the layout design of the ring oscillator that completes the link design is performed.
  • the arrangement of each RO can be shown in FIG. 3 .
  • the logic gates are arranged in an S shape to ensure the rationality of the width-to-length ratio in the layout design. For example, when 200 logic gates are arranged, 50 logic gates are placed horizontally in the first row, and 50 logic gates are placed in the second row in a mirrored manner. Then, the above 100 logic gates are mirrored to obtain the final arrangement. At this time, the starting point and the end point are located on the same side (such as The layout design shown in Figure 3 starts on the right side of the first row and ends on the right side of the fourth row), forming a loop to save device space and reduce power wiring.
  • the vertical AA (Active area) space is kept consistent with the Device AA space to further reduce the subsequent device space usage and maximize PPAC benefits.
  • other ROs are also laid out in the above manner, and the layout of the entire device model is arranged vertically or horizontally.
  • step S20 may include but is not limited to the following steps:
  • Step S201 performing simulation verification on each unit to be verified to obtain a model simulation result.
  • step S50 may include but is not limited to the following steps:
  • Step S501 if the error between the hardware test result and the model simulation result is greater than a preset threshold, the model parameters are adjusted to improve the device model, and based on the improved device model, the step of performing simulation verification based on the device model to obtain the model simulation result is returned to be executed, until the error between the new hardware test result and the model simulation result is less than the preset threshold.
  • the preset threshold can be specified by the process factory or adjusted appropriately by the designer.
  • the device model is improved by adjusting the model parameters until the error between the model simulation result and the actual test result is less than the set value.
  • This embodiment can achieve iteration of device model optimization by repeatedly analyzing the model simulation results and the actual test results, thereby promoting the consistency between model simulation and actual manufacturing, and promoting the improvement of design performance and yield.
  • the model design method may further include but is not limited to the following steps:
  • Step A If the error between the hardware test result and the model simulation result is less than a preset threshold, the device model is set as a mass production model.
  • the present application also provides a model design device, referring to FIG. 4 , which is a schematic diagram of the structure of a model design device provided in an embodiment of the present application.
  • the model design device includes: a model design module 100 , a simulation verification module 200 , a trial production module 300 , a hardware testing module 400 and an iterative optimization module 500 .
  • a model design module 100 is configured to design a device model including a plurality of ring oscillators based on a preset process library model, wherein the basic structure of each ring oscillator is different;
  • a simulation verification module 200 is configured to perform simulation verification based on a device model to obtain a model simulation result
  • the trial production module 300 is configured to tape out the actual chip including each ring oscillator based on the device model if the model simulation result meets the preset standard;
  • a hardware testing module 400 is configured to perform hardware testing based on an actual chip to obtain a hardware testing result
  • the iterative optimization module 500 is configured to iteratively optimize the device model based on the hardware test results and the model simulation results.
  • This embodiment proposes a model design device, which designs a device model including multiple ring oscillators based on a preset process library model.
  • the basic structures of each ring oscillator are different, which overcomes the technical defect that the device model in the prior art cannot fully cover the design and use requirements, and significantly expands the applicable scenarios of the device model.
  • the device model is a circuit design performed by digital layout and wiring means, and the circuit wiring is automatically generated by software, so that the designed circuit can be closer to the digital design environment, and the test chip results can be closer to the actual digital circuit results, thereby strengthening the coupling between the experimental circuit and the digital circuit.
  • the embodiment of the present application simulates and verifies the device model, and compares the model simulation results of the ring oscillator with the actual tape-out test results. By analyzing the comparison results, iterative optimization of the device model is achieved, ensuring that the device model is consistent with the production and manufacturing results, promoting the integration of model simulation and actual production and manufacturing processes, and being able to continuously improve circuit performance, and ultimately achieving a ring oscillator with wide coverage, strong manufacturability, high reliability, and high precision.
  • model design device provided in this embodiment and the model design method provided in the above embodiment belong to the same inventive concept.
  • the technical details not fully described in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as executing the model design method.
  • the device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the embodiment of the present application also provides a model design device, and the model design method applied to the model design device can be executed by a model design device, and the model design device can be implemented by software and/or hardware and integrated in the model design device.
  • the model design device can be a mobile device such as a mobile phone, a notebook, a tablet computer, etc. that can communicate with the network side.
  • FIG. 5 is a schematic diagram of the hardware structure of a model design device provided in an embodiment of the present application.
  • the model design device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005.
  • the communication bus 1002 is used to realize the connection and communication between these components.
  • the user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface.
  • the network interface 1004 may include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, WI-FI) interface).
  • the memory 1005 may be a high-speed random access memory (Random Access Memory, RAM) or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk storage.
  • RAM Random Access Memory
  • NVM Non-Volatile Memory
  • the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
  • the structure shown in FIG5 does not constitute a limitation on the model design device, and may include more or fewer components than shown, or combine certain components, or arrange components differently.
  • the memory 1005 as a storage medium may include an operating system, a data storage module, a network communication module, a user interface module, and a computer program.
  • the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the model design device, and the model design device calls the computer program stored in the memory 1005 through the processor 1001, and executes the model design method applied to the model design device provided in any of the above embodiments.
  • model design device proposed in this embodiment and the model design method applied to the model design device proposed in the above embodiment belong to the same inventive concept.
  • the technical details not fully described in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as executing the model design method.
  • an embodiment of the present application also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the model design method provided in any of the above embodiments is implemented.
  • computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data).
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

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Abstract

本申请实施例公开了一种模型设计方法、装置、设备及计算机可读存储介质，属于集成电路技术领域。该模型设计方法包括：基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各环形振荡器的基本结构不同；基于器件模型进行仿真验证以得到模型仿真结果；若模型仿真结果符合预设标准，则基于器件模型进行流片以得到包括各环形振荡器的实际芯片；基于实际芯片进行硬件测试以得到硬件测试结果；基于硬件测试结果和模型仿真结果迭代优化器件模型。

Description

模型设计方法、装置、设备及计算机可读存储介质
相关申请
本申请要求于2022年10月11号申请的、申请号为202211263584.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及集成电路技术领域，尤其涉及模型设计方法、装置、设备及计算机可读存储介质。
背景技术
随着集成电路朝着更高密度、更小尺寸的方向发展，其对器件模型准确度以及工艺水平要求也越发严格。
目前，环形振荡器(RO，Ring Oscillator)经常被用于设计与工艺协同优化(Design Technology Co-Optimization，DTCO)研究，其结果可以应用于器件结构优化、电路设计裕度的收紧和S2S(Spice to Silicon，模型和测试数据)的校准，最终实现设计上的PPAC(Power Performance Area Cost，功耗、性能、面积和成本)收益。
现有的环形振荡器设计方案提供的器件模型中一般只包括了一种环形振荡器的设计方式，而随着先进工艺的导入，这种单一的器件模型往往不能全部覆盖设计使用要求；此外，这些方案的仿真结果与生产制造测试结果也存在一定误差，严重影响电路性能的提升。
发明内容
本申请实施例的主要目的在于提供一种模型设计方法、装置、设备及计算机可读存储介质，旨在促进模型仿真与实际生产制造相融合，最终实现覆盖面广、可制造性强、可靠性高、精度高的环形振荡器。
为实现上述目的，本申请实施例提供一种模型设计方法，所述方法包括：
基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各所述环形振荡器的基本结构不同；
基于所述器件模型进行仿真验证以得到模型仿真结果；
若所述模型仿真结果符合预设标准，则基于所述器件模型进行流片以得到包括各所述环形振荡器的实际芯片；
基于所述实际芯片进行硬件测试以得到硬件测试结果；
基于所述硬件测试结果和所述模型仿真结果迭代优化所述器件模型。
此外，为实现上述目的，本申请实施例还提供一种模型设计装置，所述模型设计装置包括：
模型设计模块，设置为基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各所述环形振荡器的基本结构不同；
仿真验证模块，设置为基于所述器件模型进行仿真验证以得到模型仿真结果；
试生产模块，设置为若所述模型仿真结果符合预设标准，则基于所述器件模型进行流片以得到包括各所述环形振荡器的实际芯片；
硬件测试模块，设置为基于所述实际芯片进行硬件测试以得到硬件测试结果；
迭代优化模块，设置为基于所述硬件测试结果和所述模型仿真结果迭代优化所述器件模型。
此外，为实现上述目的，本申请实施例还提供一种模型设计设备，所述模型设计设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述计算机程序被所述处理器执行时实现如上所述的模型设计方法。
此外，为实现上述目的，本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如上所述的模型设计方法。
本申请实施例提出一种模型设计方法、装置、设备及计算机可读存储介质，在该模型设计方法中，基于预设的工艺库模型设计了包含多种环形振荡 器的器件模型，各所述环形振荡器的基本结构不同，克服了现有技术中的器件模型不能全部覆盖设计使用要求的技术缺陷，显著地拓展了器件模型的适用场景，且该器件模型是通过数字PR(Place and Route，布局与布线)手段进行的电路设计，电路布线由软件自动生成，使得设计电路能够更贴近数字设计环境，让测试芯片结果更贴近实际数字电路结果，加强了实验电路和数字电路的耦合；本申请实施例通过对所述器件模型进行仿真验证，并将环形振荡器的模型仿真结果与实际流片测试结果进行对比，通过分析对比结果，实现了器件模型的迭代优化，确保器件模型与生产制造结果趋于一致，促进了模型仿真与实际生产制造过程相融合，能够持续提升电路性能，最终实现覆盖面广、可制造性强、可靠性高、精度高的环形振荡器。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请实施例的一部分，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的一种模型设计方法的流程示意图；
图2为本申请一实施例提供的一种模型设计方法设计的不同结构的晶体管版图设计示意图；
图3为本申请一实施例提供的一种模型设计方法涉及的环形振荡器版图设计示意图；
图4为本申请一实施例提供的一种模型设计装置的结构示意图；
图5为本申请一实施例提供的一种模型设计设备的硬件结构示意图。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请实施例。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请实施例的描述。
需要说明的是，虽然在流程图中示出了逻辑顺序，但是在某些情况下， 可以以不同于流程图中的顺序执行所示出或描述的步骤。说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
还应当理解，在本申请实施例说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请实施例的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
在数字IC(Integrated Circuit Chip，集成电路芯片)设计中，先进工艺的设计裕度问题变得越来越突出。目前，环形振荡器(RO，Ring Oscillator)经常被用于设计与工艺协同优化研究，其结果可以应用于器件结构优化、电路设计裕度的收紧和S2S的校准，最终实现设计上的PPAC收益。现有的环形振荡器设计方案提供的器件模型中一般只包括了一种环形振荡器的设计方式，而随着先进工艺的导入，这种单一的器件模型往往不能全部覆盖设计使用要求；此外，这些方案的仿真结果与生产制造测试结果也存在一定误差，严重影响电路性能的提升。
基于此，本申请实施例提供了一种模型设计方法、装置、设备及计算机可读存储介质，基于预设的工艺库模型设计了包含多种环形振荡器的器件模型，各环形振荡器的基本结构不同，克服了现有技术中的器件模型不能全部覆盖设计使用要求的技术缺陷，显著地拓展了器件模型的适用场景，且该器件模型是通过数字布局与布线手段进行的电路设计，电路布线由软件自动生成，使得设计电路能够更贴近数字设计环境，让测试芯片结果更贴近实际数字电路结果，加强了实验电路和数字电路的耦合；本申请实施例通过对器件模型进行仿真验证，并将环形振荡器的模型仿真结果与实际流片测试结果进行对比，通过分析对比结果，实现了器件模型的迭代优化，确保器件模型与生产制造结果趋于一致，促进了模型仿真与实际生产制造过程相融合，能够 持续提升电路性能，最终实现覆盖面广、可制造性强、可靠性高、精度高的环形振荡器。
本申请实施例提供的模型设计方法、装置、设备及计算机可读存储介质，具体通过如下实施例进行说明，首先描述本申请实施例中的模型设计方法。
参照图1，图1为本申请一实施例提供的一种模型设计方法的流程示意图，该模型设计方法可以应用于模型设计设备，如图1所示，本实施例提供的模型设计方法包括步骤S10至S50。
步骤S10，基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各环形振荡器的基本结构不同；
需要说明的是，预设的工艺库模型来自于工艺厂，本实施例在进行环形振荡器的电路仿真设计之前，需要先导入由工艺厂提供的工艺库模型，并基于该工艺库模型根据环形振荡器中门电路种类、以及输入通路的不同将环形振荡器设计为多种基本结构，每一基本结构的环形振荡器由奇数级(例如201级)的反相逻辑门组成，其中，反相逻辑门可以是NAND与非门、INV求逆矩阵或NOR或非门；本实施例中，通过数字PR手段实现器件模型中各环形振荡器的电路结构设计，通过寄存器和选择器实现具体链路的选择，从而满足不同使用需求；通过调换输入端口的方式，实现不同Type(类型)链路的设计，进一步基于先进制程的要求，分别考虑FIN(鳍状物)、NF(Finger Number，栅指数量)、POWER(电力，功率，性能)等因素对环形振荡器的影响，确保设计覆盖常见标准单元；采用相邻布局、整体镜像和S型排布等方式实现版图，达到节省器件空间和减小电源布线的目的，实现PPAC收益最大化。
步骤S20，基于器件模型进行仿真验证以得到模型仿真结果；
在完成器件模型的构建之后，本实施例会对该器件模型进行验证和后仿真，根据验证和后仿真结果确认该器件模型是否符合设计要求。
步骤S30，若模型仿真结果符合预设标准，则基于器件模型进行流片以得到包括各环形振荡器的实际芯片；
预设标准可以是工艺厂给定的设计标准，也可以是在设计者在给定的设计标准的基础上进行调整后得到的设计要求，在器件模型中的各个环形振荡 器的版图都符合设计要求的情况下，就可以将设计生成的GDSII(一个数据库文件格式，用于集成电路版图的数据转换)交由工艺厂进行流片，并获取工艺厂基于GDSII流片得到的芯片，该芯片中包括器件模型中的多路环形振荡器。
此外，若模型仿真结果不符合预设标准，则无需进行后续的流片步骤，而需要基于模型仿真结果重新进行器件模型的电路和版图设计。
步骤S40，基于实际芯片进行硬件测试以得到硬件测试结果；
本实施例中，通过外接电源给芯片中的某一路RO(Ring Oscillator，环形振荡器)上电，且电源的参数设置为器件模型中相应的环形振荡器的设计值，通过芯片的输出端口读取输出数据(例如输出电流、频率或相位噪声等)，然后更换其他路RO进行相同的操作，直至测试完芯片中的所有RO，即可将从芯片的输出端口读取到的所有测试数据作为硬件测试结果。
步骤S50，基于硬件测试结果和模型仿真结果迭代优化器件模型。
本实施例中，通过对比模型仿真结果和实物芯片关键测试点的测试结果，并进行数据分析，当模型仿真结果与实际测试结果误差大于阈值时，通过调整模型参数对器件模型改进，直到模型仿真结果与实际测试误差小于设定值，此时认为所设计的环形振荡器模型在实际先进工艺下达到预期目标，能够应用于实际生产。通过反复分析模型仿真结果与实际测试结果的方式，实现器件模型的迭代和优化，从而促进模型仿真与实际制造相一致，促进设计性能及良率提升。
振荡器是作为时钟产生电路的核心模块，其自身性能很大程度的影响了整个时钟产生电路的性能。CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)振荡器的实现结构往往集中在LC(电感L、电容C)振荡器和环形振荡器两种，而环形振荡器主要由若干个延迟单元级联组成，当某一单元的输出信号经过整个环路并回到该单元的输入时，信号翻转，使得电路产生了周期性的振荡信号，由于环形振荡器没有高品质的滤波器，因此相位噪声受PVT(process，voltage，temperature，工艺，电压，温度)的影响十分大。本实施例基于环形振荡器的这一特点，仿真并流片出基于TSMC(台积电，台湾积体电路制造股份有限公司)先进制程的由奇数级(例如201个，也可以根据电路的实际需要改为其他奇数值)反相门电路构成不同种类 的环形振荡器，并用于工艺库模型的校验。
本实施例提出一种模型设计方法，基于预设的工艺库模型设计了包含多种环形振荡器的器件模型，各环形振荡器的基本结构不同，克服了现有技术中的器件模型不能全部覆盖设计使用要求的技术缺陷，显著地拓展了器件模型的适用场景，且该器件模型是通过数字布局与布线手段进行的电路设计，电路布线由软件自动生成，使得设计电路能够更贴近数字设计环境，让测试芯片结果更贴近实际数字电路结果，加强了实验电路和数字电路的耦合；本申请实施例通过对器件模型进行仿真验证，并将环形振荡器的模型仿真结果与实际流片测试结果进行对比，通过分析对比结果，实现了器件模型的迭代优化，确保器件模型与生产制造结果趋于一致，促进了模型仿真与实际生产制造过程相融合，能够持续提升电路性能，最终实现覆盖面广、可制造性强、可靠性高、精度高的环形振荡器。
在一些可行的实施例中，步骤S10中基于预设的工艺库模型设计包含多种环形振荡器的器件模型的步骤可以包括但不限于以下步骤：
步骤S11，基于预设的工艺库模型设计多种环形振荡器，各环形振荡器的基本结构不同；
步骤S12，基于各环形振荡器分别进行拓展以得到多种设计方式；
步骤S13，基于各设计方式例化多个待验证单元，各待验证单元对应一种环形振荡器；
步骤S14，基于各待验证单元生成包含多种环形振荡器的器件模型。
在一些可行的实施例中，各环形振荡器包括多种元器件，步骤S12可以包括但不限于以下步骤：
步骤S121，改变各元器件的类型和数量，并将改变后的各元器件重新组合，以得到覆盖预设标准单元库的多种设计方式。
本实施例中，根据门电路类型(非门、与非门1、与非门2、或非门1、或非门2)和先进制程下FinFET(Fin Field-Effect Transistor，鳍式场效应晶体管)结构里Finger的数量、MOS管Vt(Threshold Voltage，阈值电压)大小将环形振荡器分为若干种，这些振荡器单元几乎能覆盖常见的标准单元类型；各环形振荡器的基本结构可以包括但不限于分别使用NAND+INV、NAND、以及INV+NOR进行环形振荡器链路的设计，考虑NAND和NOR在实际工 艺中的不对称性，通过调换输入端口的方式实现不同场景的覆盖，因此共设计多种基本结构(Type)的环形振荡器链路；除了单栅极结构的晶体管外，本实施例还引入多栅指结构，台积电先进制程可以根据需求定制栅极和鳍片(FIN)数量，本实施例引入多栅指结构以模拟不同栅数量下的仿真情况，多栅指结构器件通过增加栅极的个数来增强控制电流的能力，参照图2，图2分别示出了FIN＝2与NF＝1、2、4的三种不同结构的晶体管版图，Metal即金属材料，Poly即多晶硅材料，G、D、S分别对应栅极、漏极、源极；本实施例将阈值电压Vt设计成ULVT(Ultra-Low Voltage Threshold，超低阈值电压)、SVT(Standard Value Threshold，标准值阈值)、LVT(Low Voltage Threshold，低阈值)、ELVT(Extra-Low Voltage Threshold，超低阈值电压)、LVTLL、ULVTLL等多种类型，因此共有复数种环形振荡器；将每一个振荡器例化为一个模块(即待验证单元)，例如将每个RO单独例化为一个Cell(单元)并命名，在FIN等于2的情况下，定义RO_FIN2_NFx_TYPEy_VTz为RO名称，其中x，y，z需替换为实际使用器件Finger Number，电路类型，Vt类型。Cell的输入pin定义为IN_FIN2_NFx_TYPEy_VTz，其中x，y，z需替换为实际使用器件Finger Number，电路类型，Vt类型。各链路中，Cell的输入信号分别为A1和A2。ZN_FIN2_NFx_TYPEy_VTz为输出pin定义，其中x，y，z需替换为实际使用器件Finger Number，电路类型，Vt类型；通过对Type、Fin、NF、Vt的组合，共构成多种设计方式，从而覆盖后端设置中的常见标准单元。需要注意的是，在本实施例提供的多种设计方式的基础上，通过调整链路种类、逻辑门个数、Fin、NF以及Vt以实现环形振荡器优化的技术方案均应该包含在本实施例的保护范围之内。
在一些可行的实施例中，步骤S14可以包括但不限于以下步骤：
基于各待验证单元进行版图设计以得到多种环形振荡器版图；
基于各环形振荡器版图生成包含多种环形振荡器的器件模型。
本实施例中，对完成链路设计的环形振荡器进行版图设计，参照图3，每个RO的排布方式可以如图3所示。其中，逻辑门以S型排布，从而确保版图设计上的宽长比合理性。示例性地，在200个逻辑门排布时，第一排横向放置50个逻辑门，第二排采用镜像的方式放置50个逻辑门，随后将上述100个逻辑门进行镜像，得到最终的排布方式，此时起点和终点位于同一侧(如 图3所示的版图设计，起点在第一排右侧，终点在第四排右侧)，形成一个环，达到节省器件空间和减小电源布线的目的。版图设计过程中，保持纵向AA(Active area，有源区面积)space与Device AA space一致，进一步减小后续器件空间使用，实现PPAC收益最大化。此外，其他RO同样以上述方式进行布局，并以纵向或者横向进行整个器件模型的版图排布。
在一些可行的实施例中，步骤S20可以包括但不限于以下步骤：
步骤S201，对各待验证单元进行仿真验证以得到模型仿真结果。
在进行仿真验证时，需要对器件模型中的每一个Cell中的环形振荡器进行仿真测试并读取各环形振荡器的输出数据，将器件模型中所有的待验证单元的测试数据作为模型仿真结果。
在一些可行的实施例中，步骤S50可以包括但不限于以下步骤：
步骤S501，若硬件测试结果和模型仿真结果之间的误差大于预设阈值，则调整模型参数对器件模型进行改进，并基于改进后的器件模型返回执行基于器件模型进行仿真验证以得到模型仿真结果的步骤，直至新的硬件测试结果和模型仿真结果之间的误差小于预设阈值。
预设阈值可以由工艺厂指定或设计者适当调整，当模型仿真结果与实际测试结果误差大于预设阈值时，通过调整模型参数对器件模型改进，直到模型仿真结果与实际测试误差小于设定值，此时认为所设计的环形振荡器模型在实际先进工艺下达到预期目标，能够应用于实际生产，本实施例通过反复分析模型仿真结果与实际测试结果的方式，可以实现器件模型优化的迭代，从而促进模型仿真与实际制造相一致，促进设计性能及良率提升。
在一些可行的实施例中，步骤S50之后，模型设计方法还可以包括但不限于以下步骤：
步骤A，若硬件测试结果和模型仿真结果之间的误差小于预设阈值，则将器件模型设定为量产模型。
若模型仿真结果与实际测试误差小于设定值，则认为所设计的环形振荡器模型在实际先进工艺下达到预期目标，能够应用于实际生产。
此外，本申请实施例还提供一种模型设计装置，参照图4，图4为本申请一实施例提供的一种模型设计装置的结构示意图，如图4所示，本实施例中， 模型设计装置包括：模型设计模块100、仿真验证模块200、试生产模块300、硬件测试模块400和迭代优化模块500。
模型设计模块100，设置为基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各环形振荡器的基本结构不同；
仿真验证模块200，设置为基于器件模型进行仿真验证以得到模型仿真结果；
试生产模块300，设置为若模型仿真结果符合预设标准，则基于器件模型进行流片以得到包括各环形振荡器的实际芯片；
硬件测试模块400，设置为基于实际芯片进行硬件测试以得到硬件测试结果；
迭代优化模块500，设置为基于硬件测试结果和模型仿真结果迭代优化器件模型。
本实施例提出一种模型设计装置，基于预设的工艺库模型设计了包含多种环形振荡器的器件模型，各环形振荡器的基本结构不同，克服了现有技术中的器件模型不能全部覆盖设计使用要求的技术缺陷，显著地拓展了器件模型的适用场景，且该器件模型是通过数字布局与布线手段进行的电路设计，电路布线由软件自动生成，使得设计电路能够更贴近数字设计环境，让测试芯片结果更贴近实际数字电路结果，加强了实验电路和数字电路的耦合；本申请实施例通过对器件模型进行仿真验证，并将环形振荡器的模型仿真结果与实际流片测试结果进行对比，通过分析对比结果，实现了器件模型的迭代优化，确保器件模型与生产制造结果趋于一致，促进了模型仿真与实际生产制造过程相融合，能够持续提升电路性能，最终实现覆盖面广、可制造性强、可靠性高、精度高的环形振荡器。
本实施例提供的模型设计装置与上述实施例提供的模型设计方法属于同一发明构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行模型设计方法相同的有益效果。
以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
此外，本申请实施例还提供一种模型设计设备，上述应用于模型设计设备的模型设计方法可以由模型设计装置执行，该模型设计装置可以通过软件和/或硬件的方式实现，并集成在模型设计设备中。模型设计设备可以为手机、笔记本、平板电脑等可与网络侧通信的移动设备。
参照图5，图5为本申请一实施例提供的一种模型设计设备的硬件结构示意图。如图5所示，模型设计设备可以包括：处理器1001，例如中央处理器(Central Processing Unit，CPU)，通信总线1002、用户接口1003，网络接口1004，存储器1005。其中，通信总线1002用于实现这些组件之间的连接通信。用户接口1003可以包括显示屏(Display)、输入单元比如键盘(Keyboard)，用户接口1003还可以包括标准的有线接口、无线接口。网络接口1004可以包括标准的有线接口、无线接口(如无线保真(Wireless-Fidelity，WI-FI)接口)。存储器1005可以是高速的随机存取存储器(Random Access Memory，RAM)，也可以是稳定的非易失性存储器(Non-Volatile Memory，NVM)，例如磁盘存储器。存储器1005还可以是独立于前述处理器1001的存储设备。
本领域技术人员可以理解，图5中示出的结构并不构成对模型设计设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。如图5所示，作为一种存储介质的存储器1005中可以包括操作系统、数据存储模块、网络通信模块、用户接口模块以及计算机程序。
在图5所示的模型设计设备中，网络接口1004主要用于与其他设备进行数据通信；用户接口1003主要用于与用户进行数据交互；本实施例中的处理器1001、存储器1005可以设置在模型设计设备中，模型设计设备通过处理器1001调用存储器1005中存储的计算机程序，并执行上述任一实施例提供的应用于模型设计设备的模型设计方法。
本实施例提出的模型设计设备与上述实施例提出的应用于模型设计设备的模型设计方法属于同一发明构思，未在本实施例中详尽描述的技术细节可参见上述任意实施例，并且本实施例具备与执行模型设计方法相同的有益效果。
此外，本申请实施例还提供一种计算机可读存储介质，该计算机可读存储介质可以为非易失性计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器执行时实现上述任一实施例提供的模型设计方法。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统可以被实施为软件、固件、硬件及其适当的组合。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上是对本申请实施例的较佳实施进行了具体说明，但本申请实施例并不局限于上述实施方式，熟悉本领域的技术人员在不违背本申请实施例精神的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请实施例权利要求所限定的范围内。

Claims (10)

  1. 一种模型设计方法，包括：
    基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各所述环形振荡器的基本结构不同；
    基于所述器件模型进行仿真验证以得到模型仿真结果；
    若所述模型仿真结果符合预设标准，则基于所述器件模型进行流片以得到包括各所述环形振荡器的实际芯片；
    基于所述实际芯片进行硬件测试以得到硬件测试结果；
    基于所述硬件测试结果和所述模型仿真结果迭代优化所述器件模型。
  2. 如权利要求1所述的模型设计方法，其中，所述基于预设的工艺库模型设计包含多种环形振荡器的器件模型的步骤，包括：
    基于预设的工艺库模型设计多种环形振荡器，各所述环形振荡器的基本结构不同；
    基于各所述环形振荡器分别进行拓展以得到多种设计方式；
    基于各所述设计方式例化多个待验证单元，各所述待验证单元对应一种环形振荡器；
    基于各所述待验证单元生成包含多种环形振荡器的器件模型。
  3. 如权利要求2所述的模型设计方法，其中，各所述环形振荡器包括多种元器件，所述基于各所述环形振荡器分别进行拓展以得到多种设计方式的步骤，包括：
    改变各所述元器件的类型和数量，并将改变后的各所述元器件重新组合，以得到覆盖预设标准单元库的多种设计方式。
  4. 如权利要求2所述的模型设计方法，其中，所述基于所述器件模型进行仿真验证以得到模型仿真结果的步骤，包括：
    对各所述待验证单元进行仿真验证以得到模型仿真结果。
  5. 如权利要求2所述的模型设计方法，其中，所述基于各所述待验证单元生成包含多种环形振荡器的器件模型的步骤，包括：
    基于各所述待验证单元进行版图设计以得到多种环形振荡器版图；
    基于各所述环形振荡器版图生成包含多种环形振荡器的器件模型。
  6. 如权利要求1至5中任一项所述的模型设计方法，其中，所述基于所述硬件测试结果和所述模型仿真结果迭代优化所述器件模型的步骤，包括：
    若所述硬件测试结果和所述模型仿真结果之间的误差大于预设阈值，则调整模型参数对所述器件模型进行改进，并基于改进后的器件模型返回执行所述基于所述器件模型进行仿真验证以得到模型仿真结果的步骤，直至新的硬件测试结果和模型仿真结果之间的误差小于所述预设阈值。
  7. 如权利要求6所述的模型设计方法，其中，所述基于所述硬件测试结果和所述模型仿真结果迭代优化所述器件模型的步骤之后，所述模型设计方法还包括：
    若所述硬件测试结果和所述模型仿真结果之间的误差小于预设阈值，则将所述器件模型设定为量产模型。
  8. 一种模型设计装置，包括：
    模型设计模块，设置为基于预设的工艺库模型设计包含多种环形振荡器的器件模型，各所述环形振荡器的基本结构不同；
    仿真验证模块，设置为基于所述器件模型进行仿真验证以得到模型仿真结果；
    试生产模块，设置为若所述模型仿真结果符合预设标准，则基于所述器件模型进行流片以得到包括各所述环形振荡器的实际芯片；
    硬件测试模块，设置为基于所述实际芯片进行硬件测试以得到硬件测试结果；
    迭代优化模块，设置为基于所述硬件测试结果和所述模型仿真结果迭代优化所述器件模型。
  9. 一种模型设计设备，其中，所述模型设计设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述计算机程序被所述处理器执行时实现如权利要求1至7中任一项所述的模型设计方法。
  10. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至7中任一项所述的模型设计方法。
PCT/CN2023/086003 2022-10-11 2023-04-03 模型设计方法、装置、设备及计算机可读存储介质 WO2024077892A1 (zh)

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