WO2024077890A1 - 一种异步fifo读写控制方法、系统及电子设备 - Google Patents

一种异步fifo读写控制方法、系统及电子设备 Download PDF

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Publication number
WO2024077890A1
WO2024077890A1 PCT/CN2023/085935 CN2023085935W WO2024077890A1 WO 2024077890 A1 WO2024077890 A1 WO 2024077890A1 CN 2023085935 W CN2023085935 W CN 2023085935W WO 2024077890 A1 WO2024077890 A1 WO 2024077890A1
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fifo
fifo queue
data
read
queue
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PCT/CN2023/085935
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English (en)
French (fr)
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刘伟
卢圣才
王洪良
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浪潮电子信息产业股份有限公司
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Publication of WO2024077890A1 publication Critical patent/WO2024077890A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Definitions

  • the present application relates to the technical field of data reading and writing, and in particular to an asynchronous FIFO reading and writing control method, system and electronic device.
  • the purpose of the present application is to provide an asynchronous FIFO read and write control method, system and electronic device, which can effectively control the dual FIFO ping-pong cache read and write during the interface bridging process, and realize asynchronous cache processing of variable packet length data.
  • the present application provides an asynchronous FIFO read and write control method, which is applied to a processor having a front-end interface and a back-end interface, comprising:
  • the data is ping-pong read from the first FIFO queue and the second FIFO queue using the empty threshold and the minimum time interval, so as to output the read data through the back-end interface.
  • the method before ping-pong writing the valid video data into the first FIFO queue and the second FIFO queue, the method further includes:
  • determining the empty thresholds of the first FIFO queue and the second FIFO queue according to the length of the data packet includes:
  • the emptying thresholds of the first FIFO queue and the second FIFO queue are calculated according to the packet length and the queue depth; wherein the packet length is positively correlated with the emptying threshold, and the queue depth is positively correlated with the emptying threshold.
  • the process proceeds to a step of determining whether the empty threshold is updated to the first FIFO queue and the second FIFO queue.
  • using an empty threshold and a minimum time interval to ping-pong read data from a first FIFO queue and a second FIFO queue includes:
  • empty threshold to set an empty flag; wherein the empty flag is used to describe whether the data in the first FIFO queue and the second FIFO queue is less than a preset amount;
  • the delayed done signal is set using the minimum time interval; wherein the delayed done signal is used to describe whether the delayed waiting is completed;
  • a data ping-pong reading operation is performed on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal.
  • using the empty threshold to set the empty flag includes:
  • the delay done signal is set using the minimum time interval, including:
  • the delayed done signal is set to 1.
  • the process further includes:
  • performing a data ping-pong reading operation on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal includes:
  • the empty flag is set to 0 and the delayed done signal is set to 1; wherein, the empty flag is set to 0 to indicate that the data in the first FIFO queue and the second FIFO queue is less than or equal to a preset amount, and the delayed done signal is set to 1 to indicate that the delay between the two read operations is completed;
  • the present application also provides an asynchronous FIFO read-write control system, which is applied to a processor having a front-end interface and a back-end interface, including:
  • the parsing module is used to parse the data received by the front-end interface to obtain the data packet length and valid video data;
  • a threshold setting module used to determine the empty threshold of the first FIFO queue and the second FIFO queue according to the length of the data packet
  • a write control module used for ping-pong writing valid video data into the first FIFO queue and the second FIFO queue
  • a delay control module is used to determine the minimum time interval for reading the FIFO according to the sending timing of the back-end interface
  • the read control module is used to ping-pong read data from the first FIFO queue and the second FIFO queue by using an empty threshold and a minimum time interval, so as to output the read data through a back-end interface.
  • the processor is an FPGA chip
  • the front-end interface is a hard-core MIPI D-PHY interface or a soft-core MIPI D-PHY interface constructed by the FPGA chip
  • the back-end interface is a hard-core MIPI D-PHY interface or a soft-core MIPI D-PHY interface built on the FPGA chip.
  • the processor includes at least two back-end interfaces.
  • queue parameters of the first FIFO queue and the second FIFO queue are the same; wherein the queue parameters include queue depth and bit width.
  • the present application also provides an electronic device, comprising a processor having a front-end interface and a back-end interface;
  • the processor is used to parse the data received by the front-end interface to obtain the data packet length and valid video data; it is also used to determine the empty threshold of the first FIFO queue and the second FIFO queue according to the data packet length, and ping-pong write the valid video data into the first FIFO queue and the second FIFO queue; it is also used to determine the minimum time interval for reading the FIFO according to the sending timing of the back-end interface; it is also used to ping-pong read data from the first FIFO queue and the second FIFO queue using the empty threshold and the minimum time interval, so as to output the read data through the back-end interface.
  • the electronic device includes a VR helmet, a server or a mobile set-top box.
  • the present application provides an asynchronous FIFO read and write control method, which is applied to a processor with a front-end interface and a back-end interface, comprising: parsing data received by the front-end interface to obtain a data packet length and valid video data; determining an empty threshold of a first FIFO queue and a second FIFO queue according to the data packet length, and ping-pong-writing the valid video data into the first FIFO queue and the second FIFO queue; determining a minimum time interval for reading the FIFO according to the sending timing of the back-end interface; and ping-pong-reading data from the first FIFO queue and the second FIFO queue using the empty threshold and the minimum time interval, so as to output the read data through the back-end interface.
  • the present application is applied to a processor with a built-in front-end interface and a back-end.
  • the processor determines the length of the data packet and the valid video data according to the data transmitted by the front-end interface, sets the empty threshold of the FIFO queue according to the length of the data packet, and determines the minimum time interval between two adjacent FIFO reads according to the sending timing of the back-end interface.
  • the present application ping-pongs the valid video data into the first FIFO queue and the second FIFO queue, and also ping-pongs the first FIFO queue and the second FIFO queue based on the empty threshold and the minimum time interval, so that the back-end interface outputs the read data.
  • the present application dynamically sets the empty threshold of the FIFO according to the data packet length corresponding to the front-end interface, and sets a fixed delay between two FIFO reads according to the sending timing of the back-end interface.
  • the above method can effectively control the reading and writing of the dual FIFO ping-pong cache during the interface bridging process, and realizes asynchronous cache processing of variable packet length data.
  • the present application also provides an asynchronous FIFO read-write control system and an electronic device, which have the above-mentioned beneficial effects and are not repeated here.
  • FIG1 is a flow chart of an asynchronous FIFO read/write control method provided by an embodiment of the present application
  • FIG2 is a schematic diagram of a variable packet length asynchronous FIFO read control processing principle provided by an embodiment of the present application
  • FIG3 is a timing diagram of a variable packet length asynchronous FIFO read/write control provided by an embodiment of the present application
  • FIG4 is a schematic diagram of the structure of an asynchronous FIFO read-write control system provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a non-volatile readable storage medium provided in an embodiment of the present application.
  • Figure 1 is a flow chart of an asynchronous FIFO read and write control method provided in an embodiment of the present application.
  • S101 parsing the data received by the front-end interface to obtain the data packet length and valid video data
  • some embodiments of the present application can be applied to a processor having a front-end interface and a back-end interface.
  • the processor includes one front-end interface and one back-end interface, one-input-one-output bridging can be implemented; when the processor includes one front-end interface and multiple back-end interfaces, one-input-multiple-output bridging can be implemented; when the processor includes multiple front-end interfaces and one back-end interface, multiple-input-one-output bridging can be implemented.
  • the processor can obtain the data packet length and valid video data by parsing the data received by the above-mentioned front-end interface.
  • the above-mentioned valid data refers to the data received by the front-end interface except the packet header and the packet tail.
  • the data packet length refers to the byte length of the valid video data.
  • the processor can be a FPGA (Field-Programmable Gate Array) chip
  • the front-end interface can be a front-end MIPI D-PHY (Mobile Industry Processor Interface D-PHY, one of the mobile industry processor interface protocols) interface
  • the back-end interface can be a back-end MIPI D-PHY interface. Therefore, S101 can be implemented in the following way: parsing the COMMAND data received by the front-end MIPI D-PHY interface to obtain the data packet length and valid video data.
  • the above process uses a programmable logic device FPGA to implement the MIPI DSI bridge.
  • the MIPI receiving end video needs to be cached, then read out from the cache, and finally sent out through the MIPI sending end according to a certain MIPI protocol.
  • the link layer of MIPI DSI has two modes: command mode (COMMAND MODE) and video mode (VIDEO MODE).
  • the video mode provides a continuous clock
  • the output end can use the CLK clock of the input end
  • the cache can be designed as a synchronous FIFO (First Input First Output) queue
  • the command mode provides a discontinuous clock
  • the output end clock can only use an asynchronous clock.
  • the cache must be designed as an asynchronous FIFO.
  • the COMMAND data in some embodiments of the present application refers to the video data in the command mode.
  • the FPGA can receive the COMMAND data through the front-end MIPI D-PHY interface, and the data packet length and valid video data can be obtained by parsing the above COMMAND data.
  • the above valid data refers to the data in the COMMAND data except the header and the tail, and the data packet length refers to the byte length of the valid video data.
  • S102 determining empty thresholds of the first FIFO queue and the second FIFO queue according to the length of the data packet, and ping-pong-writing the valid video data into the first FIFO queue and the second FIFO queue;
  • the operation of the first FIFO queue and the second FIFO queue can also be set before this step, and the first FIFO queue and the second FIFO queue have the same depth and bit width.
  • some embodiments of the present application can determine the empty threshold of the first FIFO queue and the second FIFO queue according to the length of the data packet, and the first FIFO queue and the second FIFO queue have the same empty threshold.
  • the empty threshold is aempty_cnt.
  • the empty signal is valid (aempty is 1), and the empty signal is transmitted to the downstream module B, notifying the downstream module to stop reading data, and preventing the situation where the read data operation is still generated when there is no valid data in the FIFO queue.
  • some embodiments of the present application can pre-set the corresponding relationship between the length interval and the empty threshold, and determine the empty threshold corresponding to the data packet length based on the corresponding relationship.
  • Some embodiments of the present application may first perform a lane (channel) sequential reorganization operation on the valid video data, and then The valid video data reorganized in sequence is ping-pong written into the first FIFO queue and the second FIFO queue.
  • S103 Determine the minimum time interval for reading the FIFO according to the sending timing of the back-end interface
  • the processor may also query the sending timing of the back-end interface, which refers to the timing of sending video data. After obtaining the sending timing, the minimum time interval required for two FIFO reads is calculated based on the sending timing.
  • S104 Ping-pong reading of data from the first FIFO queue and the second FIFO queue using the empty threshold and the minimum time interval, so as to output the read data through the backend interface.
  • the empty threshold and the minimum time interval can be used to perform data ping-pong reading operations.
  • the data in the first FIFO queue is less than the empty threshold, stop reading the first FIFO queue, and when the data in the second FIFO queue is less than the empty threshold, stop reading the second FIFO queue. If the time interval between the current time and the completion time of the last read operation is less than the minimum time interval, the next read operation will not be performed; if the time interval between the current time and the completion time of the last read operation is greater than or equal to the minimum time interval, the next read operation can be performed.
  • the data can be encapsulated and the encapsulated data can be transmitted to the back-end interface so that the back-end interface outputs the read data.
  • Some embodiments of the present application are applied to a processor with a built-in front-end interface and a back-end.
  • the processor determines the length of the data packet and the valid video data according to the data transmitted by the front-end interface, sets the empty threshold of the FIFO queue according to the length of the data packet, and determines the minimum time interval between two adjacent read FIFOs according to the sending timing of the back-end interface.
  • Some embodiments of the present application ping-pong write the valid video data into the first FIFO queue and the second FIFO queue, and also ping-pong read the first FIFO queue and the second FIFO queue based on the empty threshold and the minimum time interval, so that the back-end interface outputs the read data.
  • Some embodiments of the present application dynamically set the empty threshold of the FIFO according to the data packet length corresponding to the front-end interface, and set a fixed delay between two read FIFOs according to the sending timing of the back-end interface.
  • the above method can effectively control the reading and writing of the dual FIFO ping-pong cache during the interface bridging process, and realize asynchronous cache processing of variable packet length data.
  • the empty threshold can be determined in the following manner: determine the queue depth of the first FIFO queue or the second FIFO queue, and calculate the empty threshold of the first FIFO queue and the second FIFO queue based on the data packet length and the queue depth; wherein the data packet length is positively correlated with the empty threshold, and the queue depth is positively correlated with the empty threshold.
  • some embodiments of the present application can determine the lower limit value of the target interval according to the data packet length, determine the upper limit value of the target interval according to the queue depth, and select an empty threshold within the target interval. For example, N times the data packet length can be set as the lower limit value, N ⁇ 1; M times the queue depth can also be set as the upper limit value, 0 ⁇ M ⁇ 1.
  • the empty thresholds of the first FIFO queue and the second FIFO queue may be set first, and the ping-pong write operation may be performed after the empty thresholds are set.
  • the specific process is as follows:
  • Step A1 determining the empty thresholds of the first FIFO queue and the second FIFO queue according to the length of the data packet;
  • Step A2 Update the empty threshold to the first FIFO queue and the second FIFO queue
  • Step A3 Determine whether the empty threshold is updated to the first FIFO queue and the second FIFO queue; if so, proceed to step A4; if not, proceed to step A5;
  • Step A4 Ping-pong write the valid video data into the first FIFO queue and the second FIFO queue;
  • Step A5 After delaying for a preset time, proceed to step A3.
  • data ping-pong reading can be implemented in the following manner:
  • Step B1 using the empty threshold to set the empty flag
  • the empty flag is used to describe whether the data in the first FIFO queue and the second FIFO queue is less than a preset amount.
  • the process of setting the empty flag using the empty threshold includes: determining whether the data in the first FIFO queue and the second FIFO queue is less than a preset amount; if so, setting the empty flag to 1; if not, setting the empty flag to 0.
  • Step B2 Using the minimum time interval to set the delayed done signal
  • the delayed done (end) signal is used to describe whether the delayed waiting is completed.
  • the process of setting the delayed done signal using the minimum time interval includes: when executing the current FIFO read operation, setting the delayed done signal to 0; after completing the current FIFO read operation, starting the counter; if the value of the counter is equal to the minimum time interval, setting the delayed done signal to 1. After setting the delayed done signal to 1, the value of the counter can also be cleared to allow for the next timing.
  • Step B3 performing a data ping-pong reading operation on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal.
  • Some embodiments of the present application can determine whether the empty flag is set to 0 and the delayed done signal is set to 1; wherein, setting the empty flag to 0 indicates that the data in the first FIFO queue and the second FIFO queue is less than or equal to a preset number, and the delayed done signal is 1 indicating that the delay between the two read operations is completed; if so, a data ping-pong read operation is performed on the first FIFO queue and the second FIFO queue; if not, the data ping-pong read operation is not performed.
  • the empty flag is 0 and the delayed done signal is 1, the data ping-pong read operation can be performed; if the empty flag is 0 and the delayed done signal is 0, the data ping-pong read operation is not performed; if the empty flag is 1 and the delayed done signal is 0, the data ping-pong read operation is not performed; if the empty flag is 1 and the delayed done signal is 0, the data ping-pong read operation is not performed; if the empty flag is 1 and the delayed done signal is 1, the data ping-pong read operation is not performed.
  • a corresponding empty flag may be set for the first FIFO queue and the second FIFO queue, respectively.
  • start the counter After reading data from the first FIFO queue, start the counter to start timing.
  • the delayed done signal is set to 1, determine whether the empty flag corresponding to the second FIFO queue is 0. If the empty flag is 0, read data from the second FIFO queue. If the empty flag is not 0, delay and wait to write valid video data into the second FIFO queue.
  • start the counter After reading data from the second FIFO queue, start the counter to start timing.
  • the delayed done signal When the delayed done signal is set to 1, determine whether the empty flag corresponding to the first FIFO queue is 0. If the empty flag is 0, read data from the first FIFO queue. If the empty flag is not 0, delay and wait to write valid video data into the first FIFO queue.
  • Multi-clock system drive design is becoming more and more common.
  • cross-clock domain clock data signal transmission has become a problem that must be considered.
  • the commonly used method for single-bit data transmission is to use multi-level registers to beat; the commonly used method for multi-bit data transmission is to use asynchronous FIFO. The following is an example of an actual application to illustrate the process described in the above embodiment.
  • MIPI DSI to MIPI DSI "passthrough" design also requires the provision of upgraded MIPI DSI configurations suitable for new display devices.
  • a dedicated bridge chip and the other is to use a programmable logic device FPGA with built-in MIPI D-PHY (hard core or soft core).
  • Dedicated bridge chips have relatively single functions, poor scalability, and relatively high costs. Therefore, this article mainly introduces the solution of using programmable logic devices FPGA to implement MIPI DSI bridging.
  • Some embodiments of the present application propose an asynchronous FIFO read control processing solution with variable packet length, which dynamically sets the FIFO empty threshold through front-end packet length analysis, sets a fixed delay between two FIFO reads according to the back-end MIPI send timing, and effectively avoids read-write conflicts with a certain probability through a dual FIFO ping-pong cache mechanism, thereby effectively solving the asynchronous cache processing of variable packet length data.
  • Figure 2 is a schematic diagram of a variable packet length asynchronous FIFO read control processing principle provided by an embodiment of the present application.
  • Figure 2 shows the MIPI D-PHY interface, MIPI protocol parsing and packet assembly process, dynamic FIFO threshold setting module, asynchronous FIFO read and write control module, read delay control module, MIPI send timing control process MIPI D-PHY interface, asynchronous FIFO 1 is the first FIFO queue, and asynchronous FIFO 2 is the second FIFO queue.
  • Some embodiments of the present application use FPGA as a hardware implementation unit, and design a variable packet length asynchronous FIFO cache management method, dynamically set the FIFO empty threshold according to the previous packet length information, and determine the minimum delay between two read FIFOs according to the subsequent MIPI send timing, as well as ping-pong read and write cache, which greatly facilitates the MIPI DSI bridge design scheme, effectively avoids some shortcomings caused by the use of dedicated bridge chips, and flexibly expands system functions in the later stage.
  • This implementation method can be easily transplanted on various platforms and improve the product development cycle.
  • the MIPI protocol parsing module is used to parse the length information and valid data information of the MIPI COMMAND data packet, and to reorganize the valid data in order between lanes. After the MIPI data packet length information is written into the dynamic FIFO threshold setting module, the dynamic FIFO threshold setting module calculates the FIFO empty threshold and passes it to the FIFO read and write control module to complete the dynamic update of the FIFO threshold.
  • the MIPI protocol parsing module is used to delay the parsed valid data by several clocks and write them into two FIFOs.
  • the read delay control module is used to calculate the minimum time interval required for two read FIFOs according to the back-end MIPI transmission timing and set the delay parameters.
  • the counter switch When the falling edge of the read FIFO enable is detected (a FIFO read operation is completed), the counter switch is started. When the counter value is equal to the set delay parameter, the done signal is set to 1. When the next read enable is valid, the done signal is set to 0. When the FIFO empty flag is 0 and the done signal is 1 (satisfying the delay between two read operations), the read FIFO enable is started. When the FIFO empty flag changes to 1 (the FIFO is about to be read empty), the FIFO read enable is set to 0.
  • Some embodiments of the present application receive front-end MIPI COMMAND data through the MIPI D-PHY interface (hard core or soft core) built into the FPGA, enter the MIPI protocol parsing and packet assembly module, complete the parsing of the MIPI protocol, parse the data packet length information and valid data information, and send the length information to the dynamic FIFO threshold setting module to generate the corresponding FIFO empty threshold and send it to the FIFO read-write control module to complete the setting of the FIFO empty threshold; at the same time, the effective data information is reorganized in sequence between lanes, and written into two FIFO caches in a ping-pong manner under the control of the FIFO read-write control module.
  • the read delay control module will set the corresponding read control delay according to the sending timing of the COMMAND data by the back-end MIPI D-PHY interface to ensure that the interval between two MIPI data transmissions maintains sufficient timing margin.
  • variable packet length asynchronous FIFO read control processing mainly includes the following steps:
  • Step B1 MIPI D-PHY receives the front-end MIPI COMMAND data and sends it to the MIPI protocol parsing module to complete the parsing of the MIPI data packet length and valid video data, and reorganizes the valid data in order between lanes;
  • Step B2 the data packet length information is sent to the dynamic FIFO threshold setting module, the FIFO empty threshold is calculated according to the data packet length and the FIFO depth, and finally the FIFO empty threshold is sent to the FIFO read-write control module;
  • Step B3 delay the valid video data parsed based on the MIPI protocol by several clocks (after the FIFO completes updating the empty threshold) and write it into the two FIFOs in a ping-pong manner;
  • Step B4 The read delay control module calculates the minimum time interval required for two FIFO reads according to the back-end MIPI transmission timing and sets the delay parameters.
  • Step B5 When the falling edge of the read FIFO enable is detected (a FIFO read operation is completed), the counter switch is started. When the counter value is equal to the set delay parameter, the done signal is set to 1. When the next read enable is valid, the done signal is set to 0.
  • Step B6 When the FIFO sets the empty flag to 0 and the done signal to 1 (satisfying the delay between two read operations), the FIFO read enable is started. When the FIFO sets the empty flag to 1 (the FIFO is about to be read empty), the FIFO read enable is set to 0.
  • Step B7 Loop steps B3 to B6 to ping-pong write and read the FIFO.
  • FIG. 3 is a variable packet length asynchronous FIFO read and write control timing diagram provided in an embodiment of the present application.
  • WR_CLK represents the write clock
  • IN represents the data input
  • WR1 represents writing data to the first FIFO queue
  • WR2 represents writing data to the second FIFO queue
  • RD_CLK represents the read clock
  • RD1 represents reading data from the first FIFO queue
  • RD2 represents reading data from the second FIFO queue
  • OUT represents data output
  • DONE represents a delayed done signal
  • DELAY represents delay
  • the numbers 1, 2, 3, 4, 5, 6, 7, and 8 represent the read and write data.
  • Some embodiments of the present application use a programmable logic device FPGA with multiple built-in MIPI D-PHY (hard core or soft core) as hardware implementation, describe the algorithm through a hardware description language, parse the data packet through the front-end MIPI protocol parsing module, extract the packet length information, calculate the FIFO empty threshold according to the FIFO depth, and dynamically pass it to the FIFO read and write control module.
  • the read delay control module will generate a fixed read FIFO delay according to the back-end MIPI send timing.
  • the dual FIFO ping-pong cache read and write effectively avoids a certain probability of read and write conflicts.
  • Using FPGA as a hardware implementation unit facilitates the flexible expansion of system functions in the later stage. At the same time, this implementation method can be easily transplanted on various platforms and improve the product development cycle.
  • FIG. 4 is a schematic diagram of the structure of an asynchronous FIFO read-write control system provided in an embodiment of the present application.
  • the system can be applied to a processor having a front-end interface and a back-end interface, including:
  • the parsing module 401 is used to parse the data received by the front-end interface to obtain the data packet length and the valid video data;
  • a threshold setting module 402 configured to determine an empty threshold of the first FIFO queue and the second FIFO queue according to the length of the data packet;
  • the delay control module 404 is used to determine the minimum time interval for reading the FIFO according to the sending timing of the back-end interface;
  • the read control module 405 is used to ping-pong read data from the first FIFO queue and the second FIFO queue by using the empty threshold and the minimum time interval, so as to output the read data through the back-end interface.
  • some embodiments of the present application can be applied to a processor having a front-end interface and a back-end interface.
  • the processor includes one front-end interface and one back-end interface, one-input-one-output bridging can be implemented; when the processor includes one front-end interface and multiple back-end interfaces, one-input-multiple-output bridging can be implemented; when the processor includes multiple front-end interfaces and one back-end interface, multiple-input-one-output bridging can be implemented.
  • the processor can obtain the data packet length and valid video data by parsing the data received by the above-mentioned front-end interface.
  • the above-mentioned valid data refers to the data received by the front-end interface except the packet header and the packet tail.
  • the data packet length refers to the byte length of the valid video data.
  • the processor may be a Field-Programmable Gate Array (FPGA).
  • Field Programmable Gate Array (FPGA) chip the front-end interface can be a front-end MIPI D-PHY interface, and the back-end interface can be a back-end MIPI D-PHY interface, so S101 can be implemented in the following way: parsing the COMMAND data received by the front-end MIPI D-PHY interface to obtain the data packet length and valid video data.
  • the above process uses a programmable logic device FPGA to implement MIPI DSI bridging. First, the MIPI receiving end video needs to be cached, then read out from the cache, and finally sent out through the MIPI sending end according to a certain MIPI protocol.
  • command mode provides a continuous clock
  • the output end can use the input end CLK clock
  • the cache can be designed as a synchronous FIFO (First Input First Output) queue
  • command mode provides a discontinuous clock
  • the output end clock can only use an asynchronous clock
  • the cache must be designed as an asynchronous FIFO.
  • video resolution and sending mode of the command mode are not fixed (line mode, segment mode, full frame mode), so the asynchronous FIFO cache needs to dynamically and adaptively adjust various packet lengths.
  • the COMMAND data in some embodiments of the present application refers to the video data in the command mode.
  • the FPGA can receive the COMMAND data through the front-end MIPI D-PHY interface, and the data packet length and valid video data can be obtained by parsing the COMMAND data.
  • the valid data refers to the data in the COMMAND data except the header and the tail, and the data packet length refers to the byte length of the valid video data.
  • some embodiments of the present application can also set the operation of the first FIFO queue and the second FIFO queue, and the first FIFO queue and the second FIFO queue have the same depth and bit width. After obtaining the length of the data packet, some embodiments of the present application can determine the empty threshold of the first FIFO queue and the second FIFO queue according to the length of the data packet, and the first FIFO queue and the second FIFO queue have the same empty threshold.
  • the empty threshold is aempty_cnt.
  • the empty signal is valid (aempty is 1), and the empty signal is transmitted to the downstream module B, notifying the downstream module to stop reading data, and preventing the situation where the read data operation is still generated when there is no valid data in the FIFO queue.
  • some embodiments of the present application can pre-set the corresponding relationship between the length interval and the empty threshold, and determine the empty threshold corresponding to the data packet length based on the corresponding relationship.
  • the processor may also query the sending timing of the back-end interface, which refers to the timing of sending video data. After obtaining the sending timing, the minimum time interval required for two FIFO reads is calculated based on the sending timing.
  • the empty threshold and the minimum time interval can be used to perform data ping-pong reading operations.
  • the data in the first FIFO queue is less than the empty threshold, stop reading the first FIFO queue, and when the data in the second FIFO queue is less than the empty threshold, stop reading the second FIFO queue. If the time interval between the current time and the completion time of the last read operation is less than the minimum time interval, the next read operation will not be performed; if the time interval between the current time and the completion time of the last read operation is greater than or equal to the minimum time interval, the next read operation can be performed.
  • the data can be encapsulated and the encapsulated data can be transmitted to the back-end interface so that the back-end interface outputs the read data.
  • Some embodiments of the present application are applied to a processor with a built-in front-end interface and a back-end.
  • the processor determines the length of the data packet and the valid video data according to the data transmitted by the front-end interface, sets the empty threshold of the FIFO queue according to the length of the data packet, and determines the minimum time interval between two adjacent read FIFOs according to the sending timing of the back-end interface.
  • Some embodiments of the present application ping-pong write the valid video data into the first FIFO queue and the second FIFO queue, and also ping-pong read the first FIFO queue and the second FIFO queue based on the empty threshold and the minimum time interval, so that the back-end interface outputs the read data.
  • Some embodiments of the present application dynamically set the empty threshold of the FIFO according to the data packet length corresponding to the front-end interface, and set a fixed delay between two read FIFOs according to the sending timing of the back-end interface.
  • the above method can effectively control the reading and writing of the dual FIFO ping-pong cache during the interface bridging process, and realize asynchronous cache processing of variable packet length data.
  • the processor is an FPGA chip
  • the front-end interface is a hard-core MIPI D-PHY interface or a soft-core MIPI D-PHY interface constructed by the FPGA chip
  • the back-end interface is a hard-core MIPI D-PHY interface or a soft-core MIPI D-PHY interface built on the FPGA chip.
  • the processor includes at least two back-end MIPI D-PHY interfaces.
  • the queue parameters of the first FIFO queue and the second FIFO queue are the same; wherein the queue parameters include queue depth and bit width.
  • the reorganization module is used to perform an inter-lane sequential reorganization operation on the valid video data before ping-pong writing the valid video data into the first FIFO queue and the second FIFO queue.
  • the process of the threshold setting module 402 determining the empty threshold of the first FIFO queue and the second FIFO queue according to the data packet length includes: determining the queue depth of the first FIFO queue or the second FIFO queue; calculating the empty threshold of the first FIFO queue and the second FIFO queue according to the data packet length and the queue depth; wherein the data packet length is positively correlated with the empty threshold, and the queue depth is positively correlated with the empty threshold.
  • the delay judgment module is used to judge whether the empty threshold is updated to the first FIFO queue and the second FIFO queue before the valid video data is ping-pong written into the first FIFO queue and the second FIFO queue; if so, the write control module 403 is entered to ping-pong write the valid video data into the first FIFO queue and the second FIFO queue; if not, after delaying for a preset time, the step of judging whether the empty threshold is updated to the first FIFO queue and the second FIFO queue is entered.
  • the process of the read control module 405 using the empty threshold and the minimum time interval to ping-pong read data from the first FIFO queue and the second FIFO queue includes: using the empty threshold to set the empty flag; wherein the empty flag is used to describe whether the data in the first FIFO queue and the second FIFO queue is less than a preset quantity; using the minimum time interval to set the delayed done signal; wherein the delayed done signal is used to describe whether the delayed waiting is completed; and performing data ping-pong reading operations on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal.
  • the process of the read control module 405 setting the empty flag using the empty threshold includes: determining whether the data in the first FIFO queue and the second FIFO queue is less than a preset amount; if so, setting the empty flag to 1; if not, setting the empty flag to 0.
  • the process of the read control module 405 setting the delayed done signal using the minimum time interval includes: when executing the current FIFO read operation, setting the delayed done signal to 0; after completing the current FIFO read operation, starting the counter; if the value of the counter is equal to the minimum time interval, setting the delayed done signal to 1.
  • the clearing module is used to clear the value of the counter to zero after the delayed done signal is set to 1.
  • the process of the read control module 405 performing a data ping-pong read operation on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal includes: determining whether the empty flag is 0 and the delayed done signal is 1; wherein, the empty flag is 0 indicating that the data in the first FIFO queue and the second FIFO queue is less than or equal to a preset number, and the delayed done signal is 1 indicating that the delay between the two read operations is completed; if so, performing a data ping-pong read operation on the first FIFO queue and the second FIFO queue.
  • the present application also provides an electronic device, comprising a processor having a front-end interface and a back-end interface; wherein the processor Used to parse the data received by the front-end interface to obtain the data packet length and valid video data; also used to determine the empty threshold of the first FIFO queue and the second FIFO queue according to the data packet length, and ping-pong write the valid video data into the first FIFO queue and the second FIFO queue; also used to determine the minimum time interval for reading FIFO according to the sending timing of the back-end interface; also used to ping-pong read data from the first FIFO queue and the second FIFO queue using the empty threshold and the minimum time interval, so as to output the read data through the back-end interface.
  • the above-mentioned electronic device can also include various network interfaces, power supplies and other components.
  • the above-mentioned electronic device can be a VR helmet, a server or a mobile set-top box.
  • the processor may further perform an inter-lane sequential reorganization operation on the valid video data.
  • the process of the processor determining the empty threshold of the first FIFO queue and the second FIFO queue based on the data packet length includes: determining the queue depth of the first FIFO queue or the second FIFO queue; calculating the empty threshold of the first FIFO queue and the second FIFO queue based on the data packet length and the queue depth; wherein the data packet length is positively correlated with the empty threshold, and the queue depth is positively correlated with the empty threshold.
  • the processor is also used to determine whether the empty threshold is updated to the first FIFO queue and the second FIFO queue; if so, entering the step of ping-pong writing the valid video data into the first FIFO queue and the second FIFO queue; if not, after delaying for a preset time, entering the step of determining whether the empty threshold is updated to the first FIFO queue and the second FIFO queue.
  • the process of the processor using the empty threshold and the minimum time interval to ping-pong read data from the first FIFO queue and the second FIFO queue includes: using the empty threshold to set the empty flag; wherein the empty flag is used to describe whether the data in the first FIFO queue and the second FIFO queue is less than a preset amount; using the minimum time interval to set the delayed done signal; wherein the delayed done signal is used to describe whether the delayed waiting is completed; performing data ping-pong reading operations on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal.
  • the process of the processor using the empty threshold to set the empty flag includes: determining whether the data in the first FIFO queue and the second FIFO queue is less than a preset amount; if so, setting the empty flag to 1; if not, setting the empty flag to 0.
  • the process of the processor setting the delayed done signal using the minimum time interval includes: setting the delayed done signal to 0 when executing the current FIFO read operation; starting the counter after completing the current FIFO read operation; and setting the delayed done signal to 1 if the value of the counter is equal to the minimum time interval.
  • the processor is further configured to clear the value of the counter to zero.
  • the process of the processor performing a data ping-pong read operation on the first FIFO queue and the second FIFO queue according to the empty flag and the delayed done signal includes: determining whether the empty flag is 0 and the delayed done signal is 1; wherein, the empty flag is 0 indicating that the data in the first FIFO queue and the second FIFO queue is less than or equal to a preset number, and the delayed done signal is 1 indicating that the delay between the two read operations is completed; if so, performing a data ping-pong read operation on the first FIFO queue and the second FIFO queue.
  • FIG5 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. As shown in FIG5 , the electronic device includes:
  • Communication interface 501 capable of exchanging information with other devices such as network devices;
  • the processor 502 is connected to the communication interface 501 to implement information exchange with other devices, and is used to execute the erasure code fusion method provided by one or more technical solutions when running a computer program.
  • the computer program is stored in the memory 503.
  • bus system 504. the various components in the electronic device are coupled together through the bus system 504. It can be understood that the overall The line system 504 is used to realize the connection and communication between these components.
  • the bus system 704 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, various buses are labeled as bus system 504 in FIG. 5 .
  • the present application also provides a non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed, the steps provided in the above embodiment can be implemented.
  • the non-volatile readable storage medium may include: semiconductor memory chip, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code.
  • Figure 6 is a structural schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application.
  • the non-volatile readable storage medium can be a non-volatile or non-transient storage chip, specifically including a decoding driver, a storage matrix, a read-write circuit, an address line, a data line, a chip select line and a read/write control line.

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Abstract

本申请公开了一种异步FIFO读写控制方法、系统及电子设备，所属的技术领域为数据读写技术。异步FIFO读写控制方法包括：解析前端接口接收的数据，得到数据包长度和有效视频数据；根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；根据后端接口的发送时序确定读FIFO的最小时间间隔；利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。本申请能够在接口桥接过程中有效控制双FIFO乒乓缓存读写，实现可变包长数据的异步缓存处理。

Description

一种异步FIFO读写控制方法、系统及电子设备
相关申请的交叉引用
本申请要求于2022年10月12日提交中国专利局，申请号为202211244073.6，申请名称为“一种异步FIFO读写控制方法、系统及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据读写技术领域，特别涉及一种异步FIFO读写控制方法、系统及电子设备。
背景技术
在VR头盔、移动机顶盒等电子设备的设计过程中，通常存在两个接口进行桥接的需求，例如工程师需要将单个接口的输入视频拆分为两路视频流，并以一半的带宽通过两个接口输出。目前常用的解决方案主要有两种，一种是采用专用的桥接芯片，一种是采用内置接口的处理器。专用的桥接芯片存在功能相对单一、扩展性较差、成本相对较高等问题，本领域通常使用处理器实现接口桥接的方案，该方案需要使用基于异步时钟的双FIFO乒乓缓存读写，这种方式极易出现读写冲突，该方式难以实现可变包长数据的异步缓存处理。
因此，如何在接口桥接过程中有效控制双FIFO乒乓缓存读写，实现可变包长数据的异步缓存处理是本领域技术人员目前需要解决的技术问题。
发明内容
本申请的目的是提供一种异步FIFO读写控制方法、系统及电子设备，能够在接口桥接过程中有效控制双FIFO乒乓缓存读写，实现可变包长数据的异步缓存处理。
为解决上述技术问题，本申请提供一种异步FIFO读写控制方法，应用于具有前端接口和后端接口的处理器，包括：
解析前端接口接收的数据，得到数据包长度和有效视频数据；
根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；
根据后端接口的发送时序确定读FIFO的最小时间间隔；
利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。
本申请一些实施例中，在将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列之前，还包括：
对有效视频数据执行lane间顺序重组操作。
本申请一些实施例中，根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，包括：
确定第一FIFO队列或第二FIFO队列的队列深度；
根据数据包长度和队列深度计算第一FIFO队列和第二FIFO队列的将空阈值；其中，数据包长度与将空阈值正相关，队列深度与将空阈值正相关。
本申请一些实施例中，在将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列之 前，还包括：
判断将空阈值是否更新至第一FIFO队列和第二FIFO队列；
若是，则进入将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列的步骤；
若否，则在延时预设时间后，进入判断将空阈值是否更新至第一FIFO队列和第二FIFO队列的步骤。
本申请一些实施例中，利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，包括：
利用将空阈值设置将空标志；其中，将空标志用于描述第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；
利用最小时间间隔设置延迟done信号；其中，延迟done信号用于描述是否延迟等待完毕；
根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
本申请一些实施例中，利用将空阈值设置将空标志，包括：
判断第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；
若是，则将将空标志设置为1；
若否，则将将空标志设置为0。
本申请一些实施例中，利用最小时间间隔设置延迟done信号，包括：
在执行当前的FIFO读操作时，将延迟done信号设置为0；
在完成当前的FIFO读操作后，启动计数器；
若计数器的值等于最小时间间隔，则将延迟done信号设置为1。
本申请一些实施例中，在将延迟done信号设置为1之后，还包括：
将计数器的值清零。
本申请一些实施例中，根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作，包括：
判断是否将空标志为0且延迟done信号为1；其中，将空标志为0表示第一FIFO队列和第二FIFO队列中的数据小于或等于预设数量，延迟done信号为1表示前后两次读操作间隔延迟完毕；
若是，则对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
本申请还提供了一种异步FIFO读写控制系统，应用于具有前端接口和后端接口的处理器，包括：
解析模块，用于解析前端接口接收的数据，得到数据包长度和有效视频数据；
阈值设置模块，用于根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值；
写控制模块，用于将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；
延迟控制模块，用于根据后端接口的发送时序确定读FIFO的最小时间间隔；
读控制模块，用于利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。
本申请一些实施例中，处理器为FPGA芯片，前端接口为FPGA芯片构建的硬核MIPI D-PHY接口或软核MIPI D-PHY接口；
后端接口为FPGA芯片构建的硬核MIPI D-PHY接口或软核MIPI D-PHY接口。
本申请一些实施例中，处理器包括至少两个后端接口。
本申请一些实施例中，第一FIFO队列和第二FIFO队列的队列参数相同；其中，队列参数包括队列深度和位宽。
本申请还提供了一种电子设备，包括具有前端接口和后端接口的处理器；
其中，处理器用于解析前端接口接收的数据，得到数据包长度和有效视频数据；还用于根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；还用于根据后端接口的发送时序确定读FIFO的最小时间间隔；还用于利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。
本申请一些实施例中，电子设备包括VR头盔、服务器或移动机顶盒。
本申请提供了一种异步FIFO读写控制方法，应用于具有前端接口和后端接口的处理器，包括：解析前端接口接收的数据，得到数据包长度和有效视频数据；根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；根据后端接口的发送时序确定读FIFO的最小时间间隔；利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。
本申请应用于内置前端接口和后端的处理器，处理器根据前端接口传输的数据确定数据包长度和有效视频数据，根据数据包长度设置FIFO队列的将空阈值，根据后端接口的发送时序确定相邻两次读FIFO的最小时间间隔。本申请将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列，还基于空阈值和最小时间间隔对第一FIFO队列和第二FIFO队列进行乒乓读取，进而使后端接口输出读取的数据。本申请根据前端接口对应的数据包长度动态设置FIFO的将空阈值，根据后端接口发送时序设置两次读FIFO间的固定延迟，上述方式能够在接口桥接过程中有效控制双FIFO乒乓缓存读写，实现可变包长数据的异步缓存处理。本申请同时还提供了一种异步FIFO读写控制系统及一种电子设备，具有上述有益效果，在此不再赘述。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例所提供的一种异步FIFO读写控制方法的流程图；
图2为本申请实施例所提供的一种可变包长异步FIFO读控制处理原理示意图；
图3为本申请实施例所提供的一种可变包长异步FIFO读写控制时序图；
图4为本申请实施例所提供的一种异步FIFO读写控制系统的结构示意图；
图5为本申请实施例所提供的一种电子设备的结构示意图；
图6为本申请实施例所提供的一种非易失性可读存储介质的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请 一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下面请参见图1，图1为本申请实施例所提供的一种异步FIFO读写控制方法的流程图。
具体步骤可以包括：
S101：解析前端接口接收的数据，得到数据包长度和有效视频数据；
其中，本申请一些实施例可以应用于具有前端接口和后端接口的处理器，当处理器包括一个前端接口和一个后端接口时，可以实现一输入一输出的桥接；当处理器包括一个前端接口和多个后端接口时，可以实现一输入多输出的桥接；当处理器包括多个前端接口和一个后端接口时，可以实现多输入一输出的桥接。处理器通过解析上述前端接口接收的数据可以得到数据包长度和有效视频数据，上述有效数据指前端接口接收的数据中除了包头和包尾的数据，数据包长度指有效视频数据的字节长度。
作为一种可行的实施方式，上述处理器可以为FPGA(Field-Programmable Gate Array，现场可编程门阵列)芯片，上述前端接口可以为前端MIPI D-PHY(Mobile Industry Processor Interface D-PHY，移动产业处理器接口协议中的一项)接口，后端接口可以为后端MIPI D-PHY接口，因此可以通过以下方式实现S101：解析前端MIPI D-PHY接口接收的COMMAND(命令)数据，得到数据包长度和有效视频数据。上述过程利用可编程逻辑器件FPGA实现MIPI DSI的桥接，首先需要将MIPI接收端视频进行缓存，然后再从缓存中读出，最后通过MIPI发送端按照一定的MIPI协议发送出去。目前MIPI DSI的链路层有两种模式：命令模式(COMMAND MODE)和视频模式(VIDEO MODE)。视频模式提供了连续的时钟，输出端可以使用输入端的CLK时钟，缓存可以设计为同步FIFO(First Input First Output，先进先出)队列，而命令模式提供的是非连续的时钟，输出端时钟只能使用异步的时钟，缓存必须设计为异步FIFO，同时命令模式的视频分辨率及发送模式不固定(分行模式、分段模式、全帧模式)，因此异步FIFO缓存需要对各种包长进行动态的自适应调整。本申请一些实施例中的COMMAND数据指命令模式下的视频数据。FPGA可以通过前端MIPI D-PHY接口接收COMMAND数据，通过解析上述COMMAND数据可以得到数据包长度和有效视频数据，上述有效数据指COMMAND数据中除了包头和包尾的数据，数据包长度指有效视频数据的字节长度。
S102：根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；
其中，在本步骤之前还可以设置第一FIFO队列和第二FIFO队列的操作，第一FIFO队列和第二FIFO队列具有相同的深度及位宽。在得到数据包长度之后，本申请一些实施例可以确定根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，第一FIFO队列和第二FIFO队列具有相同的将空阈值。将空阈值即aempty_cnt，当FIFO队列内包含的数据量小于等于将空阈值时，将空信号有效(aempty为1)，将空信号传输给下游模块B，通知下游模块停止读数据，防止FIFO队列中没有有效数据时仍产生读数据操作的情况。作为一种可行的实施方式，本申请一些实施例可以预先设置长度区间与将空阈值的对应关系，基于该对应关系确定数据包长度对应的将空阈值。
本申请一些实施例可以先对对有效视频数据执行lane(通道)间顺序重组操作，将lane 间顺序重组后的有效视频数据乒乓写入第一FIFO队列和第二FIFO队列。
S103：根据后端接口的发送时序确定读FIFO的最小时间间隔；
其中，处理器还可以查询后端接口的发送时序，该发送时序指发送视频数据的时序。在得到发送时序后，基于发送时序计算两次读FIFO所需的最小时间间隔。
S104：利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。
其中，在得到将空阈值和最小时间间隔后，可以利用将空阈值和最小时间间隔进行数据乒乓读取操作。当第一FIFO队列中的数据小于将空阈值时，停止对第一FIFO队列的读取，当第二FIFO队列中的数据小于将空阈值时，停止对第二FIFO队列的读取。若当前时间距离上一次读操作完成时间的时间间隔小于最小时间间隔，则不执行下一次读操作；若当前时间距离上一次读操作完成时间的时间间隔大于或等于最小时间间隔，则可以执行下一次读操作。在乒乓读取第一FIFO队列和第二FIFO队列中的数据后，可以对数据进行封装，将封装后的数据传输至后端接口，以便后端接口输出读取的数据。
本申请一些实施例应用于内置前端接口和后端的处理器，处理器根据前端接口传输的数据确定数据包长度和有效视频数据，根据数据包长度设置FIFO队列的将空阈值，根据后端接口的发送时序确定相邻两次读FIFO的最小时间间隔。本申请一些实施例将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列，还基于空阈值和最小时间间隔对第一FIFO队列和第二FIFO队列进行乒乓读取，进而使后端接口输出读取的数据。本申请一些实施例根据前端接口对应的数据包长度动态设置FIFO的将空阈值，根据后端接口发送时序设置两次读FIFO间的固定延迟，上述方式能够在接口桥接过程中有效控制双FIFO乒乓缓存读写，实现可变包长数据的异步缓存处理。
作为对于图1对应实施例的进一步介绍，可以通过以下方式确定将空阈值：确定第一FIFO队列或第二FIFO队列的队列深度，根据数据包长度和队列深度计算第一FIFO队列和第二FIFO队列的将空阈值；其中，数据包长度与将空阈值正相关，队列深度与将空阈值正相关。
作为一种可行的实施方式，本申请一些实施例可以根据数据包长度确定目标区间的下限值，根据队列深度确定目标区间的上限值，在目标区间内选取将空阈值，例如可以将数据包长度的N倍设置为下限值，N≥1；还可以将队列深度的M倍设置为上限值，0＜M＜1。
作为对于图1对应实施例的进一步介绍，可以先设置第一FIFO队列和第二FIFO队列的将空阈值，在设置将空阈值后在进行乒乓写操作，具体流程如下：
步骤A1：根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值；
步骤A2：将将空阈值更新至第一FIFO队列和第二FIFO队列
步骤A3：判断将空阈值是否更新至第一FIFO队列和第二FIFO队列；若是，则进入步骤A4；若否，则进入步骤A5；
步骤A4：将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；
步骤A5：在延时预设时间后，进入步骤A3。
作为对于图1对应实施例的进一步介绍，可以通过以下方式实现数据乒乓读取：
步骤B1：利用将空阈值设置将空标志；
其中，将空标志用于描述第一FIFO队列和第二FIFO队列中的数据是否小于预设数量。
具体的，利用将空阈值设置将空标志的过程包括：判断第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；若是，则将将空标志设置为1；若否，则将将空标志设置为0。
步骤B2：利用最小时间间隔设置延迟done信号；
其中，延迟done(结束)信号用于描述是否延迟等待完毕。具体的，利用最小时间间隔设置延迟done信号的过程包括：在执行当前的FIFO读操作时，将延迟done信号设置为0；在完成当前的FIFO读操作后，启动计数器；若计数器的值等于最小时间间隔，则将延迟done信号设置为1。在将延迟done信号设置为1之后，还可以将计数器的值清零，以便进行下一次计时。
步骤B3：根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
本申请一些实施例可以判断是否将空标志为0且延迟done信号为1；其中，将空标志为0表示第一FIFO队列和第二FIFO队列中的数据小于或等于预设数量，延迟done信号为1表示前后两次读操作间隔延迟完毕；若是，则对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作；若否，则不执行数据乒乓读取操作。
具体的，若空标志为0且延迟done信号为1，则可以执行数据乒乓读取操作；若空标志为0且延迟done信号为0，则不执行数据乒乓读取操作；若空标志为1且延迟done信号为0，则不执行数据乒乓读取操作；若空标志为1且延迟done信号为1，则不执行数据乒乓读取操作。
本申请一些实施例可以为第一FIFO队列和第二FIFO队列分别设置对应的将空标志，举例说明上述过程：
在对第一FIFO队列读取数据后，启动计数器开始计时，当延迟done信号设置为1时判断第二FIFO队列对应的将空标志是否为0，若将空标志为0则对第二FIFO队列读取数据，若将空标志不为0则延迟等待将有效视频数据写入第二FIFO队列。
在对第二FIFO队列读取数据后，启动计数器开始计时，当延迟done信号设置为1时判断第一FIFO队列对应的将空标志是否为0，若将空标志为0则对第一FIFO队列读取数据，若将空标志不为0则延迟等待将有效视频数据写入第一FIFO队列。
在ASIC或FPGA设计中，随着设计复杂度的不断提高，单一时钟驱动已无法满足设计及应用需求，多时钟系统驱动设计越来越普遍，在异步时钟域设计中，跨时钟域时钟数据信号传输成了必须要考虑的问题。目前单bit(比特)数据传输常用的方法是利用多级寄存器打拍；多bit数据传输常用的方法是利用异步FIFO。下面通过在实际应用中的实施例说明上述实施例描述的流程。
目前，VR头盔和移动机顶盒设计过程中，工程师常常需要将单个MIPI DSI接口的输入视频拆分为两路视频流，并以一半的带宽通过两个MIPI DSI输出。有时MIPI DSI到MIPI DSI的“Passthrough(直通)”设计也会要求提供适用于新型显示设备、升级MIPI DSI配置 需求，或者需要延长处理器和显示设备之间的距离作为信号中继器使用。目前常用的解决方案主要有两种，一种是采用专用的桥接芯片，一种是采用内置MIPI D-PHY(硬核或软核)的可编程逻辑器件FPGA。专用的桥接芯片因功能相对单一、扩展性较差、成本相对较高等问题，为此本文主要着重介绍利用可编程逻辑器件FPGA实现MIPI DSI桥接的方案。
本申请一些实施例提出了一种可变包长的异步FIFO读控制处理方案，通过前端包长解析动态设置FIFO的将空阈值，同时根据后端MIPI发送时序设置两次读FIFO间的固定延迟，以及通过双FIFO乒乓缓存机制有效避免一定概率的读写冲突等操作，可以有效的解决对可变包长数据的异步缓存处理。
请参见图2，图2为本申请实施例所提供的一种可变包长异步FIFO读控制处理原理示意图，图2中示出了MIPI D-PHY接口、MIPI协议解析及组包流程、动态FIFO阈值设置模块、异步FIFO读写控制模块、读延迟控制模块、MIPI发送时序控制流程MIPI D-PHY接口，异步FIFO 1即第一FIFO队列，异步FIFO 2即第二FIFO队列。本申请一些实施例使用FPGA作为硬件实现单元，设计了一种针对可变包长异步FIFO缓存管理方法，根据前级包长信息动态设置FIFO将空阈值，同时根据后级MIPI发送时序确定两次读FIFO最小延迟，以及乒乓读写缓存，极大的方便了MIPI DSI桥接设计方案，有效的避免使用专用桥接芯片带来的一些不足之处，同时后期灵活扩展系统功能，这种实现方式可以方便在各个平台移植，提高产品研发周期。
MIPI协议解析模块用于解析MIPI COMMAND数据包长度信息和有效数据信息，同时对有效数据进行lane间顺序重组。MIPI数据包长度信息写入动态FIFO阈值设置模块后，动态FIFO阈值设置模块计算FIFO将空阈值，传入FIFO读写控制模块，完成FIFO阈值的动态更新。MIPI协议解析模块用于将解析后的有效数据延迟若干时钟乒乓写入两个FIFO。读延迟控制模块用于根据后端MIPI发送时序计算两次读FIFO所需最小时间间隔，设置延迟参数。当检测到读FIFO使能下降沿(完成一次FIFO读操作)启动计数器开关，当计数器值等于设置的延迟参数时，置done信号为1，当下一次读使能有效时，置done信号为0。当FIFO将空标志为0且done信号为1(满足两次读操作间隔延迟)启动读FIFO使能。当FIFO将空标志变为1是(FIFO即将被读空)，FIFO读使能置0。本申请一些实施例可以扩展多个模块，以适应多通道MIPI DSI输入或输出。数据从FIFO读出后可进一步进行数据处理，之后再通过MIPI发送端输出，不过读延迟控制模块需根据数据处理模块时序进行适当调整延迟参数。
本申请一些实施例通过FPGA内置的MIPI D-PHY接口(硬核或软核)接收前端MIPI COMMAND数据，进入MIPI协议解析及组包模块，完成MIPI协议的解析，解析数据包长度信息和有效数据信息，长度信息送入动态FIFO阈值设置模块，产生对应的FIFO将空阈值送入FIFO读写控制模块完成对FIFO将空阈值的设置；同时对有效数据信息完成lane间顺序重组，在FIFO读写控制模块控制下乒乓写入两个FIFO缓存，读延迟控制模块会根据后端MIPI D-PHY接口对COMMAND数据的发送时序设置相应的读控制延迟，确保两次MIPI数据发送间隔保持足够的时序余量。
可变包长异步FIFO读控制处理实现时主要包括以下几个步骤：
步骤B1：MIPI D-PHY接收前端MIPI COMMAND数据送给MIPI协议解析模块完成MIPI数据包长度和有效视频数据的解析，同时对有效数据进行lane间顺序重组；
步骤B2：数据包长度信息送入动态FIFO阈值设置模块，根据数据包长度及FIFO深度计算FIFO将空阈值，最后将FIFO将空阈值送给FIFO读写控制模块；
步骤B3：将基于MIPI协议解析出的有效视频数据延迟若干时钟(待FIFO将空阈值更新完毕)乒乓写入两个FIFO中；
步骤B4：读延迟控制模块根据后端MIPI发送时序计算两次读FIFO所需最小时间间隔，设置延迟参数。
步骤B5：当检测到读FIFO使能下降沿(完成一次FIFO读操作)启动计数器开关，当计数器值等于设置的延迟参数时，置done信号为1，当下一次读使能有效时，置done信号为0；
步骤B6：当FIFO将空标志为0且done信号为1(满足两次读操作间隔延迟)启动读FIFO使能。当FIFO将空标志变为1是(FIFO即将被读空)，FIFO读使能置0。
步骤B7：循环步骤B3至和步骤B6，以便乒乓写入和读取FIFO。
请参见图3，图3为本申请实施例所提供的一种可变包长异步FIFO读写控制时序图，图中WR_CLK表示写时钟，IN表示数据输入，WR1表示向第一FIFO队列中写数据，WR2表示向第二FIFO队列中写数据，RD_CLK表示读时钟，RD1表示从第一FIFO队列中读数据，RD2表示从第二FIFO队列中读数据，OUT表示数据输出，DONE表示延迟done信号，DELAY表示延迟，数字1、2、3、4、5、6、7、8表示读写的数据。
本申请一些实施例使用内置多个MIPI D-PHY(硬核或软核)的可编程逻辑器件FPGA作为硬件实现，通过硬件描述语言对算法进行描述，通过前端MIPI协议解析模块对数据包进行解析，提取包长信息根据FIFO深度计算FIFO将空阈值，动态传递给FIFO读写控制模块，读延时控制模块会根据后端MIPI发送时序产生固定的读FIFO延迟，同时双FIFO乒乓缓存读写有效避免一定概率的读写冲突。使用FPGA作为硬件实现单元，方便后期灵活扩展系统功能，同时这种实现方式可以方便在各个平台移植，提高产品研发周期。
请参见图4，图4为本申请实施例所提供的一种异步FIFO读写控制系统的结构示意图，该系统可以应用于具有前端接口和后端接口的处理器，包括：
解析模块401，用于解析前端接口接收的数据，得到数据包长度和有效视频数据；
阈值设置模块402，用于根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值；
写控制模块403，用于将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；
延迟控制模块404，用于根据后端接口的发送时序确定读FIFO的最小时间间隔；
读控制模块405，用于利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。
其中，本申请一些实施例可以应用于具有前端接口和后端接口的处理器，当处理器包括一个前端接口和一个后端接口时，可以实现一输入一输出的桥接；当处理器包括一个前端接口和多个后端接口时，可以实现一输入多输出的桥接；当处理器包括多个前端接口和一个后端接口时，可以实现多输入一输出的桥接。处理器通过解析上述前端接口接收的数据可以得到数据包长度和有效视频数据，上述有效数据指前端接口接收的数据中除了包头和包尾的数据，数据包长度指有效视频数据的字节长度。
作为一种可行的实施方式，上述处理器可以为FPGA(Field-Programmable Gate Array， 现场可编程门阵列)芯片，上述前端接口可以为前端MIPI D-PHY接口，后端接口可以为后端MIPI D-PHY接口，因此可以通过以下方式实现S101：解析前端MIPI D-PHY接口接收的COMMAND数据，得到数据包长度和有效视频数据。上述过程利用可编程逻辑器件FPGA实现MIPI DSI的桥接，首先需要将MIPI接收端视频进行缓存，然后再从缓存中读出，最后通过MIPI发送端按照一定的MIPI协议发送出去。目前MIPI DSI的链路层有两种模式：命令模式(COMMAND MODE)和视频模式(VIDEO MODE)。视频模式提供了连续的时钟，输出端可以使用输入端的CLK时钟，缓存可以设计为同步FIFO(First Input First Output，先进先出)队列，而命令模式提供的是非连续的时钟，输出端时钟只能使用异步的时钟，缓存必须设计为异步FIFO，同时命令模式的视频分辨率及发送模式不固定(分行模式、分段模式、全帧模式)，因此异步FIFO缓存需要对各种包长进行动态的自适应调整。本申请一些实施例中的COMMAND数据指命令模式下的视频数据。FPGA可以通过前端MIPI D-PHY接口接收COMMAND数据，通过解析上述COMMAND数据可以得到数据包长度和有效视频数据，上述有效数据指COMMAND数据中除了包头和包尾的数据，数据包长度指有效视频数据的字节长度。
其中，本申请一些实施例还可以设置第一FIFO队列和第二FIFO队列的操作，第一FIFO队列和第二FIFO队列具有相同的深度及位宽。在得到数据包长度之后，本申请一些实施例可以确定根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，第一FIFO队列和第二FIFO队列具有相同的将空阈值。将空阈值即aempty_cnt，当FIFO队列内包含的数据量小于等于将空阈值时，将空信号有效(aempty为1)，将空信号传输给下游模块B，通知下游模块停止读数据，防止FIFO队列中没有有效数据时仍产生读数据操作的情况。作为一种可行的实施方式，本申请一些实施例可以预先设置长度区间与将空阈值的对应关系，基于该对应关系确定数据包长度对应的将空阈值。
其中，处理器还可以查询后端接口的发送时序，该发送时序指发送视频数据的时序。在得到发送时序后，基于发送时序计算两次读FIFO所需的最小时间间隔。
其中，在得到将空阈值和最小时间间隔后，可以利用将空阈值和最小时间间隔进行数据乒乓读取操作。当第一FIFO队列中的数据小于将空阈值时，停止对第一FIFO队列的读取，当第二FIFO队列中的数据小于将空阈值时，停止对第二FIFO队列的读取。若当前时间距离上一次读操作完成时间的时间间隔小于最小时间间隔，则不执行下一次读操作；若当前时间距离上一次读操作完成时间的时间间隔大于或等于最小时间间隔，则可以执行下一次读操作。在乒乓读取第一FIFO队列和第二FIFO队列中的数据后，可以对数据进行封装，将封装后的数据传输至后端接口，以便后端接口输出读取的数据。
本申请一些实施例应用于内置前端接口和后端的处理器，处理器根据前端接口传输的数据确定数据包长度和有效视频数据，根据数据包长度设置FIFO队列的将空阈值，根据后端接口的发送时序确定相邻两次读FIFO的最小时间间隔。本申请一些实施例将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列，还基于空阈值和最小时间间隔对第一FIFO队列和第二FIFO队列进行乒乓读取，进而使后端接口输出读取的数据。本申请一些实施例根据前端接口对应的数据包长度动态设置FIFO的将空阈值，根据后端接口发送时序设置两次读FIFO间的固定延迟，上述方式能够在接口桥接过程中有效控制双FIFO乒乓缓存读写，实现可变包长数据的异步缓存处理。
进一步的，处理器为FPGA芯片，前端接口为FPGA芯片构建的硬核MIPI D-PHY接口或软核MIPI D-PHY接口；
后端接口为FPGA芯片构建的硬核MIPI D-PHY接口或软核MIPI D-PHY接口。
进一步的，处理器包括至少两个后端MIPI D-PHY接口。
进一步的，第一FIFO队列和第二FIFO队列的队列参数相同；其中，队列参数包括队列深度和位宽。
进一步的，还包括：
重组模块，用于在将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列之前，对有效视频数据执行lane间顺序重组操作。
进一步的，阈值设置模块402根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值的过程包括：确定第一FIFO队列或第二FIFO队列的队列深度；根据数据包长度和队列深度计算第一FIFO队列和第二FIFO队列的将空阈值；其中，数据包长度与将空阈值正相关，队列深度与将空阈值正相关。
进一步的，还包括：
延迟判断模块，用于在将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列之前，判断将空阈值是否更新至第一FIFO队列和第二FIFO队列；若是，则进入写控制模块403将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列的步骤；若否，则在延时预设时间后，进入判断将空阈值是否更新至第一FIFO队列和第二FIFO队列的步骤。
进一步的，读控制模块405利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据的过程包括：利用将空阈值设置将空标志；其中，将空标志用于描述第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；利用最小时间间隔设置延迟done信号；其中，延迟done信号用于描述是否延迟等待完毕；根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
进一步的，读控制模块405利用将空阈值设置将空标志的过程包括：判断第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；若是，则将将空标志设置为1；若否，则将将空标志设置为0。
进一步的，读控制模块405利用最小时间间隔设置延迟done信号的过程包括：在执行当前的FIFO读操作时，将延迟done信号设置为0；在完成当前的FIFO读操作后，启动计数器；若计数器的值等于最小时间间隔，则将延迟done信号设置为1。
进一步的，还包括：
清零模块，用于在将延迟done信号设置为1之后，将计数器的值清零。
进一步的，读控制模块405根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作的过程包括：判断是否将空标志为0且延迟done信号为1；其中，将空标志为0表示第一FIFO队列和第二FIFO队列中的数据小于或等于预设数量，延迟done信号为1表示前后两次读操作间隔延迟完毕；若是，则对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
由于系统部分的实施例与方法部分的实施例相互对应，因此系统部分的实施例请参见方法部分的实施例的描述，这里暂不赘述。
本申请还提供了一种电子设备，包括具有前端接口和后端接口的处理器；其中，处理器 用于解析前端接口接收的数据，得到数据包长度和有效视频数据；还用于根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列；还用于根据后端接口的发送时序确定读FIFO的最小时间间隔；还用于利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据，以便通过后端接口输出读取的数据。当然上述电子设备还可以包括各种网络接口，电源等组件。上述电子设备可以为VR头盔、服务器或移动机顶盒。
在将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列之前，处理器还可以对有效视频数据执行lane间顺序重组操作。
进一步的，处理器根据数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值的过程包括：确定第一FIFO队列或第二FIFO队列的队列深度；根据数据包长度和队列深度计算第一FIFO队列和第二FIFO队列的将空阈值；其中，数据包长度与将空阈值正相关，队列深度与将空阈值正相关。
进一步的，在将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列之前，处理器还用于判断将空阈值是否更新至第一FIFO队列和第二FIFO队列；若是，则进入将有效视频数据乒乓写入第一FIFO队列和第二FIFO队列的步骤；若否，则在延时预设时间后，进入判断将空阈值是否更新至第一FIFO队列和第二FIFO队列的步骤。
进一步的，处理器利用将空阈值和最小时间间隔从第一FIFO队列和第二FIFO队列中乒乓读取数据的过程包括：利用将空阈值设置将空标志；其中，将空标志用于描述第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；利用最小时间间隔设置延迟done信号；其中，延迟done信号用于描述是否延迟等待完毕；根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
进一步的，处理器利用将空阈值设置将空标志的过程包括：判断第一FIFO队列和第二FIFO队列中的数据是否小于预设数量；若是，则将将空标志设置为1；若否，则将将空标志设置为0。
进一步的，处理器利用最小时间间隔设置延迟done信号的过程包括：在执行当前的FIFO读操作时，将延迟done信号设置为0；在完成当前的FIFO读操作后，启动计数器；若计数器的值等于最小时间间隔，则将延迟done信号设置为1。
进一步的，在将延迟done信号设置为1之后，处理器还用于将计数器的值清零。
进一步的，处理器根据将空标志和延迟done信号对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作的过程包括：判断是否将空标志为0且延迟done信号为1；其中，将空标志为0表示第一FIFO队列和第二FIFO队列中的数据小于或等于预设数量，延迟done信号为1表示前后两次读操作间隔延迟完毕；若是，则对第一FIFO队列和第二FIFO队列执行数据乒乓读取操作。
图5为本申请实施例所提供的一种电子设备的结构示意图，如图5所示，电子设备包括：
通信接口501，能够与其它设备比如网络设备等进行信息交互；
处理器502，与通信接口501连接，以实现与其它设备进行信息交互，用于运行计算机程序时，执行上述一个或多个技术方案提供的纠删码融合方法。而计算机程序存储在存储器503上。
当然，实际应用时，电子设备中的各个组件通过总线系统504耦合在一起。可理解，总 线系统504用于实现这些组件之间的连接通信。总线系统704除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图5中将各种总线都标为总线系统504。
本申请还提供了一种非易失性可读存储介质，其上存有计算机程序，该计算机程序被执行时可以实现上述实施例所提供的步骤。该非易失性可读存储介质可以包括：半导体存储芯片、U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。图6为本申请实施例所提供的一种非易失性可读存储介质的结构示意图，该非易失性可读存储介质可以为非易失或非瞬时的存储芯片，具体包括译码驱动、存储矩阵、读写电路、地址线、数据线、片选线和读/写控制线。
说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的系统而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的状况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (20)

  1. 一种异步FIFO读写控制方法，其特征在于，应用于具有前端接口和后端接口的处理器，包括：
    解析所述前端接口接收的数据，得到数据包长度和有效视频数据；
    根据所述数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将所述有效视频数据乒乓写入所述第一FIFO队列和所述第二FIFO队列；
    根据所述后端接口的发送时序确定读FIFO的最小时间间隔；
    利用所述将空阈值和所述最小时间间隔从所述第一FIFO队列和所述第二FIFO队列中乒乓读取数据，以便通过所述后端接口输出读取的数据。
  2. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，在将所述有效视频数据乒乓写入所述第一FIFO队列和所述第二FIFO队列之前，还包括：
    对所述有效视频数据执行lane间顺序重组操作。
  3. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，根据所述数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，包括：
    确定所述第一FIFO队列或所述第二FIFO队列的队列深度；
    根据所述数据包长度和所述队列深度计算所述第一FIFO队列和所述第二FIFO队列的将空阈值；其中，所述数据包长度与所述将空阈值正相关，所述队列深度与所述将空阈值正相关。
  4. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，在将所述有效视频数据乒乓写入所述第一FIFO队列和所述第二FIFO队列之前，还包括：
    判断所述将空阈值是否更新至所述第一FIFO队列和所述第二FIFO队列；
    若是，则进入将所述有效视频数据乒乓写入所述第一FIFO队列和所述第二FIFO队列的步骤；
    若否，则在延时预设时间后，进入判断所述将空阈值是否更新至所述第一FIFO队列和所述第二FIFO队列的步骤。
  5. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，所述根据所述后端接口的发送时序确定读FIFO的最小时间间隔的步骤，包括：
    查询后端接口的发送时序；其中，所述发送时序指发送视频数据的时序；
    基于发送时序计算两次读FIFO的最小时间间隔。
  6. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，利用所述将空阈值和所述最小时间间隔从所述第一FIFO队列和所述第二FIFO队列中乒乓读取数据，包括：
    利用所述将空阈值设置将空标志；其中，所述将空标志用于描述第一FIFO队列和所述第二FIFO队列中的数据是否小于预设数量；
    利用所述最小时间间隔设置延迟done信号；其中，所述延迟done信号用于描述是否延迟等待完毕；
    根据所述将空标志和所述延迟done信号对所述第一FIFO队列和所述第二FIFO队列执行数据乒乓读取操作。
  7. 根据权利要求6所述异步FIFO读写控制方法，其特征在于，利用所述将空阈值设置将空标志，包括：
    判断所述第一FIFO队列和所述第二FIFO队列中的数据是否小于预设数量；
    若是，则将所述将空标志设置为1；
    若否，则将所述将空标志设置为0。
  8. 根据权利要求6所述异步FIFO读写控制方法，其特征在于，利用所述最小时间间隔设置延迟done信号，包括：
    在执行当前的FIFO读操作时，将所述延迟done信号设置为0；
    在完成当前的FIFO读操作后，启动计数器；
    若所述计数器的值等于所述最小时间间隔，则将所述延迟done信号设置为1。
  9. 根据权利要求8所述异步FIFO读写控制方法，其特征在于，在将所述延迟done信号设置为1之后，还包括：
    将所述计数器的值清零。
  10. 根据权利要求6所述异步FIFO读写控制方法，其特征在于，根据所述将空标志和所述延迟done信号对所述第一FIFO队列和所述第二FIFO队列执行数据乒乓读取操作，包括：
    判断是否所述将空标志为0且所述延迟done信号为1；其中，所述将空标志为0表示所述第一FIFO队列和所述第二FIFO队列中的数据小于或等于所述预设数量，所述延迟done信号为1表示前后两次读操作间隔延迟完毕；
    若是，则对所述第一FIFO队列和所述第二FIFO队列执行数据乒乓读取操作。
  11. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，所述利用所述将空阈值和所述最小时间间隔从所述第一FIFO队列和所述第二FIFO队列中乒乓读取数据，包括：
    当第一FIFO队列中的数据小于将空阈值时，停止对第一FIFO队列的读取；
    当第二FIFO队列中的数据小于将空阈值时，停止对第二FIFO队列的读取。
  12. 根据权利要求1所述异步FIFO读写控制方法，其特征在于，所述利用所述将空阈值和所述最小时间间隔从所述第一FIFO队列和所述第二FIFO队列中乒乓读取数据，包括：
    若当前时间距离上一次读操作完成时间的时间间隔小于最小时间间隔，则不执行下一次读操作；
    若当前时间距离上一次读操作完成时间的时间间隔大于或等于最小时间间隔，则可以执行下一次读操作。
  13. 一种异步FIFO读写控制系统，其特征在于，应用于具有前端接口和后端接口的处理器，包括：
    解析模块，用于解析所述前端接口接收的数据，得到数据包长度和有效视频数据；
    阈值设置模块，用于根据所述数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值；
    写控制模块，用于将所述有效视频数据乒乓写入所述第一FIFO队列和所述第二FIFO队列；
    延迟控制模块，用于根据所述后端接口的发送时序确定读FIFO的最小时间间隔；
    读控制模块，用于利用所述将空阈值和所述最小时间间隔从所述第一FIFO队列和所述第二FIFO队列中乒乓读取数据，以便通过所述后端接口输出读取的数据。
  14. 根据权利要求13所述异步FIFO读写控制系统，其特征在于，所述处理器为FPGA芯片，所述前端接口为所述FPGA芯片构建的硬核MIPI D-PHY接口或软核MIPI D-PHY接口；
    所述后端接口为所述FPGA芯片构建的硬核MIPI D-PHY接口或软核MIPI D-PHY接口。
  15. 根据权利要求14所述异步FIFO读写控制系统，其特征在于，所述解析模块具体用于解析所述前端MIPI D-PHY接口接收的命令COMMAND数据，得到数据包长度和有效视频数据；其中，MIPI DSI的链路层包括命令模式COMMAND MODE和视频模式VIDEO MODE，命令COMMAND数据为命令模式COMMAND MODE下的视频数据。
  16. 根据权利要求15所述的异步FIFO读写控制系统，其特征在于，所述有效视频数据包括命令COMMAND数据中包头和包尾之外的数据。
  17. 根据权利要求14所述异步FIFO读写控制系统，其特征在于，所述延迟控制模块具体用于根据后端MIPI发送时序计算两次读FIFO所需最小时间间隔，设置延迟参数。
  18. 根据权利要求13所述异步FIFO读写控制系统，其特征在于，所述处理器包括至少两个所述后端接口。
  19. 根据权利要求13所述异步FIFO读写控制系统，其特征在于，所述第一FIFO队列和所述第二FIFO队列的队列参数相同；其中，所述队列参数包括队列深度和位宽。
  20. 一种电子设备，其特征在于，包括具有前端接口和后端接口的处理器；
    其中，所述处理器用于解析所述前端接口接收的数据，得到数据包长度和有效视频数据；还用于根据所述数据包长度确定第一FIFO队列和第二FIFO队列的将空阈值，将所述有效视频数据乒乓写入所述第一FIFO队列和所述第二FIFO队列；还用于根据所述后端接口的发送时序确定读FIFO的最小时间间隔；还用于利用所述将空阈值和所述最小时间间隔从所述第一FIFO队列和所述第二FIFO队列中乒乓读取数据，以便通过所述后端接口输出读取的数据。
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