WO2024077803A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2024077803A1
WO2024077803A1 PCT/CN2023/070660 CN2023070660W WO2024077803A1 WO 2024077803 A1 WO2024077803 A1 WO 2024077803A1 CN 2023070660 W CN2023070660 W CN 2023070660W WO 2024077803 A1 WO2024077803 A1 WO 2024077803A1
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type
source
region
drain
well region
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French (fr)
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胡建城
曺奎锡
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular to a semiconductor device and a method for manufacturing the same.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS is widely used in various types of semiconductor devices, such as memory, image sensors, etc.
  • semiconductor devices such as memory, image sensors, etc.
  • the demand and application scope of semiconductor devices are increasing. Improving the production efficiency of CMOS and reducing production costs have become one of the key research projects.
  • the technical problem to be solved by the embodiments of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, which can improve production efficiency and reduce production costs.
  • an embodiment of the present disclosure provides a method for preparing a semiconductor device, comprising: providing a substrate, the substrate having a first type well region and a second type well region; performing a first ion doping to form a second type source and drain region in the first type well region, and forming a doped region in the second type well region; forming a first mask layer, the first mask layer covering the second type source and drain region and exposing the doped region; removing at least a portion of the doped region; performing a second ion doping to form a first type source and drain region in the second type well region, the doping type of the first ion doping and the second ion doping being complementary; forming a first source and drain contact and a second source and drain contact, the first source and drain contact being connected to the first type source and drain region, the second source and drain contact being connected to the second type source and drain region, and in a direction perpendicular to the top surface of the semiconductor device, a connection
  • the first type well region is an N-type well region
  • the second type well region is a P-type well region
  • the step of performing the first ion doping includes performing P-type impurity doping
  • the step of performing the second ion doping includes performing N-type impurity doping.
  • the step of performing P-type impurity doping or before the step includes: performing germanium ion and/or carbon ion doping.
  • the first type well region is a P-type well region
  • the second type well region is an N-type well region
  • the step of performing the first ion doping includes performing N-type impurity doping
  • the step of performing the second ion doping includes performing P-type impurity doping.
  • the step of removing at least a portion of the doped region comprises removing the doped region using a dry etching process.
  • the removal depth is 3-5 nanometers.
  • the steps before the step of performing the first ion doping, the steps include: forming a first dielectric layer, the first dielectric layer covering the surface of the substrate; patterning the first dielectric layer to form a first via and a second via, the first via exposing a portion of the first type well region, and the second via exposing a portion of the second type well region; in the step of performing the first ion doping, performing the first ion doping along the first via and the second via; in the step of removing the doped region, removing the doped region along the second via; in the step of performing the second ion doping, performing the second ion doping along the second via.
  • the substrate in the step of patterning the first dielectric layer to form the first via hole and the second via hole, is overetched so that the first via hole and the second via hole both extend into the substrate.
  • the step of forming the first mask layer includes: forming a mask material layer, the mask material layer covers the first dielectric layer and fills the first via hole and the second via hole; removing the mask material layer in the second via hole to form the first mask layer.
  • the following step is also included: forming a first gate structure and a second gate structure on the substrate, the first gate structure is arranged on the surface of the second type well region, and the second gate structure is arranged on the surface of the first type well region.
  • the step of performing the second ion doping includes: removing the first mask layer to expose the second type source and drain regions; forming source and drain contacts, the source and drain contacts are connected to the second type source and drain regions and the first type source and drain regions.
  • the step includes: performing annealing treatment on the first type source and drain regions and the second type source and drain regions.
  • the presently disclosed embodiment also provides a semiconductor device, comprising: a first type transistor having a first type source and drain region; a second type transistor having a second type source and drain region, wherein the first type transistor and the second type transistor are complementary transistors; a first source and drain contact connected to the first type source and drain region; and a second source and drain contact connected to the second type source and drain region, wherein in a direction perpendicular to the top surface of the semiconductor device, a connection surface between the first source and drain contact and the first type source and drain region is lower than a connection surface between the second source and drain contact and the second type source and drain region.
  • a height difference between a connection surface between the first source-drain contact and the first type source-drain region and a connection surface between the second source-drain contact and the second type source-drain region is 3-5 nanometers.
  • the first type source and drain regions have P-type impurities and N-type impurities, and the concentration of the N-type impurities is greater than the concentration of the P-type impurities.
  • the first type transistor is an N-type transistor and the second type transistor is a P-type transistor, or the first type transistor is a P-type transistor and the second type transistor is an N-type transistor.
  • the semiconductor device further includes: a substrate having a first type well region and a second type well region, the first type source and drain region being located in the second type well region, and the second type source and drain region being located in the first type well region; a first dielectric layer covering the substrate, the first source and drain contact penetrating the first dielectric layer and connected to the first type source and drain region, the second source and drain contact penetrating the first dielectric layer and connected to the second type source and drain region, the connection surface between the first source and drain contact and the first type source and drain region is lower than the contact surface between the substrate and the first dielectric layer, and the connection surface between the second source and drain contact and the second type source and drain region is lower than the contact surface between the substrate and the first dielectric layer.
  • the first type transistor has a first gate structure, the first gate structure is arranged on the surface of the second type well region, and the second type well region corresponding to the first gate structure serves as the channel region of the first type transistor, and the second type transistor has a second gate structure, the second gate structure is arranged on the surface of the first type well region, and the first type well region corresponding to the second gate structure serves as the channel region of the second type transistor.
  • the method for preparing a semiconductor device does not use a mask when performing the first ion doping to form a second type of source and drain region and a doping region, then removes the doping region, and then uses a mask to perform a second ion doping to form a first type of source and drain region, thereby achieving the purpose of forming a CMOS transistor having an NMOS transistor and a PMOS transistor using only one mask, greatly improving production efficiency and reducing production costs, and at the same time also enabling the NMOS transistor or the PMOS transistor to maintain a low resistance value, thereby ensuring that the performance of the CMOS transistor is not lost.
  • FIG1 is a schematic diagram of the steps of a method for preparing a semiconductor device provided by an embodiment of the present disclosure
  • 2A-2I are schematic diagrams of semiconductor structures formed by main steps of a preparation method provided in an embodiment of the present disclosure
  • FIG. 3 is an enlarged schematic diagram of the area circled by the dotted frame A in FIG. 2I .
  • the specific implementation of the semiconductor device and the method for manufacturing the same provided by the present disclosure is described in detail below in conjunction with the accompanying drawings.
  • the semiconductor device described in this specific implementation may be, but is not limited to, a DRAM.
  • FIG1 is a schematic diagram of the steps of a method for preparing a semiconductor device provided by an embodiment of the present disclosure.
  • the method comprises: step S10, providing a substrate, the substrate having a first type well region and a second type well region; step S11, performing a first ion doping, forming a second type source and drain region in the first type well region, and forming a doping region in the second type well region; step S12, forming a first mask layer, the first mask layer covering the second type source and drain region and exposing the doping region; step S13, removing at least part of the doping region; step S14, performing a second ion doping, forming a first type source and drain region in the second type well region, the doping type of the first ion doping and the second ion doping being complementary; step S15, forming a first source and drain contact and a second source and drain contact, the first source and drain contact being connected to the first type source and drain region, the second
  • 2A-2I are schematic diagrams of semiconductor structures formed by main steps of the preparation method provided in an embodiment of the present disclosure.
  • a substrate 200 is provided.
  • the substrate 200 has a first-type well region W1 and a second-type well region W2 .
  • the base 200 includes a substrate 201 and a shallow trench isolation structure 202 (Shallow Trench Isolation, STI) disposed in the substrate 201.
  • the shallow trench isolation structure 202 separates the substrate 201 into a plurality of independent active regions.
  • the active regions are subjected to first type doping and second type doping to form the first type well region W1 and the second type well region W2.
  • the substrate 201 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 201 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 201 may also be a stacked structure, such as a silicon/silicon germanium stack, etc.
  • the substrate 201 may also be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 201, such as field effect transistors, capacitors, inductors and/or diodes, etc.
  • the substrate 201 is described as a silicon substrate.
  • the substrate 201 may also include other device structures, such as metal wiring structures, etc., but they are not shown because they are irrelevant to the embodiments of the present disclosure.
  • the shallow trench isolation structure 202 may be a single-layer or multi-layer composite structure.
  • the shallow trench isolation structure 202 is an oxide isolation structure.
  • the shallow trench isolation structure 202 is a composite structure of a silicon oxide isolation structure and a nitride isolation structure.
  • the first type well region W1 and the second type well region W2 are well regions with different doping types.
  • the first type well region W1 is an N-type well region
  • the second type well region W2 is a P-type well region.
  • the first type well region W1 is a P-type well region
  • the second type well region W2 is an N-type well region.
  • the P-type well region refers to a region doped with P-type impurities in the substrate 201, and the P-type impurities include but are not limited to boron (B) or gallium (Ga).
  • the N-type well region refers to a region doped with N-type impurities in the substrate 201, and the N-type impurities include but are not limited to phosphorus (P) or arsenic (As).
  • the present disclosure provides a method for forming the substrate 200.
  • the method includes:
  • a substrate 201 is provided, and shallow trenches are formed in the substrate 201.
  • a patterned mask layer is formed on the surface of the substrate 201, and the mask layer is used as a shield to etch the substrate 201 to form shallow trenches in the substrate 201.
  • the shallow trenches separate the substrate 201 into multiple independent regions, which are the active regions.
  • An isolation material is filled in the shallow trench to form the shallow trench isolation structure 202.
  • Methods for filling the isolation material include but are not limited to chemical vapor deposition, atomic layer deposition, and the like.
  • the active area is doped to form the first type well area W1 and the second type well area W2.
  • the active area can be doped by an ion implantation process.
  • phosphorus ions are implanted in a preset area of the active area by an ion implantation process to form the first type well area W1
  • the first type well area W1 is an N-type well area.
  • Boron ions are implanted in a preset area of the active area by an ion implantation process to form the second type well area W2, and the second type well area W2 is a P-type well area.
  • a first gate structure 210 and a second gate structure 220 are further formed on the substrate 200.
  • the first gate structure 210 is disposed on the surface of the second type well region W2
  • the second gate structure 220 is disposed on the surface of the first type well region W1.
  • Both the first gate structure 210 and the second gate structure 220 include a gate dielectric layer and a gate line disposed on the surface of the gate dielectric layer.
  • the gate dielectric layer is disposed on the surface of the active region as an isolation structure between the gate line and the active region.
  • the gate dielectric layer includes but is not limited to a silicon oxide layer or a high-K dielectric layer
  • the gate line includes but is not limited to a composite gate line composed of a polysilicon gate line, a metal titanium nitride layer and a tungsten layer.
  • sidewalls of the first gate structure 210 and the second gate structure 220 are further provided with sidewall spacers to protect the first gate structure 210 and the second gate structure 220 , and the second type well region W2 and the first type well region W1 covered by the first gate structure 210 and the second gate structure 220 .
  • the method further includes the following steps:
  • a first dielectric layer 230 is formed, and the first dielectric layer 230 covers the surface of the substrate 200.
  • the first dielectric layer 230 also covers the first gate structure 210 and the second gate structure 220.
  • a dielectric material may be deposited by a process such as chemical vapor deposition to form the first dielectric layer 230.
  • the first dielectric layer 230 may be a single-layer structure or a multi-layer composite structure.
  • the first dielectric layer 230 is a silicon nitride single-layer structure.
  • the first dielectric layer 230 is a double-layer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the first dielectric layer 230 is a double-layer composite structure composed of a silicon oxide layer and a silicon nitride layer as an example for description.
  • the silicon oxide layer covers the surface of the substrate 200 and the first gate structure 210 and the second gate structure 220, and the silicon nitride layer covers the surface of the silicon oxide layer.
  • the first dielectric layer 230 is patterned to form a first via 231 and a second via 232.
  • the first via 231 exposes a portion of the first type well region W1
  • the second via 232 exposes a portion of the second type well region W2.
  • the first via 231 includes two vias, which serve as a source via and a drain via, respectively, and are disposed on both sides of the second gate structure 220 and expose the first type well region W1 respectively.
  • the second via 232 includes two vias, which serve as a source via and a drain via, respectively, and are disposed on both sides of the first gate structure 210 and expose the second type well region W2 respectively.
  • a patterned mask layer (not shown in the drawings) and a photoresist layer (not shown in the drawings) may be formed on the surface of the first dielectric layer 230, and the pattern on the mask layer may be transferred to the first dielectric layer 230 through an etching process to form the first via hole 231 and the second via hole 232.
  • the mask layer and the photoresist layer are removed to form the structure shown in FIG. 2C.
  • the substrate 200 is overetched so that the first via hole 231 and the second via hole 232 are extended into the substrate 200 to increase the surface area of the first type well region W1 and the second type well region W2 exposed to the first via hole 231 and the second via hole 232, thereby increasing the contact area between the subsequently formed source-drain contact and the source-drain region.
  • step S11 a first ion doping is performed to form a second type source/drain region 240 in the first type well region W1 , and a doped region 241 in the second type well region W2 .
  • the first ion doping is performed along the first via hole 231 and the second via hole 232. Since the first type well region W1 is exposed to the first via hole 231, the second type well region W2 is exposed to the second via hole 232, and other areas of the substrate 200 are blocked by the first dielectric layer 230, after performing this step, the second type source and drain region 240 is formed in the first type well region W1 corresponding to the first via hole 231, and the doping region 241 is formed in the second type well region W2 corresponding to the second via hole 232.
  • the first type well region W1 is an N type well region, then in step S11, P type impurity doping is performed, and the second type source and drain region 240 formed in the first type well region W1 is a P type region.
  • the P type impurity includes but is not limited to boron (B) or gallium (Ga).
  • the first type well region W1 and the second type well region W2 are implanted with P type impurities by an ion implantation process to form the second type source and drain region 240 and the doped region 241.
  • the doping concentration and doping depth of the formed second type source and drain region 240 and the doped region 241 can be controlled by controlling the implantation dose and energy during the ion implantation process.
  • the first type well region W1 is a P type well region
  • step S11 N type impurity doping is performed
  • the second type source and drain region 240 formed in the first type well region W1 is an N type region.
  • N type impurity doping is performed
  • the second type source and drain region 240 formed in the first type well region W1 is an N type region.
  • the N type impurity includes but is not limited to phosphorus (P) or arsenic (As).
  • the first type well region W1 and the second type well region W2 can be implanted with N type impurities by an ion implantation process to form the second type source and drain region 240 and the doped region 241.
  • the step of performing P-type impurity doping or before includes: performing germanium ion and/or carbon ion doping.
  • germanium ion or carbon ion doping is performed before performing P-type impurity doping.
  • both germanium ion doping and carbon ion doping are performed before performing P-type impurity doping, for example, germanium ion doping is performed first, and then carbon ion doping is performed, or carbon ion doping is performed first, and then germanium ion doping is performed, or germanium ion doping and carbon ion doping are performed simultaneously.
  • the doping of germanium ions and/or carbon ions is performed in the same step as the doping of boron ions.
  • Germanium ion implantation can amorphize silicon crystals and tend to amorphous amorphous silicon to inhibit the penetration of boron ions, thereby achieving the purpose of inhibiting the diffusion of boron ions; carbon ion implantation can fill defects in silicon crystals with carbon ions to inhibit the diffusion of boron ions.
  • step S12 a first mask layer 250 is formed, and the first mask layer 250 covers the second type source and drain regions 240 and exposes the doped regions 241 .
  • the first mask layer 250 not only fills the first via hole 231 and covers the surface of the second type source and drain region 240 at the bottom of the first via hole 231, but also covers the surface of the first dielectric layer 230. However, since the subsequent steps require the doping region 241 to be processed through the second via hole 232, the first mask layer 250 does not fill the second via hole 232, and the second via hole 232 and the doping region 241 at the bottom of the second via hole 232 are exposed.
  • an embodiment of the present disclosure provides a method for forming the first mask layer 250, the method comprising:
  • a mask material layer is formed, the mask material layer covers the first dielectric layer 230 and fills the first via hole 231 and the second via hole 232.
  • the mask material layer may be deposited by a chemical vapor deposition process, an atomic layer deposition process, etc.
  • the mask material layer includes but is not limited to a photoresist layer.
  • the mask material layer in the second via hole 232 is removed to form the first mask layer 250.
  • a mask may be used to remove the mask material layer in the second via hole 232, and only the mask material layer in the first via hole 231 is retained as the first mask layer 250. It is understood that, in some embodiments, the mask material layer on a portion of the surface of the first dielectric layer 230 is also retained, for example, the mask material layer on the surface of the first dielectric layer 230 corresponding to the active region where the first type well region W1 is located is also retained.
  • step S13 at least a portion of the doped region 241 is removed.
  • the first mask layer 250 is used as a shield, and a dry etching process is used to remove at least a portion of the doped region 241 through the second via hole 232.
  • a dry etching process is used to remove at least a portion of the doped region 241 through the second via hole 232.
  • the anisotropic characteristics of the dry etching process in this step, only the doped region 241 at the bottom of the second via hole 232 is etched, and the first dielectric layer 230 and the substrate 200 exposed on the sidewall of the second via hole 232 are not etched, which will not affect the performance of the transistor formed subsequently.
  • the doping region 241 is a region formed when the first ion doping is performed, and its doping type is the same as the doping type of the second type source and drain region 240. In the subsequent steps, it is necessary to form a first type source and drain region 260 in the second type well region W2 where the doping region 241 is located.
  • the first type source and drain region 260 is complementary to the second type source and drain region 240, that is, the doping type of the doping region 241 is complementary to the doping type of the first type source and drain region 260 formed subsequently, which makes the resistance of the transistor formed subsequently in the second type well region W2 higher, which is not conducive to improving the performance of the transistor.
  • at least part of the doping region 241 is removed before forming the first type source and drain region 260 in the second type well region W2, so as to avoid increasing the resistance of the transistor due to the presence of the doping region 241.
  • the doping type of the doped impurities when performing the first ion doping is P-type, that is, the doping type of the doping region 241 is P-type, and when performing the second ion doping in the subsequent step to form the first type source and drain region 260, the doping type of the doped impurities is N-type, and the doping type of the doping region 241 is complementary to the doping type of the first type source and drain region 260. If the doping region 241 is not removed before forming the first type source and drain region 260, the resistance of the formed NMOS transistor will be higher, affecting the performance of the transistor. Therefore, this step removes at least part of the doping region 241 to avoid increasing the resistance of the NMOS transistor due to the presence of the doping region 241.
  • the etching process is performed until the doping region 241 is completely removed, while in other embodiments, the etching process is performed until the set depth is removed, that is, after the set depth is etched, the etching is stopped regardless of whether the doping region 241 is completely removed.
  • the removal depth is 3 to 5 nanometers, that is, after etching 3 to 5 nanometers, the etching is stopped regardless of whether the doping region 241 is completely removed. After the etching is stopped, the doping region 241 may be completely removed or partially removed.
  • the removal depth is limited to 3 to 5 nanometers.
  • the etching depth is too small, more doped regions 241 may remain, which is not conducive to reducing the resistance of the transistor formed subsequently; on the other hand, if the etching depth is too large, the surface of the first type source and drain regions 260 is at a deeper position, which may cause the subsequently formed source and drain contacts to have poor ohmic contact with the first type source and drain regions 260, affecting the performance of the transistor.
  • step S14 a second ion doping is performed to form a first type source/drain region 260 in the second type well region W2 , and the doping types of the first ion doping and the second ion doping are complementary.
  • the second ion doping is performed along the second via hole 232 using the first mask layer 250 as a shield. Since the second type well region W2 is exposed to the second via hole 232 and the second type source and drain region 240 is shielded by the first mask layer 250, after this step is performed, the first type source and drain region 260 is formed only in the second type well region W2 corresponding to the second via hole 232.
  • the doping types of the first ion doping and the second ion doping are complementary, that is, the doping types of the second type source and drain region 240 and the first type source and drain region 260 are complementary.
  • the type of the doping impurity of the first ion doping is P type
  • the doping type of the second type source and drain region 240 is P type
  • the type of the doping impurity of the second ion doping is N type
  • the doping type of the first type source and drain region 260 is N type
  • the type of the doping impurity of the second ion doping is P type
  • the doping type of the first type source and drain region 260 is P type.
  • the second type well region W2 is a P type well region
  • N type impurity doping is performed, and the first type source and drain region 260 formed in the second type well region W2 is an N type region.
  • the N type impurities include but are not limited to phosphorus (P) or arsenic (As).
  • an ion implantation process is used to implant N type impurities into the second type well region W2 to form the first type source and drain region 260.
  • the doping concentration and doping depth of the formed first type source and drain region 260 can be controlled by controlling the implantation dose and energy during the ion implantation process.
  • the second type well region W2 is an N type well region, then in step S14, P type impurity doping is performed, and the first type source and drain region 260 formed in the second type well region W2 is a P type region.
  • the P type impurity includes but is not limited to boron (B) or gallium (Ga).
  • the second type well region W2 can be implanted with P type impurities by an ion implantation process to form the first type source and drain region 260.
  • the doping region 241 if the doping region 241 is not completely removed, it is necessary to increase the concentration of doping ions when performing the second ion doping to prevent the inverse ions in the doping region 241 from affecting the reliability of the first type source and drain region 260 .
  • the first mask layer 250 is removed to expose the first type source and drain regions 260 and the second type source and drain regions 240.
  • an ashing process may be used to remove the first mask layer 250.
  • a cleaning step is performed to remove impurities.
  • the method further includes: performing annealing on the first type source and drain region 260 and the second type source and drain region 240 to activate doped impurities, restore the crystal structure changed by ion implantation, eliminate defects caused by ion implantation, and improve the performance of the semiconductor device.
  • the annealing includes but is not limited to rapid thermal processing (RTP).
  • the method further includes the step of forming a first source-drain contact 270 and a second source-drain contact 280.
  • step S15 the first source-drain contact 270 and the second source-drain contact 280 are formed, the first source-drain contact 270 is connected to the first type source-drain region 260, the second source-drain contact 280 is connected to the second type source-drain region 240, and in a direction perpendicular to the top surface of the semiconductor device, the connection surface between the first source-drain contact 270 and the first type source-drain region 260 is lower than the connection surface between the second source-drain contact 280 and the second type source-drain region 240.
  • a second type transistor 2 is formed in the first type well region W1
  • the second type transistor 2 is a P-type transistor
  • the second type source and drain region 240 is used as the source and drain region of the P-type transistor
  • the second gate structure 220 is used as the gate of the P-type transistor
  • the second source and drain contact 280 is connected to the second type source and drain region 240 as the lead-out structure of the source and drain region of the P-type transistor
  • a first type transistor 1 is formed in the second type well region W2, the first type transistor 1 is an N-type transistor, the first type source and drain region 260 is used as the source and drain region of the N-type transistor, the first gate structure 210 is used as the gate of the N-type transistor, and the first source and drain contact 270 is connected to the first type source and drain region 260 as the lead-out structure of the source and drain region of the N-type transistor.
  • the first gate structure 210 can be connected to the second gate structure 220, and the drain electrode in the first source and drain contact 270 is connected to the drain electrode in the second source and drain contact 280 to form a CMOS transistor, and the CMOS transistor can be used as an inverter.
  • the embodiment of the present disclosure provides a method for forming the first source-drain contact 270 and the second source-drain contact 280, the method comprising: after annealing, metallizing and annealing the first type source-drain region 260 and the second type source-drain region 240 to form a metal silicide layer 290, so as to improve the contact performance between the first source-drain contact 270 and the first type source-drain region 260 and the second source-drain contact 280 and the second type source-drain region 240, which is beneficial to reduce the contact resistance and improve the performance of the semiconductor device.
  • the metal silicide includes but is not limited to a cobalt layer or a silicon-nickel layer.
  • the material of the source-drain contact includes but is not limited to one or more of metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), titanium nitride (TiN), tungsten nitride (WN), copper (Cu) and aluminum (Al).
  • metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), titanium nitride (TiN), tungsten nitride (WN), copper (Cu) and aluminum (Al).
  • the preparation method provided by the embodiment of the present disclosure does not use a mask when performing the first ion doping, and forms a second type of source and drain region 240 in the first type well region W1 and a doping region 241 in the second type well region W2, then removes the doping region 241, and then uses a mask to perform a second ion doping to form a first type of source and drain region 260 in the second type well region W2, thereby achieving the purpose of forming a CMOS transistor having an NMOS transistor and a PMOS transistor by using only one mask, greatly reducing the production cost, and at the same time, it can also enable the NMOS transistor or the PMOS transistor to maintain a low resistance value, ensuring that the performance of the CMOS transistor is not lost.
  • the semiconductor device includes a first type transistor 1, a second type transistor 2, a first source-drain contact 270 and a second source-drain contact 280.
  • the first type transistor 1 and the second type transistor 2 are complementary transistors.
  • the first type transistor 1 is an N-type transistor and the second type transistor 2 is a P-type transistor.
  • the first type transistor 1 is a P-type transistor and the second type transistor 2 is an N-type transistor.
  • the first type transistor 1 has a first type source and drain region 260
  • the second type transistor 2 has a second type source and drain region 240
  • the doping types of the first type source and drain region 260 and the second type source and drain region 240 are complementary.
  • the first type source and drain region 260 is N-type
  • the second type source and drain region 240 is P-type.
  • the first source-drain contact 270 is connected to the first type source-drain region 260 as a lead-out structure of the source-drain region of the first type transistor 1
  • the second source-drain contact 280 is connected to the second type source-drain region 240 as a lead-out structure of the source-drain region of the second type transistor 2 .
  • FIG. 3 is an enlarged view of the area circled by the dotted frame A in FIG. 2I .
  • the connection surface between the first source-drain contact 270 and the first type source-drain region 260 is lower than the connection surface between the second source-drain contact 280 and the second type source-drain region 240.
  • the metal silicide layer 290 exists between the first source-drain contact 270 and the first type source-drain region 260 and between the second source-drain contact 280 and the second type source-drain region 240, in the direction perpendicular to the top surface of the semiconductor device, the interface C1 between the metal silicide layer 290 and the first type source-drain region 260 is lower than the interface C2 between the metal silicide layer 290 and the second type source-drain region 240.
  • the first type source and drain region 260 has P-type impurities and N-type impurities, and the concentration of the N-type impurities is greater than the concentration of the P-type impurities to prevent the P-type impurities from affecting the reliability of the first type source and drain region 260 .
  • the height difference between the connection surface of the first source-drain contact 270 and the first type source-drain region 260 and the connection surface of the second source-drain contact 280 and the second type source-drain region 240 is 3-5 nanometers.
  • the height difference H1 between the interface C1 of the metal silicide layer 290 and the first type source-drain region 260 and the interface C2 of the metal silicide layer 290 and the second type source-drain region 240 is 3-5 nanometers.
  • the semiconductor device further includes a substrate 200 and a first dielectric layer 230 .
  • the substrate 200 has a first-type well region W1 and a second-type well region W2, the first-type source and drain region 260 is located in the second-type well region W2, and the second-type source and drain region 240 is located in the first-type well region W1.
  • the first-type source and drain region 260 and the second-type well region W2 have complementary doping types, and the second-type source and drain region 240 and the second-type well region W2 have complementary doping types.
  • the base 200 includes a substrate 201 and a shallow trench isolation structure 202.
  • the shallow trench isolation structure 202 separates the substrate 201 into a plurality of independent active areas.
  • the active areas are subjected to first-type doping and second-type doping to form the first-type well area W1 and the second-type well area W2.
  • Heavy doping is performed in the first-type well area W1 and the second-type well area W2 to form the first-type source and drain area 260 and the second-type source and drain area 240.
  • the first dielectric layer 230 covers the substrate 200, the first source-drain contact 270 penetrates the first dielectric layer 230 and is connected to the first type source-drain region 260, and the second source-drain contact 280 penetrates the first dielectric layer 230 and is connected to the second type source-drain region 240.
  • the connection surface E1 between the first source-drain contact 270 and the first type source-drain region 260 is lower than the contact surface E2 between the substrate 200 and the first dielectric layer 230
  • the connection surface E3 between the second source-drain contact 280 and the second type source-drain region 240 is lower than the contact surface E2 between the substrate 200 and the first dielectric layer 230. That is, the first source-drain contact 270 and the second source-drain contact 280 extend into the substrate 200.
  • the first type transistor 1 has a first gate structure 210, and the first gate structure 210 is arranged on the surface of the second type well region W2.
  • the second type well region W2 corresponding to the first gate structure 210 serves as the channel region of the first type transistor 1.
  • the second type transistor 2 has a second gate structure 220, and the second gate structure 220 is arranged on the surface of the first type well region W1.
  • the first type well region W1 corresponding to the second gate structure 220 serves as the channel region of the second type transistor 2.
  • the first gate structure 210 and the second gate structure 220 both include a gate dielectric layer and a gate line disposed on the surface of the gate dielectric layer, and the gate dielectric layer is disposed on the surface of the active area as an isolation structure between the gate line and the active area.
  • the gate dielectric layer includes but is not limited to a silicon oxide layer or a high-K dielectric layer
  • the gate line includes but is not limited to a composite gate line composed of a polysilicon gate line, a metal titanium nitride layer and a tungsten layer.
  • the first gate structure 210 can be connected to the second gate structure 220, and the drain electrode in the first source-drain contact 270 is connected to the drain electrode in the second source-drain contact 280 to form a CMOS transistor, and the CMOS transistor can be used as an inverter.
  • the semiconductor device provided by the embodiment of the present disclosure has low manufacturing cost and can also maintain a relatively low resistance value of the NMOS transistor or the PMOS transistor, thereby ensuring that the performance of the CMOS transistor is not compromised.

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Abstract

一种半导体器件的制备方法，包括：提供基底，基底具有第一类型阱区及第二类型阱区；执行第一次离子掺杂，于第一类型阱区内形成第二类型源漏区，于第二类型阱区内形成掺杂区；形成第一掩膜层，第一掩膜层覆盖第二类型源漏区，且显露掺杂区；至少去除部分掺杂区；执行第二次离子掺杂，于第二类型阱区内形成第一类型源漏区，第一次离子掺杂与第二次离子掺杂的掺杂类型互补；形成第一源漏接触及第二源漏接触，第一源漏接触与第一类型源漏区连接，第二源漏接触与第二类型源漏区连接，在垂直半导体器件顶面的方向上，第一源漏接触与第一类型源漏区的连接面低于第二源漏接触与第二类型源漏区的连接面。所述方法仅采用一道光罩就能实现形成CMOS晶体管的目的，也保证了CMOS晶体管的性能不受损失。

Description

半导体器件及其制备方法
相关申请引用说明
本申请要求于2022年10月13日递交的中国专利申请号202211258047.9、申请名为“半导体器件及其制备方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及集成电路领域，尤其涉及一种半导体器件及其制备方法。
背景技术
CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)由绝缘场效应晶体管组成，由于只有一种载流子，因而是一种单极型晶体管集成电路，其基本结构是一个N沟道MOS管和一个P沟道MOS管。
CMOS被广泛应用在各种类型的半导体器件中，例如，存储器、图像传感器等。随着科技的发展，半导体器件的需求量及应用范围越来越大，提高CMOS的生产效率，降低生产成本成为目前研究的重点项目之一。
发明内容
本公开实施例所要解决的技术问题是，提供一种半导体器件及其制备方法，其能够提供生产效率，降低生产成本。
为了解决上述问题，本公开实施例提供了一种半导体器件的制备方法，包括：提供基底，所述基底具有第一类型阱区及第二类型阱区；执行第一次离子掺杂，于所述第一类型阱区内形成第二类型源漏区，于所述第二类型阱区内形成掺杂区；形成第一掩膜层，所述第一掩膜层覆盖所述第二类型源漏区，且显露所述掺杂区；至少去除部分所述掺杂区；执行第二次离子掺杂，于所述第二类型阱区内形成第一类型源漏区，所述第一次离子掺杂与所述第二次离子掺杂的掺杂类型互补；形成第一源漏接触及第二源漏接触，所述第一源漏接触与所述第一类型源漏区连接，所述第二源漏接触与所述第二类型源漏区连接，在垂直所述半导体器件顶面的方向上，所述第一源漏接触与所述第一类型源漏区的连接面低于所述第二源漏接触与所述第二类型源漏区的连接面。
在一实施例中，所述第一类型阱区为N型阱区，所述第二类型阱区为P型阱区，所述执行第一次离子掺杂的步骤包括执行P型杂质掺杂，所述执行第二次离子掺杂包括执行N型杂质掺杂。
在一实施例中，所述执行P型杂质掺杂的步骤中或者之前包括：执行锗离子和/或碳离子掺杂。
在一实施例中，所述第一类型阱区为P型阱区，所述第二类型阱区为N型阱区，所述执行第一次离子掺杂的步骤包括执行N型杂质掺杂，所述执行第二次离子掺杂包括执行P型杂质掺杂。
在一实施例中，至少去除部分所述掺杂区的步骤：采用干法刻蚀工艺去除所述掺杂区。
在一实施例中，至少去除部分所述掺杂区的步骤中，去除深度为3～5纳米。
在一实施例中，在所述执行第一次离子掺杂的步骤之前包括：形成第一介质层，所述第一介质层覆盖所述基底表面；图案化所述第一介质层，形成第一过孔及第二过孔，所述第一过孔暴露出部分所述第一类型阱区，所述第二过孔暴露出部分所述第二类型阱区；在所述执行第一次离子掺杂的步骤中，沿所述第一过孔及第二过孔执行所述第一次离子掺杂；在所述去除所述掺杂区的步骤中，沿所述第二过孔去除所述掺杂区；在所述执行第二次离子掺杂的步骤中，沿所述第二过孔执行第二次离子掺杂。
在一实施例中，在图案化所述第一介质层，形成第一过孔及第二过孔的步骤中，过刻蚀所述基底，使所述第一过孔及所述第二过孔均延伸至所述基底内。
在一实施例中，所述形成第一掩膜层的步骤包括：形成掩膜材料层，所述掩膜材料层覆盖所述第一介质层，且填充所述第一过孔及第二过孔；去除所述第二过孔内的掩膜材料层，形成所述第一掩膜层。
在一实施例中，在所述形成第一介质层之前还包括如下步骤：在所述基底上形成第一栅极结构及第二栅极结构，所述第一栅极结构设置在所述第二类型阱区表面，所述第二栅极结构设置在所述第一类型阱区表面。
在一实施例中，所述执行第二次离子掺杂的步骤之后包括：去除所述第一掩膜层，显露所述第二类型源漏区；形成源漏接触，所述源漏接触与所述第二类型源漏区及所述第一类型源漏区连接。
在一实施例中，所述去除所述第一掩膜层的步骤之后包括：对所述第一类型源漏区及所述第二类型源漏区进行退火处理。
本公开实施例还提供一种半导体器件，其包括：第一类型晶体管，具有第一类型源漏区；第二类型晶体管，具有第二类型源漏区，，所述第一类型晶体管与所述第二类型晶体管为互补晶体管；第一源漏接触，与所述第一类型源漏区连接；第二源漏接触，与所述第二类型源漏区连接，在垂直所述半导体器件顶面的方向上，所述第一源漏接触与所述第一类型源漏区的连接面低于所述第二源漏接触与所述第二类型源漏区的连接面。
在一实施例中，所述第一源漏接触与所述第一类型源漏区的连接面与所述第二源漏接 触，和所述第二类型源漏区的连接面之间的高度差为3～5纳米。
在一实施例中，所述第一类型源漏区具有P型杂质及N型杂质，所述N型杂质浓度大于所述P型杂质浓度。
在一实施例中，所述第一类型晶体管为N型晶体管，所述第二类型晶体管为P型晶体管，或者所述第一类型晶体管为P型晶体管，所述第二类型晶体管为N型晶体管。
在一实施例中，所述半导体器件还包括：基底，具有第一类型阱区及第二类型阱区，所述第一类型源漏区位于所述第二类型阱区内，所述第二类型源漏区位于所述第一类型阱区内；第一介质层，覆盖所述基底，所述第一源漏接触贯穿所述第一介质层与所述第一类型源漏区连接，所述第二源漏接触贯穿所述第一介质层与所述第二类型源漏区连接，所述第一源漏接触与所述第一类型源漏区的连接面低于所述基底与所述第一介质层的接触面，且所述第二源漏接触与所述第二类型源漏区的连接面低于所述基底与所述第一介质层的接触面。
在一实施例中，所述第一类型晶体管具有第一栅极结构，所述第一栅极结构设置在所述第二类型阱区表面，所述第一栅极结构对应的第二类型阱区作为所述第一类型晶体管的沟道区，所述第二类型晶体管具有第二栅极结构，所述第二栅极结构设置在所述第一类型阱区表面，所述第二栅极结构对应的第一类型阱区作为所述第二类型晶体管的沟道区。
本公开实施例提供的半导体器件的制备方法在执行第一次离子掺杂时不使用光罩，形成第二类型源漏区及掺杂区，然后去除所述掺杂区，再采用光罩进行第二次离子掺杂，形成第一类型源漏区，从而实现仅采用一道光罩就能形成具有NMOS晶体管与PMOS晶体管的CMOS晶体管的目的，大大提供了生产效率，降低了生产成本，同时也能够使NMOS晶体管或者PMOS晶体管保持较低的阻值，保证了CMOS晶体管的性能不受损失。
附图说明
图1是本公开实施例提供的半导体器件的制备方法的步骤示意图；
图2A-图2I是本公开实施例提供的制备方法的主要步骤形成的半导体结构的示意图；
图3是图2I中虚线框A所圈示区域的放大示意图。
具体实施方式
下面结合附图对本公开提供的半导体器件及其制备方法的具体实施方式做详细说明。本具体实施方式中所述的半导体器件可以是但不限于DRAM。
图1是本公开实施例提供的半导体器件的制备方法的步骤示意图。请参阅图1，所述制备方法包括：步骤S10，提供基底，所述基底具有第一类型阱区及第二类型阱区；步骤S11， 执行第一次离子掺杂，于所述第一类型阱区内形成第二类型源漏区，于所述第二类型阱区内形成掺杂区；步骤S12，形成第一掩膜层，所述第一掩膜层覆盖所述第二类型源漏区，且显露所述掺杂区；步骤S13，至少去除部分所述掺杂区；步骤S14，执行第二次离子掺杂，于所述第二类型阱区内形成第一类型源漏区，第一次离子掺杂与所述第二次离子掺杂的掺杂类型互补；步骤S15，形成第一源漏接触及第二源漏接触，所述第一源漏接触与所述第一类型源漏区连接，所述第二源漏接触与所述第二类型源漏区连接，在垂直所述半导体器件顶面的方向上，所述第一源漏接触与所述第一类型源漏区的连接面低于所述第二源漏接触与所述第二类型源漏区的连接面。
图2A-图2I是本公开实施例提供的制备方法的主要步骤形成的半导体结构的示意图。
请参阅图1及图2A，步骤S10，提供基底200，所述基底200具有第一类型阱区W1及第二类型阱区W2。
在本实施例中，所述基底200包括衬底201及设置在所述衬底201内的浅沟槽隔离结构202(Shallow Trench Isolation，STI)，所述浅沟槽隔离结构202将所述衬底201分隔为多个彼此独立的有源区，在一些实施例中，对所述有源区进行第一类型掺杂及第二类型掺杂，形成所述第一类型阱区W1及所述第二类型阱区W2。
所述衬底201可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等；所述衬底201还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，所述衬底201还可以为叠层结构，例如硅/锗硅叠层等。另外，所述衬底201还可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；所述衬底201中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或二极管等。在本实施例中，以所述衬底201为硅衬底为例进行说明。衬底201内部还可以包括其他器件结构，例如金属布线结构等，但由于与本公开实施例无关，所以不绘示。
所述浅沟槽隔离结构202可为单层或者多层复合结构，例如，在一些实施例中，浅沟槽隔离结构202为氧化物隔离结构，在另一些实施例中，浅沟槽隔离结构202为氧化硅隔离结构与氮化物隔离结构的复合结构。
所述第一类型阱区W1与所述第二类型阱区W2为掺杂类型不同的阱区。例如，在本实施例中，所述第一类型阱区W1为N型阱区，所述第二类型阱区W2为P型阱区，在另一些实施例中，所述第一类型阱区W1为P型阱区，所述第二类型阱区W2为N型阱区。所述P型阱区是指衬底201内掺杂有P型杂的区域，P型杂质包括但不限于硼(B)或镓(Ga)。 所述N型阱区是指衬底201内掺杂有N型杂质的区域，N型杂质包括但不限于磷(P)或砷(As)。
作为示例，本公开实施例提供一种形成所述基底200的方法。所述方法包括：
提供衬底201，并在所述衬底201内形成浅沟槽。例如，在一些实施例中，于所述衬底201表面形成图案化的掩膜层，利用所述掩膜层作为遮挡，刻蚀所述衬底201，以在所述衬底201内形成浅沟槽。所述浅沟槽将所述衬底201分隔为多个独立的区域，所述区域为所述有源区。
在所述浅沟槽内填充隔离材料，形成所述浅沟槽隔离结构202。填充隔离材料的方法包括但不限于化学气相沉积、原子层沉积等。
对所述有源区进行掺杂，形成所述第一类型阱区W1及所述第二类型阱区W2。在一些实施例中，可采用离子注入工艺对所述有源区进行掺杂。例如，采用离子注入工艺在所述有源区的预设区域注入磷离子形成所述第一类型阱区W1，所述第一类型阱区W1为N型阱区，采用离子注入工艺在所述有源区的预设区域注入硼离子形成第二类型阱区W2，所述第二类型阱区W2为P型阱区。
请继续参阅图2A，在一些实施例中，在所述基底200上还形成第一栅极结构210及第二栅极结构220。所述第一栅极结构210设置在所述第二类型阱区W2表面，所述第二栅极结构220设置在所述第一类型阱区W1表面。所述第一栅极结构210与所述第二栅极结构220均包括栅介质层及设置在所述栅介质层表面的栅线，所述栅介质层设置在所述有源区表面，作为所述栅线与所述有源区之间的隔离结构。所述栅介质层包括但不限于氧化硅层或高K介质层，所述栅线包括但不限于多晶硅栅线、金属氮化钛层与钨层构成的复合栅线。
在一些实施例中，所述第一栅极结构210及所述第二栅极结构220的侧壁还设置有侧墙，以保护所述第一栅极结构210及第二栅极结构220、以及所述第一栅极结构210及所述第二栅极结构220覆盖的所述第二类型阱区W2及所述第一类型阱区W1。
在一些实施例中，在形成所述第一栅极结构210及所述第二栅极结构220之后，所述方法还包括如下步骤：
请参阅图2B，形成第一介质层230，所述第一介质层230覆盖所述基底200表面。在本实施例中，所述第一介质层230还覆盖所述第一栅极结构210及所述第二栅极结构220。在该步骤中，可采用化学气相沉积等工艺沉积介质材料形成所述第一介质层230。所述第一介质层230可为单层结构或者多层复合结构，例如，在一些实施例中，所述第一介质层230为氮化硅单层结构，在另一些实施例中，所述第一介质层230为氧化硅层与氮化硅层构成 的双层复合结构。在本实施例中，以所述第一介质层230为氧化硅层与氮化硅层构成的双层复合结构为例进行说明。所述氧化硅层覆盖所述基底200表面及所述第一栅极结构210与第二栅极结构220，所述氮化硅层覆盖所述氧化硅层表面。
请参阅图2C，图案化所述第一介质层230，形成第一过孔231及第二过孔232，所述第一过孔231暴露出部分所述第一类型阱区W1，所述第二过孔232暴露出部分所述第二类型阱区W2。所述第一过孔231包括两个过孔，分别作为源极过孔及漏极过孔，设置在所述第二栅极结构220的两侧，且分别暴露出所述第一类型阱区W1，所述第二过孔232包括两个过孔，分别作为源极过孔及漏极过孔，设置在所述第一栅极结构210的两侧，且分别暴露出所述第二类型阱区W2。
在该步骤中，可在所述第一介质层230表面形成图案化的掩膜层(附图中未绘示)及光刻胶层(附图中未绘示)，通过刻蚀工艺将所述掩膜层上的图案转移到所述第一介质层230上，形成所述第一过孔231及所述第二过孔232。形成所述第一过孔231及所述第二过孔232后，去除所述掩膜层及所述光刻胶层，即形成图2C所示结构。
为了增大源漏区与源漏接触的接触面积，降低源漏接触与源漏区之间接触电阻，在本实施例中，在形成所述第一过孔231及所述第二过孔232的步骤中，过刻蚀所述基底200，使所述第一过孔231及所述第二过孔232均延伸至所述基底200内，以增大所述第一类型阱区W1及所述第二类型阱区W2暴露于所述第一过孔231及所述第二过孔232的表面积，进而增大后续形成的源漏接触与源漏区的接触面积。
请一并参阅图1及图2D，步骤S11，执行第一次离子掺杂，于所述第一类型阱区W1内形成第二类型源漏区240，于所述第二类型阱区W2内形成掺杂区241。
在本实施例中，沿所述第一过孔231及第二过孔232执行所述第一次离子掺杂。由于所述第一类型阱区W1暴露于所述第一过孔231，所述第二类型阱区W2暴露于所述第二过孔232，所述基底200的其他区域被所述第一介质层230遮挡，则执行本步骤之后，在所述第一过孔231对应的所述第一类型阱区W1内形成第二类型源漏区240，在所述第二过孔232对应的所述第二类型阱区W2内形成所述掺杂区241。
在本实施例中，所述第一类型阱区W1为N型阱区，则在步骤S11中，执行P型杂质掺杂，在所述第一类型阱区W1内形成的所述第二类型源漏区240为P型区域。所述P型杂质包括但不限于硼(B)或镓(Ga)。在本实施例中，采用离子注入工艺对所述第一类型阱区W1及所述第二类型阱区W2进行P型杂质注入，形成所述第二类型源漏区240及所述掺杂区241。其中，可通过控制所述离子注入工艺时的注入剂量及能量来控制形成的第二 类型源漏区240及掺杂区241的掺杂浓度及掺杂深度。
在另一些实施例中，所述第一类型阱区W1为P型阱区，则在步骤S11中，执行N型杂质掺杂，在所述第一类型阱区W1内形成的所述第二类型源漏区240为N型区域。则在该步骤中，执行N型杂质掺杂，在所述第一类型阱区W1内形成的所述第二类型源漏区240为N型区域。所述N型杂质包括但不限于磷(P)或砷(As)。其中，可采用离子注入工艺对所述第一类型阱区W1及所述第二类型阱区W2进行N型杂质注入，形成所述第二类型源漏区240及所述掺杂区241。
进一步，在执行P型杂质掺杂的步骤中或者之前包括：执行锗离子和/或碳离子掺杂。在一些实施例中，在执行P型杂质掺杂之前仅进行锗离子或者碳离子其中之一掺杂。在另一些实施例中，在执行P型杂质掺杂之前进行锗离子掺与碳离子两种离子的掺杂，例如，先进行锗离子掺杂，再进行碳离子掺杂，或者先进行碳离子掺杂，再进行锗离子掺杂，或者锗离子与碳离子同时进行掺杂。在另一些实施例中，锗离子和/或碳离子的掺杂与硼离子掺杂在同一步骤中进行。
进行锗离子与碳离子掺杂的方法包括但不限于离子注入工艺。锗离子注入可使硅晶体非晶化，趋于不定形非晶硅，以抑制硼离子的贯穿，从而达到抑制硼离子的扩散的目的；碳离子注入可使碳离子填隙在硅晶体内的缺陷，以抑制硼离子的扩散。
请一并参阅图1及图2E，步骤S12，形成第一掩膜层250，所述第一掩膜层250覆盖所述第二类型源漏区240，且显露所述掺杂区241。
在该步骤中，所述第一掩膜层250不仅填充所述第一过孔231并覆盖所述第一过孔231底部的所述第二类型源漏区240的表面，还覆盖所述第一介质层230表面，而由于后续步骤需要通过所述第二过孔232对所述掺杂区241进行处理，因此，所述第一掩膜层250并未填充所述第二过孔232，所述第二过孔232及所述第二过孔232底部的掺杂区241显露。
作为示例，本公开实施例提供一种形成所述第一掩膜层250的方法，所述方法包括：
形成掩膜材料层，所述掩膜材料层覆盖所述第一介质层230，且填充所述第一过孔231及第二过孔232。在该步骤中，可采用化学气相沉积工艺、原子层沉积工艺等沉积所述掩膜材料层。在一些实施例中，所述掩膜材料层包括但不限于光刻胶层。
去除所述第二过孔232内的掩膜材料层，形成所述第一掩膜层250。在该步骤中，可利用光罩去除所述第二过孔232内的掩膜材料层，仅保留位于所述第一过孔231内的掩膜材料层作为所述第一掩膜层250。可以理解的是，在一些实施例中，所述第一介质层230部分表面的掩膜材料层也被保留，例如，所述第一介质层230与所述第一类型阱区W1所在的 有源区对应的表面上的所述掩膜材料层也被保留。
请一并参阅图1及图2F，步骤S13，至少去除部分所述掺杂区241。在该步骤中，以所述第一掩膜层250作为遮挡，采用干法刻蚀工艺经所述第二过孔232至少去除部分所述掺杂区241。鉴于所述干法刻蚀工艺各项异性的特性，在该步骤中，仅所述第二过孔232底部的掺杂区241被刻蚀，所述第二过孔232侧壁暴露的第一介质层230及所述基底200并未被刻蚀，不会影响后续形成的晶体管的性能。
所述掺杂区241为在执行第一次离子掺杂时形成的区域，其掺杂类型与第二类型源漏区240的掺杂类型相同，而在后续步骤中，需要在掺杂区241所在的第二类型阱区W2中形成第一类型源漏区260，所述第一类型源漏区260与第二类型源漏区240互补，也就是说，所述掺杂区241的掺杂类型与后续形成的所述第一类型源漏区260的掺杂类型互补，这使得后续在所述第二类型阱区W2中形成的晶体管的电阻较高，不利于提高晶体管的性能。而在本公开实施例中，在所述第二类型阱区W2中形成第一类型源漏区260之前先至少去除部分所述掺杂区241，从而避免因掺杂区241的存在而提高晶体管的电阻。
举例说明，在本实施例中，执行第一次离子掺杂时掺杂杂质的掺杂类型为P型，即所述掺杂区241的掺杂类型为P型，在后续步骤执行第二次离子掺杂形成第一类型源漏区260时，掺杂杂质的掺杂类型为N型，所述掺杂区241的掺杂类型与所述第一类型源漏区260的掺杂类型互补，若在形成所述第一类型源漏区260之前不去除所述掺杂区241会导致形成的NMOS晶体管的电阻较高，影响晶体管的性能。因此，该步骤至少去除部分所述掺杂区241，避免因掺杂区241的存在而增大NMOS晶体管的电阻。
在本实施例中，执行刻蚀工艺直至所述掺杂区241被完全去除，而在另外一些实施例中，执行刻蚀工艺直至去除设定深度，即刻蚀设定深度后不论所述掺杂区241是否被完全去除，均停止刻蚀。例如，在一实施例中，去除深度为3～5纳米，也就是说，刻蚀3～5纳米后不论所述掺杂区241是否被完全去除均停止刻蚀。在停止刻蚀后，所述掺杂区241可能被完全去除、可能被部分去除。
去除深度限定为3～5纳米的原因在于，一方面是，若刻蚀深度太小可能造成掺杂区241残留较多，不利于降低后续形成的晶体管电阻；另一方面是，若刻蚀深度太大，使得第一类型源漏区260表面处于较深的位置，可能导致后续形成的源漏接触与第一类型源漏区260具有不良的欧姆接触，影响晶体管的性能。
请一并参阅图1及图2G，步骤S14，执行第二次离子掺杂，于所述第二类型阱区W2内形成第一类型源漏区260，第一次离子掺杂与所述第二次离子掺杂的掺杂类型互补。
在本实施例中，以所述第一掩膜层250作为遮挡，沿所述第二过孔232执行所述第二次离子掺杂。由于所述第二类型阱区W2暴露于所述第二过孔232，所述第二类型源漏区240被所述第一掩膜层250遮挡，则执行本步骤之后，仅在所述第二过孔232对应的所述第二类型阱区W2内形成第一类型源漏区260。
其中，第一次离子掺杂与所述第二次离子掺杂的掺杂类型互补，即所述第二类型源漏区240与所述第一类型源漏区260的掺杂类型互补。例如，第一次离子掺杂的掺杂杂质的类型为P型，第二类型源漏区240的掺杂类型为P型，则第二次离子掺杂的掺杂杂质的类型为N型，第一类型源漏区260的掺杂类型为N型；再例如，第一次离子掺杂的掺杂杂质的类型为N型，第二类型源漏区240的掺杂类型为N型，则第二次离子掺杂的掺杂杂质的类型为P型，第一类型源漏区260的掺杂类型为P型。
举例说明，在本实施例中，所述第二类型阱区W2为P型阱区，则在步骤S14中，执行N型杂质掺杂，在所述第二类型阱区W2内形成的所述第一类型源漏区260为N型区域。所述N型杂质包括但不限于磷(P)或砷(As)。在本实施例中，采用离子注入工艺对所述第二类型阱区W2进行N型杂质注入，形成所述第一类型源漏区260。其中，可通过控制所述离子注入工艺时的注入剂量及能量来控制形成的第一类型源漏区260的掺杂浓度及掺杂深度。
举例说明，在另一些实施例中，所述第二类型阱区W2为N型阱区，则在步骤S14中，执行P型杂质掺杂，在所述第二类型阱区W2内形成的所述第一类型源漏区260为P型区域。所述P型杂质包括但不限于硼(B)或镓(Ga)。其中，可采用离子注入工艺对所述第二类型阱区W2进行P型杂质注入，形成所述第一类型源漏区260。
在一些实施例中，若所述掺杂区241并未被完全去除，则需要在执行第二次离子掺杂时提高掺杂离子的浓度，以避免掺杂区241的反型离子对所述第一类型源漏区260的可靠性产生影响。
请参阅图2H，去除所述第一掩膜层250，暴露出所述第一类型源漏区260及第二类型源漏区240。在该步骤中，可采用灰化工艺去除所述第一掩膜层250。在去除所述第一掩膜层250之后执行清洗步骤，以去除杂质。
在执行清洗步骤之后还包括：对所述第一类型源漏区260及所述第二类型源漏区240进行退火处理，激活掺杂杂质，并恢复因离子注入而变化的晶体结构，消除因离子注入而引起的缺陷，提高半导体器件性能。其中，所述退火处理包括但不限于快速热退火处理(Rapid Thermal Processing，RTP)。
请参阅图1及图2I，在执行退火处理后，所述方法还包括形成第一源漏接触270及第二源漏接触280的步骤。具体地说，步骤S15，形成第一源漏接触270及第二源漏接触280，所述第一源漏接触270与所述第一类型源漏区260连接，所述第二源漏接触280与所述第二类型源漏区240连接，在垂直所述半导体器件顶面的方向上，所述第一源漏接触270与所述第一类型源漏区260的连接面低于所述第二源漏接触280与所述第二类型源漏区240的连接面。
在本实施例中，在所述第一类型阱区W1形成第二类型晶体管2，所述第二类型晶体管2为P型晶体管，所述第二类型源漏区240作为所述P型晶体管的源漏区，所述第二栅极结构220作为所述P型晶体管的栅极，所述第二源漏接触280与所述第二类型源漏区240连接，作为所述P型晶体管源漏区的引出结构；在所述第二类型阱区W2形成第一类型晶体管1，所述第一类型晶体管1为N型晶体管，所述第一类型源漏区260作为所述N型晶体管的源漏区，所述第一栅极结构210作为所述N型晶体管的栅极，所述第一源漏接触270与所述第一类型源漏区260连接，作为所述N型晶体管源漏区的引出结构。可以理解的是，在一些实施例中，所述第一栅极结构210可与所述第二栅极结构220连接，所述第一源漏接触270中的漏电极与所述第二源漏接触280中的漏电极连接，以形成CMOS晶体管，所述CMOS晶体管可作为反相器使用。
作为示例，本公开实施例提供一种形成所述第一源漏接触270及第二源漏接触280的方法，所述方法包括：退火处理后，对所述第一类型源漏区260及第二类型源漏区240进行金属化处理及退火处理，形成金属硅化物层290，以提高第一源漏接触270与第一类型源漏区260及第二源漏接触280与第二类型源漏区240的接触性能，有利于降低接触电阻，提升半导体器件的性能。所述金属硅化物包括但不限于钴层或硅镍层。在金属化处理后，在所述第一过孔231及第二过孔232内填充金属，形成所述第一源漏接触270及第二源漏接触280。所述源漏接触的材料包括但不限于钴(Co)、镍(Ni)、钛(Ti)、钨(W)、钽(Ta)、钛化钽(TaTi)、氮化钛(TiN)、氮化钨(WN)、铜(Cu)及铝(Al)等金属材料中的一种或几种。
本公开实施例提供的制备方法在执行第一次离子掺杂时不使用光罩，在第一类型阱区W1形成第二类型源漏区240及在第二类型阱区W2形成掺杂区241，然后去除所述掺杂区241，再采用光罩进行第二次离子掺杂，在第二类型阱区W2形成第一类型源漏区260，从而实现仅采用一道光罩就能形成具有NMOS晶体管与PMOS晶体管的CMOS晶体管的目的，大大降低了生产成本，同时也能够使NMOS晶体管或者PMOS晶体管保持较低的阻值，保证了CMOS晶体管的性能不受损失。
本公开实施例还提供一种采用上述制备方法制备的半导体器件。请参阅图2A～图2I，所述半导体器件包括第一类型晶体管1、第二类型晶体管2、第一源漏接触270及第二源漏接触280。所述第一类型晶体管1与所述第二类型晶体管2为互补晶体管，在本实施例中，以所述第一类型晶体管1为N型晶体管，所述第二类型晶体管2为P型晶体管进行说明，在另一些实施例中，所述第一类型晶体管1为P型晶体管，所述第二类型晶体管2为N型晶体管。
所述第一类型晶体管1具有第一类型源漏区260，所述第二类型晶体管2具有第二类型源漏区240，所述第一类型源漏区260与所述第二类型源漏区240的掺杂类型互补。例如，在本实施例中，所述第一类型源漏区260为N型，所述第二类型源漏区240为P型。
所述第一源漏接触270与所述第一类型源漏区260连接，作为所述第一类型晶体管1源漏区的引出结构，所述第二源漏接触280与所述第二类型源漏区240连接，作为所述第二类型晶体管2源漏区的引出结构。
请参阅图3，其为图2I中虚线框A所圈示区域的放大图，在垂直所述半导体器件顶面的方向上(如图2I中的D方向)，所述第一源漏接触270与所述第一类型源漏区260的连接面低于所述第二源漏接触280与所述第二类型源漏区240的连接面。在本实施例中，由于所述第一源漏接触270与所述第一类型源漏区260之间、所述第二源漏接触280与所述第二类型源漏区240之间存在金属硅化物层290，则在垂直所述半导体器件顶面的方向上，所述金属硅化物层290与第一类型源漏区260的交界面C1低于所述金属硅化物层290与第二类型源漏区240的交界面C2。
在一些实施例中，所述第一类型源漏区260具有P型杂质及N型杂质，所述N型杂质浓度大于所述P型杂质浓度，以避免P型杂质对所述第一类型源漏区260的可靠性产生影响。
在一些实施例中，所述第一源漏接触270与所述第一类型源漏区260的连接面，和所述第二源漏接触280与所述第二类型源漏区240的连接面之间的高度差为3～5纳米。具体说，在本实施例中，所述金属硅化物层290与第一类型源漏区260的交界面C1与所述金属硅化物层290与第二类型源漏区240的交界面C2的高度差H1为3～5纳米。
在一些实施例中，所述半导体器件还包括基底200及第一介质层230。
所述基底200具有第一类型阱区W1及第二类型阱区W2，所述第一类型源漏区260位于所述第二类型阱区W2内，所述第二类型源漏区240位于所述第一类型阱区W1内。其中，所述第一类型源漏区260与所述第二类型阱区W2的掺杂类型互补，所述第二类型源 漏区240与所述第二类型阱区W2的掺杂类型互补。
所述基底200包括衬底201及浅沟槽隔离结构202，所述浅沟槽隔离结构202将所述衬底201分隔为多个彼此独立的有源区，对所述有源区进行第一类型掺杂及第二类型掺杂，形成所述第一类型阱区W1及所述第二类型阱区W2，在所述第一类型阱区W1及所述第二类型阱区W2内进行重掺杂形成所述第一类型源漏区260及所述第二类型源漏区240。
所述第一介质层230覆盖所述基底200，所述第一源漏接触270贯穿所述第一介质层230与所述第一类型源漏区260连接，所述第二源漏接触280贯穿所述第一介质层230与所述第二类型源漏区240连接。其中，在一些实施例中，请参阅图3，所述第一源漏接触270与所述第一类型源漏区260的连接面E1低于所述基底200与所述第一介质层230的接触面E2，且所述第二源漏接触280与所述第二类型源漏区240的连接面E3低于所述基底200与所述第一介质层230的接触面E2。也就是说，所述第一源漏接触270及所述第二源漏接触280延伸至所述基底200内。
在本实施例中，所述第一类型晶体管1具有第一栅极结构210，所述第一栅极结构210设置在所述第二类型阱区W2表面，所述第一栅极结构210对应的第二类型阱区W2作为所述第一类型晶体管1的沟道区，所述第二类型晶体管2具有第二栅极结构220，所述第二栅极结构220设置在所述第一类型阱区W1表面，所述第二栅极结构220对应的第一类型阱区W1作为所述第二类型晶体管2的沟道区。
所述第一栅极结构210与所述第二栅极结构220均包括栅介质层及设置在所述栅介质层表面的栅线，所述栅介质层设置在所述有源区表面，作为所述栅线与所述有源区之间的隔离结构。所述栅介质层包括但不限于氧化硅层或高K介质层，所述栅线包括但不限于多晶硅栅线、金属氮化钛层与钨层构成的复合栅线。在一些实施例中，所述第一栅极结构210可与所述第二栅极结构220连接，所述第一源漏接触270中的漏电极与所述第二源漏接触280中的漏电极连接，以形成CMOS晶体管，所述CMOS晶体管可作为反相器使用。
本公开实施例提供的半导体器件制造成本低，且同时也能够使NMOS晶体管或者PMOS晶体管保持较低的阻值，保证了CMOS晶体管的性能不受损失。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (18)

  1. 一种半导体器件的制备方法，包括：
    提供基底，所述基底具有第一类型阱区及第二类型阱区；
    执行第一次离子掺杂，于所述第一类型阱区内形成第二类型源漏区，于所述第二类型阱区内形成掺杂区；
    形成第一掩膜层，所述第一掩膜层覆盖所述第二类型源漏区，且显露所述掺杂区；
    至少去除部分所述掺杂区；
    执行第二次离子掺杂，于所述第二类型阱区内形成第一类型源漏区，所述第一次离子掺杂与所述第二次离子掺杂的掺杂类型互补；
    形成第一源漏接触及第二源漏接触，所述第一源漏接触与所述第一类型源漏区连接，所述第二源漏接触与所述第二类型源漏区连接，在垂直所述半导体器件顶面的方向上，所述第一源漏接触与所述第一类型源漏区的连接面低于所述第二源漏接触与所述第二类型源漏区的连接面。
  2. 如权利要求1所述的半导体器件的制备方法，其中，所述第一类型阱区为N型阱区，所述第二类型阱区为P型阱区，所述执行第一次离子掺杂的步骤包括执行P型杂质掺杂，所述执行第二次离子掺杂包括执行N型杂质掺杂。
  3. 如权利要求2所述的半导体器件的制备方法，其中，所述执行P型杂质掺杂的步骤中或者之前包括：执行锗离子和/或碳离子掺杂。
  4. 如权利要求1所述的半导体器件的制备方法，其中，所述第一类型阱区为P型阱区，所述第二类型阱区为N型阱区，所述执行第一次离子掺杂的步骤包括执行N型杂质掺杂，所述执行第二次离子掺杂包括执行P型杂质掺杂。
  5. 如权利要求1所述的半导体器件的制备方法，其中，至少去除部分所述掺杂区的步骤包括：
    采用干法刻蚀工艺至少去除部分所述掺杂区。
  6. 如权利要求1所述的半导体器件的制备方法，其中，至少去除部分所述掺杂区的步骤中，去除深度为3～5纳米。
  7. 如权利要求1所述的半导体器件的制备方法，其中，在所述执行第一次离子掺杂的步骤之前包括：
    形成第一介质层，所述第一介质层覆盖所述基底表面；
    图案化所述第一介质层，形成第一过孔及第二过孔，所述第一过孔暴露出部分所述第一类型阱区，所述第二过孔暴露出部分所述第二类型阱区；
    在所述执行第一次离子掺杂的步骤中，沿所述第一过孔及第二过孔执行所述第一次离子掺杂；
    在所述去除所述掺杂区的步骤中，沿所述第二过孔去除所述掺杂区；
    在所述执行第二次离子掺杂的步骤中，沿所述第二过孔执行第二次离子掺杂。
  8. 如权利要求7所述的半导体器件的制备方法，其中，在图案化所述第一介质层，形成第一过孔及第二过孔的步骤中，过刻蚀所述基底，使所述第一过孔及所述第二过孔均延伸至所述基底内。
  9. 如权利要求7所述的半导体器件的制备方法，其中，所述形成第一掩膜层的步骤包括：
    形成掩膜材料层，所述掩膜材料层覆盖所述第一介质层，且填充所述第一过孔及第二过孔；
    去除所述第二过孔内的掩膜材料层，形成所述第一掩膜层。
  10. 如权利要求7所述的半导体器件的制备方法，其中，在所述形成第一介质层之前还包括如下步骤：在所述基底上形成第一栅极结构及第二栅极结构，所述第一栅极结构设置在所述第二类型阱区表面，所述第二栅极结构设置在所述第一类型阱区表面。
  11. 如权利要求1所述的半导体器件的制备方法，其中，所述执行第二次离子掺杂的步骤之后包括：
    去除所述第一掩膜层，显露所述第二类型源漏区；
    形成第一源漏接触及第二源漏接触，所述第一源漏接触与所述第一类型源漏区连接，所述第二源漏接触与所述第二类型源漏区连接。
  12. 如权利要求11所述的半导体器件的制备方法，其中，所述去除所述第一掩膜层的步骤之后包括：对所述第一类型源漏区及所述第二类型源漏区进行退火处理。
  13. 一种半导体器件，包括：
    第一类型晶体管，具有第一类型源漏区；
    第二类型晶体管，具有第二类型源漏区，所述第一类型晶体管与所述第二类型晶体管为互补晶体管；
    第一源漏接触，与所述第一类型源漏区连接；
    第二源漏接触，与所述第二类型源漏区连接，在垂直所述半导体器件顶面的方向上，所述第一源漏接触与所述第一类型源漏区的连接面低于所述第二源漏接触与所述第二类型源漏区的连接面。
  14. 如权利要求13所述的半导体器件，其中，所述第一源漏接触与所述第一类型源漏区的 连接面，和所述第二源漏接触与所述第二类型源漏区的连接面之间的高度差为3～5纳米。
  15. 如权利要求13所述的半导体器件，其中，所述第一类型源漏区具有P型杂质及N型杂质，所述N型杂质浓度大于所述P型杂质浓度。
  16. 如权利要求13所述的半导体器件，其中，所述第一类型晶体管为N型晶体管，所述第二类型晶体管为P型晶体管，或者所述第一类型晶体管为P型晶体管，所述第二类型晶体管为N型晶体管。
  17. 如权利要求13所述的半导体器件，其中，所述半导体器件还包括：基底，具有第一类型阱区及第二类型阱区，所述第一类型源漏区位于所述第二类型阱区内，所述第二类型源漏区位于所述第一类型阱区内；
    第一介质层，覆盖所述基底，所述第一源漏接触贯穿所述第一介质层与所述第一类型源漏区连接，所述第二源漏接触贯穿所述第一介质层与所述第二类型源漏区连接，所述第一源漏接触与所述第一类型源漏区的连接面低于所述基底与所述第一介质层的接触面，且所述第二源漏接触与所述第二类型源漏区的连接面低于所述基底与所述第一介质层的接触面。
  18. 如权利要求13所述的半导体器件，其中，所述第一类型晶体管具有第一栅极结构，所述第一栅极结构设置在所述第二类型阱区表面，所述第一栅极结构对应的第二类型阱区作为所述第一类型晶体管的沟道区，所述第二类型晶体管具有第二栅极结构，所述第二栅极结构设置在所述第一类型阱区表面，所述第二栅极结构对应的第一类型阱区作为所述第二类型晶体管的沟道区。
PCT/CN2023/070660 2022-10-13 2023-01-05 半导体器件及其制备方法 Ceased WO2024077803A1 (zh)

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