WO2024077800A1 - 时钟生成电路及存储器 - Google Patents

时钟生成电路及存储器 Download PDF

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Publication number
WO2024077800A1
WO2024077800A1 PCT/CN2023/070338 CN2023070338W WO2024077800A1 WO 2024077800 A1 WO2024077800 A1 WO 2024077800A1 CN 2023070338 W CN2023070338 W CN 2023070338W WO 2024077800 A1 WO2024077800 A1 WO 2024077800A1
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unit
output
clock
gate
input end
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PCT/CN2023/070338
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English (en)
French (fr)
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唐玉玲
王琳
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Definitions

  • the present disclosure relates to memory technology, and more particularly to a clock generation circuit and a memory.
  • DRAM dynamic random access memory
  • chip select testing CS training
  • CS training chip select testing
  • a frequency-divided sampling clock with a period that meets the sampling requirements is used to sample the chip select signal, obtain the operation result of the complete chip select signal, and output the result according to the output clock. Therefore, how to generate an output clock suitable for chip select testing in a timely manner becomes a problem that needs to be solved.
  • Embodiments of the present disclosure provide a clock generation circuit and a memory.
  • the first aspect of the present disclosure provides a clock generation circuit, including: a sampling module, which is used to sample continuous chip select signals based on a sampling clock, the holding time of each data bit of the chip select signal is equal to the period of the system clock, the sampling clock includes an odd clock and an even clock with opposite phases, the period of the odd clock and the even clock is equal to twice the period of the system clock, the data obtained by sampling based on the odd clock is recorded as odd data, and the data obtained by sampling based on the even clock is recorded as even data; a detection module, connected to the sampling module, is used to output an indication signal of a first state when it is detected that the adjacent chip select signals meet a predetermined condition, otherwise it outputs an indication signal of a second state; wherein the predetermined condition includes that the data bits of the previous chip select signal are all in the first level state, and the first data bit of the next chip select signal is in the second level state; a generation module, connected to the detection module, is used to generate an output clock when the indication signal
  • each chip select signal includes four data bits.
  • the detection module includes: a first delay unit, a second delay unit, a first operation unit and a second operation unit; the first delay unit is connected to the sampling module, and is used to delay the output of the odd data in sequence according to a predetermined time interval to obtain the first delayed odd data, the second delayed odd data, the third delayed odd data, the fourth delayed odd data and the fifth delayed odd data; the second delay unit is connected to the sampling module, and is used to delay the output of the even data in sequence according to the time interval to obtain the first delayed even data, the second delayed even data, the third delayed even data, the fourth delayed even data and the fifth delayed even data; the input end of the first operation unit is connected to the first delay unit and the second delay unit, and the first operation unit is used to receive the first delayed odd data, the second delayed even data, the third delayed odd data, the fourth delayed even data and the fifth delayed odd data, and detect whether the predetermined condition is met; the output end of the first operation unit is connected to the generation module; the input end of the second operation unit is connected to
  • the first operation unit includes: a first NOT gate, a first NAND gate, a second NAND gate, and a first NOR gate; the input end of the first NOT gate receives the first delayed odd data, and the output end of the first NOT gate is connected to the first input end of the first NAND gate; the second input end of the first NAND gate receives the second delayed even data, the third input end of the first NAND gate receives the third delayed odd data, and the output end of the first NAND gate is connected to the first input end of the first NOR gate; the first input end of the second NAND gate receives the fourth delayed even data, the second input end of the second NAND gate receives the fifth delayed odd data, and the output end of the second NAND gate is connected to the second input end of the first NOR gate; the output end of the first NOR gate is connected to the generating module
  • the blocks are connected; the second operation unit includes: a second NOT gate, a third NAND gate and a fourth NAND gate, and a second NOR gate; the input end of
  • the first delay unit includes: a plurality of first delay sub-units connected in series; the input end of the first first delay sub-unit is connected to the sampling module, for receiving first delayed odd data generated based on odd data; the input end of each first delay sub-unit is connected to the output end of the previous first delay sub-unit, and each first delay sub-unit is used to output the received data after a time interval;
  • the second delay unit includes: a plurality of second delay sub-units connected in series; the input end of the first second delay sub-unit is connected to the sampling module, for receiving first delayed even data generated based on even data; the input end of each second delay sub-unit is connected to the output end of the previous second delay sub-unit, and each second delay sub-unit is used to output the received data after a time interval.
  • the output clock includes a first output clock and a second output clock with opposite phases; at the same time, the first output clock or the second output clock is valid; wherein the validity of any output clock indicates that the sampling clock corresponding to the output clock first samples the next chip selection signal in which the first data bit is in a low level state.
  • the generation module includes: a selection unit, a first generation unit and a second generation unit; the selection unit is connected to the first operation unit and the second operation unit; the selection unit is used to output a valid first enable signal to the first generation unit in response to the first operation unit first outputting an indication signal of the first state; and, in response to the second operation unit first outputting an indication signal of the first state, output a valid second enable signal to the second generation unit; the enable end of the first generation unit is connected to the selection unit, the first generation unit receives an odd clock, and the first generation unit is used to divide the odd clock in response to the first enable signal being valid, and output a first output clock; the enable end of the second generation unit is connected to the selection unit, the second generation unit receives an even clock, and the second generation unit is used to divide the even clock in response to the second enable signal being valid, and output a second output clock.
  • the first generating unit includes a first trigger and a third delay unit; the input end of the first trigger is connected to the inverting output end of the first trigger, the clock end of the first trigger receives an odd clock, the reset end of the first trigger is the enable end of the first generating unit, and the output end of the first trigger is connected to the input end of the third delay unit; the third delay unit is used to delay the signal output by the first trigger to obtain a first output clock; the second generating unit includes a second trigger and a fourth delay unit; the input end of the second trigger is connected to the inverting output end of the second trigger, the clock end of the second trigger receives an even clock, the reset end of the second trigger is the enable end of the second generating unit, and the output end of the second trigger is connected to the input end of the fourth delay unit; the fourth delay unit is used to delay the signal output by the second trigger to obtain a second output clock.
  • the first generating unit also includes a fifth delay unit; the input end of the fifth delay unit is connected to the output end of the first trigger, and the fifth delay unit is used to invert and delay the signal output by the first trigger to obtain the inverted signal of the first output clock; the second generating unit also includes a sixth delay unit; the input end of the sixth delay unit is connected to the output end of the second trigger, and the sixth delay unit is used to invert and delay the signal output by the second trigger to obtain the inverted signal of the second output clock.
  • the selection unit includes: a first transmission unit, a second transmission unit and a control unit; the input end of the first transmission unit receives a first high-level signal, the control end of the first transmission unit receives an indication signal output by the first operation unit, and the output end of the first transmission unit is connected to an enable end of the first generation unit and the control unit; the first transmission unit is used to transmit the first high-level signal to the control unit when the indication signal output by the first operation unit is in a first state; the input end of the second transmission unit receives a second high-level signal, the control end of the second transmission unit receives an indication signal output by the second operation unit, and the output end of the second transmission unit is connected to an enable end of the second generation unit and the control unit; the second transmission unit is used to transmit the second high-level signal to the control unit when the indication signal output by the second operation unit is in a first state; the control unit is connected to the enable end of the first transmission unit and the enable end of the second transmission unit, and is used to enable the first transmission
  • control unit includes: a third NOR gate and a fourth NOR gate; the input end of the third NOR gate is connected to the output end of the second transmission unit, and the output end of the third NOR gate is connected to the enable end of the first transmission unit; the input end of the fourth NOR gate is connected to the output end of the first transmission unit, and the output end of the fourth NOR gate is connected to the enable end of the second transmission unit.
  • control unit also includes: a first reset unit; the first reset unit includes: a seventh NOT gate and an OR gate; the input end of the seventh NOT gate receives a test mode signal, and the output end of the seventh NOT gate is connected to the first input end of the OR gate; the second input end of the OR gate receives a reset signal, and the output end of the OR gate is connected to another input end of the third OR NAND gate and another input end of the fourth OR NAND gate.
  • the generation module also includes: a second reset unit; the second reset unit includes: an eighth NOT gate, a ninth NOT gate, a fifth NOR gate and a sixth NOR gate; the input end of the eighth NOT gate is connected to the output end of the first transmission unit, and the output end of the eighth NOT gate is connected to the first input end of the fifth NOR gate; the second input end of the fifth NOR gate is connected to the first input end of the sixth NOR gate, and the output end of the fifth NOR gate is connected to the enable end of the first generation unit; the input end of the ninth NOT gate is connected to the output end of the second transmission unit, and the output end of the ninth NOT gate is connected to the second input end of the sixth NOR gate; the first input end of the sixth NOR gate receives a reset signal, and the output end of the sixth NOR gate is connected to the enable end of the second generation unit.
  • the second reset unit includes: an eighth NOT gate, a ninth NOT gate, a fifth NOR gate and a sixth NOR gate; the input end of the eighth NOT
  • the second aspect of the present disclosure provides a memory, comprising: a clock generation circuit and a chip test circuit as described above; wherein the clock generation circuit and the chip test circuit are connected to provide an output clock for the chip test circuit, and the chip test circuit is used to perform a chip select signal test on the memory.
  • the sampling module samples the continuous chip select signal based on the odd clock and the even clock to obtain odd data and even data
  • the detection module detects whether the adjacent chip select signals meet the predetermined conditions based on the odd data and the even data.
  • the generation module starts to generate the output clock.
  • the predetermined conditions that can characterize the start of the chip select test can be set according to the actual test, and the data bits in the chip select signal can be collected, detected and timely generated based on the odd clock and the even clock whose clock cycle is twice the system clock cycle.
  • the output clock can be generated in time while ensuring accurate and reliable sampling.
  • the output clock can cooperate with the accurate output of the chip select test results to achieve accurate and reliable chip select testing.
  • FIG1 is an example diagram of a memory architecture according to an embodiment of the present disclosure
  • FIG2 is a structural diagram of a storage unit according to an embodiment of the present disclosure.
  • FIG3 is an example storage topology architecture
  • FIG4 is a structural diagram of a clock generation circuit provided by an embodiment
  • FIGS. 5 and 6 are sample timing diagrams
  • FIG7 is a structural diagram of a detection module provided by an embodiment
  • FIGS 8 and 9 are timing diagrams of data sequences
  • FIG10 is a diagram showing an exemplary structure of a first operation unit and a second operation unit provided by an embodiment
  • 11 and 12 are structural diagrams of a first delay unit and a second delay unit provided as examples;
  • 13 to 16 are diagrams showing examples of the structure of the generation module.
  • FIG1 is an example diagram of the architecture of a memory device according to an embodiment of the present disclosure.
  • DRAM taking DRAM as an example, it includes a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a memory array.
  • the memory array is mainly composed of word lines, bit lines, and memory cells.
  • the word lines in the memory array extend in the row direction, and the bit lines in the memory array extend in the column direction.
  • the intersection of the word lines and the bit lines is the memory cell of the memory array.
  • FIG2 is a structural example diagram of a storage unit according to an embodiment of the present disclosure.
  • the storage unit is mainly composed of a transistor M and a capacitor C.
  • the capacitor is used to store data, and the transistor is used to turn off or on according to the state of the word line.
  • a certain storage cell can be activated by controlling the row and column to achieve access to the storage cell.
  • the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder, and accordingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa.
  • the write scenario as an example: when data needs to be written to a certain storage cell, such as writing 1.
  • the word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.
  • FIG3 is an example of a storage topology architecture. It should be noted that the figure is only an example. There are multiple chip topology architectures in the related art, such as but not limited to dual T architecture, Fly-By topology architecture, etc., which are not limited here. In combination with the example shown in the figure, when a certain storage unit needs to be accessed, the storage chip where the storage unit is located must be selected first, that is, chip selection is performed.
  • the chip select signal corresponding to a certain storage chip is latched at a high level, all commands are ignored, that is, the storage chip is not selected; on the contrary, if it is at a low level, the storage chip is selected and the command response can be executed. Then, the corresponding storage unit is selected from the selected chip based on the address information, so as to achieve access to the storage unit, such as data access. It can be seen that the chip select signal affects whether the storage unit to be accessed can be successfully addressed. Therefore, relevant content about chip select signal testing is stipulated in the relevant standards. As an example, during the test process, a sample signal is sent to the memory, and the memory performs calculations based on the sampled chip select signal to obtain a calculation result. If the calculation result is consistent with the standard result, it means that the memory can receive the chip select signal normally and the CS test passes; otherwise, it means that the memory cannot correctly receive the chip select signal.
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • CSTM chip select test mode
  • MPC Multi Purpose Command
  • odd clocks and even clocks with a clock cycle twice the system clock cycle are used to sample and calculate chip select signals, and the calculation results are output in response to the output clock.
  • the output clock here is used to capture the calculation results obtained based on the complete chip select signal and output the calculation results to implement chip select signal testing, so it is necessary to ensure that when the chip select test starts, an accurate output clock is provided in time.
  • FIG. 4 is a structural example diagram of a clock generation circuit provided by an embodiment. As shown in FIG. 4 , the clock generation circuit includes:
  • the sampling module 11 is used to sample the continuous chip selection signal based on the sampling clock.
  • the holding time of each data bit of the chip selection signal is equal to the period of the system clock.
  • the sampling clock includes an odd clock and an even clock with opposite phases.
  • the period of the odd clock and the even clock is equal to twice the period of the system clock.
  • the data obtained by sampling based on the odd clock is recorded as odd data
  • the data obtained by sampling based on the even clock is recorded as even data.
  • the detection module 12 is connected to the sampling module 11, and is used to output an indication signal of a first state when it is detected that the adjacent chip selection signal meets a predetermined condition, otherwise output an indication signal of a second state; wherein the predetermined condition includes that the data bits of the previous chip selection signal are all in the first level state, and the first data bit of the next chip selection signal is in the second level state;
  • the generation module 13 is connected to the detection module and is used to generate an output clock when the indication signal is in the first state; wherein the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock of the subsequent chip select signal that first samples the first data bit as a low level state.
  • the chip test circuit provided in this embodiment can be applied to various memories, and as an example, can be applied to, including but not limited to, double data rate synchronous dynamic random access memory (DDR), etc.
  • DDR double data rate synchronous dynamic random access memory
  • Each chip select signal includes at least one data bit.
  • each chip select signal includes four data bits.
  • DDR5 an example is given in combination with actual scenarios: when a CS test is required, the CSTM mode can be started.
  • an odd clock and an even clock with opposite phases and a period of twice the system clock period are used for sampling, and the corresponding sampled signals are called odd data and even data, respectively, so as to provide sufficient sampling windows for the sampling of the chip select signal, avoid sampling errors and sampling failures, and ensure the accuracy of the CS test.
  • the chip select signal can be sampled at the rising edge of the odd clock and the even clock.
  • the "odd data” and “even data” here are just the names of the data collected in response to the odd clock and the even clock, and do not limit the specific content of the data actually sampled or the parity attributes in the chip select signal.
  • the chip select test operation is performed based on the odd data and to obtain the operation result.
  • the output clock is used to control when the operation result is output. This is because, based on the odd data and the even data, a complete chip select signal cannot always be formed, but a complete chip select signal is formed in a specific period of time, such as after the last data bit of the chip select signal is sampled until the sampling of the new chip select signal begins.
  • the output clock is used to control the output of the calculation results in a specific period of time, while ignoring the calculation results obtained in other periods of time, so as to ensure the accuracy of the test results.
  • the output clock is provided in time by setting a predetermined condition that can characterize the start of the chip selection test.
  • the setting object of the predetermined condition here is the chip selection signal, that is, when the data of the chip selection signal meets the predetermined condition, it indicates that the chip selection test is started.
  • the predetermined condition can be set in advance, and the chip selection signal is provided based on the predetermined condition when the chip selection signal is provided later, so as to identify whether the test is started. In practical applications, relevant content about the chip selection signal test is specified in the relevant standards.
  • the chip selection signal after receiving the instruction indicating entering the CSTM mode, before the sample signal of the chip selection signal is input, the chip selection signal will be controlled to maintain a high level for a period of time, and then the real chip selection test will be started, that is, the sample signal of the chip selection signal is input, and the calculation is performed based on the sampled chip selection signal and the calculation result is output. Therefore, in an example, the predetermined condition can include that the data bits of the previous chip selection signal are all 1, and the first data bit of the next chip selection signal is 0, so that it is not necessary to adjust other signals, and it is possible to accurately identify when the chip selection test starts.
  • Figures 5 and 6 are timing example diagrams of sampling.
  • CS is the chip select signal
  • CLK is the system clock
  • CLK_E is the even clock
  • CLK_O is the odd clock.
  • the odd data obtained based on the odd clock sampling is ODD
  • the even data obtained based on the even clock sampling is EVEN.
  • two situations are shown in the figure, one situation is that the chip select test is detected first in response to the odd clock; the other situation is that the chip select test is detected first in response to the even clock.
  • FIG. 7 is a structural example diagram of a detection module provided by an embodiment.
  • the detection module 12 includes: a first delay unit 21, a second delay unit 22, a first operation unit 23, and a second operation unit 24;
  • the first delay unit 21 is connected to the sampling module 11, and is used to delay the output of the odd data ODD in sequence according to a predetermined time interval to obtain the first delayed odd data ODD1, the second delayed odd data ODD2, the third delayed odd data ODD3, the fourth delayed odd data ODD4 and the fifth delayed odd data ODD5;
  • the second delay unit 22 is connected to the sampling module 11, and is used to delay and output the even data EVEN in sequence according to the time interval to obtain the first delayed even data EVEN1, the second delayed even data EVEN2, the third delayed even data EVEN3, the fourth delayed even data EVEN4 and the fifth delayed even data EVEN5;
  • the input end of the first operation unit 23 is connected to the first delay unit 21 and the second delay unit 22.
  • the first operation unit 23 is used to receive the first delayed odd data ODD1, the second delayed even data EVEN2, the third delayed odd data ODD3, the fourth delayed even data EVEN4 and the fifth delayed odd data ODD5, and detect whether a predetermined condition is met; the output end of the first operation unit 23 is connected to the generation module 13;
  • the input end of the second operation unit 24 is connected to the first delay unit 21 and the second delay unit 22.
  • the second operation unit 24 is used to receive the first delayed even data EVEN1, the second delayed odd data ODD2, the third delayed even data EVEN3, the fourth delayed odd data ODD4 and the fifth delayed even data EVEN5, and detect whether a predetermined condition is met; the output end of the second operation unit 23 is connected to the generation module 13.
  • the time interval is one system clock cycle.
  • Figures 8 and 9 are timing example diagrams of data sequences.
  • the data sequence is generated by the first delay unit and the second delay unit based on the odd data and even data obtained by sampling.
  • the data sequence includes ODD1 ⁇ ODD5 output by the first delay unit and EVEN1 ⁇ EVEN5 output by the second delay unit.
  • the odd clock and the even clock are used to sample the chip select signal in this embodiment, before performing the chip select test, it is necessary to first integrate the previous chip select signal (four data bits) and the first data bit of the subsequent chip select signal based on the odd data and the even data obtained by sampling.
  • the chip select signal with the first data bit of 0 is the first sample signal.
  • the first operation unit and the second operation unit correspond to the two situations mentioned above respectively. Combined with the example of Figure 8, the first operation unit first detects that the current five data bits meet the predetermined conditions in response to the odd clock in the sampling module, that is, the received fifth delayed odd data ODD5, fourth delayed even data EVEN4, third delayed odd data ODD3, and second delayed even data EVEN2 are a chip select signal, each data bit is 1, and the first data bit D0 of the next chip select signal is 0.
  • FIG10 is a structural example diagram of the first operation unit and the second operation unit provided by an embodiment.
  • the first operation unit includes 23: a first NOT gate 231, a first NAND gate 232 and a second NAND gate 233, and a first NOR gate 234;
  • the input end of the first NOT gate 231 receives the first delayed odd data ODD1, and the output end of the first NOT gate 231 is connected to the first input end of the first NAND gate 232; the second input end of the first NAND gate 232 receives the second delayed even data EVEN2, the third input end of the first NAND gate 232 receives the third delayed odd data ODD3, and the output end of the first NAND gate 232 is connected to the first input end of the first NOR gate 234; the first input end of the second NAND gate 233 receives the fourth delayed even data EVEN4, the second input end of the second NAND gate 233 receives the fifth delayed odd data ODD5, and the output end of the second NAND gate 233 is connected to the second input end of the first NOR gate 234; the output end of the first NOR gate 234 is connected to the generation module 13;
  • the second operation unit 24 includes: a second NOT gate 241, a third NAND gate 242 and a fourth NAND gate 243, and a second NOR gate 244; the input end of the second NOT gate 241 receives the first delayed even data EVEN1, and the output end of the second NOT gate 241 is connected to the first input end of the third NAND gate 242; the second input end of the third NAND gate 242 receives the second delayed odd data ODD2, the third input end of the third NAND gate 242 receives the third delayed even data EVEN3, and the output end of the third NAND gate 242 is connected to the first input end of the second NOR gate 244; the first input end of the fourth NAND gate 243 receives the fourth delayed odd data ODD4, the second input end of the fourth NAND gate 243 receives the fifth delayed even data EVEN5, and the output end of the fourth NAND gate 243 is connected to the second input end of the second NOR gate 244; the output end of the second NOR gate 244 is connected to the generation module 13.
  • the operation result output by the operation module represents whether the predetermined conditions are currently met.
  • the operation result output by the operation module represents whether the predetermined conditions are currently met.
  • the current ODD5, EVEN4, ODD3 and EVEN2 are all 1, and ODD1 is 0.
  • ODD1 outputs 1 through the first NOT gate, and ODD3 and EVEN2, which are 1, are input into the first NAND gate for NAND operation, and the first NAND gate outputs 0 to the first NOR gate;
  • ODD5 and EVEN4 which are 1, are input into the second NAND gate for NAND operation, and the second NAND gate outputs 0 to the first NOR gate; accordingly, the two inputs of the first NOR gate are both 0, and the first NOR gate outputs a calculation result of 1, which represents that the predetermined conditions are currently met, that is, the five consecutive data bits are 11110.
  • the first operation unit and the second operation unit are implemented by conventional devices such as NOT gates, NAND gates, and NOR gates, thereby effectively simplifying the circuit structure and reducing costs while ensuring timely and accurate generation of the output clock.
  • the operation module in order to detect whether five consecutive data bits meet a predetermined condition based on the sampled odd data and even data, the operation module first delays the odd data and the even data to obtain multiple data sequences, and then uses these multiple data sequences to combine into five consecutive data bits for operation.
  • Figure 11 is a structural example diagram of the first delay unit and the second delay unit provided by an embodiment.
  • the first delay unit 21 includes: a plurality of first delay sub-units 211 connected in series; the input end of the first first delay sub-unit 211 is connected to the sampling module 11, for receiving the first delayed odd data ODD1 generated based on the odd data ODD; the input end of each first delay sub-unit 211 is connected to the output end of the previous first delay sub-unit 211, and each first delay sub-unit 211 is used to output the received data after a time interval;
  • the second delay unit 22 includes: a plurality of second delay sub-units 221 connected in series; the input end of the first second delay sub-unit 221 is connected to the sampling module 11, for receiving the first delayed even data EVEN1 generated based on the even data EVEN; the input end of each second delay sub-unit 221 is connected to the output end of the previous second delay sub-unit 221, and each second delay sub-unit 221 is used to output the
  • the number of the first delay subunit and the second delay subunit can be determined according to the number of consecutive data bits specified in the predetermined condition.
  • the number of the first delay subunit and the second delay subunit is four.
  • the input end of the first delay subunit outputs the first delayed odd data ODD1 generated based on the odd data ODD
  • the output end of each first delay subunit outputs ODD2, ODD3, ODD4 and ODD5 respectively.
  • the input end of the first second delay subunit outputs the first delayed even data EVEN1 generated based on the even data EVEN
  • the output end of each second delay subunit outputs EVEN2, EVEN3, EVEN4 and EVEN5 respectively.
  • the time interval between adjacent delayed odd data is one system clock cycle
  • the time interval between adjacent delayed even data is also one system clock cycle.
  • the phases of the odd clock and the even clock are opposite and the period is twice the system clock period, so the corresponding delayed odd data and delayed even data (for example, between ODD1 and EVEN1, or between ODD2 and EVEN2) also differ by one system clock cycle.
  • five consecutive data bits can be formed to detect whether the predetermined conditions are currently met, thereby realizing the timely generation of the output clock.
  • FIG. 12 is a structural example diagram of a first delay unit and a second delay unit provided by an embodiment.
  • Each first delay subunit 211 includes a first trigger 31 and a third NOT gate 32, the input end of the first trigger 31 serves as the input end of the first delay subunit 211, the output end of the first trigger 31 is connected to the input end of the third NOT gate 32, and the output end of the third NOT gate 32 serves as the output end of the first delay subunit 211; wherein, the clock end of the odd-numbered first trigger 31 is connected to the inverted signal CLK_OB of the odd clock, and the clock end of the even-numbered first trigger 31 is connected to the odd clock CLK_O; each second delay subunit 221 includes a second trigger 33 and a fourth NOT gate 34, the input end of the second trigger 33 serves as the input end of the second delay subunit 221, the inverted output end of the second trigger 33 is connected to the input end of the fourth NOT gate 34, and the output end of the fourth NOT gate 34 serves
  • a delay subunit is formed by a trigger and a NOT gate to generate a data sequence with a certain time interval, thereby realizing subsequent accurate detection of whether the current predetermined condition is met.
  • conventional devices can simplify the circuit structure and reduce costs.
  • the inverted output of the trigger output combined with the inverted processing performed by the NOT gate can play a driving role and improve the accuracy of the generated signal.
  • the output clock includes a first output clock CLK_2_O and a second output clock CLK_2_E with opposite phases. And at the same time, the first output clock CLK_2_O or the second output clock CLK_2_E is valid; wherein any output clock is valid, indicating that the sampling clock corresponding to the output clock first samples the latter chip selection signal with the first data bit in the low level state.
  • the first output clock CLK_2_O corresponds to the odd clock CLK_O
  • the second output clock CLK_2_E corresponds to the even clock CLK_E.
  • Each rising edge of the output clock corresponds to the rising edge of the corresponding sampling clock.
  • a single chip select signal includes four data bits, and accordingly, the period of the output clock is consistent with the length of the single chip select signal, which is four system clock periods, that is, twice the sampling clock.
  • the corresponding output clock can be generated based on the sampling clock by a frequency division circuit DIV.
  • FIG. 13 is a structural example diagram of a generation module provided by an embodiment.
  • the generation module 13 includes: a selection unit 131 , a first generation unit 132 and a second generation unit 133 ;
  • the selection unit 131 is connected to the first operation unit 23 and the second operation unit 24; the selection unit 131 is used to output a valid first enable signal CS_O to the first generation unit 132 in response to the first operation unit 23 first outputting the indication signal of the first state; and, in response to the second operation unit 24 first outputting the indication signal of the first state, output a valid second enable signal CS_E to the second generation unit 133;
  • the enable terminal of the first generating unit 132 is connected to the selecting unit 131.
  • the first generating unit 132 receives the odd clock CLK_O.
  • the first generating unit 132 is used to divide the odd clock CLK_O in response to the first enable signal CS_O being valid, and output the first output clock CLK_2_O;
  • the enable terminal of the second generation unit 133 is connected to the selection unit 131 .
  • the second generation unit 133 receives the even clock CLK_E.
  • the second generation unit 133 is used to divide the even clock CLK_E in response to the second enable signal CS_E being valid, and output the second output clock CLK_2_E.
  • the first state can be set according to actual conditions. For example, if the first state is a high level state, when the signal output by a certain operation unit is 1, it indicates that the five consecutive data bits currently received meet the predetermined conditions.
  • the selection unit will output a valid enable signal to the generation unit corresponding to the operation unit that first receives the first state, so that the generation unit outputs the corresponding output clock based on the received sampling clock.
  • the selection unit will reset the generation unit corresponding to another operation unit to provide only one valid output clock at the same time, thereby avoiding the subsequent chip selection test.
  • the operation result obtained in response to the odd clock and the operation result obtained in response to the even clock have a signal conflict when they are output.
  • FIG. 14 is a structural example diagram of a generation module provided by an embodiment.
  • the selection unit 131 includes: a first transmission unit 41 , a second transmission unit 42 and a control unit 43 ;
  • the input end of the first transmission unit 41 receives the first high level signal
  • the control end of the first transmission unit 41 receives the indication signal output by the first operation unit 23, and the output end of the first transmission unit 41 is connected to the enable end of the first generation unit 132 and the control unit 43;
  • the first transmission unit 41 is used to transmit the first high level signal to the control unit 43 when the indication signal output by the first operation unit 23 is in the first state;
  • the input end of the second transmission unit 42 receives the second high level signal
  • the control end of the second transmission unit 42 receives the indication signal output by the second operation unit 24, and the output end of the second transmission unit 42 is connected to the enable end of the second generation unit 133 and the control unit 43;
  • the second transmission unit 42 is used to transmit the second high level signal to the control unit 43 when the indication signal output by the second operation unit 24 is in the first state;
  • the control unit 43 is connected to the enable end of the first transmission unit 41 and the enable end of the second transmission unit 42, and is used to enable the first transmission unit 41 and reset the second transmission unit 42 when receiving a signal output by the first transmission unit 41; and to enable the second transmission unit 42 and reset the first transmission unit 41 when receiving a signal output by the second transmission unit 42.
  • the selection unit is used to enable the generation unit corresponding to the operation unit and reset the generation unit corresponding to the other operation unit when any operation unit in the first operation unit and the second operation unit detects that the predetermined condition is currently met, that is, the operation unit outputs the indication signal of the first state.
  • the first transmission unit transmits the first high-level signal to the control unit.
  • the control unit receives the signal transmitted by the first transmission unit, the first transmission unit is enabled and the second transmission unit is reset. After the first transmission unit is enabled, the first high-level signal is continuously transmitted to the enable end of the first generation unit to enable the first generation unit to work and output the first output clock.
  • the implementation mode of the first high-level signal and the second high-level signal is not limited, and can be the same or different. In actual situations, it can be set according to the enable level of the generation unit.
  • the first high-level signal and the second high-level signal are both power supply signals VDD.
  • the first high-level signal output by the first transmission unit is used as the enable signal CS_O of the first generation unit
  • the second high-level signal output by the second transmission unit is used as the enable signal CS_E of the second generation unit.
  • the high-level signal output by the transmission unit may be further subjected to logic operation or processing to obtain an enable signal of the generation unit, and the specific content of the enable signal is not limited herein.
  • Figure 15 is a structural example diagram of a generation module provided by an embodiment.
  • the control unit 43 includes: a third NOR gate 431 and a fourth NOR gate 432; the input end of the third NOR gate 431 is connected to the output end of the second transmission unit 42, and the output end of the third NOR gate 431 is connected to the enable end of the first transmission unit 41; the input end of the fourth NOR gate 432 is connected to the output end of the first transmission unit 41, and the output end of the fourth NOR gate 432 is connected to the enable end of the second transmission unit 42.
  • the first transmission unit will output a high-level signal to the input end of the fourth NOR gate
  • the fourth NOR gate outputs a low-level signal to the enable end of the second transmission unit
  • the second transmission unit is reset.
  • the second transmission unit will output a high-level signal to the input end of the third NOR gate
  • the third NOR gate outputs a low-level signal to the enable end of the first transmission unit
  • the first transmission unit is reset.
  • two NOR gates are used to control the enabling or resetting of the transmission unit according to the output of the indication signal by the operation unit, which can further simplify the circuit structure.
  • the control unit 43 also includes: a first reset unit 433; the first reset unit 433 includes: a seventh NOT gate and an OR gate; the input end of the seventh NOT gate receives the test mode signal CSTM_ENT, and the output end of the seventh NOT gate is connected to the first input end of the OR gate; the second input end of the OR gate receives the reset signal VPU RST, and the output end of the OR gate is connected to the other input end of the third NOR gate 431 and the other input end of the fourth NOR gate 432.
  • the first reset unit can realize the reset function. Specifically, when the reset signal VPU RST is 1, the third NOR gate and the fourth NOR gate both output 0, and the first transmission unit and the second transmission unit are reset. It should be noted that although it is called the first reset unit, other functions except the reset function are not limited. For example, in practical applications, considering that DDR5 stipulates a special chip select test mode (CSTM), the first reset unit can also be set to control entry or exit from this mode to better suit the memory scenario. Combined with the example shown in the figure, when entering the CSTM mode, the test mode signal CSTM_ENT is in an activated state, for example, 1, and outputs 0 to the OR gate through the seventh NOR gate.
  • CSTM chip select test mode
  • the reset signal VPU RST is 0, then the OR gate outputs 0, and the first transmission unit and the second transmission unit will not be reset.
  • the two transmission units can work normally according to the aforementioned principles.
  • the test mode signal CSTM_ENT is in an inactive state, for example, 0, and outputs 1 to the OR gate through the seventh NOT gate.
  • the OR gate outputs 1, and the third and fourth NOR gates both output 0, and the first transmission unit and the second transmission unit are reset and do not work. This example can realize the effective and timely reset and control of the control unit.
  • the first transmission unit 41 includes a third trigger 411; the input end of the third trigger 411 receives the first high level signal VDD, the clock end of the third trigger 411 receives the indication signal output by the first operation unit 23, and the output end of the third trigger 411 is connected to the control unit 43 and the enable end of the first generation unit 132; the second transmission unit 42 includes a fourth trigger 421; the input end of the fourth trigger 421 receives the second high level signal VDD, the clock end of the fourth trigger 421 receives the indication signal output by the second operation unit 24, and the output end of the fourth trigger 421 is connected to the control unit 43 and the enable end of the second generation unit 133.
  • a trigger is used to realize that under the control of a control unit, the first transmission unit or the second transmission unit transmits a high-level signal to a corresponding generation unit to enable the generation unit and reset the other generation unit, thereby further simplifying the circuit structure while achieving timely and accurate generation of the output clock.
  • FIG16 is a structural example diagram of a generating module provided by an embodiment.
  • the first generating unit 132 includes a first trigger 51 and a third delay unit 52; the input end of the first trigger 51 is connected to the inverting output end of the first trigger 51, the clock end of the first trigger 51 receives the odd clock CLK_O, the reset end of the first trigger 51 is the enable end of the first generating unit 132, and the output end of the first trigger 51 is connected to the input end of the third delay unit 52; the third delay unit 52 is used to delay the signal output by the first trigger 51 to obtain the first output clock CLK_2_O;
  • the second generating unit 133 includes a second trigger 53 and a fourth delay unit 54; the input end of the second trigger 53 is connected to the inverting output end of the second trigger 53, the clock end of the second trigger 53 receives the even clock CLK_E, the reset end of the second trigger 53 is the enable end of the second generating unit 133, and the output end of the second trigger 53 is connected to the input end of the fourth delay unit 54; the fourth delay unit 54 is used to delay the signal output by the second trigger 53 to obtain the second output clock CLK_2_E.
  • the first generation unit and the second generation unit are enabled, based on the received sampling clock, the output clock with a period twice the period of the sampling clock is output, and the first generation unit or the second generation unit is enabled when the first operation unit or the second operation unit detects that the predetermined condition is currently satisfied, so the rising edge of the output clock output is aligned with the sample signal that first samples the chip select signal, that is, the rising edge of the sampling clock that detects the start of the chip select test.
  • a multi-stage inverting drive is added to the generated output clock.
  • the third delay unit 52 and the fourth delay unit 54 both include a plurality of fifth NOT gates connected in series, wherein the number of the plurality of fifth NOT gates is an even number.
  • the first generation unit 132 further includes a fifth delay unit 55; the input end of the fifth delay unit 55 is connected to the output end of the first trigger 51, and the fifth delay unit 55 is used to invert and delay the signal output by the first trigger 51 to obtain the inverted signal CLK_2_OB of the first output clock CLK_2_O;
  • the second generation unit 133 further includes a sixth delay unit 56; the input end of the sixth delay unit 56 is connected to the output end of the second trigger 53, and the sixth delay unit 56 is used to invert and delay the signal output by the second trigger 53 to obtain the inverted signal CLK_2_EB of the second output clock CLK_2_E.
  • the fifth delay unit 55 and the sixth delay unit 56 both include a plurality of sixth NOT gates connected in series, wherein the number of the plurality of sixth NOT gates is an odd number.
  • the inverted delay processing is implemented by a conventional NOT gate, thereby further simplifying the circuit structure.
  • the generating module 13 further includes: a second reset unit 134;
  • the second reset unit 134 includes: an eighth NOT gate 61, a ninth NOT gate 62, a fifth NOR gate 63 and a sixth NOR gate 64;
  • the input end of the eighth NOT gate 61 is connected to the output end of the first transmission unit 41, and the output end of the eighth NOT gate 61 is connected to the first input end of the fifth NOR gate 63; the second input end of the fifth NOR gate 63 is connected to the first input end of the sixth NOR gate 64, and the output end of the fifth NOR gate 63 is connected to the enable end of the first generation unit 132;
  • the input end of the ninth NOT gate 62 is connected to the output end of the second transmission unit 42, and the output end of the ninth NOT gate 62 is connected to the second input end of the sixth NOR gate 64; the first input end of the sixth NOR gate 64 receives the reset signal VPU RST, and the output end of the sixth NOR gate 64 is connected to the enable end of the second generation unit 133.
  • a second reset unit is provided for the first generation unit and the second generation unit to implement a reset function for the generation unit, thereby improving the reliability of circuit operation and simplifying the circuit structure.
  • the sampling module samples the continuous chip select signal based on the odd clock and the even clock to obtain odd data and even data
  • the detection module detects whether the adjacent chip select signals meet the predetermined conditions based on the odd data and the even data.
  • the generation module starts to generate the output clock.
  • the second embodiment of the present disclosure provides a memory, which includes: a chip test circuit and a clock generation circuit as described above; wherein:
  • the clock generation circuit is connected to the chip test circuit to provide an output clock for the chip test circuit.
  • the chip test circuit is used to perform a chip selection signal test on the memory.
  • the chip test circuit and the clock generation circuit can be started to enter the CSTM mode. After a certain period of time, the sample signal of the chip select signal begins to be input, and when the clock generation circuit detects the sample signal, it begins to generate the output clock; at the same time, the chip test circuit uses odd clocks and even clocks for sampling to obtain odd data and even data. Among them, the phases of the odd clock and the even clock are opposite, and the cycle is twice the system clock cycle, so sufficient sampling windows can be provided for the sampling of the chip select signal, avoiding sampling errors and sampling failures, and ensuring the accuracy of the CS test.
  • the complete chip select signal is integrated to perform the chip select test operation, and the operation result is output when the rising edge of the output clock provided by the clock generation circuit arrives. Based on the comparison of the output operation result and the standard result, it is judged whether the chip select signal is received normally.
  • the chip test circuit performs sampling based on odd clock and even clock to perform comparison operation to obtain the operation result, and outputs the operation result in response to the output clock provided by the clock generation circuit.
  • the sampling module of the clock generation circuit performs sampling based on odd clock and even clock to obtain odd data and even data
  • the detection module detects whether the adjacent chip select signals before and after meet the predetermined conditions based on the odd data and even data. When it is detected that the adjacent chip select signals meet the predetermined conditions, the generation module starts to generate the output clock.
  • the predetermined conditions that can characterize the start of the chip select test can be set according to the actual test, and the data bits in the chip select signal can be collected, detected and generated in time based on the odd clock and even clock whose clock cycle is twice the system clock cycle.
  • the output clock can be generated and provided in time while ensuring accurate and reliable sampling.
  • the output clock can be used to cooperate with the accurate output of the chip select test results to achieve accurate and reliable chip select testing.

Abstract

本公开提供一种时钟生成电路及存储器，包括：采样模块基于采样时钟对连续的片选信号进行采样，得到奇数据和偶数据；检测模块用于当检测到相邻的片选信号满足预定条件时，输出第一状态的指示信号，否则输出第二状态的指示信号；其中，所述预定条件包括前一片选信号的数据位均为第一电平状态，且后一片选信号的首个数据位为第二电平状态；生成模块用于在所述指示信号处于第一状态时，生成输出时钟。本方案能够在保证采样准确可靠的同时及时生成输出时钟。

Description

时钟生成电路及存储器
本公开要求于2022年10月14日提交中国专利局、申请号为202211260989.0、申请名称为“时钟生成电路及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器技术，尤其涉及一种时钟生成电路及存储器。
背景技术
伴随存储器技术的发展，存储器被广泛应用在多种领域，比如，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的使用非常广泛。
实际应用中，为了保证存储器的正常工作，通常需要对存储器进行信号测试。比如，为了改善片选(Chip Select，简称CS)信号引脚的时间裕度，进行片选测试(CS training)，也称CS训练。
考虑到存储器的特点，尤其在存储器的速率较高的情况下，采用周期满足采样需求的分频采样时钟进行片选信号的采样，得到完整片选信号的运算结果，按照输出时钟输出结果。因此，如何及时生成适用于片选测试的输出时钟成为需要解决的问题。
发明内容
本公开的实施例提供一种时钟生成电路及存储器。
根据一些实施例，本公开第一方面提供一种时钟生成电路，包括：采样模块，用于基于采样时钟对连续的片选信号进行采样，片选信号的每一数据位的保持时长等于系统时钟的周期，采样时钟包含相位相反的奇时钟和偶时钟，奇时钟和偶时钟的周期等于系统时钟的周期的两倍，记基于奇时钟采样得到的数据为奇数据，记基于偶时钟采样得到的数据为偶数据；检测模块，与采样模块连接，用于当检测到相邻的片选信号满足预定条件时，输出第一状态的指示信号，否则输出第二状态的指示信号；其中，预定条件包括前一片选信号的数据位均为第一电平状态，且后一片选信号的首个数据位为第二电平状态；生成模块，与检测模块连接，用于在指示信号处于第一状态时，生成输出时钟；其中，输出时钟的周期为单个片选信号的长度，输出时钟的上升沿与最先采样到首个数据位为低电平状态的后一片选信号的采样时钟的上升沿对齐。
在一些实施例中，每个片选信号包括四个数据位。
在一些实施例中，检测模块包括：第一延迟单元、第二延迟单元、第一运算单元和第二运算单元；第一延迟单元，与采样模块连接，用于将奇数据按照预定的时间间隔依次延时输出，得到第一延迟奇数 据、第二延迟奇数据、第三延迟奇数据、第四延迟奇数据和第五延迟奇数据；第二延迟单元，与采样模块连接，用于将偶数据按照时间间隔依次延时输出，得到第一延迟偶数据、第二延迟偶数据、第三延迟偶数据、第四延迟偶数据和第五延迟偶数据；第一运算单元的输入端与第一延迟单元和第二延迟单元连接，第一运算单元用于接收第一延迟奇数据、第二延迟偶数据、第三延迟奇数据、第四延迟偶数据和第五延迟奇数据，并检测是否满足预定条件；第一运算单元的输出端与生成模块连接；第二运算单元的输入端与第一延迟单元和第二延迟单元连接，第二运算单元用于接收第一延迟偶数据、第二延迟奇数据、第三延迟偶数据、第四延迟奇数据和第五延迟偶数据，并检测是否满足预定条件；第二运算单元的输出端与生成模块连接。
在一些实施例中，第一运算单元包括：第一非门、第一与非门和第二与非门、以及第一或非门；第一非门的输入端接收第一延迟奇数据，第一非门的输出端与第一与非门的第一输入端连接；第一与非门的第二输入端接收第二延迟偶数据，第一与非门的第三输入端接收第三延迟奇数据，第一与非门的输出端与第一或非门的第一输入端连接；第二与非门的第一输入端接收第四延迟偶数据，第二与非门的第二输入端接收第五延迟奇数据，第二与非门的输出端与第一或非门的第二输入端连接；第一或非门的输出端与生成模块连接；第二运算单元包括：第二非门、第三与非门和第四与非门、以及第二或非门；第二非门的输入端接收第一延迟偶数据，第二非门的输出端与第三与非门的第一输入端连接；第三与非门的第二输入端接收第二延迟奇数据，第三与非门的第三输入端接收第三延迟偶数据，第三与非门的输出端与第二或非门的第一输入端连接；第四与非门的第一输入端接收第四延迟奇数据，第四与非门的第二输入端接收第五延迟偶数据，第四与非门的输出端与第二或非门的第二输入端连接；第二或非门的输出端与生成模块连接。
在一些实施例中，第一延迟单元包括：多个串联的第一延迟子单元；首个第一延迟子单元的输入端与采样模块连接，用于接收基于奇数据生成的第一延迟奇数据；每个第一延迟子单元的输入端与前一第一延迟子单元的输出端连接，每个第一延迟子单元用于将接收的数据经过时间间隔后输出；第二延迟单元包括：多个串联的第二延迟子单元；首个第二延迟子单元的输入端与采样模块连接，用于接收基于偶数据生成的第一延迟偶数据；每个第二延迟子单元的输入端与前一第二延迟子单元的输出端连接，每个第二延迟子单元用于将接收的数据经过时间间隔后输出。
在一些实施例中，输出时钟包括相位相反的第一输出时钟和第二输出时钟；在同一时刻下，第一输出时钟或第二输出时钟有效；其中任一输出时钟有效表征该输出时钟对应的采样时钟最先采样到首个数据位为低电平状态的后一片选信号。
在一些实施例中，生成模块包括：选择单元、第一生成单元和第二生成单元；选择单元与第一运算单元和第二运算单元连接；选择单元用于响应于第一运算单元先输出第一状态的指示信号，向第一生成单元输出有效的第一使能信号；以及，响应于第二运算单元先输出第一状态的指示信号，向第二生成单 元输出有效的第二使能信号；第一生成单元的使能端与选择单元连接，第一生成单元接收奇时钟，第一生成单元用于响应于第一使能信号有效，对奇时钟进行分频，输出第一输出时钟；第二生成单元的使能端与选择单元连接，第二生成单元接收偶时钟，第二生成单元用于响应于第二使能信号有效，对偶时钟进行分频，输出第二输出时钟。
在一些实施例中，第一生成单元包括第一触发器和第三延迟单元；第一触发器的输入端与第一触发器的反相输出端连接，第一触发器的时钟端接收奇时钟，第一触发器的复位端为第一生成单元的使能端，第一触发器的输出端与第三延迟单元的输入端连接；第三延迟单元用于将第一触发器输出的信号延迟输出得到第一输出时钟；第二生成单元包括第二触发器和第四延迟单元；第二触发器的输入端与第二触发器的反相输出端连接，第二触发器的时钟端接收偶时钟，第二触发器的复位端为第二生成单元的使能端，第二触发器的输出端与第四延迟单元的输入端连接；第四延迟单元用于将第二触发器输出的信号延迟输出得到第二输出时钟。
在一些实施例中，第一生成单元还包括第五延迟单元；第五延迟单元的输入端与第一触发器的输出端连接，第五延迟单元用于将第一触发器输出的信号进行反相延迟输出得到第一输出时钟的反相信号；第二生成单元还包括第六延迟单元；第六延迟单元的输入端与第二触发器的输出端连接，第六延迟单元用于将第二触发器输出的信号进行反相延迟输出得到第二输出时钟的反相信号。
在一些实施例中，选择单元包括：第一传输单元、第二传输单元和控制单元；第一传输单元的输入端接收第一高电平信号，第一传输单元的控制端接收第一运算单元输出的指示信号，第一传输单元的输出端连接至第一生成单元的使能端和控制单元；第一传输单元用于在第一运算单元输出的指示信号处于第一状态时，将第一高电平信号传输至控制单元；第二传输单元的输入端接收第二高电平信号，第二传输单元的控制端接收第二运算单元输出的指示信号，第二传输单元的输出端连接至第二生成单元的使能端和控制单元；第二传输单元用于在第二运算单元输出的指示信号处于第一状态时，将第二高电平信号传输至控制单元；控制单元与第一传输单元的使能端和第二传输单元的使能端连接，用于当接收到第一传输单元输出的信号时，使能第一传输单元并复位第二传输单元；以及当接收到第二传输单元输出的信号时，使能第二传输单元并复位第一传输单元。
在一些实施例中，控制单元包括：第三或非门和第四或非门；第三或非门的输入端与第二传输单元的输出端连接，第三或非门的输出端与第一传输单元的使能端连接；第四或非门的输入端与第一传输单元的输出端连接，第四或非门的输出端与第二传输单元的使能端连接。
在一些实施例中，控制单元还包括：第一复位单元；第一复位单元包括：第七非门和或门；第七非门的输入端接收测试模式信号，第七非门的输出端连接至或门的第一输入端；或门的第二输入端接收复位信号，或门的输出端连接至第三或非门的另一输入端和第四或非门的另一输入端。
在一些实施例中，生成模块还包括：第二复位单元；第二复位单元包括：第八非门、第九非门、第 五或非门和第六或非门；第八非门的输入端与第一传输单元的输出端连接，第八非门的输出端与第五或非门的第一输入端连接；第五或非门的第二输入端与第六或非门的第一输入端连接，第五或非门的输出端与第一生成单元的使能端连接；第九非门的输入端与第二传输单元的输出端连接，第九非门的输出端与第六或非门的第二输入端连接；第六或非门的第一输入端接收复位信号，第六或非门的输出端与第二生成单元的使能端连接。
根据一些实施例，本公开第二方面提供一种存储器，包括：如前的时钟生成电路和芯片测试电路；其中，时钟生成电路和芯片测试电路连接，用于为芯片测试电路提供输出时钟，芯片测试电路用于对存储器进行片选信号测试。
本公开实施例提供的时钟生成电路及存储器中，采样模块基于奇时钟和偶时钟对连续的片选信号进行采样获得奇数据和偶数据，检测模块基于奇数据和偶数据检测前后相邻的片选信号是否满足预定条件，当检测到相邻的片选信号满足预定条件时，生成模块开始生成输出时钟。通过上述方案，可以根据实际测试设定能够表征开始进行片选测试的预定条件，实现基于时钟周期为系统时钟周期两倍的奇时钟和偶时钟对片选信号中各数据位的采集、检测并及时地生成输出时钟，从而能够在保证采样准确可靠的同时及时生成输出时钟，该输出时钟可配合片选测试结果的准确输出，实现准确可靠的片选测试。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开实施例的原理。
图1为本公开一实施例示出的存储器的架构示例图；
图2为本公开一实施例示出的存储单元的结构示例图；
图3为示例的存储拓扑架构；
图4为一实施例提供的时钟生成电路的结构示例图；
图5和图6为采样的时序示例图；
图7为一实施例提供的检测模块的结构示例图；
图8和图9为数据序列的时序示例图；
图10为一实施例提供的第一运算单元和第二运算单元的结构示例图；
图11和图12为示例提供的第一延迟单元和第二延迟单元的结构示例图；
图13-图16为示例的生成模块的结构示例图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开中的用语“包括”和“具有”用以表示开放式的包括在内的意思，并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记或区分使用，不是对其对象的先后顺序或数量限制。此外，附图中的不同元件和区域只是示意性示出，因此本公开不限于附图中示出的尺寸或距离。
下面以具体地实施例对本公开的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图1为本公开一实施例示出的存储器的架构示例图，如图1所示，以DRAM作为示例，包括数据输入/输出缓冲、行解码器、列解码器、感测放大器以及存储阵列。存储阵列主要由字线、位线和存储单元组成。存储阵列中的字线沿行方向延伸，存储阵列中的位线沿列方向延伸，字线与位线的交叉处为存储阵列的存储单元。
其中，每个存储单元用于存储一个位(bit)的数据。如图2所示，图2为本公开一实施例示出的存储单元的结构示例图，存储单元主要由晶体管M和电容C组成。其中，电容用于存储数据，晶体管用于根据字线状态，关断或导通。
可以通过控制行和列来激活某个存储单元，以实现对该存储单元的访问。结合读取场景作为示例：需要读取存储单元中的数据时，可以通过行解码器选中该存储单元所在行的字线，相应的，图示中的晶体管M导通，通过对位线信号的感测放大就可以感知到此时电容C上的状态。例如，如果存储单元中存储的数据为1，那么晶体管M导通后就会从存储单元的位线上读到1，反之也是同样的道理。另外，结合写入场景作为示例：需要向某存储单元中写入数据时，比如写入1。可以通过行解码器选中该存储单元所在行的字线，相应的图示中的晶体管M导通，通过将位线的逻辑电平设为1，使得电容C充电，即向存储单元写入1。反之，如果要写入0，那么位线的逻辑电平设为0，使得电容C放电，即向存储单元写入0。
实际应用中，为了增加存储容量，通常需要采用多个存储芯片。作为示例，图3为示例的存储拓扑架构。需要说明的是，图中仅是一种示例，相关技术中存在多种芯片拓扑架构，比如包括但不限于双T架构、Fly-By拓扑架构等，在此并未对其进行限制。结合图示的示例，当需要访问某存储单元时，首 先要选择该存储单元所在的存储芯片，即进行片选。举例来说，某存储芯片对应的片选信号锁存为高电平时，所有的命令都被忽略，即该存储芯片未被选中；反之，若为低电平时，则该存储芯片被选中，可执行命令响应。然后，再从选中的芯片中基于地址信息选择相应的存储单元，从而实现对该存储单元的访问，比如进行数据存取等。可见，片选信号影响能否成功寻址到需访问的存储单元。故在相关标准中规定有关于片选信号测试的相关内容。作为示例，在测试过程中向存储器发出样本信号，存储器基于采样到的片选信号进行运算得到运算结果，如果运算结果与标准结果一致，则说明存储器能够在正常接收片选信号，CS测试通过；否则，说明存储器无法正确接收片段信号。
以双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，简称DDR SDRAM)示例，在DDR5的相关标准规定了片选测试模式(CS training mode，简称CSTM)，以独立为CS测试提供模式。一旦进入CSTM模式，DRAM将在时钟上升沿对接收到的CS信号进行采样。具体的，可以使用多用途命令(Multi Purpose Command，简称MPC)进入和退出CSTM模式。
实际应用中，由于DDR5的速度和频率明显高于DDR4，故对CS测试的可靠性提出更高要求。在一些实施例中，采用时钟周期为系统时钟周期两倍的奇时钟和偶时钟进行片选信号的采样和运算，得到的运算结果响应于输出时钟输出。这里的输出时钟用于捕获基于完整的片选信号得到的运算结果并输出该运算结果，以实现片选信号测试，故需要保证当开始进行片选测试时，及时提供准确的输出时钟。
本公开实施例的一些方面涉及上述考虑。以下结合本公开的一些实施例对方案进行示例介绍。
实施例一
图4为一实施例提供的时钟生成电路的结构示例图，如图4所示，该时钟生成电路包括：
采样模块11，用于基于采样时钟对连续的片选信号进行采样，片选信号的每一数据位的保持时长等于系统时钟的周期，采样时钟包含相位相反的奇时钟和偶时钟，奇时钟和偶时钟的周期等于系统时钟的周期的两倍，记基于奇时钟采样得到的数据为奇数据，记基于偶时钟采样得到的数据为偶数据；
检测模块12，与采样模块11连接，用于当检测到相邻的片选信号满足预定条件时，输出第一状态的指示信号，否则输出第二状态的指示信号；其中，预定条件包括前一片选信号的数据位均为第一电平状态，且后一片选信号的首个数据位为第二电平状态；
生成模块13，与检测模块连接，用于在指示信号处于第一状态时，生成输出时钟；其中，输出时钟的周期为单个片选信号的长度，输出时钟的上升沿与最先采样到首个数据位为低电平状态的后一片选信号的采样时钟的上升沿对齐。
实际应用中，本实施例提供的芯片测试电路可应用在各种存储器，作为示例，可以应用在包括但不限双倍速率同步动态随机存储器(简称DDR)等。其中，每个片选信号包括至少一个数据位。结合存储器场景，在一个示例中，每个片选信号包括四个数据位。
以DDR5为例，结合实际场景进行示例说明：当需要进行CS测试时，可以启动进入CSTM模式。 考虑到DDR5的高速率特点，为了保证采样的可靠性，在一些实施例中采用相位相反，且周期为系统时钟周期的两倍的奇时钟和偶时钟进行采样，对应采样得到的信号分别称为奇数据和偶数据，从而为片选信号的采样提供充足的采样窗口，避免采样错误和采样失败，保证CS测试的准确性。作为示例，可以在奇时钟和偶时钟的上升沿，对片选信号进行采样。需要说明的是，这里的“奇数据”和“偶数据”只是对响应于奇时钟和偶时钟采集得到的数据的称呼，并未限制实际采样得到的数据的具体内容或者在片选信号中的奇偶属性。后续基于奇数据和进行片选测试运算，得到运算结果。输出时钟用于控制运算结果何时输出，这是因为，基于奇数据和偶数据并非始终都能组成一个完整的片选信号，而是在特定的时段内，比如片选信号的最后一个数据位被采样之后直至新片选信号的采样开始之前，方构成一个完整的片选信号。而输出时钟即用于控制输出该特定时段下的运算结果，而忽略其它时段下得到的运算结果，以保证测试结果的准确性。
故输出时钟的及时生成，影响测试结果的准确性。本实施例中，通过设定能够表征片选测试开始的预定条件，来保证及时提供输出时钟。这里的预定条件的设定对象是片选信号，即当片选信号的数据满足预定条件时，表明开始进行片选测试。该预定条件可以预先设定，后续在提供片选信号时基于该预定条件提供片选信号，以便于能够识别出测试是否开始。实际应用中，在相关标准中规定有关于片选信号测试的相关内容，比如，在接收到指示进入CSTM模式的指令之后，输入片选信号的样本信号之前的期间，会先控制片选信号维持一段时间的高电平，之后才开始真正的片选测试，即输入片选信号的样本信号，基于采样的片选信号进行运算以及输出运算结果。故在一个示例中，预定条件可以包括前一片选信号的数据位均为1，且后一片选信号的首个数据位为0，这样无需对其它信号进行调整，即可准确识别出片选测试何时开始。
结合图5和图6进行示例：图5和图6为采样的时序示例图。其中，CS为片选信号，CLK为系统时钟，CLK_E为偶时钟，CLK_O为奇时钟。基于奇时钟采样得到的奇数据为ODD，基于偶时钟采样得到的偶数据为EVEN。另外，图中分别示出了两种情况，一种情况为响应于奇时钟先检测到开始片选测试；另一种情况为响应于偶时钟先检测到开始片选测试。
在一个示例中，图7为一实施例提供的检测模块的结构示例图，如图7所示，检测模块12包括：第一延迟单元21、第二延迟单元22、第一运算单元23和第二运算单元24；
第一延迟单元21，与采样模块11连接，用于将奇数据ODD按照预定的时间间隔依次延时输出，得到第一延迟奇数据ODD1、第二延迟奇数据ODD2、第三延迟奇数据ODD3、第四延迟奇数据ODD4和第五延迟奇数据ODD5；
第二延迟单元22，与采样模块11连接，用于将偶数据EVEN按照时间间隔依次延时输出，得到第一延迟偶数据EVEN1、第二延迟偶数据EVEN2、第三延迟偶数据EVEN3、第四延迟偶数据EVEN4和第五延迟偶数据EVEN5；
第一运算单元23的输入端与第一延迟单元21和第二延迟单元22连接，第一运算单元23用于接收第一延迟奇数据ODD1、第二延迟偶数据EVEN2、第三延迟奇数据ODD3、第四延迟偶数据EVEN4和第五延迟奇数据ODD5，并检测是否满足预定条件；第一运算单元23的输出端与生成模块13连接；
第二运算单元24的输入端与第一延迟单元21和第二延迟单元22连接，第二运算单元24用于接收第一延迟偶数据EVEN1、第二延迟奇数据ODD2、第三延迟偶数据EVEN3、第四延迟奇数据ODD4和第五延迟偶数据EVEN5，并检测是否满足预定条件；第二运算单元23的输出端与生成模块13连接。
在一个示例中，时间间隔为一个系统时钟周期。结合图8和图9进行示例：图8和图9为数据序列的时序示例图。其中，数据序列是第一延时单元和第二延迟单元基于采样得到的奇数据和偶数据生成的，举例来说，数据序列包括第一延时单元输出的ODD1～ODD5以及第二延迟单元输出的EVEN1～EVEN5。具体的，由于本实施例中采用奇时钟和偶时钟进行片选信号的采样，故在进行片选测试的运算之前，需要先基于采样得到的奇数据和偶数据整合出之前的片选信号(四个数据位)和之后的片选信号的首个数据位，当这五个数据位满足11110时，即当前满足预定条件，说明开始进行片选测试，具体的，首个数据位为0的片选信号即首个样本信号。在本示例中，第一运算单元和第二运算单元分别对应前面提到的两种情况，结合图8的示例，第一运算单元在采样模块响应于奇时钟先检测到当前的五个数据位满足预定条件，即接收的第五延迟奇数据ODD5、第四延迟偶数据EVEN4、第三延迟奇数据ODD3、第二延迟偶数据EVEN2为一个片选信号，各数据位均为1，接下来的片选信号的首个数据位D0为0。
具体的，第一运算单元和第二运算单元基于接收的信号，通过进行运算检测当前是否满足预定条件。在一些示例中，图10为一实施例提供的第一运算单元和第二运算单元的结构示例图，如图10所示，第一运算单元包括23：第一非门231、第一与非门232和第二与非门233、以及第一或非门234；
第一非门231的输入端接收第一延迟奇数据ODD1，第一非门231的输出端与第一与非门232的第一输入端连接；第一与非门232的第二输入端接收第二延迟偶数据EVEN2，第一与非门232的第三输入端接收第三延迟奇数据ODD3，第一与非门232的输出端与第一或非门234的第一输入端连接；第二与非门233的第一输入端接收第四延迟偶数据EVEN4，第二与非门233的第二输入端接收第五延迟奇数据ODD5，第二与非门233的输出端与第一或非门234的第二输入端连接；第一或非门234的输出端与生成模块13连接；
第二运算单元24包括：第二非门241、第三与非门242和第四与非门243、以及第二或非门244；第二非门241的输入端接收第一延迟偶数据EVEN1，第二非门241的输出端与第三与非门242的第一输入端连接；第三与非门242的第二输入端接收第二延迟奇数据ODD2，第三与非门242的第三输入端接收第三延迟偶数据EVEN3，第三与非门242的输出端与第二或非门244的第一输入端连接；第四与非门243的第一输入端接收第四延迟奇数据ODD4，第四与非门243的第二输入端接收第五延迟偶数据EVEN5，第四与非门243的输出端与第二或非门244的第二输入端连接；第二或非门244的输出端与 生成模块13连接。
实际应用中，运算模块输出的运算结果表征当前是否满足预定条件。结合第一运算单元作为示例，假设当前ODD5、EVEN4、ODD3以及EVEN2均为1，ODD1为0。则相应的，ODD1经过第一非门输出1，和为1的ODD3以及EVEN2输入第一与非门进行与非运算，第一与非门输出0至第一或非门；此时，为1的ODD5和EVEN4输入第二与非门进行与非运算，第二与非门输出0至第一或非门；相应的，第一或非门的两个输入均为0，第一或非门输出为1的运算结果，表征当前满足预定条件，即连续的五个数据位为11110。
本示例中，第一运算单元和第二运算单元通过非门、与非门以及或非门等常规器件实现，从而在保证及时准确生成输出时钟的同时，有效简化电路结构，降低成本。
具体的，前述内容中为了基于采样的奇数据和偶数据，检测连续的五个数据位是否满足预定条件，运算模块先通过对奇数据和偶数据进行间隔延迟，得到多个数据序列后，利用这多个数据序列组合为连续的五个数据位进行运算。
作为示例，图11为一实施例提供的第一延迟单元和第二延迟单元的结构示例图，如图11所示，第一延迟单元21包括：多个串联的第一延迟子单元211；首个第一延迟子单元211的输入端与采样模块11连接，用于接收基于奇数据ODD生成的第一延迟奇数据ODD1；每个第一延迟子单元211的输入端与前一第一延迟子单元211的输出端连接，每个第一延迟子单元211用于将接收的数据经过时间间隔后输出；第二延迟单元22包括：多个串联的第二延迟子单元221；首个第二延迟子单元221的输入端与采样模块11连接，用于接收基于偶数据EVEN生成的第一延迟偶数据EVEN1；每个第二延迟子单元221的输入端与前一第二延迟子单元221的输出端连接，每个第二延迟子单元221用于将接收的数据经过时间间隔后输出。
其中，第一延迟子单元和第二延迟子单元的数量可以根据预定条件中规定的连续数据位的数量确定。作为示例，第一延迟子单元和第二延迟子单元的数量均为四个。具体的，首个第一延迟子单元的输入端输出基于奇数据ODD生成的第一延迟奇数据ODD1，每个第一延迟子单元的输出端分别输出ODD2、ODD3、ODD4和ODD5。类似的，首个第二延迟子单元的输入端输出基于偶数据EVEN生成的第一延迟偶数据EVEN1，每个第二延迟子单元的输出端分别输出EVEN2、EVEN3、EVEN4和EVEN5。
作为示例，相邻的延迟奇数据之间的时间间隔为一个系统时钟周期，相邻的延迟偶数据之间的时间间隔同样为一个系统时钟周期。具体的，奇时钟和偶时钟的相位相反且周期为系统时钟周期的两倍，故对应的延迟奇数据和延迟偶数据之间(比如，ODD1和EVEN1之间，或者ODD2和EVEN2之间)同样相差一个系统时钟周期。结合前述的示例，基于上述延迟单元产生的各数据序列，能够构成连续的五个数据位用于检测当前是否满足预定条件，从而实现输出时钟的及时生成。
在一个示例中，图12为一实施例提供的第一延迟单元和第二延迟单元的结构示例图，如图12所示， 每个第一延迟子单元211包括第一触发器31和第三非门32，第一触发器31的输入端作为第一延迟子单元211的输入端，第一触发器31的输出端与第三非门32的输入端连接，第三非门32的输出端作为第一延迟子单元211的输出端；其中，第奇数个第一触发器31的时钟端连接奇时钟的反相信号CLK_OB，第偶数个第一触发器31的时钟端连接奇时钟CLK_O；每个第二延迟子单元221包括第二触发器33和第四非门34，第二触发器33的输入端作为第二延迟子单元221的输入端，第二触发器33的反相输出端与第四非门34的输入端连接，第四非门34的输出端作为第二延迟子单元221的输出端；其中，第奇数个第二触发器33的时钟端连接偶时钟的反相信号CLK_EB，第偶数个第二触发器33的时钟端连接偶时钟CLK_E。
本示例中，通过触发器和非门构成延迟子单元，产生具有一定时间间隔的数据序列，从而实现后续准确检测当前是否预定条件。并且，通过常规器件能够简化电路结构，降低成本。此外，通过触发器输出反相输出结合非门执行反相处理的方式，能够起到驱动作用，提高产生信号的准确性。
结合前述内容，考虑到前述存在两种情形，为了实现不同情形下的输出时钟，在一个示例中，输出时钟包括相位相反的第一输出时钟CLK_2_O和第二输出时钟CLK_2_E。并且，在同一时刻下，第一输出时钟CLK_2_O或第二输出时钟CLK_2_E有效；其中任一输出时钟有效表征该输出时钟对应的采样时钟最先采样到所述首个数据位为低电平状态的所述后一片选信号。
具体的，第一输出时钟CLK_2_O对应奇时钟CLK_O，第二输出时钟CLK_2_E对应偶时钟CLK_E。输出时钟的每个上升沿对应至相应的采样时钟的上升沿。作为示例，单个片选信号包括四个数据位，相应的，输出时钟的周期与单个片选信号的长度一致，为四个系统时钟周期，即采样时钟的两倍。在一个示例中，可以基于采样时钟，通过分频电路DIV生成对应的输出时钟。
作为示例，图13为一实施例提供的生成模块的结构示例图，如图13所示，生成模块13包括：选择单元131、第一生成单元132和第二生成单元133；
选择单元131与第一运算单元23和第二运算单元24连接；选择单元131用于响应于第一运算单元23先输出第一状态的指示信号，向第一生成单元132输出有效的第一使能信号CS_O；以及，响应于第二运算单元24先输出第一状态的指示信号，向第二生成单元133输出有效的第二使能信号CS_E；
第一生成单元132的使能端与选择单元131连接，第一生成单元132接收奇时钟CLK_O，第一生成单元132用于响应于第一使能信号CS_O有效，对奇时钟CLK_O进行分频，输出第一输出时钟CLK_2_O；
第二生成单元133的使能端与选择单元131连接，第二生成单元133接收偶时钟CLK_E，第二生成单元133用于响应于第二使能信号CS_E有效，对偶时钟CLK_E进行分频，输出第二输出时钟CLK_2_E。
其中，第一状态可以根据实际情况设定。比如，第一状态为高电平状态，则当某运算单元输出的信 号为1时，表明当前接收的五个连续数据位满足预定条件。相应的，选择单元会向先接收到第一状态的运算单元对应的生成单元输出有效的使能信号，以使生成单元基于接收到的采样时钟，输出对应的输出时钟。同时，选择单元将复位另一运算单元对应的生成单元，以在同一时刻下，只提供一个有效的输出时钟，从而避免后续进行片选测试时，响应于奇时钟得到的运算结果和响应于偶时钟得到的运算结果在输出时发生信号冲突。
在一个示例中，图14为一实施例提供的生成模块的结构示例图，如图14所示，选择单元131包括：第一传输单元41、第二传输单元42和控制单元43；
第一传输单元41的输入端接收第一高电平信号，第一传输单元41的控制端接收第一运算单元23输出的指示信号，第一传输单元41的输出端连接至第一生成单元132的使能端和控制单元43；第一传输单元41用于在第一运算单元23输出的指示信号处于第一状态时，将第一高电平信号传输至控制单元43；
第二传输单元42的输入端接收第二高电平信号，第二传输单元42的控制端接收第二运算单元24输出的指示信号，第二传输单元42的输出端连接至第二生成单元133的使能端和控制单元43；第二传输单元42用于在第二运算单元24输出的指示信号处于第一状态时，将第二高电平信号传输至控制单元43；
控制单元43与第一传输单元41的使能端和第二传输单元42的使能端连接，用于当接收到第一传输单元41输出的信号时，使能第一传输单元41并复位第二传输单元42；以及当接收到第二传输单元42输出的信号时，使能第二传输单元42并复位第一传输单元41。
具体的，选择单元用于当第一运算单元和第二运算单元中，任一运算单元先检测到当前满足预定条件，即运算单元输出第一状态的指示信号时，使能该运算单元对应的生成单元，并复位另一运算单元对应的生成单元。以第一运算单元先输出第一状态的指示信号为例，第一传输单元会将第一高电平信号传输给控制单元，控制单元接收到第一传输单元传输的该信号，则使能第一传输单元并复位第二传输单元，经过使能的第一传输单元，则继续将第一高电平信号传输至第一生成单元的使能端，以使能第一生成单元工作，输出第一输出时钟。其中，第一高电平信号和第二高电平信号的实现方式不限，可以相同也可以不同，实际情况中可以根据生成单元的使能电平设定。作为示例，第一高电平信号和第二高电平信号均为电源信号VDD。需要说明的是，本示例中，将第一传输单元输出的第一高电平信号作为第一生成单元的使能信号CS_O，将第二传输单元输出的第二高电平信号作为第二生成单元的使能信号CS_E，实际应用中，并不限于示例的情形。比如，可以对传输单元输出的高电平信号进行进一步逻辑运算或处理，得到生成单元的使能信号，在此不对使能信号的具体内容进行限制。
在一个示例中，图15为一实施例提供的生成模块的结构示例图，如图15所示，控制单元43包括：第三或非门431和第四或非门432；第三或非门431的输入端与第二传输单元42的输出端连接，第三 或非门431的输出端与第一传输单元41的使能端连接；第四或非门432的输入端与第一传输单元41的输出端连接，第四或非门432的输出端与第二传输单元42的使能端连接。
结合图示，以第一运算单元先输出第一状态的指示信号为例，第一传输单元会输出高电平信号至第四或非门的输入端，第四或非门输出低电平信号至第二传输单元的使能端，第二传输单元被复位。以第二运算单元先输出第一状态的指示信号为例，第二传输单元会输出高电平信号至第三或非门的输入端，第三或非门输出低电平信号至第一传输单元的使能端，第一传输单元被复位。本示例中，通过两个或非门实现根据运算单元输出指示信号的情况，控制传输单元的使能或复位，能够进一步简化电路结构。
考虑实际应用中需要复位的情形，在一个示例中，如图15所示，控制单元43还包括：第一复位单元433；第一复位单元433包括：第七非门和或门；第七非门的输入端接收测试模式信号CSTM_ENT，第七非门的输出端连接至或门的第一输入端；或门的第二输入端接收复位信号VPU RST，或门的输出端连接至第三或非门431的另一输入端和第四或非门432的另一输入端。
其中，第一复位单元可实现复位功能。具体的，当复位信号VPU RST为1时，第三或非门和第四或非门均输出0，第一传输单元和第二传输单元均被复位。需要说明的是，尽管称为第一复位单元，但并未限制除复位功能以外的其它功能。举例来说，实际应用中，考虑到DDR5规定了专门的片选测试模式(CSTM)，故第一复位单元还可以设置用于控制进入或退出该模式，以更好适用于存储器场景。结合图示举例，当进入CSTM模式，测试模式信号CSTM_ENT处于激活状态，例如为1，经过第七非门输出0至或门，假设此时并未进行复位，复位信号VPU RST为0，则或门输出0，不会复位第一传输单元和第二传输单元，两个传输单元可参照前述的原理正常工作。当退出CSTM模式，测试模式信号CSTM_ENT处于未激活状态，例如为0，经过第七非门输出1至或门，无论此时复位信号VPU RST为1或0，或门输出1，第三或非门和第四或非门均输出0，第一传输单元和第二传输单元复位，不工作。通过本示例能够实现控制单元的有效及时复位和控制。
具体的，在控制单元的控制下，选择第一传输单元或第二传输单元将电平信号传输至对应的生成单元，以使能生成单元输出对应的输出时钟。在一个示例中，如图15所示，第一传输单元41包括第三触发器411；第三触发器411的输入端接收第一高电平信号VDD，第三触发器411的时钟端接收第一运算单元23输出的指示信号，第三触发器411的输出端连接至控制单元43和第一生成单元132的使能端；第二传输单元42包括第四触发器421；第四触发器421的输入端接收第二高电平信号VDD，第四触发器421的时钟端接收第二运算单元24输出的指示信号，第四触发器421的输出端连接至控制单元43和第二生成单元133的使能端。
本示例中，通过触发器实现在控制单元的控制下，第一传输单元或第二传输单元将高电平信号传输至对应的生成单元，以使能该生成单元并复位另一生成单元，在实现及时准确生成输出时钟的同时，进一步简化电路结构。
本实施例中，针对前述的两种情形，设置两个生成单元，以提供不同情形下的输出时钟。在一个示例中，图16为一实施例提供的生成模块的结构示例图，如图16所示，第一生成单元132包括第一触发器51和第三延迟单元52；第一触发器51的输入端与第一触发器51的反相输出端连接，第一触发器51的时钟端接收奇时钟CLK_O，第一触发器51的复位端为第一生成单元132的使能端，第一触发器51的输出端与第三延迟单元52的输入端连接；第三延迟单元52用于将第一触发器51输出的信号延迟输出得到第一输出时钟CLK_2_O；
第二生成单元133包括第二触发器53和第四延迟单元54；第二触发器53的输入端与第二触发器53的反相输出端连接，第二触发器53的时钟端接收偶时钟CLK_E，第二触发器53的复位端为第二生成单元133的使能端，第二触发器53的输出端与第四延迟单元54的输入端连接；第四延迟单元54用于将第二触发器53输出的信号延迟输出得到第二输出时钟CLK_2_E。
具体的，第一生成单元和第二生成单元在被使能时，基于接收到的采样时钟，输出周期为采样时钟的周期的两倍的输出时钟，并且第一生成单元或第二生成单元是在第一运算单元或第二运算单元检测到当前满足预定条件时被使能，故输出的输出时钟的上升沿与最先采样到片选信号的样本信号，即检测到片选测试开始的采样时钟的上升沿对齐。为了改善信号质量，向生成的输出时钟加入多级反相驱动。在一个示例中，第三延迟单元52和第四延迟单元54均包括串联的多个第五非门，其中多个第五非门的数量为偶数。
在一个示例中，第一生成单元132还包括第五延迟单元55；第五延迟单元55的输入端与第一触发器51的输出端连接，第五延迟单元55用于将第一触发器51输出的信号进行反相延迟输出得到第一输出时钟CLK_2_O的反相信号CLK_2_OB；第二生成单元133还包括第六延迟单元56；第六延迟单元56的输入端与第二触发器53的输出端连接，第六延迟单元56用于将第二触发器53输出的信号进行反相延迟输出得到第二输出时钟CLK_2_E的反相信号CLK_2_EB。本示例中，通过生成输出时钟的反相信号，提高输出时钟信号的丰富性。作为示例，第五延迟单元55和第六延迟单元56均包括串联的多个第六非门，其中多个第六非门的数量为奇数。本示例中，通过常规的非门实现反相延迟处理，实现进一步简化电路结构。
同样考虑到第一生成单元和第二生成单元的复位功能，在一个示例中，生成模块13还包括：第二复位单元134；第二复位单元134包括：第八非门61、第九非门62、第五或非门63和第六或非门64；
第八非门61的输入端与第一传输单元41的输出端连接，第八非门61的输出端与第五或非门63的第一输入端连接；第五或非门63的第二输入端与第六或非门64的第一输入端连接，第五或非门63的输出端与第一生成单元132的使能端连接；
第九非门62的输入端与第二传输单元42的输出端连接，第九非门62的输出端与第六或非门64的第二输入端连接；第六或非门64的第一输入端接收复位信号VPU RST，第六或非门64的输出端与 第二生成单元133的使能端连接。
本示例中，为第一生成单元和第二生成单元设置第二复位单元，实现对生成单元的复位功能，提高电路运行的可靠性，并且电路结构简单。
本实施例提供的时钟生成电路中，采样模块基于奇时钟和偶时钟对连续的片选信号进行采样获得奇数据和偶数据，检测模块基于奇数据和偶数据检测前后相邻的片选信号是否满足预定条件，当检测到相邻的片选信号满足预定条件时，生成模块开始生成输出时钟。通过上述方案，可以根据实际测试设定能够表征开始进行片选测试的预定条件，实现基于时钟周期为系统时钟周期两倍的奇时钟和偶时钟对片选信号中各数据位的采集、检测并及时地生成输出时钟，从而能够在保证采样准确可靠的同时及时地生成和提供输出时钟，该输出时钟可用于配合片选测试结果的准确输出，实现准确可靠的片选测试。
实施例二
本公开实施例二提供一种存储器，该存储器包括：芯片测试电路以及如前的时钟生成电路；其中，
时钟生成电路和芯片测试电路连接，用于为芯片测试电路提供输出时钟，芯片测试电路用于对存储器进行片选信号测试。
作为示例，当需要进行CS测试时，可以启动芯片测试电路和时钟生成电路进入CSTM模式。经过一定时间后，开始输入片选信号的样本信号，时钟生成电路检测到样本信号时，开始生成输出时钟；同时，芯片测试电路采用奇时钟和偶时钟进行采样，得到奇数据和偶数据。其中，奇时钟和偶时钟的相位相反，且周期为系统时钟周期的两倍，因此可以为片选信号的采样提供充足的采样窗口，避免采样错误和采样失败，保证CS测试的准确性。基于采样得到的奇数据和偶数据，整合得到完整的片选信号进行片选测试运算，得到运算结果在时钟生成电路提供的输出时钟的上升沿到来时输出。基于输出的运算结果和标准结果进行比较，判断片选信号接收是否正常。
本实施例提供的存储器中，芯片测试电路基于奇时钟和偶时钟进行采样进行对比运算获得运算结果，响应于时钟生成电路提供的输出时钟输出运算结果。具体的，时钟生成电路的采样模块基于奇时钟和偶时钟进行采样获得奇数据和偶数据，检测模块基于奇数据和偶数据检测前后相邻的片选信号是否满足预定条件，当检测到相邻的片选信号满足预定条件时，生成模块开始生成输出时钟。通过上述方案，可以根据实际测试设定能够表征开始进行片选测试的预定条件，实现基于时钟周期为系统时钟周期两倍的奇时钟和偶时钟对片选信号中各数据位的采集、检测并及时地生成输出时钟，从而能够在保证采样准确可靠的同时及时地生成和提供输出时钟，该输出时钟可用于配合片选测试结果的准确输出，实现准确可靠的片选测试。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示 例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (14)

  1. 一种时钟生成电路，包括：
    采样模块，用于基于采样时钟对连续的片选信号进行采样，所述片选信号的每一数据位的保持时长等于系统时钟的周期，所述采样时钟包含相位相反的奇时钟和偶时钟，所述奇时钟和所述偶时钟的周期等于所述系统时钟的周期的两倍，记基于所述奇时钟采样得到的数据为奇数据，记基于所述偶时钟采样得到的数据为偶数据；
    检测模块，与所述采样模块连接，用于当检测到相邻的片选信号满足预定条件时，输出第一状态的指示信号，否则输出第二状态的指示信号；其中，所述预定条件包括前一片选信号的数据位均为第一电平状态，且后一片选信号的首个数据位为第二电平状态；
    生成模块，与所述检测模块连接，用于在所述指示信号处于第一状态时，生成输出时钟；其中，所述输出时钟的周期为单个片选信号的长度，所述输出时钟的上升沿与最先采样到所述首个数据位为低电平状态的所述后一片选信号的所述采样时钟的上升沿对齐。
  2. 根据权利要求1所述的时钟生成电路，其中，每个片选信号包括四个数据位。
  3. 根据权利要求2所述的时钟生成电路，其中，所述检测模块包括：第一延迟单元、第二延迟单元、第一运算单元和第二运算单元；
    所述第一延迟单元，与所述采样模块连接，用于将所述奇数据按照预定的时间间隔依次延时输出，得到第一延迟奇数据、第二延迟奇数据、第三延迟奇数据、第四延迟奇数据和第五延迟奇数据；
    所述第二延迟单元，与所述采样模块连接，用于将所述偶数据按照所述时间间隔依次延时输出，得到第一延迟偶数据、第二延迟偶数据、第三延迟偶数据、第四延迟偶数据和第五延迟偶数据；
    所述第一运算单元的输入端与所述第一延迟单元和所述第二延迟单元连接，所述第一运算单元用于接收所述第一延迟奇数据、所述第二延迟偶数据、所述第三延迟奇数据、所述第四延迟偶数据和所述第五延迟奇数据，并检测是否满足所述预定条件；第一运算单元的输出端与所述生成模块连接；
    所述第二运算单元的输入端与所述第一延迟单元和所述第二延迟单元连接，所述第二运算单元用于接收所述第一延迟偶数据、所述第二延迟奇数据、所述第三延迟偶数据、所述第四延迟奇数据和所述第五延迟偶数据，并检测是否满足所述预定条件；所述第二运算单元的输出端与所述生成模块连接。
  4. 根据权利要求3所述的时钟生成电路，其中，
    所述第一运算单元包括：第一非门、第一与非门和第二与非门、以及第一或非门；所述第一非门的输入端接收所述第一延迟奇数据，所述第一非门的输出端与所述第一与非门的第一输入端连接；所述第一与非门的第二输入端接收所述第二延迟偶数据，所述第一与非门的第三输入端接收所述第三延迟奇数据，所述第一与非门的输出端与所述第一或非门的第一输入端连接；所述第二与非门的第一输入端接收 所述第四延迟偶数据，所述第二与非门的第二输入端接收所述第五延迟奇数据，所述第二与非门的输出端与所述第一或非门的第二输入端连接；所述第一或非门的输出端与所述生成模块连接；
    所述第二运算单元包括：第二非门、第三与非门和第四与非门、以及第二或非门；所述第二非门的输入端接收所述第一延迟偶数据，所述第二非门的输出端与所述第三与非门的第一输入端连接；所述第三与非门的第二输入端接收所述第二延迟奇数据，所述第三与非门的第三输入端接收所述第三延迟偶数据，所述第三与非门的输出端与所述第二或非门的第一输入端连接；所述第四与非门的第一输入端接收所述第四延迟奇数据，所述第四与非门的第二输入端接收所述第五延迟偶数据，所述第四与非门的输出端与所述第二或非门的第二输入端连接；所述第二或非门的输出端与所述生成模块连接。
  5. 根据权利要求3所述的时钟生成电路，其中，
    所述第一延迟单元包括：多个串联的第一延迟子单元；首个第一延迟子单元的输入端与所述采样模块连接，用于接收基于所述奇数据生成的所述第一延迟奇数据；每个第一延迟子单元的输入端与前一第一延迟子单元的输出端连接，每个第一延迟子单元用于将接收的数据经过所述时间间隔后输出；
    所述第二延迟单元包括：多个串联的第二延迟子单元；首个第二延迟子单元的输入端与所述采样模块连接，用于接收基于所述偶数据生成的所述第一延迟偶数据；每个第二延迟子单元的输入端与前一第二延迟子单元的输出端连接，每个第二延迟子单元用于将接收的数据经过所述时间间隔后输出。
  6. 根据权利要求3-5任一项所述的时钟生成电路，其中，所述输出时钟包括相位相反的第一输出时钟和第二输出时钟；
    在同一时刻下，所述第一输出时钟或所述第二输出时钟有效；其中任一输出时钟有效表征该输出时钟对应的采样时钟最先采样到所述首个数据位为低电平状态的所述后一片选信号。
  7. 根据权利要求6所述的时钟生成电路，其中，所述生成模块包括：选择单元、第一生成单元和第二生成单元；
    所述选择单元与所述第一运算单元和所述第二运算单元连接；所述选择单元用于响应于所述第一运算单元先输出第一状态的指示信号，向所述第一生成单元输出有效的第一使能信号；以及，响应于所述第二运算单元先输出第一状态的指示信号，向所述第二生成单元输出有效的第二使能信号；
    所述第一生成单元的使能端与所述选择单元连接，所述第一生成单元接收所述奇时钟，所述第一生成单元用于响应于所述第一使能信号有效，对所述奇时钟进行分频，输出所述第一输出时钟；
    所述第二生成单元的使能端与所述选择单元连接，所述第二生成单元接收所述偶时钟，所述第二生成单元用于响应于所述第二使能信号有效，对所述偶时钟进行分频，输出所述第二输出时钟。
  8. 根据权利要求7所述的时钟生成电路，其中，
    所述第一生成单元包括第一触发器和第三延迟单元；所述第一触发器的输入端与所述第一触发器的反相输出端连接，所述第一触发器的时钟端接收所述奇时钟，所述第一触发器的复位端为所述第一生成 单元的使能端，所述第一触发器的输出端与所述第三延迟单元的输入端连接；所述第三延迟单元用于将所述第一触发器输出的信号延迟输出得到所述第一输出时钟；
    所述第二生成单元包括第二触发器和第四延迟单元；所述第二触发器的输入端与所述第二触发器的反相输出端连接，所述第二触发器的时钟端接收所述偶时钟，所述第二触发器的复位端为所述第二生成单元的使能端，所述第二触发器的输出端与所述第四延迟单元的输入端连接；所述第四延迟单元用于将所述第二触发器输出的信号延迟输出得到所述第二输出时钟。
  9. 根据权利要求8所述的时钟生成电路，其中，
    所述第一生成单元还包括第五延迟单元；所述第五延迟单元的输入端与所述第一触发器的输出端连接，所述第五延迟单元用于将所述第一触发器输出的信号进行反相延迟输出得到所述第一输出时钟的反相信号；
    所述第二生成单元还包括第六延迟单元；所述第六延迟单元的输入端与所述第二触发器的输出端连接，所述第六延迟单元用于将所述第二触发器输出的信号进行反相延迟输出得到所述第二输出时钟的反相信号。
  10. 根据权利要求7-9任一项所述的时钟生成电路，其中，所述选择单元包括：第一传输单元、第二传输单元和控制单元；所述第一传输单元的输入端接收第一高电平信号，所述第一传输单元的控制端接收所述第一运算单元输出的指示信号，所述第一传输单元的输出端连接至所述第一生成单元的使能端和所述控制单元；所述第一传输单元用于在所述第一运算单元输出的指示信号处于第一状态时，将所述第一高电平信号传输至所述控制单元；
    所述第二传输单元的输入端接收第二高电平信号，所述第二传输单元的控制端接收所述第二运算单元输出的指示信号，所述第二传输单元的输出端连接至所述第二生成单元的使能端和所述控制单元；所述第二传输单元用于在所述第二运算单元输出的指示信号处于第一状态时，将所述第二高电平信号传输至所述控制单元；
    所述控制单元与所述第一传输单元的使能端和所述第二传输单元的使能端连接，用于当接收到所述第一传输单元输出的信号时，使能所述第一传输单元并复位所述第二传输单元；以及当接收到所述第二传输单元输出的信号时，使能所述第二传输单元并复位所述第一传输单元。
  11. 根据权利要求10所述的时钟生成电路，其中，所述控制单元包括：第三或非门和第四或非门；
    所述第三或非门的输入端与所述第二传输单元的输出端连接，所述第三或非门的输出端与所述第一传输单元的使能端连接；
    所述第四或非门的输入端与所述第一传输单元的输出端连接，所述第四或非门的输出端与所述第二传输单元的使能端连接。
  12. 根据权利要求11所述的时钟生成电路，其中，所述控制单元还包括：第一复位单元；
    所述第一复位单元包括：第七非门和或门；所述第七非门的输入端接收测试模式信号，所述第七非门的输出端连接至所述或门的第一输入端；所述或门的第二输入端接收复位信号，所述或门的输出端连接至所述第三或非门的另一输入端和所述第四或非门的另一输入端。
  13. 根据权利要求10所述的时钟生成电路，其中，所述生成模块还包括：第二复位单元；所述第二复位单元包括：第八非门、第九非门、第五或非门和第六或非门；
    所述第八非门的输入端与所述第一传输单元的输出端连接，所述第八非门的输出端与所述第五或非门的第一输入端连接；所述第五或非门的第二输入端与所述第六或非门的第一输入端连接，所述第五或非门的输出端与所述第一生成单元的使能端连接；
    所述第九非门的输入端与所述第二传输单元的输出端连接，所述第九非门的输出端与所述第六或非门的第二输入端连接；所述第六或非门的第一输入端接收所述复位信号，所述第六或非门的输出端与所述第二生成单元的使能端连接。
  14. 一种存储器，包括：如权利要求1-13任一项所述的时钟生成电路和芯片测试电路；其中，
    所述时钟生成电路和所述芯片测试电路连接，用于为所述芯片测试电路提供输出时钟，所述芯片测试电路用于对存储器进行片选信号测试。
PCT/CN2023/070338 2022-10-14 2023-01-04 时钟生成电路及存储器 WO2024077800A1 (zh)

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US20100244915A1 (en) * 2009-03-30 2010-09-30 Samsung Electronics Co., Ltd. Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same
US20180122486A1 (en) * 2016-10-27 2018-05-03 Samsung Electronics Co., Ltd. Memory device and clock training method thereof
CN110870010A (zh) * 2017-08-30 2020-03-06 美光科技公司 在ddr5 dram中调整到锁存路径的指令延迟
CN111541446A (zh) * 2020-05-18 2020-08-14 上海兆芯集成电路有限公司 时钟同步电路

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US20100244915A1 (en) * 2009-03-30 2010-09-30 Samsung Electronics Co., Ltd. Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same
US20180122486A1 (en) * 2016-10-27 2018-05-03 Samsung Electronics Co., Ltd. Memory device and clock training method thereof
CN110870010A (zh) * 2017-08-30 2020-03-06 美光科技公司 在ddr5 dram中调整到锁存路径的指令延迟
CN111541446A (zh) * 2020-05-18 2020-08-14 上海兆芯集成电路有限公司 时钟同步电路

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