WO2024068536A1 - Appareil de commutation, système informatique et procédé - Google Patents

Appareil de commutation, système informatique et procédé Download PDF

Info

Publication number
WO2024068536A1
WO2024068536A1 PCT/EP2023/076381 EP2023076381W WO2024068536A1 WO 2024068536 A1 WO2024068536 A1 WO 2024068536A1 EP 2023076381 W EP2023076381 W EP 2023076381W WO 2024068536 A1 WO2024068536 A1 WO 2024068536A1
Authority
WO
WIPO (PCT)
Prior art keywords
multiplexer
board
switching
signal line
connection pins
Prior art date
Application number
PCT/EP2023/076381
Other languages
German (de)
English (en)
Inventor
Dominik Kraus
Daniyal Noor
Original Assignee
Fujitsu Client Computing Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Client Computing Limited filed Critical Fujitsu Client Computing Limited
Publication of WO2024068536A1 publication Critical patent/WO2024068536A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling

Definitions

  • the present invention relates to a switching device for a printed circuit board, a computer system comprising such a switching device, and a method for operating such a computer system.
  • An object of the invention is to solve or mitigate the above problems.
  • a switching device for a printed circuit board the switching device being designed for connecting signal lines to a board-to-board connector, comprising:
  • connection pins for a board-to-board connector
  • At least one multiplexer which is designed to connect at least one signal line connected to the at least one multiplexer to at least one connection pin of the plurality of connection pins for the board-to-board connector
  • controller that is set up to evaluate switching information regarding a signal assignment of the at least one signal line and to switch the at least one multiplexer based on the evaluated switching information.
  • the switching device shown here is that platform independence is achieved for the board-to-board connector.
  • One and the same board-to-board connector also known as a board-to-board connector, can be used to connect another board, for example a so-called adapter board or input/output module board, to a circuit board on which the switching device is installed is appropriate to connect, regardless of what platform architecture is used on the circuit board and how signal lines are coded on the circuit board.
  • the at least one multiplexer comprises at least one 2-to-1 multiplexer.
  • 2-to-1 multiplexers represent particularly simple and cost-effective versions of such multiplexers, which ensure a particularly uncomplicated and simple structure of the switching device. Since 2-to-1 multiplexers only have two switching states, this also enables uncomplicated control and switching of the multiplexers used.
  • the at least one multiplexer comprises exactly three 2-to-1 multiplexers, wherein:
  • a first 2-to-1 multiplexer of the three 2-to-1 multiplexers is connected to both a second and a third 2-to-1 multiplexer
  • the second and third of the three 2-to-1 multiplexers are connected to corresponding pins of the plurality of pins for the board-to-board connector
  • the first 2-to-1 multiplexer is set up to connect a first signal line either to the second or the third 2-to-1 multiplexer
  • the second and the third 2-to-1 multiplexer are each set up to selectively connect a second or a third signal line or the first signal line to the corresponding connection pins.
  • Such a switching device with three 2-to-1 multiplexers makes it possible to connect a total of three signal lines on the circuit board with two signal lines of the board-to-board connector via the connection pins. This represents a particularly simple and cost-effective design of the switching device.
  • a computer system comprises a circuit board with a switching device according to one of the embodiments shown above.
  • this is based on
  • Switching information regarding the signal assignment of the at least one signal line on a platform architecture and/or adapter plate information is a platform architecture and/or adapter plate information.
  • the information based on a platform architecture includes, for example, the information as to whether e.g. B. an Intel chipset or an AMD chipset is used on the circuit board. Based on this information, the controller can then switch the at least one multiplexer in accordance with the signal line coding belonging to the respective chipsets.
  • information based on adapter plate information includes, for example, an adapter plate type that is to be connected to the plate-to-plate connector, for example that the adapter plate is a WLAN/LAN module plate, a PCIe module plate, a graphics module plate, or a USB module plate.
  • the information based on adapter plate information can also be a signal flow direction act with regard to the adapter plate provided.
  • the computer system can act as a host or sink, and the signal line codings can be different accordingly.
  • the adapter plate is, for example, a USB module plate
  • the computer system can be configured as a USB host or as a USB drain.
  • the signal line codings differ, so that with the switching device shown here, the signal lines are connected to the respective connection pins so that, depending on the configuration, the appropriate signals are present at the correct connection pins. be tapped.
  • the computer system further comprises a board-to-board connector connected to the plurality of connection pins and an adapter plate connected to the circuit board via the board-to-board connector.
  • the computer system further comprises a system processor, wherein the system processor is set up to apply signals to the signal lines after switching the at least one multiplexer.
  • the switching information is provided and the at least one multiplexer is switched before signals are applied to the signal lines by means of the system processor. In this way, it can be prevented that signals are incorrectly coded and sent to the connection pins, which can lead to errors or even defects.
  • the following steps are also carried out before the steps of evaluating the switching information and switching the at least one multiplexer:
  • the system can independently evaluate the corresponding information in order to provide suitable switching information to the controller.
  • the following step is also carried out:
  • Figure 1 shows a switching device according to a
  • FIG. 2 shows a switching device according to another
  • Figure 3 shows a computer system according to one
  • Figure 4 is a flow chart of a method according to an embodiment of the invention.
  • FIG. 1 shows a schematic representation of a switching device 1 according to an exemplary embodiment of the invention.
  • the switching device 1 is shown schematically here and shows a possible configuration; any further configurations are of course possible.
  • the switching device 1 includes a plurality of connection pins 2 for a board-to-board connector, which is not shown here.
  • connection pins 2 are shown here, which represent, for example, soldering points or plug-in devices on a circuit board for such a board-to-board connector. Any arrangement of such connection pins 2 is possible.
  • connection pins 2 Two of the connection pins 2 shown here are directly connected to signal lines 3a of a circuit board on which this switching device 1 is arranged.
  • the signal lines 3a that are directly connected to the connection pins 2 are signal lines 3a that always carry the same signal types regardless of the platform architecture used and regardless of the adapter plate used, so that no switching is necessary for these signal lines.
  • the switching device 1 further comprises a multiplexer 4.
  • the multiplexer 4 is a 2-to-1 multiplexer 4, which connects either two further signal lines 3b to one of the connection pins 2 or one further signal line 3b to one of the connection pins 2. This is indicated by dashed lines. lines in Figure 1.
  • the multiplexer 4 can of course also be a more complex multiplexer which can connect two or more signal lines 3b to two or more of the connection pins 2.
  • the switching device 1 also comprises a controller 5 which is designed to evaluate switching information relating to a signal assignment of the signal lines 3b connected to the multiplexer 4.
  • the controller 5 is, for example, an input/output controller, also known as an I/O controller.
  • the controller 5 is connected to the multiplexer 4 via a control line 6 and can thus switch the multiplexer 4 in accordance with the evaluated switching information.
  • the switching information can, for example, be based on platform information and/or adapter plate information, so that the signal lines 3b, which are coded depending on the platform, are connected to corresponding suitable connection pins 2, which correspond to an adapter plate type of an adapter plate which is connected to the plate-to-plate connector via a plate-to-plate connector Connection pins 2 should be connected or connected, different applied signals are required.
  • the same plate-to-plate connectors can always be used for different adapter plate types and platform architectures, as well as the same adapter plates for different platform architectures for the same adapter plate types.
  • Figure 2 shows a schematic representation of a
  • Switching device 1 according to an embodiment of the Invention.
  • the switching device 1 is shown schematically here and shows one possible embodiment; any other embodiments are of course possible. Details that have already been described with reference to Figure 1 are not explicitly repeated here, but apply accordingly.
  • the switching device 1 comprises a total of three 2-to-1 multiplexers 4a, 4b, 4c.
  • a first multiplexer 4a is connected to a first signal line 7a, which provides a first signal input.
  • the first multiplexer 4a is set up to selectively connect this first signal line 7a to one of two outputs of the first multiplexer 4a.
  • a second multiplexer 4b and a third multiplexer 4c of the three 2-to-1 multiplexers of the switching device 1 are each arranged in such a way that one of two inputs can be selectively connected to an output.
  • the second multiplexer 4b has a second signal line 7b and one of the outputs of the first multiplexer 4a as inputs, corresponding to the first signal line 7a when connected accordingly.
  • the third multiplexer 4c has a third signal line 7c and the other of the outputs of the first multiplexer 4a as inputs, corresponding to the first signal line 7a when connected accordingly. All signal lines 7a, 7b, 7c and corresponding connections are shown here with double lines for differential signal transmission. Alternatively, single lines can of course also be used, depending on the area of application.
  • the outputs of the second and third multiplexers 4b, 4c are connected to connection pins 2a, 2b of a plate-to-plate connector 8.
  • the plate-to-plate connector 8 represents a connection port for an adapter plate 9.
  • the signals present at pins 2a, 2b are forwarded to the adapter plate 9 via the plate-to-plate connector 8.
  • the adapter plate 9 is, for example, a module plate, also known as a flexible input/output plate (FlexIO plate), which provides a connection of a module, for example a WLAN and/or LAN module, a graphics module, e.g. a DisplayPort module, a PCIe module, or a USB module.
  • a module plate also known as a flexible input/output plate (FlexIO plate)
  • a graphics module e.g. a DisplayPort module, a PCIe module, or a USB module.
  • All three multiplexers 4a, 4b, 4c also each have a control connection 10a, 10b, 10c, via which the multiplexers 4a, 4b, 4c are connected to corresponding control pins 11 of a controller 5 using control lines not shown here.
  • the controller 5 is set up via these control pins 11 to send control signals to the respective multiplexers 4a, 4b, 4c and to switch them based on control information, for example information regarding a platform architecture used or an adapter plate type used.
  • the controller 5 is connected via an I2C bus (clock signal and data signal) directly via the plate-to-plate connector 8 to an I2C EEPROM (Electrically Erasable Programmable Read-Only Memory) memory module 12, via which the controller 5 can read information from the EEPROM memory module 12, for example information regarding an adapter plate type or a signal flow direction (e.g. whether it is a host or a receiver). About it
  • the controller 5 knows in which platform architecture the switching device 1 is used. For this purpose, the controller 5 also has a memory module, not shown here, for example. All this information can then be used to switch the multiplexers 4a, 4b, 4c accordingly.
  • the controller 5 includes, for example, a list in which available types of adapter plates 9 (or corresponding types of modules) and associated switching states of the multiplexers 4a, 4b, 4c are linked. An example of this looks like this:
  • MUX 1 to 3 stand for the first multiplexer (MUX1), second multiplexer (MUX2), and the third multiplexer (MUX3).
  • the multiplexers 4a, 4b, 4c can be switched so that the desired signals are present at the respective connection pins 2a, 2b.
  • FIG 3 shows a schematic representation of a computer system 13 according to an embodiment of the invention.
  • the computer system 13 is shown schematically here and shows a possible embodiment, any Further configurations are of course possible. Details which have already been described with reference to Figures 1 and 2 are not explicitly repeated here, but apply accordingly.
  • the computer system 13 includes a system board 14 on which a switching device 1 is arranged, for example a switching device 1 as described according to FIG. 1 or FIG. 2.
  • the system board 14 is chosen here as an example; it can also be any other circuit board.
  • the switching device 1 is further connected to a plate-to-plate connector 8 and an adapter plate 9.
  • An EEPROM memory module 12 is arranged on the adapter plate 9. Details of this have already been described with reference to FIGS. 1 and 2 and will not be repeated here.
  • a system processor 15 is also arranged on the system board 14.
  • the system processor 15 is, for example, set up to start a BIOS of the computer system 14 or to wake up the computer system 14 from a sleep state and, when switching of the multiplexers of the switching device 1 is completed, to apply the corresponding signals to the signal lines.
  • Figure 4 shows a flowchart of a method according to an exemplary embodiment of the invention.
  • Figure 4 shows a possible embodiment of such a method; any further embodiments are of course possible.
  • the method according to FIG. 4 is particularly suitable for a switching device or to operate a computer system according to one of the examples as described with reference to Figures 1, 2 and 3. Details already related to figures 1, 2 and 3 are not explicitly repeated here, but apply accordingly.
  • a BIOS of a computer system is started or the computer system is woken up from a sleep state.
  • step S2 adapter plate information is read from a memory module of an adapter plate connected to a plurality of connection pins of the switching device via a plate-to-plate connector.
  • a platform architecture used in the computer system in which the switching device is arranged is determined.
  • step S5 switching information regarding a signal assignment of at least one signal line of the switching device is evaluated.
  • a step S 6 at least one multiplexer of the switching device is switched based on the evaluated switching information.
  • a step S 6 signals are applied to the at least one signal line of the switching device.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Information Transfer Systems (AREA)

Abstract

L'invention concerne un appareil de commutation (1) pour une carte de circuit imprimé (14), l'appareil de commutation (1), pour appliquer des lignes de signal à un connecteur carte à carte (8), comprenant : - une pluralité de broches de connexion (2) pour un connecteur carte à carte (8), au moins un multiplexeur (4) qui est configuré pour connecter au moins une ligne de signal (3, 7) appliquée au ou aux multiplexeurs (4) à au moins une broche de connexion (2) de la pluralité de broches de connexion (2) pour le connecteur carte à carte (8), - un dispositif de commande (5) qui est configuré pour évaluer des informations de commutation relatives à une attribution de signal de la ou des lignes de signal (3, 7) et pour commuter le ou les multiplexeurs (4) sur la base des informations de commutation évaluées.
PCT/EP2023/076381 2022-09-28 2023-09-25 Appareil de commutation, système informatique et procédé WO2024068536A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102022124995.6 2022-09-28
DE102022124995.6A DE102022124995A1 (de) 2022-09-28 2022-09-28 Schaltvorrichtung, Computersystem, und Verfahren

Publications (1)

Publication Number Publication Date
WO2024068536A1 true WO2024068536A1 (fr) 2024-04-04

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WO (1) WO2024068536A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004045527A1 (de) * 2003-10-08 2005-05-19 Siemens Ag Konfigurierbare Logikschaltungsanordnung
US20100049878A1 (en) * 2004-02-12 2010-02-25 Super Talent Electronics, Inc. Differential Data Transfer For Flash Memory Card
US20200019526A1 (en) * 2018-07-12 2020-01-16 Texas Instruments Incorporated Detection of displayport alternate mode communication and connector plug orientation without use of a power distribution controller
CN112306952A (zh) * 2020-11-25 2021-02-02 海光信息技术股份有限公司 一种主机板及服务器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004045527A1 (de) * 2003-10-08 2005-05-19 Siemens Ag Konfigurierbare Logikschaltungsanordnung
US20100049878A1 (en) * 2004-02-12 2010-02-25 Super Talent Electronics, Inc. Differential Data Transfer For Flash Memory Card
US20200019526A1 (en) * 2018-07-12 2020-01-16 Texas Instruments Incorporated Detection of displayport alternate mode communication and connector plug orientation without use of a power distribution controller
CN112306952A (zh) * 2020-11-25 2021-02-02 海光信息技术股份有限公司 一种主机板及服务器

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