WO2024066533A1

WO2024066533A1 - Chip assembly and information processing method thereof, and computer readable medium

Info

Publication number: WO2024066533A1
Application number: PCT/CN2023/102614
Authority: WO
Inventors: 杜嘉宇; 孙福山; 潘跃
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2022-09-30
Filing date: 2023-06-27
Publication date: 2024-04-04
Also published as: CN117854566A

Abstract

The present invention provides an information processing method of a chip assembly. The chip assembly comprises a chip, an information memory, and a one-time programmable memory eFUSE. The method comprises: encrypting a plaintext of confidential information according to an information encryption algorithm to obtain a ciphertext of the confidential information; and writing the ciphertext of the confidential information into the information memory, and writing configuration information into the eFUSE, wherein the configuration information represents the storage situation of the ciphertext of the confidential information in the information memory. The present invention further provides a chip assembly and a computer readable medium.

Description

Chip assembly and information processing method thereof, and computer readable medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application claims priority to Chinese patent application 202211230338.7 filed with the State Intellectual Property Office of China on September 30, 2022, and the disclosure of this Chinese patent application is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to the field of chip technology, and in particular to a chip component and an information processing method thereof, and a computer-readable medium.

Background technique

Security information used by a chip (such as a security chip) can be stored in a one-time programmable memory eFUSE to ensure that it cannot be modified.

However, in the related art, the storage space of the eFUSE used in the chip is insufficient and it is difficult to meet the requirements of customers.

Summary of the invention

The present disclosure provides a chip component and an information processing method thereof, and a computer-readable medium.

In a first aspect, an embodiment of the present disclosure provides a method for information processing of a chip component, wherein the chip component includes a chip, an information storage device, and an eFUSE. The method includes: encrypting plaintext of confidential information according to an information encryption algorithm to obtain ciphertext of the confidential information; writing the ciphertext of the confidential information into the information storage device, and writing configuration information into the eFUSE, wherein the configuration information represents the storage status of the ciphertext of the confidential information in the information storage device.

In a second aspect, the present disclosure provides a method for information processing of a chip component, wherein the chip component includes a chip, an information storage device, and an eFUSE; the information storage device stores ciphertext of confidential information, and the ciphertext of the confidential information is encrypted according to an information encryption algorithm. The eFUSE stores configuration information, and the configuration information represents the storage status of the ciphertext of the confidential information in the information storage device. The method includes: reading the configuration information stored in the eFUSE; reading the ciphertext of the confidential information from the information storage device according to the configuration information; and decrypting the ciphertext of the confidential information according to the information encryption algorithm to obtain the plaintext of the confidential information.

In a third aspect, an embodiment of the present disclosure provides a chip component, including a chip, an information storage device, and an eFUSE, wherein the chip can implement an information processing method of any chip component of the embodiment of the present disclosure.

In some embodiments, the information storage includes a flash memory FLASH.

In a fourth aspect, an embodiment of the present disclosure provides a non-temporary computer-readable medium having a computer program stored thereon, which, when executed by a processor, can implement a method for information processing in which the chip can implement any chip component of the embodiment of the present disclosure.

In the disclosed embodiments, confidential information is actually stored in an information storage device (such as FLASH), and eFUSE only stores its configuration information. Therefore, no matter how large the confidential information is, the space required for eFUSE is very small, thereby being able to store a larger amount of information at a low cost of eFUSE to meet customer needs. At the same time, the confidential information is encrypted, and its configuration information is stored in eFUSE and cannot be modified. Therefore, although the confidential information is actually located in the information storage device, its security is still very high and cannot be cracked or tampered with.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings of the embodiments of the present disclosure:

FIG1 is a block diagram of a chip assembly according to an embodiment of the present disclosure;

FIG2 is a flow chart of a method for information processing of a chip assembly provided by an embodiment of the present disclosure;

FIG3 is a flow chart of a method for information processing of a chip assembly provided by another embodiment of the present disclosure;

FIG4 is a flow chart of a method for information processing of a chip component provided by another embodiment of the present disclosure;

FIG5 is a flow chart of a method for information processing of a chip assembly provided by another embodiment of the present disclosure;

FIG. 6 is a logic diagram of a method for processing information of a chip component provided in an embodiment of the present disclosure. Process diagram;

FIG. 7 is a block diagram of the composition of a computer-readable medium provided in an embodiment of the present disclosure.

Detailed ways

In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the chip assembly and its information processing method and computer-readable medium provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

The present disclosure may be described with reference to plan views and/or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and/or tolerances.

In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and/or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an unreasonable meaning. The meaning of the wording should not be taken in an abstract or excessive form unless the present disclosure clearly defines it as such.

The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

In some related technologies, security information used by a chip (eg, a security chip) may be stored in a one-time programmable memory (eFUSE).

One-time programmable memory is called eFUSE or OTP (One Time Programable). It is a special memory whose physical properties can ensure that it can only be written once (if written, the fuse structure will be burned out). Therefore, once the information is written into it, it cannot be modified again (for example, because the fuse is broken).

Some of the information used by the chip requires high security and cannot be changed. This type of information is called "security information". Based on the need for security information, it can be stored in eFUSE to ensure that it cannot be tampered with.

However, the eFUSE used in chips is often expensive, so the storage space is limited and is often fixed when the chip is designed. In contrast, the amount of security information data may vary depending on the needs (such as different services). For example, customers may require that their serial (SN) code, market code, access code, etc. be stored in the eFUSE as security information.

This results in that in some cases, the eFUSE storage space used by the chip is insufficient to meet customer needs.

An embodiment of the present disclosure provides a method for information processing of a chip component, wherein the chip component includes a chip, an information storage device, and an eFUSE.

The information processing method of the embodiment of the present disclosure is executed by a chip component, that is, it is a method for the chip component to process information.

1 , the chip assembly of the embodiment of the present disclosure includes a chip (processor) that actually performs data operations, and an information memory and eFUSE for storing information (or data).

It should be understood that the above chips, information storage, and eFUSE can communicate with each other, that is, the chip can write information to the information storage and eFUSE, and can also read information from the information storage and eFUSE. The chip component also has an external interface for receiving external instructions (such as from software) to perform corresponding operations and feedback the results of the operations to the outside.

eFUSE can be integrated with the chip (i.e., on-chip storage), and information storage The memory is a rewritable memory that can be stored outside the chip (i.e., off-chip storage).

In some embodiments, the information storage includes a flash memory FLASH.

As one embodiment of the present disclosure, FLASH (such as off-chip FLASH) may be used as an information storage device in a chip component.

It should be understood that the specific form of the information storage device in the embodiments of the present disclosure is not limited thereto, and it may also be other forms of storage device.

2 , the method for information processing of a chip assembly according to an embodiment of the present disclosure includes steps S101 and S102 .

In step S101, the plain text of the confidential information is encrypted according to the information encryption algorithm to obtain the cipher text of the confidential information.

The chip uses a preset encryption algorithm (called an information encryption algorithm) to encrypt the plain text of the information that needs to be kept confidential (i.e., the confidential information, that is, the information to be stored in the eFUSE) to obtain the ciphertext of the confidential information.

The specific form of the information encryption algorithm is diverse, for example, it can be a symmetric encryption algorithm such as AES_CBC256.

In step S102, the ciphertext of the confidential information is written into the information storage device, and the configuration information is written into the eFUSE.

The configuration information represents the storage status of the ciphertext of the confidential information in the information storage device.

The chip writes the ciphertext of the confidential information obtained above into the information storage device (such as FLASH), and writes the storage status (such as address) of the ciphertext of the confidential information in the information storage device into the eFUSE as configuration information, so that the written configuration information cannot be modified.

Therefore, when confidential information is needed, the configuration information must be obtained from the eFUSE first, and the confidential information (specifically, the ciphertext of the confidential information) is determined in the information storage according to the configuration information, and then the confidential information is obtained from the information storage. Therefore, even if the hacker tampers with the confidential information in the information storage (such as writing "fake" confidential information in other locations of the information storage), the storage of the tampered information does not match the configuration information in the eFUSE (the configuration information cannot be modified), so the chip component still will not obtain the tampered information.

In the disclosed embodiment, the confidential information is actually stored in the information storage device (such as FLASH) eFUSE only stores its configuration information. Therefore, no matter how large the confidential information is, the space required by eFUSE is very small, so that more information can be stored at a low cost of eFUSE to meet customer needs. At the same time, the confidential information is encrypted, and its configuration information is stored in eFUSE and cannot be modified. Therefore, although the confidential information is actually located in the information storage device, its security is still very high and cannot be cracked or tampered with.

In some embodiments, the configuration information includes at least one of the following: the address of the ciphertext of the confidential information in the information storage device, the size of the ciphertext of the confidential information, and the configuration of whether the confidential information is readable by the software.

As one mode of an embodiment of the present disclosure, the configuration information may include the storage address of the confidential information, the size of the information, etc., and may also include a configuration indicating whether the confidential information is readable by the software, etc., so that the confidential information can be read from the information storage in a corresponding manner based on this information.

In some embodiments, the chip includes an encryption interface, and the information key is embedded in the chip.

3 , encrypting the plain text of confidential information according to the information encryption algorithm to obtain the cipher text of the confidential information ( S101 ) includes steps S1011 and S1012 .

In step S1011, through the encryption interface, the chip uses the information key according to the information encryption algorithm to encrypt the plain text of the confidential information to obtain the cipher text of the confidential information.

In step S1012, the encryption interface is closed.

As a method of the embodiment of the present disclosure, confidential information can be encrypted through an encryption interface using an information key solidified in the chip, and then the encryption interface is permanently closed (such as solidifying another eFUSE built into the chip), thereby ensuring that hackers cannot obtain the information key to crack the confidential information, and cannot use the chip to re-encrypt to obtain "fake" confidential information, thereby further improving the security of the confidential information.

For example, during the production process of the chip, an information key can be randomly generated on the hardware. The information key is fixed in the chip, so it cannot be modified or obtained again (because it is randomly generated). In addition, the information key is invisible and inaccessible to the outside world (such as software). The software can only implement encryption operations through the encryption interface of the chip hardware (such as the encryption and decryption module controlled by a specific register). After the encryption of the confidential information is completed, the encryption interface can be closed by hardware, so that it cannot be reused.

In some embodiments, referring to FIG. 3 , the method of the embodiment of the present disclosure further includes steps S1031 and S1032 .

In step S1031, verification information is generated according to the ciphertext of the confidential information and/or the plaintext of the confidential information.

In step S1032, the verification information is written into the information storage.

As a method of an embodiment of the present disclosure, verification information (such as a "certificate") derived from confidential information (plain text, cipher text) may also be stored in an information storage device so that when the confidential information is read, the confidential information may be verified based on the verification information to determine whether it is correct.

The specific forms of verification information are diverse.

For example, the verification information can be attached to the header of the ciphertext of the confidential information, thereby serving as its "header certificate".

For example, the verification information can be a check value (such as a hash value) calculated based on the confidential information (ciphertext, plaintext), so that when reading the confidential information, its check value can be calculated again, and the correctness of the confidential information can be judged based on whether the calculated check value is the same as the check value in the verification information.

For another example, the verification information itself can also be encrypted by a preset encryption algorithm (such as a verification encryption algorithm). For example, the verification encryption algorithm can be an asymmetric encryption algorithm such as RSA2048, which is encrypted by a private key, and the verification information is decrypted by a public key when reading confidential information.

For example, as long as confidential information (ciphertext, plaintext) is generated, the corresponding verification information can be calculated based on it and the verification information can be written into the information storage device. Therefore, the numbering and description order of the above steps do not necessarily represent their execution order. For example, the process of writing the verification information into the information storage device can be performed before or after the process of writing the confidential information into the information storage device, or it can be performed simultaneously (such as writing as a header certificate of confidential information).

It should be understood that the above chips, information storage, and eFUSE can communicate with each other, that is, the chip can write information to the information storage and eFUSE, and can also read information from the information storage and eFUSE; at the same time, the chip component also has an external interface to receive external Instructions (such as from software) are used to perform corresponding operations and the results of the operations are fed back to the outside.

The eFUSE may be integrated with the chip (ie, on-chip storage), while the information memory is a rewritable memory that may be located outside the chip (ie, off-chip storage).

In some embodiments, the information storage includes FLASH.

The information storage device stores ciphertext of confidential information, which is obtained by encrypting plaintext of the confidential information according to an information encryption algorithm. The eFUSE stores configuration information, which represents the storage status of the ciphertext of the confidential information in the information storage device.

The information in the chip component of the embodiment of the present disclosure is written by the above chip component information processing method, so the ciphertext of confidential information is stored in its information storage, and the corresponding configuration information is stored in the eFUSE.

4 , the information processing method of the chip assembly according to the embodiment of the present disclosure includes steps S201 to S203 .

In step S201, the configuration information stored in the eFUSE is read.

When confidential information is needed, the chip first reads its configuration information from eFUSE.

In step S202, the ciphertext of the confidential information is read from the information storage according to the configuration information.

Then, the chip can actually read the ciphertext of the corresponding confidential information from the information storage (such as FLASH) according to the above configuration information.

For example, the corresponding information may be read from the information storage device according to the address and size of the ciphertext of the confidential information, and whether the confidential information is readable by the software may be determined according to the configuration.

In step S203, the ciphertext of the confidential information is decrypted according to the information encryption algorithm to obtain the plaintext of the confidential information.

After obtaining the ciphertext of the confidential information, the chip can perform corresponding decryption according to the information encryption algorithm to obtain the plaintext of the confidential information for subsequent use.

It should be understood that the prerequisite for executing the above steps is that the configuration information is stored in the eFUSE, that is, the eFUSE has been solidified. If there is no configuration information in the eFUSE (not solidified), the above steps do not need to be performed.

In some embodiments, referring to FIG. 5 , reading the configuration information stored in the eFUSE includes step S2011 .

In step S2011, in response to the chip remotely starting the bootrom, the configuration information stored in the eFUSE is read.

As one method of an embodiment of the present disclosure, the above process of reading confidential information can be performed when the chip is in bootrom, and can only be performed when the chip is in bootrom, so that the confidential information can be used after the chip is started, and it can be ensured that the above steps are not performed in other processes, thereby further improving the security of the confidential information.

In some embodiments, referring to FIG. 5 , after decrypting the ciphertext of the confidential information according to the information encryption algorithm to obtain the plaintext of the confidential information ( S203 ), step S205 is further included.

In step S205, the plain text of the confidential information is written into the random access memory RAM.

As one method of an embodiment of the present disclosure, the plain text of the confidential information obtained by the above decryption can be stored in the RAM of the chip, so that the confidential information (plain text) can be obtained from the RAM at any time and used after the chip is started.

The confidential information in the RAM can also have different forms as needed. For example, whether the confidential information is readable by the software can be set when writing to the RAM based on the configuration of whether the confidential information is readable by the software.

In some embodiments, the chip includes a decryption interface, and the information key is embedded in the chip.

5 , decrypting the ciphertext of the confidential information according to the information encryption algorithm to obtain the plaintext of the confidential information ( S203 ) includes step S2031 .

In step S2031, through the decryption interface, the chip uses the information key according to the information encryption algorithm to decrypt the ciphertext of the confidential information to obtain the plaintext of the confidential information.

As one method of an embodiment of the present disclosure, when the ciphertext of the confidential information is encrypted using the fixed information key through the above writing interface, the chip may also have a hardware decryption interface.

Therefore, after the confidential information is encrypted through the write interface and the write interface is permanently closed, in the subsequent reading process (such as when the chip bootrom), the software calls the decryption interface to make the chip decrypt with the information key solidified in it, so that the outside world can only obtain the plaintext as the decryption result, but still cannot access the information key, further improving security.

In some embodiments, the information storage device further stores verification information, where the verification information is generated based on the ciphertext of the confidential information and/or the plaintext of the confidential information.

5 , the method of the embodiment of the present disclosure further includes steps S2041 and S2042 .

In step S2041, the verification information stored in the information storage is read.

In step S2042, the ciphertext of the confidential information and/or the plaintext of the confidential information is verified according to the verification information.

As a method of an embodiment of the present disclosure, when the above verification information is also stored in the information storage device, the above verification information can also be used to verify the correctness of the verification information during the process of reading the confidential information.

It should be understood that the specific methods of using verification information for verification are diverse and correspond to the form of the verification information.

For example, the verification information may be attached to the header of the ciphertext of the confidential information, so that the verification information may be read at the same time as the confidential information is read.

For example, the verification information itself can also be encrypted by a preset encryption algorithm (such as a verification encryption algorithm). For example, the verification encryption algorithm can be an asymmetric encryption algorithm such as RSA2048, which is encrypted by a private key, and the verification information is decrypted by a public key when reading confidential information.

For another example, once confidential information (ciphertext, plaintext) is generated, it can be verified based on the verification information, so the numbering and description order of the above steps does not necessarily represent their execution order.

For example, when the verification fails (such as the checksum value is different), there may be multiple Different processing methods can be used, such as automatically terminating the processing of confidential information or issuing an alarm.

Illustratively, a method for information processing of a chip component according to an embodiment of the present disclosure may specifically include steps A101 to A109 , some of which are shown in FIG. 6 .

In step A101, when the chip is designed and produced, the information encryption algorithm, information key, and verification encryption algorithm are solidified in it, and a hardware encryption interface and decryption interface controlled by software are set in the chip.

The information encryption algorithm may be a symmetric encryption algorithm (AES_CBC256), and the information key used by the algorithm is a random number of a fixed size (eg, 256 bits) generated by hardware when the chip is produced.

The verification encryption algorithm is used to encrypt the verification information, which may be an asymmetric encryption algorithm (such as RSA2048), and its key is a randomly generated key pair, in which the private key is used for encryption and the public key is used for decryption.

The encryption interface (register interface) can be the plaintext address, plaintext size, and DDR address where the ciphertext is stored in the memory DDR (double data rate synchronous dynamic random access memory), and another built-in eFUSE is used to calibrate whether the encryption is completed.

In step A102, during the production (or development and debugging) of the security version, the hardware encryption interface is called, and the plain text of the confidential information written into the eFUSE in the related technology is encrypted using the information encryption algorithm to convert the ciphertext of the security information.

For example, the ciphertext may be obtained by encrypting the plaintext using a symmetric encryption algorithm (such as AES_CBC256).

In step A103, the ciphertext of the security information is stored in a specific storage area of the off-chip FLASH (information storage), verification information about the plaintext and ciphertext is generated, and the verification information is written as a header certificate in the header of the ciphertext of the security information.

For example, HASH256 operation can be performed on the ciphertext and plaintext of the confidential information respectively to obtain a 256-bit HASH value (check value) respectively, and the two HASH values are encrypted through an asymmetric encryption algorithm (such as the private key of RSA2048) to generate a 2048-bit signature, and the 1KB header certificate and the ciphertext image of the confidential information are used as encrypted images and returned to the specific DDR space through configuration.

In step A104, the address, size, and whether the security information ciphertext is readable by software in the FLASH are used as configuration information, and the configuration information is written into the eFUSE, and the eFUSE is solidified to become Read-only, permanently close the hardware encryption interface, the encryption function becomes invalid, the hardware ensures that the relevant registers become read-only, and finally erase the plaintext and ciphertext stored in DDR.

In step A105, when the chip boots into rom, it attempts to read the fixation mark of eFUSE. If it has been fixed (configuration information has been written), the following steps are executed. If it has not been fixed, it boots into rom in a conventional manner.

In step A106, configuration information is obtained, information of corresponding size is read from the corresponding FLASH address as ciphertext of security information, and the header certificate etc. is read at the same time.

In step A107, the header certificate is used to perform signature verification and decryption to obtain the corresponding plaintext. If the signature verification and decryption fails, an error is reported and the process stops. If successful, the corresponding plaintext is obtained and the subsequent steps are continued.

Through the decryption interface, a symmetric encryption algorithm (such as AES_CBC256) can be used to decrypt with a fixed information key to obtain plaintext; and an asymmetric encryption algorithm can be used to decrypt the header certificate (such as the public key of RSA2048) to obtain two 256-bit HASH values corresponding to the ciphertext and plaintext stored therein; then the ciphertext stored in the FLASH and the decrypted plaintext are respectively subjected to HASH256 operations to calculate two 256-bit HASH values corresponding to the ciphertext and plaintext respectively; finally, the stored HASH value is compared with the calculated HASH value to see if they are the same. If they are the same, the signature verification and decryption are successful, and the decrypted plaintext is used as the correct plaintext. If they are different, the signature verification and decryption fail (if the HASH values of the ciphertext are different, it means that the ciphertext has been tampered with; if the HASH values of the plaintext are different, it means that the decryption failed or the plaintext has been tampered with)

In step A108, the plain text is written to a specific address of the RAM, and whether it is readable by the software is set according to the configuration, thereby ensuring that the subsequent code can only read the contents of the above specific address of the RAM, or cannot read it (that is, only hardware access is allowed).

In step A109, after the chip is started, the security information can be read from the corresponding area of the RAM and used when needed.

Referring to FIG. 1 again, an embodiment of the present disclosure provides a chip component, including a chip, an information storage device, and an eFUSE, wherein the chip can implement an information processing method of any chip component of the embodiment of the present disclosure.

The chip component of the disclosed embodiment can execute the above chip component information processing method (including both the above method of writing confidential information and the above method of reading confidential information), thereby meeting various needs of customers and ensuring the security of confidential information at a low eFUSE cost.

In some embodiments, the information storage includes FLASH.

7 , an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, a chip can implement a method for information processing of any chip component of the embodiment of the present disclosure.

A processor is a device with data processing capabilities, including but not limited to a central processing unit (CPU); a memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); an I/O interface (read-write interface) is connected between the processor and the memory, and can realize information exchange between the memory and the processor, including but not limited to a data bus (Bus), etc.

Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules/units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

In hardware implementations, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; CD-ROM, DVD or other optical disk storage; cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and/or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

A method for information processing of a chip component, the chip component comprising a chip, an information storage device, and a one-time programmable memory eFUSE, the method comprising:

Encrypting the plain text of the confidential information according to the information encryption algorithm to obtain the cipher text of the confidential information;

Writing the ciphertext of the confidential information into the information storage device, and writing the configuration information into the eFUSE,

The configuration information represents the storage status of the ciphertext of the confidential information in the information storage device.
The method according to claim 1, wherein the chip includes an encryption interface, an information key is fixed in the chip, and

Wherein, encrypting the plaintext of the confidential information according to the information encryption algorithm to obtain the ciphertext of the confidential information includes:

Through the encryption interface, the chip uses the information key according to the information encryption algorithm to encrypt the plain text of the confidential information to obtain the ciphertext of the confidential information;

Close the encryption interface.
The method according to claim 1, further comprising:

Generate verification information according to the ciphertext of the confidential information and/or the plaintext of the confidential information;

The verification information is written into the information storage.
The method according to claim 1, wherein the configuration information includes at least one of the following:

The address of the ciphertext of the confidential information in the information storage device, the size of the ciphertext of the confidential information, and the configuration of whether the confidential information is readable by software.
A method for information processing of a chip component, wherein the chip component comprises a chip, an information storage device, and an eFUSE, wherein the information storage device stores a secret key of confidential information. The ciphertext of the confidential information is obtained by encrypting the plaintext of the confidential information according to an information encryption algorithm, the eFUSE stores configuration information, and the configuration information represents the storage status of the ciphertext of the confidential information in the information storage device, and the method includes:

Reading the configuration information stored in the eFUSE;

reading the ciphertext of the confidential information from the information storage according to the configuration information;

The ciphertext of the confidential information is decrypted according to the information encryption algorithm to obtain the plaintext of the confidential information.
The method according to claim 5, wherein the chip includes a decryption interface, the chip has an information key fixed therein, and

Wherein, decrypting the ciphertext of the confidential information according to the information encryption algorithm to obtain the plaintext of the confidential information includes:

Through the decryption interface, the chip uses the information key to decrypt the ciphertext of the confidential information according to the information encryption algorithm to obtain the plaintext of the confidential information.
The method according to claim 5, wherein the information storage device further stores verification information, the verification information is generated based on the ciphertext of the confidential information and/or the plaintext of the confidential information, and

Wherein, the method further comprises:

Reading the verification information stored in the information storage device;

The ciphertext of the confidential information and/or the plaintext of the confidential information are verified according to the verification information.
The method according to claim 5, wherein the configuration information includes at least one of the following:

The address of the ciphertext of the confidential information in the information storage device, the size of the ciphertext of the confidential information, and the configuration of whether the confidential information is readable by software.
The method according to claim 5, wherein the reading the configuration information stored in the eFUSE comprises:

In response to the chip remotely starting the bootrom, the configuration information stored in the eFUSE is read.
The method according to claim 5, wherein, after decrypting the ciphertext of the confidential information according to the information encryption algorithm to obtain the plaintext of the confidential information, it also includes:

The plain text of the confidential information is written into a random access memory RAM.
A chip component includes a chip, an information storage device, and an eFUSE, wherein:

The chip can implement the information processing method of the chip component described in any one of claims 1 to 4, and/or the information processing method of the chip component described in any one of claims 5 to 9.
The chip assembly according to claim 11, wherein:

The information storage device comprises a flash memory FLASH.
A non-transitory computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, can implement the information processing method of the chip component described in any one of claims 1 to 4, and/or the information processing method of the chip component described in any one of claims 5 to 9.