JP5591964B2 - Authentication method, device to be authenticated, and authentication device - Google Patents

Description

  The present invention relates to an authentication apparatus, an apparatus to be authenticated, and an authentication method thereof.

  In general, in a field requiring information security, a method using secret information and an encryptor shared with each other is adopted as a means for proving its validity.

  For example, in an IC card (SmartCard) used for electronic payment, an ID in the card and secret information for individualizing the IC card are held, and the IC card is based on the ID and secret information. It has a cryptographic processing function for performing authentication. In another example, an authentication method is defined in Content Protection for Recordable Media (CPRM) as means for proving the validity of an SD (registered trademark) card in protecting the copyright of content.

  When building a security system such as authentication, it is also necessary to assume that the device that performs the authentication process is attacked and secret information is extracted, and the extracted confidential information is invalidated. The method of revoking is also important. In Advanced Access Content System (AACS), which is a protection technology defined for protecting content recorded on the aforementioned CPRM and Blu-ray Disc, Media Key Block is used to invalidate device keys that are confidential information. (MKB) is used, and a method employing a public key cryptosystem-based protocol uses a public key certificate list (Revocation List) paired with leaked private key information.

  Taking as an example a system that plays video data recorded on an SD (registered trademark) card with video playback software installed on a PC, the CPRM processing in the SD (registered trademark) card is implemented in hardware. It is very difficult to illegally extract information that is concealed in secret information, but it is often easier for an attack to extract confidential information from reproduction software. In reality, there are many softwares that illegally decrypt protected DVD and Blu-ray video content, and the unauthorized software uses confidential information extracted from legitimate software players.

  In addition, it may be necessary to take measures for preventing counterfeit software or counterfeit SD cards, such as using a secret information extracted from software to impersonate an SD (registered trademark) card and tricking a legitimate software player. For example, by making it possible to easily read the encryption key used for content encryption from a counterfeit SD (registered trademark) card, it is possible to convert it to a counterfeit SD (registered trademark) card using a regular video recording device. The recorded video content can be easily decoded later.

  Here, the authentication device is provided not only as a dedicated hardware device such as a consumer device but also as a program (software) that can be executed by a PC (personal computer), for example, and the software becomes a substantial authentication device. In some cases. On the other hand, the device to be authenticated is, for example, a recording medium or the like, and even if a program called firmware is interposed in the operation of the hardware constituting the recording medium, important processing and information are stored in the hardware in the cell array. It is stored in a concealed state. Therefore, in reality, for example, when the software executed on the PC is an authentication device, there is a concern that the tamper resistance (resistance to attack) may be lower than the authentication target device such as a recording medium. The

  For this reason, there is a concern that by attacking an authentication device with low tamper resistance, secret information that is concealed by an authentication target device with high tamper resistance will be exposed and impersonated as a high tamper resistance device. . In this way, prevention of unauthorized use of secret information tends to be required.

  In recent years, the above requirements have been strengthened even in an environment where restrictions on circuit scale are imposed simultaneously, such as hardware implementation of public key encryption processing and MKB processing requiring a relatively large circuit scale. There is also a trend.

Content Protection for Recordable Media (CPRM), http://www.4centity.com/ Media Identifier Management Technology (MIMT), http://www.4ecntity.com/

  Provided are a memory device, a storage medium, a host device, and a system that are advantageous for preventing unauthorized use of confidential information.

An authentication method according to an embodiment is an authentication method in which an authentication device authenticates a device to be authenticated, and the device to be authenticated holds confidential first key information and identification information of the device to be authenticated , and the authentication device Holds the second key information concealed with the original information, the authenticated device generates third key information based on the original information and the first key information, and the authenticated device Generating a first session key based on the third key information and the random number information; and generating a second session key based on the second key information and the random number information that are concealed by the authentication device. A step of generating unidirectional conversion identification information by converting the identification information with a unidirectional function using the first session key, and the authentication device comprising: Recognition using unidirectional conversion identification information And a step of.

1 is a block diagram showing a configuration example of a memory system according to a first embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 1st Embodiment. The figure which shows the structural example of the encryption LotID bundle | flux (SELID) which concerns on 1st Embodiment. The block diagram which shows the structural example of the memory system which concerns on 2nd Embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 2nd Embodiment. The figure which shows the structural example of the encryption LotID bundle | flux (SELID) which concerns on 2nd Embodiment. The block diagram which shows the structural example of the memory system which concerns on 3rd Embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 3rd Embodiment. FIG. 10 is a block diagram illustrating a configuration example of a memory system according to a fourth embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 4th Embodiment. FIG. 10 is a block diagram illustrating a configuration example of a memory system according to a fifth embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 5th Embodiment. FIG. 14 is a block diagram illustrating a configuration example of a memory system according to a sixth embodiment. FIG. 10 is a flowchart showing an authentication flow of a memory system according to a sixth embodiment. FIG. 10 is a block diagram illustrating a configuration example of a memory system according to a seventh embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 7th Embodiment. The figure which shows the structural example of the encryption LotID bundle | flux (SELID) which concerns on 7th Embodiment. FIG. 20 is a block diagram illustrating a configuration example of a memory system according to an eighth embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 8th Embodiment. The figure which shows the structural example of the encryption ChipID bundle | flux (SECID) which concerns on 8th Embodiment. FIG. 20 is a block diagram illustrating a configuration example of a memory system according to a ninth embodiment. FIG. 10 is a flowchart showing an authentication flow of a memory system according to a ninth embodiment. The figure which shows the structural example of the encryption ChipID bundle | flux (SECID) which concerns on 9th Embodiment. FIG. 20 is a block diagram illustrating a configuration example of a memory system according to a tenth embodiment. The flowchart which shows the authentication flow of the memory system which concerns on 10th Embodiment. A block diagram showing an example of composition of a memory system concerning an 11th embodiment. FIG. 20 is a flowchart showing an authentication flow of the memory system according to the eleventh embodiment. A block diagram showing an example of composition of a memory system concerning a 12th embodiment. The figure which shows the to-be-authenticated apparatus before the SECID writing which concerns on 12th Embodiment. The block diagram which shows the system which downloads SECID which concerns on 12th Embodiment. The flowchart which shows the flow which downloads SECID which concerns on 12th Embodiment. A block diagram showing a memory system concerning a 13th embodiment. FIG. 18 is a block diagram showing a NAND flash memory according to a fourteenth embodiment. The equivalent circuit schematic which shows the block (BLOCK) based on 14th Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In this description, a memory system is given as an example of the authentication device, the device to be authenticated, and the authentication method thereof, but the present invention is not limited to this. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
An authentication device, a device to be authenticated, and an authentication method thereof according to the first embodiment will be described.

<1. Configuration example (memory system)>
First, a configuration example of the memory system according to the first embodiment will be described with reference to FIG.

  As shown in the figure, the memory system according to the first embodiment includes a NAND flash memory 10 that is a device to be authenticated, a host device 20 that is an authentication device, and a controller 19 that mediates both. The host device 20 accesses the NAND flash memory 10 by the controller 19.

  Here, a manufacturing process of a semiconductor product such as the NAND flash memory 10 will be briefly described. The manufacturing process of a semiconductor product is mainly divided into a pre-process for forming a circuit on a base wafer and a post-process for cutting a wafer in the previous period into individual pieces and enclosing wiring or a resin package. Here, when the controller 19 is configured to be included in the NAND flash memory 10 in the previous process, the controller 19 is not included in the previous process but is configured to be included in the same package in the subsequent process. There are various cases such as taking a chip form different from the type flash memory 10. In the following, including FIG. 1, the controller 19 takes an example of a chip form different from that of the NAND flash memory 10. Hereinafter, unless otherwise specified, the controller 19 often mediates in the exchange of data and instructions between the host device 20 and the NAND flash memory 10. Even in this case, the controller 19 does not change the essential contents of the above-described data and instructions, and therefore details may be omitted. A detailed description of configuration examples of the NAND flash memory 10 and the controller 19 will be given later.

  In addition, when the host device 20 is configured with dedicated hardware such as a consumer device, the function of the device operates on a PC as well as a combination of dedicated hardware and firmware that operates the host device 20. It may be configured by a software program.

  In the following, each component and data processing shown in FIG. 1 will be described below. In this example, the identification information such as ChipID and LotID recorded in the NAND flash memory 10 that is the device to be authenticated is read in a concealed state from a third party, and the data read from the device to be authenticated 10 is read. A method for reliably confirming the existence and a configuration example when the method is applied to the NAND flash memory 10 are shown.

1-1. NAND flash memory
Next, the NAND flash memory 10 that is the device to be authenticated will be described.
A NAND flash memory 10 according to this example includes a cell array 11, a data cache 12 arranged in a peripheral region of the cell array 11, data generation circuits (Generate) 13, 16, a data combination circuit (Concatenate) 14, a random number generator ( RNG) 15, an exclusive OR circuit (EXOR) 17, an encryptor (Encrypt) 18, and the like.

  In the cell array 11, a plurality of memory cells are arranged in a matrix at intersections of bit lines and word lines (not shown). The memory cell includes a tunnel insulating film, a floating gate, an interlayer insulating film, and a control gate connected to a word line in order on the semiconductor substrate. The current paths of the memory cells in the bit line direction are connected in series to form a cell unit. The cell unit is selected by a selection transistor connected to the bit line and the source line. The plurality of memory cells in the word line direction form one page (Page) which is a unit of data reading and data writing. A plurality of pages form a block which is a unit for erasing data. Details will be described later.

  The cell array 11 includes a general area (User area) 11-1, a secret area (Hidden area) 11-2, a ROM area (ROM area) 11-3, and the like.

  The general area (User area) 11-1 is an area where both data recording and data reading are freely possible. In the general area 11-1, SELID (Set of Encrypted LotID) which is a bundle of encrypted LotIDs is recorded. In addition, content data such as photographs, videos, music, or electronic books are recorded in the general area 11-1. A configuration example of the SELID in this example will be described later with reference to FIG.

  The hidden area 11-2 is an area where not only data recording but also data reading is prohibited outside the NAND flash memory 10 (Read / Program inhibit). In the secret area 11-2 according to this example, NKey (first key information) that is secret information used by the NAND flash memory 10 in the authentication is recorded. As will be described later, second key information (HKey) is generated from the first key information (NKey). On the other hand, the first key information (NKey) is not generated from the second key information (HKey).

  The ROM area 11-3 is an area where data recording from outside is prohibited and data reading is permitted. In the ROM area 11-3 according to this example, a chip ID (ChipID) and a lot ID (LotID), which are identification information, are recorded. When these ChipID and LotID are recorded, it is generally recorded in an error correction encoded state so that correct identification information can be read even if an error occurs in the data. The correction encoding / decoding process is not particularly illustrated. Here, the chip ID (ChipID) refers to a unique ID assigned to each chip of the NAND flash memory 10. The lot ID (LotID) is an ID that is given differently to some extent in the manufacturing process of the NAND flash memory 10. For example, the LotID may be changed for each predetermined quantity such as 1 million pieces, or may be changed for each production period such as one month or half a year. Further, when these Chip IDs and Lot IDs are always kept secret from the outside, they may be recorded in the secret area instead of the ROM area.

  Note that the ROM area 11-3, the secret area 11-2, and the general area 11-2 in the above may be realized by different physical configurations, or the physical configuration is the same, but the NAND flash memory. It may be realized by the logical control within 10. Here, logical control refers to a case where an identifier for controlling access from outside the NAND flash memory 10 is provided for each area, the identifier is held, and the NAND flash memory 10 accepts access to the area from the outside. In addition, there is a method of performing access control using the same identifier.

  Further, each memory cell constituting the cell array 11 may be a cell that stores a plurality of bits (MLC: Multi Level Cell), or a cell that records 1 bit (SLC: Single Level Cell). It may be. Further, the ROM area 11-3 and the secret area 11-2 may be configured to be used in SLC, and the general area 11-1 may be configured to be used in MLC. At this time, the physical configuration of the cell array may be different between the SLC region and the MLC region, or only a part of the bits of the memory cell that can be used as the MLC are used as a pseudo SLC region. Also good.

  A data cache 12 temporarily stores data read from the cell array 11.

The data generation circuits (Generate) 13 and 16 are circuits that generate output data from a plurality of input data by a predetermined calculation. The data generation circuit 13 generates HKey _j (second key information) by converting the information (HC _j ) received from the host device 20 using the first secret information NKey. Thus, on the NAND flash memory 10 side, the second key information (HKey _j ) can be generated from the first key information (NKey).

The data generation circuit 16 converts the data obtained by combining the random number RN _h received from the host device 20 and the random number RN _c generated by the NAND flash memory 10 itself using the HKey _j, thereby obtaining the session key SKey _j . Generate. For example, the data generation circuits 13 and 16 can use an AES (Advanced Encryption Standard) encryptor.

  The data generation circuits (Generate) 13 and 16 are circuits for outputting new data from a plurality of input information. In order to reduce the overall circuit scale, it is also possible to configure with the same circuit as the encryptor 18 or a circuit using the encryptor 18. Similarly, two data generation circuits 13 and 16 shown as different components for easy understanding of the data processing procedure can repeatedly use the same circuit.

The data combination circuit (Concatenate) 14 combines two input data (random number RN _h and random number RN _c ) and outputs the combined data to the data generation circuit 16.

Random number generator (RNG: Random Number Generator) 15 generates a random number RN _c used for authentication.

  The exclusive OR circuit (EXOR) 17 inputs two pieces of identification information (ChipID, LotID) read from the ROM area 11-3, calculates the exclusive OR of these two input data, and outputs the result. To do. When the identification information is recorded in the secret area instead of the ROM area as described above, the identification information that is input data of the exclusive OR circuit is read from the secret area.

The encryptor (Encrypt) 18 is a circuit that encrypts input data with separately input key data and outputs the encrypted input data. In the present embodiment, the result of the calculation by the exclusive OR circuit 17 of two pieces of identification information (ChipID, LotID) read from the ROM area 11-3 is used by using the key data SKey _j generated by the data generation circuit 16. Encryption is performed and encryption identification information Enc-ID = Enc (SKey _j , ChipID (+) LotID) is generated. As described above, the encryptor 18 can also be used as a data generation circuit in order to reduce the overall hardware circuit scale. Here, (+) represents exclusive OR.

  Although not shown here, for example, an output unit that outputs data sent to the host device 20 via the controller 19 is actually arranged as a component.

  It should be noted that the constituent elements such as the data cache 12 other than the cell array 11 can also be arranged in, for example, a memory controller 19.

1-2. Host device
Next, the host device (Host) 20 according to this example will be described.
The host device 20 includes a memory 23, a random number generation unit (RNG) 25, a data combination unit (Concatenate) 26, exclusive OR units (EXOR) 24 and 29, a data selection unit (Select) 21, and a data generation unit. (Generate) 27, decryption units (Decrypt) 22, 28, and the like.

The memory 23 stores the secret information HKey _j and the host constant HC _j necessary for executing the authentication process of the present embodiment. In particular, the secret information HKey _j needs to be stored using a means that does not expose it to the outside. Therefore, for example, in the case of a host device such as a consumer device configured using dedicated hardware, it is recorded in a dedicated memory that is completely shut off from the outside, or an encryption process prepared by the host device that is not shown. It is desirable to use a means such as encrypting the data and recording it in a memory. For example, in the case of program software running on a PC, the secret information HKey _j can be strictly protected by protecting the program itself using tamper-resistant software technology.

A random number generator (RNG: Random Number Generator) 25 generates an RN _h used for authentication.

The data combination unit (Concatenate) 26 combines the two input random number data (RN _h , RN _c ) generated from the random number generation units 15 and 25 and outputs the combined data.

  The exclusive OR units (EXOR) 24 and 29 calculate the exclusive OR of the two input data and output the result.

The data selection unit (Select) 21 receives encrypted LotID data that can be decrypted from the encrypted LotID bundle (SELID) read from the NAND flash memory 10 by using the secret information HKey _j that the host device 20 conceals. Selection is made using the index information _j of the secret information HKey _j . For example, the secret information HKey _j is recorded after being encrypted in an internal dedicated memory by a manufacturer's original method if it is a consumer device, or illegal by tamper resistant software (TRS) technology if it is a software program. If it is held in a state where it can be protected from analysis, or if a security module is incorporated, it is concealed after taking measures such as concealing using the function of the security module.

The data generation unit (Generate) 27 is a calculation unit that generates output data from a plurality of input data by a predetermined calculation, and performs the same calculation process as the data generation circuit 16 provided in the NAND flash memory. The data generation unit 27 of this example includes secret information HKey that the host device 20 conceals with data obtained by combining the random number RN _h generated by the host device 20 itself and the random number RN _c received from the NAND flash memory 10. _The session key SKey _j is generated by converting using _j . Note that the data generation unit 27 can also use an AES encryption operation or the like.

Decryption units (Decrypt) 22 and 28 decrypt input data with separately input key data, and output the decrypted input data. In this embodiment, the decoding unit 22, a result of the host apparatus is calculated by the exclusive OR unit index information j for identifying the confidential information HKey _j if necessary secret information HKey _j are concealed It is used to obtain the LotID by decrypting the encrypted LotID data selected by the data selection unit 21 as the key information.
The decryption unit 28 decrypts the encrypted identification information Enc-ID received from the NAND flash memory 10 using the SKey _j output from the data generation unit 27 and outputs the decrypted logical OR 29 to the exclusive OR 29. As a result of these decoding processes, the host device 20 can obtain data of two pieces of identification information, ChipID and LotID.

As described above, the host device 20 obtains LotID by the first-stage decryption unit 22. Furthermore, ChipID can also be obtained from the obtained LotID and the output data of the second-stage decoding unit 28 based on the calculation result of the exclusive OR 29. Further, by encrypting the encrypted identification information Enc-ID using the shared key data SKey _j , the identification information (ChipID, LotID) is correctly read from the NAND flash memory 10 authenticated by the host device 20. It is to confirm that it has been issued.

  In addition, an error correction processing unit (not shown) is also provided as a component as necessary.

<2. Authentication flow>
Next, an authentication flow of the memory system in the configuration shown in FIG. 1 will be described with reference to FIG.

  First, when authentication is started (Start), the host device 20 reads an encrypted LotID bundle (SELID: Set of Encrypted LotID) from the NAND flash memory 10 (Step S11).

Subsequently, the host device 20 performs a selection process from the read SELID by the selection unit 21 and reads encrypted LotID data that can be decrypted by the host device 20. Further, the decryption unit 22 performs the decryption process using the secret information HKey _j that is concealed to obtain LotID (Step S12).

Subsequently, the host device 20 generates a random number RN _h that is necessary when an authentication request is made. By using the random number RN _h for the authentication process, it becomes possible to use a different shared key with the NAND flash memory 10 each time in the following process (Step S13).

Subsequently, the host device 20 transmits the host constant (HC _j ) and the random number RN _h held in advance together with an authentication request (Request authentication) to the NAND flash memory 10 (Step S14).

  Subsequently, the NAND flash memory 10 receives the authentication request, loads the NKey to be concealed in the concealment area 11-2, and stores it in the data cache 12 (Step S15).

Then, NAND-type flash memory 10 generates a random number RN _c required for authentication by the random number generator 15, and sends to the host device (Step S16).

Here, in parallel with the processing in Step S16, the host device 20 uses the random number RN _h generated in Step S13 and the random number RN _c received in Step S15, and as a result of the data combining processing by the combining unit 26, the combined data RN _h || RN _c is generated. Further, by using the secret information HKey _j that has been concealed in advance and the combined data RN _h || RN _c , the data generation processing by the generation unit 27 causes SKey _j (= Generate (HKey _j , RN _h || RN _c ) ) Is generated (Step S17).

Subsequently, the NAND flash memory 10 generates HKey _j by the data generation processing circuit 13 using the loaded NKey and the host constant HC _j received in Step S14. Further, the data combination processing circuit 14 generates combined data RN _h || RN _c from the random number RN _h received in Step S14 and the random number RN _c generated in Step S15. Further, by using the HKey _j and the combined data RN _h || RN _c , key data SKey _j (= Generate (HKey _j , RN _h || RN _c )) is generated by the data generation process of the data generation circuit 16. (Step S18).

  Subsequently, the host device 20 sends an ID request (Request ID) to the NAND flash memory 10 (Step S19).

  Subsequently, the NAND flash memory 10 reads ChipID and LotID from the ROM area 11-3 (Step S21).

Subsequently, the NAND flash memory 10 calculates an exclusive OR (ChipID (+) LotID) of ChipID and LotID by the exclusive OR circuit 17. Further, the encryptor 18 encrypts these with the key data SKey _j generated in Step S18 to generate encrypted identification information Enc-ID (= Enc (SKey _j , ChipID (+) LotID)). The encrypted identification information Enc-ID is sent to the host device 20 (Step S22).

Subsequently, the host device 20 uses the decryption unit 28 to decrypt the received encrypted identification information Enc-ID using the key data SKey _j generated in Step S17, thereby obtaining ID = ChipID (+) LotID (Step S11). .

  Subsequently, the host device 20 obtains ChipID by obtaining the exclusive OR of the ID and the LotID obtained in Step S12 by the exclusive OR unit 29 (Step S24).

  With the above operation, the authentication flow according to the first embodiment is ended (End).

<3. About SELID>
Next, the SELID according to this example will be described with reference to FIG.
In order to generate a SELID suitable for a NAND flash memory in which LotID is recorded, a second key information bundle (HKey _j (j = 1,..., N) (Set of HKeys), which is secret information prepared in advance, is used. The LotID is encrypted one by one using the second key information HKey _j of each), that is, the SELID is encrypted LotID _j (E-LotID _j ) = Encrypt (HKey _j , LotID) A set of encrypted LotIDs is called an encrypted LotID bundle.

At the time of encryption, each second key information HKey _j uses the result of performing an exclusive OR operation with each index information j as an encryption key as necessary. The encryption LotID _{j at} that time is as follows: E-LotID _j = Encrypt (HKey _j (+) j, LotID).

Here, the above example is an example in which HKey _j (+) j is used as the encryption key. However, the present invention is not limited to this, and for example, a cyclic shift operation may be used. The cyclic shift operation is to move a bit and move a bit that exceeds a digit to the opposite side. Taking the left cyclic shift operation as an example, 11010101 is binary-shifted three times to the left, and 10101110 is obtained. The encryption key may be calculated using the following formula: E-LotID _j = Encrypt (CyclicLeftShift (HKey _j , j), LotID). Here, CyclicLeftShift (HKey _j , j) represents a cyclic shift of HKey _j to the left by j times. In this case, the exclusive OR unit 24 in FIG. 1 may be replaced with a left cyclic shift unit that performs a left cyclic shift operation. These matters are the same in other embodiments described later.

Note that the configuration of the SELID is not limited to this example. For example, when a specific HKey _j is exposed, the host apparatus 20 that holds the HKey _j uses the secret information HKey _j to prevent the LotID from being decrypted from the encrypted LotID bundle. When the NAND flash memory 10 in which the newly configured SELID is recorded by deleting the decryptable encrypted LotID from the SELID is used, the host device can obtain (decrypt) the correct LotID and ChipID. It is also possible not to do so. By doing in this way, it is also possible to provide a function of invalidating the host device 20 that holds the secret information HKey _j .

<4. Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the first embodiment, at least the following effects (1) to (2) can be obtained.

(1) Even if secret information is leaked from the host device 20, unauthorized use of the secret information of the NAND flash memory 10 using the leaked information can be prevented.
Here, the host device 20 which is an authentication device is provided not only as a dedicated hardware device such as a consumer device but also as a program (software) that can be executed by, for example, a PC (personal computer). It may be a host device. On the other hand, the NAND flash memory 10 that is the device to be authenticated is a recording medium, and even when a program called firmware is present, important processes and information are kept secret in the hardware in the cell array 11. Is memorized. Therefore, in reality, for example, there is a concern that software executed on a PC has a lower tamper resistance (resistance to attack) than a recording medium. Therefore, by attacking the host device (authentication device) 20 with low tamper resistance, secret information concealed in the NAND flash memory 10 (authenticated device) with high tamper resistance is also exposed, and tamper resistance is improved. There is concern about impersonating a high device.

  Therefore, in the configuration and the authentication method according to the first embodiment, as described above, the NAND flash memory 10 having relatively high tamper resistance has the first key information (NKey) to the second key information (HKey). The first key information (NKey) for generating is secretly stored in the cell array 11. On the other hand, the host device 20 whose tamper resistance is relatively low conceals only the second key information (HKey) that does not generate the first key information (NKey) from the second key information (HKey) in the memory 23. .

For this reason, the NAND flash memory 10 uses the original information (HC) received from the host device 20 and the first key information (NKey) concealed by itself, and the second key information (HKey) concealed by the authentication device. Is generated. The NAND flash memory 10 generates a session key (SKey) from the second key information (HKey) and the random number information (RN _h , RN _c ).

The host device 20 generates a session key (SKey ′) from the second key information (HKey) to be concealed and random number information (RN _h , RN _c ). As a result, both the NAND flash memory 10 and the host device 20 share a session key having the same value.

  Thus, in this example, the secret level of information concealed by the NAND flash memory (authenticated device) 10 and the secret level of information concealed by the host device (authentication device) 20 can be asymmetric. For example, in this example, the secret level of information concealed by the NAND flash memory 10 having relatively high tamper resistance is set higher than the secret level of information concealed by the host apparatus 20 having relatively low tamper resistance. can do.

  Therefore, even if information concealed by the host device 20 is leaked, since the secret level of the information concealed by the NAND flash memory 10 having relatively high tamper resistance is higher, the NAND using the leaked information is performed. The type flash memory 10 cannot be “spoofed”. Therefore, it is advantageous in that unauthorized use of the secret information of the NAND flash memory 10 using the leaked information can be prevented. As a result, for example, it is possible to reliably confirm that the ID information read from the authentication device is the information read from the target device to be authenticated, and invalidate illegal use of the other party.

(2) It is advantageous in mounting.
In the configuration as in this example, there is an environment in which restrictions on circuit scale are imposed simultaneously, such as hardware implementation of public key encryption processing and MKB processing requiring a relatively large circuit scale.

  However, according to this example, it is not necessary to use public key encryption processing that requires a relatively large circuit scale although the key information is asymmetric. Furthermore, as described above, by making the secret level of the information concealed between the host device (authentication device) 20 and the NAND flash memory (authenticated device) 10 asymmetrical, only information leaked from one device is already present. Authentication means that cannot be impersonated by one device is performed, and a session key (SKey) that is secret information is shared between the authentication device and the device to be authenticated.

  Therefore, it can be said that it is advantageous in mounting even in a severe environment where the above restrictions are imposed.

  Furthermore, as described above, the circuit scale can be made relatively small by making the data generation circuit and the encryptor constituting the memory system the same processing.

[Second Embodiment (an example including a plurality of NKeys)]
Next, an authentication device, a device to be authenticated, and an authentication method thereof according to the second embodiment will be described. This embodiment relates to an example including a plurality of NKeys (first key information). In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
First, a configuration example according to the second embodiment will be described with reference to FIG.
As shown in the figure, in the configuration example according to the second embodiment, a plurality of secret information NKey is stored in a secret area 11-2 in a cell array 11 of the NAND flash memory 10 in a secret area NKey _i (i = 1,..., M) It is different from the first embodiment in that it is concealed. Furthermore, a selection unit 31 that selects NKey _i from the secret information NKey _i (i = 1,..., M) that is concealed according to the index information i received from the host device (authentication device) is further provided.

Further, in the host device 20, the index information i indicating which secret information HKey _{i, j} corresponding to which secret information NKey _i in the NAND flash memory 10 is concealed is concealed.

  In the above configuration, the host device 20 uses the index information i for specifying the secret information together with the index information j by the selection unit 21 when executing the authentication process, and the host device 20 can decrypt the host device itself from the SELID. Select a LotID.

  In addition, the host device 20 transmits the index information i to the NAND flash memory 10.

NAND-type flash memory 10, the selector 31, the secret information NKey _i are concealed (i = 1, ..., m ) to select the NKey _i corresponding to the index information i received from.

<Authentication flow>
Next, an authentication flow according to the second embodiment will be described with reference to FIG.
As shown in the figure, in this example, the index information i necessary for selecting the secret information NKey _i concealed in the NAND flash memory is received from the host device 20 in the authentication request (Request authentication) in step S14. It is further transmitted to the NAND flash memory 10.

Furthermore, in step S18, the NAND flash memory 10 uses the index information i to generate the second key information HKey _{i, j} .

  The other authentication flows are substantially the same as those in the first embodiment, and a detailed description thereof will be omitted.

<About SELID>
Next, the SELID according to the second embodiment will be described with reference to FIG.
As shown in (a) and (c), in the second embodiment, the index information for designating NKey and HKey is two, i and j, so that it is a two-dimensional matrix. .

  The rest is substantially the same as in the first embodiment, and a detailed description thereof will be omitted.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method thereof according to the second embodiment, it is possible to obtain the same functions and effects as in the first embodiment of the above (1) and (2).

Furthermore, in the second embodiment, a plurality of NKey _i (i = 1,..., M) is concealed in a concealed area (Hidden area) 11-2 in the cell array 11 of the NAND flash memory 10.

  Therefore, the host device 20 corresponding to this also conceals the secret information HKey that is different for each application, so even if the HKey or NKey distributed for a specific application is exposed, it can be used for other purposes. Is more advantageous in that it has no adverse effects.

For example, when the secret information NKey No. ₁ is assigned for the video player and the secret information NKey is assigned for the electronic book, even if the secret information HKey _{1, j} / NKey ₁ assigned for the video player is exposed Even if the secret information HKey _{1, j} / NKey ₁ is used, an electronic book reader cannot be configured. Alternatively, when a different HKey / NKey is assigned for each host device manufacturer, even if the secret information is exposed from the host device of manufacturer A, the host device of manufacturer B cannot be configured. Accordingly, it is possible to newly manufacture and provide a NAND flash memory 10 in which only a specific manufacturer A for whom secret information has been exposed cannot correctly read LotID and ChipID.

[Third embodiment (an example in which a plurality of NKeys are provided for each lot)]
Next, an authentication device, a device to be authenticated, and an authentication method thereof according to the third embodiment will be described. This embodiment relates to an example in which a plurality of NKeys (first key information) are provided for each lot (each NAND manufacturer). In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
First, a configuration example according to the third embodiment will be described with reference to FIG.
As shown in the figure, in the configuration example according to the third embodiment, the secret area (Hidden area) 11-2 of the NAND flash memory 10 is selected from a plurality of NKey _i (i = 1,..., M). One secret information NKey _i is recorded. Further, in the ROM area 11-3, the index information i for specifying the secret information NKey _i is a point to be recorded, which differs from the first embodiment.

Further, the host device 20 can execute authentication processing with the NAND flash memory 10 in which any NKey _i in the m pieces of secret information NKey _i (i = 1,..., M) is concealed. Confidential information HKey _i (i = 1, ..., m) is all kept secret.

In the above configuration, the host device 20 reads the index information i from the NAND flash memory 10 when executing the authentication process, and selects the corresponding HKey _i from the secret HKey _i (i = 1,..., M). To do. Similarly, an encrypted LotID that can be decrypted by the host device 20 is selected from the encrypted LotID bundle (SELID) read from the NAND flash memory 10.

<Authentication flow>
Next, an authentication flow according to the third embodiment will be described with reference to FIG.
In this example, the NAND flash memory 10 further loads the index information i for specifying the secret information NKey _i into the ROM area 11-3 in step S32.

In step S33, the host device 20 reads the encrypted LotID bundle (SELID) from the NAND flash memory 10 and uses the index information i for specifying the secret information NKey _i concealed in the NAND flash memory. Is read further.

Subsequently, in step S17, the host device 20 uses the corresponding HKey _i from the plurality of secret information HKey _i (i = 1,. From LotID.

Further, the host device 20, the secret information set by using the index information i received in the processing _{HKey i, j (i = 1} , ..., m) key from the data SKey _i, HKey _i required to generate the _{j , J.}

  In the illustrated processing flow, reading is performed in the order of the index i and SELID, but the reading order is not particularly limited.

<About SELID>
Also in this embodiment, there are two index information i and j for specifying the HKey. Therefore, the SELID is the same as that of the second embodiment shown in FIG.

  The rest is substantially the same as in the first embodiment, and a detailed description thereof will be omitted.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the third embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

Furthermore, in the third embodiment, a plurality of NKeys (first key information) are stored for each lot (each NAND manufacturer) in the secret area 11-2 of the NAND flash memory 10. Further, in the ROM area 11-3 records the index information i for specifying the secret information NKey _i.

  In this way, by changing the NKey to be concealed for each NAND flash memory maker, information management of a specific NAND flash memory maker was insufficient, so the NKey, which is particularly important secret information, leaked NAND flash memory manufactured by other NAND flash memory manufacturers can be used even if the secret information NKey is leaked due to insufficient information concealment methods in the NAND flash memory sold. This is advantageous in that it can be used without change.

[Fourth embodiment (an example of recording a SELID in a protected area)]
Next, an authentication device, a device to be authenticated, and an authentication method thereof according to the fourth embodiment will be described. This embodiment relates to an example of recording a SELID in a protected area. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
First, a configuration example according to the fourth embodiment will be described with reference to FIG.
As shown in the figure, in the fourth embodiment, the encrypted LotID bundle (SELID) is recorded in the protected area 11-4 of the cell array 11 of the NAND flash memory 10. It is different from the embodiment. The protected area 11-4 is an area in which data writing / reading processing is permitted only when authentication processing separately implemented in the controller 19 is successful for external access.

  Such a protection area 11-4 is an area that is currently distributed, for example, an SD (registered trademark) card or the like, and the data recorded in the protection area 11-4 is exchanged with the controller 19. In addition to being kept secret from those other than the authorized host device 20 that can execute the authentication process, it is possible to prevent the user from rewriting / deleting data by mistake. Therefore, it is also an area for storing information indispensable for data reproduction processing.

  Therefore, the SELID according to the present example is transmitted to the host device 20 after establishing the secure channel 33 in which the authentication process separately prepared with the controller 19 is executed.

<Authentication flow>
Next, an authentication flow according to the fourth embodiment will be described with reference to FIG.

  As shown in the figure, the host device 20 establishes a secure channel by executing an authentication process separately prepared with the controller 19 in step S35.

  Therefore, in step S35, the host device 20 obtains access permission to the protected area 11-4 and reads the encrypted LotID bundle (SELID) through the established secure channel.

  The SELID according to the fourth embodiment is the same as that shown in FIG.

  Other configurations and the like are the same as those in the first embodiment, and thus detailed description thereof is omitted.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the fourth embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Furthermore, in the fourth embodiment, an encrypted LotID bundle (SELID) is recorded in a protected area 11-4 of the cell array 11. For this reason, it is possible to prevent troubles such as the inability to read ChipID and LotID, which are caused when the user mistakenly rewrites / deletes SELID.

[Fifth Embodiment (an example in which a NAND does not include a random number generator)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method thereof according to the fifth embodiment will be described. This embodiment relates to an example in which the NAND flash memory 10 is not provided with the random number generator 15. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the fifth embodiment will be described with reference to FIG.

  As shown in the figure, in the configuration example according to the fifth embodiment, the NAND flash memory 10 does not include the random number generator (RNG) 15.

Instead, fixed value index information (i-NAND) prepared for each NAND flash memory 10 is held in the ROM area 11-3 in the cell array. This i-NAND is a value used when generating the key data SKey _j instead of the random number RN _c in the first embodiment, and is a random value, ChipID or LotID generated in advance when the NAND flash memory is manufactured. The values generated by various generation means such as the hash value, the value obtained by encrypting ChipID or LotID with a specific value can be used.

  Therefore, the NAND flash memory 10 further includes a data cache 12B.

<Authentication flow>
Next, an authentication flow according to the fifth embodiment will be described with reference to FIG.
As shown in the figure, when the NAND flash memory 10 receives an authentication request (Request authentication) from the host device 20 in step S16, the NAND flash memory 10 is fixed from the ROM area 11-3 instead of generating a random number by a random number generator. The value index information (i-NAND) is read and sent to the host device 20.

The host device 20 and the NAND flash memory 10 use the random number RN _h generated by the host device and the combined data RN _h || i-NAND and HKey _j generated by the host device when generating the key data SKey _j. Perform the above data generation process (SKey _j = Generate (HKey _j , RN _h || i-NAND)).

  The SELID according to the fifth embodiment is the same as that shown in FIG.

  The rest is substantially the same as in the first embodiment, and a detailed description thereof will be omitted.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the fifth embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Furthermore, in the fifth embodiment, the NAND flash memory 10 does not include the random number generator (RNG) 15 shown in FIG. For this reason, the mounting circuit scale of the NAND flash memory 10 can be further reduced, which is more advantageous for miniaturization.

[Sixth embodiment (an example of generating a token)]
Next, an authentication device, a device to be authenticated, and an authentication method according to the sixth embodiment will be described. This embodiment relates to an example of generating verification data (Token). In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the sixth embodiment will be described with reference to FIG.

As shown in the figure, in the configuration example according to the sixth embodiment, both the NAND flash memory 10 side and the host device 20 side use data generation circuits (Generate) 16 and 26, and secret information HKey _j and 2 The key data SKey _j is generated from the combined data RN _h || RN _{c of the} two random numbers, and the verification data (Token to confirm that the same key data SKey _j can be generated between the host device and the NAND flash memory. ) Is different from the above embodiment.

The verification data (Token) may be data calculated based on the session key SKey _j and values shared by the host device 20 and the NAND flash memory 10. In this embodiment, Token (= Generate (SKey _j , RN _c || RN _h )) obtained by using a value RN _c || RN _{h in} which the order of combining two random numbers is exchanged is used as an example. In the figure, Generate () is indicated as G () for the convenience of description space.

The data generation circuit used for generating the session key SKey _j and the data generation circuit used for generating the token are illustrated as the same circuit. However, since the purpose is to generate the same data in the host device 20 and the NAND flash memory 10, the two data generation circuits do not necessarily have to be the same data generation circuit, and may be configured with different circuits. Good.

  The generated verification data Token is sent from the NAND flash memory to the host device.

The host device 20 determines in the comparator 35 whether or not the received verification data Token matches the verification data calculated by the host device itself. When the verification data Token values are the same (Yes), the gate unit 36 outputs the session key SKey _j to the decryption unit (Decrypt) 28, and the subsequent processing is continued as in the first embodiment. On the other hand, if the verification data Token values are different (No), the subsequent processing is aborted (Abort).

<Authentication flow>
Next, an authentication flow according to the sixth embodiment will be described with reference to FIG.
In the sixth embodiment, the following processing is added after the key data SKey _j is generated in the first embodiment.

The host device 20 calculates verification data Token = Generate (SKey _j , RN _c || RN _h ) from the generated key data SKey _j and the two random numbers RN _h and RN _c in step S36.

Similarly, the NAND flash memory also calculates verification data Token = Generate (SKey _j , RN _c || RN _h ) from the generated key data SKey _j and the two random numbers RN _h and RN _{c at} the step S37. The token is sent to the host device.

  Subsequently, in step S39, the host device checks whether or not the received Token matches the Token generated by the host device itself. If they match, the subsequent authentication processing is continued. Cancels the subsequent authentication process.

  The SELID according to the sixth embodiment is the same as that shown in FIG.

  Since others are the same as those in the first embodiment, a detailed description thereof will be omitted.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the sixth embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

Furthermore, in the sixth embodiment, verification data (Token) for confirming that the same key data SKey _j can be generated between the host device and the NAND flash memory is generated, and this match is determined.

  Therefore, it is possible to confirm that the key sharing process by authentication is correctly performed between the two, and it is possible to easily confirm that the data is incorrect or falsified in the unauthorized authentication partner or the intermediate path of the authentication process. This is further advantageous.

[Seventh embodiment (an example of using another set of IDKey for SELID encryption)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method thereof according to the seventh embodiment will be described. This embodiment relates to an example of using another set of IDKeys for SELID encryption. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the seventh embodiment will be described with reference to FIG.

  As shown in the drawing, in the configuration example according to the seventh embodiment, the encryption key used for generating the encrypted LotID bundle (SELID) is changed to an encryption key IDKey different from the HKey derived from NKey. It is different from the embodiment. However, the components of the NAND flash memory 10 according to this example are not substantially changed.

The host apparatus 20 according to the present example is different in that the new secret information IDKey _k is concealed in the memory 23 and the IDKey _k is used for the decryption process of the SELID read from the NAND flash memory 10. However, there is no change in the decoding process itself.

<Authentication flow>
Next, an authentication flow according to the seventh embodiment will be described with reference to FIG.
As shown in the figure, the host device 20 uses the secret information IDKey _k and the index information k to decrypt the encrypted LotID bundle (SELID) read from the NAND flash memory 10 in step S12. It is different from the above embodiment.

  Further, since the key data used for the LotID encryption has been changed as described above, a configuration example of the SELID in this example is as shown in FIG.

  Others are substantially the same as those of the first embodiment, and thus detailed description thereof is omitted.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the seventh embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Furthermore, in the seventh embodiment, even if the secret information NKey concealed in the NAND flash memory is used, the SELID cannot be decrypted to obtain the LotID. Therefore, even if the secret information NKey is exposed from the NAND flash memory 10 or the secret information NKey is leaked from the manufacturer of the NAND flash memory 10, it is illegal to decrypt LotID and ChipID using SELID. It is further advantageous in that the host device can be eliminated.

[Eighth embodiment (an example in which ChipID transmission is a one-way function)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method according to an eighth embodiment will be described. This embodiment relates to an example in which computation at the time of ChipID transmission is a one-way function. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the eighth embodiment will be described with reference to FIG.
As shown in the figure, in the configuration example according to the eighth embodiment, not the LotID but the ChipID is encrypted in the general area (User area) 11-1 in the cell array 11 of the NAND flash memory 10. The configured encrypted ChipID bundle (SECID) is recorded, and only the ChipID is recorded in the ROM area 11-3, which is different from the above embodiment.

The NAND flash memory 10 and the host device 20 include unidirectional converters (Oneway) 38 and 39 for performing a unidirectional operation instead of encrypting the ID with the session key SKey _j .

The host device 20 includes a decoding unit 22 similar to that of the first embodiment for reading the SECID from the NAND flash memory 10 and obtaining the ChipID from the SECID using the HKey _j and the index information j.

The host device 20 verifies the value (Oneway (SKey _j , ChipID)) obtained by unidirectional conversion of the ChipID received from the NAND flash memory 10 and the unidirectional conversion value of the ChipID calculated by the host device 20 itself. The data verification part 40 which determines a result is provided.

<Authentication flow>
Next, an authentication flow according to the eighth embodiment will be described with reference to FIG.
As shown in the figure, first, when authentication is started (Start), the host device 20 reads an encrypted ChipID bundle (SECID: Set of Encrypted ChipID) from the NAND flash memory 10 (Step S11).

Subsequently, the host device 20 performs the above selection process from the read SECID, reads the encrypted ChipID data that can be decrypted by the host device, and decrypts it by the decryption process using the secret information HKey _j that is kept secret. Thus, ChipID is obtained (Step S12).

Subsequently, the host device 20 generates a random number RN _h that is necessary when an authentication request is made. By using a random number for the authentication process, a shared key different from the NAND flash memory is used every time in the following process (Step S13).

Subsequently, the host device 20 sends the host constant (HC _j ) and the random number RN _h held in advance together with an authentication request (Request authentication) to the NAND flash memory 10 (Step S14).

Subsequently, the NAND flash memory 10 generates a random number RN _c necessary for authentication and sends it to the host device (Step S15).

Subsequently, the NAND flash memory 10 generates HKey _j by the data generation process using the secret NKey and the HC _j received in Step S14, and the random number RN _h received in Step S14 and Step S15. The combined data RN _h || RN _c is generated from the generated random number RN _c by the data combining process, and the key data SKey _j (=) is generated by the data generating process using the HKey _j and the combined data RN _h || RN _c. Generate (HKey _j , RN _h || RN _c )) is generated (Step S16).
In parallel with the process of step S16, the host device 20 generates combined data RN _h || RN _c by the data combining process from the generated random number RN _h and the received random number RN _c, and secret information that has been concealed in advance. SKey _j (= Generate (HKey _j , RN _h || RN _c )) is generated by the data generation process using HKey _j and the combined data RN _h || RN _c (Step S17).

  Subsequently, the host device 20 sends an ID request (Request ID) to the NAND flash memory (Step S19).

  Subsequently, the NAND flash memory 10 reads ChipID from the ROM area (Step S21).

Subsequently, the NAND flash memory 10 performs one-way conversion using the key data SKey _j that generated ChipID, and generates one-way conversion data Oneway-ID (= Oneway (SKey _j , ChipID)). The generated unidirectional conversion data Oneway-ID is sent to the host device (Step S38).

Subsequently, the host device 20 performs one-way conversion using the key data SKey _j that generated ChipID, and obtains one-way conversion data Oneway-ID (Step S39).

Subsequently, the host device 20 confirms that the received one-way conversion data Oneway-ID matches the obtained one-way conversion data, and if they match, determines that the Chip ID is the correct Chip ID, If they do not match, it is determined that the ChipID is an invalid ID (Step S40).
With the above operation, the authentication flow according to the eighth embodiment is ended (End).

  Note that a configuration example of SECID which is an encrypted ChipID bundle is similarly shown in FIG.

  Others are substantially the same as those in the first embodiment.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the eighth embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Further, in the eighth embodiment, an encrypted ChipID bundle configured by encrypting ChipID instead of LotID in the general area (User area) 11-1 in the cell array 11 of the NAND flash memory 10 is used. (SECID) is recorded, and only the ChipID is recorded in the ROM area 11-3.

  Therefore, the amount of ID information that the NAND flash memory 10 must hold can be reduced.

[Ninth Embodiment (an example of a combination of the seventh and eighth embodiments)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method thereof according to the ninth embodiment will be described. This embodiment relates to an example of a combination of the seventh and eighth embodiments. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the ninth embodiment will be described with reference to FIG.

  As shown in the figure, the present embodiment includes both of the modifications of the seventh embodiment and the eighth embodiment added to the first embodiment. In other words, the introduction of IDKey and the change of SELID to SECID are the main differences from the first embodiment.

<Authentication flow>
FIG. 22 shows an authentication flow according to the ninth embodiment.

  As shown in the figure, the authentication flow is also an authentication flow that combines the authentication flow of the seventh embodiment and the authentication flow of the eighth embodiment.

  A configuration example of the SECID that is an encrypted ChipID bundle is similarly shown in FIG.

  Others are substantially the same as those in the first embodiment.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the ninth embodiment, the same operational effects (1) and (2) as those in the first embodiment can be obtained.

  Furthermore, in the ninth embodiment, it is possible to obtain both functions and effects added in the seventh embodiment and the eighth embodiment.

[Tenth embodiment (an example of a combination of the third, seventh, and eighth embodiments)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method according to the tenth embodiment will be described. This embodiment relates to an example of a combination of the third, seventh, and eighth embodiments. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the tenth embodiment will be described with reference to FIG.

  As shown in the figure, the present embodiment includes differences added to the third, seventh, and eighth embodiments. That is, the introduction of IDKey, the change from SELID to SECID, and the fact that the host device conceals a plurality of secret information HKey are the main differences from the first embodiment.

<Authentication flow>
Next, an authentication flow according to the tenth embodiment will be described with reference to FIG.

  As shown in the figure, the authentication flow is also different in that the following processing flow is added to the authentication flow of the ninth embodiment.

  First, the host device 20 makes an authentication request (Request authentication) in step S14.

Subsequently, in step S33, the host device 20 transmits the random number RN _h and the host constant HC _j, and then reads the NKey _i index information i concealed in the NAND flash memory from the ROM area of the NAND flash memory. . Further, after receiving the random number RN _c from the NAND flash memory, the host device uses the index information i received in the above processing to generate the key data SKey _i from the secret information set HKey _{i, j} (i = 1,..., M). _, HKey _{i, j} required to generate _j is selected.

However, the processing flow shown in FIG. 25 is an example, and reading of the index information i and HKey _{i, j} selection processing, etc. are performed in this processing flow if data necessary for each processing can be obtained in advance. It is not limited.

  A configuration example of the SECID that is an encrypted ChipID bundle is similarly shown in FIG.

  Others are substantially the same as those in the first embodiment.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the tenth embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Furthermore, according to the tenth embodiment, it is possible to obtain the effects of the third, seventh, and eighth embodiments.

[Eleventh embodiment (an example not including a random number generator)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method according to the eleventh embodiment will be described. This embodiment relates to an example in which the NAND flash memory 1 does not include the random number generator 15 in the tenth embodiment. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the eleventh embodiment will be described with reference to FIG.

  As shown in the figure, this embodiment is different from the tenth embodiment in that the random number generator (RNG) 15 provided in the NAND flash memory is not provided in the tenth embodiment.

In the tenth embodiment, two random numbers RN _h and RN _c the combined data and secret data HKey _{i, j} and the session key data SKey _i, had generated a _j, in this embodiment a random number RN _h Session key data SKey _{i, j} is generated from the secret data HKey _{i, j} .

Details of the configuration example according to the eleventh embodiment will be described below.
In the embodiment, the identification information ChipID recorded in the NAND flash memory as the device to be authenticated is read in a concealed manner from a third party, and the data read from the device to be authenticated is surely confirmed. A confirmation method and a configuration when the method is applied to a NAND flash memory are shown.

NAND flash memory
As described above, the NAND flash memory 10 is a device to be authenticated.

  As shown in the figure, a NAND flash memory 10 according to this example includes a cell array 11, data caches 12A and 12B arranged in the peripheral region of the cell array, data generation circuits (Generate) 13 and 16, and a random number generator (RNG). 15. A one-way converter (Oneway) 38 and the like are provided.

The cell array 11 includes a ROM area 11-3, a hidden area 11-2, a general area 11-1, and the like.
The ROM area 11-3 is an area where data recording from outside is prohibited and data reading is permitted. In the ROM area 11-3 according to the present example, Chip information as identification information and index information i (index of NKey) for indicating secret information NKey _i recorded in the hidden area are recorded. However, when the ChipID or index i is recorded, even if an error occurs in the data, it is generally recorded in an error correction encoded state so that correct identification information can be read out. Here, the error correction encoding / decoding process is not particularly illustrated.
The hidden area 11-2 is an area in which not only data recording but also data reading is prohibited outside the NAND flash memory 10 (Read / Program inhibit). In the secret area 11-2 according to this example, NKey _i that is secret information used by the NAND flash memory 10 in the authentication is recorded. Further, when the ChipID is always kept secret from the outside, it may be recorded in the secret area instead of the ROM area.
The general area (User area) 11-1 is an area where both data recording and data reading are freely possible. In the general area 11-1, an SECID (Set of Encrypted ChipID) that is an encrypted ChipID bundle is recorded, and in addition, content data such as a photo, video, music, or an electronic book is recorded. The configuration example of the SECID that is the encrypted ChipID is the same as that shown in FIG.

  Data caches 12A and 12B temporarily store data read from the cell array 11.

  The data generation circuits 13 and 16 are circuits that output new data from a plurality of pieces of input information. In order to reduce the overall circuit scale, the same or one-way converter as described above is used. It is also possible to configure with a circuit. Similarly, two data generation circuits illustrated as different components in order to make the data processing procedure easy to understand can repeatedly use the same circuit.

The data generation circuits (Generate) 13 and 16 are circuits that generate output data from a plurality of input data by a predetermined calculation. The information (HC _j ) received from the host device 20 is converted into the secret information NKey _i described above. HKey _{i, j} is generated by using the key _, and SKey _{i, j} is generated by converting the random number RN _h received from the host device using the previous HKey _j . AES (Advanced It is also possible to use an encryption standard.

The one-way converter (Oneway) 38 is a circuit that performs one-way conversion on input data and key data that is input separately, and outputs the input data that has been subjected to the one-way conversion. In this embodiment, the identification information ChipID read from the ROM area is converted by a one-way function using the key data SKey _{i, j} generated by the data generation circuit, and the one-way conversion identification information Oneway-ID (= Oneway (SKey _{i, j} , ChipID)). As in the first embodiment, when the identification information ChipID is recorded in the secret area instead of the ROM area, the identification information ChipID that is input data of the one-way converter is the secret area. Read from.

  As described above, the one-way converter 38 can be used as the data generation circuit in order to reduce the overall hardware circuit scale.

  Although not shown, an output unit for outputting data sent to the host device 20 via the controller 19 may actually be arranged as a component.

Host device
As shown in the figure, a host device (Host) 20 according to this example includes a random number generation unit (RNG) 25, an exclusive OR unit (EXOR) 24, data selection units (Select) 21-1, 21-2, and decryption. Unit (Decrypt) 22, data generation unit (Generate) 27, unidirectional conversion unit (Oneway) 39, data verification unit (Verify) 40, and the like. In addition, an error correction processing unit (not shown) or the like can be provided as a component as necessary.

A random number generator (RNG: Random Number Generator) 25 generates an RN _h used for authentication.

  The exclusive OR unit (EXOR) 24 calculates the exclusive OR of the two input data and outputs the result.

Two data selection units (Select) 21-1 and 21-2 are arranged. Data selecting unit of the first stage (Select1) 21-1 is, NAND-type flash memory read from 10 encrypted ChipID bundle (SECID) the host is concealed from the secret information IDKey _k decrypted cryptographic using The selected ChipID data is selected using the index information k of the secret information HKey _j .

The second-stage data selection unit (Select2) 21-2 uses the index information i of the secret information NKey _i read from the NAND flash memory 10, and the secret information set HKey _i kept secret by the host device 20 _{, J} (i = 1,..., M _{, where j} is a fixed value in the HKey _{i, j} ), the secret information HKey _{i, j} necessary for the authentication process with the NAND flash memory 10 is obtained. select.

The secret information IDKey _k , HKey _{i, j} is recorded in an internal dedicated memory after being encrypted by a manufacturer's original method for consumer devices, or tamper resistant software (TRS) technology for software programs. If the security module is stored in a state where it can be protected from unauthorized analysis, or if a security module is incorporated, it is concealed after taking measures such as concealing using the function of the security module.

The decryption unit (Decrypt) 22 decrypts the input data with the separately input key data, and outputs the decrypted input data. In this embodiment, the results of host device is calculated by the exclusive OR unit index information k for identifying the confidential information IDKey _k optionally the secret information IDKey _k being secret as the key information the It is used to obtain the ChipID by decrypting the encrypted ChipID data selected by the data selection unit 1.

The data generation unit (Generate) 27 is a calculation unit that generates output data by a predetermined calculation from a plurality of input data, and the host device 20 conceals the random number RN _h generated by the host device 20 itself. It is used to generate SKey _{i, j} by converting it using secret information HKey _{i, j,} and it is also possible to use an AES encryption operation or the like.

The one-way conversion unit (Oneway) 39 converts the ChipID output from the decoding unit by a one-way function using SKey _{i, j} output from the data generation unit, and generates one-way conversion identification information Oneway- Generate an ID.

  The data verification unit (Verify) 40 compares the one-way conversion identification information Oneway-ID received from the NAND flash memory 10 with the one-way conversion identification information obtained from the one-way conversion unit in the host device. If both values match, it is determined that the ChipID obtained by the decoding unit is a correct ChipID, and if they do not match, the ChipID is determined to be an invalid ID.

  In addition, similarly, an error correction processing unit (not shown) or the like can be provided as a component as necessary.

<2. Authentication flow>
Next, an authentication flow of the memory system according to the eleventh embodiment will be described with reference to FIG.

  As illustrated, when authentication is started (Start), the host device 20 reads an encrypted ChipID bundle (SECID: Set of Encrypted ChipID) from the NAND flash memory 10 (Step S11).

Subsequently, the host device 20 performs data selection processing by the data selection unit (Select1) 21-1 from the read SECID, reads encrypted ChipID data that can be decrypted by the host device 20, and conceals secret information. ChipID is _obtained by decoding by the decoding processing unit 22 using IDKey _k (Step S12).

Subsequently, the host device 20 generates a random number RN _h that is necessary when an authentication is requested (Step S13). By using a random number for the authentication process, a shared key different from the NAND flash memory is used every time in the following process.

Subsequently, the host device sends the host constant (HC _j ) and the random number RN _h held in advance together with an authentication request (Request authentication) to the NAND flash memory (Step S14).

Subsequently, in the NAND flash memory 10, the host device 20 selects HKey _{i, j} necessary for authentication with the NAND flash memory from the secret information set HKey _{i, j} (i = 1,..., M). NKey index information i necessary for the process is read out and sent to the host device 20 (Steps S15 and S33).

Subsequently, the NAND flash memory 10 generates HKey _{i, j} by data generation processing in the data generation circuit using the secret NKey _i and the received HC _j, and also uses the received random number RN _h. Key data SKey _{i, j} (= Generate (HKey _{i, j} , RN _h )) is generated by data generation processing in the data generation circuit (Step S18).

In parallel with the processing of Step S32, the host device 20 uses the received index information i to generate the NAND flash from the secret information set HKey _{i, j} (i = 1,..., M) that has been concealed in advance. Secret information HKey _{i, j} necessary for the authentication process with the memory 10 is selected (Step S33).

Subsequently, the host device 20 uses the selected secret information HKey _{i, j} and the generated random number RN _h to perform the session key SKey _{i, j} (= Generate (HKey _{i, j} , RN _h )) is generated (Step S17).

  Subsequently, the host device 20 sends an ID request (Request ID) to the NAND flash memory 10 (Step S19).

  Subsequently, the NAND flash memory 10 reads ChipID from the ROM area (Step S21).

Subsequently, the NAND flash memory 10 performs the unidirectional conversion process in the unidirectional converter 38 using the key data SKey _{i, j} generated with ChipID, and the unidirectional conversion data Oneway-ID (= Oneway (SKey _{i, j} , ChipID)) and the generated unidirectional conversion data Oneway-ID are sent to the host device (Step S38).

Subsequently, the host device 20 performs one-way conversion processing in the one-way conversion unit 39 using the key data SKey _{i, j} that generated ChipID, and obtains one-way conversion data Oneway-ID (Step S39).

  Subsequently, the host device 20 confirms that the received one-way conversion data Oneway-ID and the obtained one-way conversion data match, and if they match, determines that the Chip ID is the correct Chip ID, If they do not match, it is determined that the ChipID is an invalid ID (Step S40).

  With the above operation, the authentication flow according to the eleventh embodiment is ended (End).

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the eleventh embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Further, in the eleventh embodiment, it is not necessary to mount the random number generator 15 in the NAND flash memory 11. Therefore, it is advantageous in that the operational effects of the first embodiment and the operational effects added in the tenth embodiment can be realized in the same manner, and the mounting circuit scale of the NAND flash memory can be further reduced. is there.

[Twelfth embodiment (an example in which ID-index is written)]
Next, an authentication apparatus, an apparatus to be authenticated, and an authentication method thereof according to a twelfth embodiment will be described. This embodiment relates to an example in which index information ID-index necessary for specifying ChipID is written. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example (memory system)>
A configuration example according to the twelfth embodiment will be described with reference to FIG.

  As shown in FIG. 23, in this example, index information ID-index necessary for specifying ChipID is written in the ROM area 11-3 of the NAND flash memory 10, and ChipID is a hidden area. 11-2, and is different from the eleventh embodiment in that a data cache (Data Cache) 12B is provided for reading the ChipID as necessary.

  The configuration example of the SECID that is the encrypted ChipID is the same as that shown in FIG.

<Authentication flow>
The NAND flash memory 10 reads the ChipID from the secret area via the data cache as necessary, but the other processing flow is substantially the same as in the eleventh embodiment.

<SECID writing>
The writing of the encrypted ChipID bundle (SECID) will be described with reference to FIG.

  Here, when the encrypted ChipID bundle (SECID) is written at the time of manufacturing the NAND flash memory 10, the processing is not particularly necessary. However, when the NAND flash memory 10 and the controller 19 are combined to obtain a general user as a storage media product such as an SD (registered trademark) card and written later in the market when using the card, the SECID Write processing is required.

  FIG. 29 shows the case of data recorded on a storage medium in which the SECID is not recorded as described above.

As shown in the figure, in the NAND flash memory 10, the secret information NKey _i and the identification information ChipID are recorded in the secret area 11-2, and the index information i and the identification information necessary for specifying the secret information NKey _i are shown. The index information ID-index necessary for specifying the ChipID is written in the ROM area 11-3. However, the SECID has not been written in the NAND flash memory 10 yet.

  A case where the SECID is downloaded and recorded from the server to the storage medium 10 in which the SECID is not recorded will be described with reference to FIG.

  As shown in the figure, in this case, a data cache 12 is arranged in the NAND flash memory 10 as necessary.

Server 60 according to this embodiment, ChipID generator for generating a ChipID from ID-index (Generate ChipID) 62 , the encryption unit (Encrypt) 63, and IDKey database _{(Set of IDKey i s (i} = 1, ... X)) 61.

As a method for generating ChipID from ID-index, various conversions can be used. An example is shown below.
(Conversion example)
First, in advance using the conversion key K _m, which is distributed to each manufacturer of the NAND flash memory 10, a value obtained by encrypting the ChipID by encryption with ID-index. ID-index is shown as follows.

ID-index = Encrypt (K _m , ChipID)
The ID-index is transmitted to the server 60 via the Internet 50.

  The server 60 obtains the ChipID by using the generation unit 62 to decrypt the received ID-index using the conversion key Km. ChipID is shown as follows.

ChipID = Decrypt (K _m , ID-index)
Note that the conversion key K _m is not only common to all NAND flash memory 10 manufacturers, but can also be a different value for each NAND flash memory 10 manufacturer.

  The host device 20 has a function of determining whether or not new writing of the SECID is necessary, and requesting the SECID from the server as necessary.

<SECID write flow>
Next, a flow of downloading an encrypted ChipID bundle (SECID) from the server 60 and writing it into the NAND flash memory 10 will be described with reference to FIG.

  As shown in the figure, first, when the host device 20 determines that the SECID download is necessary, the SECID writing is started (Start), and the host device 20 issues a SECID request to the server 60 (Step S55).

  Subsequently, the server 60 requests the NAND flash memory 10 for index information ID-index necessary for specifying ChipID (Step S60).

  Subsequently, the NAND flash memory 10 reads the ID-index from the ROM area 11-3 and sends the ID-index to the server (Step S61).

  Subsequently, the server 60 generates a Chip ID using the ID-index received by the Chip ID generation unit 62 (Step S62).

Subsequently, the server 60 reads the secret IDKey _i (i = 1,..., X), encrypts the ChipID generated using each IDKey _i 61, and generates an encrypted ChipID bundle (SECID). (Step S63).

  Subsequently, the server 60 sends the formed encrypted ChipID bundle (SECID) to the NAND flash memory (Step S64).

  Subsequently, the NAND flash memory 10 writes and records the received encrypted ChipID bundle (SECID) in the general area 11-1 (Step S65).

  With the above operation, the encrypted ChipID bundle (SECID) download flow according to the twelfth embodiment is ended (End).

  Other configurations and operations are substantially the same as those in the eleventh embodiment.

<Effect>
According to the authentication device, the device to be authenticated, and the authentication method according to the twelfth embodiment, the same operational effects (1) and (2) as in the first embodiment can be obtained.

  Further, the present invention can be applied to the case where the SECID is written later as in the twelfth embodiment.

[Thirteenth embodiment (an example of a memory, a controller, and a host)]
Next, a thirteenth embodiment will be described with reference to FIG. The thirteenth embodiment relates to an example of the NAND flash memory 10, the controller 19, and the host device 20 that can be applied to the above embodiment. In this example, an SD (registered trademark) card is taken as an example of a memory card.

  As shown in the figure, in this example, functional blocks of the host device connected to the memory card are also shown. Each functional block can be realized as hardware, computer software, or a combination of both. Therefore, in order to make it clear that each block is any of these, it will be described below in terms of their functions in general. Whether such functionality is implemented as hardware or software depends upon the specific implementation or design constraints imposed on the overall system. Those skilled in the art can implement these functions in various ways for each specific embodiment, and any implementation technique is included in the scope of the present invention.

  The host device 20 includes software 211 such as an application and an operating system. The software 211 is instructed by the user to write data to the memory card and read data from the memory card. The software 211 instructs the file system 212 to write and read data. The file system 212 is a mechanism for managing file data recorded in a storage medium to be managed, records management information in a storage area of the storage medium, and manages the file data using this management information. .

  The host device 20 has an SD interface 213. The SD interface 213 includes hardware and software necessary for performing interface processing between the host device 20 and the memory card. The host device 20 communicates with the memory card via the SD interface 213. The SD interface 213 defines various agreements necessary for the communication between the host device 20 and the memory card, and includes various command sets that can be mutually recognized with the SD interface 231 of the memory card described later. The SD interface 213 also includes a hardware configuration (pin arrangement, number, etc.) that can be connected to the SD interface 231 of the memory card.

  The memory card has a NAND flash memory 10 and a controller 19 for controlling the memory 10. When the memory card is connected to the host device 20 or inserted into the host device 20 in the off state, the memory card receives power supply and performs an initialization operation. Process according to the access from.

  The NAND memory 10 stores data in a nonvolatile manner, and writes and reads data in units called pages composed of a plurality of memory cells. Each page is assigned a unique physical address. The memory 10 erases data in units called physical blocks (erase blocks) composed of a plurality of pages. A physical address may be assigned in units of physical blocks.

  The controller 19 manages the storage state of data in the memory 10. Storage state management refers to the relationship between which physical address page (or physical block) holds which logical address data, and which physical address page (or physical block) is erased (nothing written) Management of whether the data is not stored or has invalid data.

  The controller 19 includes an SD interface 31, a micro processing unit (MPU) 32, a read only memory (ROM) 33, a random access memory (RAM) 34, and a NAND interface 35.

  The SD interface 131 includes hardware and software necessary for performing interface processing between the host device 20 and the controller 19, and, like the SD interface 13, defines an agreement that enables communication between the two, and various types This includes a command set and includes hardware configuration (pin arrangement, number, etc.). The memory card (controller 22) communicates with the host 1 via the SD interface 131. The SD interface 131 includes a register 136.

  The MPU 132 controls the operation of the entire memory card. For example, when the memory card receives power supply, the MPU 132 reads the firmware (control program) stored in the ROM 133 onto the RAM 134 and executes predetermined processing. The MPU 132 creates various tables on the RAM 134 in accordance with the control program, and executes predetermined processing on the memory in accordance with commands received from the host 20.

  The ROM 133 stores a control program controlled by the MPU 132 and the like. The RAM 134 is used as a work area for the MPU 132 and temporarily stores control programs and various tables. As such a table, a conversion table (logical / physical table) of physical addresses of pages that actually store data having logical addresses assigned to data by the file system 212 is included. The NAND interface 135 performs an interface process between the controller 19 and the memory 10.

  As described above, the storage area in the NAND flash memory 10 is, for example, a general area (User area), a hidden area (Hidden area), a protected area (Protected area), a ROM according to the type of data to be stored. An area (ROM area) and the like are included. The controller 19 secures a part of the general area and stores control data (logical / physical table or the like) necessary for its own operation.

[Fourteenth Embodiment (Configuration Example of NAND Flash Memory)]
Next, a specific configuration example of the NAND flash memory 10 will be described as a fourteenth embodiment.

<Example of overall configuration>
A specific overall configuration example of the NAND flash memory 10 is shown in FIG.

  As shown in the figure, the NAND flash memory 10 according to this example includes a memory cell array 11, a control circuit 19, an authentication circuit 151, a bit line control circuit 152, a column decoder 153, a data input / output buffer 154, a data input / output terminal 155, A word line drive circuit 156, a control signal input terminal 158, and a power supply generation circuit 159 are provided.

  The memory cell array 11 includes a plurality of blocks (BLOCK1 to BLOCKn). Each of the plurality of blocks (BLOCK1 to BLOCKn) includes a plurality of memory cells arranged at intersections of word lines and bit lines. For example, BLOCK1 is the ROM area 11-3. For example, BLOCK2 is the secret area 11-2. The other blocks include a general area (User area) 11-1 that can be used from the host device 20.

  The ROM area 11-3 is an OTP (One Time Program) block, for example, and only one write is permitted. After writing, the block decoder is controlled using means such as an electric fuse, a laser fuse, and a ROM fuse to prohibit the erase operation. The secret area 11-2 cannot be selected by, for example, decoding of an external address, and is an area that can be read only by the control circuit 19 inside the NAND flash memory.

  The authentication circuit 151 includes, for example, the data cache 12, the generation circuits 13 and 16, the combination circuit 14, the random number generation circuit 15, the exclusive OR circuit 17, the encryptor 18, and the like, and is controlled by the control circuit 19.

  The bit line control circuit 152 reads the data of the memory cells in the memory cell array 11 through the bit lines, and detects the state of the memory cells in the memory cell array 11 through the bit lines. In addition, the bit line control circuit 152 applies a write control voltage to the memory cells in the memory cell array 11 via the bit lines to perform writing to the memory cells.

  In the bit line control circuit 152, a data storage circuit such as the page buffer (not shown) is provided, and the data storage circuit is selected by the column decoder 153. The memory cell data read to the data storage circuit is output to the outside from the data input / output terminal 155 via the data input / output buffer 154.

  The data input / output terminal 155 is connected to, for example, the external host device 20 or the like. The data input / output terminal 155 has a bus width of, for example, 8 bits or 16 bits. The NAND flash memory 10 may support a high-speed interface standard such as a toggle mode interface. In the toggle mode interface, for example, data transfer is performed via the data input / output terminal 155 in synchronization with both rising and falling edges of the data strobe signal (DQS).

  The host device 20 is, for example, a microcomputer and receives data output from the data input / output terminal 155. The host device 20 outputs various commands CMD (write command, read command, erase command, status read command, etc.), address ADD, and data DT for controlling the operation of the NAND flash memory 10. Write data DT input from the host device 20 to the data input / output terminal 155 is supplied to the data storage circuit (not shown) selected by the column decoder 153 via the data input / output buffer 154. On the other hand, the command CMD and the address ADD are supplied to the control circuit 19.

  The word line driving circuit 156 selects a word line in the memory cell array 11 under the control of the control circuit 19 and applies a voltage necessary for reading, writing, or erasing to the selected word line.

  The voltage generation circuit 159 supplies a voltage necessary for the operation of the connected constituent circuits in the figure under the control of the control circuit 19. For example, the voltage generation circuit 159 boosts an external voltage supplied from the host device, and generates a voltage applied to the word line at the time of reading, writing, or erasing.

  The control circuit (Controller) 19 gives necessary control signals and control voltages to each connected circuit in order to control the entire operation of the NAND flash memory 10. The control circuit 19 is connected to the memory cell array 11, the authentication circuit 151, the bit line control circuit 152, the column decoder 153, the data input / output buffer 154, the word line drive circuit 156, and the voltage generation circuit 159. The connected constituent circuits are controlled by the control circuit 19.

  The control circuit 19 is connected to the control signal input terminal 158, and receives a WE (write enable) signal, an RE (read enable) signal, and an ALE (address latch) input from the host device 20 via the control signal input terminal 158. It is controlled by a combination of control signals such as an enable signal and a CLE (command latch enable) signal.

  Here, in terms of function, the word line driving circuit 156, the bit line control circuit 152, the column decoder 153, and the control circuit 19 constitute a data write circuit, a data read circuit, and a data erase circuit. The host device 20 detects whether the NAND flash memory 10 is executing internal operations such as writing, reading, and erasing by monitoring a RY / BY (Ready / Busy) signal output terminal (not shown). To do. The control circuit 19 outputs the RY / BY signal via the RY / BY signal output terminal.

<Configuration example of block (BLOCK)>
Next, a configuration example of a block (BLOCK) included in the memory cell array will be described with reference to FIG. Here, BLOCK1 in FIG. 33 will be described as an example. Here, since the memory cells in the block BLOCK1 are erased collectively, the block is a data erase unit.

  The block BLOCK1 is composed of a plurality of memory cell units MU arranged in the word line direction (WL direction). The memory cell unit MU is arranged in a bit line direction (BL direction) intersecting the WL direction, and a NAND string (memory cell string) including eight memory cells MC0 to MC7 whose current paths are connected in series, and a NAND string The source-side selection transistor S1 connected to one end of the current path of the current and the drain-side selection transistor S2 connected to the other end of the current path of the NAND string.

  In this example, the memory cell unit MU is composed of eight memory cells MC0 to MC7, but may be composed of two or more memory cells, for example, 56, 32, etc. It is not limited to individuals.

  The other end of the current path of the source side select transistor S1 is connected to the source line SL. The other end of the current path of the drain-side selection transistor S2 is provided above the memory cell unit MU corresponding to each memory cell unit MU, and is connected to the bit line BLm-1 extending in the BL direction.

  Word lines WL0 to WL7 extend in the WL direction and are commonly connected to control gate electrodes of a plurality of memory cells in the WL direction. The selection gate line SGS extends in the WL direction and is commonly connected to a plurality of selection transistors S1 in the WL direction. The selection gate line SGD also extends in the WL direction and is commonly connected to a plurality of selection transistors S2 in the WL direction.

  A page (PAGE) exists for each of the word lines WL0 to WL7. For example, as indicated by being surrounded by a broken line in the figure, the page 7 (PAGE 7) exists in the word line WL7. Since a data read operation and a data write operation which will be described later are performed for each page (PAGE), the page (PAGE) is a data read unit and a data write unit.

As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.
The claims appended at the beginning of the filing of the present application will be appended below.
[1] An authentication method in which an authentication device authenticates a device to be authenticated,
The device to be authenticated holds secret first key information (NKey),
The authentication device retains original information (HC) and concealed second key information (HKey),
The authenticated device generating third key information (HKey ′) based on the original information (HC) and first key information (NKey);
The authenticated device generating a first session key (SKey) based on the third key information (HKey ′) and random number information;
An authentication method comprising: a step of generating a second session key (SKey ′) based on the second key information (HKey) and the random number information which are kept secret.
[2] The authentication target device further includes a step of encrypting the ID information held using the first session key and transmitting the encrypted ID information to the authentication device. Authentication method.
[3] The authentication device records the whole ID information (ChipID and LotID) encrypted in advance or partial ID information (LotID or ChipID) that is a part thereof in a recording area,
The authentication device reads the pre-encrypted ID information or the pre-encrypted partial ID information from the recording area of the device to be authenticated, and the pre-encrypted ID information or the pre-encrypted ID information or partial ID information is obtained by decoding using the second key information (HKey) concealing the partial ID information, and the decrypted ID information or partial ID information is sent from the authenticated device to the ID The authentication method according to [2], further comprising a step of confirming that the information is all or part of the information.
[4] The authentication device obtains the ID information by decrypting the ID information encrypted with the first session key transmitted from the device to be authenticated with the second session key;
The authentication device uses the part of the ID information obtained by decryption using the second key information and the ID information obtained by decryption using the second session key. The authentication method according to [3], further comprising a step of acquiring device identification information (ChipID).
[5] a cell array for storing the first key information (NKey) to be concealed;
A first data generation circuit that generates second key information (HKey) using original information (HC) of the authentication device and the first key information (NKey);
A device to be authenticated comprising a second data generation circuit that generates a session key (SKey) using the generated second key information (HKey) and random number information;
The second key information (HKey) is generated from the first key information (NKey), but the first key information (NKey) is not generated from the second key information (HKey).
[6] The cell array further stores identification information (ChipID) of the device to be authenticated,
The authenticated device according to [5], further comprising a one-way converter that converts the identification information (ChipID) by a one-way function using the session key (SKey).
[7] An authentication device for authenticating a device to be authenticated that holds confidential first key information (NKey), wherein the authentication device includes:
A memory for storing second key information (HKey) to be concealed;
A random number generator for generating random number information;
A data generation circuit that generates a session key (SKey) using the second key information (HKey) and the random number information;
The second key information (HKey) is generated from the first key information (NKey), but the first key information (NKey) is not generated from the second key information (HKey).
[8] The authentication device according to [7], further comprising a one-way converter that converts identification information (ChipID) received from the device to be authenticated by a one-way function using the session key (SKey).
[9] The authentication device transmits the pre-encrypted partial ID information (LotID or ChipID), which is the entire pre-encrypted ID information (ChipID and LotID) or a part thereof, from the authenticated device. reading,
The authentication device receives third key information (IDKey) different from the second key information (HKey) necessary for decrypting the pre-encrypted ID information or the pre-encrypted partial ID information. Further storing in the memory;
The authentication device acquires the ID information or the partial ID information by decrypting the pre-encrypted ID information or the pre-encrypted partial ID information with the third key information (IDKey). The authentication device according to [7] or [8].

  DESCRIPTION OF SYMBOLS 10 ... Device to be authenticated (NAND flash memory), 19 ... Controller, 20 ... Authentication device (host device), 11 ... Cell array, 23 ... Memory, NKey ... First key information, HKey ... Second key information, SKey ... Session Key information.

Claims (4)

An authentication method in which an authentication device authenticates a device to be authenticated,
The device to be authenticated holds confidential first key information and identification information of the device to be authenticated ,
The authentication device holds the original information and the second key information concealed,
The authenticated device generating third key information based on the original information and the first key information;
The device to be authenticated generates a first session key based on the third key information and random number information;
The authentication device generating a second session key based on the second key information and random number information concealed ;
The authenticated device generates unidirectional conversion identification information by converting the identification information with a unidirectional function using the first session key;
An authentication method comprising: authenticating the authentication apparatus using the one-way conversion identification information . A cell array for storing the first key information to be concealed and the identification information of the device to be authenticated ;
A first data generation circuit for generating second key information using the original information of the authentication device and the first key information;
A second data generation circuit for generating a session key using the generated second key information and random number information ;
By converting the identification information with a one-way function using the session key, the one-way conversion identification information is generated, and the one-way conversion identification information is authenticated by the authentication device. A to-be-authenticated device comprising a unidirectional converter for transmitting to
An apparatus to be authenticated, configured to generate the second key information from the first key information, but not to generate the first key information from the second key information. An authentication device for authenticating a device to be authenticated that holds confidential first key information, wherein the authentication device includes:
A memory for storing secret second key information;
A random number generator for generating random number information;
A data generation circuit for generating a session key using the second key information and the random number information ;
A unidirectional converter that generates unidirectional conversion identification information by converting the first identification information received from the device to be authenticated using the session key with a unidirectional function;
A verification unit that verifies whether the one-way conversion identification information matches the second identification information received from the device to be authenticated ;
The authentication apparatus is configured to generate the second key information from the first key information in the authenticated apparatus, but not to generate the first key information from the second key information. The authentication apparatus, the pre-encrypted ID information, read out from said apparatus to be authenticated,
The authentication device further stores necessary for decoding the ID information of the pre encrypted, the third key information that is different from the second key information in said memory,
The authentication device, the by decoding by the pre-encrypted ID information and the third key information, the authentication device according to claim 3 for obtaining the first identification information.

Images