WO2024065488A1 - Method and apparatus for sidelink channel structure - Google Patents

Method and apparatus for sidelink channel structure Download PDF

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Publication number
WO2024065488A1
WO2024065488A1 PCT/CN2022/122849 CN2022122849W WO2024065488A1 WO 2024065488 A1 WO2024065488 A1 WO 2024065488A1 CN 2022122849 W CN2022122849 W CN 2022122849W WO 2024065488 A1 WO2024065488 A1 WO 2024065488A1
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WO
WIPO (PCT)
Prior art keywords
slot structure
symbol
sidelink
starting point
symbols
Prior art date
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PCT/CN2022/122849
Other languages
French (fr)
Inventor
Yuzhou HU
Youxiong Lu
Jie Chen
Weimin XING
Haigang HE
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Zte Corporation
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Publication date
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Priority to PCT/CN2022/122849 priority Critical patent/WO2024065488A1/en
Publication of WO2024065488A1 publication Critical patent/WO2024065488A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W72/00Local resource management
    • H04W72/20Control channels or signalling for resource management
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/003Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053Allocation of signaling, i.e. of overhead other than pilot signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/0091Signaling for the administration of the divided path
    • H04L5/0094Indication of how sub-channels of the path are allocated
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W72/00Local resource management
    • H04W72/04Wireless resource allocation
    • H04W72/044Wireless resource allocation based on the type of the allocated resource
    • H04W72/0446Resources in time domain, e.g. slots or frames
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W72/00Local resource management
    • H04W72/40Resource management for direct mode communication, e.g. D2D or sidelink

Definitions

  • This document is directed generally to wireless communications, in particular 5 th generation wireless communications, and in particular to sidelink (SL) communications.
  • wireless communications in particular 5 th generation wireless communications
  • SL sidelink
  • the channel structure for SL operation over an unlicensed spectrum is under discussion.
  • the number of starting points for a given slot structure is one per bandwidth part (BWP) , implying that the channel access of the SL operation takes place only on a slot boundary. This could lead to an uncompetitive situation versus Wifi technology whose channel access takes place effectively at any time.
  • BWP bandwidth part
  • blind decoding efforts for a physical SL control channel (PSCCH) per slot may be increased to M times the number of subchannels within one BWP.
  • PSCCH physical SL control channel
  • the bandwidth for the unlicensed spectrum is configured as 100MHz and a subcarrier spacing (SCS) is set as 30kHz according to the number of interlaces configured as below table, i.e., 5 interlaces in one resource block (RB) set
  • SCS subcarrier spacing
  • configured can refer to either configured by the network, pre-configured by the higher layer or predefined.
  • the decoding efforts shall be calculated as:
  • N is the number of RBs taken from the tables below for frequency range 1 (FR1) and frequency range 1 (FR2) respectively:
  • This document relates to methods, systems, and devices for sidelink communications, and in particular to methods, systems, and devices for determining sidelink channel structure of the sidelink communications.
  • the present disclosure relates to a wireless communication method for use in a first wireless device.
  • the method comprises:
  • the first control channel is shifted from the first starting point to the second starting point.
  • the first control channel is shifted based on a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point.
  • the second sidelink slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
  • the second sidelink slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
  • mapping the first control channel of the first sidelink slot structure from the first starting point to the same position as the second starting point corresponding the second control channel of the second sidelink slot structure comprises: performing a cyclic shift operation on the first control channel.
  • the wireless communication method further comprises performing the cyclic shift operation on at least one of one or more demodulation reference signals, DMRSs, of the first control channel, one or more shared channels of the first sidelink slot structure or one or more DMRSs of the one or more shared channels.
  • DMRSs demodulation reference signals
  • the cyclic shift operation is performed before or after mapping symbols of the first sidelink structure to physical resources.
  • the cyclic shift operation is not applied to at least one of an automatic gain control symbol or a gap symbol.
  • the cyclic shift operation is performed before mapping symbols of the first sidelink slot structure to physical resources, and the cyclic shift operation is performed by:
  • l (l′+SO) mod l d +floor [ (l′+SO) /l d ] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
  • l [ (l′-1+SO) mod l d ] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
  • SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • the cyclic shift operation is performed after mapping symbols of the first sidelink slot structure to physical resources,
  • l f (l+SO) mod l d +floor [ (l+SO) /l d ] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
  • l f [ (l-1+SO) mod l d ] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
  • SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • the cyclic shift operation is applied to symbols within a shifting range.
  • the shifting range starts at a symbol from which the first control channel of the first sidelink slot structure is mapped.
  • the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length excluding the additional automatic gain control symbols of the first sidelink slot structure and a second symbol length of the second sidelink slot structure, wherein an additional automatic gain control symbol is configured in the first sidelink slot structure.
  • the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length excluding the additional AGC symbols of the first sidelink slot structure and a second symbol length of the second sidelink slot structure, wherein an additional AGC symbol is configured in the first sidelink slot structure.
  • the cyclic shift operation is performed before mapping symbols of the first sidelink slot structure to physical resources
  • mapping a symbol at a location l′ in the shifting range to a location l based on:
  • l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • the cyclic shift operation is performed after mapping symbols of the first sidelink slot structure to physical resources,
  • l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • a DMRS transmitted based on the symbol index in the first slot structure is generated before or after the cyclic operation is performed.
  • the wireless communication method further comprises at least one of:
  • sidelink control information on the control channel of the first sidelink slot structure comprises at least one of an indication of a starting symbol, cyclic shift information associated with a cyclic shift operation performed on the first sidelink slot structure, or an indication of sidelink transmission symbols.
  • the present disclosure relates to a first wireless device.
  • the first wireless device comprises:
  • a processor configured to map a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
  • Various embodiments may preferably implement the following feature:
  • the processor is further configured to perform any of the aforementioned wireless communication methods.
  • the present disclosure relates to a computer program product comprising a computer-readable program medium code stored thereupon, the code, when executed by a processor, causing the processor to implement a wireless communication method recited in any one of foregoing methods.
  • the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and/or hierarchy of steps in the methods disclosed herein are merely exemplary approaches. Based upon design preferences, the specific order or hierarchy of steps of the disclosed methods or processes can be re-arranged while remaining within the scope of the present disclosure. Thus, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or acts in a sample order, and the present disclosure is not limited to the specific order or hierarchy presented unless expressly stated otherwise.
  • FIGS. 1A, 1B, 2A and 2B show schematic diagrams of slot structures according to embodiments of the present disclosure.
  • FIG. 3 shows a schematic diagram of a network (architecture) according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • FIGS. 6A to 6C show schematic diagrams of slot structures according to an embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • FIG. 9 shows an example of a schematic diagram of a wireless terminal according to an embodiment of the present disclosure.
  • FIG. 10 shows an example of a schematic diagram of a wireless network node according to an embodiment of the present disclosure.
  • FIG. 11 shows a flowchart of a method according to an embodiment of the present disclosure.
  • FIGS. 12 and 13 show schematic diagrams of slot structures according to embodiments of the present disclosure.
  • the time domain channel structure of SL operation consists of the following:
  • PSSCH physical SL shared channel
  • DMRS demodulation reference signal
  • PSCCH physical sidelink control channel
  • FIGS. 1A, 1B, 2A and 2B show schematic diagrams of slot structures for 6 to 8 symbols and for 13 symbols according to embodiments of the present disclosure.
  • FIG. 3 shows a schematic diagram of a network (architecture) according to an embodiment of the present disclosure.
  • the network shown in FIG. 3 comprises a base station (BS) , a relay (node) (e.g., a header UE) and two UEs UE1 and UE2.
  • the UE1 may be a mobile phone and the UE2 may be a smart gadget (e.g., smart glasses) .
  • the UE1 and/or UE2 may be an internet of things (IoT) device.
  • IoT internet of things
  • the UE1 and/or UE2 may communicate with the BS directly or via relay.
  • the relay, UE1 and UE2 may communicate with each other, where the communication between every two of the relays, UE1 and UE2 are called SL communications.
  • the SL communication may be in the form of unicast, groupcast or broadcast.
  • the UE2 may communicate with the BS/relay via the UE1. That is the UE1 may act as a UE/mobile relay.
  • the mapping rule of PSCCH is changed from starting from the first symbol of the PSSCH for a slot structure to starting from a common location to all the starting points configured as illustrated in FIG. 4.
  • a slot structure 4A represents a slot structure with a starting point 0 (i.e., starting at the first symbol other than AGC symbol) and a slot structure 4C represents a slot structure with a starting point 3 (i.e., starting at the third symbol other than AGC symbol) .
  • the PSCCH mapping of the slot structure with starting point 0 starts from the symbol 4 (i.e., the symbol with an index 4) .
  • the slot structure 4A becomes a slot structure 4B shown in FIG. 4.
  • d ld, 1 -ld, 2.
  • the starting point of the slot structure of symbol length ld, 2 as ls, 2.
  • the starting point of PSCCH mapping shall be the symbol d+ ls, 2 (i.e. symbol with the index d+ ls, 2) for the slot structure of a larger symbol length ld, 1 (e.g., slot structure 4A) .
  • the rule of changing the mapping rule of PSCCH can be extended to the case of more than two starting points to shift/change the PSCCH starting points of all slot structures to one common location.
  • the common location may be determined to be equal to the PSCCH location of the slot structure with the fewest number of symbols or with a starting point whose symbol index is largest.
  • a cyclic shift operation may be performed to one or all of the symbols of a slot structure with a given starting point to generate another slot structure that has a common PSCCH location as a slot structure with another given starting point.
  • the cyclic shift can be performed before the mapping to physical resources or after the mapping to physical resources.
  • the cyclic shift operation may be applied to PSCCH and one or all of the PSCCH DMRS, the PSSCH, the PSSCH DMRS. In an embodiment, the cyclic shift operation is not applied to the AGC symbol and/or the gap symbol.
  • the operation is performed as follows:
  • the modulated PSCCH and/or PSCCH DMRS and/or PSSCH and/or PSSCH DMRS symbols are arranged in sequence to the form of (k, l′) along the allocated frequency range for k and the time domain location for l′.
  • the rule/formula can be:
  • SO is a shifting offset.
  • the SO is determined by/based on either a starting point difference between the first starting point and the common starting point or a symbol length difference between the slot structure with the first starting point or the largest symbol length and the slot structure with the fewest number of symbols.
  • the SO can be equal to the starting point difference or the symbol length difference.
  • the cyclic shift operation is performed as below.
  • the modulated PSCCH, PSCCH DMRS, PSSCH and PSSCH DMRS symbols are mapped in sequence to the form of (k, l) along the allocated frequency range for k and the time domain location for l.
  • the cyclic shift operation is performed to each symbol l to generate a slot structure with symbol l f .
  • the time domain resource allocation of the transmitted slot structure follows the symbol l f .
  • l d refers to the length of symbols of the slot structure with a first starting point including the AGC symbol and not including the gap symbol (see, e.g., the examples of the symbol length equal to 13 in FIG. 2A and 2B) and l f can be determined as:
  • l d may be the symbol length not including the AGC symbol or the gap symbol (see, e.g., the examples of the symbol length equal to 12 in FIG. 2A and 2B) and the formula for determining l f can be:
  • the shifting offset SO is determined by either the starting point difference or the symbol length difference and can be equal to the starting point difference or the symbol length difference.
  • FIG. 5 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • the cyclic shift operation is applied on all of the PSCCH, PSCCH DMRS, PSSCH, and PSSCH DMRS of a slot structure 51, to generate a slot structure 52 having a starting point the same with that of a slot structure 53.
  • the cyclic shift operation is applied on all of symbols excluding the AGC symbol or the gap symbol (GP) of the slot structure 51, the symbols 1 to 9 in the slot structure 51 are shifted to symbols 4 to 12 in the slot structure 52 and the symbols 10 to 12 in the slot structure 51 are shifted to symbols 1 to 3 in the slot structure 52.
  • the slot structures 52 and 53 have the same starting point.
  • FIGS. 6A to 6C show schematic diagrams of slot structures according to an embodiment of the present disclosure.
  • the cyclic shift operation if performed, is applied on all of the PSCCH, PSCCH DMRS, PSSCH, and PSSCH DMRS of a slot structure.
  • the cyclic shift operation is applied on a slot structure 61, to generate a slot structure 62 of which the PSCCH starting point is the same with those of slot structures 63 and 67 having the fewest number of symbols. As shown in FIG.
  • the symbols 7 to 11 in the slot structure 61 are shifted to the symbols 8 to 12 of the slot structure 62 and the symbol 12 in the slot structure 61 is shifted to the symbol 7 in the slot structure 62.
  • the cyclic shift operation is applied on a slot structure 64, to generate a slot structure 65 of which the PSCCH starting point is the same with those of the slot structures 63 and 67.
  • the symbols 6 to 10 in the slot structure 64 are shifted to symbols 8 to 12 of the slot structure 65 and the symbols 11 and 12 in the slot structure 64 are shifted to the symbols 6 and 7 in the slot structure 65.
  • FIG. 6B the symbols 6 to 10 in the slot structure 64 are shifted to symbols 8 to 12 of the slot structure 65 and the symbols 11 and 12 in the slot structure 64 are shifted to the symbols 6 and 7 in the slot structure 65.
  • the cyclic shift operation is applied on a slot structure 66, to generate a slot structure 67 having the same PSCCH starting point as the slot structures 63 and 67. Specifically, the symbols 5 to 8 in the slot structure 66 are shifted to symbols 8 to 12 of the slot structure 67 and the symbols 9 to 11 in the slot structure 66 are shifted to the symbols 5 to 7 in the slot structure 67.
  • the starting point of the PSCCH for slot structures 63 and 67 remain the same.
  • the cyclic shift operation may be applied to only certain symbols (e.g., symbols in a shifting range) among the one or all of the PSCCH, PSCCH DMRS, PSSCH, PSSCH DMRS symbols.
  • the number of symbols on which the cyclic shift operation is applied is greater than or equal to 2*d when there is no additional AGC symbol configured, where d is the difference of the symbol lengths or staring points.
  • l d is based on the number of symbols in the shifting range where the cyclic shift operation is performed.
  • FIG. 7 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • the cyclic shift operation is applied only to the symbols 1 to 6 in the shifting range. Specifically, the symbols (1, 2, 3) in a slot structure 71 are shifted to the symbols (4, 5, 6) in a slot structure 72 and the symbols (4, 5, 6) in the slot structure 71 are shifted to the symbols (1, 2, 3) in the slot structure 72.
  • the slot structure 72 and the slot structure 73 have the same starting point.
  • the CS operation shall/is not be applied to the AGC symbols within the same range of symbols as in the above embodiments.
  • FIG. 8 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • the cyclic shift operation is applied only to the symbols (1, 2, 4, 5) in the slot structure 81.
  • the symbol 3 in the slot structure 81 remains unchanged because being the AGC symbol.
  • the symbols (1, 2) in the slot structure 81 are shifted to the symbols (4, 5) in a slot structure 82 and the symbols (4, 5) in the slot structure 81 are shifted to the symbols (1, 2) in the slot structure 82.
  • the slot structures 82 and 83 have the same starting points. Note that the shifting range shall thus not take into account any AGC symbol.
  • FIG. 12 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • the PSCCH symbols in a slot structure 121 are directly mapping to the symbol 4 or the cyclic shift operation is applied to the PSCCH symbols whose starting point is shifted to the symbol 4 making the PSCCH symbols coincide in time domain with the slot structure 123 (see slot structure 122) .
  • the PSSCH DMRS symbol 1 (for PSSCH) and PSSCH symbols (2, 3) in the slot structure 122 are truncated and not used to carry payload. With the truncation, the slot structure 122 has the same number of symbols to carry payload as the slot structure 123.
  • the transport block determined (e.g., based on the slot structures 122 and 123) from a MAC layer (entity) could be the same as well.
  • Duplicated PSSCH symbols and/or PSSCH DMRS symbols and/or AGC symbols at the truncated symbol location may still be transmitted.
  • FIG. 13 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
  • the TB size calculation and transport block determined from the MAC layer (entity) is based on a configured symbol length and starting point.
  • the physical resource mapping of the PSSCH is also based on the configured symbol length and starting point.
  • the PSCCH symbols are directly mapped to the symbol 4 or the cyclic shift operation is applied to the PSCCH symbols whose starting point is shifted to the symbol 4.
  • There exists therefore a candidate starting point region comprising symbol indexes 1, 2 and 3 (or symbols with the indexes 1, 2 and 3) , see, e.g., slot structure 131.
  • the candidate starting point region may further include the symbol index 0 (the configured starting point herein) .
  • the candidate starting point region comprises a symbol whose symbol index plus 1 equal to the index of the first symbol where PSCCH is mapped over.
  • the transmission can start from any symbol (actual starting point) within the candidate starting point region apart from the symbol index 0, i.e. the configured starting point.
  • the PSSCH symbols between the configured starting point and the actual starting point are truncated prior to transmission/punctured in the transmission.
  • the truncating/puncturing herein refers to not transmitting the symbols between the configured starting point and actual starting point.
  • the PSCCH of the slot structures with both starting symbols may reserve some indication for starting symbol information and cyclic shift operation information.
  • SCI sidelink control information
  • the SCI bits may also be used to indicate the localized cyclic shift operation (i.e., associated with the cyclic shift operation performed on symbols in the shifting range) or full range cyclic shift operation information (i.e., associated with the cyclic shift operation performed on all of symbols in the slot structure) or an indication of sidelink transmission symbols to determine the transmission block size.
  • the indication of sidelink transmission symbols can refer to whether to take into account the transmission symbol length difference corresponding to the slot structures associated with multiple starting points.
  • the indication of sidelink transmission symbols can refer to the average of multiple symbol lengths among the symbol lengths associated with different starting points, the largest symbol length among the symbol lengths associated with different starting points or the smallest symbol length among the symbol lengths associated with different starting points.
  • the PSCCH/PSSCH DMRS is generated by using the position information of the DMRS before the cyclic shift operation or directly mapping to a common location.
  • the PSCCH/PSSCH DMRS is generated by using the position information of the DMRS after the cyclic shift operation or directly mapping to a common location.
  • the common starting point for the PSCCH mapping may be fixed.
  • the starting points of the PSSCH/PSCCH DMRS or PSSCH itself shall be determined as a configured offest to the common starting point for PSCCH mapping.
  • the cyclic shift operation or directly mapping PSCCH or one of PSSCH, PSSCH DMRS or PSCCH DMRS is not applied. For those slots, only one starting point among the multiple configured starting points is used.
  • FIG. 9 relates to a schematic diagram of a wireless terminal 90 according to an embodiment of the present disclosure.
  • the wireless terminal 90 may be a user equipment (UE) , a mobile phone, a laptop, a tablet computer, an electronic book or a portable computer system and is not limited herein.
  • the wireless terminal 90 may include a processor 900 such as a microprocessor or Application Specific Integrated Circuit (ASIC) , a storage unit 910 and a communication unit 920.
  • the storage unit 910 may be any data storage device that stores a program code 912, which is accessed and executed by the processor 900.
  • Embodiments of the storage unit 910 include but are not limited to a subscriber identity module (SIM) , read-only memory (ROM) , flash memory, random-access memory (RAM) , hard-disk, and optical data storage device.
  • SIM subscriber identity module
  • ROM read-only memory
  • RAM random-access memory
  • the communication unit 920 may a transceiver and is used to transmit and receive signals (e.g., messages or packets) according to processing results of the processor 900.
  • the communication unit 920 transmits and receives the signals via at least one antenna 922 shown in FIG. 9.
  • the storage unit 910 and the program code 912 may be omitted and the processor 900 may include a storage unit with stored program code.
  • the processor 900 may implement any one of the steps in exemplified embodiments on the wireless terminal 90, e.g., by executing the program code 912.
  • the communication unit 920 may be a transceiver.
  • the communication unit 920 may as an alternative or in addition be combining a transmitting unit and a receiving unit configured to transmit and to receive, respectively, signals to and from a wireless network node (e.g., a base station) .
  • a wireless network node e.g., a base station
  • FIG. 10 relates to a schematic diagram of a wireless network node 100 according to an embodiment of the present disclosure.
  • the wireless network node 100 may be a satellite, a base station (BS) , a network entity, a Mobility Management Entity (MME) , Serving Gateway (S-GW) , Packet Data Network (PDN) Gateway (P-GW) , a radio access network (RAN) node, a next generation RAN (NG-RAN) node, a gNB, an eNB, a gNB central unit (gNB-CU) , a gNB distributed unit (gNB-DU) a data network, a core network or a Radio Network Controller (RNC) , and is not limited herein.
  • BS base station
  • MME Mobility Management Entity
  • S-GW Serving Gateway
  • PDN Packet Data Network Gateway
  • RAN radio access network
  • NG-RAN next generation RAN
  • gNB next generation RAN
  • gNB next generation RAN
  • the wireless network node 100 may comprise (perform) at least one network function such as an access and mobility management function (AMF) , a session management function (SMF) , a user place function (UPF) , a policy control function (PCF) , an application function (AF) , etc.
  • the wireless network node 100 may include a processor 1000 such as a microprocessor or ASIC, a storage unit 1010 and a communication unit 1020.
  • the storage unit 1010 may be any data storage device that stores a program code 1012, which is accessed and executed by the processor 1000. Examples of the storage unit 1010 include but are not limited to a SIM, ROM, flash memory, RAM, hard-disk, and optical data storage device.
  • the communication unit 1020 may be a transceiver and is used to transmit and receive signals (e.g., messages or packets) according to processing results of the processor 1000.
  • the communication unit 1020 transmits and receives the signals via at least one antenna 1022 shown in FIG. 10.
  • the storage unit 1010 and the program code 1012 may be omitted.
  • the processor 1000 may include a storage unit with stored program code.
  • the processor 1000 may implement any steps described in exemplified embodiments on the wireless network node 100, e.g., via executing the program code 1012.
  • the communication unit 1020 may be a transceiver.
  • the communication unit 1020 may as an alternative or in addition be combining a transmitting unit and a receiving unit configured to transmit and to receive, respectively, signals to and from a wireless terminal (e.g., a user equipment or another wireless network node) .
  • a wireless terminal e.g., a user equipment or another wireless network node
  • FIG. 11 shows a flowchart of a method according to an embodiment of the present disclosure.
  • the method shown in FIG. 11 may be used in a first wireless device (e.g. UE) and comprises the following step:
  • Step 1101 Map a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
  • the first wireless device maps a first control channel (e.g., PSCCH) of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
  • a first control channel e.g., PSCCH
  • the control channels in different slot structures have the same starting point (i.e., common starting point) .
  • the number of blind detections performed by a receiving terminal in the sidelink communications is therefore decreased.
  • the first control channel may perform the mapping on other slot structure (s) . That is the method may be used in a case with more than 2 slot structures.
  • the second slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
  • the mapping may be performed by shifting the first control channel from the first starting point to the second starting point (see, e.g., FIG. 4) .
  • the first control channel is shifted based on a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point.
  • mapping the first control channel of the first sidelink slot structure from the first starting point to the same position as the second starting point corresponding the second control channel of the second sidelink slot structure comprises:
  • the cyclic shift operation may also be performed on at least one of DMRS (s) of the first control channel, shared channel (s) (e.g., PSSCH (s) ) or DMRS (s) of the shared channel (s) .
  • DMRS DMRS
  • the cyclic shift operation is performed before or after mapping symbols of the first sidelink structure to physical resources.
  • the cyclic shift operation is not applied to at least one of an automatic gain control symbol or a gap symbol.
  • the cyclic shift operation being performed before mapping symbols of the first sidelink slot structure to physical resources.
  • the cyclic shift operation is performed by:
  • l (l′+SO) mod l d +floor [ (l′+SO) /l d ] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
  • l [ (l′-1+SO) mod l d ] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
  • SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • the cyclic shift operation is performed by:
  • l f (l+SO) mod l d +floor [ (l+SO) /l d ] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
  • SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • the cyclic shift operation is applied to symbols within a shifting range (see, e.g., FIG. 7 or 8) .
  • the shifting range starts at a symbol from which the first control channel of the first sidelink slot structure is mapped.
  • the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point, wherein there is no additional AGC symbol configured in the first sidelink slot structure.
  • the cyclic shift operation is performed by:
  • mapping a symbol at a location l′ in the shifting range to a location l based on:
  • l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • the cyclic shift operation is performed by:
  • l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  • a DMRS transmitted based on the symbol index in the first slot structure is generated before or after the cyclic operation is performed.
  • the first wireless device may transmit, to a second wireless device, sidelink signals based on the first sidelink slot structure.
  • the first wireless device is a transmitting side in the sidelink communications.
  • the first wireless device performs a blind detection for sidelink signals based on the first sidelink slot structure.
  • the first wireless device is a receiving side in the sidelink communications.
  • the first wireless device receives, from the second wireless device, sidelink signals based on the first sidelink slot structure.
  • the first wireless device is the receiving side in the sidelink communications.
  • the first wireless device may transmit, to a second wireless device, sidelink signals based on the second sidelink slot structure.
  • the first wireless device is a transmitting side in the sidelink communications.
  • the first wireless device performs a blind detection for sidelink signals based on the second sidelink slot structure.
  • the first wireless device is a receiving side in the sidelink communications.
  • the first wireless device receives, from the second wireless device, sidelink signals based on the second sidelink slot structure. In this embodiment, the first wireless device is the receiving side in the sidelink communications.
  • SCI on the control channel of the first sidelink slot structure comprises at least one of an indication of a starting symbol, cyclic shift information associated with a cyclic shift operation performed on the first sidelink slot structure, or an indication of sidelink transmission symbols.
  • any reference to an element herein using a designation such as “first, “ “second, “ and so forth does not generally limit the quantity or order of those elements. Rather, these designations can be used herein as a convenient means of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element in some manner.
  • any one of the various illustrative logical blocks, units, processors, means, circuits, methods and functions described in connection with the aspects disclosed herein can be implemented by electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two) , firmware, various forms of program or design code incorporating instructions (which can be referred to herein, for convenience, as "software” or a “software unit” ) , or any combination of these techniques.
  • a processor, device, component, circuit, structure, machine, unit, etc. can be configured to perform one or more of the functions described herein.
  • IC integrated circuit
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the logical blocks, units, and circuits can further include antennas and/or transceivers to communicate with various components within the network or within the device.
  • a general purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, or state machine.
  • a processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other suitable configuration to perform the functions described herein. If implemented in software, the functions can be stored as one or more instructions or code on a computer-readable medium. Thus, the steps of a method or algorithm disclosed herein can be implemented as software stored on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program or code from one place to another.
  • a storage media can be any available media that can be accessed by a computer.
  • such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • unit refers to software, firmware, hardware, and any combination of these elements for performing the associated functions described herein. Additionally, for purpose of discussion, the various units are described as discrete units; however, as would be apparent to one of ordinary skill in the art, two or more units may be combined to form a single unit that performs the associated functions according embodiments of the present disclosure.
  • memory or other storage may be employed in embodiments of the present disclosure.
  • memory or other storage may be employed in embodiments of the present disclosure.
  • any suitable distribution of functionality between different functional units, processing logic elements or domains may be used without detracting from the present disclosure.
  • functionality illustrated to be performed by separate processing logic elements, or controllers may be performed by the same processing logic element, or controller.
  • references to specific functional units are only references to a suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization.

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Abstract

A wireless communication method for use in a first wireless device is disclosed. The method comprises mapping a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.

Description

METHOD AND APPARATUS FOR SIDELINK CHANNEL STRUCTURE
This document is directed generally to wireless communications, in particular 5 th generation wireless communications, and in particular to sidelink (SL) communications.
The channel structure for SL operation over an unlicensed spectrum is under discussion. In the existing art, the number of starting points for a given slot structure is one per bandwidth part (BWP) , implying that the channel access of the SL operation takes place only on a slot boundary. This could lead to an uncompetitive situation versus Wifi technology whose channel access takes place effectively at any time.
If M (where M >1) starting positions are configured per BWP, however, blind decoding efforts for a physical SL control channel (PSCCH) per slot may be increased to M times the number of subchannels within one BWP. For example, if the bandwidth for the unlicensed spectrum is configured as 100MHz and a subcarrier spacing (SCS) is set as 30kHz according to the number of interlaces configured as below table, i.e., 5 interlaces in one resource block (RB) set, the total number of interlaces/subchannels within 100MHz shall be 25, resulting an overall PSCCH blind detection effort of 50 times if M =2 starting positions are configured. In the remaining description of the specification, configured can refer to either configured by the network, pre-configured by the higher layer or predefined.
Based on the following UE capability requirements, the decoding efforts shall be calculated as:
{N/10, 2*N/10} ,
where N is the number of RBs taken from the tables below for frequency range 1 (FR1) and frequency range 1 (FR2) respectively:
Table: FR1
Figure PCTCN2022122849-appb-000001
Figure PCTCN2022122849-appb-000002
Table: FR2
Figure PCTCN2022122849-appb-000003
Simple calculation will lead to the decoding capability as below:
  FR1 FR2
15 {54, 27}  
30 {48, 24}  
60 {24, 12} {52, 26}
120   {52, 26}
That is, in a case of SCS (sub-carrier spacing) = 30kHz, one RB set consisting of 5 interlaces, the total number of interlaces being 25 and each subchannel occupying one interlace, the total number of decoding efforts for the PSCCH per slot shall be 50 for M=2 starting points. If more than 2 starting points are considered for further improving the channel access probability, barely a device could be implemented in a way tolerating the blind detection efforts for the PSCCH.
In order not to restrict the flexibility of subchannel vs interlace association (i.e., leaving the option of 1 subchannel containing a single interlace open) , some mechanism are required to make sure that the decoding efforts of multiple access points are not beyond the UE capability.
This document relates to methods, systems, and devices for sidelink communications, and in particular to methods, systems, and devices for determining sidelink channel structure of the sidelink communications.
The present disclosure relates to a wireless communication method for use in a first wireless device. The method comprises:
mapping a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
Various embodiments may preferably implement the following features:
Preferably, the first control channel is shifted from the first starting point to the second starting point.
Preferably, the first control channel is shifted based on a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point.
Preferably, the second sidelink slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
Preferably, the second sidelink slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
Preferably, mapping the first control channel of the first sidelink slot structure from the first starting point to the same position as the second starting point corresponding the second control channel of the second sidelink slot structure comprises: performing a cyclic shift operation on the first control channel.
Preferably, the wireless communication method further comprises performing the cyclic shift operation on at least one of one or more demodulation reference signals, DMRSs, of the first control channel, one or more shared channels of the first sidelink slot structure or one or more DMRSs of the one or more shared channels.
Preferably, the cyclic shift operation is performed before or after mapping symbols of  the first sidelink structure to physical resources.
Preferably, the cyclic shift operation is not applied to at least one of an automatic gain control symbol or a gap symbol.
Preferably, the cyclic shift operation is performed before mapping symbols of the first sidelink slot structure to physical resources, and the the cyclic shift operation is performed by:
mapping a symbol at a location l′ in the first sidelink slot structure to a location l based on:
l=(l′+SO) mod l d+floor [ (l′+SO) /l d] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
l= [ (l′-1+SO) mod l d] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
wherein SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
Preferably, the cyclic shift operation is performed after mapping symbols of the first sidelink slot structure to physical resources,
wherein the cyclic shift operation is performed by:
performing the cyclic shift operation on the mapped first sidelink slot structure, wherein a symbol at a location l in the mapped first sidelink slot structure has a location l f after the cyclic shift operation is performed and:
l f= (l+SO) mod l d+floor [ (l+SO) /l d] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
l f= [ (l-1+SO) mod l d] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
wherein SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
Preferably, the cyclic shift operation is applied to symbols within a shifting range.
Preferably, the shifting range starts at a symbol from which the first control channel of the first sidelink slot structure is mapped.
Preferably, the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length excluding the additional automatic gain control symbols of the first sidelink slot structure and a second symbol length of the second sidelink slot structure, wherein an additional automatic gain control symbol is configured in the first sidelink slot structure.
Preferably, the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length excluding the additional AGC symbols of the first sidelink slot structure and a second symbol length of the second sidelink slot structure, wherein an additional AGC symbol is configured in the first sidelink slot structure.
Preferably, the cyclic shift operation is performed before mapping symbols of the first sidelink slot structure to physical resources,
wherein the cyclic shift operation is performed by:
mapping a symbol at a location l′ in the shifting range to a location l based on:
l=(l′+SO) mod l d+floor [ (l′+SO) /l d] , or
l=[ (l′-1+SO) mod l d] +1,
wherein l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
Preferably, the cyclic shift operation is performed after mapping symbols of the first sidelink slot structure to physical resources,
wherein the cyclic shift operation is performed by:
performing the cyclic shift operation on mapped symbols in the shifting range, wherein  a symbol at a location l in shifting range has a location l f after the cyclic shift operation is performed and:
l f= (l+SO) mod l d+floor [ (l′+SO) /l d] , or
l f= [ (l-1+SO) mod l d] +1,
wherein l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
Preferably, a DMRS transmitted based on the symbol index in the first slot structure is generated before or after the cyclic operation is performed.
Preferably, the wireless communication method further comprises at least one of:
transmitting, to a second wireless device, sidelink signals based on the first sidelink slot structure,
receiving, from the second wireless device, sidelink signals based on the first sidelink slot structure, or
performing a blind detection for sidelink signals based on the the first sidelink slot structure.
Preferably, sidelink control information on the control channel of the first sidelink slot structure comprises at least one of an indication of a starting symbol, cyclic shift information associated with a cyclic shift operation performed on the first sidelink slot structure, or an indication of sidelink transmission symbols.
The present disclosure relates to a first wireless device. The first wireless device comprises:
a processor, configured to map a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
Various embodiments may preferably implement the following feature:
Preferably, the processor is further configured to perform any of the aforementioned wireless communication methods.
The present disclosure relates to a computer program product comprising a computer-readable program medium code stored thereupon, the code, when executed by a processor, causing the processor to implement a wireless communication method recited in any one of foregoing methods.
The exemplary embodiments disclosed herein are directed to providing features that will become readily apparent by reference to the following description when taken in conjunction with the accompany drawings. In accordance with various embodiments, exemplary systems, methods, devices and computer program products are disclosed herein. It is understood, however, that these embodiments are presented by way of example and not limitation, and it will be apparent to those of ordinary skill in the art who read the present disclosure that various modifications to the disclosed embodiments can be made while remaining within the scope of the present disclosure.
Thus, the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and/or hierarchy of steps in the methods disclosed herein are merely exemplary approaches. Based upon design preferences, the specific order or hierarchy of steps of the disclosed methods or processes can be re-arranged while remaining within the scope of the present disclosure. Thus, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or acts in a sample order, and the present disclosure is not limited to the specific order or hierarchy presented unless expressly stated otherwise.
The above and other aspects and their implementations are described in greater detail in the drawings, the descriptions, and the claims.
FIGS. 1A, 1B, 2A and 2B show schematic diagrams of slot structures according to embodiments of the present disclosure.
FIG. 3 shows a schematic diagram of a network (architecture) according to an embodiment of the present disclosure.
FIG. 4 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
FIG. 5 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
FIGS. 6A to 6C show schematic diagrams of slot structures according to an  embodiment of the present disclosure.
FIG. 7 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
FIG. 8 shows a schematic diagram of slot structures according to an embodiment of the present disclosure.
FIG. 9 shows an example of a schematic diagram of a wireless terminal according to an embodiment of the present disclosure.
FIG. 10 shows an example of a schematic diagram of a wireless network node according to an embodiment of the present disclosure.
FIG. 11 shows a flowchart of a method according to an embodiment of the present disclosure.
FIGS. 12 and 13 show schematic diagrams of slot structures according to embodiments of the present disclosure.
In an embodiment, the time domain channel structure of SL operation consists of the following:
- a single starting symbol ranging from {0, 1, 2, 3, 4, 5, 6, 7} ,
- a length of symbols ranging from {7, 8, 9, 10, 11, 12, 13, 14} ,
- a PSSCH (physical SL shared channel) DMRS (demodulation reference signal) pattern following the table below:
Table 1: PSSCH DM-RS time-domain location
Figure PCTCN2022122849-appb-000004
Figure PCTCN2022122849-appb-000005
- a PSCCH (physical sidelink control channel) time-frequency configuration:
1) number of symbols {2, 3} ; and
2) number of PRBs {10, 12, 15, 20, 25} .
- a PSCCH DMRS (demodulation reference signal) configuration:
OCC (Orthogonal Cover Code) randomly selected from the list below
Figure PCTCN2022122849-appb-000006
DMRS mapping to RE #1, #5, #9 in each RB of all symbols used as PSCCH with antenna port p=2000.
FIGS. 1A, 1B, 2A and 2B show schematic diagrams of slot structures for 6 to 8 symbols and for 13 symbols according to embodiments of the present disclosure. In FIG. 1A, the slot structures with symbol length ld=6, 7 and 8 are shown, wherein the PSCCH is configured with 2 symbols. In FIG. 1B, the slot structures with symbol length ld=6, 7 and 8 are shown, wherein the PSCCH is configured with 3 symbols.
In FIG. 2A, the slot structures with symbol length ld=13 are shown, wherein the PSCCH is configured with 2 symbols. Note that the slot structures have different numbers of DMRS. Similarly, the slot structures with symbol length ld=13 and different numbers of DMRS are shown in FIG. 2B, wherein the PSCCH is configured with 3 symbols.
FIG. 3 shows a schematic diagram of a network (architecture) according to an  embodiment of the present disclosure. The network shown in FIG. 3 comprises a base station (BS) , a relay (node) (e.g., a header UE) and two UEs UE1 and UE2. For example, the UE1 may be a mobile phone and the UE2 may be a smart gadget (e.g., smart glasses) . As an alternative, the UE1 and/or UE2 may be an internet of things (IoT) device. The UE1 and/or UE2 may communicate with the BS directly or via relay. Based on a SL scheduling received from the BS, the relay, UE1 and UE2 may communicate with each other, where the communication between every two of the relays, UE1 and UE2 are called SL communications. The SL communication may be in the form of unicast, groupcast or broadcast. Furthermore, the UE2 may communicate with the BS/relay via the UE1. That is the UE1 may act as a UE/mobile relay.
In some embodiments, the mapping rule of PSCCH is changed from starting from the first symbol of the PSSCH for a slot structure to starting from a common location to all the starting points configured as illustrated in FIG. 4. In FIG. 4, a slot structure 4A represents a slot structure with a starting point 0 (i.e., starting at the first symbol other than AGC symbol) and a slot structure 4C represents a slot structure with a starting point 3 (i.e., starting at the third symbol other than AGC symbol) . To make the PSCCH appear at the same location for these two starting points (slot structures) , the PSCCH mapping of the slot structure with starting point 0 starts from the symbol 4 (i.e., the symbol with an index 4) . After the PSCCH mapping, the slot structure 4A becomes a slot structure 4B shown in FIG. 4.
In an embodiment of changing the mapping rule of PSCCH for two slot structures, length of symbols excluding the gap symbols in these two slot structures are denoted as ld, 1 and ld, 2, respectively, and a positive difference between the two lengths is denoted as d = ld, 1 -ld, 2. Denote further the starting point of the slot structure of symbol length ld, 2 as ls, 2. In this embodiment, the starting point of PSCCH mapping shall be the symbol d+ ls, 2 (i.e. symbol with the index d+ ls, 2) for the slot structure of a larger symbol length ld, 1 (e.g., slot structure 4A) .
In an embodiment, the rule of changing the mapping rule of PSCCH can be extended to the case of more than two starting points to shift/change the PSCCH starting points of all slot structures to one common location. For example, the common location may be determined to be equal to the PSCCH location of the slot structure with the fewest number of symbols or with a starting point whose symbol index is largest.
In some embodiment, a cyclic shift operation may be performed to one or all of the  symbols of a slot structure with a given starting point to generate another slot structure that has a common PSCCH location as a slot structure with another given starting point. The cyclic shift can be performed before the mapping to physical resources or after the mapping to physical resources. Note that the cyclic shift operation may be applied to PSCCH and one or all of the PSCCH DMRS, the PSSCH, the PSSCH DMRS. In an embodiment, the cyclic shift operation is not applied to the AGC symbol and/or the gap symbol.
In an embodiment of the cyclic shift operation being performed before the mapping to physical resources, the operation is performed as follows:
The modulated PSCCH and/or PSCCH DMRS and/or PSSCH and/or PSSCH DMRS symbols are arranged in sequence to the form of (k, l′) along the allocated frequency range for k and the time domain location for l′.
The symbol sequence at the symbol l'is mapped to a symbol l as per the following rule/formula: (Note that l d herein refers to the length of symbols of the slot structure with a first starting point including the AGC symbol and not including the gap symbol, an example of the symbol length equals to 13 in Fig. 2A and 2B) 
l=(l′+SO) mod l d+floor [ (l′+SO) /l d] .
Alternatively, when the definition of l d is the symbol length not including the AGC symbol or the gap symbol (an example of the symbol length equals to 12 in Fig. 2A and 2B) , the rule/formula can be:
l=[ (l′-1+SO) mod l d] +1.
In the above formulas/rules, SO is a shifting offset. The SO is determined by/based on either a starting point difference between the first starting point and the common starting point or a symbol length difference between the slot structure with the first starting point or the largest symbol length and the slot structure with the fewest number of symbols. In an embodiment, the SO can be equal to the starting point difference or the symbol length difference.
In an embodiment of the cyclic shift operation being performed after the mapping to physical resources, the cyclic shift operation is performed as below.
The modulated PSCCH, PSCCH DMRS, PSSCH and PSSCH DMRS symbols are mapped in sequence to the form of (k, l) along the allocated frequency range for k and the time domain location for l. The cyclic shift operation is performed to each symbol l to generate a slot  structure with symbol l f. The time domain resource allocation of the transmitted slot structure follows the symbol l f. In an embodiment, l d refers to the length of symbols of the slot structure with a first starting point including the AGC symbol and not including the gap symbol (see, e.g., the examples of the symbol length equal to 13 in FIG. 2A and 2B) and l f can be determined as:
l f= (l+SO) mod l d+floor [ (l+SO) /l d] .
In another embodiment, l d may be the symbol length not including the AGC symbol or the gap symbol (see, e.g., the examples of the symbol length equal to 12 in FIG. 2A and 2B) and the formula for determining l f can be:
l f= [ (l-1+SO) mod l d] +1.
The shifting offset SO is determined by either the starting point difference or the symbol length difference and can be equal to the starting point difference or the symbol length difference.
FIG. 5 shows a schematic diagram of slot structures according to an embodiment of the present disclosure. In FIG. 5, the cyclic shift operation is applied on all of the PSCCH, PSCCH DMRS, PSSCH, and PSSCH DMRS of a slot structure 51, to generate a slot structure 52 having a starting point the same with that of a slot structure 53. As shown in FIG. 5, because the cyclic shift operation is applied on all of symbols excluding the AGC symbol or the gap symbol (GP) of the slot structure 51, the symbols 1 to 9 in the slot structure 51 are shifted to symbols 4 to 12 in the slot structure 52 and the symbols 10 to 12 in the slot structure 51 are shifted to symbols 1 to 3 in the slot structure 52. As a result, the  slot structures  52 and 53 have the same starting point.
FIGS. 6A to 6C show schematic diagrams of slot structures according to an embodiment of the present disclosure. In FIGS. 6A to 6C, the cyclic shift operation, if performed, is applied on all of the PSCCH, PSCCH DMRS, PSSCH, and PSSCH DMRS of a slot structure. In FIG. 6A, the cyclic shift operation is applied on a slot structure 61, to generate a slot structure 62 of which the PSCCH starting point is the same with those of  slot structures  63 and 67 having the fewest number of symbols. As shown in FIG. 6A, the symbols 7 to 11 in the slot structure 61 are shifted to the symbols 8 to 12 of the slot structure 62 and the symbol 12 in the slot structure 61 is shifted to the symbol 7 in the slot structure 62. Similarly, in FIG. 6B, the cyclic shift operation is applied on a slot structure 64, to generate a slot structure 65 of which the PSCCH starting point is the same with those of the  slot structures  63 and 67. As shown in FIG. 6B, the symbols 6 to 10 in  the slot structure 64 are shifted to symbols 8 to 12 of the slot structure 65 and the  symbols  11 and 12 in the slot structure 64 are shifted to the  symbols  6 and 7 in the slot structure 65. In FIG. 6C, the cyclic shift operation is applied on a slot structure 66, to generate a slot structure 67 having the same PSCCH starting point as the  slot structures  63 and 67. Specifically, the symbols 5 to 8 in the slot structure 66 are shifted to symbols 8 to 12 of the slot structure 67 and the symbols 9 to 11 in the slot structure 66 are shifted to the symbols 5 to 7 in the slot structure 67. The starting point of the PSCCH for  slot structures  63 and 67 remain the same.
In some embodiments, the cyclic shift operation may be applied to only certain symbols (e.g., symbols in a shifting range) among the one or all of the PSCCH, PSCCH DMRS, PSSCH, PSSCH DMRS symbols.
In an embodiment, for a slot structure with longer symbol length, the number of symbols on which the cyclic shift operation is applied is greater than or equal to 2*d when there is no additional AGC symbol configured, where d is the difference of the symbol lengths or staring points.
In an embodiment, depending on whether the cyclic shift operation is applied prior to the mapping operation or posterior to the mapping operation, one of the following formulae can be applied.
if the cyclic shift operation is applied prior to the mapping operation:
l=(l′+ O) mod l d+floor [ (l′+ O) /l d] , or
l=[ (l′-1+SO) mod l d] +1;
if the cyclic shift operation is applied posterior to the mapping operation:
l f= (l+SO) mod l d+floor [ (l+SO) /l d] ; or
l f= [ (l-1+SO) mod l d] +1.
Note that the definition of l d is based on the number of symbols in the shifting range where the cyclic shift operation is performed.
FIG. 7 shows a schematic diagram of slot structures according to an embodiment of the present disclosure. In FIG. 7, the cyclic shift operation is applied only to the symbols 1 to 6 in the shifting range. Specifically, the symbols (1, 2, 3) in a slot structure 71 are shifted to the symbols (4, 5, 6) in a slot structure 72 and the symbols (4, 5, 6) in the slot structure 71 are shifted to the symbols (1, 2, 3) in the slot structure 72. As a result, the slot structure 72 and the slot structure 73  have the same starting point.
In some embodiment of additional AGC symbols being configured in the slot structure at a starting point, the CS operation shall/is not be applied to the AGC symbols within the same range of symbols as in the above embodiments.
FIG. 8 shows a schematic diagram of slot structures according to an embodiment of the present disclosure. In FIG. 8, the cyclic shift operation is applied only to the symbols (1, 2, 4, 5) in the slot structure 81. Note that the symbol 3 in the slot structure 81 remains unchanged because being the AGC symbol. Under such conditions, the symbols (1, 2) in the slot structure 81 are shifted to the symbols (4, 5) in a slot structure 82 and the symbols (4, 5) in the slot structure 81 are shifted to the symbols (1, 2) in the slot structure 82. As a result, the  slot structures  82 and 83 have the same starting points. Note that the shifting range shall thus not take into account any AGC symbol.
FIG. 12 shows a schematic diagram of slot structures according to an embodiment of the present disclosure. In FIG. 12, the PSCCH symbols in a slot structure 121 are directly mapping to the symbol 4 or the cyclic shift operation is applied to the PSCCH symbols whose starting point is shifted to the symbol 4 making the PSCCH symbols coincide in time domain with the slot structure 123 (see slot structure 122) . In this embodiment, the PSSCH DMRS symbol 1 (for PSSCH) and PSSCH symbols (2, 3) in the slot structure 122 are truncated and not used to carry payload. With the truncation, the slot structure 122 has the same number of symbols to carry payload as the slot structure 123. Thus, the transport block determined (e.g., based on the slot structures 122 and 123) from a MAC layer (entity) could be the same as well. Duplicated PSSCH symbols and/or PSSCH DMRS symbols and/or AGC symbols at the truncated symbol location may still be transmitted.
FIG. 13 shows a schematic diagram of slot structures according to an embodiment of the present disclosure. In FIG. 13, the TB size calculation and transport block determined from the MAC layer (entity) is based on a configured symbol length and starting point. The physical resource mapping of the PSSCH is also based on the configured symbol length and starting point. In this embodiment, the PSCCH symbols are directly mapped to the symbol 4 or the cyclic shift operation is applied to the PSCCH symbols whose starting point is shifted to the symbol 4. There exists therefore a candidate starting point region comprising  symbol indexes  1, 2 and =3 (or  symbols with the  indexes  1, 2 and 3) , see, e.g., slot structure 131. The candidate starting point region may further include the symbol index 0 (the configured starting point herein) . The candidate starting point region comprises a symbol whose symbol index plus 1 equal to the index of the first symbol where PSCCH is mapped over. Whenever channel access procedure is completed with a successful LBT (listen before talk) procedure and/or channel occupancy, the transmission can start from any symbol (actual starting point) within the candidate starting point region apart from the symbol index 0, i.e. the configured starting point. The PSSCH symbols between the configured starting point and the actual starting point (not including the actual starting point) are truncated prior to transmission/punctured in the transmission. The truncating/puncturing herein refers to not transmitting the symbols between the configured starting point and actual starting point.
In some embodiments, the PSCCH of the slot structures with both starting symbols may reserve some indication for starting symbol information and cyclic shift operation information.
In an embodiment, when the common PSCCH for multiple starting point is fixed into one location, some bits in sidelink control information (SCI) 1-Amay be used to indicate the actual starting point or the cyclic shift operation information of the PSCCH, PSSCH, PSSCH DMRS or PSCCH DMRS.
In an embodiment, the SCI bits may also be used to indicate the localized cyclic shift operation (i.e., associated with the cyclic shift operation performed on symbols in the shifting range) or full range cyclic shift operation information (i.e., associated with the cyclic shift operation performed on all of symbols in the slot structure) or an indication of sidelink transmission symbols to determine the transmission block size. The indication of sidelink transmission symbols can refer to whether to take into account the transmission symbol length difference corresponding to the slot structures associated with multiple starting points. When the symbol length difference is taken into account, the indication of sidelink transmission symbols can refer to the average of multiple symbol lengths among the symbol lengths associated with different starting points, the largest symbol length among the symbol lengths associated with different starting points or the smallest symbol length among the symbol lengths associated with different starting points.
In an embodiment, the PSCCH/PSSCH DMRS is generated by using the position information of the DMRS before the cyclic shift operation or directly mapping to a common  location.
In an embodiment, the PSCCH/PSSCH DMRS is generated by using the position information of the DMRS after the cyclic shift operation or directly mapping to a common location.
In an embodiment, the common starting point for the PSCCH mapping may be fixed. The starting points of the PSSCH/PSCCH DMRS or PSSCH itself shall be determined as a configured offest to the common starting point for PSCCH mapping. In an embodiment, for a slot with PSFCH (physical sidelink feedback channel) configured, the cyclic shift operation or directly mapping PSCCH or one of PSSCH, PSSCH DMRS or PSCCH DMRS is not applied. For those slots, only one starting point among the multiple configured starting points is used.
FIG. 9 relates to a schematic diagram of a wireless terminal 90 according to an embodiment of the present disclosure. The wireless terminal 90 may be a user equipment (UE) , a mobile phone, a laptop, a tablet computer, an electronic book or a portable computer system and is not limited herein. The wireless terminal 90 may include a processor 900 such as a microprocessor or Application Specific Integrated Circuit (ASIC) , a storage unit 910 and a communication unit 920. The storage unit 910 may be any data storage device that stores a program code 912, which is accessed and executed by the processor 900. Embodiments of the storage unit 910 include but are not limited to a subscriber identity module (SIM) , read-only memory (ROM) , flash memory, random-access memory (RAM) , hard-disk, and optical data storage device. The communication unit 920 may a transceiver and is used to transmit and receive signals (e.g., messages or packets) according to processing results of the processor 900. In an embodiment, the communication unit 920 transmits and receives the signals via at least one antenna 922 shown in FIG. 9.
In an embodiment, the storage unit 910 and the program code 912 may be omitted and the processor 900 may include a storage unit with stored program code.
The processor 900 may implement any one of the steps in exemplified embodiments on the wireless terminal 90, e.g., by executing the program code 912.
The communication unit 920 may be a transceiver. The communication unit 920 may as an alternative or in addition be combining a transmitting unit and a receiving unit configured to transmit and to receive, respectively, signals to and from a wireless network node (e.g., a base station) .
FIG. 10 relates to a schematic diagram of a wireless network node 100 according to an embodiment of the present disclosure. The wireless network node 100 may be a satellite, a base station (BS) , a network entity, a Mobility Management Entity (MME) , Serving Gateway (S-GW) , Packet Data Network (PDN) Gateway (P-GW) , a radio access network (RAN) node, a next generation RAN (NG-RAN) node, a gNB, an eNB, a gNB central unit (gNB-CU) , a gNB distributed unit (gNB-DU) a data network, a core network or a Radio Network Controller (RNC) , and is not limited herein. In addition, the wireless network node 100 may comprise (perform) at least one network function such as an access and mobility management function (AMF) , a session management function (SMF) , a user place function (UPF) , a policy control function (PCF) , an application function (AF) , etc. The wireless network node 100 may include a processor 1000 such as a microprocessor or ASIC, a storage unit 1010 and a communication unit 1020. The storage unit 1010 may be any data storage device that stores a program code 1012, which is accessed and executed by the processor 1000. Examples of the storage unit 1010 include but are not limited to a SIM, ROM, flash memory, RAM, hard-disk, and optical data storage device. The communication unit 1020 may be a transceiver and is used to transmit and receive signals (e.g., messages or packets) according to processing results of the processor 1000. In an example, the communication unit 1020 transmits and receives the signals via at least one antenna 1022 shown in FIG. 10.
In an embodiment, the storage unit 1010 and the program code 1012 may be omitted. The processor 1000 may include a storage unit with stored program code.
The processor 1000 may implement any steps described in exemplified embodiments on the wireless network node 100, e.g., via executing the program code 1012.
The communication unit 1020 may be a transceiver. The communication unit 1020 may as an alternative or in addition be combining a transmitting unit and a receiving unit configured to transmit and to receive, respectively, signals to and from a wireless terminal (e.g., a user equipment or another wireless network node) .
FIG. 11 shows a flowchart of a method according to an embodiment of the present disclosure. The method shown in FIG. 11 may be used in a first wireless device (e.g. UE) and comprises the following step:
Step 1101: Map a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control  channel of a second sidelink slot structure.
In this embodiment, the first wireless device maps a first control channel (e.g., PSCCH) of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure. After the mapping, the control channels in different slot structures have the same starting point (i.e., common starting point) . The number of blind detections performed by a receiving terminal in the sidelink communications is therefore decreased.
Note that the first control channel may perform the mapping on other slot structure (s) . That is the method may be used in a case with more than 2 slot structures. In an embodiment, the second slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
In an embodiment, the mapping may be performed by shifting the first control channel from the first starting point to the second starting point (see, e.g., FIG. 4) . For example, the first control channel is shifted based on a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point.
In an embodiment, mapping the first control channel of the first sidelink slot structure from the first starting point to the same position as the second starting point corresponding the second control channel of the second sidelink slot structure comprises:
performing a cyclic shift operation on the first control channel.
In an embodiment, the cyclic shift operation may also be performed on at least one of DMRS (s) of the first control channel, shared channel (s) (e.g., PSSCH (s) ) or DMRS (s) of the shared channel (s) .
In an embodiment, the cyclic shift operation is performed before or after mapping symbols of the first sidelink structure to physical resources.
In an embodiment, the cyclic shift operation is not applied to at least one of an automatic gain control symbol or a gap symbol.
In an embodiment of the cyclic shift operation being performed before mapping symbols of the first sidelink slot structure to physical resources. In this embodiment, the cyclic shift operation is performed by:
mapping a symbol at a location l′ in the first sidelink slot structure to a location l based on:
l= (l′+SO) mod l d+floor [ (l′+SO) /l d] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
l= [ (l′-1+SO) mod l d] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
wherein SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
In an embodiment of the cyclic shift operation being performed after mapping symbols of the first sidelink slot structure to physical resources, the cyclic shift operation is performed by:
performing the cyclic shift operation on the mapped first sidelink slot structure, wherein a symbol at a location l in the mapped first sidelink slot structure has a location l f after the cyclic shift operation is performed and:
l f= (l+SO) mod l d+floor [ (l+SO) /l d] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
l f= [ (l-1+SO) mod l d] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
wherein SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
In an embodiment, the cyclic shift operation is applied to symbols within a shifting  range (see, e.g., FIG. 7 or 8) .
In an embodiment, the shifting range starts at a symbol from which the first control channel of the first sidelink slot structure is mapped.
In an embodiment, the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point, wherein there is no additional AGC symbol configured in the first sidelink slot structure.
In an embodiment of the cyclic shift operation being performed before mapping symbols of the first sidelink slot structure to physical resources, the cyclic shift operation is performed by:
mapping a symbol at a location l′ in the shifting range to a location l based on:
l= (l′+SO) mod l d+floor [ (l′+SO) /l d] , or
l= [ (l′-1+SO) mod l d] +1,
where l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
In an embodiment of the cyclic shift operation being performed after mapping symbols of the first sidelink slot structure to physical resources, the cyclic shift operation is performed by:
performing the cyclic shift operation on mapped symbols in the shifting range, wherein a symbol at a location l in shifting range has a location l f after the cyclic shift operation is performed and:
l f= (l+SO) mod l d+floor [ (l′+SO) /l d] , or
l f= [ (l-1+SO) mod l d] +1,
where l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
In an embodiment, a DMRS transmitted based on the symbol index in the first slot structure is generated before or after the cyclic operation is performed.
In an embodiment, the first wireless device may transmit, to a second wireless device, sidelink signals based on the first sidelink slot structure. In this embodiment, the first wireless device is a transmitting side in the sidelink communications.
In an embodiment, the first wireless device performs a blind detection for sidelink signals based on the first sidelink slot structure. In this embodiment, the first wireless device is a receiving side in the sidelink communications.
In an embodiment, the first wireless device receives, from the second wireless device, sidelink signals based on the first sidelink slot structure. In this embodiment, the first wireless device is the receiving side in the sidelink communications.
In an embodiment, the first wireless device may transmit, to a second wireless device, sidelink signals based on the second sidelink slot structure. In this embodiment, the first wireless device is a transmitting side in the sidelink communications.
In an embodiment, the first wireless device performs a blind detection for sidelink signals based on the second sidelink slot structure. In this embodiment, the first wireless device is a receiving side in the sidelink communications.
In an embodiment, the first wireless device receives, from the second wireless device, sidelink signals based on the second sidelink slot structure. In this embodiment, the first wireless device is the receiving side in the sidelink communications.
In an embodiment, SCI on the control channel of the first sidelink slot structure comprises at least one of an indication of a starting symbol, cyclic shift information associated with a cyclic shift operation performed on the first sidelink slot structure, or an indication of sidelink transmission symbols.
While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. Likewise, the various diagrams may depict an example architectural or configuration, which are provided to enable persons of ordinary skill in the art to understand exemplary features and functions of the present disclosure. Such persons would understand, however, that the present  disclosure is not restricted to the illustrated example architectures or configurations, but can be implemented using a variety of alternative architectures and configurations. Additionally, as would be understood by persons of ordinary skill in the art, one or more features of one embodiment can be combined with one or more features of another embodiment described herein. Thus, the breadth and scope of the present disclosure should not be limited by any one of the above-described exemplary embodiments.
It is also understood that any reference to an element herein using a designation such as "first, " "second, " and so forth does not generally limit the quantity or order of those elements. Rather, these designations can be used herein as a convenient means of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element in some manner.
Additionally, a person having ordinary skill in the art would understand that information and signals can be represented using any one of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits and symbols, for example, which may be referenced in the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
A skilled person would further appreciate that any one of the various illustrative logical blocks, units, processors, means, circuits, methods and functions described in connection with the aspects disclosed herein can be implemented by electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two) , firmware, various forms of program or design code incorporating instructions (which can be referred to herein, for convenience, as "software" or a "software unit” ) , or any combination of these techniques.
To clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, units, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software, or a combination of these techniques, depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in various ways for each particular application, but such implementation decisions do  not cause a departure from the scope of the present disclosure. In accordance with various embodiments, a processor, device, component, circuit, structure, machine, unit, etc. can be configured to perform one or more of the functions described herein. The term “configured to” or “configured for” as used herein with respect to a specified operation or function refers to a processor, device, component, circuit, structure, machine, unit, etc. that is physically constructed, programmed and/or arranged to perform the specified operation or function.
Furthermore, a skilled person would understand that various illustrative logical blocks, units, devices, components and circuits described herein can be implemented within or performed by an integrated circuit (IC) that can include a general purpose processor, a digital signal processor (DSP) , an application specific integrated circuit (ASIC) , a field programmable gate array (FPGA) or other programmable logic device, or any combination thereof. The logical blocks, units, and circuits can further include antennas and/or transceivers to communicate with various components within the network or within the device. A general purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other suitable configuration to perform the functions described herein. If implemented in software, the functions can be stored as one or more instructions or code on a computer-readable medium. Thus, the steps of a method or algorithm disclosed herein can be implemented as software stored on a computer-readable medium.
Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program or code from one place to another. A storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer.
In this document, the term "unit" as used herein, refers to software, firmware, hardware, and any combination of these elements for performing the associated functions described herein. Additionally, for purpose of discussion, the various units are described as discrete units; however,  as would be apparent to one of ordinary skill in the art, two or more units may be combined to form a single unit that performs the associated functions according embodiments of the present disclosure.
Additionally, memory or other storage, as well as communication components, may be employed in embodiments of the present disclosure. It will be appreciated that, for clarity purposes, the above description has described embodiments of the present disclosure with reference to different functional units and processors. However, it will be apparent that any suitable distribution of functionality between different functional units, processing logic elements or domains may be used without detracting from the present disclosure. For example, functionality illustrated to be performed by separate processing logic elements, or controllers, may be performed by the same processing logic element, or controller. Hence, references to specific functional units are only references to a suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization.
Various modifications to the implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other implementations without departing from the scope of the claims. Thus, the disclosure is not intended to be limited to the implementations shown herein, but is to be accorded the widest scope consistent with the novel features and principles disclosed herein, as recited in the claims below.

Claims (22)

  1. A wireless communication method for use in a first wireless device, the method comprising:
    mapping a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
  2. The wireless communication method of claim 1, wherein the first control channel is shifted from the first starting point to the second starting point.
  3. The wireless communication method of claim 1 or 2, wherein the first control channel is shifted based on a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point.
  4. The wireless communication method of any of claims 1 to 3, wherein the second sidelink slot structure is a sidelink slot structure having the minimum number of symbols within a plurality of sidelink slot structures or having a starting point of the largest symbol index.
  5. The wireless communication method of any of claims 1 to 4, wherein mapping the first control channel of the first sidelink slot structure from the first starting point to the same position as the second starting point corresponding the second control channel of the second sidelink slot structure comprises:
    performing a cyclic shift operation on the first control channel.
  6. The wireless communication method of claim 5, further comprising:
    performing the cyclic shift operation on at least one of one or more demodulation reference signals, DMRSs, of the first control channel, one or more shared channels of the first sidelink slot structure or one or more DMRSs of the one or  more shared channels.
  7. The wireless communication method of claim 5 or 6, wherein the cyclic shift operation is performed before or after mapping symbols of the first sidelink structure to physical resources.
  8. The wireless communication method of any of claims 5 to 7, wherein the cyclic shift operation is not applied to at least one of an automatic gain control symbol or a gap symbol.
  9. The wireless communication method of any of claims 5 to 8, wherein the cyclic shift operation is performed before mapping symbols of the first sidelink slot structure to physical resources,
    wherein the cyclic shift operation is performed by:
    mapping a symbol at a location l′ in the first sidelink slot structure to a location l based on:
    l= (l′+SO) mod l d+floor [ (l′+SO) /l d] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
    l= [ (l′-1+SO) mod l d] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
    wherein SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  10. The wireless communication method of any of claims 5 to 8, wherein the cyclic shift operation is performed after mapping symbols of the first sidelink slot structure to  physical resources,
    wherein the cyclic shift operation is performed by:
    performing the cyclic shift operation on the mapped first sidelink slot structure, wherein a symbol at a location l in the mapped first sidelink slot structure has a location l f after the cyclic shift operation is performed and:
    l f= (l+SO) mod l d+floor [ (l+SO) /l d] , where l d is the length of symbols of the first sidelink slot structure including an automatic gain control symbol and excluding a gap symbol, or
    l f= [ (l-1+SO) mod l d] +1, where l d is the length of symbols of the first sidelink slot structure excluding an automatic gain control symbol and a gap symbol,
    wherein SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  11. The wireless communication method of any of claims 5 to 8, wherein the cyclic shift operation is applied to symbols within a shifting range.
  12. The wireless communication method of claim 11, wherein the shifting range starts at a symbol from which the first control channel of the first sidelink slot structure is mapped.
  13. The wireless communication method of claim 11 or 12, wherein the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length of the first sidelink slot structure and a second symbol length of the second sidelink slot structure or a starting point difference between the first starting point and the second starting point, wherein there is no additional AGC symbol configured in the first sidelink slot structure.
  14. The wireless communication method of claim 11 or 12, wherein the number of symbols in the shifting range is greater than or equal to 2 times a length difference between a first symbol length excluding the additional automatic gain control symbols of the first sidelink slot structure and a second symbol length of the second sidelink slot structure, wherein an additional automatic gain control symbol is configured in the first sidelink slot structure.
  15. The wireless communication method of any of claims 11 to 14, wherein the cyclic shift operation is performed before mapping symbols of the first sidelink slot structure to physical resources,
    wherein the cyclic shift operation is performed by:
    mapping a symbol at a location l′ in the shifting range to a location l based on:
    l= (l′+SO) mod l d+floor [ (l′+SO) /l d] , or
    l= [ (l′-1+SO) mod l d] +1,
    where l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  16. The wireless communication method of any of claims 11 to 14, wherein the cyclic shift operation is performed after mapping symbols of the first sidelink slot structure to physical resources,
    wherein the cyclic shift operation is performed by:
    performing the cyclic shift operation on mapped symbols in the shifting range, wherein a symbol at a location l in shifting range has a location l f after the cyclic shift operation is performed and:
    l f= (l+SO) mod l d+floor [ (l′+SO) /l d] , or
    l f= [ (l-1+SO) mod l d] +1,
    where l d is determined based on the number of symbols in the shifting range and SO is a shifting offset which is determined based on a difference between the first starting point and the second starting point or between a first symbol length of the first sidelink slot structure and the second sidelink slot structure.
  17. The wireless communication method of any of claims 5 to 16, wherein a DMRS transmitted based on the symbol index in the first slot structure is generated before or after the cyclic operation is performed.
  18. The wireless communication method of any of claims 1 to 17, further comprising at least one of:
    transmitting, to a second wireless device, sidelink signals based on the first sidelink slot structure,
    receiving, from the second wireless device, sidelink signals based on the first sidelink slot structure, or
    performing a blind detection for sidelink signals based on the the first sidelink slot structure.
  19. The wireless communication method any of claims 1 to 18, wherein sidelink control information on the control channel of the first sidelink slot structure comprises at least one of an indication of a starting symbol, cyclic shift information associated with a cyclic shift operation performed on the first sidelink slot structure, or an indication of sidelink transmission symbols.
  20. A first wireless device, comprising:
    a processor, configured to map a first control channel of a first sidelink slot structure from a first starting point to the same position as a second starting point corresponding a second control channel of a second sidelink slot structure.
  21. The first wireless device of claim 20, wherein the processor is further configured to perform the wireless communication method of any of claims 2 to 19.
  22. A computer program product comprising a computer-readable program medium code stored thereupon, the code, when executed by a processor, causing the processor to implement a wireless communication method recited in any one of claims 1 to 19.
PCT/CN2022/122849 2022-09-29 2022-09-29 Method and apparatus for sidelink channel structure WO2024065488A1 (en)

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US20200053528A1 (en) * 2018-08-10 2020-02-13 Mediatek Inc. Multiplexing of physical sidelink control channel (pscch) and physical sidelink shared channel (pssch)
US20220061041A1 (en) * 2019-04-03 2022-02-24 Mediatek Singapore Pte. Ltd. Two-stage sidelink control information for sidelink communications
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