WO2024063161A1 - Through electrode, structure using same, and three-dimensional laminate structure - Google Patents

Through electrode, structure using same, and three-dimensional laminate structure Download PDF

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Publication number
WO2024063161A1
WO2024063161A1 PCT/JP2023/034546 JP2023034546W WO2024063161A1 WO 2024063161 A1 WO2024063161 A1 WO 2024063161A1 JP 2023034546 W JP2023034546 W JP 2023034546W WO 2024063161 A1 WO2024063161 A1 WO 2024063161A1
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Prior art keywords
electrode
interposer
circuit board
electrodes
semiconductor chip
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PCT/JP2023/034546
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French (fr)
Japanese (ja)
Inventor
克弥 菊地
佑樹 荒賀
直也 渡辺
真久 藤野
ウェイ 馮
博 仲川
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国立研究開発法人産業技術総合研究所
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Publication of WO2024063161A1 publication Critical patent/WO2024063161A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details

Definitions

  • the present invention relates to a through electrode, a structure using the same, and a three-dimensional laminated structure.
  • TSVs Through silicon vias
  • Through electrodes are used to electrically connect three-dimensionally stacked devices such as logic, memory, sensors, actuators, etc. (see, for example, Patent Document 1).
  • the present invention has been made in view of the above circumstances, and its purpose is to provide a through electrode, a structure using the same, and a three-dimensional laminated structure that can improve heat dissipation performance. .
  • the first aspect of the present invention is a through electrode that penetrates a support, the support having a through hole formed therein that penetrates between a first surface and a second surface, the through electrode having a thermal conductor that connects between the first surface and the second surface, and a superconductor that connects between the first surface and the second surface, the thermal conductor and the superconductor being formed in contact with each other inside the through hole.
  • a second aspect of the present invention is that the superconductor is a substance that exhibits superconductivity at a temperature of 4.2K or lower, and the thermal conductor is a substance that exhibits normal conductivity at a temperature of 4.2K or lower. This is a characteristic feature of the first aspect of the through electrode.
  • a third aspect of the present invention is the through electrode according to the first or second aspect, wherein the thermal conductor is copper.
  • a fourth aspect of the present invention is a structure characterized by having the through electrode according to any one of the first to third aspects and the support body.
  • the support body is made of silicon (Si), and a silicon oxide film is formed between the silicon (Si) and the through electrode on the inner wall surface of the through hole.
  • the structure according to the fourth aspect wherein the silicon oxide film has a thickness of 10 nm or less.
  • a sixth aspect of the present invention is the structure according to the fourth or fifth aspect, wherein the through electrode protrudes from at least one of the first surface and the second surface of the support. It is the body.
  • a seventh aspect of the present invention is the structure according to any one of the fourth to sixth aspects, further comprising a semiconductor chip, the through electrode being used for connection to the semiconductor chip.
  • An eighth aspect of the present invention is the structure according to the seventh aspect, characterized in that the semiconductor chip is a quantum bit chip.
  • a ninth aspect of the present invention is the structure according to the seventh or eighth aspect, characterized in that the through electrode protrudes from the support and is directly connected to the semiconductor chip.
  • a tenth aspect of the present invention is the structure according to any one of the seventh to ninth aspects, characterized in that the semiconductor chip operates in a vacuum environment.
  • An eleventh aspect of the present invention is a three-dimensional laminated structure characterized in that two or more of the structures according to any one of the fourth to tenth aspects are laminated.
  • a twelfth aspect of the present invention is the eleventh aspect, wherein the three-dimensional laminated structure includes a circuit board including a cooling surface and an interposer, and the circuit board and the interposer each have the through electrode. It is a three-dimensional laminated structure of an aspect.
  • the through electrode can perform heat transfer and superconductivity between the first surface and the second surface of the support using a thermal conductor and a superconductor, respectively.
  • a thermal conductor and a superconductor respectively.
  • the thermal conductor and the superconductor are formed in contact with each other inside the through hole, heat transfer is mainly performed by the thermal conductor, and electricity supply is mainly performed by the superconductor. Current flow through the thermal conductor is suppressed, and heat transfer through the superconductor is also suppressed.
  • the second aspect of the present invention it is useful when it is necessary to use it in an extremely low temperature environment of 4.2K or lower.
  • heat transfer performance can be improved.
  • heat transfer and superconductivity between the first surface and the second surface of the support can be performed by the thermal conductor and superconductor of the through electrode, respectively.
  • the thermal conductor and the superconductor are formed in contact with each other inside the through hole, heat transfer is mainly performed by the thermal conductor, and electricity supply is mainly performed by the superconductor. Current flow through the thermal conductor is suppressed, and heat transfer through the superconductor is also suppressed.
  • processing techniques for silicon (Si) substrates can be applied, which facilitates high-precision processing. Since silicon has a low heat transfer coefficient, heat transfer performance can be improved by using a through electrode. Since the thickness of the silicon oxide film on the inner wall surface of the through hole is 10 nm or less, a step of forming a silicon oxide film such as thermal oxidation is not necessary. According to the sixth aspect of the present invention, the step of superconductively connecting the through electrode protruding from the support with a superconducting device or the like outside the support becomes easy.
  • a through electrode having a thermal conductor and a superconductor can be used for connection with a semiconductor chip.
  • the eighth aspect of the present invention when a quantum bit chip is used as a semiconductor chip, it is possible to operate the quantum bit chip more stably.
  • the process of superconductively connecting the through electrode protruding from the support to the semiconductor chip is facilitated.
  • the heat dissipation performance can be improved.
  • high density can be achieved by stacking integrated circuits using through electrodes.
  • heat from a device such as a semiconductor chip can be efficiently transferred to the cooling surface of the circuit board via the interposer and the through electrode of the circuit board.
  • FIG. 3 is a cross-sectional view showing an example of a through electrode.
  • 3 is a cross-sectional view of a through electrode taken along line III-III in FIG. 2.
  • FIG. 2 is a plan view showing an example of the arrangement of through electrodes with respect to an interposer.
  • FIG. 2 is a cross-sectional view showing an example of a through electrode directly connected to a semiconductor chip. It is a figure showing an example of heat distribution in an example. It is a figure which shows an example of heat distribution in a comparative example. It is a graph showing the thermal conductivity of Cu, Si, and Al at extremely low temperatures.
  • FIG. 1 shows an example of a three-dimensional laminated structure.
  • FIG. 2 shows an example of a through electrode.
  • FIG. 3 shows a cross section of the through electrode taken along line III-III in FIG. 2.
  • the three-dimensional stacked structure 10 includes, for example, a semiconductor chip 1, an interposer 2 including a through electrode 21, and a circuit board 3 including a through electrode 31. Bumps 4 are formed between the semiconductor chip 1 and the through electrodes 21 of the interposer 2. A bump 5 is formed between the through electrode 21 of the interposer 2 and the through electrode 31 of the circuit board 3.
  • the interposer 2 and the circuit board 3 are examples of structures having through electrodes 21 and 31 and supports 20 and 30, respectively. Therefore, the three-dimensional structure 10 includes two or more structures stacked together.
  • the semiconductor chip 1 is a chip whose substrate material is a semiconductor such as silicon, for example, like a normal semiconductor chip.
  • the semiconductor chip 1 may be a quantum bit chip.
  • a quantum bit chip is a chip equipped with a quantum bit. Examples of the quantum bit include, but are not limited to, magnetic flux quantum bits, transmon type quantum bits, and the like. Examples of quantum bit chips include, but are not limited to, circuit-type or annealing-type quantum computers.
  • quantum bits are extremely unstable and easily affected by noise, in order to make them uniform and stable, it is necessary to place them in an extremely low temperature environment of, for example, about 20 mK.
  • the quantum bit chip can be operated more stably.
  • one semiconductor chip 1 is mounted on a circuit board 3 via an interposer 2.
  • a plurality of semiconductor chips 1 may be mounted along the surface of the circuit board 3.
  • a plurality of semiconductor chips 1 may be mounted on one circuit board 3 via one interposer 2.
  • a plurality of interposers 2 may be used for one circuit board 3.
  • One semiconductor chip 1 may be mounted on one interposer 2.
  • a plurality of semiconductor chips 1 may be mounted on one interposer 2.
  • the interposer 2 only needs to have the through electrode 21 in the through hole 25 that penetrates at least between the first surface 26 and the second surface 27 of the support body 20.
  • the support 20 is preferably a semiconductor substrate made of silicon or the like.
  • the through electrode 21 includes a thermal conductor 22 that communicates between a first surface 26 and a second surface 27 , and a superconductor 23 that communicates between the first surface 26 and second surface 27 . has. That is, the thermal conductor 22 and the superconductor 23 included in the through electrode 21 are connected to each other when the member is provided on the first surface 26 and the second surface 27 of the support 20. It is formed. Inside the through hole 25, the thermal conductor 22 and the superconductor 23 are formed in contact with each other. In the example shown in FIG.
  • the thermal conductor 22 is formed to surround the outer periphery of the superconductor 23.
  • the superconductor 23 may be formed to surround the outer periphery of the thermal conductor 22. Further, the thermal conductor 22 and the superconductor 23 may be arranged facing each other.
  • the thermal conductor 22 transfers heat between the first surface 26 and the second surface 27, and the superconductor 23 can exhibit superconductivity. Since the thermal conductor 22 and the superconductor 23 are formed in contact with each other inside the through hole 25, the thermal resistance or electrical resistance between the thermal conductor 22 and the superconductor 23 is sufficiently small. This suppresses current flow through the thermal conductor 22 and heat transfer through the superconductor 23.
  • interposer 2 In addition to the through electrodes 21, active elements such as logic, memory, sensors, actuators, etc. may be formed in the interposer 2.
  • the interposer 2 in this case should also be called an interposer chip.
  • the interposer 2 of this embodiment when the support body 20 is made of silicon, it is different from a conventional interposer in which wiring is formed on a resin substrate.
  • the interposer 2 can include a plurality of through electrodes 21.
  • at least one of the plurality of through electrodes 21 is configured to transmit and receive signals to and from the semiconductor chip 1 .
  • FIG. 4 shows an example of the arrangement of the through electrodes 21 with respect to the interposer 2.
  • FIG. 1 shows an example in which one layer of interposer 2 is placed between a semiconductor chip 1 and a circuit board 3.
  • two or more layers of interposers 2 may be arranged between the semiconductor chip 1 and the circuit board 3.
  • the circuit board 3 only needs to have the through electrode 31 in the through hole 35 that penetrates at least between the first surface 36 and the second surface 37 of the support body 30.
  • the arrangement of the through electrodes 31 with respect to the circuit board 3 may be the same as the arrangement of the through electrodes 21 with respect to the interposer 2.
  • the support 30 is preferably a semiconductor substrate made of silicon or the like.
  • the through electrode 31 includes a thermal conductor 32 that communicates between a first surface 36 and a second surface 37, and a superconductor 33 that communicates between the first surface 36 and second surface 37. has. That is, the thermal conductor 32 and the superconductor 33 included in the through electrode 31 are formed so that they can be connected to the member when the member is provided on the first surface 36 and the second surface 37, respectively.
  • a thermal conductor 32 and a superconductor 33 are formed in contact with each other.
  • the thermal conductor 32 is formed to surround the outer periphery of the superconductor 33.
  • the superconductor 33 may be formed to surround the outer periphery of the thermal conductor 32. Further, the thermal conductor 32 and the superconductor 33 may be arranged facing each other.
  • the circuit board 3 has the through electrode 31 including the thermal conductor 32 and the superconductor 33, the thermal conductor 32 transfers heat between the first surface 36 and the second surface 37, and The body 33 is capable of superconducting. Since the thermal conductor 32 and the superconductor 33 are formed in contact with each other inside the through hole 35, the thermal resistance or electrical resistance between the thermal conductor 32 and the superconductor 33 is sufficiently small. This suppresses current flow through the thermal conductor 32 and heat transfer through the superconductor 33.
  • the circuit board 3 has a cooling surface 6 as a heat radiation surface.
  • the cooling surface 6 may be arranged, for example, on the surface of the circuit board 3 opposite to the side on which the interposer 2 is mounted (the first surface 36 in FIG. 2).
  • the circuit board 3 may be a mounting board that supports the semiconductor chip 1 via the interposer 2 and is used for mounting the semiconductor chip 1.
  • the circuit board 3 may also include wiring, etc., although not particularly shown.
  • the circuit board 3 in this case is also called a wiring board or a package board.
  • the material is different from that of a conventional wiring board in which wiring is formed on a resin substrate.
  • the circuit board 3 can include a plurality of through electrodes 31.
  • the wiring of the circuit board 3 may be formed on the surface of the circuit board 3 on which the interposer 2 is mounted (the second surface 37 in FIG. 2). In this case, the wiring of the circuit board 3 is connected to the through electrode 21 of the interposer 2 via the bump 5.
  • the through electrodes 31 of the circuit board 3 are connected to the through electrodes 21 of the interposer 2 via bumps 5.
  • the through electrodes 31 of the circuit board 3 may not play a role in transmitting and receiving signals to and from the semiconductor chip 1, but may only play a role in transmitting heat to the cooling surface 6.
  • the through electrode 31 of the circuit board 3 may be formed only from the thermal conductor 32 without the superconductor 33. That is, in the three-dimensional laminated structure 10, the interposer 2 has a thermal conductor 22 and a superconductor 23 formed in contact with each other, and the circuit board 3 does not have a superconductor 33. Good too.
  • the through electrode 31 includes a thermal conductor 32 and a superconductor 33. Therefore, the thermal conductor 32 can play the role of transmitting heat to the cooling surface 6, and the superconductor 33 can play the role of transmitting and receiving signals with the semiconductor chip 1.
  • the circuit board 3 includes a plurality of through electrodes 31, at least one of the plurality of through electrodes 31 can be configured to transmit and receive signals with the semiconductor chip 1.
  • the thermal conductor 22 of the through electrodes 21 is made of a material with a higher thermal conductivity than the support 20 of the interposer 2.
  • the thermal conductor 32 of the through electrodes 31 is made of a material with a higher thermal conductivity than the support 30 of the circuit board 3.
  • the thermal conductors 22 and 32 of the through electrodes 21 and 31 can be made of a metal material such as copper, tungsten, aluminum, polysilicon, etc., for example. Among these materials, it is preferable to use copper as the thermal conductors 22, 32.
  • the through electrodes 21 and 31 are referred to as through silicon vias (TSV).
  • the superconductors 23 and 33 of the through electrodes 21 and 31 include tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), niobium (Nb), indium (In), and aluminum (Al). If it is necessary to use the semiconductor chip 1 in an extremely low temperature environment of 4.2K or less, the superconductors 23, 33 of the through electrodes 21, 31 must be a material that exhibits superconductivity at a temperature of 4.2K or less. preferable. That is, it is preferable that the superconducting transition temperature of the material constituting the superconductors 23 and 33 is 4.2K or less.
  • a barrier metal may be formed on the inner wall surfaces of the through holes 25 and 35 around the through electrodes 21 and 31.
  • the barrier metal include Ti, TiN, TaN, Ta, etc., which are exemplified as the barrier layer in Patent Document 1.
  • the superconductors 23 and 33 may also serve as barrier metals. As shown in FIGS. 2 and 3, superconductors 23 and 33 are formed in contact with the inner wall surfaces of through holes 25 and 35, and thermal conductors 22 and 32 are formed inside the superconductors 23 and 33. Good too.
  • An insulating film may be formed between the supports 20 and 30 of the interposer 2 or the circuit board 3 and the through electrodes 21 and 31.
  • an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a resin film is used.
  • the silicon oxide film may be a natural oxide film having a thickness of 10 nm or less.
  • the insulating film between the supports 20, 30 and the through electrodes 21, 31 is a resin film, examples thereof include Parylene (registered trademark) of Japan Parylene LLC, a polymer of paraxylylene, etc. It is not limited.
  • the thermal conductors 22 and 32 of the through electrodes 21 and 31 play the role of transmitting heat
  • the superconductors 23 and 33 play the role of transmitting and receiving signals with the semiconductor chip 1
  • the thermal conductors 22 and 32 play a role of 4.2K. It is preferable that the material exhibits normal conductivity at a temperature below. As a result, when it is necessary to use the semiconductor chip 1 in an extremely low temperature environment of 4.2K or less, the thermal conductors 22 and 32 can play the role of exclusively transmitting heat without playing the role of sending and receiving signals. can.
  • the diameter of the through electrodes 21 and 31 is not limited, but is, for example, 1 ⁇ m to 100 ⁇ m. Further, the pitch between the through electrodes 21 and 31 is not limited, but is set to be twice or more the diameter of the through electrodes 21 and 31, for example.
  • the semiconductor chip 1 is a quantum bit chip
  • the through electrodes 21 and 31, which are responsible for exchanging signals with the active elements of the interposer 2 may be formed closely. In this case, the diameter and pitch of the through electrodes 21 and 31 tend to become smaller. Further, when the through electrodes 21 and 31 are connected to a power source, the diameter and pitch of the through electrodes 21 and 31 tend to become larger.
  • the length of the through electrodes 21, 31 in the thickness direction of the supports 20, 30 is not limited, but is, for example, about 20 ⁇ m to 600 ⁇ m.
  • the first surfaces 26, 36 and the second surfaces 27, 37 of the supports 20, 30 may be two surfaces facing each other in the thickness direction of the supports 20, 30, but are not limited to this. not.
  • the first surface 26, 36 or the second surface 27, 37 is not limited to a flat surface, and may have a curved surface, an uneven surface, a device, etc.
  • a heat dissipating metal layer may be formed on the cooling surface 6.
  • the heat dissipation metal layer can be treated as being included in the cooling surface 6.
  • the material of the heat dissipation metal layer is not limited, but it can be made of metal materials such as copper, tungsten, aluminum, and polysilicon. Among these materials, it is preferable to form the heat dissipation metal layer from copper.
  • the heat dissipation metal layer is made of the same metal material as the heat conductor 32 of the through electrode 31, the heat dissipation metal layer of the cooling surface 6 and the heat conductor 32 can be easily bonded, and the heat dissipation characteristics can be improved.
  • the semiconductor chip 1 Since the three-dimensional stacked structure 10 of this embodiment mounts a quantum bit chip as the semiconductor chip 1, the semiconductor chip 1 is used at extremely low temperatures and in a vacuum environment during operation.
  • the three-dimensional laminated structure 10 is used, for example, in an extremely low temperature environment of 4.2K or lower. Furthermore, the three-dimensional laminated structure 10 is used, for example, in a vacuum environment of 10 ⁇ 2 Pa or less. In such a vacuum environment, heat dissipation performance through air is poor unlike in an air atmosphere, so it is useful to improve heat dissipation performance by providing through electrodes 31 including thermal conductors 32 on circuit board 3. According to the three-dimensional laminated structure 10, heat from the semiconductor chip 1 can be efficiently transferred to the cooling surface 6 of the circuit board 3 via the interposer 2 and the through electrodes 21, 31 of the circuit board 3. .
  • bumps 4 and 5 There is no limitation on the material of the bumps 4 and 5, but examples include gold (Au), copper (Cu), silver (Ag), nickel (Ni), or solder-based materials such as Sn-Ag-Cu and Sn-Bi. , Au-Sn, Sn-Pb, etc.
  • Au gold
  • Cu copper
  • Ag silver
  • Ni nickel
  • solder-based materials such as Sn-Ag-Cu and Sn-Bi. , Au-Sn, Sn-Pb, etc.
  • bumps 4 are used between the semiconductor chip 1 and the interposer 2
  • bumps 5 are used between the interposer 2 and the circuit board 3.
  • Bumps may also be used.
  • FIG. 5 is a cross-sectional view showing an example of the through electrode 21 that is directly connected to the semiconductor chip 1.
  • the through electrodes 21 of the interposer 2 may protrude from the support body 20 and be directly connected to the semiconductor chip 1.
  • the protrusion 24 of the through electrode 21 functions as the bump 4, the bump 4 between the semiconductor chip 1 and the interposer 2 can be omitted.
  • the protrusion 24 of the through electrode 21 is not limited to the surface of the interposer 2 on the semiconductor chip 1 side, but may be formed on the surface of the interposer 2 on the side remote from the semiconductor chip 1. In this way, the protrusion 24 of the through electrode 21 may be formed on at least one surface of the supports 20 and 30 of the interposer 2 or the circuit board 3. Since the through electrodes 21, 31 protrude from at least one of the first surfaces 26, 36 or the second surfaces 27, 37 of the supports 20, 30, the through electrodes 21, 31 are This simplifies the process of making superconducting connections with external superconducting devices.
  • the bumps 5 can be omitted.
  • the through electrodes 21 of the interposer 2 and the through electrodes 31 of the circuit board 3 may be directly joined.
  • the through electrodes 21 protruding from the support body 20 of the interposer 2 may be joined to the wiring on the circuit board 3 side.
  • the structure of the through electrode 31 of the circuit board 3 may have a protruding shape similar to the structure of the through electrode 21 shown in FIG. It may be connected to the wiring.
  • a device such as a semiconductor chip may be a device that operates at a temperature higher than cryogenic temperatures.
  • Devices such as semiconductor chips can be mounted not only on the three-dimensional stacked structure 10 having the interposer 2 and the circuit board 3 but also on the structure having the through electrodes of the embodiment.
  • the through electrodes 21 and 31 shown in FIGS. 1 and 2 may be applied to structures other than the interposer 2 and the circuit board 3.
  • the through electrodes 21 shown in FIGS. 3 to 5 may be applied to structures other than the interposer 2.
  • FEM Finite Element Method
  • the semiconductor chip 1 is a quantum bit chip
  • the semiconductor chip 1, the support 20 of the interposer 2, and the support 30 of the circuit board 3 are made of silicon with a thickness of 400 ⁇ m.
  • the thermal conductors 22 and 32 and the bumps 4 and 5 are made of copper (thermal conductivity 0.530 W/mK).
  • the superconductors 23 and 33 of the through electrodes 21 and 31 are made of TiN, TaN, or the like.
  • the supports 20 and 30 are squares with one side of 1 mm (ie, 1000 ⁇ m).
  • five through electrodes 21 were arranged at five locations, one at the center of the square and four midpoints between the center and the apex of the square.
  • the through electrodes 31 of the circuit board 3 were similarly arranged at five locations.
  • the diameter of the through electrodes 21 and 31 was 50 ⁇ m.
  • the pitch between adjacent through electrodes 21 and 31 is approximately 353 ⁇ m, which is equal to the length of a diagonal line of a square whose sides are 250 ⁇ m.
  • the length (height in the stacking direction) of the through electrodes 21 and 31 is equal to the thickness of the supports 20 and 30, which is 400 ⁇ m.
  • the bumps 4 and 5 are located at positions overlapping with the through electrodes 21 and 31.
  • the diameters of the bumps 4 and 5 may be approximately the same as the diameters of the through electrodes 21 and 31 so that the bumps 4 and 5 are in contact with the thermal conductors 22 and 32 and the superconductors 23 and 33 of the through electrodes 21 and 31.
  • the height of the bumps 4 and 5 is, for example, 4 ⁇ m.
  • a through electrode was used that did not have a two-layer structure of thermal conductors 22, 32 and superconductors 23, 33, and in which through electrodes 21, 31 and bumps 4, 5 were formed only from aluminum. was carried out in the same manner as in the example.
  • the semiconductor chip 1 of the comparative example is also a quantum bit chip, and the semiconductor chip 1, the support 20 of the interposer 2, and the support 30 of the circuit board 3 are made of silicon with a thickness of 400 ⁇ m.
  • Figure 6 shows the heat distribution in the embodiment.
  • Figure 6 shows the heat distribution 1A of the quantum bit chip, the heat distribution 2A of the interposer, the heat distribution 3A of the circuit board, the heat distribution 4A of the heat generating surface, and the heat distribution 5A of the bumps between the interposer and the circuit board in the structure of the embodiment.
  • FIG. 7 is a diagram showing the heat distribution of a comparative example.
  • FIG. 7 shows the thermal distribution of the quantum bit chip 1B, the thermal distribution of the interposer 2B, the thermal distribution of the circuit board 3B, the thermal distribution of the heat generating surface 4B, and the thermal distribution of the bump between the interposer and the circuit board in the structure of the comparative example. 5B is shown.
  • the surface opposite to the side on which the interposer is mounted on the circuit board is the cooling surface, and the temperature of the cooling surface is 10.0 mK in both Examples and Comparative Examples.
  • the interposer has a heat generating surface on the side on which the quantum bit chip is mounted. The amount of heat generated by the interposer is, for example, 1.56 nW/mm 2 .
  • FIG. 8 is a graph showing the thermal conductivity (W/mK) of copper (Cu), silicon (Si), and aluminum (Al) at extremely low temperatures.
  • Al has a critical temperature (superconducting transition temperature) of about 1.2 K and exhibits superconductivity at extremely low temperatures. When Al undergoes a superconducting transition, its thermal conductivity decreases significantly. It can be seen that silicon also has a lower thermal conductivity than copper.
  • the maximum temperature of the thermal distribution 1A of the quantum bit chip was 14.3 mK
  • the maximum temperature of the thermal distribution 1B of the quantum bit chip was 38.9 mK. From this, it can be seen that the comparative example has a lower effect of reducing the temperature of the quantum bit chip than the example.
  • the entire heat distribution 3A of the circuit board maintained a temperature of 10.5 mK or less
  • the maximum temperature of the heat distribution 3B of the circuit board was 16.4 to 19.6 mK. It was within the range of
  • the heat distribution 2B of the interposer in the comparative example was partially within the range of 32.4 to 35.7 mK, but almost all of the interposer and all of the quantum bit chips were within the range of 35.7 to 38.9 mK. It became inside.
  • the heat distribution 4A of the heat generating surface of the example was within the range of 10.2 to 14.2 mK, whereas the heat distribution 4B of the heat generating surface of the comparative example was within the range of 38.0 to 38.8 mK. there were.
  • heat conduction from the heat generating surface of the interposer to the quantum bit chip cannot be suppressed.
  • the heat from the heat generating surface of the interposer is more actively conducted to the cooling surface of the circuit board, and the temperature of the quantum bit chip is reduced.
  • the maximum temperature of the quantum bit chip is 14.2 mK, so it is possible to achieve the temperature below 20 mK required for stable operation of the quantum bit chip. As described above, according to the example, the maximum temperature of the quantum bit chip can be significantly reduced compared to the comparative example.

Abstract

A through electrode penetrating a support including a through-hole penetrating between a first surface and a second surface, the through electrode including a heat conductor communicating between the first surface and the second surface, and a superconductor communicating between the first surface and the second surface, wherein, inside the through-hole, the through electrode is formed by the heat conductor and the superconductor in contact with each other.

Description

貫通電極、これを用いた構造体及び3次元積層構造体Through electrode, structure using the same, and three-dimensional laminated structure
 本発明は、貫通電極、これを用いた構造体及び3次元積層構造体に関する。
 本願は、2022年9月22日に、日本に出願された特願2022-151961号に基づき優先権を主張し、その内容をここに援用する。
The present invention relates to a through electrode, a structure using the same, and a three-dimensional laminated structure.
This application claims priority based on Japanese Patent Application No. 2022-151961 filed in Japan on September 22, 2022, the contents of which are incorporated herein.
 電子デバイスを相互接続する手法として、3次元実装技術が注目を浴びている。シリコン貫通電極(TSV)等の貫通電極は、3次元実装を成し遂げるための技術の一つである。ロジック、メモリ、センサ、アクチュエータ等の3次元に積層されたデバイスを電気的に接続するために貫通電極が使用されている(例えば特許文献1参照)。 Three-dimensional packaging technology is attracting attention as a method for interconnecting electronic devices. Through silicon vias (TSVs) and other through silicon vias are one of the techniques for achieving three-dimensional packaging. Through electrodes are used to electrically connect three-dimensionally stacked devices such as logic, memory, sensors, actuators, etc. (see, for example, Patent Document 1).
特開2016-213349号公報Japanese Patent Application Publication No. 2016-213349
 3次元実装技術を用いて製造された3次元積層構造体では、半導体チップの熱を外部に効率よく放散させる手法が重要である。特に極低温かつ真空環境下で使用される量子ビットチップに3次元実装技術を適用した場合、量子ビットチップからの熱を効率よく放散できない問題が生じた。量子ビットチップの安定動作のためには、量子ビットチップを極低温に保つことが重要である。 In a three-dimensional stacked structure manufactured using three-dimensional packaging technology, it is important to have a method for efficiently dissipating heat from a semiconductor chip to the outside. In particular, when three-dimensional packaging technology is applied to quantum bit chips used at extremely low temperatures and in a vacuum environment, a problem arises in which heat from the quantum bit chips cannot be efficiently dissipated. For stable operation of qubit chips, it is important to keep them at extremely low temperatures.
 本発明は、かかる事情に鑑みてなされたものであり、その目的は、熱放散性能を向上させることが可能な貫通電極、これを用いた構造体及び3次元積層構造体を提供することにある。 The present invention has been made in view of the above circumstances, and its purpose is to provide a through electrode, a structure using the same, and a three-dimensional laminated structure that can improve heat dissipation performance. .
 本発明の第1の態様は、支持体を貫通する貫通電極であって、前記支持体は、第1の面と第2の面との間を貫通する貫通孔が形成されており、前記貫通電極は、前記第1の面と前記第2の面との間を連絡する熱伝導体と、前記第1の面と前記第2の面との間を連絡する超伝導体とを有し、前記貫通孔の内部において、前記熱伝導体と前記超伝導体とが互いに接して形成されていることを特徴とする貫通電極である。 The first aspect of the present invention is a through electrode that penetrates a support, the support having a through hole formed therein that penetrates between a first surface and a second surface, the through electrode having a thermal conductor that connects between the first surface and the second surface, and a superconductor that connects between the first surface and the second surface, the thermal conductor and the superconductor being formed in contact with each other inside the through hole.
 本発明の第2の態様は、前記超伝導体が4.2K以下の温度で超伝導を示す物質であり、前記熱伝導体が4.2K以下の温度で常伝導を示す物質であることを特徴とする第1の態様の貫通電極である。
 本発明の第3の態様は、前記熱伝導体が銅であることを特徴とする第1又は第2の態様の貫通電極である。
A second aspect of the present invention is that the superconductor is a substance that exhibits superconductivity at a temperature of 4.2K or lower, and the thermal conductor is a substance that exhibits normal conductivity at a temperature of 4.2K or lower. This is a characteristic feature of the first aspect of the through electrode.
A third aspect of the present invention is the through electrode according to the first or second aspect, wherein the thermal conductor is copper.
 本発明の第4の態様は、第1~第3のいずれか1の態様の貫通電極と、前記支持体とを有することを特徴とする構造体である。
 本発明の第5の態様は、前記支持体がシリコン(Si)から形成され、前記貫通孔の内壁面において、前記シリコン(Si)と前記貫通電極との間にシリコン酸化膜が形成されており、前記シリコン酸化膜の厚さが10nm以下であることを特徴とする第4の態様の構造体である。
 本発明の第6の態様は、前記貫通電極が、前記支持体の前記第1の面及び前記第2の面の少なくとも一方から突出していることを特徴とする第4又は第5の態様の構造体である。
A fourth aspect of the present invention is a structure characterized by having the through electrode according to any one of the first to third aspects and the support body.
In a fifth aspect of the present invention, the support body is made of silicon (Si), and a silicon oxide film is formed between the silicon (Si) and the through electrode on the inner wall surface of the through hole. , the structure according to the fourth aspect, wherein the silicon oxide film has a thickness of 10 nm or less.
A sixth aspect of the present invention is the structure according to the fourth or fifth aspect, wherein the through electrode protrudes from at least one of the first surface and the second surface of the support. It is the body.
 本発明の第7の態様は、半導体チップをさらに備え、前記貫通電極が、半導体チップとの接続に用いられることを特徴とする第4~第6のいずれか1の態様の構造体である。
 本発明の第8の態様は、前記半導体チップが量子ビットチップであることを特徴とする第7の態様の構造体である。
 本発明の第9の態様は、前記貫通電極が前記支持体から突出して、前記半導体チップと直接接続されていることを特徴とする第7又は第8の態様の構造体である。
 本発明の第10の態様は、前記半導体チップが真空環境で動作することを特徴とする第7~第9のいずれか1の態様の構造体である。
A seventh aspect of the present invention is the structure according to any one of the fourth to sixth aspects, further comprising a semiconductor chip, the through electrode being used for connection to the semiconductor chip.
An eighth aspect of the present invention is the structure according to the seventh aspect, characterized in that the semiconductor chip is a quantum bit chip.
A ninth aspect of the present invention is the structure according to the seventh or eighth aspect, characterized in that the through electrode protrudes from the support and is directly connected to the semiconductor chip.
A tenth aspect of the present invention is the structure according to any one of the seventh to ninth aspects, characterized in that the semiconductor chip operates in a vacuum environment.
 本発明の第11の態様は、第4~第10のいずれか1の態様の構造体が、2以上積層して含まれることを特徴とする3次元積層構造体である。
 本発明の第12の態様は、前記3次元積層構造体が、冷却面を含む回路基板及びインターポーザを含み、前記回路基板及び前記インターポーザが、それぞれ前記貫通電極を有することを特徴とする第11の態様の3次元積層構造体である。
An eleventh aspect of the present invention is a three-dimensional laminated structure characterized in that two or more of the structures according to any one of the fourth to tenth aspects are laminated.
A twelfth aspect of the present invention is the eleventh aspect, wherein the three-dimensional laminated structure includes a circuit board including a cooling surface and an interposer, and the circuit board and the interposer each have the through electrode. It is a three-dimensional laminated structure of an aspect.
 本発明の第1の態様によれば、貫通電極が、支持体の第1の面と第2の面との間における熱伝達及び超伝導をそれぞれ熱伝導体と超伝導体とにより行うことができる。貫通孔の内部において、熱伝導体と超伝導体が互いに接して形成されているため、熱伝達は主に熱伝導体により行われ、通電は主に超伝導体により行われる。熱伝導体を介した通電が抑制され、また、超伝導体を介した熱伝達が抑制される。 According to the first aspect of the present invention, the through electrode can perform heat transfer and superconductivity between the first surface and the second surface of the support using a thermal conductor and a superconductor, respectively. can. Since the thermal conductor and the superconductor are formed in contact with each other inside the through hole, heat transfer is mainly performed by the thermal conductor, and electricity supply is mainly performed by the superconductor. Current flow through the thermal conductor is suppressed, and heat transfer through the superconductor is also suppressed.
 本発明の第2の態様によれば、4.2K以下の極低温環境で使用することが必要な場合に有用となる。
 本発明の第3の態様によれば、熱伝達性能を向上することができる。
According to the second aspect of the present invention, it is useful when it is necessary to use it in an extremely low temperature environment of 4.2K or lower.
According to the third aspect of the present invention, heat transfer performance can be improved.
 本発明の第4の態様によれば、支持体の第1の面と第2の面との間における熱伝達及び超伝導を、それぞれ貫通電極の熱伝導体と超伝導体とにより行うことができる。貫通孔の内部において、熱伝導体と超伝導体が互いに接して形成されているため、熱伝達は主に熱伝導体により行われ、通電は主に超伝導体により行われる。熱伝導体を介した通電が抑制され、また、超伝導体を介した熱伝達が抑制される。 According to the fourth aspect of the present invention, heat transfer and superconductivity between the first surface and the second surface of the support can be performed by the thermal conductor and superconductor of the through electrode, respectively. can. Since the thermal conductor and the superconductor are formed in contact with each other inside the through hole, heat transfer is mainly performed by the thermal conductor, and electricity supply is mainly performed by the superconductor. Current flow through the thermal conductor is suppressed, and heat transfer through the superconductor is also suppressed.
 本発明の第5の態様によれば、シリコン(Si)基板に対する加工技術を応用することができるため、高精度の加工が容易になる。シリコンは熱伝達率が低いことから、貫通電極を用いることにより、熱伝達性能を向上することができる。貫通孔の内壁面においてシリコン酸化膜の厚さが10nm以下であることにより、熱酸化等のシリコン酸化膜を形成する工程が不要となる。
 本発明の第6の態様によれば、支持体から突出した貫通電極を、支持体の外部の超伝導デバイス等と超伝導接続する工程が容易になる。
According to the fifth aspect of the present invention, processing techniques for silicon (Si) substrates can be applied, which facilitates high-precision processing. Since silicon has a low heat transfer coefficient, heat transfer performance can be improved by using a through electrode. Since the thickness of the silicon oxide film on the inner wall surface of the through hole is 10 nm or less, a step of forming a silicon oxide film such as thermal oxidation is not necessary.
According to the sixth aspect of the present invention, the step of superconductively connecting the through electrode protruding from the support with a superconducting device or the like outside the support becomes easy.
 本発明の第7の態様によれば、熱伝導体及び超伝導体を有する貫通電極を、半導体チップとの接続に用いることができる。
 本発明の第8の態様によれば、半導体チップとして量子ビットチップを用いる場合に、量子ビットチップをより安定に動作させることができる。
 本発明の第9の態様によれば、支持体から突出した貫通電極を、半導体チップと超伝導接続する工程が容易になる。
 本発明の第10の態様によれば、空気を介した熱放散性能に乏しい構造体であっても、放熱性能を向上することができる。
According to the seventh aspect of the present invention, a through electrode having a thermal conductor and a superconductor can be used for connection with a semiconductor chip.
According to the eighth aspect of the present invention, when a quantum bit chip is used as a semiconductor chip, it is possible to operate the quantum bit chip more stably.
According to the ninth aspect of the present invention, the process of superconductively connecting the through electrode protruding from the support to the semiconductor chip is facilitated.
According to the tenth aspect of the present invention, even if the structure has poor heat dissipation performance through air, the heat dissipation performance can be improved.
 本発明の第11の態様によれば、貫通電極を用いて集積した回路を積層して、高密度化を実現することができる。
 本発明の第12の態様によれば、インターポーザ及び回路基板の貫通電極を介して、半導体チップ等のデバイスからの熱を回路基板の冷却面へと効率的に伝達することができる。
According to the eleventh aspect of the present invention, high density can be achieved by stacking integrated circuits using through electrodes.
According to the twelfth aspect of the present invention, heat from a device such as a semiconductor chip can be efficiently transferred to the cooling surface of the circuit board via the interposer and the through electrode of the circuit board.
3次元積層構造体の一例を示す断面図である。It is a sectional view showing an example of a three-dimensional laminated structure. 貫通電極の一例を示す断面図である。FIG. 3 is a cross-sectional view showing an example of a through electrode. 図2のIII-III線における貫通電極の断面図である。3 is a cross-sectional view of a through electrode taken along line III-III in FIG. 2. FIG. インターポーザに対する貫通電極の配置の一例を示す平面図である。FIG. 2 is a plan view showing an example of the arrangement of through electrodes with respect to an interposer. 半導体チップと直接接続されている貫通電極の一例を示す断面図である。FIG. 2 is a cross-sectional view showing an example of a through electrode directly connected to a semiconductor chip. 実施例における熱分布の一例を示す図である。It is a figure showing an example of heat distribution in an example. 比較例における熱分布の一例を示す図である。It is a figure which shows an example of heat distribution in a comparative example. Cu、Si及びAlの極低温における熱伝導率を示すグラフである。It is a graph showing the thermal conductivity of Cu, Si, and Al at extremely low temperatures.
 以下、好適な実施形態に基づいて、本発明を説明する。以下の実施形態は、本発明を説明するための例示であり、本発明を実施形態に限定する趣旨ではない。さらに、本発明は、その要旨を逸脱しない限り、さまざまな改変が可能である。 The present invention will be described below based on preferred embodiments. The following embodiments are illustrative for explaining the present invention, and are not intended to limit the present invention to the embodiments. Furthermore, various modifications can be made to the present invention without departing from the gist thereof.
 図1に、3次元積層構造体の一例を示す。図2に、貫通電極の一例を示す。図3に、図2のIII-III線における貫通電極の断面を示す。 FIG. 1 shows an example of a three-dimensional laminated structure. FIG. 2 shows an example of a through electrode. FIG. 3 shows a cross section of the through electrode taken along line III-III in FIG. 2.
 3次元積層構造体10は、例えば、半導体チップ1と、貫通電極21を備えるインターポーザ2と、貫通電極31を備える回路基板3とを備える。半導体チップ1とインターポーザ2の貫通電極21との間にバンプ4が形成されている。インターポーザ2の貫通電極21と回路基板3の貫通電極31との間にバンプ5が形成されている。インターポーザ2及び回路基板3は、それぞれ貫通電極21,31及び支持体20,30を有する構造体の一例である。そのため、3次元構造体10は、2以上の構造体が積層して含まれる。 The three-dimensional stacked structure 10 includes, for example, a semiconductor chip 1, an interposer 2 including a through electrode 21, and a circuit board 3 including a through electrode 31. Bumps 4 are formed between the semiconductor chip 1 and the through electrodes 21 of the interposer 2. A bump 5 is formed between the through electrode 21 of the interposer 2 and the through electrode 31 of the circuit board 3. The interposer 2 and the circuit board 3 are examples of structures having through electrodes 21 and 31 and supports 20 and 30, respectively. Therefore, the three-dimensional structure 10 includes two or more structures stacked together.
 半導体チップ1は、通常の半導体チップと同様に、例えばシリコン等の半導体を基板材料としたチップである。半導体チップ1は、量子ビットチップであってもよい。量子ビットチップは、量子ビットを搭載したチップである。量子ビットとしては、特に限定されないが、磁束量子ビット、トランズモン型量子ビット等が挙げられる。量子ビットチップとしては、特に限定されないが、回路方式又はアニーリング方式の量子コンピュータが挙げられる。 The semiconductor chip 1 is a chip whose substrate material is a semiconductor such as silicon, for example, like a normal semiconductor chip. The semiconductor chip 1 may be a quantum bit chip. A quantum bit chip is a chip equipped with a quantum bit. Examples of the quantum bit include, but are not limited to, magnetic flux quantum bits, transmon type quantum bits, and the like. Examples of quantum bit chips include, but are not limited to, circuit-type or annealing-type quantum computers.
 量子ビットは極めて不安定で、ノイズの影響を受けやすいため、それらを均一化かつ安定化させるためには、例えば20mK程度の極低温環境下に配置する必要がある。実施形態の貫通電極21,31を用いることにより、半導体チップ1として量子ビットチップを用いる場合であっても、量子ビットチップをより安定に動作させることができる。 Since quantum bits are extremely unstable and easily affected by noise, in order to make them uniform and stable, it is necessary to place them in an extremely low temperature environment of, for example, about 20 mK. By using the through electrodes 21 and 31 of the embodiment, even when a quantum bit chip is used as the semiconductor chip 1, the quantum bit chip can be operated more stably.
 図1に示す3次元積層構造体10では、回路基板3にインターポーザ2を介して1つの半導体チップ1が搭載されている。回路基板3の面に沿って複数の半導体チップ1が搭載されていてもよい。1つの回路基板3に対して、1つのインターポーザ2を介して複数の半導体チップ1が搭載されていてもよい。1つの回路基板3に対して、複数のインターポーザ2が使用されてもよい。1つのインターポーザ2に1つの半導体チップ1が搭載されていてもよい。1つのインターポーザ2に複数の半導体チップ1が搭載されていてもよい。 In the three-dimensional stacked structure 10 shown in FIG. 1, one semiconductor chip 1 is mounted on a circuit board 3 via an interposer 2. A plurality of semiconductor chips 1 may be mounted along the surface of the circuit board 3. A plurality of semiconductor chips 1 may be mounted on one circuit board 3 via one interposer 2. A plurality of interposers 2 may be used for one circuit board 3. One semiconductor chip 1 may be mounted on one interposer 2. A plurality of semiconductor chips 1 may be mounted on one interposer 2.
 インターポーザ2は、少なくとも支持体20の第1の面26と第2の面27との間を貫通する貫通孔25に、貫通電極21を有すればよい。支持体20としては、シリコン等の半導体基板が好ましい。貫通電極21は、第1の面26と第2の面27との間を連絡する熱伝導体22と、第1の面26と第2の面27との間を連絡する超伝導体23とを有する。すなわち、貫通電極21に含まれる熱伝導体22及び超伝導体23は、支持体20の第1の面26及び第2の面27に部材が設けられたとき、該部材と接続可能なように形成されている。貫通孔25の内部において、熱伝導体22と超伝導体23とは、互いに接して形成されている。図1に示す例では、熱伝導体22が超伝導体23の外周を囲むように形成されている。超伝導体23が熱伝導体22の外周を囲むように形成されていてもよい。また、熱伝導体22及び超伝導体23が、対向して配置されていてもよい。 The interposer 2 only needs to have the through electrode 21 in the through hole 25 that penetrates at least between the first surface 26 and the second surface 27 of the support body 20. The support 20 is preferably a semiconductor substrate made of silicon or the like. The through electrode 21 includes a thermal conductor 22 that communicates between a first surface 26 and a second surface 27 , and a superconductor 23 that communicates between the first surface 26 and second surface 27 . has. That is, the thermal conductor 22 and the superconductor 23 included in the through electrode 21 are connected to each other when the member is provided on the first surface 26 and the second surface 27 of the support 20. It is formed. Inside the through hole 25, the thermal conductor 22 and the superconductor 23 are formed in contact with each other. In the example shown in FIG. 1, the thermal conductor 22 is formed to surround the outer periphery of the superconductor 23. The superconductor 23 may be formed to surround the outer periphery of the thermal conductor 22. Further, the thermal conductor 22 and the superconductor 23 may be arranged facing each other.
 インターポーザ2が熱伝導体22及び超伝導体23を含む貫通電極21を有することにより、第1の面26と第2の面27との間において、熱伝導体22が熱伝達を、超伝導体23が超伝導を行うことができる。貫通孔25の内部において、熱伝導体22と超伝導体23が互いに接して形成されているため、熱伝導体22と超伝導体23との間の熱抵抗又は電気抵抗は十分に小さい。これにより、熱伝導体22を介した通電、超伝導体23を介した熱伝達が抑制される。 Since the interposer 2 has the through electrode 21 including the thermal conductor 22 and the superconductor 23, the thermal conductor 22 transfers heat between the first surface 26 and the second surface 27, and the superconductor 23 can exhibit superconductivity. Since the thermal conductor 22 and the superconductor 23 are formed in contact with each other inside the through hole 25, the thermal resistance or electrical resistance between the thermal conductor 22 and the superconductor 23 is sufficiently small. This suppresses current flow through the thermal conductor 22 and heat transfer through the superconductor 23.
 インターポーザ2には、貫通電極21以外にも、ロジック、メモリ、センサ、アクチュエータ等の能動素子が形成されてもよい。この場合のインターポーザ2は、インターポーザチップとも称すべきものである。本実施形態のインターポーザ2において、支持体20がシリコンである場合は、従来の樹脂基板に配線を形成したインターポーザとは異なる。 In addition to the through electrodes 21, active elements such as logic, memory, sensors, actuators, etc. may be formed in the interposer 2. The interposer 2 in this case should also be called an interposer chip. In the interposer 2 of this embodiment, when the support body 20 is made of silicon, it is different from a conventional interposer in which wiring is formed on a resin substrate.
 インターポーザ2は、複数の貫通電極21を備えることができる。この場合、複数の貫通電極21のうち少なくとも1つを、半導体チップ1との信号の授受を担うように構成される。図4には、インターポーザ2に対する貫通電極21の配置の一例を示す。 The interposer 2 can include a plurality of through electrodes 21. In this case, at least one of the plurality of through electrodes 21 is configured to transmit and receive signals to and from the semiconductor chip 1 . FIG. 4 shows an example of the arrangement of the through electrodes 21 with respect to the interposer 2.
 図1では、半導体チップ1と回路基板3との間に、1層のインターポーザ2を配置した例を示している。実施形態の3次元積層構造体10は、半導体チップ1と回路基板3との間に、2層以上のインターポーザ2を配置してもよい。 FIG. 1 shows an example in which one layer of interposer 2 is placed between a semiconductor chip 1 and a circuit board 3. In the three-dimensional stacked structure 10 of the embodiment, two or more layers of interposers 2 may be arranged between the semiconductor chip 1 and the circuit board 3.
 回路基板3は、少なくとも支持体30の第1の面36と第2の面37との間を貫通する貫通孔35に、貫通電極31を有すればよい。回路基板3に対する貫通電極31の配置としては、インターポーザ2に対する貫通電極21の配置と同様にしてもよい。支持体30としては、シリコン等の半導体基板が好ましい。貫通電極31は、第1の面36と第2の面37との間を連絡する熱伝導体32と、第1の面36と第2の面37との間を連絡する超伝導体33とを有する。すなわち、貫通電極31に含まれる熱伝導体32及び超伝導体33は、それぞれ、第1の面36、第2の面37に部材が設けられたときに該部材と接続可能なように形成されている。貫通孔35の内部において、熱伝導体32と超伝導体33とが互いに接して形成されている。図1に示す例では、熱伝導体32が超伝導体33の外周を囲むように形成されている。超伝導体33が熱伝導体32の外周を囲むように形成されていてもよい。また、熱伝導体32及び超伝導体33が、対向して配置されていてもよい。 The circuit board 3 only needs to have the through electrode 31 in the through hole 35 that penetrates at least between the first surface 36 and the second surface 37 of the support body 30. The arrangement of the through electrodes 31 with respect to the circuit board 3 may be the same as the arrangement of the through electrodes 21 with respect to the interposer 2. The support 30 is preferably a semiconductor substrate made of silicon or the like. The through electrode 31 includes a thermal conductor 32 that communicates between a first surface 36 and a second surface 37, and a superconductor 33 that communicates between the first surface 36 and second surface 37. has. That is, the thermal conductor 32 and the superconductor 33 included in the through electrode 31 are formed so that they can be connected to the member when the member is provided on the first surface 36 and the second surface 37, respectively. ing. Inside the through hole 35, a thermal conductor 32 and a superconductor 33 are formed in contact with each other. In the example shown in FIG. 1, the thermal conductor 32 is formed to surround the outer periphery of the superconductor 33. The superconductor 33 may be formed to surround the outer periphery of the thermal conductor 32. Further, the thermal conductor 32 and the superconductor 33 may be arranged facing each other.
 回路基板3が熱伝導体32及び超伝導体33を含む貫通電極31を有することにより、第1の面36と第2の面37との間において、熱伝導体32が熱伝達を、超伝導体33が超伝導を行うことができる。貫通孔35の内部において、熱伝導体32と超伝導体33が互いに接して形成されているため、熱伝導体32と超伝導体33との間の熱抵抗又は電気抵抗は十分に小さい。これにより、熱伝導体32を介した通電、超伝導体33を介した熱伝達が抑制される。 Since the circuit board 3 has the through electrode 31 including the thermal conductor 32 and the superconductor 33, the thermal conductor 32 transfers heat between the first surface 36 and the second surface 37, and The body 33 is capable of superconducting. Since the thermal conductor 32 and the superconductor 33 are formed in contact with each other inside the through hole 35, the thermal resistance or electrical resistance between the thermal conductor 32 and the superconductor 33 is sufficiently small. This suppresses current flow through the thermal conductor 32 and heat transfer through the superconductor 33.
 回路基板3は、放熱面として冷却面6を有する。冷却面6は、例えば、回路基板3にインターポーザ2が搭載される側とは反対側の面(図2では第1の面36)に配置してもよい。回路基板3は、インターポーザ2を介して半導体チップ1を支持して半導体チップ1の実装に使用される実装基板であってもよい。 The circuit board 3 has a cooling surface 6 as a heat radiation surface. The cooling surface 6 may be arranged, for example, on the surface of the circuit board 3 opposite to the side on which the interposer 2 is mounted (the first surface 36 in FIG. 2). The circuit board 3 may be a mounting board that supports the semiconductor chip 1 via the interposer 2 and is used for mounting the semiconductor chip 1.
 回路基板3は、貫通電極31以外にも、特に図示しないが、配線等を備えてもよい。この場合の回路基板3は、配線基板又はパッケージ基板とも称される。本実施形態の回路基板3において、支持体30がシリコンである場合は、従来の樹脂基板に配線を形成した配線基板とは材質が異なる。回路基板3は、複数の貫通電極31を備えることができる。 In addition to the through electrodes 31, the circuit board 3 may also include wiring, etc., although not particularly shown. The circuit board 3 in this case is also called a wiring board or a package board. In the circuit board 3 of this embodiment, when the support body 30 is made of silicon, the material is different from that of a conventional wiring board in which wiring is formed on a resin substrate. The circuit board 3 can include a plurality of through electrodes 31.
 回路基板3の配線は、回路基板3にインターポーザ2が搭載される側の面(図2では第2の面37)に形成してもよい。この場合は、回路基板3の配線は、バンプ5を介してインターポーザ2の貫通電極21に接続される。回路基板3の貫通電極31は、インターポーザ2の貫通電極21にバンプ5を介して接続される。回路基板3の貫通電極31は、半導体チップ1との信号の授受を担わず、専ら熱を冷却面6に伝達する役割を担ってもよい。この場合、回路基板3の貫通電極31が超伝導体33を有さず、熱伝導体32のみから形成されてもよい。すなわち、3次元積層構造体10において、インターポーザ2は、互いに接して形成された熱伝導体22及び超伝導体23を有し、回路基板3は、超伝導体33を有さない構成であってもよい。 The wiring of the circuit board 3 may be formed on the surface of the circuit board 3 on which the interposer 2 is mounted (the second surface 37 in FIG. 2). In this case, the wiring of the circuit board 3 is connected to the through electrode 21 of the interposer 2 via the bump 5. The through electrodes 31 of the circuit board 3 are connected to the through electrodes 21 of the interposer 2 via bumps 5. The through electrodes 31 of the circuit board 3 may not play a role in transmitting and receiving signals to and from the semiconductor chip 1, but may only play a role in transmitting heat to the cooling surface 6. In this case, the through electrode 31 of the circuit board 3 may be formed only from the thermal conductor 32 without the superconductor 33. That is, in the three-dimensional laminated structure 10, the interposer 2 has a thermal conductor 22 and a superconductor 23 formed in contact with each other, and the circuit board 3 does not have a superconductor 33. Good too.
 実施形態の回路基板3では、貫通電極31が熱伝導体32及び超伝導体33を有する。このため、熱伝導体32が熱を冷却面6に伝達する役割を担い、超伝導体33が半導体チップ1との信号の授受を担うことができる。回路基板3が複数の貫通電極31を備える場合、複数の貫通電極31のうち少なくとも1つを、半導体チップ1との信号の授受を担うように構成することができる。 In the circuit board 3 of the embodiment, the through electrode 31 includes a thermal conductor 32 and a superconductor 33. Therefore, the thermal conductor 32 can play the role of transmitting heat to the cooling surface 6, and the superconductor 33 can play the role of transmitting and receiving signals with the semiconductor chip 1. When the circuit board 3 includes a plurality of through electrodes 31, at least one of the plurality of through electrodes 31 can be configured to transmit and receive signals with the semiconductor chip 1.
 本実施形態の3次元積層構造体10では、インターポーザ2に貫通電極21が形成されるだけではなく、回路基板3にも貫通電極31が形成されている。貫通電極21の熱伝導体22は、インターポーザ2の支持体20よりも熱伝導率が高い材料から構成される。同様に、貫通電極31の熱伝導体32は、回路基板3の支持体30よりも熱伝導率が高い材料から構成される。 In the three-dimensional laminated structure 10 of this embodiment, not only are through electrodes 21 formed in the interposer 2, but through electrodes 31 are also formed in the circuit board 3. The thermal conductor 22 of the through electrodes 21 is made of a material with a higher thermal conductivity than the support 20 of the interposer 2. Similarly, the thermal conductor 32 of the through electrodes 31 is made of a material with a higher thermal conductivity than the support 30 of the circuit board 3.
 貫通電極21,31の熱伝導体22,32は、例えば、銅、タングステン、アルミニウム、ポリシリコン等の金属材料から構成することができる。これらの材料の中でも、銅を熱伝導体22,32とすることが好ましい。支持体20,30がシリコンである場合、貫通電極21,31は、シリコン貫通電極(TSV)と称される。 The thermal conductors 22 and 32 of the through electrodes 21 and 31 can be made of a metal material such as copper, tungsten, aluminum, polysilicon, etc., for example. Among these materials, it is preferable to use copper as the thermal conductors 22, 32. When the supports 20 and 30 are silicon, the through electrodes 21 and 31 are referred to as through silicon vias (TSV).
 貫通電極21,31の超伝導体23,33としては窒化タンタル(TaN)、窒化チタン(TiN)、タンタル(Ta)、ニオブ(Nb)、インジウム(In)、アルミニウム(Al)等が挙げられる。4.2K以下の極低温環境で半導体チップ1を使用することが必要な場合、貫通電極21,31の超伝導体23,33が4.2K以下の温度で超伝導を示す物質であることが好ましい。すなわち、超伝導体23,33を構成する物質の超伝導転移温度は4.2K以下であることが好ましい。 Examples of the superconductors 23 and 33 of the through electrodes 21 and 31 include tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), niobium (Nb), indium (In), and aluminum (Al). If it is necessary to use the semiconductor chip 1 in an extremely low temperature environment of 4.2K or less, the superconductors 23, 33 of the through electrodes 21, 31 must be a material that exhibits superconductivity at a temperature of 4.2K or less. preferable. That is, it is preferable that the superconducting transition temperature of the material constituting the superconductors 23 and 33 is 4.2K or less.
 貫通電極21,31の周囲において、貫通孔25,35の内壁面には、バリアメタルが形成されていてもよい。バリアメタルとしては、例えば特許文献1のバリア層として例示されたTi,TiN,TaN,Ta等が挙げられる。超伝導体23,33がバリアメタルを兼ねてもよい。図2及び図3に示すように、超伝導体23,33が貫通孔25,35の内壁面に接して形成され、熱伝導体22,32が超伝導体23,33の内側に形成されてもよい。 A barrier metal may be formed on the inner wall surfaces of the through holes 25 and 35 around the through electrodes 21 and 31. Examples of the barrier metal include Ti, TiN, TaN, Ta, etc., which are exemplified as the barrier layer in Patent Document 1. The superconductors 23 and 33 may also serve as barrier metals. As shown in FIGS. 2 and 3, superconductors 23 and 33 are formed in contact with the inner wall surfaces of through holes 25 and 35, and thermal conductors 22 and 32 are formed inside the superconductors 23 and 33. Good too.
 インターポーザ2又は回路基板3の支持体20,30と貫通電極21,31との間には絶縁膜が形成されていてもよい。絶縁膜としては、酸化シリコン、窒化シリコン等の無機絶縁膜、又は、樹脂膜等の有機絶縁膜が用いられる。支持体20,30と貫通電極21,31との間の絶縁膜がシリコン酸化膜である場合は、シリコン酸化膜が10nm以下の厚さを有する自然酸化膜であってもよい。支持体20,30と貫通電極21,31との間の絶縁膜が樹脂膜である場合は、例えば、日本パリレン合同会社のパリレン(登録商標)、パラキシリレンの重合物等が挙げられるが、これに限定されるものではない。 An insulating film may be formed between the supports 20 and 30 of the interposer 2 or the circuit board 3 and the through electrodes 21 and 31. As the insulating film, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a resin film is used. When the insulating film between the supports 20, 30 and the through electrodes 21, 31 is a silicon oxide film, the silicon oxide film may be a natural oxide film having a thickness of 10 nm or less. When the insulating film between the supports 20, 30 and the through electrodes 21, 31 is a resin film, examples thereof include Parylene (registered trademark) of Japan Parylene LLC, a polymer of paraxylylene, etc. It is not limited.
 貫通電極21,31の熱伝導体22,32が熱を伝達する役割を担い、超伝導体23,33が半導体チップ1との信号の授受を担う場合、熱伝導体22,32が4.2K以下の温度で常伝導を示す物質であることが好ましい。これにより、4.2K以下の極低温環境で半導体チップ1を使用することが必要な場合に、熱伝導体22,32は信号の授受を担うことなく、専ら熱を伝達する役割を担うことができる。 When the thermal conductors 22 and 32 of the through electrodes 21 and 31 play the role of transmitting heat, and the superconductors 23 and 33 play the role of transmitting and receiving signals with the semiconductor chip 1, the thermal conductors 22 and 32 play a role of 4.2K. It is preferable that the material exhibits normal conductivity at a temperature below. As a result, when it is necessary to use the semiconductor chip 1 in an extremely low temperature environment of 4.2K or less, the thermal conductors 22 and 32 can play the role of exclusively transmitting heat without playing the role of sending and receiving signals. can.
 貫通電極21,31の径に限定はないが、例えば、1μm~100μmである。また、貫通電極21,31のピッチに限定はないが、例えば、貫通電極21,31の径の2倍以上に設定される。半導体チップ1が量子ビットチップである場合、インターポーザ2の能動素子との間において信号の授受を担う貫通電極21,31は、密集して形成されてもよい。この場合には、貫通電極21,31の径及びピッチは小さくなる傾向にある。また、貫通電極21,31が電源に接続される場合には、貫通電極21,31の径及びピッチは大きくなる傾向にある。 The diameter of the through electrodes 21 and 31 is not limited, but is, for example, 1 μm to 100 μm. Further, the pitch between the through electrodes 21 and 31 is not limited, but is set to be twice or more the diameter of the through electrodes 21 and 31, for example. When the semiconductor chip 1 is a quantum bit chip, the through electrodes 21 and 31, which are responsible for exchanging signals with the active elements of the interposer 2, may be formed closely. In this case, the diameter and pitch of the through electrodes 21 and 31 tend to become smaller. Further, when the through electrodes 21 and 31 are connected to a power source, the diameter and pitch of the through electrodes 21 and 31 tend to become larger.
 支持体20,30の厚さ方向における貫通電極21,31の長さに限定はないが、例えば、20μm~600μm程度である。支持体20,30の第1の面26,36及び第2の面27,37は、支持体20,30の厚さ方向に対向する2面であってもよいが、これに限定されるものでもない。各々の支持体20,30において、第1の面26,36又は第2の面27,37は、平面に限らず、曲面、凹凸、デバイス等を有してもよい。 The length of the through electrodes 21, 31 in the thickness direction of the supports 20, 30 is not limited, but is, for example, about 20 μm to 600 μm. The first surfaces 26, 36 and the second surfaces 27, 37 of the supports 20, 30 may be two surfaces facing each other in the thickness direction of the supports 20, 30, but are not limited to this. not. In each support body 20, 30, the first surface 26, 36 or the second surface 27, 37 is not limited to a flat surface, and may have a curved surface, an uneven surface, a device, etc.
 冷却面6において熱をできるだけ分散させるため、冷却面6に放熱金属層が形成されていてもよい。ここで、3次元積層構造体10に放熱金属層が形成される場合、放熱金属層は冷却面6に含まれるとして扱うことができる。放熱金属層の材料に限定はないが、例えば、銅、タングステン、アルミニウム、ポリシリコン等の金属材料から構成することができる。これらの材料の中でも、銅から放熱金属層を形成することが好ましい。放熱金属層が貫通電極31の熱伝導体32と同じ金属材料である場合、冷却面6の放熱金属層と熱伝導体32との接合が容易になり、放熱特性を向上させることができる。 In order to disperse heat as much as possible on the cooling surface 6, a heat dissipating metal layer may be formed on the cooling surface 6. Here, when a heat dissipation metal layer is formed in the three-dimensional laminated structure 10, the heat dissipation metal layer can be treated as being included in the cooling surface 6. The material of the heat dissipation metal layer is not limited, but it can be made of metal materials such as copper, tungsten, aluminum, and polysilicon. Among these materials, it is preferable to form the heat dissipation metal layer from copper. When the heat dissipation metal layer is made of the same metal material as the heat conductor 32 of the through electrode 31, the heat dissipation metal layer of the cooling surface 6 and the heat conductor 32 can be easily bonded, and the heat dissipation characteristics can be improved.
 本実施形態の3次元積層構造体10は、半導体チップ1として量子ビットチップを搭載していることから、半導体チップ1の動作時において半導体チップ1が極低温及び真空環境下で使用される。3次元積層構造体10は、例えば、4.2K以下の極低温環境下で使用される。また、3次元積層構造体10は、例えば、10-2Pa以下の真空環境下で使用される。このような真空環境下では大気雰囲気と異なり空気を介した熱放散性能に乏しいことから、回路基板3に熱伝導体32を含む貫通電極31を設けることによる放熱性能の向上が有用となる。3次元積層構造体10によれば、インターポーザ2及び回路基板3の貫通電極21,31を介して、半導体チップ1からの熱を回路基板3の冷却面6へと効率的に伝達することができる。 Since the three-dimensional stacked structure 10 of this embodiment mounts a quantum bit chip as the semiconductor chip 1, the semiconductor chip 1 is used at extremely low temperatures and in a vacuum environment during operation. The three-dimensional laminated structure 10 is used, for example, in an extremely low temperature environment of 4.2K or lower. Furthermore, the three-dimensional laminated structure 10 is used, for example, in a vacuum environment of 10 −2 Pa or less. In such a vacuum environment, heat dissipation performance through air is poor unlike in an air atmosphere, so it is useful to improve heat dissipation performance by providing through electrodes 31 including thermal conductors 32 on circuit board 3. According to the three-dimensional laminated structure 10, heat from the semiconductor chip 1 can be efficiently transferred to the cooling surface 6 of the circuit board 3 via the interposer 2 and the through electrodes 21, 31 of the circuit board 3. .
 バンプ4,5の材料に限定はないが、例えば、金(Au)、銅(Cu)、銀(Ag)、ニッケル(Ni)等、あるいは、はんだ系材料のSn-Ag-Cu、Sn-Bi、Au-Sn、Sn-Pb等により構成することができる。インターポーザ2を2層以上積層する場合は、半導体チップ1とインターポーザ2との間にバンプ4を用い、インターポーザ2と回路基板3との間にバンプ5を用いるのと同様に、インターポーザ2の間にバンプを用いてもよい。 There is no limitation on the material of the bumps 4 and 5, but examples include gold (Au), copper (Cu), silver (Ag), nickel (Ni), or solder-based materials such as Sn-Ag-Cu and Sn-Bi. , Au-Sn, Sn-Pb, etc. When stacking two or more layers of interposers 2, bumps 4 are used between the semiconductor chip 1 and the interposer 2, and bumps 5 are used between the interposer 2 and the circuit board 3. Bumps may also be used.
 図5は、半導体チップ1と直接接続されている貫通電極21の一例を示す断面図である。図5に示すように、インターポーザ2の貫通電極21が、支持体20から突出して、半導体チップ1と直接接続されていてもよい。この場合は、貫通電極21の突出部24がバンプ4の機能を担うため、半導体チップ1とインターポーザ2との間のバンプ4を省略することができる。 FIG. 5 is a cross-sectional view showing an example of the through electrode 21 that is directly connected to the semiconductor chip 1. As shown in FIG. 5, the through electrodes 21 of the interposer 2 may protrude from the support body 20 and be directly connected to the semiconductor chip 1. In this case, since the protrusion 24 of the through electrode 21 functions as the bump 4, the bump 4 between the semiconductor chip 1 and the interposer 2 can be omitted.
 貫通電極21の突出部24は、インターポーザ2の半導体チップ1側の面に限定されず、インターポーザ2の半導体チップ1から離間した側の面に形成されていてもよい。このように、貫通電極21の突出部24は、インターポーザ2又は回路基板3の支持体20,30の少なくとも一方の面に形成してもよい。貫通電極21,31が支持体20,30の第1の面26,36又は第2の面27,37の少なくとも一方から突出していることにより、貫通電極21,31を、支持体20,30の外部の超伝導デバイス等と超伝導接続する工程が容易になる。 The protrusion 24 of the through electrode 21 is not limited to the surface of the interposer 2 on the semiconductor chip 1 side, but may be formed on the surface of the interposer 2 on the side remote from the semiconductor chip 1. In this way, the protrusion 24 of the through electrode 21 may be formed on at least one surface of the supports 20 and 30 of the interposer 2 or the circuit board 3. Since the through electrodes 21, 31 protrude from at least one of the first surfaces 26, 36 or the second surfaces 27, 37 of the supports 20, 30, the through electrodes 21, 31 are This simplifies the process of making superconducting connections with external superconducting devices.
 インターポーザ2と回路基板3との間において、貫通電極21,31の少なくとも一方が支持体20,30から突出している場合、バンプ5を省略することができる。インターポーザ2の貫通電極21と回路基板3の貫通電極31とを直接接合してもよい。インターポーザ2の支持体20から突出した貫通電極21を、回路基板3側の配線と接合してもよい。回路基板3の貫通電極31の構造が、図5に示される貫通電極21の構造と同様な突出形状であってもよく、回路基板3の支持体30から突出した貫通電極31を、インターポーザ2側の配線と接合してもよい。 If at least one of the through electrodes 21 and 31 protrudes from the supports 20 and 30 between the interposer 2 and the circuit board 3, the bumps 5 can be omitted. The through electrodes 21 of the interposer 2 and the through electrodes 31 of the circuit board 3 may be directly joined. The through electrodes 21 protruding from the support body 20 of the interposer 2 may be joined to the wiring on the circuit board 3 side. The structure of the through electrode 31 of the circuit board 3 may have a protruding shape similar to the structure of the through electrode 21 shown in FIG. It may be connected to the wiring.
 以上、本発明を好適な実施形態に基づいて説明してきたが、本発明は実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の改変が可能である。 Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the embodiments, and various modifications can be made without departing from the gist of the present invention.
 実施形態では、半導体チップとして量子ビットチップを例に説明したが、本発明は、量子ビットチップ以外の半導体チップ及び半導体チップ以外のデバイスに適用することも可能である。半導体チップ等のデバイスが、極低温より高い温度で動作するデバイスであってもよい。半導体チップ等のデバイスは、インターポーザ2及び回路基板3を有する3次元積層構造体10に限らず、実施形態の貫通電極を有する構造体に搭載することができる。図1~2に示す貫通電極21,31が、インターポーザ2及び回路基板3以外の構造体に適用されてもよい。図3~5に示す貫通電極21が、インターポーザ2以外の構造体に適用されてもよい。 Although the embodiment has been described using a quantum bit chip as an example of a semiconductor chip, the present invention can also be applied to semiconductor chips other than quantum bit chips and devices other than semiconductor chips. A device such as a semiconductor chip may be a device that operates at a temperature higher than cryogenic temperatures. Devices such as semiconductor chips can be mounted not only on the three-dimensional stacked structure 10 having the interposer 2 and the circuit board 3 but also on the structure having the through electrodes of the embodiment. The through electrodes 21 and 31 shown in FIGS. 1 and 2 may be applied to structures other than the interposer 2 and the circuit board 3. The through electrodes 21 shown in FIGS. 3 to 5 may be applied to structures other than the interposer 2.
 以下、貫通電極の実施例について、FEM(Finite Element Method)の結果を参照して説明する。FEMは、貫通電極による応力状態及び信頼性を解析する上で一般に使用されている手法である。 Examples of through electrodes will be described below with reference to FEM (Finite Element Method) results. FEM is a commonly used method for analyzing the stress state and reliability caused by through electrodes.
 実施例では、半導体チップ1は量子ビットチップであり、半導体チップ1、インターポーザ2の支持体20及び回路基板3の支持体30は、400μmの厚さのシリコンとした。実施例の貫通電極21,31では、熱伝導体22,32及びバンプ4,5は銅(熱伝導率0.530W/mK)とした。貫通電極21,31の超伝導体23,33は、TiN,TaN等とした。 In the embodiment, the semiconductor chip 1 is a quantum bit chip, and the semiconductor chip 1, the support 20 of the interposer 2, and the support 30 of the circuit board 3 are made of silicon with a thickness of 400 μm. In the through electrodes 21 and 31 of the embodiment, the thermal conductors 22 and 32 and the bumps 4 and 5 are made of copper (thermal conductivity 0.530 W/mK). The superconductors 23 and 33 of the through electrodes 21 and 31 are made of TiN, TaN, or the like.
 支持体20,30は、1辺が1mm(すなわち1000μm)の正方形である。インターポーザ2では、図4に示すように、5個の貫通電極21を、正方形の中心の1箇所及び正方形の中心と頂点との中点4箇所、合わせて5箇所に配置した。回路基板3の貫通電極31も同様に5箇所に配置した。 The supports 20 and 30 are squares with one side of 1 mm (ie, 1000 μm). In the interposer 2, as shown in FIG. 4, five through electrodes 21 were arranged at five locations, one at the center of the square and four midpoints between the center and the apex of the square. The through electrodes 31 of the circuit board 3 were similarly arranged at five locations.
 貫通電極21,31の径は50μmとした。隣接する貫通電極21,31のピッチは、1辺が250μmの正方形の対角線の長さに等しく、約353μmである。貫通電極21,31の長さ(積層方向の高さ)は、支持体20,30の厚さに等しく、400μmである。バンプ4,5の位置は、貫通電極21,31と重なる位置である。バンプ4,5の径は、バンプ4,5が貫通電極21,31の熱伝導体22,32及び超伝導体23,33と接するよう、貫通電極21,31の径と同程度にしてもよい。バンプ4,5の高さは、例えば4μmである。 The diameter of the through electrodes 21 and 31 was 50 μm. The pitch between adjacent through electrodes 21 and 31 is approximately 353 μm, which is equal to the length of a diagonal line of a square whose sides are 250 μm. The length (height in the stacking direction) of the through electrodes 21 and 31 is equal to the thickness of the supports 20 and 30, which is 400 μm. The bumps 4 and 5 are located at positions overlapping with the through electrodes 21 and 31. The diameters of the bumps 4 and 5 may be approximately the same as the diameters of the through electrodes 21 and 31 so that the bumps 4 and 5 are in contact with the thermal conductors 22 and 32 and the superconductors 23 and 33 of the through electrodes 21 and 31. . The height of the bumps 4 and 5 is, for example, 4 μm.
 比較例として、熱伝導体22,32及び超伝導体23,33の2層構造を有さず、貫通電極21,31及びバンプ4,5がアルミニウムのみから形成された貫通電極を用いたこと以外は、実施例と同様にした。比較例の半導体チップ1も量子ビットチップであり、半導体チップ1、インターポーザ2の支持体20及び回路基板3の支持体30は、400μmの厚さのシリコンである。 As a comparative example, a through electrode was used that did not have a two-layer structure of thermal conductors 22, 32 and superconductors 23, 33, and in which through electrodes 21, 31 and bumps 4, 5 were formed only from aluminum. was carried out in the same manner as in the example. The semiconductor chip 1 of the comparative example is also a quantum bit chip, and the semiconductor chip 1, the support 20 of the interposer 2, and the support 30 of the circuit board 3 are made of silicon with a thickness of 400 μm.
 図6は、実施例の熱分布を示す図である。図6には、実施例の構造における量子ビットチップの熱分布1A、インターポーザの熱分布2A、回路基板の熱分布3A、発熱面の熱分布4A及びインターポーザと回路基板との間のバンプの熱分布5Aを示す。 Figure 6 shows the heat distribution in the embodiment. Figure 6 shows the heat distribution 1A of the quantum bit chip, the heat distribution 2A of the interposer, the heat distribution 3A of the circuit board, the heat distribution 4A of the heat generating surface, and the heat distribution 5A of the bumps between the interposer and the circuit board in the structure of the embodiment.
 図7は、比較例の熱分布を示す図である。図7には、比較例の構造における量子ビットチップの熱分布1B、インターポーザの熱分布2B、回路基板の熱分布3B、発熱面の熱分布4B及びインターポーザと回路基板との間のバンプの熱分布5Bを示す。 FIG. 7 is a diagram showing the heat distribution of a comparative example. FIG. 7 shows the thermal distribution of the quantum bit chip 1B, the thermal distribution of the interposer 2B, the thermal distribution of the circuit board 3B, the thermal distribution of the heat generating surface 4B, and the thermal distribution of the bump between the interposer and the circuit board in the structure of the comparative example. 5B is shown.
 回路基板にインターポーザが搭載される側とは反対側の面が冷却面であり、実施例、比較例とも冷却面の温度は10.0mKである。インターポーザは、量子ビットチップが搭載される側の面に発熱面を有する。インターポーザの発熱量は、例えば1.56nW/mmである。 The surface opposite to the side on which the interposer is mounted on the circuit board is the cooling surface, and the temperature of the cooling surface is 10.0 mK in both Examples and Comparative Examples. The interposer has a heat generating surface on the side on which the quantum bit chip is mounted. The amount of heat generated by the interposer is, for example, 1.56 nW/mm 2 .
 図8は、銅(Cu)、シリコン(Si)及びアルミニウム(Al)の極低温における熱伝導率(W/mK)を示すグラフである。Alは、臨界温度(超伝導転移温度)が約1.2Kであり、極低温で超伝導を示す。Alが超伝導転移すると、熱伝導率が大幅に低下する。シリコンも、銅に比べて熱伝導率が小さいことが分かる。 FIG. 8 is a graph showing the thermal conductivity (W/mK) of copper (Cu), silicon (Si), and aluminum (Al) at extremely low temperatures. Al has a critical temperature (superconducting transition temperature) of about 1.2 K and exhibits superconductivity at extremely low temperatures. When Al undergoes a superconducting transition, its thermal conductivity decreases significantly. It can be seen that silicon also has a lower thermal conductivity than copper.
 実施例の構造では、量子ビットチップの熱分布1Aの最高温度が14.3mKであるのに対し、比較例の構造では、量子ビットチップの熱分布1Bの最高温度が38.9mKであった。このことから、比較例は、実施例よりも量子ビットチップの温度低減効果が低いことが分かる。 In the structure of the example, the maximum temperature of the thermal distribution 1A of the quantum bit chip was 14.3 mK, whereas in the structure of the comparative example, the maximum temperature of the thermal distribution 1B of the quantum bit chip was 38.9 mK. From this, it can be seen that the comparative example has a lower effect of reducing the temperature of the quantum bit chip than the example.
 実施例の構造では、回路基板の熱分布3A全体が10.5mK以下の温度を維持したのに対し、比較例の構造では、回路基板の熱分布3Bの最高温度は16.4~19.6mKの範囲内となった。また、比較例のインターポーザの熱分布2Bは、一部が32.4~35.7mKの範囲内であったものの、インターポーザのほぼ全部と量子ビットチップの全部が35.7~38.9mKの範囲内となった。 In the structure of the example, the entire heat distribution 3A of the circuit board maintained a temperature of 10.5 mK or less, whereas in the structure of the comparative example, the maximum temperature of the heat distribution 3B of the circuit board was 16.4 to 19.6 mK. It was within the range of In addition, the heat distribution 2B of the interposer in the comparative example was partially within the range of 32.4 to 35.7 mK, but almost all of the interposer and all of the quantum bit chips were within the range of 35.7 to 38.9 mK. It became inside.
 実施例の発熱面の熱分布4Aは、10.2~14.2mKの範囲内であったのに対し、比較例の発熱面の熱分布4Bは、38.0~38.8mKの範囲内であった。比較例の構造では、インターポーザの発熱面から量子ビットチップへの熱伝導が抑制できていない。実施例の構造では、インターポーザの発熱面の熱をより積極的に回路基板の冷却面に熱伝導させ、量子ビットチップの温度低減効果を奏する。 The heat distribution 4A of the heat generating surface of the example was within the range of 10.2 to 14.2 mK, whereas the heat distribution 4B of the heat generating surface of the comparative example was within the range of 38.0 to 38.8 mK. there were. In the structure of the comparative example, heat conduction from the heat generating surface of the interposer to the quantum bit chip cannot be suppressed. In the structure of the embodiment, the heat from the heat generating surface of the interposer is more actively conducted to the cooling surface of the circuit board, and the temperature of the quantum bit chip is reduced.
 実施例の構造では、量子ビットチップの最高温度が14.2mKになるため、量子ビットチップの安定動作に必要な20mK以下を達成することができている。このように、実施例によれば、比較例と比べて、量子ビットチップの最高温度を顕著に低減することができる。 In the structure of the example, the maximum temperature of the quantum bit chip is 14.2 mK, so it is possible to achieve the temperature below 20 mK required for stable operation of the quantum bit chip. As described above, according to the example, the maximum temperature of the quantum bit chip can be significantly reduced compared to the comparative example.
 実施形態の効果を説明するために、実施例ではFEMによる解析結果を用いたが、本発明は、FEM解析を行うための具体的な条件(材料、膜厚、形状等)に限定されるものではない。 In order to explain the effects of the embodiment, analysis results by FEM were used in the examples, but the present invention is limited to specific conditions (material, film thickness, shape, etc.) for performing FEM analysis. isn't it.
1…半導体チップ、1A,1B…量子ビットチップの熱分布、2…インターポーザ、2A,2B…インターポーザの熱分布、3…回路基板、3A,3B…回路基板の熱分布、4,5…バンプ、4A,4B…発熱面の熱分布、5A,5B…バンプの熱分布、6…冷却面、10…3次元積層構造体、20,30…支持体、21,31…貫通電極、22,32…熱伝導体、23,33…超伝導体、24…突出部、25,35…貫通孔、26,36…第1の面、27,37…第2の面。 1... Semiconductor chip, 1A, 1B... Heat distribution of quantum bit chip, 2... Interposer, 2A, 2B... Heat distribution of interposer, 3... Circuit board, 3A, 3B... Heat distribution of circuit board, 4, 5... Bump, 4A, 4B... Heat distribution of heat generating surface, 5A, 5B... Heat distribution of bump, 6... Cooling surface, 10... Three-dimensional laminated structure, 20, 30... Support body, 21, 31... Through electrode, 22, 32... Thermal conductor, 23, 33... superconductor, 24... protrusion, 25, 35... through hole, 26, 36... first surface, 27, 37... second surface.

Claims (12)

  1.  支持体を貫通する貫通電極であって、
     前記支持体は、第1の面と第2の面との間を貫通する貫通孔が形成されており、
     前記貫通電極は、前記第1の面と前記第2の面との間を連絡する熱伝導体と、前記第1の面と前記第2の面との間を連絡する超伝導体とを有し、
     前記貫通孔の内部において、前記熱伝導体と前記超伝導体とが互いに接して形成されていることを特徴とする貫通電極。
    A through electrode that penetrates the support,
    The support has a through hole formed between the first surface and the second surface,
    The through electrode includes a thermal conductor that communicates between the first surface and the second surface, and a superconductor that communicates between the first surface and the second surface. death,
    The through electrode is characterized in that the thermal conductor and the superconductor are formed in contact with each other inside the through hole.
  2.  前記超伝導体が4.2K以下の温度で超伝導を示す物質であり、前記熱伝導体が4.2K以下の温度で常伝導を示す物質であることを特徴とする請求項1に記載の貫通電極。 2. The superconductor according to claim 1, wherein the superconductor is a substance that exhibits superconductivity at a temperature of 4.2K or lower, and the thermal conductor is a substance that exhibits normal conductivity at a temperature of 4.2K or lower. Through electrode.
  3.  前記熱伝導体が銅であることを特徴とする請求項1に記載の貫通電極。 The through electrode according to claim 1, wherein the thermal conductor is copper.
  4.  請求項1に記載の貫通電極と、前記支持体とを有することを特徴とする構造体。 A structure comprising the through electrode according to claim 1 and the support.
  5.  前記支持体がシリコン(Si)から形成され、前記貫通孔の内壁面において、前記シリコン(Si)と前記貫通電極との間にシリコン酸化膜が形成されており、
     前記シリコン酸化膜の厚さが10nm以下であることを特徴とする請求項4に記載の構造体。
    The support body is made of silicon (Si), and a silicon oxide film is formed between the silicon (Si) and the through electrode on the inner wall surface of the through hole,
    5. The structure according to claim 4, wherein the silicon oxide film has a thickness of 10 nm or less.
  6.  前記貫通電極が、前記支持体の前記第1の面及び前記第2の面の少なくとも一方から突出していることを特徴とする請求項4に記載の構造体。 The structure according to claim 4, wherein the through electrode protrudes from at least one of the first surface and the second surface of the support.
  7.  半導体チップをさらに備え、
     前記貫通電極が、前記半導体チップとの接続に用いられることを特徴とする請求項4に記載の構造体。
    Further equipped with a semiconductor chip,
    5. The structure according to claim 4, wherein the through electrode is used for connection with the semiconductor chip.
  8.  前記半導体チップが量子ビットチップであることを特徴とする請求項7に記載の構造体。 The structure according to claim 7, wherein the semiconductor chip is a quantum bit chip.
  9.  前記貫通電極が前記支持体から突出して、前記半導体チップと直接接続されていることを特徴とする請求項7に記載の構造体。 8. The structure according to claim 7, wherein the through electrode protrudes from the support and is directly connected to the semiconductor chip.
  10.  前記半導体チップが真空環境で動作することを特徴とする請求項7に記載の構造体。 8. The structure according to claim 7, wherein the semiconductor chip operates in a vacuum environment.
  11.  請求項4~10のいずれか1項に記載の構造体が、2以上積層して含まれることを特徴とする3次元積層構造体。 A three-dimensional laminated structure comprising two or more of the structures according to any one of claims 4 to 10 in a laminated manner.
  12.  前記3次元積層構造体が、冷却面を含む回路基板及びインターポーザを含み、前記回路基板及び前記インターポーザが、それぞれ前記貫通電極を有することを特徴とする請求項11に記載の3次元積層構造体。 The three-dimensional laminated structure according to claim 11, wherein the three-dimensional laminated structure includes a circuit board including a cooling surface and an interposer, and the circuit board and the interposer each have the through electrode.
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Citations (4)

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JP2009049349A (en) * 2007-08-16 2009-03-05 Hynix Semiconductor Inc Through-electrode for semiconductor package and semiconductor package having the same
JP2012142414A (en) * 2010-12-28 2012-07-26 Panasonic Corp Semiconductor device, manufacturing method of the same and laminated semiconductor device using the same
US20150262910A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Via structure for signal equalization
JP2022041642A (en) * 2020-09-01 2022-03-11 国立研究開発法人産業技術総合研究所 Three-dimensional laminated structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049349A (en) * 2007-08-16 2009-03-05 Hynix Semiconductor Inc Through-electrode for semiconductor package and semiconductor package having the same
JP2012142414A (en) * 2010-12-28 2012-07-26 Panasonic Corp Semiconductor device, manufacturing method of the same and laminated semiconductor device using the same
US20150262910A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Via structure for signal equalization
JP2022041642A (en) * 2020-09-01 2022-03-11 国立研究開発法人産業技術総合研究所 Three-dimensional laminated structure

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