WO2024060604A1 - 半导体结构、版图结构以及存储器 - Google Patents

半导体结构、版图结构以及存储器 Download PDF

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Publication number
WO2024060604A1
WO2024060604A1 PCT/CN2023/089247 CN2023089247W WO2024060604A1 WO 2024060604 A1 WO2024060604 A1 WO 2024060604A1 CN 2023089247 W CN2023089247 W CN 2023089247W WO 2024060604 A1 WO2024060604 A1 WO 2024060604A1
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Prior art keywords
read
verification
write control
memory cell
control circuit
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English (en)
French (fr)
Inventor
常小卫
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure, layout structure, and memory.
  • Dynamic Random Access Memory is widely used in modern electronic systems due to its high storage density and fast transmission speed.
  • Dynamic random access memory usually includes a core storage area and a peripheral circuit area, wherein the core storage area is used to set up multiple storage units for storing data information, and the peripheral circuit area is electrically connected to the storage unit through a data line so that the storage unit can complete the storage or reading of data information.
  • embodiments of the present disclosure provide a semiconductor structure, a layout structure, and a memory.
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • a plurality of memory cell arrays wherein the memory cell arrays are arranged in parallel along a first direction;
  • a plurality of read and write control circuits arranged in parallel along the first direction are located on one side of the memory cell array in the second direction, and each of the read and write control circuits is connected to a corresponding one through a first data line.
  • the memory cell array, the read and write control circuit is used to control writing or reading data to the memory cell array, and the second direction is perpendicular to the first direction;
  • Verification circuit the verification circuit is located on the side of the read-write control circuit away from the memory cell array, and the verification circuit is connected to the read-write control circuit through a second data line.
  • the verification circuit uses To verify the data.
  • each of the memory cell arrays is connected to a plurality of the first data lines extending along the second direction;
  • the read-write control circuit includes a plurality of sub-circuits, and each sub-circuit is connected to the memory cell array corresponding to the read-write control circuit through a first data line.
  • the verification circuit includes at least:
  • a plurality of first-level verification units the first-level verification unit is connected to at least one of the read-write control circuits and is used to verify the data read by the read-write control circuit or the data to be written, Get the first-level verification results;
  • the first-level verification unit is located on a side of the read-write control circuit away from the memory cell array and is arranged along the first direction.
  • the verification circuit further includes:
  • At least one second-level verification unit connected to at least one of the first-level verification units, is used to verify the first-level verification results and obtain the second-level verification results;
  • the second-level verification unit and the first-level verification unit are alternately arranged along the first direction, or the second-level verification unit is located away from the first-level verification unit.
  • One side of the read/write control circuit is alternately arranged along the first direction, or the second-level verification unit is located away from the first-level verification unit.
  • the verification circuit further includes:
  • a verification storage unit is connected to the second-level verification unit and used to store the final verification result among the second-level verification results.
  • the semiconductor structure further includes: a first metal layer and a second metal layer; the second metal layer is located on the first metal layer; the first level verification unit is connected to the read-write control circuit via a wire located in the first metal layer;
  • the second-level verification unit is connected to other verification circuits through wires located on the second metal layer.
  • the first-level verification unit and the read-write control circuit are connected through at least one first conductor in the first metal layer, and the first conductor extends along the second direction;
  • the second-level verification unit is connected to other verification circuits through at least one second conductor in the second metal layer, and the second conductor extends along the first direction.
  • the first-level verification unit is connected to two adjacent read-write control circuits.
  • the plurality of second-level verification units include: at least one first verification unit and at least one second verification unit;
  • the first verification unit is connected to at least one of the first-level verification units and is used to perform a first verification on the first-level verification result;
  • the second verification unit is connected to at least one of the first verification units and is used to perform a second verification on the result of the first verification and output the final verification result.
  • the semiconductor structure includes:
  • each of the read and write control circuits includes 16 sub-circuits; wherein, each of the memory cell arrays is connected to the corresponding one through 16 of the first data lines.
  • first-level verification units and 3 second-level verification units include: two first verification units and one second verification unit ;
  • the first-level verification unit and the second-level verification unit are alternately arranged along the first direction.
  • the semiconductor structure includes:
  • the first-level verification unit connects two adjacent read-write control circuits through a first wire in the first metal layer, and the first wire extends along the second direction;
  • the first verification unit connects the two first-level verification units through a second wire in the second metal layer, and the second wire extends along the first direction;
  • the second verification unit is connected to the two first verification units through a second conductor in the second metal layer, and the second conductor extends along the first direction.
  • the semiconductor structure further includes: a plurality of sub-word line drivers
  • the sub-word line drivers and the memory cell array are arranged alternately along the first direction; the sub-word line drivers are used to control word lines in the memory cell array.
  • an embodiment of the disclosure provides a memory including the semiconductor structure described in the first aspect of the disclosure.
  • embodiments of the present disclosure provide a layout structure, including:
  • a plurality of memory cell array layouts arranged side by side along the first direction;
  • a plurality of read-write control circuit layouts arranged in parallel along the first direction in one-to-one correspondence with the memory cell array layout, and the read-write control circuit layout is located on one side of the memory cell array in the second direction , the second direction is perpendicular to the first direction;
  • a plurality of first data line patterns extending along the second direction.
  • the first data line pattern is located on a side of the read-write control circuit layout close to the memory cell array layout.
  • the memory cell array layout passes through the The first data line graphically connects the corresponding read-write control circuit layout.
  • the layout structure further includes:
  • a plurality of verification circuit layouts arranged side by side along the first direction; at least one of the verification circuit layouts is connected to at least one of the read and write control circuit layouts;
  • the verification circuit layout is located on a side of the read/write control circuit layout away from the memory cell array layout.
  • the memory cell array is arranged in parallel along the first direction
  • the read and write control circuit is located on one side of the memory cell array in the second direction and is arranged in parallel along the first direction, and the second The direction is perpendicular to the first direction
  • the verification circuit is located on the side of the read-write control circuit away from the memory cell array.
  • the memory cell array and the read-write control circuit are in one-to-one correspondence in the second direction, so that the memory cell array and the read-write control circuit are in one-to-one correspondence.
  • the write control circuit can be connected through linear wires, optimizing the connection line between the read and write control circuit and the memory cell array, thereby reducing the difficulty of the memory preparation process, while reducing the memory's power consumption during data transmission and improving data transmission. speed.
  • Figure 1 is a schematic diagram 1 of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2 is a schematic diagram 2 of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic diagram of a connection method between a memory cell array and a read and write control circuit in a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 4 is a schematic diagram 1 of a semiconductor structure including a first-level verification circuit and a second-level verification circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram 2 of a semiconductor structure including a first-level verification circuit and a second-level verification circuit provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a semiconductor structure including a sub-word line driver provided by an embodiment of the present disclosure.
  • terms can be understood at least in part from their use in context.
  • the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense.
  • terms such as “one” or “the” can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context.
  • the term “based on” can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.
  • Semiconductor memory is a memory that uses semiconductor circuits for access. Among them, DRAM is widely used in various fields due to its fast storage speed and high integration level.
  • FIG. 1 is a partial structural diagram of a DRAM.
  • the semiconductor structure shown in Figure 1 includes: a plurality of memory cell arrays 10 arranged in parallel along a first direction X; a plurality of read and write control circuits RW and a plurality of error correcting codes (Error Correcting Code, ECC) verification circuit, the read-write control circuit RW is connected to the memory cell array 10 through multiple data lines, and is used to control writing or reading data to the memory cell array 10; the verification circuit passes through the metal layer (not (shown in the figure) is connected to the read and write control circuit RW, thereby acquiring the data of the memory cell array 10 and verifying it.
  • ECC Error Correcting Code
  • the read/write control circuit RW and the ECC check circuit are located on one side of the memory cell array 10 in the second direction Y perpendicular to the first direction X, and are arranged alternately along the first direction X.
  • the layout of the semiconductor structure shown in FIG1 makes the semiconductor structure more compact and improves the integration of the memory to a certain extent, it also causes that the data line 01 connected to the read/write control circuit RW and the data line 02 connected to the memory cell array 10 cannot correspond one to one in the second direction Y. In this case, the read/write control circuit RW and the memory cell array 10 cannot be connected by a straight wire, and the data line between the two needs to be jumpered to achieve conduction.
  • a wire 03 is added between the data line 01 and the data line 02 to make the line between the read/write control circuit RW and the memory cell array 10 conductive.
  • embodiments of the present disclosure provide a semiconductor structure, a layout structure and a memory.
  • FIG2 is a schematic diagram of a semiconductor structure of a half storage block provided by an embodiment of the present disclosure.
  • the semiconductor structure includes:
  • a plurality of memory cell arrays 10, the memory cell arrays 10 are arranged side by side along the first direction X;
  • the verification circuit is located at a side of the read/write control circuit RW away from the memory cell array 10 and is connected to the read/write control circuit RW via a second data line 05 .
  • the verification circuit is used to verify the data in the memory cell array 10 .
  • the memory cell array 10 is used to store data, thereby realizing the storage function of the semiconductor memory.
  • the memory cell array 10 may include word lines, bit lines, memory cells, etc.
  • the memory unit further includes a storage capacitor and a transistor, the control end of the transistor is connected to the word line, and the first end of the transistor is connected to the storage capacitor. connection, the second end of the transistor is connected to the bit line.
  • the word line control transistor is turned on, the storage capacitor and the bit line are turned on, thereby achieving Reading and writing of data information, that is, when reading data information, the storage capacitor transmits the stored data information to the bit line; when writing data information, the bit line sends the data information to be written to the storage capacitance.
  • multiple memory cell arrays 10 are arranged side by side along the first direction half, it can also be other, and the embodiment of the present disclosure does not limit this.
  • the read and write control circuit RW is a logic circuit module connected to the memory cell array 10 and controlling the memory cell array 10 to read and write data.
  • the read and write control circuit RW can be used to receive a read and write enable signal (such as a read enable signal RdEn and a write enable signal WrEn), and send data to be written to the memory cell array 10 or receive read data,
  • a read and write enable signal such as a read enable signal RdEn and a write enable signal WrEn
  • the read and write control circuit RW may perform a write operation according to the write enable signal WrEn to store data into the memory cell array 10 selected by the address, and perform a read operation according to the read enable signal RdEn.
  • a fetch operation is performed to output data stored in the memory cell array 10.
  • Each read and write control circuit RW can be connected to a corresponding memory cell array 10 through the first data line 04, and connected to the verification circuit through the second data line 05, thereby realizing data interaction with the memory cell array 10 and the verification circuit, and then Data written or read from the memory cell array 10 is transferred to the verification circuit.
  • the first data line 04 may be a signal line connected to the memory cell array 10 and used to provide write data to a circuit to which each memory cell is connected.
  • the data to be written can be transferred to the bit line connected to the memory unit through the first data line 04, and the signal on the bit line is further transferred to the memory unit during the writing process.
  • the verification circuit is connected to the read and write control circuit RW, and can obtain the data read from or written to the memory cell array 10 and perform corresponding operations, thereby verifying whether the data information in the memory cell array 10 is accurate. , and outputs the verification result, thereby improving the reliability of data reading and writing of the memory cell array 10 .
  • Each verification circuit can be used to verify data information of one or more storage arrays.
  • the check circuit may be a parity check circuit or an error correction code ECC check circuit, or it may be another type of check circuit or a combination of check circuits, etc., which is not limited.
  • the check circuit may be an ECC check circuit, which is used for error detection and correction of data transmitted between the memory and the processor.
  • ECC check code used for error detection and correction of data transmitted between the memory and the processor.
  • the ECC check code is generated.
  • error detection and correction are performed on the transmitted data based on the ECC check code.
  • Error after error detection and correction, Discard the ECC check code and output the corrected data.
  • the ECC check code of the transmitted data is generated.
  • the transmitted data is transmitted to the memory, error detection and correction of the transmitted data are performed based on the ECC check code. After error detection and correction, the ECC check code is discarded and the corrected data is output.
  • the memory cell array 10 is arranged side by side along the first direction X; the read and write control circuit RW is located on one side of the memory cell array 10 in the second direction Y and is arranged side by side along the first direction X; The verification circuit is located on the side away from the memory cell array 10 of the read/write control circuit RW.
  • the verification circuit is disposed on the side of the read-write control circuit RW away from the memory cell array 10, so that each read-write control circuit RW and its corresponding memory cell array 10 are in one-to-one correspondence in the second direction Y. Therefore, the memory cell array 10 and the read/write control circuit RW can be connected through linear wires.
  • the arrangement of the embodiment of the present disclosure optimizes the connection line between the read-write control circuit RW and the memory cell array 10, thereby reducing the difficulty of the memory manufacturing process. , while reducing the power consumption of the memory during data transmission and increasing the speed of data transmission.
  • each memory cell array 10 is connected to a plurality of first data lines 04 extending along the second direction Y;
  • the read-write control circuit RW includes a plurality of sub-circuits 06, and each sub-circuit 06 is connected to the corresponding memory cell array 10 of the read-write control circuit RW through one of the first data lines 04.
  • each memory cell array 10 includes multiple memory cells. In order to ensure the efficiency of writing or reading data in the memory cell array 10, each memory cell array 10 communicates with read data through a plurality of first data lines 04. Write control circuit RW connection. The memory cell array 10 may receive data to be written or output stored data through the first data line 04 . In the embodiment of the disclosure, a plurality of first data lines 04 connected to each memory cell array 10 are arranged in parallel along the first direction X, and the first data lines 04 are linear conductors extending along the second direction Y.
  • the sub-circuit 06 in the read-write control circuit RW is a logic circuit module connected to the memory cell array 10 and controlling the memory cell array 10 to read and write data.
  • the sub-circuit 06 in the read-write control circuit RW is located on one side of its corresponding memory cell array 10 in the second direction Y.
  • a plurality of sub-circuits 06 are arranged in parallel along the first direction
  • the data line 04 corresponds one-to-one with the sub-circuit 06 in the corresponding read-write control circuit RW in the second direction Y.
  • Each sub-circuit 06 is connected to the memory cell array 10 corresponding to the read-write control circuit RW through a first data line 04. Therefore, the read and write control circuit RW can pass multiple first data lines 04
  • the memory cell array 10 receives read data or transmits data to be written to the memory cell array 10 .
  • the present disclosure makes the first data line 04 connected to the memory cell array 10 correspond one-to-one with the sub-circuit 06 in the read-write control circuit RW in the second direction Y, so that the linear first data extending along the second direction Y Line 04 may connect the memory cell array 10 and the read/write control circuit RW. Since the read-write control circuit RW is located on one side of its corresponding memory cell array 10 in the second direction Y, the arrangement of the present disclosure further optimizes the connection line between the read-write control circuit RW and the memory cell array 10, reducing the memory cost. Preparation process difficulty.
  • the verification circuit at least includes:
  • a plurality of first-level verification units 11, the first-level verification unit 11 is connected to at least one read-write control circuit RW, and is used to verify the data read by the read-write control circuit RW or the data to be written, to obtain the first-level verification unit 11. Level 1 verification results;
  • the first-level verification unit 11 is located on a side of the read-write control circuit RW away from the memory cell array 10 and is arranged along the first direction X.
  • the first-level verification unit 11 is a calculation circuit module connected to the read-write control circuit RW and verifies the data read by the read-write control circuit RW or the data to be written.
  • the first-level verification unit 11 passes through the second
  • the data line 05 is connected to the read-write control circuit RW.
  • Each first-level verification unit 11 can be connected to one or more read-write control circuits RW, and the data read from the one or more read-write control circuits RW to which it is connected. The data or data to be written is verified to obtain the first-level verification result.
  • the first-level verification unit 11 is connected to two read-write control circuits RW, then during a verification process, the data in the two memory cell arrays 10 corresponding to the two read-write control circuits RW are simultaneously processed. Verify to get the first level verification result.
  • the first-level verification unit 11 is located on the side of the read-write control circuit RW away from the memory cell array 10.
  • the first-level verification unit 11 may be arranged in parallel along the first direction X, or may be dispersedly arranged along the first direction X.
  • the first verification units 12-1 are dispersedly arranged along the first direction X, so that each first-level verification unit 11 is as close as possible to its corresponding read-write control circuit RW, thereby shortening the first
  • the connection line between the first-level verification unit 11 and the read-write control circuit RW reduces the resistance in the line, thereby reducing the power consumption of the memory during data transmission; at the same time, the first-level verification unit 11 and the read-write control circuit
  • the connection between RW is easier to realize, and the connection line between the read and write control circuit RW and the first-level verification unit 11 is optimized to reduce the difficulty of the memory preparation process.
  • the first-level verification unit 11 can verify the data in one verification process.
  • the number of memory cell arrays 10 that can be checked by a first-level check unit 11 at a time can be determined according to the number of bytes of data that can be checked by the first-level check unit 11 at a time and the number of bytes of data that can be stored in each memory cell array 10, and then the number of read-write control circuits RW connected to a first-level check unit 11 can be determined.
  • each memory cell array 10 reads or writes 16 bits of data at a time
  • the first-level check unit 11 can check 32 bits of data at a time
  • each first-level check unit 11 can check the data in two memory cell arrays 10 at a time, therefore, each first-level check unit 11 can be connected to two read-write control circuits RW, and the data in the two memory cell arrays 10 connected to the two read-write control circuits RW are checked to obtain the first-level check result.
  • the amount of data required for the memory bank 20 can also be determined based on the amount of data that the first-level verification unit 11 can verify each time and the amount of data that all memory cell arrays 10 in the memory block can read or write at one time.
  • the first-level check unit 11 can read or write 16-bit data at a time. If 32-byte data can be verified at the same time, the half memory bank 20 requires four first-level verification units 11.
  • the verification circuit further includes:
  • At least one second-level verification unit 12 is connected to at least one first-level verification unit 11, and is used to verify the first-level verification results and obtain the second-level verification results;
  • the second-level verification unit 12 and the first-level verification unit 11 are alternately arranged along the first direction side.
  • the verification circuit can verify each time is limited. In order to improve the verification speed and verification efficiency of the verification circuit and ensure the reliability of data reading and writing in the semiconductor memory, the verification circuit can pass Verification units of different levels are set up to perform multiple verifications on the data in the storage unit.
  • the verification circuit includes a first-level verification unit 11 and a second-level verification unit 12.
  • the first-level verification unit 11 is connected to the read-write control circuit RW and reads
  • the calculation circuit module is used to verify the data read by the write control circuit RW or the data to be written.
  • the second-level verification unit 12 is connected to the first-level verification unit 11 and verifies the first-level verification result. calculation circuit module.
  • the first-level verification unit 11 in the verification circuit first verifies the data in the memory cell array 10 to obtain the first-level verification result; the first-level verification unit 11 passes the third data line 07 Connected to the second-level verification unit 12, and the third data line 07 The first-level verification result is transmitted to the second-level verification unit 12, and then the second-level verification unit 12 verifies the first-level verification result to obtain the second-level verification result.
  • the second-level verification unit 12 and the first-level verification unit 11 are both located on the side of the read-write control circuit RW away from the memory cell array 10 , and the second-level verification unit 12 is located on the side of the read-write control circuit RW away from the memory cell array 10 .
  • the verification units 12 and the first-level verification units 11 are alternately arranged along the first direction
  • the connection line between the unit 12 and the first-level verification unit 11 reduces the resistance in the line, thereby reducing the power consumption of the memory during data transmission; at the same time, the second-level verification unit 12 and the first-level verification unit
  • the connection between the units 11 is easier to realize, optimizing the connection line between the second-level verification unit 12 and the first-level verification unit 11, and reducing the difficulty of the memory preparation process.
  • the first-level verification unit 11 is located on the side of the read-write control circuit RW away from the memory cell array 10
  • the second-level verification unit 12 is located on the side away from the first-level verification unit 11 .
  • the read-write control circuit RW, the first-level verification unit 11 and the second-level verification unit 12 are arranged in sequence along the second direction Y.
  • the first-level verification unit 11 and the read-write control circuit RW are connected through the second data line 05
  • the second-level verification unit 12 and the first-level verification unit 11 are connected through the third data line 07.
  • the second data line 05 and the third data line 07 have the same routing direction.
  • the second data line 05 and the third data line 07 both extend along the second direction Y, which is beneficial to forming the second data line 05 and the third data line 07 at the same time in the same process, thereby simplifying the process flow.
  • the second-level verification unit 12 can be connected to one first-level verification unit 11 or multiple first-level verification units 11 .
  • the data that the second-level verification unit 12 can verify each time is limited.
  • the first-level verification unit 11 can verify 32 bytes of data each time, that is, the first-level verification unit 11 includes the first-level verification result of the 32-byte data; if the second-level verification unit 12 The first-level verification result of 64 bytes of data can be verified each time, so each second-level verification unit 12 can be connected to two first-level verification units 11 .
  • the verification circuit further includes:
  • the verification storage unit is connected to the second-level verification unit 12 and is used to store the final verification result in the second-level verification result.
  • the verification storage unit is a logic circuit module that can control the final verification result in the verification circuit to be stored in the corresponding memory unit array 10 .
  • transfer data from memory to processor During the process, when data is output from the memory, the verification circuit verifies the data and generates the final verification result; when the data is transmitted to the processor, error detection and error correction are performed on the transmitted data based on the final verification result. After error correction, discard the final verification result and output the corrected data.
  • the verification circuit first verifies the data in the memory cell array 10 through the connected first-level verification unit 11 to obtain the first-level verification result; and then verifies the data through the second-level verification unit 12
  • the first verification result is verified to obtain a second-level verification result.
  • the second-level verification result includes at least one final verification result;
  • the second-level verification unit 12 is connected to the verification storage unit through a fourth data line. , and transmits the final verification structure in the second-level verification result to the verification storage unit through the fourth data line, and the verification storage unit receives and stores the final verification result in the second-level verification result; finally, the verification The verification storage unit controls to store the final verification result into the corresponding memory unit array 10.
  • the semiconductor structure further includes: a first metal layer and a second metal layer; the second metal layer is located on the first metal layer;
  • the first-level verification unit 11 is connected to the read-write control circuit RW through wires located on the first metal layer;
  • the second-level verification unit 12 is connected to other verification circuits through wires located on the second metal layer.
  • the first metal layer and the second metal layer are mainly used as conductors to connect the read-write control circuit, the first-level verification unit, and the second-level verification unit.
  • the materials of the first metal layer and the second metal layer include but are not limited to titanium, tantalum, palladium, nickel, platinum, cobalt, tungsten, zirconium, and molybdenum, and can be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition ( Formed by Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD).
  • the first-level verification unit 11 is connected to the read-write control circuit RW through a plurality of second data lines 05; the second-level verification unit 12 is connected to other verification circuits through the third data line 07, and the other
  • the verification circuit includes a first-level verification unit 11 and other second-level verification units 12 .
  • the second data line 05 may be a conductor located in the first metal layer
  • the third data line 07 may be a conductor located in the second metal layer, that is, the first-level verification unit 11 and the read-write control circuit RW pass through a conductor located in the second metal layer.
  • the second-level calibration unit 12 is connected to other calibration circuits through wires located in the second metal layer.
  • the first-level verification unit 11 is located on one side of the read-write control circuit RW in the second direction, and connects the first-level verification unit 11 with the second number of the read-write control circuit RW.
  • the data line 05 can extend along the second direction Y; the second-level verification circuit and the first-level verification circuit are alternately arranged along the first direction
  • the third data line 07 of the verification unit 11 or other second-level verification unit 12) may extend along the first direction X. Therefore, the second data line 05 and the third data line 07 in the semiconductor structure shown in FIG. 4 are perpendicular to each other. .
  • Using different layers of metal layers as conductors to realize the connection between the read and write control circuit RW and the verification circuit, as well as the connection between the verification circuits, can reduce the short circuit between different lines in the memory and the coupling effect between circuits , thereby improving memory performance.
  • the first-level verification unit 11 and the read-write control circuit RW are connected through at least one first conductor 08 in the first metal layer, and the first conductor 08 extends along the second direction Y;
  • the second-level verification unit 12 is connected to other verification circuits through at least one second conductor 09 in the second metal layer, and the second conductor 09 extends along the first direction X.
  • the read-write control circuit RW in this embodiment is located on one side of the memory cell array 10 in the second direction Y, and the first-level verification unit 11 is located on the side of the read-write control circuit RW away from the memory cell array 10.
  • One side that is, the first-level verification unit 11 is located on the side of the read-write control circuit RW in the second direction Y. Therefore, the first-level verification unit 11 can be connected to the read-write control circuit through a wire extending along the second direction Y. Circuit RW.
  • the first-level verification unit 11 and the second-level verification unit 12 are alternately arranged along the first direction X. Therefore, the second verification unit 12-2 can be connected through wires extending along the first direction X.
  • a first conductor 08 extending along the second direction Y is arranged in the first metal layer, and a second conductor 09 extending along the first direction X is arranged in the second metal layer.
  • the primary verification unit 11 is connected to the read-write control circuit RW through one or more first wires 08 in the first metal layer.
  • the first wires 08 can carry the data read by the read-write control circuit RW or the data to be written.
  • the second-level verification unit 12 and other verification circuits (the first-level verification unit 11 or other second-level verification units 12) pass through one or more of the second metal layers
  • the second wire 09 is connected to the second wire 09, and the second wire 09 can realize data interaction between the second-level verification unit 12 and the first-level verification unit 11, as well as data interaction between multiple second-level verification units 12.
  • the first-level verification unit 11 connects two adjacent read and write control circuits RW.
  • the first-level verification unit 11 can verify the data in the two memory cell arrays 10 at the same time.
  • Each memory cell array 10 converts the data through a read-write control circuit RW.
  • the data is transmitted to the first-level verification unit 11. Therefore, the first-level verification unit 11 simultaneously verifies the data in the two memory cell arrays 10 by connecting two read and write control circuits RW.
  • the two read-write control circuits RW connected to the first-level verification unit 11 are adjacent, which can shorten the connection line between the first-level verification unit 11 and the read-write control circuit RW, and reduce the number of circuits.
  • the resistance is the resistance.
  • the plurality of second-level verification units 12 include: at least one first verification unit 12-1 and at least one second verification unit 12-2;
  • the first verification unit 12-1 is connected to at least one of the first-level verification units 11 and is used to perform the first verification on the first-level verification results;
  • the second verification unit 12-2 is connected to at least one of the first verification units 12-1, and is used to perform a second verification on the result of the first verification and output the final verification result.
  • the verification circuit performs on the data in the memory cell array 10 through the first-level verification unit 11 , the first verification unit 12 - 1 and the second verification unit 12 - 2 . check. Specifically, the verification circuit first verifies the data in the memory cell array 10 through the first-level verification unit 11 to obtain the first-level verification result; the first-level verification unit 11 communicates with the third data line 07 through the third data line 07. The first verification unit 12-1 in the second-level verification unit 12 is connected and transmits the first-level verification result to the first verification unit 12-1 through the third data line 07.
  • the first verification pair is the first
  • the first-level verification result is subjected to the first verification;
  • the first verification unit 12-1 in the second-level verification unit 12 is connected to the second verification unit 12-2 through the fifth data line, and
  • the result of the first verification is transmitted to the second verification unit 12-2.
  • the second verification unit 12-2 performs a second verification on the result of the first verification and outputs the final verification result.
  • the semiconductor structure shown in Figure 4 includes:
  • Each read-write control circuit RW includes 16 sub-circuits 06; wherein, each memory cell array 10 is connected to the corresponding read-write circuit through 16 first data lines 04. Subcircuit 06 of write control circuit RW;
  • first-level verification units 11 and 3 second-level verification units 12 include: two first-level verification units 12-1 and one second-level verification unit 12-2;
  • the first-level verification unit 11 and the second-level verification unit 12 are alternately arranged along the first direction X.
  • the semiconductor structure provided by this embodiment includes 8 memory cell arrays 10 , 8 read and write control circuits RW, 4 first-level verification units 11 and 3 second-level verification units 12 .
  • 8 memory cell arrays 10 are arranged in parallel along the first direction X
  • 8 read and write control circuits RW are located on one side of the memory cell array 10 in the second direction Y and are arranged in parallel along the first direction X
  • 4 Three first-level verification units 11 and three second-level verification units 12 are located on the side of the read-write control circuit RW away from the memory cell array 10, and the first-level verification unit 11 and the second-level verification unit 12 are alternately arranged along the first direction X.
  • the verification circuit is disposed on the side of the read-write control circuit RW away from the memory cell array 10, so that each read-write control circuit RW and its corresponding memory cell array 10 are in one-to-one correspondence in the second direction Y.
  • the connection line between the read and write control circuit RW and the memory cell array 10 is optimized, thereby reducing the difficulty of the memory preparation process, while reducing the resistance of the circuit, reducing the power consumption of the memory during data transmission, and increasing the speed of data transmission. .
  • each read-write control circuit RW includes 16 sub-circuits 06.
  • the first data line 04 connecting the memory cell array 10 and the sub-circuit 06 in the read-write control circuit RW correspond one to one in the second direction Y.
  • Each sub-circuit 06 One first data line 04 in the corresponding memory cell array 10 is connected, that is, each memory cell array 10 is connected to the 16 sub-circuits 06 of the corresponding read-write control circuit RW through 16 first data lines 04 .
  • the first data line 04 connecting the memory cell array 10 and the sub-circuit 06 in the read-write control circuit RW are in one-to-one correspondence in the second direction Y, so that the memory cell array 10 and the read-write control circuit RW can pass through
  • Straight-line connection means that the memory cell array 10 and the read-write control circuit RW can be directly connected without using a jumper, which optimizes the connection line between the read-write control circuit RW and the memory cell array 10 .
  • the first-level verification unit 11 can verify the data in two memory cell arrays 10 at the same time.
  • Each memory cell array 10 passes the data through a read-write control circuit RW. is transmitted to the first-level verification unit 11. Therefore, each first-level verification unit 11 in this embodiment is connected to two adjacent read-write control circuits RW.
  • the first-level verification unit 11 passes through the read-write control circuit RW obtains the data in its corresponding memory cell array 10, verifies the data in the two memory cell arrays 10 simultaneously, and obtains the first-level verification result.
  • the first verification unit 12-1 in the second-level verification unit 12 can simultaneously perform a first verification on two first-level verification results
  • the second verification unit 12-2 can simultaneously perform a second verification on the verification results of the two first-level verification units 12-1.
  • the first verification unit 12-1 is connected to two first-level verification units 11, and each first-level verification unit 11 is only connected to one first verification unit 12-1; the first verification unit 12-1 performs a first verification on the first-level verification result of the connected first-level verification unit 11; the second verification unit 12-2 is connected to the two first verification units 12-1, and performs a second verification on the first verification results of the two first verification units 12-1, Get the final verification result.
  • the semiconductor structure includes:
  • the first-level verification unit 11 connects two adjacent read-write control circuits RW through the first conductor 08 in the first metal layer, and the first conductor 08 extends along the second direction Y;
  • the first verification unit 12-1 connects the two first-level verification units 11 through a second wire 09 in the second metal layer, and the second wire 09 extends along the first direction X;
  • the second verification unit 12-2 is connected to the two first verification units 12-1 through a second wire 09 in the second metal layer, and the second wire 09 extends along the first direction X.
  • the read and write control circuit RW, the first-level verification unit 11, the first verification unit 12-1 and the second verification unit 12-2 in this embodiment implement data through wires in the metal layer. transmission.
  • the first-level verification unit 11 is located on one side of the read-write control circuit RW in the second direction Y.
  • the first-level verification unit 11 can be connected to the read-write control circuit RW through a wire extending along the second direction Y.
  • the first-level verification unit 11, the first verification unit 12-1 and the second verification unit 12-2 are arranged side by side along the first direction X. Therefore, the first verification unit 12-1 can
  • the first-level verification unit 11 is connected through wires extending along the first direction X
  • the second verification unit 12-2 can be connected to the first verification unit 12-1 through wires extending along the first direction X.
  • the first conductor 08 extending along the second direction Y is arranged in the first metal layer
  • the second conductor 09 extending along the first direction X is arranged in the second metal layer
  • the first-level verification unit 11 is connected to two adjacent read-write control circuits RW through two first wires 08 in the first metal layer
  • the first-level verification unit 12-1 is connected through two first wires 08 in the second metal layer.
  • the second wires 09 are respectively connected to the two first-level verification units 11, and the second verification unit 12-2 is connected to the two first-level verification units 12-1 through a second wire 09 in the second metal layer.
  • the second metal layer is located on the upper layer of the first metal layer.
  • the metal layers of different layers are used as conductors to realize the connection between the read and write control circuit RW and the verification circuit, as well as the connection between the verification circuits, which can reduce Short circuits between different lines in the memory and coupling effects between circuits, thereby improving memory performance.
  • the semiconductor structure further includes: a plurality of subword line drivers 13 (Subword driver, SWD);
  • the sub-word line drivers 13 and the memory cell array 10 are arranged alternately along the first direction X; the sub-word line drivers 13 are used to control the word lines in the memory cell array 10 .
  • word lines may be used as conductors that carry gate voltages required to drive one or more cell transistors of a memory cell.
  • the cell transistor can respond to the potential state of the word line The operation makes it possible to write data to or read data from the memory cell through the cell transistor.
  • line delays caused by such word lines can be considered one of the most important delay factors limiting the operating speed of semiconductor devices.
  • the long word line is divided into multiple sub-word lines, and each sub-word line is controlled by the sub-word line driver 13 .
  • the sub-word line drivers 13 and the memory cell array 10 are alternately arranged along the first direction X.
  • Each sub-word line driver 13 can selectively drive one or more sub-word lines according to the main word line driving signal.
  • the main word line drive signal may represent a memory cell drive signal transmitted through the main word line.
  • the present disclosure also provides a memory, which includes the semiconductor structure according to any one of the preceding embodiments.
  • the memory can be DRAM, static random access memory (Static Random-Access Memory, SRAM), three-dimensional NAND flash memory, two-dimensional NAND flash memory, phase change memory, etc.
  • SRAM static random access memory
  • three-dimensional NAND flash memory three-dimensional NAND flash memory
  • two-dimensional NAND flash memory phase change memory, etc.
  • the present disclosure also provides a layout structure for preparing the semiconductor structure as described above, the layout structure comprising:
  • a plurality of memory cell array layouts arranged side by side along the first direction X;
  • the first data line pattern is located on one side of the read-write control circuit layout close to the memory cell array layout.
  • the memory cell array layout is connected to the corresponding data lines through the first data line patterns. Read and write control circuit layout.
  • the layout structure further includes:
  • a plurality of verification circuit layouts arranged in parallel along the first direction X; at least one of the verification circuit layouts is connected to at least one of the read-write control circuit layouts;
  • the verification circuit layout is located on the side of the read/write control circuit layout away from the memory cell array layout.
  • the verification circuit layout at least includes: a plurality of first-level verification unit layouts, and the first-level verification unit layout is connected to at least one read-write control circuit layout, wherein the first-level verification unit layout is located in the read-write control circuit layout.
  • the write control circuit is arranged away from one side of the memory cell array and along the first direction X.
  • the verification circuit layout further includes: at least one second-level verification unit layout diagram, connecting at least one first-level verification unit layout; wherein the second-level verification unit layout and the first-level verification unit layout are alternately arranged along the first direction X, or the second-level verification unit layout
  • the first-level verification unit layout is located on the side of the first-level verification unit layout away from the read-write control circuit.
  • the verification circuit layout also includes: a verification storage unit layout connected to the second-level verification unit layout.
  • the layout structure also includes: a first metal layer layout and a second metal layer layout; the second metal layer layout is located above the first metal layer layout; the first metal layer layout is used to layout the first metal layer Wires, the second metal layer layout is used to lay out the wires in the second metal layer.
  • the first-level verification unit layout in the layout structure connects two adjacent read-write control circuit layouts.
  • the second-level verification unit layout in the layout structure includes: at least one first verification unit layout and at least one second verification unit layout; the first verification unit layout connects at least one first-level The verification unit layout; the second verification unit layout is connected to at least one first verification unit layout.

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Abstract

公开了一种半导体结构、版图结构以及存储器，该半导体结构包括：沿第一方向并列排布的多个存储单元阵列、位于存储单元阵列在第二方向上的一侧且沿第一方向并列排布的多个读写控制电路，以及位于读写控制电路远离存储单元阵列的一侧的校验电路，第二方向垂直于第一方向；其中，每一读写控制电路通过第一数据线连接对应的一个存储单元阵列，用于控制向存储单元阵列写入或读出数据，校验电路通过第二数据线连接读写控制电路，用于对数据进行校验。

Description

半导体结构、版图结构以及存储器
相关申请的交叉引用
本公开基于申请号为202211157022.X、申请日为2022年09月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构、版图结构以及存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)由于其存储密度高、传输速度快等特点，广泛应用于现代电子系统中。动态随机存储器通常包括核心存储区和外围电路区，其中，核心存储区用于设置多个存储单元，用于对数据信息进行存储，外围电路区通过数据线与存储单元电连接，以使得存储单元完成对数据信息的存储或者读取。
随着半导体技术的发展，存储单元的集成度越来越高，外围电路与存储单元之间的连接线路也越来越复杂，增大存储器的制备工艺难度，同时使得存储器的功耗也越来越高，进而降低存储器的性能。
发明内容
有鉴于此，本公开实施例提供了一种半导体结构、版图结构以及存储器。
第一方面，本公开实施例提供了一种半导体结构，包括：
多个存储单元阵列，所述存储单元阵列沿第一方向并列排布；
沿所述第一方向并列排布的多个读写控制电路，位于所述存储单元阵列在第二方向上的一侧且每一所述读写控制电路通过第一数据线连接对应的一个所述存储单元阵列，所述读写控制电路用于控制向所述存储单元阵列写入或读出数据，所述第二方向垂直于所述第一方向；
校验电路，所述校验电路位于所述读写控制电路远离所述存储单元阵列的一侧且所述校验电路通过第二数据线连接所述读写控制电路，所述校验电路用于对所述数据进行校验。
在一些实施例中，每个所述存储单元阵列连接多条沿所述第二方向延伸的所述第一数据线；
所述读写控制电路包括多个子电路，每个所述子电路通过一条所述第一数据线连接所述读写控制电路对应的所述存储单元阵列。
在一些实施例中，所述校验电路至少包括：
多个第一级校验单元，所述第一级校验单元连接至少一个所述读写控制电路，用于对所述读写控制电路读取的数据或待写入的数据进行校验，得到第一级校验结果；
其中，所述第一级校验单元位于所述读写控制电路远离所述存储单元阵列的一侧且沿所述第一方向排布。
在一些实施例中，所述校验电路还包括：
至少一个第二级校验单元，连接至少一个所述第一级校验单元，用于对所述第一级校验结果进行校验，得到第二级校验结果；
其中，所述第二级校验单元与所述第一级校验单元沿所述第一方向交替排布，或所述第二级校验单元位于所述第一级校验单元远离所述读写控制电路的一侧。
在一些实施例中，所述校验电路还包括：
校验存储单元，与所述第二级校验单元连接，用于存储所述第二级校验结果中的最终校验结果。
在一些实施例中，所述半导体结构，还包括：第一金属层和第二金属层；所述第二金属层位于所述第一金属层上层；所述第一级校验单元与所述读写控制电路通过位于所述第一金属层的导线连接；
所述第二级校验单元与其他所述校验电路通过位于所述第二金属层的导线连接。
在一些实施例中，所述第一级校验单元与所述读写控制电路通过所述第一金属层中的至少一个第一导线连接，所述第一导线沿所述第二方向延伸；
所述第二级校验单元与其他所述校验电路通过所述第二金属层中的至少一个第二导线连接，所述第二导线沿所述第一方向延伸。
在一些实施例中，所述第一级校验单元，连接两个相邻的所述读写控制电路。
在一些实施例中，多个所述第二级校验单元包括：至少一个第一校验单元和至少一个第二校验单元；
所述第一校验单元，连接至少一个所述第一级校验单元，用于对所述第一级校验结果进行第一校验；
所述第二校验单元，连接至少一个所述第一校验单元，用于对所述第一校验的结果进行第二校验，并输出最终校验结果。
在一些实施例中，所述半导体结构，包括：
8个所述存储单元阵列和8个所述读写控制电路，每个所述读写控制电路包括16个子电路；其中，每个所述存储单元阵列通过16条所述第一数据线连接对应的所述读写控制电路的所述子电路；
4个所述第一级校验单元和3个所述第二级校验单元；其中，3个所述第二级校验单元包括：两个第一校验单元和一个第二校验单元；所述第一级校验单元与所述第二级校验单元沿所述第一方向交替排布。
在一些实施例中，所述半导体结构，包括：
所述第一级校验单元通过第一金属层中的第一导线连接两个相邻的所述读写控制电路，所述第一导线沿所述第二方向延伸；
所述第一校验单元通过第二金属层中的第二导线连接两个所述第一级校验单元，所述第二导线沿所述第一方向延伸；
所述第二校验单元通过第二金属层中的第二导线连接两个所述第一校验单元连接，所述第二导线沿所述第一方向延伸。
在一些实施例中，所述半导体结构，还包括：多个子字线驱动器；
所述子字线驱动器与所述存储单元阵列沿所述第一方向交替排布；所述子字线驱动器用于控制所述存储单元阵列中的字线。
第二方面，本公开实施例提供了一种存储器，包括如本公开第一个方面所述的半导体结构。
第三方面，本公开实施例提供了一种版图结构，包括：
多个沿第一方向并列排布的存储单元阵列版图；
与所述存储单元阵列版图一一对应的多个沿所述第一方向并列排布的读写控制电路版图，所述读写控制电路版图位于所述存储单元阵列在第二方向上的一侧，所述第二方向垂直于所述第一方向；
沿所述第二方向延伸的多条第一数据线图形，所述第一数据线图形位于所述读写控制电路版图靠近所述存储单元阵列版图的一侧，所述存储单元阵列版图通过所述第一数据线图形连接对应的所述读写控制电路版图。
在一些实施例中，所述版图结构还包括：
多个沿所述第一方向并列排布的多个校验电路版图；至少一个所述校验电路版图与至少一个所述读写控制电路版图连接；
所述校验电路版图位于所述读写控制电路版图远离所述存储单元阵列版图的一侧。
本公开实施例提供的半导体结构中，存储单元阵列沿第一方向并列排布，读写控制电路位于所述存储单元阵列在第二方向上的一侧且沿第一方向并列排布，第二方向垂直于第一方向；校验电路位于所述读写控制电路远离所述存储单元阵列的一侧。本公开提供的半导体结构，通过将校验电路设置于读写控制电路远离存储单元阵列的一侧，使存储单元阵列与读写控制电路在第二方向上一一对应，使得存储单元阵列与读写控制电路可以通过直线型导线实现连接，优化了读写控制电路与存储单元阵列之间的连接线路，从而降低存储器的制备工艺难度，同时降低存储器在数据传输过程中的功耗，提高数据传输的速度。
附图说明
图1为本公开实施例提供的一种半导体结构的示意图一；
图2为本公开实施例提供的一种半导体结构的示意图二；
图3为本公开实施例提供的半导体结构中的存储单元阵列与读写控制电路的一种连接方式示意图；
图4为本公开实施例提供的一种包括第一级校验电路和第二级校验电路的半导体结构的示意图一；
图5为本公开实施例提供的一种包括第一级校验电路和第二级校验电路的半导体结构的示意图二；
图6为本公开实施例提供的一种包括子字线驱动器的半导体结构的示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图更详细地描述本公开公开 的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在一些实施例中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里可以不描述实际实施例的全部特征，不详细描述公知的功能和结构。
一般地，术语可以至少部分地从上下文中的使用来理解。例如，至少部分地取决于上下文，如本文中所用的术语“一个或多个”可以用于以单数意义描述任何特征、结构或特性，或者可以用于以复数意义描述特征、结构或特性的组合。类似地，诸如“一”或“所述”的术语同样可以被理解为传达单数用法或传达复数用法，这至少部分地取决于上下文。另外，属于“基于”可以被理解为不一定旨在传达排他的一组因素，并且可以替代地允许存在不一定明确地描述的附加因素，这同样至少部分地取决于上下文。
除非另有定义，本文所使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
半导体存储器是一种利用半导体电路进行存取的存储器，其中，DRAM以其快速的存储速度和高集成度被广泛应用于各个领域。
在一些实施例中，在DRAM中设置校验电路，校验读取的数据是否准确，从而获得更高的数据读写可靠性，如图1所示的一种DRAM的局部结构示意图。图1所示的半导体结构包括：多个沿第一方向X并列排布的存储单元阵列10；多个读写控制电路RW和多个纠错码(Error Correcting  Code，ECC)校验电路，读写控制电路RW通过多条数据线与存储单元阵列10连接，用于控制向所述存储单元阵列10写入或读出数据；校验电路通过金属层(未在图中示出)与读写控制电路RW连接，从而获取存储单元阵列10的数据并对其进行校验。
参考图1，读写控制电路RW与ECC校验电路位于存储单元阵列10在垂直于第一方向X的第二方向Y上的一侧，且沿第一方向X交替排布。图1所示的半导体结构的布局方式，虽然使得半导体结构更加紧密，在一定程度上提高存储器的集成度，但是也造成了读写控制电路RW连接的数据线01与存储单元阵列10连接的数据线02在第二方向Y上不能一一对应，在这种情况下，读写控制电路RW与存储单元阵列10不能通过直线型的导线连接，还需要在两者之间的数据线进行跳线处理才能实现导通，如图1所示，在数据线01和数据线02之间增加导线03，使读写控制电路RW与存储单元阵列10之间的线路导通。这样使存储器的电路变得更加复杂，增大存储器制备工艺的难度；并且在数据线之间跳线会增大电路中的电阻，降低数据传输的速度，从而增大存储器的功耗，降低存储器的性能。
有鉴于此，本公开实施例提供一种半导体结构，版图结构以及存储器。
图2为本公开实施例提供的一种半存储块的半导体结构示意图。参考图2所示，该半导体结构，包括：
多个存储单元阵列10，所述存储单元阵列10沿第一方向X并列排布；
沿第一方向X并列排布的多个读写控制电路RW，位于存储单元阵列10在第二方向Y上的一侧且每一读写控制电路RW通过第一数据线04连接对应的一个存储单元阵列10，读写控制电路RW用于控制向所述存储单元阵列10写入或读出数据，第二方向Y垂直于所述第一方向X；
校验电路，位于读写控制电路RW远离所述存储单元阵列10的一侧且通过第二数据线05连接所述读写控制电路RW，校验电路用于对存储单元阵列10中的数据进行校验。
在本公开实施例中，存储单元阵列10用于存储数据，从而实现半导体存储器的存储功能。示例性地，存储单元阵列10中可以包括字线、位线和存储单元等等，存储单元中还进一步包括存储电容和晶体管，晶体管的控制端与字线连接，晶体管的第一端与存储电容连接，晶体管的第二端与位线连接。当字线控制晶体管导通时，存储电容与位线之间导通，从而实现 数据信息的读写，即，当进行数据信息的读取时，存储电容将存储的数据信息传输至位线；当进行数据信息的写入时，位线将待写入的数据信息发送至存储电容。本公开实施例中的多个存储单元阵列10沿第一方向X并列排布，构成一个存储块，该存储块可以是一个完整的存储体20(bank)，也可以是存储体20(bank)的一半，还可以是其他，本公开实施例对此不作限制。
读写控制电路RW是与存储单元阵列10连接并控制存储单元阵列10进行数据读写的逻辑电路模块。例如，读写控制电路RW可以用于接收读写使能信号(如读使能信号RdEn和写使能信号WrEn)，以及将要写入的数据发送至存储单元阵列10或者接收读取的数据，从而实现控制存储单元阵列10写入或读出数据的功能。示例性地，在读写操作期间，读写控制电路RW可以根据写使能信号WrEn执行写入操作以将数据存储到由地址选择的存储单元阵列10中，并且根据读使能信号RdEn执行读取操作以输出存储单元阵列10中存储的数据。
每个读写控制电路RW可以通过第一数据线04连接对应的一个存储单元阵列10，通过第二数据线05连接校验电路，从而实现与存储单元阵列10和校验电路进行数据交互，进而将从存储单元阵列10中写入或读出的数据传输至校验电路。第一数据线04可以是连接至存储单元阵列10，并用于向每个存储单元所连接的电路提供写入数据的信号线。示例性地，可以将要写入的数据通过第一数据线04传递至存储单元所连接的位线，并在写入过程中将位线上的信号进一步传递至存储单元。
校验电路与读写控制电路RW连接，并可以获取从存储单元阵列10读出或要写入存储单元阵列10的数据并进行相应的运算，进而校验存储单元阵列10中的数据信息是否准确，并输出校验结果，从而提高存储单元阵列10的数据读写可靠性。每个校验电路可以用于校验一个或多个存储阵列的数据信息。在本公开实施例中，校验电路可以是奇偶校验电路或者纠错码ECC校验电路，也可以是其他的一种校验电路或多种组合的校验电路等，对此不作限定。
在一实施例中，校验电路具体可以为ECC校验电路，用于存储器和处理器之间传输数据的检错纠错。具体地，在存储器向处理器中传输数据的过程中，当数据从存储器输出时，生成传输数据的ECC校验码，当数据传输至处理器，基于ECC校验码对传输数据进行检错纠错，进行检错纠错后， 舍弃ECC校验码并输出纠正后的数据。在处理器向存储器中传输数据的过程中，当数据从处理器输出时，生成传输数据的ECC校验码，当传输数据传输至存储器，基于ECC校验码对传输数据进行检错纠错，进行检错纠错后，舍弃ECC校验码并输出纠正后的数据。
在本公开实施例中，存储单元阵列10沿第一方向X并列排布；读写控制电路RW位于存储单元阵列10在第二方向Y上的一侧且沿第一方向X并列排布；校验电路位于读写控制电路RW远离所述存储单元阵列10的一侧。
本公开实施例通过将校验电路设置于读写控制电路RW远离存储单元阵列10的一侧，使得每个读写控制电路RW与其对应的存储单元阵列10在第二方向Y上一一对应，使得存储单元阵列10与读写控制电路RW可以通过直线型导线实现连接。相比于将校验电路与读写控制电路RW交替摆放的方式，本公开实施例的设置优化了读写控制电路RW与存储单元阵列10之间的连接线路，从而降低存储器的制备工艺难度，同时降低存储器在数据传输过程中的功耗，提高数据传输的速度。
在一些实施例中，如图3所示，每个存储单元阵列10连接多条沿第二方向Y延伸的第一数据线04；
读写控制电路RW包括多个子电路06，每个子电路06通过一条所述第一数据线04连接读写控制电路RW对应的存储单元阵列10。
在本公开实施例中，每个存储单元阵列10包括多个存储单元，为保证存储单元阵列10写入或读出数据的效率，每个存储单元阵列10通过多条第一数据线04与读写控制电路RW连接。存储单元阵列10可以通过第一数据线04接收要写入的数据或者输出存储的数据。本公开实施例中每个存储单元阵列10连接的多条第一数据线04沿第一方向X并列排布，且第一数据线04为沿第二方向Y延伸的直线型导线。
读写控制电路RW中的子电路06是与存储单元阵列10连接并控制存储单元阵列10进行数据读写的逻辑电路模块。读写控制电路RW中的子电路06位于其对应的存储单元阵列10在第二方向Y的一侧，多个子电路06沿第一方向X并列排布，存储单元阵列10连接的多条第一数据线04与其对应的读写控制电路RW中的子电路06在第二方向Y上一一对应，每个子电路06通过一条第一数据线04连接读写控制电路RW对应的存储单元阵列10，从而读写控制电路RW可以通过多条第一数据线04 接收读取的数据或者存储单元阵列10将要写入的数据发送至存储单元阵列10。
本公开通过使存储单元阵列10连接的第一数据线04与读写控制电路RW中的子电路06在第二方向Y上一一对应，使得沿第二方向Y延伸的直线型的第一数据线04可以连接存储单元阵列10与读写控制电路RW。由于读写控制电路RW位于其对应的存储单元阵列10在第二方向Y上的一侧，本公开的设置进一步优化了读写控制电路RW与存储单元阵列10之间的连接线路，降低存储器的制备工艺难度。
在一些实施例中，如图4所示，校验电路至少包括：
多个第一级校验单元11，第一级校验单元11连接至少一个读写控制电路RW，用于对读写控制电路RW读取的数据或待写入的数据进行校验，得到第一级校验结果；
其中，第一级校验单元11位于读写控制电路RW远离存储单元阵列10的一侧且沿第一方向X排布。
第一级校验单元11是与读写控制电路RW连接并对读写控制电路RW读取的数据或待写入的数据进行校验的计算电路模块，第一级校验单元11通过第二数据线05连接读写控制电路RW，每个第一级校验单元11可以连接一个或者多个读写控制电路RW，并对其所连接的一个或多个读写控制电路RW中读取的数据或待写入的数据进行校验，得到第一级校验结果。示例性的，如果第一级校验单元11连接两个读写控制电路RW，则在一次校验过程中，同时对两个读写控制电路RW对应的两个存储单元阵列10中的数据进行校验，得到第一级校验结果。
第一级校验单元11位于读写控制电路RW远离存储单元阵列10的一侧，第一级校验单元11可以沿第一方向X并列排布，也可以沿第一方向X分散排布。在本公开实施例中，第一校验单元12-1沿第一方向X分散排布，使得每个第一级校验单元11尽可能靠近与其对应的读写控制电路RW，从而缩短第一级校验单元11与读写控制电路RW之间的连接线路，减小线路中的电阻，从而降低存储器在数据传输过程中的功耗；同时使得第一级校验单元11与读写控制电路RW之间的连接更加容易实现，优化读写控制电路RW与第一级校验单元11之间的连接线路，降低存储器的制备工艺难度。
需要说明的是，第一级校验单元11在一次校验过程中能够校验的数据 是有限的，可以根据第一级校验单元11每次能够校验的数据的字节数以及每个存储单元阵列10所能储存的数据的字节数，来确定一个第一级校验单元11一次能够校验的存储单元阵列10的数量，进而确定一个第一级校验单元11连接的读写控制电路RW的数量。例如，每个存储单元阵列10一次读或一次写16比特数据，第一级校验单元11每次可以同时对32比特数据进行校验，则每个第一级校验单元11一次可以校验2个存储单元阵列10中的数据，因此，每个第一级校验单元11可以连接2个读写控制电路RW，对这2个读写控制电路RW连接的2个存储单元阵列10中的数据进行校验，得到第一级校验结果。
另一方面，也可以根据第一级校验单元11每次能够校验的数据量，以及存储块中的所有存储单元阵列10一次读或一次写的数据量，来确定存储体20所需的第一级校验单元11的数量。例如，半个存储体20中包含8个存储单元阵列10，每个存储单元阵列10能够一次读或一次写16比特数据，即一次读或一次写128比特数据，第一级校验单元11每次可以同时对32字节数据进行校验，则该半个存储体20需要4个第一级校验单元11。
在一些实施例中，如图4所示，所述校验电路还包括：
至少一个第二级校验单元12，连接至少一个第一级校验单元11，用于对第一级校验结果进行校验，得到第二级校验结果；
其中，第二级校验单元12与第一级校验单元11沿第一方向X交替排布，或第二级校验单元12位于第一级校验单元11远离读写控制电路RW的一侧。
需要说明的是，校验电路每次能够校验的数据是有限的，为了提高校验电路的校验速度和校验效率，以保证半导体存储器中数据读写可靠性，校验电路中可以通过设置不同等级的校验单元对存储单元中的数据进行多次校验。
在本实施例中，如图4所示，校验电路包括第一级校验单元11和第二级校验单元12，第一级校验单元11是与读写控制电路RW连接并对读写控制电路RW读取的数据或待写入的数据进行校验的计算电路模块，第二级校验单元12是与第一级校验单元11连接并对第一级校验结果进行校验的计算电路模块。示例性地，校验电路中的第一级校验单元11首先对存储单元阵列10中的数据进行校验，得到第一级校验结果；第一级校验单元11通过第三数据线07与第二级校验单元12连接，并通过第三数据线07将第 一级校验结果传输至第二级校验单元12，然后第二级校验单元12对第一校验结果进行校验，得到第二级校验结果。
在本公开实施例中，如图4所示，第二级校验单元12与第一级校验单元11均位于读写控制电路RW远离所述存储单元阵列10的一侧，且第二级校验单元12与第一级校验单元11沿第一方向X交替排布，使第二级校验单元12位于其连接的第一级校验单元11之间，从而缩短第二级校验单元12与第一级校验单元11之间的连接线路，减小线路中的电阻，从而降低存储器在数据传输过程中的功耗；同时使得第二级校验单元12与第一级校验单元11之间的连接更加容易实现，优化第二级校验单元12与第一级校验单元11之间的连接线路，降低存储器的制备工艺难度。
在一示例中，如图5所示，第一级校验单元11位于读写控制电路RW远离存储单元阵列10的一侧，第二级校验单元12位于第一级校验单元11远离所述读写控制电路RW的一侧，使读写控制电路RW，第一级校验单元11与第二级校验单元12沿第二方向Y依次排布。其中，第一级校验单元11与读写控制电路RW通过第二数据线05连接，第二级校验单元12与第一级校验单元11通过第三数据线07连接，第二数据线05与第三数据线07的走线方向相同。示例性的，第二数据线05与第三数据线07均沿第二方向Y延伸，有利于在同一个制程工艺中同时形成第二数据线05和第三数据线07，从而简化工艺流程。
需要说明的是，第二级校验单元12可以连接一个第一级校验单元11，也可以连接多个第一级校验单元11。第二级校验单元12每次能够校验的数据是有限的，通过第二级校验单元12每次能够校验的数据的字节数以及第一级校验结果中的数据的字节数，来确定第二级校验单元12所连接的第一级校验单元11的数量。例如，第一级校验单元11每次可以校验32字节数据，即第一级校验单元11中包括该32字节数据的第一级校验结果；如果第二级校验单元12每次可以校验64字节数据的第一级校验结果，则每个第二级校验单元12可以连接两个第一级校验单元11。
在一些实施例中，所述校验电路还包括：
校验存储单元，与第二级校验单元12连接，用于存储第二级校验结果中的最终校验结果。
校验存储单元是一个逻辑电路模块，可以控制将校验电路中的最终校验结果存储到对应的存储单元阵列10中。在存储器向处理器中传输数据的 过程中，当数据从存储器输出时，校验电路对数据进行校验并生成最终校验结果；当数据传输至处理器，基于最终校验结果对传输的数据进行检错纠错，进行检错纠错后，舍弃最终校验结果并输出纠正后的数据。
在本实施例中，校验电路首先通过连接的第一级校验单元11对存储单元阵列10中的数据进行校验，得到第一级校验结果；再通过第二级校验单元12对第一校验结果进行校验，得到第二级校验结果，第二级校验结果中至少包括一个最终校验结果；第二级校验单元12通过第四数据线与校验存储单元连接，并通过第四数据线将第二级校验结果中的最终校验结构传输至校验存储单元，校验存储单元接收并存储第二级校验结果中的最终校验结果；最后，校验存储单元控制将最终的校验结果存储到对应的存储单元阵列10中。
在一些实施例中，所述半导体结构，还包括：第一金属层和第二金属层；第二金属层位于第一金属层上层；
第一级校验单元11与读写控制电路RW通过位于所述第一金属层的导线连接；
第二级校验单元12与其他校验电路通过位于所述第二金属层的导线连接。
第一金属层和第二金属层主要用于作为导体，可以导通读写控制电路，第一级校验单元以及第二级校验单元之间的连接。第一金属层和第二金属层的材料包括但不限于钛、钽、钯、镍、铂、钴、钨、锆、钼，可以通过化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic Layer Deposition，ALD)或物理气相沉积(Physical Vapor Deposition，PVD)等形成。
如图4所示，第一级校验单元11通过多条第二数据线05与读写控制电路RW连接；第二级校验单元12通过第三数据线07与其他校验电路连接，其他校验电路包括第一级校验单元11以及其他第二级校验单元12。这里，第二数据线05可以是位于第一金属层中的导线，第三数据线07可以是位于第二金属层的导线，即第一级校验单元11与读写控制电路RW通过位于第一金属层的导线连接，第二级校验单元12与其他校验电路通过位于第二金属层的导线连接。
示例性的，如图4所示，第一级校验单元11位于读写控制电路RW在第二方向上的一侧，连接第一级校验单元11与读写控制电路RW的第二数 据线05可以沿第二方向Y延伸；第二级校验电路与第一级校验电路沿第一方向X交替排布，第二级校验单元12与其他校验电路(第一级校验单元11或其他第二级校验单元12)的第三数据线07可以沿第一方向X延伸，因此，图4所示半导体结构中的第二数据线05和第三数据线07相互垂直。
通过不同层的金属层作为导体来实现读写控制电路RW与校验电路之间的连接，以及校验电路之间的连接，可以减少存储器中不同线路之间的短路以及电路之间的耦合效应，进而提高存储器的性能。
在一些实施例中，第一级校验单元11与读写控制电路RW通过第一金属层中的至少一个第一导线08连接，第一导线08沿所述第二方向Y延伸；
第二级校验单元12与其他校验电路通过第二金属层中的至少一个第二导线09连接，第二导线09沿第一方向X延伸。
如图4所示，本实施例中的读写控制电路RW位于存储单元阵列10在第二方向Y上的一侧，第一级校验单元11位于读写控制电路RW远离存储单元阵列10的一侧，即第一级校验单元11位于读写控制电路RW在第二方向Y上的一侧，因此，第一级校验单元11可以通过沿第二方向Y延伸的导线连接读写控制电路RW。本实施例中的第一级校验单元11和第二级校验单元12沿第一方向X交替排布，因此，第二校验单元12-2可以通过沿第一方向X延伸的导线连接第一级校验单元11或其他第二级校验单元12。
在本实施例中，如图4所示，在第一金属层中布置沿第二方向Y延伸的第一导线08，在第二金属层布置沿第一方向X延伸的第二导线09，第一级校验单元11与读写控制电路RW通过第一金属层中的一个或者多个第一导线08连接，第一导线08可以将读写控制电路RW读取的数据或待写入的数据传输至第一级校验单元11；第二级校验单元12与其他校验电路(第一级校验单元11或者其他第二级校验单元12)通过第二金属层中的一个或多个第二导线09连接，第二导线09可以实现第二级校验单元12与第一级校验单元11之间的数据交互，以及多个第二级校验单元12之间的数据交互。
在一些实施例中，如图4所示，第一级校验单元11连接两个相邻的读写控制电路RW。
在本实施例中，第一级校验单元11可以同时对两个存储单元阵列10中的数据进行校验，每个存储单元阵列10通过一个读写控制电路RW将数 据传输至第一级校验单元11，因此，第一级校验单元11通过连接两个读写控制电路RW，对两个存储单元阵列10中的数据同时进行校验。
在本实施例中，第一级校验单元11连接的两个读写控制电路RW相邻，可以缩短第一级校验单元11与读写控制电路RW之间的连接线路，减小电路中的电阻。
在一些实施例中，如图4所示，多个第二级校验单元12包括：至少一个第一校验单元12-1和至少一个第二校验单元12-2；
第一校验单元12-1，连接至少一个所述第一级校验单元11，用于对第一级校验结果进行第一校验；
第二校验单元12-2，连接至少一个所述第一校验单元12-1，用于对第一校验的结果进行第二校验，并输出最终校验结果。
在本实施例中，如图4所示，校验电路通过第一级校验单元11，第一校验单元12-1以及第二校验单元12-2对存储单元阵列10中的数据进行校验。具体地，校验电路首先通过第一级校验单元11对存储单元阵列10中的数据进行校验，得到第一级校验结果；第一级校验单元11通过第三数据线07与第二级校验单元12中的第一校验单元12-1连接，并通过第三数据线07将第一级校验结果传输至第一校验单元12-1，第一校验对第一级校验结果进行第一校验；第二级校验单元12中的第一校验单元12-1通过第五数据线与第二校验单元12-2连接，并通过第五数据线将第一校验的结果传输至第二校验单元12-2，第二校验单元12-2对第一校验的结果进行第二校验，并输出最终校验结果。
在一些实施例中，如图4所示的半导体结构，包括：
8个存储单元阵列10和8个读写控制电路RW，每个读写控制电路RW包括16个子电路06；其中，每个存储单元阵列10通过16条所述第一数据线04连接对应的读写控制电路RW的子电路06；
4个第一级校验单元11和3个第二级校验单元12；其中，3个第二级校验单元12包括：两个第一校验单元12-1和一个第二校验单元12-2；第一级校验单元11与第二级校验单元12沿第一方向X交替排布。
如图4所示，本实施例提供的半导体结构包括8个存储单元阵列10，8个读写控制电路RW，4个第一级校验单元11以及3个第二级校验单元12。其中，8个存储单元阵列10沿第一方向X并列排布，8个读写控制电路RW位于存储单元阵列10在第二方向Y上的一侧且沿第一方向X并列排布；4 个第一级校验单元11和3个第二级校验单元12位于读写控制电路RW远离存储单元阵列10的一侧，且第一级校验单元11与所述第二级校验单元12沿所述第一方向X交替排布。本公开实施例通过将校验电路设置于读写控制电路RW远离存储单元阵列10的一侧，使得每个读写控制电路RW与其对应的存储单元阵列10在第二方向Y上一一对应，从而优化了读写控制电路RW与存储单元阵列10之间的连接线路，从而降低存储器的制备工艺难度，同时减小电路的电阻，降低存储器在数据传输过程中的功耗，提高数据传输的速度。
在本实施例中，如图4所示，存储单元阵列10通过第一数据线04与读写控制电路RW进行数据传输，且第一数据线04沿第二方向Y延伸；如图5所示，每个读写控制电路RW包括16个子电路06，连接存储单元阵列10的第一数据线04与读写控制电路RW中的子电路06在第二方向Y上一一对应，每个子电路06连接对应的存储单元阵列10中的一条第一数据线04，即每个存储单元阵列10通过16条第一数据线04连接对应的读写控制电路RW的16个子电路06。本实施例通过使连接存储单元阵列10的第一数据线04与读写控制电路RW中的子电路06在第二方向Y上一一对应，使得存储单元阵列10与读写控制电路RW可以通过直线连接，即存储单元阵列10与读写控制电路RW不用通过跳线就可以直接连接，优化了读写控制电路RW与存储单元阵列10之间的连接线路。
在本实施例中，如图4所示，第一级校验单元11可以同时对两个存储单元阵列10中的数据进行校验，每个存储单元阵列10通过一个读写控制电路RW将数据传输至第一级校验单元11，因此，本实施例中的每个第一级校验单元11连接两个相邻的读写控制电路RW，第一级校验单元11通过读写控制电路RW获取其对应的存储单元阵列10中的数据，对两个存储单元阵列10中的数据同时进行校验，得到第一级校验结果。
在本实施例中，如图4所示，第二级校验单元12中的第一校验单元12-1可以同时对两个第一级校验结果进行第一校验，第二校验单元12-2可以同时对两个第一校验单元12-1的校验结果进行第二校验。本实施例中的第一校验单元12-1连接两个第一级校验单元11，且每个第一级校验单元11仅与一个第一校验单元12-1连接；第一校验单元12-1对所连接的第一级校验单元11的第一级校验结果进行第一校验；第二校验单元12-2连接两个第一校验单元12-1，对两个第一校验单元12-1中的第一校验结果进行第二校验， 得到最终校验结果。
在一些实施例中，半导体结构包括：
第一级校验单元11通过第一金属层中的第一导线08连接两个相邻的读写控制电路RW，第一导线08沿第二方向Y延伸；
第一校验单元12-1通过第二金属层中的第二导线09连接两个第一级校验单元11，所述第二导线09沿第一方向X延伸；
第二校验单元12-2通过第二金属层中的第二导线09连接两个第一校验单元12-1连接，所述第二导线09沿第一方向X延伸。
如图4所示，本实施例中的读写控制电路RW，第一级校验单元11，第一校验单元12-1以及第二校验单元12-2通过金属层中的导线实现数据传输。第一级校验单元11位于读写控制电路RW在第二方向Y上的一侧，第一级校验单元11可以通过沿第二方向Y延伸的导线连接读写控制电路RW。本实施例中的第一级校验单元11，第一校验单元12-1以及第二校验单元12-2沿第一方向X并列排布，因此，第一校验单元12-1可以通过沿第一方向X延伸的导线连接第一级校验单元11，第二校验单元12-2可以通过沿第一方向X延伸的导线连接第一校验单元12-1。
在本实施例中，如图4所示，在第一金属层中布置沿第二方向Y延伸的第一导线08，在第二金属层布置沿第一方向X延伸的第二导线09，使第一级校验单元11通过第一金属层中的两条第一导线08分别连接两个相邻的读写控制电路RW，第一校验单元12-1通过第二金属层中的两条第二导线09分别连接两个第一级校验单元11，第二校验单元12-2通过第二金属层中的一条第二导线09连接两个第一校验单元12-1。本实施例中第二金属层位于第一金属层上层，通过不同层的金属层作为导体来实现读写控制电路RW与校验电路之间的连接，以及校验电路之间的连接，可以减少存储器中不同线路之间的短路以及电路之间的耦合效应，进而提高存储器的性能。
在一些实施例中，如图6所示，半导体结构还包括：多个子字线驱动器13(Subword driver，SWD)；
子字线驱动器13与存储单元阵列10沿第一方向X交替排布；子字线驱动器13用于控制存储单元阵列10中的字线。
在半导体装置中，字线可以用作传送驱动存储器单元的一个或多个单元晶体管所需的栅极电压的导线。单元晶体管可以响应于字线的电位状态 而操作，使得可以通过单元晶体管将数据写入存储器单元或从存储器单元读取数据。随着芯片尺寸和芯片的存储器容量的增加，由此类字线引起的线延迟可以被认为是限制半导体装置的操作速度的最重要的延迟因素之一。为了使此类字线的线延迟最小化，将长字线划分为多条子字线，通过子字线驱动器13控制每条子字线。
本实施例中的子字线驱动器13与存储单元阵列10沿第一方向X交替排布，每个子字线驱动器13可以根据主字线驱动信号而选择性地驱动一条或更多条子字线，主字线驱动信号可以表示通过主字线传输的存储器单元驱动信号。
本公开还提供了一种存储器，该存储器包括前述实施例任一项所述的半导体结构。
示例地，该存储器可以是DRAM、静态随机存取存储器(Static Random-Access Memory，SRAM)、三维NAND闪存存储器、二维NAND闪存存储器、相变存储器等。
本公开还提供了一种版图结构，用于制备如上所述的半导体结构，该版图结构包括：
多个沿第一方向X并列排布的存储单元阵列版图；
与存储单元阵列版图一一对应的多个沿第一方向X并列排布的读写控制电路版图，读写控制电路版图位于存储单元阵列在第二方向Y上的一侧，第二方向Y垂直于所述第一方向X；
沿所述第二方向Y延伸的多条第一数据线图形，第一数据线图形位于读写控制电路版图靠近存储单元阵列版图的一侧，存储单元阵列版图通过第一数据线图形连接对应的读写控制电路版图。
在一些实施例中，所述版图结构还包括：
多个沿第一方向X并列排布的多个校验电路版图；至少一个所述校验电路版图与至少一个所述读写控制电路版图连接；
校验电路版图位于读写控制电路版图远离存储单元阵列版图的一侧。
在一些实施例中，校验电路版图至少包括：多个第一级校验单元版图，第一级校验单元版图连接至少一个读写控制电路版图，其中，第一级校验单元版图位于读写控制电路远离存储单元阵列的一侧且沿所述第一方向X排布。
在一些实施例中，校验电路版图还包括：至少一个第二级校验单元版 图，连接至少一个第一级校验单元版图；其中，所述第二级校验单元版图与所述第一级校验单元版图沿所述第一方向X交替排布，或所述第二级校验单元版图位于所述第一级校验单元版图远离所述读写控制电路的一侧。
在一些实施例中，校验电路版图还包括：校验存储单元版图，与第二级校验单元版图连接。
在一些实施例中，版图结构还包括：第一金属层版图和第二金属层版图；第二金属层版图位于第一金属层版图上层；第一金属层版图用来布局第一金属层中的导线，第二金属层版图用来布局第二金属层中的导线。
在一些实施例中，版图结构中的第一级校验单元版图，连接两个相邻的读写控制电路版图。
在一些实施例中，版图结构中的第二级校验单元版图包括：至少一个第一校验单元版图和至少一个第二校验单元版图；第一校验单元版图，连接至少一个第一级校验单元版图；第二校验单元版图，连接至少一个第一校验单元版图。
上述实施例仅例示性说明本公开的原理及其功效，而非用于限制本公开。任何熟悉此技术的人士皆可在不违背本公开的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本公开所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本公开的权利要求所涵盖。

Claims (15)

  1. 一种半导体结构，包括：
    多个存储单元阵列(10)，所述存储单元阵列(10)沿第一方向(X)并列排布；
    沿所述第一方向(X)并列排布的多个读写控制电路(RW)，位于所述存储单元阵列(10)在第二方向(Y)上的一侧且每一所述读写控制电路(RW)通过第一数据线(04)连接对应的一个所述存储单元阵列(10)，所述读写控制电路(RW)用于控制向所述存储单元阵列(10)写入或读出数据，所述第二方向(Y)垂直于所述第一方向(X)；
    校验电路，所述校验电路位于所述读写控制电路(RW)远离所述存储单元阵列(10)的一侧且所述校验电路通过第二数据线(05)连接所述读写控制电路(RW)，所述校验电路用于对所述数据进行校验。
  2. 根据权利要求1所述的半导体结构，其中，
    每个所述存储单元阵列(10)连接多条沿所述第二方向(Y)延伸的所述第一数据线(04)；
    所述读写控制电路(RW)包括多个子电路(06)，每个所述子电路(06)通过一条所述第一数据线(04)连接所述读写控制电路(RW)对应的所述存储单元阵列(10)。
  3. 根据权利要求2所述的半导体结构，其中，所述校验电路至少包括：
    多个第一级校验单元(11)，所述第一级校验单元(11)连接至少一个所述读写控制电路(RW)，用于对所述读写控制电路(RW)读取的数据或待写入的数据进行校验，得到第一级校验结果；
    其中，所述第一级校验单元(11)位于所述读写控制电路(RW)远离所述存储单元阵列(10)的一侧且沿所述第一方向(X)排布。
  4. 根据权利要求3所述的半导体结构，其中，所述校验电路还包括：
    至少一个第二级校验单元(12)，连接至少一个所述第一级校验单元(11)，用于对所述第一级校验结果进行校验，得到第二级校验结果；
    其中，所述第二级校验单元(12)与所述第一级校验单元(11)沿所述第一方向(X)交替排布，或所述第二级校验单元(12)位于所述第一级校验单元(11)远离所述读写控制电路(RW)的一侧。
  5. 根据权利要求4所述的半导体结构，其中，所述校验电路还包括：
    校验存储单元，与所述第二级校验单元(12)连接，用于存储所述第二级校验结果中的最终校验结果。
  6. 根据权利要求4或5所述的半导体结构，所述半导体结构，还包括：第一金属层和第二金属层；所述第二金属层位于所述第一金属层上层；所述第一级校验单元(11)与所述读写控制电路(RW)通过位于所述第一金属层的导线连接；
    所述第二级校验单元(12)与其他所述校验电路通过位于所述第二金属层的导线连接。
  7. 根据权利要求6所述的半导体结构，其中，
    所述第一级校验单元(11)与所述读写控制电路(RW)通过所述第一金属层中的至少一个第一导线(08)连接，所述第一导线(08)沿所述第二方向(Y)延伸；
    所述第二级校验单元(12)与其他所述校验电路通过所述第二金属层中的至少一个第二导线(09)连接，所述第二导线(09)沿所述第一方向(X)延伸。
  8. 根据权利要求4-7中任一项所述的半导体结构，其中，所述第一级校验单元(11)，连接两个相邻的所述读写控制电路(RW)。
  9. 根据权利要求4-8中任一项所述的半导体结构，其中，多个所述第二级校验单元(12)包括：至少一个第一校验单元(12-1)和至少一个第二校验单元(12-2)；
    所述第一校验单元(12-1)，连接至少一个所述第一级校验单元(11)，用于对所述第一级校验结果进行第一校验；
    所述第二校验单元(12-2)，连接至少一个所述第一校验单元(12-1)，用于对所述第一校验的结果进行第二校验，并输出最终校验结果。
  10. 根据权利要求9所述的半导体结构，其中，所述半导体结构，包括：
    8个所述存储单元阵列(10)和8个所述读写控制电路(RW)，每个所述读写控制电路(RW)包括16个子电路(06)；其中，每个所述存储单元阵列(10)通过16条所述第一数据线(04)连接对应的所述读写控制电路(RW)的所述子电路(06)；
    4个所述第一级校验单元(11)和3个所述第二级校验单元(12)；其中，3个所述第二级校验单元(12)包括：两个第一校验单元(12-1)和一 个第二校验单元(12-2)；所述第一级校验单元(11)与所述第二级校验单元(12)沿所述第一方向(X)交替排布。
  11. 根据权利要求10所述的半导体结构，其中，所述半导体结构，包括：
    所述第一级校验单元(11)通过第一金属层中的第一导线(08)连接两个相邻的所述读写控制电路(RW)，所述第一导线(08)沿所述第二方向(Y)延伸；
    所述第一校验单元(12-1)通过第二金属层中的第二导线(09)连接两个所述第一级校验单元(11)，所述第二导线(09)沿所述第一方向(X)延伸；
    所述第二校验单元(12-2)通过第二金属层中的第二导线(09)连接两个所述第一校验单元(12-1)连接，所述第二导线(09)沿所述第一方向(X)延伸。
  12. 根据权利要求1-11中任一项所述的半导体结构，所述半导体结构，还包括：多个子字线驱动器(13)；
    所述子字线驱动器(13)与所述存储单元阵列(10)沿所述第一方向(X)交替排布；所述子字线驱动器(13)用于控制所述存储单元阵列(10)中的字线。
  13. 一种存储器，包括：
    如权利要求1至12任一所述的半导体结构。
  14. 一种存储器的版图结构，包括：
    多个沿第一方向(X)并列排布的存储单元阵列版图；
    与所述存储单元阵列版图一一对应的多个沿所述第一方向(X)并列排布的读写控制电路版图，所述读写控制电路版图位于所述存储单元阵列在第二方向(Y)上的一侧，所述第二方向(Y)垂直于所述第一方向(X)；
    沿所述第二方向(Y)延伸的多条第一数据线图形，所述第一数据线图形位于所述读写控制电路版图靠近所述存储单元阵列版图的一侧，所述存储单元阵列版图通过所述第一数据线图形连接对应的所述读写控制电路版图。
  15. 根据权利要求14所述的版图结构，还包括：
    多个沿所述第一方向(X)并列排布的多个校验电路版图；至少一个所述校验电路版图与至少一个所述读写控制电路版图连接；
    所述校验电路版图位于所述读写控制电路版图远离所述存储单元阵列版图的一侧。
PCT/CN2023/089247 2022-09-21 2023-04-19 半导体结构、版图结构以及存储器 Ceased WO2024060604A1 (zh)

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