WO2024058044A1 - 炭化珪素エピタキシャル基板、エピタキシャル基板の製造方法および炭化珪素半導体装置の製造方法 - Google Patents

炭化珪素エピタキシャル基板、エピタキシャル基板の製造方法および炭化珪素半導体装置の製造方法 Download PDF

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WO2024058044A1
WO2024058044A1 PCT/JP2023/032681 JP2023032681W WO2024058044A1 WO 2024058044 A1 WO2024058044 A1 WO 2024058044A1 JP 2023032681 W JP2023032681 W JP 2023032681W WO 2024058044 A1 WO2024058044 A1 WO 2024058044A1
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silicon carbide
layer
epitaxial substrate
concentration
substrate
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French (fr)
Japanese (ja)
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太郎 榎薗
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to US19/109,788 priority patent/US20260082649A1/en
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
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    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
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Definitions

  • the present disclosure relates to a silicon carbide epitaxial substrate, a method for manufacturing an epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device.
  • This application claims priority based on Japanese Patent Application No. 2022-145264, which is a Japanese patent application filed on September 13, 2022. All contents described in the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 discloses a method for manufacturing a silicon carbide semiconductor device including a step of measuring the thickness of an epitaxial layer using Fourier transform infrared spectroscopy.
  • a silicon carbide epitaxial substrate includes a silicon carbide substrate and a silicon carbide epitaxial layer.
  • a silicon carbide epitaxial layer is provided on a silicon carbide substrate.
  • the silicon carbide epitaxial layer includes a boundary layer, a buffer layer, and a drift layer.
  • a boundary layer is provided on the silicon carbide substrate.
  • a buffer layer is provided on the boundary layer.
  • the drift layer is provided on the buffer layer.
  • the concentration of n-type impurities in the buffer layer is 3 ⁇ 10 18 /cm 3 or more.
  • the concentration of n-type impurities in the boundary layer is higher than the concentration of n-type impurities in the buffer layer.
  • FIG. 1 is a schematic plan view showing the structure of a silicon carbide epitaxial substrate according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a schematic diagram showing the relationship between the concentration of n-type impurities and the depth in the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 4 is a schematic cross-sectional view showing the structure of the epitaxial substrate according to this embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the structure of an epitaxial substrate according to a modification of this embodiment.
  • FIG. 6 is a schematic partial cross-sectional view showing the configuration of an epitaxial substrate manufacturing apparatus.
  • FIG. 1 is a schematic plan view showing the structure of a silicon carbide epitaxial substrate according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a schematic diagram showing the relationship between the concentration of n-type
  • FIG. 7 is a flowchart schematically showing a method for manufacturing an epitaxial substrate according to this embodiment.
  • FIG. 8 is a schematic cross-sectional view showing the process of measuring the first distance.
  • FIG. 9 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment.
  • FIG. 10 is a schematic cross-sectional view showing the process of forming the body region.
  • FIG. 11 is a schematic cross-sectional view showing the process of forming a source region.
  • FIG. 12 is a schematic cross-sectional view showing a step of forming a trench on the fifth main surface of the second silicon carbide epitaxial layer.
  • FIG. 13 is a schematic cross-sectional view showing the process of forming a gate insulating film.
  • FIG. 14 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film.
  • FIG. 15 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.
  • FIG. 16 is a schematic cross-sectional view showing a step of measuring the first distance in a silicon carbide epitaxial substrate according to a comparative example.
  • FIG. 17 is a graph showing the results of FTIR measurements on the silicon carbide epitaxial substrate according to Sample 1.
  • FIG. 18 is a graph showing FTIR measurement results for the silicon carbide epitaxial substrate of Sample 2.
  • An object of the present disclosure is to provide a silicon carbide epitaxial substrate, a method for manufacturing an epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device that can improve the accuracy of measuring the thickness of a silicon carbide epitaxial layer.
  • Silicon carbide epitaxial substrate 100 includes first silicon carbide substrate 30 and first silicon carbide epitaxial layer 40.
  • First silicon carbide epitaxial layer 40 is provided on first silicon carbide substrate 30 .
  • First silicon carbide epitaxial layer 40 includes a first boundary layer 41 , a first buffer layer 42 , and a first drift layer 43 .
  • First boundary layer 41 is provided on first silicon carbide substrate 30 .
  • the first buffer layer 42 is provided on the first boundary layer 41 .
  • the first drift layer 43 is provided on the first buffer layer 42 .
  • the concentration C2 of n-type impurities in the first buffer layer 42 is 3 ⁇ 10 18 /cm 3 or more.
  • the n-type impurity concentration C3 in the first boundary layer 41 is higher than the n-type impurity concentration C2 in the first buffer layer 42.
  • the n-type impurity concentration C3 in the first boundary layer 41 is higher than the n-type impurity concentration C4 in the first silicon carbide substrate 30. good.
  • the n-type impurity concentration C2 in the first buffer layer 42 is subtracted from the n-type impurity concentration C3 in the first boundary layer 41.
  • the value may be 1 ⁇ 10 18 /cm 3 or more.
  • the thickness T1 of the first boundary layer 41 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the n-type impurity concentration C2 in the first buffer layer 42 is the n-type impurity concentration C2 in the first drift layer 43. It may be higher than C1.
  • the n-type impurity concentration C3 in the first boundary layer 41 is 5 ⁇ 10 18 /cm 3 or more and 1 ⁇ 10 20 /cm 3 or less.
  • the n-type impurity concentration C2 in the first buffer layer 42 is 1 ⁇ 10 19 /cm 3 or less. Good too.
  • the n-type impurity concentration C1 in the first drift layer 43 is 1 ⁇ 10 15 /cm 3 or more and 5 ⁇ 10 16 /cm 3 or less.
  • a method for manufacturing an epitaxial substrate 200 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 100 according to any one of (1) to (8) above is prepared. Using silicon carbide epitaxial substrate 100, distance E1 from interface 9 between first boundary layer 41 and first buffer layer 42 to the surface (first main surface 1) of silicon carbide epitaxial substrate 100 is measured. Growth conditions are determined based on the measured distance E1. Epitaxial growth is performed using the determined growth conditions.
  • a method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps.
  • the epitaxial substrate 200 is manufactured using the method for manufacturing the epitaxial substrate 200 described in (9) above.
  • Epitaxial substrate 200 is processed.
  • FIG. 1 is a schematic plan view showing the configuration of a silicon carbide epitaxial substrate 100 according to this embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • silicon carbide epitaxial substrate 100 according to this embodiment includes a first silicon carbide substrate 30 and a first silicon carbide epitaxial layer 40.
  • First silicon carbide epitaxial layer 40 is provided on first silicon carbide substrate 30 .
  • First silicon carbide epitaxial layer 40 is in contact with first silicon carbide substrate 30 .
  • First silicon carbide epitaxial layer 40 has first main surface 1 .
  • First silicon carbide epitaxial layer 40 constitutes the surface (first main surface 1) of silicon carbide epitaxial substrate 100.
  • First silicon carbide substrate 30 constitutes the back surface (second main surface 2) of silicon carbide epitaxial substrate 100.
  • silicon carbide epitaxial substrate 100 has an outer peripheral edge 6.
  • the outer peripheral edge 6 has, for example, an orientation flat 7 and an arcuate portion 8.
  • the orientation flat 7 is linear when viewed in a direction perpendicular to the first main surface 1.
  • the orientation flat 7 extends along a first direction 101.
  • the arcuate portion 8 is continuous with the orientation flat 7.
  • the arcuate portion 8 has an arcuate shape when viewed in a direction perpendicular to the first principal surface 1 .
  • the first main surface 1 when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102.
  • the second direction 102 is a direction perpendicular to the first direction 101.
  • the first direction 101 is, for example, the ⁇ 11-20> direction.
  • the first direction 101 may be, for example, the [11-20] direction.
  • the first direction 101 may be, for example, a direction in which the ⁇ 11-20> direction is projected onto the first principal surface 1. From another perspective, the first direction 101 may be a direction including a ⁇ 11-20> direction component, for example.
  • the second direction 102 is, for example, the ⁇ 1-100> direction.
  • the second direction 102 may be, for example, the [1-100] direction.
  • the second direction 102 may be, for example, a direction in which the ⁇ 1-100> direction is projected onto the first principal surface 1. From another perspective, the second direction 102 may be a direction including a ⁇ 1-100> direction component, for example.
  • the first principal surface 1 may be a ⁇ 0001 ⁇ plane or a plane inclined with respect to the ⁇ 0001 ⁇ plane.
  • the inclination angle (off angle) with respect to the ⁇ 0001 ⁇ plane is, for example, greater than 0° and 8° or less.
  • the inclination direction (off direction) of the first main surface 1 is, for example, the ⁇ 11-20> direction.
  • the off angle may be 2° or more and 6° or less.
  • the maximum diameter W (diameter) of the first main surface 1 is, for example, 100 mm (4 inches) or more, although it is not particularly limited.
  • the maximum diameter W may be 125 mm (5 inches) or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.
  • the maximum diameter W is not particularly limited, but may be, for example, 400 mm (16 inches) or less.
  • the maximum diameter W is the longest linear distance between two different points on the outer peripheral edge 6 when viewed in a direction perpendicular to the first principal surface 1 .
  • 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm/inch). 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm/inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm/inch). 16 inches means 400 mm or 406.4 mm (16 inches x 25.4 mm/inch).
  • first silicon carbide substrate 30 has second main surface 2 and third main surface 3.
  • the third main surface 3 is opposite the second main surface 2.
  • Second main surface 2 is spaced apart from first silicon carbide epitaxial layer 40 .
  • Third main surface 3 is in contact with first silicon carbide epitaxial layer 40 .
  • the polytype of silicon carbide constituting first silicon carbide substrate 30 is, for example, 4H.
  • the polytype of silicon carbide constituting first silicon carbide epitaxial layer 40 is, for example, 4H.
  • first silicon carbide epitaxial layer 40 has fourth main surface 4.
  • the fourth main surface 4 is opposite the first main surface 1.
  • first silicon carbide epitaxial layer 40 is in contact with first silicon carbide substrate 30 .
  • First silicon carbide epitaxial layer 40 has a first boundary layer 41 , a first buffer layer 42 , and a first drift layer 43 .
  • the first drift layer 43 may be one layer, or may be two or more layers.
  • First boundary layer 41 is provided on first silicon carbide substrate 30 .
  • First boundary layer 41 is in contact with first silicon carbide substrate 30 .
  • the first boundary layer 41 constitutes the fourth main surface 4 .
  • the thickness of the first boundary layer 41 is a first thickness T1.
  • the first thickness T1 is, for example, 0.1 ⁇ m.
  • the first thickness T1 may be, for example, 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first thickness T1 is not particularly limited, but may be, for example, 0.3 ⁇ m or more, or 0.5 ⁇ m or more.
  • the first thickness T1 is not particularly limited, but may be, for example, 4 ⁇ m or less, or 3 ⁇ m or less.
  • the first buffer layer 42 is provided on the first boundary layer 41.
  • the first buffer layer 42 is in contact with the first boundary layer 41 .
  • the thickness of the first buffer layer 42 is a second thickness T2.
  • the second thickness T2 may be larger than the first thickness T1.
  • the second thickness T2 is, for example, 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 is not particularly limited, but may be, for example, 0.2 ⁇ m or more, or 0.5 ⁇ m or more.
  • the second thickness T2 is not particularly limited, but may be, for example, 5 ⁇ m or less, or 2 ⁇ m or less.
  • the first drift layer 43 is provided on the first buffer layer 42.
  • the first drift layer 43 is in contact with the first buffer layer 42 .
  • the first drift layer 43 constitutes the first main surface 1 .
  • the thickness of the first drift layer 43 is a third thickness T3.
  • the third thickness T3 is larger than the second thickness T2.
  • the third thickness T3 is, for example, 5 ⁇ m or more and 100 ⁇ m or less.
  • the third thickness T3 is not particularly limited, and may be, for example, 10 ⁇ m or more, or 20 ⁇ m or more.
  • the third thickness T3 is not particularly limited, but may be, for example, 80 ⁇ m or less, or 60 ⁇ m or less.
  • the thickness of first silicon carbide substrate 30 is a fourth thickness T4.
  • the fourth thickness T4 may be larger than the third thickness T3.
  • the fourth thickness T4 is, for example, 200 ⁇ m or more and 600 ⁇ m or less.
  • the fourth thickness T4 is not particularly limited, but may be, for example, 250 ⁇ m or more, or 300 ⁇ m or more.
  • the fourth thickness T4 is not particularly limited, but may be, for example, 550 ⁇ m or less or 500 ⁇ m or less.
  • the interface between the first boundary layer 41 and the first buffer layer 42 is a first interface 9.
  • the distance from first interface 9 to the surface (first main surface 1) of first silicon carbide epitaxial layer 40 is a first distance E1.
  • the first distance E1 is the thickness of the first silicon carbide epitaxial layer 40 excluding the first boundary layer 41.
  • the first distance E1 is, for example, the total value of the second thickness T2 and the third thickness T3.
  • FIG. 3 is a schematic diagram showing the relationship between the concentration and depth of n-type impurities in silicon carbide epitaxial substrate 100 according to this embodiment.
  • the vertical axis represents the concentration of n-type impurities
  • the horizontal axis represents the depth in the thickness direction.
  • the vertical axis is the axis of the common logarithmic scale.
  • the horizontal axis is the axis of linear scale.
  • depth means the distance from the first main surface 1 in the thickness direction. The depth increases as it approaches the second main surface 2, with the first main surface 1 being 0.
  • the position where the depth is 0 corresponds to the first main surface 1.
  • the region from the first main surface 1 to the first depth D1 corresponds to the first drift layer 43.
  • the first depth D1 corresponds to the third thickness T3.
  • the region from the first depth D1 to the second depth D2 corresponds to the first buffer layer 42.
  • the value obtained by subtracting the first depth D1 from the second depth D2 is the second thickness T2.
  • the region from the second depth D2 to the third depth D3 corresponds to the first boundary layer 41.
  • the value obtained by subtracting the second depth D2 from the third depth D3 is the first thickness T1.
  • a region deeper than third depth D3 corresponds to first silicon carbide substrate 30.
  • the first drift layer 43 contains an n-type impurity such as nitrogen (N).
  • the conductivity type of the first drift layer 43 is, for example, n-type.
  • the concentration of n-type impurities in the first drift layer 43 is set to a first concentration C1.
  • the first concentration C1 is, for example, 2 ⁇ 10 16 /cm 3 .
  • the first concentration C1 may be, for example, 1 ⁇ 10 15 /cm 3 or more and 5 ⁇ 10 16 /cm 3 or less.
  • the first concentration C1 is not particularly limited, but may be, for example, 3 ⁇ 10 15 /cm 3 or more, or 5 ⁇ 10 15 /cm 3 or more.
  • the first concentration C1 is not particularly limited, but may be, for example, 4 ⁇ 10 16 /cm 3 or less, or 3 ⁇ 10 16 /cm 3 or less.
  • the first buffer layer 42 contains an n-type impurity such as nitrogen.
  • the conductivity type of the first buffer layer 42 is, for example, n-type.
  • the concentration of n-type impurities in the first buffer layer 42 is set to a second concentration C2.
  • the second concentration C2 is higher than the first concentration C1.
  • the second concentration C2 is, for example, 7 ⁇ 10 18 /cm 3 .
  • the second concentration C2 is 3 ⁇ 10 18 /cm 3 or more.
  • the second concentration C2 is not particularly limited, but may be, for example, 5 ⁇ 10 18 /cm 3 or more, or 7 ⁇ 10 18 /cm 3 or more.
  • the second concentration C2 is not particularly limited, but may be, for example, 1 ⁇ 10 19 /cm 3 or less, or 8 ⁇ 10 18 /cm 3 or less.
  • the first boundary layer 41 contains an n-type impurity such as nitrogen.
  • the conductivity type of the first boundary layer 41 is, for example, n-type.
  • the concentration of n-type impurities in the first boundary layer 41 is set to a third concentration C3.
  • the third concentration C3 is, for example, 1 ⁇ 10 19 /cm 3 .
  • the third concentration C3 may be, for example, 5 ⁇ 10 18 /cm 3 or more and 1 ⁇ 10 20 /cm 3 or less.
  • the third concentration C3 is not particularly limited, but may be, for example, 7 ⁇ 10 18 /cm 3 or more, or 9 ⁇ 10 18 /cm 3 or more.
  • the third concentration C3 is not particularly limited, but may be, for example, 7 ⁇ 10 19 /cm 3 or less, or 3 ⁇ 10 19 /cm 3 or less.
  • the third concentration C3 is higher than the second concentration C2.
  • the value obtained by subtracting the second concentration C2 from the third concentration C3 is, for example, 3 ⁇ 10 18 /cm 3 .
  • the value obtained by subtracting the second concentration C2 from the third concentration C3 may be, for example, 1 ⁇ 10 18 /cm 3 or more.
  • the value obtained by subtracting the second concentration C2 from the third concentration C3 is not particularly limited, but may be, for example, 3 ⁇ 10 18 /cm 3 or more, or 5 ⁇ 10 18 /cm 3 or more.
  • the value obtained by subtracting the second concentration C2 from the third concentration C3 is not particularly limited, but may be, for example, 1 ⁇ 10 20 /cm 3 or less, or 5 ⁇ 10 19 /cm 3 or less.
  • first silicon carbide substrate 30 contains n-type impurities such as nitrogen.
  • the conductivity type of first silicon carbide substrate 30 is, for example, n-type.
  • the concentration of n-type impurities in first silicon carbide substrate 30 is a fourth concentration C4.
  • the fourth concentration C4 is, for example, 7 ⁇ 10 18 /cm 3 .
  • the fourth concentration C4 may be, for example, 3 ⁇ 10 18 /cm 3 or more and 1 ⁇ 10 19 /cm 3 or less.
  • the absolute value of the value obtained by subtracting the second density C2 from the fourth density C4 is smaller than the value obtained by subtracting the second density C2 from the third density C3.
  • the absolute value of the value obtained by subtracting the second concentration C2 from the fourth concentration C4 is, for example, 1 ⁇ 10 17 /cm 3 or more and 1 ⁇ 10 18 /cm 3 or less.
  • the fourth concentration C4 may be substantially the same as the second concentration C2.
  • the fourth concentration C4 is higher than the first concentration C1.
  • the third concentration C3 is higher than the fourth concentration C4.
  • SIMS secondary ion mass spectrometry
  • IMS7f which is a secondary ion mass spectrometer manufactured by Cameca
  • the primary ion is O 2 + and the primary ion energy is 8 keV.
  • FIG. 4 is a schematic cross-sectional view showing the structure of the epitaxial substrate according to this embodiment.
  • epitaxial substrate 200 has a fifth main surface 15 and a sixth main surface 16.
  • the sixth major surface 16 is opposite the fifth major surface 15.
  • Epitaxial substrate 200 has a second silicon carbide substrate 50 and a second silicon carbide epitaxial layer 60.
  • Second silicon carbide substrate 50 has a sixth main surface 16 and a seventh main surface 17.
  • the seventh major surface 17 is opposite the sixth major surface 16.
  • the thickness of second silicon carbide substrate 50 is a seventh thickness T7.
  • the polytype of silicon carbide constituting second silicon carbide substrate 50 is, for example, 4H.
  • second silicon carbide epitaxial layer 60 is provided on second silicon carbide substrate 50.
  • Second silicon carbide epitaxial layer 60 is in contact with second silicon carbide substrate 50 .
  • Second silicon carbide epitaxial layer 60 has a fifth main surface 15 and an eighth main surface 18.
  • eighth main surface 18 second silicon carbide epitaxial layer 60 is in contact with second silicon carbide substrate 50 .
  • the polytype of silicon carbide constituting second silicon carbide epitaxial layer 60 is, for example, 4H.
  • Second silicon carbide epitaxial layer 60 has a second buffer layer 62 and a second drift layer 63.
  • Second buffer layer 62 is provided on second silicon carbide substrate 50, for example.
  • Second buffer layer 62 is in contact with second silicon carbide substrate 50, for example.
  • the thickness of the second buffer layer 62 is a fifth thickness T5.
  • the fifth thickness T5 is smaller than the seventh thickness T7.
  • the second drift layer 63 is provided on the second buffer layer 62.
  • the second drift layer 63 is in contact with the second buffer layer 62.
  • the second drift layer 63 constitutes the fifth main surface 15.
  • the thickness of the second drift layer 63 is a sixth thickness T6.
  • the sixth thickness T6 is larger than the fifth thickness T5.
  • second distance E2 is the thickness of second silicon carbide epitaxial layer 60.
  • the second distance E2 is, for example, the total value of the fifth thickness T5 and the sixth thickness T6.
  • FIG. 5 is a schematic cross-sectional view showing the structure of an epitaxial substrate 200 according to a modification of this embodiment.
  • second silicon carbide epitaxial layer 60 may have a second boundary layer 61 .
  • Second boundary layer 61 is provided between second silicon carbide substrate 50 and second buffer layer 62 .
  • the interface between the second boundary layer 61 and the second buffer layer 62 is the second interface 19 .
  • the thickness of the second boundary layer 61 is an eighth thickness T8.
  • the fifth thickness T5 may be larger than the eighth thickness T8.
  • the second distance E2 is the distance from the interface between the second boundary layer 61 and the second buffer layer 62 (second interface 19) to the second silicon carbide epitaxial layer 60. is the distance to the surface (fifth principal surface 15).
  • the configuration of epitaxial substrate 200 may be substantially the same as the configuration of silicon carbide epitaxial substrate 100 (see FIG. 2).
  • Second silicon carbide substrate 50 corresponds to first silicon carbide substrate 30 (see FIG. 2).
  • Second silicon carbide epitaxial layer 60 corresponds to first silicon carbide epitaxial layer 40 (see FIG. 2).
  • the second boundary layer 61 corresponds to the first boundary layer 41 (see FIG. 2).
  • the second buffer layer 62 corresponds to the first buffer layer 42 (see FIG. 2).
  • the second drift layer 63 corresponds to the first drift layer 43 (see FIG. 2).
  • the fifth main surface 15 corresponds to the first main surface 1 (see FIG. 2).
  • the sixth main surface 16 corresponds to the second main surface 2 (see FIG. 2).
  • FIG. 6 is a schematic partial cross-sectional view showing the configuration of an epitaxial substrate manufacturing apparatus.
  • the epitaxial substrate manufacturing apparatus 300 is, for example, a hot wall horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in FIG. 6, the epitaxial substrate manufacturing apparatus 300 includes a reaction chamber 201, a gas supply section 235, a control section 245, a heating element 203, a quartz tube 204, and a heat insulating material (not shown). , and an induction heating coil (not shown).
  • the heating element 203 has, for example, a cylindrical shape, and forms a reaction chamber 201 inside.
  • the heating element 203 is made of graphite, for example.
  • the heating element 203 is provided inside the quartz tube 204.
  • the heat insulating material surrounds the outer periphery of the heating element 203.
  • the induction heating coil is wound along the outer peripheral surface of the quartz tube 204, for example.
  • the induction heating coil is configured to be able to be supplied with alternating current from an external power source (not shown). Thereby, the heating element 203 is heated by induction. As a result, reaction chamber 201 is heated by heating element 203 .
  • the reaction chamber 201 is a space surrounded by the inner wall surface 205 of the heating element 203.
  • Reaction chamber 201 is provided with susceptor 210 that holds a silicon carbide substrate.
  • Susceptor 210 is made of silicon carbide.
  • a silicon carbide substrate is placed on a susceptor 210.
  • Susceptor 210 is placed on stage 202.
  • the stage 202 is rotatably supported by a rotating shaft 209. As the stage 202 rotates, the susceptor 210 rotates.
  • the manufacturing apparatus 300 for silicon carbide epitaxial substrate 100 further includes a gas inlet 207 and a gas exhaust port 208.
  • the gas exhaust port 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate gas flows. Gas is introduced into the reaction chamber 201 through the gas inlet 207 and exhausted through the gas exhaust port 208 . The pressure within the reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.
  • the gas supply unit 235 is configured to be able to supply a mixed gas containing a raw material gas, a dopant gas, and a carrier gas to the reaction chamber 201.
  • the gas supply section 235 includes, for example, a first gas supply section 231, a second gas supply section 232, a third gas supply section 233, and a fourth gas supply section 234.
  • the first gas supply section 231 is configured to be able to supply, for example, a first gas containing carbon atoms.
  • the first gas supply unit 231 is, for example, a gas cylinder filled with a first gas.
  • the first gas is, for example, propane (C 3 H 8 ) gas.
  • the first gas may be, for example, methane (CH 4 ) gas, ethane (C 2 H 6 ) gas, acetylene (C 2 H 2 ) gas, or the like.
  • the second gas supply section 232 is configured to be able to supply, for example, a second gas containing silicon atoms.
  • the second gas supply section 232 is, for example, a gas cylinder filled with a second gas.
  • the second gas is, for example, silane (SiH 4 ) gas.
  • the second gas may be a mixed gas of silane gas and another gas other than silane.
  • the third gas supply section 233 is configured to be able to supply, for example, a third gas containing nitrogen atoms.
  • the third gas supply unit 233 is, for example, a gas cylinder filled with a third gas.
  • the third gas is a doping gas.
  • the third gas is, for example, ammonia gas. Ammonia gas is more easily thermally decomposed than nitrogen gas, which has triple bonds.
  • the fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen, for example.
  • a fourth gas carrier gas
  • the fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen.
  • the fourth gas may be argon gas.
  • the control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201.
  • the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. good.
  • Each control unit may be, for example, an MFC (Mass Flow Controller).
  • the control section 245 is arranged between the gas supply section 235 and the gas introduction port 207.
  • FIG. 7 is a flowchart schematically showing a method for manufacturing the epitaxial substrate 200 according to this embodiment.
  • the method for manufacturing epitaxial substrate 200 according to the present embodiment includes a step of preparing a silicon carbide epitaxial substrate (S10), a step of measuring a first distance (S20), and determining growth conditions. (S30) and a step (S40) of performing epitaxial growth on the second silicon carbide substrate.
  • a step (S10) of preparing a silicon carbide epitaxial substrate is performed.
  • a silicon carbide single crystal of polytype 4H is produced by a sublimation method.
  • first silicon carbide substrate 30 is prepared by slicing the silicon carbide single crystal using, for example, a wire saw.
  • First silicon carbide substrate 30 contains n-type impurities such as nitrogen.
  • the conductivity type of first silicon carbide substrate 30 is, for example, n-type.
  • first silicon carbide substrate 30 is mechanically polished.
  • first silicon carbide substrate 30 is subjected to chemical mechanical polishing.
  • first silicon carbide epitaxial layer 40 is formed on the first silicon carbide substrate 30.
  • first silicon carbide epitaxial layer 40 is formed by epitaxial growth on third main surface 3 of first silicon carbide substrate 30 using a hot wall type horizontal CVD apparatus shown in FIG.
  • the first boundary layer 41 is formed on the third main surface 3.
  • a first buffer layer 42 is formed on the first boundary layer 41 .
  • a first drift layer 43 is formed on the first buffer layer 42 .
  • silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, and hydrogen (H 2 ) is used as a carrier gas.
  • the temperature for epitaxial growth is, for example, about 1400° C. or more and 1700° C. or less.
  • an n-type impurity such as nitrogen is introduced into first silicon carbide epitaxial layer 40 .
  • the conditions of the flow rate of the source gas, the flow rate of the dopant gas, the flow rate of the carrier gas, and the epitaxial growth time when forming the first buffer layer 42 and the first drift layer 43 are set as first growth conditions.
  • silicon carbide epitaxial substrate 100 is prepared.
  • FIG. 8 is a schematic cross-sectional view showing the process of measuring the first distance.
  • the first silicon carbide epitaxial layer is The distance (first distance E1) to the surface (first principal surface 1) is measured. In other words, the total value of the thickness T2 of the first buffer layer 42 and the thickness T3 of the first drift layer 43 is measured.
  • the first distance E1 is measured using an FTIR (Fourier Transform InfraRed spectrometer).
  • the first distance E1 is measured by FTIR using the optical constant difference caused by the carrier concentration difference between the first buffer layer 42 and the first boundary layer 41.
  • the first main surface 1 is irradiated with infrared light. A portion of the infrared light travels along the first arrow 91. Specifically, a portion of the infrared light is reflected at the interface (first interface 9) between the first boundary layer 41 and the first buffer layer 42.
  • the first A distance E1 can be measured.
  • FTIR a Fourier transform infrared spectrophotometer (IRPrestige-21) manufactured by Shimadzu Corporation, for example, can be used as a measuring device.
  • the measurement wave number range is, for example, from 4700 cm -1 to 650 cm -1 .
  • the calculated wave number range is, for example, from 3400 cm ⁇ 1 to 2400 cm ⁇ 1 .
  • the wave number interval is, for example, 4 cm ⁇ 1 .
  • the incident angle of the infrared light is, for example, 25°.
  • Second growth conditions are determined based on the measured first distance E1.
  • the second growth conditions are used to manufacture epitaxial substrate 200 shown in FIG. 4.
  • silicon carbide epitaxial substrate 100 is used as a dummy substrate for determining the second growth conditions.
  • epitaxial substrate 200 is used, for example, to manufacture a silicon carbide semiconductor device, and ultimately forms part of the silicon carbide semiconductor device.
  • silicon carbide epitaxial substrate 100 is not normally used as a part of a silicon carbide semiconductor device, but may constitute a part of a silicon carbide semiconductor device.
  • the second growth conditions are determined so that the epitaxial growth time is longer than the growth conditions.
  • the second growth conditions are determined so that the epitaxial growth time is shorter than the first growth conditions, for example.
  • the second growth conditions may be determined by changing at least one of the flow rate of the source gas, the flow rate of the dopant gas, and the flow rate of the carrier gas from the first growth conditions.
  • a step (S40) of performing epitaxial growth on the second silicon carbide substrate is performed.
  • second silicon carbide substrate 50 is prepared.
  • Epitaxial growth is performed using a hot wall type horizontal CVD apparatus shown in FIG.
  • epitaxial growth is performed using the second growth conditions.
  • second silicon carbide epitaxial layer 60 is formed on second silicon carbide substrate 50.
  • epitaxial substrate 200 (see FIG. 4) is manufactured.
  • FIG. 9 is a flowchart schematically showing a method for manufacturing silicon carbide semiconductor device 400 according to this embodiment.
  • the method for manufacturing silicon carbide semiconductor device 400 according to the present embodiment mainly includes a step of preparing an epitaxial substrate (S1) and a step of processing the epitaxial substrate (S2). There is.
  • a step (S1) of preparing an epitaxial substrate is performed.
  • the epitaxial substrate 200 (see FIG. 4) according to the present embodiment is manufactured using the method for manufacturing the epitaxial substrate 200 shown in FIG.
  • a step (S2) of processing the epitaxial substrate 200 is performed. Specifically, the following processing is performed on the epitaxial substrate 200. First, ion implantation is performed into the epitaxial substrate 200.
  • FIG. 10 is a schematic cross-sectional view showing the process of forming the body region.
  • a p-type impurity such as aluminum is ion-implanted into fifth main surface 15 of second silicon carbide epitaxial layer 60 .
  • body region 113 having p-type conductivity is formed.
  • the portion where body region 113 is not formed becomes second drift layer 63 and second buffer layer 62.
  • the thickness of the body region 113 is, for example, 0.9 ⁇ m.
  • Second silicon carbide epitaxial layer 60 includes a second buffer layer 62 , a second drift layer 63 , and a body region 113 .
  • FIG. 11 is a schematic cross-sectional view showing the process of forming a source region.
  • an n-type impurity such as phosphorus is ion-implanted into body region 113, for example.
  • a source region 114 having an n-type conductivity type is formed.
  • the thickness of the source region 114 is, for example, 0.4 ⁇ m.
  • the concentration of n-type impurities contained in source region 114 is higher than the concentration of p-type impurities contained in body region 113.
  • a p-type impurity such as aluminum is ion-implanted into the source region 114, thereby forming a contact region 118.
  • Contact region 118 is formed to penetrate source region 114 and body region 113 and be in contact with second drift layer 63 .
  • the concentration of p-type impurities contained in contact region 118 is higher than the concentration of n-type impurities contained in source region 114.
  • activation annealing is performed to activate the ion-implanted impurities.
  • the activation annealing temperature is, for example, 1500° C. or more and 1900° C. or less.
  • the activation annealing time is, for example, about 30 minutes.
  • the activation annealing atmosphere is, for example, an argon atmosphere.
  • FIG. 12 is a schematic cross-sectional view showing a step of forming a trench in fifth main surface 15 of second silicon carbide epitaxial layer 60.
  • a mask 117 having an opening is formed on the fifth main surface 15 composed of the source region 114 and the contact region 118. Using mask 117, source region 114, body region 113, and a portion of second drift layer 63 are removed by etching.
  • the etching method for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF 6 or a mixed gas of SF 6 and O 2 as a reactive gas is used. A recess is formed in the fifth main surface 15 by etching.
  • thermal etching is performed in the recesses.
  • Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas containing at least one type of halogen atom, with the mask 117 formed on the fifth principal surface 15.
  • At least one type of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • the atmosphere includes, for example, Cl2 , BCl3 , SF6 or CF4 .
  • thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas, and at a heat treatment temperature of, for example, 700° C. or higher and 1000° C. or lower.
  • the reaction gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas.
  • the carrier gas for example, nitrogen gas, argon gas, or helium gas can be used.
  • trenches 56 are formed in the fifth main surface 15 by thermal etching.
  • Trench 56 is defined by side wall surface 53 and bottom wall surface 54 .
  • Sidewall surface 53 is composed of source region 114, body region 113, and second drift layer 63.
  • the bottom wall surface 54 is constituted by the second drift layer 63.
  • mask 117 is removed from fifth major surface 15.
  • FIG. 13 is a schematic cross-sectional view showing the process of forming a gate insulating film.
  • the epitaxial substrate 200 in which the trench 56 is formed in the fifth main surface 15 is heated at a temperature of, for example, 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen.
  • the bottom wall surface 54 is in contact with the second drift layer 63
  • the side wall surface 53 is in contact with the second drift layer 63
  • the fifth main surface 15 is in contact with the source region 114 and the contact region.
  • a gate insulating film 115 is formed in contact with each of the gate electrodes 118.
  • FIG. 14 is a schematic cross-sectional view showing the process of forming a gate electrode and an interlayer insulating film.
  • Gate electrode 127 is formed inside trench 56 so as to be in contact with gate insulating film 115 .
  • Gate electrode 127 is disposed inside trench 56 and formed on gate insulating film 115 so as to face each of side wall surface 53 and bottom wall surface 54 of trench 56 .
  • the gate electrode 127 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition) method.
  • Interlayer insulating film 126 is formed. Interlayer insulating film 126 is formed to cover gate electrode 127 and to be in contact with gate insulating film 115 .
  • the interlayer insulating film 126 is formed, for example, by chemical vapor deposition.
  • the interlayer insulating film 126 is made of, for example, a material containing silicon dioxide.
  • interlayer insulating film 126 and a portion of gate insulating film 115 are etched so that openings are formed over source region 114 and contact region 118. As a result, contact region 118 and source region 114 are exposed from gate insulating film 115.
  • Source electrode 116 is formed in contact with each of source region 114 and contact region 118.
  • Source electrode 116 is formed by, for example, a sputtering method.
  • the source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).
  • alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. As a result, a source electrode 116 that is in ohmic contact with the source region 114 is formed. Source electrode 116 may be in ohmic contact with contact region 118.
  • the source wiring 119 is formed.
  • the source wiring 119 is electrically connected to the source electrode 116.
  • the source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.
  • a step of forming a drain electrode is performed. First, second silicon carbide substrate 50 is polished on sixth main surface 16 . This reduces the thickness of second silicon carbide substrate 50. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with sixth main surface 16 . Through the above steps, silicon carbide semiconductor device 400 according to this embodiment is manufactured.
  • FIG. 15 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.
  • Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • Silicon carbide semiconductor device 400 mainly includes epitaxial substrate 200, gate electrode 127, gate insulating film 115, source electrode 116, drain electrode 123, source wiring 119, and interlayer insulating film 126.
  • Epitaxial substrate 200 has a second buffer layer 62, a second drift layer 63, a body region 113, a source region 114, and a contact region 118.
  • Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).
  • the concentration of n-type impurities in the buffer layer may be increased to suppress the movement of holes from the buffer layer to the drift layer during operation of the power device. This can suppress basal plane dislocations from becoming stacking faults due to holes reaching the drift layer.
  • the difference between the n-type impurity concentration in the buffer layer and the n-type impurity concentration in the silicon carbide substrate becomes small. As a result, the reflectance of infrared light at the interface between the buffer layer and the silicon carbide substrate decreases, and the accuracy of measuring the thickness of the silicon carbide epitaxial layer using FTIR decreases.
  • FIG. 16 is a schematic cross-sectional view showing a step of measuring first distance E1 in silicon carbide epitaxial substrate 100 according to a comparative example.
  • Silicon carbide epitaxial substrate 100 according to the comparative example shown in FIG. 16 does not have first boundary layer 41.
  • first boundary layer 41 is not included, first buffer layer 42 is in contact with first silicon carbide substrate 30.
  • a second arrow 92 indicates infrared light reflected at the interface between the first drift layer 43 and the first buffer layer 42 .
  • Silicon carbide epitaxial substrate 100 does not have first boundary layer 41, and the difference between n-type impurity concentration C2 in first buffer layer 42 and n-type impurity concentration C4 in first silicon carbide substrate 30 is small.
  • the intensity of infrared light (first arrow 91) reflected at the interface between first buffer layer 42 and first silicon carbide substrate 30 decreases.
  • infrared light (second arrow 92) reflected at the interface between first drift layer 43 and first buffer layer 42 is reflected at the interface between first buffer layer 42 and first silicon carbide substrate 30.
  • the intensity of the infrared light decreases. This reduces the interference between the infrared light reflected at the first principal surface 1 and the infrared light reflected at the interface between the first buffer layer 42 and the first silicon carbide substrate 30 (first arrow 91). , the measurement accuracy of the first distance E1 decreases.
  • first silicon carbide epitaxial layer 40 has first boundary layer 41 .
  • the concentration of n-type impurities in the first boundary layer 41 is higher than the concentration of n-type impurities in the first buffer layer 42 .
  • the reflectance of infrared light (first arrow 91) at the interface (first interface 9) between the first boundary layer 41 and the first buffer layer 42 can be improved. Therefore, in contrast to the infrared light reflected at the interface between the first drift layer 43 and the first buffer layer 42 (second arrow 92), the infrared light reflected at the first interface 9 (first arrow 91) Strength increases.
  • first silicon carbide epitaxial layer 40 This increases the interference between the infrared light reflected at the first principal surface 1 and the infrared light reflected at the first interface 9 (first arrow 91), so that the accuracy of measuring the first distance E1 can be improved. . As a result, the accuracy of measuring the thickness of first silicon carbide epitaxial layer 40 can be improved.
  • concentration C2 of n-type impurities in first buffer layer 42 is 3 ⁇ 10 18 /cm 3 or more. In this way, even when the n-type impurity concentration C2 in the first buffer layer 42 is high, it is possible to suppress a decrease in the accuracy of measuring the thickness of the first silicon carbide epitaxial layer 40.
  • the value obtained by subtracting the concentration C2 of n-type impurities in the first buffer layer 42 from the concentration C3 of n-type impurities in the first boundary layer 41 the higher the redness at the interface 9 between the first boundary layer 41 and the first buffer layer 42. Reflectance of external light can be improved.
  • the value obtained by subtracting the n-type impurity concentration C2 in the first buffer layer 42 from the n-type impurity concentration C3 in the first boundary layer 41 is 1 ⁇ 10 18 / cm 3 or more. Therefore, the measurement accuracy of the first distance E1 can be improved.
  • the thickness of first boundary layer 41 is 5 ⁇ m or less. Therefore, an increase in stacking faults in first silicon carbide epitaxial layer 40 can be suppressed.
  • the method for manufacturing epitaxial substrate 200 includes a step of measuring a first distance E1 using silicon carbide epitaxial substrate 100, and a step of determining growth conditions based on first distance E1. . Thereby, since the growth conditions for second silicon carbide epitaxial layer 60 are determined based on first distance E1, the accuracy of second distance E2 can be improved.
  • silicon carbide epitaxial substrates 100 according to Sample 1 and Sample 2 were prepared.
  • Silicon carbide epitaxial substrate 100 according to Sample 1 is a comparative example.
  • Silicon carbide epitaxial substrate 100 according to sample 2 is an example.
  • the structure of silicon carbide epitaxial substrate 100 according to Sample 1 was the structure of silicon carbide epitaxial substrate 100 shown in FIG. 16.
  • the structure of silicon carbide epitaxial substrate 100 according to Sample 2 was the structure of silicon carbide epitaxial substrate 100 shown in FIGS. 1 to 3.
  • Silicon carbide epitaxial substrate 100 according to sample 1 does not have first boundary layer 41 .
  • Silicon carbide epitaxial substrate 100 according to sample 2 has first boundary layer 41 .
  • the n-type impurity concentration C1 in first drift layer 43 was approximately 2 ⁇ 10 16 /cm 3 .
  • the n-type impurity concentration C2 in first buffer layer 42 was approximately 7 ⁇ 10 18 /cm 3 .
  • the n-type impurity concentration C4 in first silicon carbide substrate 30 was approximately 7 ⁇ 10 18 /cm 3 .
  • the n-type impurity concentration C3 in first boundary layer 41 was approximately 1 ⁇ 10 19 /cm 3 .
  • FIG. 17 is a graph showing the results of FTIR measurements on silicon carbide epitaxial substrate 100 according to Sample 1.
  • FIG. 18 is a graph showing the results of FTIR measurements on silicon carbide epitaxial substrate 100 according to Sample 2.
  • the vertical axis represents the intensity of reflected light
  • the horizontal axis represents the wave number of reflected light.
  • the first distance E1 is calculated based on the intensity spectrum of the reflected light with respect to the wave number. Specifically, the first distance E1 is calculated based on the number of maximum values of the intensity spectrum in the calculated wave number range. Therefore, compared to silicon carbide epitaxial substrate 100 according to Sample 1, silicon carbide epitaxial substrate 100 according to Sample 2 can measure the first distance E1 with higher accuracy.
  • first silicon carbide substrate 40 first silicon carbide epitaxial layer, 41 first boundary layer, 42 first buffer layer , 43 first drift layer, 50 second silicon carbide substrate, 53 side wall surface, 54 bottom wall surface, 56 trench, 60 second silicon carbide epitaxial layer, 61 second boundary layer, 62 second buffer layer, 63 second drift layer , 91 first arrow, 92 second arrow, 100 silicon carbide epitaxial substrate, 101 first direction, 102 second direction, 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region , 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 200 epitaxial substrate, 201 reaction chamber, 202

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PCT/JP2023/032681 2022-09-13 2023-09-07 炭化珪素エピタキシャル基板、エピタキシャル基板の製造方法および炭化珪素半導体装置の製造方法 Ceased WO2024058044A1 (ja)

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JP7667379B1 (ja) * 2024-08-13 2025-04-22 住友電気工業株式会社 炭化珪素エピタキシャル基板の製造方法および炭化珪素半導体装置の製造方法

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JP2006028016A (ja) * 2004-07-19 2006-02-02 Norstel Ab 低オフアクシスＳｉＣウエハ上のＳｉＣのホモエピタキシャル成長
JP2009130266A (ja) * 2007-11-27 2009-06-11 Toshiba Corp 半導体基板および半導体装置、半導体装置の製造方法
WO2017094764A1 (ja) * 2015-12-02 2017-06-08 三菱電機株式会社 炭化珪素エピタキシャル基板および炭化珪素半導体装置
WO2017104751A1 (ja) * 2015-12-18 2017-06-22 富士電機株式会社 炭化珪素半導体基板、炭化珪素半導体基板の製造方法、半導体装置および半導体装置の製造方法

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JP2006028016A (ja) * 2004-07-19 2006-02-02 Norstel Ab 低オフアクシスＳｉＣウエハ上のＳｉＣのホモエピタキシャル成長
JP2009130266A (ja) * 2007-11-27 2009-06-11 Toshiba Corp 半導体基板および半導体装置、半導体装置の製造方法
WO2017094764A1 (ja) * 2015-12-02 2017-06-08 三菱電機株式会社 炭化珪素エピタキシャル基板および炭化珪素半導体装置
WO2017104751A1 (ja) * 2015-12-18 2017-06-22 富士電機株式会社 炭化珪素半導体基板、炭化珪素半導体基板の製造方法、半導体装置および半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7667379B1 (ja) * 2024-08-13 2025-04-22 住友電気工業株式会社 炭化珪素エピタキシャル基板の製造方法および炭化珪素半導体装置の製造方法
WO2026038306A1 (ja) * 2024-08-13 2026-02-19 住友電気工業株式会社 炭化珪素エピタキシャル基板の製造方法および炭化珪素半導体装置の製造方法

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