WO2024058042A1 - 記録装置、不揮発性記憶装置、及び記録方法 - Google Patents

記録装置、不揮発性記憶装置、及び記録方法 Download PDF

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Publication number
WO2024058042A1
WO2024058042A1 PCT/JP2023/032655 JP2023032655W WO2024058042A1 WO 2024058042 A1 WO2024058042 A1 WO 2024058042A1 JP 2023032655 W JP2023032655 W JP 2023032655W WO 2024058042 A1 WO2024058042 A1 WO 2024058042A1
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Prior art keywords
recording
speed
command
data
memory card
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English (en)
French (fr)
Japanese (ja)
Inventor
勇雄 加藤
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to CN202380065993.8A priority Critical patent/CN119895403A/zh
Priority to JP2024546905A priority patent/JPWO2024058042A1/ja
Publication of WO2024058042A1 publication Critical patent/WO2024058042A1/ja
Priority to US19/077,788 priority patent/US20250208794A1/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Definitions

  • the present disclosure relates to a recording device that records data on a nonvolatile storage device, a nonvolatile storage device, and a speed-guaranteed recording method on a nonvolatile storage device.
  • Patent Document 1 discloses a technique that makes it possible to request a memory card to perform data recording with a guaranteed minimum recording speed.
  • Patent Document 1 discloses a procedure for reading and writing data between a host device and a memory card.
  • the imaging device which is a host device, and the memory card are connected via a PCI Express interface (hereinafter abbreviated as "PCIe interface"), and data can be read from the memory card/data transferred to the memory card.
  • PCIe interface a PCI Express interface
  • the NVMe standard protocol is used for writing.
  • An object of the present disclosure is to provide a technique for suppressing a temperature rise in a nonvolatile storage device when data is recorded in the nonvolatile storage device with a guaranteed minimum recording speed.
  • a recording device of the present disclosure is a recording device that records data on a nonvolatile storage device at a guaranteed minimum recording speed, is physically connected to the nonvolatile storage device, and has a transfer speed faster than the minimum recording speed.
  • the interface unit stores control commands in non-volatile memory, including a data write command for recording data, a command for instructing speed-guaranteed recording, and a command for instructing transition to an optimum performance operation mode. After sending a command that can be sent to the device to instruct speed-guaranteed recording and a command to instruct transition to the optimum performance operation mode, a data write command to cause data recording to be sent to the nonvolatile storage device. Send.
  • the nonvolatile storage device of the present disclosure is a nonvolatile storage device that is capable of recording data at a guaranteed minimum recording speed using a recording device, and is physically connected to the recording device and
  • the interface section includes an interface section whose transfer speed is faster than the recording speed, and the interface section includes a data write command for recording data, a command for instructing speed-guaranteed recording, and a command for instructing transition to an optimal performance operation mode.
  • a control command can be received from the recording device, and after receiving a command for instructing speed-guaranteed recording and a command for instructing transition to an optimal performance operation mode, a data write command for recording data is received.
  • non-volatile storage non-volatile storage.
  • the recording method of the present disclosure is a recording method executed in a recording device that records data in a nonvolatile storage device at a minimum recording speed via an interface unit whose transfer speed is faster than a guaranteed minimum recording speed. Then, a command for instructing speed-guaranteed recording, a command for instructing transition to the optimum performance operation mode, and a data write command for causing data recording to be performed are transmitted.
  • Configuration diagram of storage system according to the present disclosure
  • Configuration diagram of a storage system according to an exemplary embodiment Configuration diagram of a storage system according to an exemplary embodiment
  • Diagram showing an overview of the configuration of the input/output stage circuit of a full-duplex interface
  • Diagram showing an overview of the configuration of the input/output stage circuit of a half-duplex interface
  • a diagram showing an example of the shape configuration of a terminal portion of an exemplary memory card.
  • FIG. 1 Diagram showing the relationship between video speed class and interface speed mode in an SD memory card Diagram showing the relationship between capacity and card type in an SD memory card Diagram showing the relationship between video speed class and clock condition in SD memory cards Diagram showing the relationship between video speed class and data transfer speed in SD memory cards Diagram showing SDR and DDR data transfer methods Diagram showing the relationship between transmission speed (bit rate) and clock frequency of UHS-II interface in SD memory card Diagram showing the relationship between SD memory card bus speed mode and maximum power consumption Diagram showing the relationship between SD memory card video speed class and power consumption limit Diagram showing the correspondence between SD Express card bus speed mode and SD Express speed class Diagram showing the data structure of the conventional SD memory card “CMD20” A diagram showing an example of a control command developed by the present inventors for transmitting information from a recording device to a nonvolatile storage device instructing a transition to an optimal performance operation mode.
  • CMD20 A diagram showing an example of a control command developed by the present inventors for transmitting information from a recording device to a nonvolatile storage device instructing a transition to an
  • Diagram showing an example of a command sequence during speed guaranteed recording on a conventional SD memory card Diagram showing an example of a command sequence during speed guaranteed recording on an SD Express card
  • a diagram showing an example of a command sequence developed by the present inventors for realizing the transmission of information from the recording device to the nonvolatile storage device in the SD Express card instructing the transition to the optimum performance operation mode 8-bit DSPEC (stream ID), 4-bit "SCC" of "CMD20", and 3-bit "CNT/ID" are described in DSPEC (16 bits) of the data write command of the NVMe standard.
  • Diagram showing an example of multiple Power States (power consumption states) supported by the SD Express card A diagram showing the structure of the NVMe standard identify controller data structure, Power State (power consumption state), and Vendor Specific area.
  • Diagram showing an example of the Speed Class Power State of the SD Express card in the Gen4x1 card A diagram showing an example of the Speed Class Power State of an SD Express card on a Gen4x1 card
  • FIG. 1 shows the configuration of a storage system 1 according to the present disclosure.
  • the storage system 1 includes a recording device 10, which is a host device, and a nonvolatile storage device 20.
  • the recording device 10 can write data to the nonvolatile storage device 20, and can read data stored in the nonvolatile storage device 20.
  • a storage system 1 having a PCIe/NVMe SSD as the nonvolatile storage device 20 and a PC as the recording device 10 can be considered.
  • a PCIe/NVMe SSD is an SSD (Solid State Drive) that adopts the PCIe (PCI Express) standard as a connection interface and the NVMe (Non-Volatile Memory Express) standard as a data transfer protocol.
  • the SD Express memory card is a memory card that has a PCIe interface added to the SD memory card that has a conventional connection interface.
  • the conventional SD memory card connection interface and the PCIe interface are used exclusively.
  • the SD Express memory card operates as an SD memory card when inserted into the SD memory card slot.
  • an SD Express memory card is installed in an SD Express compatible device having a PCIe interface, it is connected according to the PCIe standard, and data is exchanged using a protocol defined by the NVMe standard.
  • the recording device 10 includes a system control section 12, a buffer memory 14, and an interface section 16. These components are interconnected by a bus 11 and are capable of transmitting and receiving data.
  • the system control unit 12 is a controller composed of a semiconductor integrated circuit.
  • the system control unit 12 controls the recording apparatus 10 as a whole.
  • the system control unit 12 controls issuing (transmission) of commands to the nonvolatile storage device 20 via the interface unit 16, and controls responses from the nonvolatile storage device 20.
  • the system control unit 12 also prepares data to be written to the nonvolatile storage device 20, specifically, stores data to be written to the nonvolatile storage device 20 in the buffer memory 14.
  • the system control unit 12 processes data read from the nonvolatile storage device 20 and stored in the buffer memory 14 .
  • the buffer memory 14 temporarily stores data written to the nonvolatile storage device 20 and/or data read from the nonvolatile storage device 20.
  • the interface unit 16 communicates with the interface unit 26 of the nonvolatile storage device 20. Specifically, the interface unit 16 sends commands to the nonvolatile storage device 20, receives responses from the nonvolatile storage device 20, writes data to the nonvolatile storage device 20, and/or sends commands to the nonvolatile storage device 20. It is a general term for interfaces that send and receive data read from.
  • the nonvolatile storage device 20 includes a controller 22, a buffer memory 24, an interface section 26, a memory control section 28, and a nonvolatile memory 30. These components are interconnected by a bus 21 and are capable of transmitting and receiving data.
  • the controller 22 controls the overall operation of the nonvolatile storage device 20.
  • the buffer memory 24 is a memory that temporarily stores data received from the recording device 10 and written to the nonvolatile memory 30 and/or data read from the nonvolatile memory 30 and transmitted to the recording device 10. .
  • the interface unit 26 communicates with the interface unit 16 of the recording device 10. Specifically, the interface unit 26 receives commands from the recording device 10 and transmits responses to the recording device 10. The interface unit 26 also transmits and receives data to be written and/or read data to and from the interface unit 16 of the recording device 10 .
  • the interface unit 26 is a general term for interfaces that can perform these operations.
  • the memory control unit 28 is an integrated circuit that controls writing of data to the nonvolatile memory 30 and controlling reading of data from the nonvolatile memory 30.
  • the nonvolatile memory 30 is a nonvolatile memory that can hold data even when it is not energized, and is, for example, a flash memory.
  • FIG. 2 shows the configuration of the storage system 2 according to the exemplary embodiment.
  • the storage system 2 includes a recording device 100 that is a host device, and an SD Express memory card (hereinafter abbreviated as “memory card 200”) that is a nonvolatile storage device.
  • the recording device 100 is, for example, a digital camera, a digital movie camera, or a drive recorder.
  • the memory card 200 is configured by adding a PCIe interface to an SD memory card that has a connection interface based on the conventional SD standard.
  • Memory card 200 supports a conventional SD interface and can be used with conventional SD host devices.
  • the memory card 200 employs a PCIe interface to meet the needs for high-speed, large-capacity storage, and has specifications compatible with the PCI Express standard. The specific hardware configuration of the memory card 200 will be described later.
  • the recording device 100 includes an interface unit 102, a PCIe/NVMe driver 104, an SD driver 106, a file system 108, and application software 110.
  • the PCIe/NVMe driver 104, SD driver 106, file system 108, and application software 110 function as a software layer of the recording device 100.
  • the interface unit 102 corresponds to an interface part in the hardware of the recording device 100, for example, an SoC (System on Chip), which is a semiconductor product such as an LSI or a VLSI.
  • SoC System on Chip
  • the interface unit 102 includes a PCIe interface 102a, an SD host 102b, and a selector 102c.
  • the PCIe interface 102a is an interface for connecting in accordance with the PCIe standard. When transferring data, the PCIe interface 102a sends and receives data using a protocol compliant with the NVMe standard.
  • the SD host 102b is an interface for connecting in accordance with the SD standard. When transferring data, the SD host 102b sends and receives data using a protocol compliant with the SD standard.
  • the selector 102c is a switch that realizes exclusive use of the PCIe interface 102a and the SD host 102b.
  • the memory card 200 includes a controller 210 and a NAND flash memory 220.
  • the controller 210 includes a CPU 212, a PCIe interface 214a, an SD interface 214b, a buffer memory 216, and a NAND control section 218.
  • the CPU 212 corresponds to the controller 22 in FIG. 1 and controls the overall operation of the memory card 200.
  • the PCIe interface 214a is an interface for connecting in accordance with the PCIe standard. When transferring data, the PCIe interface 214a sends and receives data using a protocol compliant with the NVMe standard.
  • the SD interface 214b is an interface for connecting in accordance with the SD standard. When transferring data, the SD interface 214b sends and receives data using a protocol compliant with the SD standard.
  • the buffer memory 216 is a memory that temporarily stores data received from the recording device 100 and written to the NAND flash memory 220 and/or data read from the NAND flash memory 220 and transmitted to the recording device 100. .
  • the NAND control unit 218 controls writing data to and/or reading data from the NAND flash memory 220.
  • FIG. 6 shows an example of the shape and configuration of the terminal portion of the exemplary memory card 200.
  • FIG. 6 in order to make it easier to understand the groups of terminals of each interface, they are surrounded by dotted lines and shown as a terminal group 232 and a terminal group 234.
  • the memory card 200 has a terminal group 232 (terminal "1" to terminal “9”) which is a connection interface based on the SD standard, and a terminal group 234 (terminal "10” to terminal “17”) which is a connection interface based on the PCIe standard.
  • the configuration example in FIG. 6 complies with the SD Express card standard (SD Ver. 7.0).
  • the terminal group 234 in FIG. 6 is assigned to the PCIe interface, so the UHS-II interface cannot be used.
  • a new terminal group 236 is provided in addition to the terminal group 232 and the terminal group 234, as shown in FIG. It was done.
  • the data bus of the SD interface consists of 4 bits, where bit “0" (DAT0) of the data line is terminal “7", bit “1” (DAT1) is terminal “8", and bit “2” (DAT2). is assigned to terminal “9” and bit “3” (DAT3) is assigned to terminal "1".
  • the data bus of the PCIe interface consists of two sets of transmission lines using a differential transmission method.
  • the - signal of the input) is terminal "12"
  • the + signal of the Rx transmission line (host device input/card output) is terminal "16”
  • the - signal of the Rx transmission line (host device input/card output) is terminal "15”. is assigned to.
  • a pair (one set) of these Tx transmission paths and Rx transmission paths is called a lane in the PCIe standard, and the memory card 200 shown in FIG. 6 includes one PCIe interface lane.
  • the transmission path for sending commands to the memory card, responses from the memory card, and writing and/or reading data to the memory card is connected to the terminal group 234 using the PCIe interface.
  • the four signals assigned to the terminal group 232 are a PCIe reset signal called PERST#, a PCIe clock request signal called CLKREQ#, and a PCIe differential clock signal pair called REFCLK+/REFCLK-. It is assigned to terminals ⁇ 1'', ⁇ 9'', ⁇ 16'', and ⁇ 15'' of ing.
  • FIG. 7 shows an example of the shape and configuration of the terminal portion of the exemplary memory card 200.
  • the memory card 200 has a terminal group 232 (terminal “1" to “9") which is a connection interface according to the SD standard, and a terminal group 234 (terminal "10" to terminal "17") which is a connection interface according to the PCIe standard. It has a terminal group 236 (terminals "20" to "27").
  • the difference in shape and configuration from the memory card 200 compliant with the SD Express card standard (SD Ver. 7.0) shown in FIG. 6 is that it has two lanes of a connection interface based on the PCIe standard.
  • the memory card 200 that complies with the SD Express card standard (SD Ver. Ver. 7.0) has achieved twice the transmission speed.
  • FIG. 3 shows the configuration of the storage system 3 according to the exemplary embodiment.
  • the storage system 3 includes a recording device 100 that is a host device, and an SD memory card (hereinafter abbreviated as “memory card 200”) that is a nonvolatile storage device.
  • the recording device 100 is, for example, a digital camera, a digital movie camera, or a drive recorder.
  • the memory card 200 is configured by adding a UHS-II interface specified by the SD memory card standard (SD Ver. 4.0) to an SD memory card having a connection interface according to the conventional SD standard. ing.
  • Memory card 200 supports a conventional SD interface and can be used with conventional SD host devices.
  • the memory card 200 employs a UHS-II interface to meet the needs for high-speed, large-capacity storage. The specific hardware configuration of the memory card 200 will be described later.
  • the recording device 100 includes an interface section 302, a UHS-II driver 304, an SD driver 106, a file system 108, and application software 110.
  • the UHS-II driver 304, SD driver 106, file system 108, and application software 110 function as a software layer of the recording device 100.
  • the interface unit 302 corresponds to an interface part in the hardware of the recording device 100, for example, an SoC which is a semiconductor product such as LSI or VLSI.
  • the interface unit 302 includes a UHS-II interface 302a, an SD host 302b, and a selector 302c.
  • the UHS-II interface 302a is an interface for connecting in accordance with the UHS-II Addendum of the SD memory card standard. When transferring data, the UHS-II interface 302a sends and receives data using a protocol that complies with the UHS-II Addendum of the SD memory card standard.
  • the SD host 302b is an interface for connecting in accordance with the SD standard. When transferring data, the SD host 302b sends and receives data using a protocol that complies with the SD standard.
  • the selector 302c is a switch that realizes exclusive use with the UHS-II interface 302a and the SD host 302b.
  • the memory card 200 includes a controller 210 and a NAND flash memory 220.
  • the controller 210 includes a CPU 212, a UHS-II interface 314a, an SD interface 314b, a buffer memory 216, and a NAND control section 218.
  • the CPU 212 corresponds to the controller 22 in FIG. 1 and controls the overall operation of the memory card 200.
  • the UHS-II interface 314a is an interface for connecting in accordance with the UHS-II Addendum of the SD memory card standard. When transferring data, the UHS-II interface 314a sends and receives data using a protocol that complies with the UHS-II Addendum of the SD memory card standard.
  • the SD interface 314b is an interface for connecting in accordance with the SD standard. When transferring data, the SD interface 314b sends and receives data using a protocol compliant with the SD standard.
  • the buffer memory 216 is a memory that temporarily stores data received from the recording device 100 and written to the NAND flash memory 220 and/or data read from the NAND flash memory 220 and transmitted to the recording device 100. .
  • the NAND control unit 218 controls writing data to and/or reading data from the NAND flash memory 220.
  • FIG. 6 shows an example of the shape and configuration of the terminal portion of the exemplary memory card 200.
  • the memory card 200 has a terminal group 232 (terminal "1" to terminal "9") which is a connection interface according to the SD standard, and a terminal group 234 (terminal "10") which is a connection interface according to the UHS-II Addendum of the SD memory card standard. ⁇ terminal "17").
  • the configuration example in FIG. 6 complies with the SD memory card standard (SD Ver. 4.0 or later).
  • the data bus of the SD interface consists of 4 bits, where bit “0" (DAT0) of the data line is terminal “7", bit “1” (DAT1) is terminal “8", and bit “2” (DAT2). is assigned to terminal “9” and bit “3” (DAT3) is assigned to terminal "1".
  • the data bus of the UHS-II interface consists of two sets of transmission lines using a differential transmission method, the + signal of transmission line “0" is connected to terminal "11", and the - signal of transmission line “0" is connected to terminal "12". , the + signal of the transmission line “1” is assigned to the terminal "16", and the - signal of the transmission route "1" is assigned to the terminal "15".
  • the transmission path for sending commands to the memory card, responses from the memory card, and writing and/or reading data to the memory card is a group of terminals.
  • two signals that are a UHS-II differential clock signal pair called RCLK+/RCLK- are assigned to terminals "7" and "8" of the terminal group 232, and are assigned to the SD
  • the standard uses signals that are switched between when operating on the interface and when operating on the UHS-II interface.
  • the maximum value of the transmission speed is 8 gigabits/second. If the memory card 200 is a UHS-II card, the maximum transmission rate is approximately 3 gigabits/second.
  • Speed guarantee of SD memory card standard In the SD memory card standard, when shooting and recording video, the purpose is to prevent interruptions in video recording due to fluctuations or decreases in recording speed, and to prevent the occurrence of "dropped frames" (dropped frames), where, for example, one frame of a video is not recorded. , specifications regarding minimum recording speed guarantee (hereinafter abbreviated as "speed guarantee”) are defined.
  • VSC Video Speed Class
  • VSC6 is a class that guarantees a minimum recording speed of 6 MB/s
  • VSC10 is a class that guarantees a minimum recording speed of 10 MB/s
  • VSC30 is a class that guarantees a minimum recording speed of 30 MB/s
  • VSC60 is a class that guarantees a minimum recording speed of 60 MB/s
  • VSC90 is a class that guarantees a minimum recording speed of 90 MB/s. This is a class that guarantees a minimum recording speed of seconds.
  • Figure 8 shows the relationship between the interface speed mode between the host device (recording device 100) and the SD memory card and the video speed class, and the types of SD memory cards that support the video speed class.
  • VSC6 and VSC10 are supported, which means that a minimum recording speed of up to 10 megabytes/second (MB/s) can be guaranteed.
  • VSC6, VSC10, and VSC30 are supported, which means that a minimum recording speed of up to 30 megabytes/second (MB/s) can be guaranteed.
  • VSC6, VSC10, VSC30, VSC60, and VSC90 are supported, which means that a minimum recording speed of up to 90 megabytes/second (MB/s) can be guaranteed.
  • the video speed class is supported by SDHC cards, SDXC cards, and SDUC cards, and does not apply to SD cards.
  • Figure 9 shows the relationship between the types of SD memory cards and their memory capacities. Cards with capacities greater than 32 gigabytes and up to 2 terabytes, SDUC cards with capacities greater than 2 terabytes and up to 128 terabytes, and video speed class are supported on cards with capacities greater than 2 gigabytes.
  • FIG. 10 is a table showing the clock conditions for measuring the speed of each video speed class.
  • the clock frequency of the SD clock is 40 MHz in the HS mode of the SD interface
  • the clock frequency of the SD clock is 40 MHz in the UHS-I SDR25 mode of the SD interface
  • the clock frequency of the SD clock is 40 MHz in the DDR50 mode
  • the clock frequency of the SD clock is 40 MHz in the HS mode of the SD interface.
  • the guaranteed speed is measured when the clock frequency of the SD clock is 80 MHz.
  • the reference clock is 35 MHz in PLL range A in FD (Full Duplex) mode of the UHS-II interface, 26 MHz in PLL range B in FD mode, and 26 MHz in PLL range B in FD mode.
  • the guaranteed speed is measured with a reference clock of 35 MHz in PLL range A in half-duplex mode, and with a reference clock of 26 MHz in PLL range B in HD mode.
  • Figure 4 is a schematic diagram of the configuration of the input/output stage circuit in a general FD interface of the differential transmission method.In order to make the characteristics of full-duplex communication easier to understand, the diagram is shown in a simplified manner, with particular attention to the transmission direction. It is.
  • the transmitting circuit 411 of the recording device 100 sends commands and/or write data to nonvolatile memory from the recording device 100 to the memory card 200, and the receiving circuit 421 of the memory card 200 sends commands sent from the recording device 100. and/or receive write data to non-volatile memory.
  • FIG. 4 shows that transmission by an interface (transmission/reception function) composed of a transmission circuit 411 of the recording device 100 and a reception circuit 421 of the memory card 200 is unidirectional transmission from the recording device 100 to the memory card 200. It shows.
  • the transmitting circuit 422 of the memory card 200 transmits a response (completion) to the command and/or read data from the nonvolatile memory from the memory card 200 to the recording device 100, and the receiving circuit 412 of the recording device 100 transmits the response (completion) to the command and/or the read data from the nonvolatile memory.
  • a response (completion) to a command sent from 200 and/or data read from non-volatile memory is received.
  • FIG. 4 shows that the transmission by the interface (transmission/reception function) composed of the transmission circuit 422 of the memory card 200 and the reception circuit 412 of the recording device 100 is unidirectional transmission from the memory card 200 to the recording device 100. It shows.
  • the interface (transmission/reception function) composed of the transmission circuit and the reception circuit is always oriented in one direction.
  • Figure 5 is a schematic diagram of the configuration of the input/output stage circuit in a general HD interface using the differential transmission method.To make the characteristics of half-duplex communication easier to understand, the diagram is shown in a simplified manner, paying particular attention to the transmission direction. It is a diagram.
  • the transmitting circuit 511 of the recording device 100 sends commands and/or write data to nonvolatile memory from the recording device 100 to the memory card 200, and the receiving circuit 521 of the memory card 200 sends commands sent from the recording device 100. and/or receive write data to non-volatile memory.
  • the transmitting circuit 523 of the memory card 200 transmits a response to a command and/or read data from the nonvolatile memory from the memory card 200 to the recording device 100, and the receiving circuit 513 of the recording device 100 transmits a response to the command and/or data read from the nonvolatile memory.
  • a response to a command sent from the non-volatile memory and/or data read from the non-volatile memory is received.
  • a receiving circuit 512 of the recording device 100 is connected to a transmitting circuit 511 of the recording device 100, and a transmitting circuit 522 of the memory card 200 is connected to a receiving circuit 521 of the memory card.
  • the receiving circuit 524 of the memory card 200 is connected to the transmitting circuit 523 of the memory card 200, and the transmitting circuit 514 of the recording device 100 is connected to the receiving circuit 513 of the recording device 100.
  • the transmitting circuit 511 and receiving circuit 512 of the recording device 100 operate exclusively, and the receiving circuit 521 and transmitting circuit 522 of the memory card 200 are also controlled to operate exclusively.
  • the receiving circuit 521 of the memory card 200 is operated, and when operating the transmitting circuit 522 of the memory card 200, the receiving circuit 512 of the recording device 100 is operated. controlled to operate.
  • the transmitting circuit 523 and receiving circuit 524 of the memory card 200 operate exclusively, and the receiving circuit 513 and transmitting circuit 514 of the recording device 100 are also controlled to operate exclusively.
  • the receiving circuit 513 of the recording device 100 is operated, and when operating the transmitting circuit 514 of the recording device 100, the receiving circuit 524 of the memory card 200 is operated. controlled to operate.
  • SD memory card protocol of the SD memory card standard will be briefly explained using an example of writing data to an SD memory card.
  • the host device cannot issue the next command until the write data transmission by one data write command issued (sent) from the host device to the SD memory card is completed.
  • HD communication with the configuration of FIG.
  • transmission/reception function consisting of the transmission circuit 514 of the recording device 100 and the reception circuit 524 of the memory card 200, and write data from the recording device 100 to the memory card 200.
  • the transmission speed can be increased to about twice that of FD communication with the configuration shown in FIG.
  • the UHS-II interface specifies two transmission methods that determine the transmission speed: FD mode transmission and HD mode transmission.
  • PLL range A and PLL range B which are other specifications that determine the transmission speed of the UHS-II interface, will be briefly explained with reference to the drawings.
  • FIG. 13 shows the relationship between the PLL range of the UHS-II interface, the frequency of the reference clock (RCLK), the PLL multiplication rate, and the transmission speed (bit rate).
  • the frequency of the reference clock is variable, and its range is from 26 MHz to 52 MHz for both PLL range A and PLL range B.
  • the PLL multiplication rate is 15 times for PLL range A and 30 times for PLL range B
  • UHS-II transmission method The above-mentioned UHS-II interface employs a differential transmission method, and UHS-II differential transmission signals are assigned to the terminal group 234 shown in FIG.
  • the UHS-I adopts the same single-end transmission method as the conventional SD interface, and the UHS-I single-end transmission signal is assigned to the terminal group 232 shown in FIG.
  • FIG. 12 is a diagram showing data transfer in SDR mode and DDR mode of UHS-I.
  • FIG. 11 shows the data transfer speed of the video speed class and interface in the SD memory card based on the above-mentioned UHS-II transmission method and UHS-I transmission method and the clock conditions of the video speed class shown in FIG. FIG.
  • the top row of each cell is the clock frequency shown in FIG. 10 in megahertz, and the bottom row of each cell is the data transfer rate of the interface in megabytes/second.
  • the clock frequency of the SD clock is 40 MHz, so the transfer speed using the 4-bit bus of the SD interface is 20 MB/s, and in the UHS-I SDR25 mode, the transfer speed is also 20 MB/s.
  • the clock frequency of the SD clock is 40 MHz, and data transfer is performed using the DDR shown in FIG. 12, so the transfer rate using the 4-bit bus is 40 MB/sec.
  • UHS-II transmission method it is possible to achieve a data transfer rate twice that of the UHS-II interface FD mode, so as shown in Figure 11, PLL The data transfer rate is 105 MB/sec in range A and 156 MB/sec in PLL range B.
  • each bus speed of the interface (HS, UHS-I, UHS-II) compatible with "VSC10"
  • the maximum transfer speed of the mode is 25 MB/sec to 312 MB/sec, which is more than necessary and sufficient, specifically 2.5 to 31 times faster than the minimum recording speed.
  • FIG. 14 shows the relationship between bus speed mode and maximum power consumption in the SD memory card standard
  • FIG. 15 shows the relationship between video speed class and power consumption limit in the SD memory card standard.
  • Figure 14 shows that the maximum power consumption increases as the bus speed increases
  • Figure 15 shows that as the guaranteed speed of the video speed class increases, the power consumption limit is relaxed, that is, more power consumption is allowed. This indicates that the
  • SD memory card standard defines the operating temperature range of an SD memory card as -25°C to 85°C.
  • Digital movie cameras and digital cameras which are examples of host devices, are equipped with image sensors such as CMOS sensors and image processing engines (SoCs, which are semiconductor products such as VLSI that perform image processing) due to the recent trends toward higher pixel counts and higher image quality. etc.) generate a large amount of heat, and the demand for smaller equipment requires high-density mounting, making heat dissipation difficult, making thermal design a major issue.
  • image sensors such as CMOS sensors and image processing engines (SoCs, which are semiconductor products such as VLSI that perform image processing) due to the recent trends toward higher pixel counts and higher image quality. etc.
  • the present inventors discovered that with the current speed guaranteed recording standards, if the guaranteed speed of speed guaranteed recording is significantly lower than the maximum bus speed of the memory card, that is, there is a large margin in the performance of the maximum bus speed. In some cases, we focused on the fact that there was no mechanism to reduce the performance to a level sufficient to achieve the guaranteed speed.
  • the UHS-II interface 314a of the memory card 200 operates as shown in the bus speed mode "UHS-II HD312" in FIG.
  • the CPU 212, buffer memory 216, NAND control unit 218, and NAND flash memory 220 are supplied with a high frequency clock to operate at a maximum speed of 312 MB/s, and to operate at a performance commensurate with the maximum speed of 312 MB/s. , the processing capacity is increased.
  • the recording device 100 records data only at a maximum speed of 90 megabytes/second (MB/s). That is, there is a large difference of about 3.5 times between the maximum bus speed and the guaranteed speed of speed guaranteed recording.
  • FD mode of UHS-II interface and PLL range B are selected. (setting) and the speed of the UHS-II interface 314a (141 MB/s) when the RCLK supplied by the recording device 100 to the memory card 200 is set to 47 MHz, the speed is guaranteed to be 90 MB/s. Recording is possible. In other words, it is possible to record a guaranteed speed of 90 megabytes/second (MB/s) at 141 megabytes/second, which is less than half of 312 megabytes/second, and the CPU 212 is required to operate at a performance commensurate with the speed of 312 megabytes/second. , the buffer memory 216, the NAND control unit 218, and the NAND flash memory 220 are operated at maximum processing capacity by supplying high frequency clocks, which is clearly excessive performance (over-spec).
  • an SD Express card (memory card 200) compatible with the SD Express speed class 600MB/s shown in FIG. 16 is installed in the recording device 100 in FIG. 2, and speeds up to 600 megabytes/second (MB/s) are guaranteed.
  • the SD Express The PCIe interface 214a of the card (memory card 200) operates at 3,938 MB/s, and in accordance with this, the CPU 212, buffer memory 216, and NAND control are performed to operate at a performance commensurate with the maximum speed of 3,938 MB/s.
  • a high frequency clock is supplied to the unit 218 and the NAND flash memory 220, and the processing capacity is maximized.
  • the recording device 100 records data only at a maximum speed of 600 megabytes/second (MB/s). That is, there is a very large difference of about 6.6 times between the maximum bus speed and the guaranteed speed of speed guaranteed recording.
  • the present inventors newly provided a means for notifying the memory card of information instructing the transition to the optimal performance operation mode from the host device, thereby allowing the memory card to maintain a speed guarantee record.
  • FIG. 19 shows an example of a command sequence when speed guaranteed recording is performed on an SD memory card.
  • the horizontal axis indicates time, and the recording device 100 issues commands to the memory card 200 in order from the left side to the right side of the figure.
  • the command is written as "CMD” and is sent from the host device to the SD memory card.
  • CMD20 is a control command issued when performing speed guaranteed recording in the SD memory card.
  • FIG. 17 shows a data structure 600 of "CMD20".
  • Speed guarantee recording is realized by parameters specified by "Speed Class Control (SCC)", “CNT/ID”, and "ADDR" of "CMD20".
  • SCC location of the directory entry of the data stream to be written
  • the file name, attributes, etc. of the data stream to be written are recorded in the directory entry.
  • CMD24 800-1 is issued, and writing (recording) to the directory entry is performed.
  • AU allocation unit
  • the SD memory card standard stipulates that the data stream is written for each free allocation unit (free AU). At this time, the number of free allocation units (vacant AUs) that can be consecutively secured is specified in the "CNT/ID" field (FIG. 17). The maximum number that can be specified is 8, and the "CNT/ID” field is 3 bits long.
  • speed guaranteed recording which is represented as a "speed class recording section" in FIG. 19, is performed.
  • data write commands "CMD25" 800-2 and 800-4 are issued from the host device to the SD memory card, and speed guarantee data to be written, such as photographed video data, is transmitted.
  • the "speed class recording section” ends when another write command (800-6) is issued.
  • the host device As a means for the host device to notify the SD memory card of information instructing the transition to the optimum performance operation mode, the unused (Reserved) argument of the existing command (CMD) specified in the SD memory card standard is used.
  • CMD existing command
  • Various concrete methods can be considered, such as a method or a method of newly defining a command that is not specified in the SD memory card standard.
  • FIG. 18 shows that the host device uses SD An example is shown in which information "OMPREQ” (Optimal Minimum Performance Request) instructing a transition to the optimum performance operation mode is assigned to the memory card.
  • OMPREQ Optimal Minimum Performance Request
  • the host device notifies the SD memory card of information instructing the transition to the optimal performance operation mode, and then executes speed guaranteed recording.
  • FIG. 21 shows an example of a command sequence when the host device notifies (presents) information instructing the transition to the optimal performance operation mode to the SD memory card and then executes speed guarantee recording.
  • the command is written as "CMD" and is sent from the host device to the SD memory card.
  • CMD20 is a control command issued when performing speed guaranteed recording in the SD memory card.
  • FIG. 18 shows the data structure 600 of "CMD20".
  • Speed guarantee recording is realized by parameters specified by "Speed Class Control (SCC)", “CNT/ID”, and "ADDR" of "CMD20".
  • the directory entry records the file name, attributes, etc. of the data stream to be written.
  • "CMD24" 800-1 is issued and writing to the directory entry is performed.
  • AU allocation unit
  • the SD memory card standard stipulates that the data stream is written for each free allocation unit (free AU). At this time, the number of free allocation units (vacant AUs) that can be consecutively secured is specified in the "CNT/ID" field (FIG. 18). The maximum number that can be specified is 8, and the "CNT/ID” field is 3 bits long.
  • CMD20 700-6 notifies the SD memory card of an instruction to shift to the optimal performance operation mode.
  • the SD memory card When the SD memory card receives "CMD20" 700-6 and recognizes the instruction to transition to the optimum performance operation mode, the SD memory card operates at the minimum performance necessary to execute speed guarantee recording, and Shifts to an operation mode that keeps the power consumption of the memory card low, expressed as a ⁇ performance operation section''.
  • the PCIe interface 214a, 214b, 314a, or 314b with the host device shown in FIGS. 2 and 3 is generally used.
  • the total power consumption of the CPU 212, buffer memory 216, and NAND control unit 218 inside the controller 210 shown in FIGS. 2 and 3, and the power consumption of the NAND flash memory 220 are much larger.
  • the power consumption is 60 mW.
  • the maximum power consumption of an SD memory card equipped with a UHS-II interface is 1.80W, which is approximately 30 times the power consumption of the UHS-II interface 314a.
  • circuit blocks inside the controller 210 and the NAND flash memory normally operate with a clock that is multiplied and/or divided based on the clock generated (transmitted) by the oscillator 219 shown in FIGS. 2 and 3.
  • the controller 210 When a command is not issued from the host device for a certain period of time, the controller 210 lowers the clock frequency by dividing the clock supplied to the circuit blocks inside the controller 210 in order to keep power consumption as low as possible. As a result, a mechanism for transitioning to power saving mode is widely and generally provided.
  • the clock supplied to the circuit block inside the controller 210 is set to the maximum clock frequency and operated, and after receiving "CMD20" 700-6, In the "optimal performance operation section", power saving control such as setting and operating the minimum clock frequency necessary to execute speed guaranteed recording can be considered.
  • speed guaranteed recording which is represented as a "speed class recording section" in FIG. 21, is performed.
  • data write commands "CMD25" 800-2 and 800-4 are issued from the host device to the SD memory card, and speed guarantee data to be written, such as photographed video data, is transmitted.
  • the "speed class recording section” ends when another write command (800-6) is issued.
  • the SD memory card can maintain a speed guarantee record. It operates with the minimum performance necessary for execution, keeping the power consumption of the memory card low, and as a result, it becomes possible to suppress the heat generation of the host device and the SD memory card.
  • a method using "CMD20" of the SD memory card standard is shown as an example of a means for the host device to notify the memory card of information instructing the transition to the optimum performance operation mode.
  • the present inventors have developed a mechanism to realize the function of "CMD20" in the SD memory card standard using commands that comply with the NVMe standard. This allows the host device to notify the memory card of information instructing it to transition to the optimum performance operating mode.
  • the SCC, CNT/ID, and ADDR in "CMD20" of the SD memory card standard shown in FIG. command data write command
  • Dword “13” bit “31” to bit “28” (4-bit area)
  • Dword “13” bit “26” to bit “24” (3-bit area)
  • Dword It is directly allocated to bits “5" to “0” of "10” and bits “31” to “10” of Dword "11” (a total of 28 bits).
  • the NVMe standard defines two types of command sets: the Admin Command Set and the NVM Command Set, and the Admin Command Set is mainly non-volatile.
  • a group of control commands for a storage device to read information related to the functions, performance, and specifications of a nonvolatile storage device, or to configure various settings for a nonvolatile storage device.
  • DSM command DataSet MANAGEMENT COMMAND (hereinafter abbreviated as "DSM command") in the NVM COMMAND set shown in FIG. RANGES “7" to bit “0”), AD (Attribute-Deallocate) of Dword “11" (bit “2”), IDW (Attribute-Integral Dataset for Write) (bit “1"), IDR (Attribute - Integral Dataset for Read) (bit “0”) and the Range list stored in the Data Pointer (memory address of the main memory of the recording device 10, etc.) of Dword “6” to Dword “9”.
  • DSM command DataSet MANAGEMENT COMMAND
  • AD Attribute-Deallocate
  • IDW Attribute-Integral Dataset for Write
  • IDR Attribute - Integral Dataset for Read
  • Range list stored in the Data Pointer (memory address of the main memory of the recording device 10, etc.) of Dword
  • FIG. 26 shows Dword “10” and Dword “11” of the DSM command of the NVMe standard, values set in the Range list, setting values such as Range attribute information set in the Range list, and “CMD20”. ” is a table showing an example of correspondence with eight functions of SCC.
  • Range attribute information is 32-bit information shown in the lower table on the left side of FIG. 26 as "Range: Context Attributes.”
  • Update DIR is a function for notifying the location of a directory entry from the host to the card
  • Update CI is a function for notifying that the host is writing CI (Continuous Information) to the card. This is a function to notify the card that small data such as directory entries and FAT (File Allocation Table) will be written, unlike continuous stream recording data such as video shooting.
  • Update DIR and Update CI are combined into one function, which is called Update DIR/CI.
  • the instruction to shift to the optimum performance operation mode is performed by setting bit "03" of Dword “11" of the DSM command to "1". That is, bit “03" of Dword “11” of the DSM command is assigned to information "OMPREQ” (Optimal Minimum Performance Request) that instructs transition to the optimal performance operation mode. (Note that bits “31” to “03” of Dword “11” of the DSM command are unused (Reserved) bits in NVM Express Base Specification Revision 1.4).
  • the embodiment of the present disclosure describes a method of using "CMD20" of the SD memory card standard as an example of a means for the host device to notify the memory card of information instructing the transition to the optimum performance operation mode.
  • the present inventors realized the function of "CMD20" in the SD memory card standard using commands compliant with the NVMe standard, as shown in FIGS. 25 and 26.
  • speed-guaranteed recording control can be performed using commands compliant with the NVMe standard as shown in FIGS. 20 and 22, without changing the command sequence during speed-guaranteed recording on the SD memory card shown in FIGS. 19 and 21. becomes possible.
  • NVMe CMD NVMe command
  • 700-1, 700-2, 700-3, 700-6 are DSM commands
  • 800-1, 800-2, 800-3, 800-4, 800-5 are Write commands of the NVMe standard. (data write command).
  • control commands other than "CMD20" in the SD memory card standard control registers in the memory card, NAND flash memory, etc. It is also possible for the host device to notify the memory card of information instructing the transition to the optimum performance operating mode by using a write command.
  • control command that sets a power consumption limit according to the SD memory card standard or a control command that performs power consumption management according to the NVMe standard.
  • CMD6 is a Switch Function Command in a conventional SD memory card, and is a control command issued when limiting the power consumption of the SD memory card or switching the interface mode.
  • FIG. 27 shows the data structure of the command argument (argument: Arg. Slice) in “CMD6”.
  • CMD6 switching between the UHS-I bus speed modes SDR25, DDR50, SDR50, and SDR104 shown in FIG. Directed by. That is, when 1h is set in bit “3" to bit “0”, it is an instruction to switch to SDR25, and similarly, when 2h is set in bit “3” to bit “0”, it is an instruction to switch to SDR50. , when 3h is set in bit “3” to bit “0”, it is an instruction to switch to SDR 104, and when 4h is set in bit "3" to bit “0”, it is an instruction to switch to DDR 50.
  • bits “15” to “12” of the command argument of CMD6 shown in FIG. 27 are bits for switching the power consumption limit.
  • bit “15” to bit “12” When bit “15” to bit “12” are set to 0h, it instructs the SD memory card to operate in a mode that suppresses the maximum power consumption to 0.72W or less.
  • 1h When 1h is set to ⁇ , the operation is instructed in a mode that suppresses the power to 1.44W or less, and when 2h is set to bits ⁇ 15'' to ⁇ 12,'' the operation is instructed to be operated in a mode that is suppressed to 2.16W or less.
  • CMD6 of the SD memory card standard and set the power commensurate with the guaranteed speed. That is, it is possible to replace 700-6 “OMPREQ” in FIG. 21 with “CMD20” and then execute it with "CMD6".
  • FIG. 28 is a diagram showing the data structure of the Set Features command that belongs to the Admin Command Set of the NVMe standard.
  • Bits “7” to “0” of Dword “10” in the set features command are feature identifiers, which are the IDs (identifiers) of the functions to be set with the set features command. This is a field to specify.
  • FIG. 29 shows a list of various functions set by the set features command and their IDs (Feature Identifiers).
  • Bit “31” to bit “0” of Dword “11” in the set features command are parameters.
  • the parameters are defined for each function specified by the feature identifier (bit “7” to bit “0” of Dword “10").
  • the feature identifier "02h" shown in FIG. 29 is Power Management (power consumption management function), and the parameters of the Power Management (power consumption management function) are shown in FIG.
  • Bits “7” to “5” of Dword “11” shown in FIG. Bits “4” to “0” of Dword “11” are Power State (power consumption state), which is one of the multiple power consumption states supported by the nonvolatile storage device. Used to specify and operate in one power consumption state.
  • the host device uses the Power Management (power consumption management function) of the set features command of the NVMe standard to set the power consumption state commensurate with the guaranteed speed. It is possible to do this. That is, it is possible to execute 700-6 "OMPREQ" in FIG. 22 with a set features command.
  • Power Management power consumption management function
  • FIG. 31(a) shows the power consumption status of each SD Express card type, which the card is required to have according to the SD standard.
  • SD Express cards There are four types of SD Express cards: a card with a PCIe interface Gen3 (3rd generation) x 1 lane (denoted as “PCIe G3x1" in the diagram), and a PCIe interface Gen3 (3rd generation) x 2 A card with a PCIe interface Gen4 (4th generation) 4th generation) x 2 lanes (denoted as "PCIe G4x2" in the figure).
  • PCIe G3x1 card and PCIe G4x1 card that support one lane of the PCIe interface are equipped with the terminals shown in Figure 6, and the PCIe G3x2 card and PCIe G4x2 card that are compatible with two lanes of the PCIe interface are equipped with the terminals shown in Figure 7. Be prepared.
  • PCIe G3x2 (a card with two Gen3 lanes)
  • PCIe G4x1 (a card with one Gen4 lane) has the same interface speed as a card (non-volatile storage device).
  • the SD standard specifies that card type PCIe G3x2 and card type PCIe G4x1 have the same five required power consumption states.
  • FIG. 31(a) shows the power consumption status of each SD Express card type, which the card is required to have according to the SD standard. An example of the power consumption state of an actual SD Express card is shown.
  • the NVMe standard that the SD standard refers to and complies with allows a card (non-volatile storage device) to have a maximum of 32 power consumption states.
  • the host device issues a 4,096-byte identify controller data structure (Identify Controller Data structure) from the card with the identify command issued to the card.
  • Identify Controller Data structure Specifications indicating the power consumption state of the card are defined in bytes 2048 to 3071 of the structure.
  • a card can have a maximum of 32 power consumption states (Power State 0 to 31), but it is only required to have at least one power consumption state.
  • a PCIe G3x1 card has an optional power consumption state of 1.6W in addition to the required power states of 1.8W, 1.44W, and 0.72W specified by the SD standard.
  • An example is shown below.
  • the power consumption states indicated by hatching in the figure (table) are not required by the SD standard; in other words, the card (non-volatile storage device) is provided as one implementation (one design), and the SD standard makes it optional. It shows the power consumption states that are positioned, and indicates that the power consumption states without hatching are the power consumption states that are required for each card type according to the SD standard.
  • FIG. 31(b) shows the required power consumption states of 2.8W, 2.5W, 1.8W, 1.44W, and 0.72W as defined by the SD standard.
  • it shows that it has optional power consumption states of 2.0W and 1.6W
  • in the example of a PCIe G4x1 card it has optional power consumption states of 2.3W, 2.1W, and 1.6W.
  • in the example of a PCIe G4x2 card it is shown to have optional power consumption states of 2.2W and 1.6W.
  • the number of power consumption states and the power value of a card differ depending on each manufacturer and each product.
  • the host device knows in advance the number of power consumption states of the card installed in the host device and the power value of each power consumption state in a phase called initialization immediately after power is turned on to the card. It is necessary to keep it.
  • the number of power consumption states provided by the card and the respective power consumption values can be read from the card by the host device using an identify command that belongs to the NVMe standard's Admin Command Set. is now possible.
  • NPSS Power States Support
  • Bit24 shows the scale of Maximum Power (MP) as Max Power Scale (MXPS), so the power in watts can be calculated by multiplying the value of MP by the scale shown in MXPS. , can be found.
  • MXPS Max Power Scale
  • the host device reads information regarding the number of power consumption states and the power consumption value of the card from the card, and then specifies (sets) the desired power consumption state for the card.
  • the Power State value is set in bits "4" to "0" of Dword "11" in the set features command shown in FIG. 30, and the command is issued to the card.
  • the power consumption states are assigned consecutive numbers starting from 0 so that each subsequent power consumption state is less than or equal to the power of the previous state. (Power State value) is attached. Therefore, power consumption state 0 (PS0) indicates the maximum power consumption that the SD Express card can consume.
  • a card can have multiple power consumption states, and the number of power consumption states a card has and the power consumption value of each power consumption state vary depending on the individual manufacturer and the individual card.
  • the host device can learn the number of power consumption states that the card has and the power consumption value of each power consumption state by issuing an identify command.
  • the host device there is no way for the host device to know the power consumption required by the card when recording data such as videos on a card (non-volatile storage device) at the desired guaranteed speed.
  • the power consumption state specified for the card by issuing the features command there is insufficient power to record to the card (non-volatile storage device) at the desired guaranteed speed, and speed guaranteed recording cannot be performed correctly, or Additionally, there was a problem in that the card consumed more power than was necessary to record on the card at the desired guaranteed speed, causing the card's temperature to rise and making it impossible to continue recording at the guaranteed speed. .
  • the inventors of the present invention have proposed that the card notifies the host device of the power consumption status in order to reduce the performance necessary and sufficient to record data such as videos on the card at the desired guaranteed speed. We considered a new mechanism to do so.
  • the NVMe standard requires 263 bytes of the 4,096-byte Identify Controller Data Structure (Identify Controller Data Structure) read from the card with the identify command to determine the number of power consumption states that the card has.
  • the number of Power States Support (NPSS) is shown in the range of 1 to 32, and the power consumption value of each power consumption state of the card is shown in the IDENTIFER as shown in FIG. This is shown in 2,048 to 3,071 bytes of the 4,096-byte identify controller data structure read from the card with the i command.
  • the card non-volatile storage device notifies the host device of the power consumption status required to operate at the necessary and sufficient performance to record data such as videos on the card at the desired guaranteed speed.
  • FIG. 32 shows the Vendor Specific area of the Identify Controller Data Structure.
  • the Vendor Specific area is allocated to 3072 to 4096 bytes.
  • FIG. 33 is a diagram showing an example of information newly allocated to the area.
  • bytes 3072 to 3073 of the Vendor Specific area indicate the value of the speed guarantee class (SD Express speed class) that the card supports.
  • SD Express speed class the speed guarantee class
  • a Gen3x1 card supports speed guarantee class 150 (150MB/s), class 300 (300MB/s), class 450 (450MB/s), and class 600 (600MB/s).
  • 01C2h 450 (decimal number) is displayed in bytes 3072 to 3073 of the Vendor Specific area.
  • the values shown here are the speed values of the fastest guaranteed speed class supported by the card.
  • bytes 3088 to 3103 of the Vendor Specific area indicate to the host device the combination of speed guarantee class and bus mode, and the necessary and minimum power consumption state of the card in the combination. defined as an area.
  • Bit [7] (MSB: most significant bit) in each byte from 3088 to 3103 indicates which bus mode and speed guarantee class the card (non-volatile storage device) supports, and is set to “0”. indicates invalidity, ie, non-compatibility, and “1” indicates validity, ie, compatibility.
  • the Gen4x1 card has Gen4x1 and Gen3x1 as bus modes.
  • the SD standard requires cards with faster bus modes to support lower speed bus modes in order to maintain backward compatibility.
  • Gen4x1 card is not compatible with Gen3x2 because it has only one row of terminals for PCIe as shown in FIG.
  • Gen4x2 card since the Gen4x2 card has two rows of PCIe terminal groups as shown in FIG. 7, it supports all four bus modes: Gen4x2, Gen4x1, Gen3x2, and Gen3x1.
  • Gen4x1 card 3092 to 3095 (a combination of Gen3x2 and each SC (speed guarantee class)) indicating the Power State of the bus mode that requires two rows of PCIe terminal groups shown in Figure 7.
  • Bit[7] MSB: most significant bit
  • MSB most significant bit
  • FIG. 34(b) is a reproduction of FIG. 31(b).
  • the Gen4x1 card has five required power consumption states (2.8W, 2.5W, 1.8W, 1.44W, 0.71W) specified by the SD standard, and three In the example with optional power consumption states (2.3W, 2.1W, 1.6W), the card has four speed guarantee classes (SD Express speed class), namely "Class 150" of 150MB/s, If it supports all of 300MB/s "Class 300", 450MB/s "Class 450", and 600MB/s "Class 600", video recording in each SC (speed guarantee class) can be done with Gen3x1.
  • FIG. 34(a) shows an example of the minimum power consumption necessary for execution in the Gen4x1 bus mode.
  • the minimum and sufficient power consumption state necessary to perform speed guarantee recording for each speed guarantee class (speed class) for each card type and bus mode is defined as a "speed class”. ⁇ Defined as "Power State (Speed Class Power State)".
  • the speed class power state is PS 2
  • 2.3W is necessary and sufficient/minimum. It can be seen that the power is
  • the speed class power state when executing class 300 speed guarantee recording is 1.8W of PS 4
  • the speed class power state when executing class 150 speed guarantee recording is PS 5. It becomes 1.6W.
  • the figure shows an example of notifying the speed class and power state of the Gen4x1 card to the host device using the Vendor Specific area 3088 bytes to 3103 bytes of the Identify Controller Data Structure (ICDS). 35(b).
  • ICDS Identify Controller Data Structure
  • FIG. 34(a) is reprinted in FIG. 35(a).
  • Bit[7] of 3092 bytes to 3095 bytes and 3100 bytes to 3103 bytes is a value indicating "invalid". "0" is stored and notified.
  • the above Gen4x1 card supports all four speed classes in the two bus modes of Gen4x1 and Gen3x1, so the Bit[ 7], the value "1" indicating "valid” is stored and notified.
  • Bits “4:0” from 3088 bytes to 3091 bytes and from 3096 bytes to 3099 bytes contain the state value itself of the speed class power state shown in FIG. 34(a) and FIG. 35(a). is stored and notified.
  • FIG. 36 shows an example of a command sequence when speed-guaranteed recording is performed on an SD Express card.
  • the horizontal axis indicates time, and the recording device 100 issues commands to the memory card 200 in order from the left side to the right side of the figure.
  • the rectangular symbols (graphic elements of the sequence) shown from 700-1 to 700-6, from 800-1 to 800-6, and from 900-1 to 900-2 are sent from the host device to the SD Express Represents the functionality of the command sent to the card.
  • command names are written in the oval symbols (graphical elements of the sequence) written below the rectangular symbols, and in the example of FIG. 36, all commands are MVMe standard commands.
  • FIG. 36 shows the basic sequence for speed guaranteed recording shown in FIG. 22 with the following processing added.
  • the host device turns on the power to the SD Express card installed in the host device (supplies power).
  • the host device executes initialization processing for the SD Express card.
  • the initialization process means that the host device reads the card's supported functions, performance, and card-specific information such as the manufacturer ID from the card. This process performs settings related to the functions used by the computer, performance, etc.
  • 700-4 is the issuance of an identify command that is executed as part of the initialization process described above, and by issuing this command, the host device transfers the identify controller consisting of 4,096 bytes from the card. - Read the data structure (ICDS: Identify Controller Data Structure).
  • the ICDS notifies the host device from the card of the number of power consumption states defined by the NVMe standard and the power consumption value of each of the power consumption states.
  • the host device issues the identify command 700-4, and based on the number of power consumption states in the ICDS acquired from the Gen4x1 card and the power consumption value of each of the power consumption states, the Gen4x1 The card's maximum power consumption state is set using the Set Features command.
  • a digital single-lens reflex camera, etc. can simultaneously process very high-pixel still image RAW data (unprocessed data) and still image JPEG data (compressed data) at 20 frames per second.
  • RAW data unprocessed data
  • JPEG data compressed data
  • RAW data refers to unprocessed image data output from an image sensor, and is raw data from an image sensor that cannot be viewed as a photograph unless it undergoes color restoration processing.
  • JPEG data is processed by processing the RAW data to restore colors, and in addition, data compression is performed by thinning out information on the intensity of light. It is common practice to record simultaneously with RAW data.
  • the default power consumption state (initial power state after power-on) of the SD Express card is defined as 1.8W in the SD standard.
  • the PS (power consumption state) of the Gen4x1 card is switched from PS 4 (1.8 W) to PS 0 (2.8 W) by the set features command of 700-5.
  • 700-6 is the issuance of a command shown in FIG. 22 to notify the information "OMPREQ” (Optimal Minimum Performance Request) instructing the transition to the optimal performance operation mode.
  • OMPREQ Optimal Minimum Performance Request
  • the host device issues a set features command to the Gen4x1 card, and thereafter notifies the Gen4x1 card to operate in the power consumption state of PS 5 (1.8W) in order to perform class 150 speed guarantee recording. are doing.
  • the Gen4x1 card shifts to the minimum power consumption state necessary and sufficient to perform guaranteed speed recording of 150 MB/s, that is, the optimal performance operating mode.
  • the host device receives from the card the number of power consumption states of the card, the power consumption value of each of the power consumption states, and the speed shown in FIG. 33 etc. newly devised and defined in this disclosure. ⁇ Based on class and speed class power state information, determine the sufficient and optimal (minimum) power required by the card to record the desired speed (desired speed class) of the host device. It becomes possible to set the power consumption state.
  • a nonvolatile storage device operates in a power consumption state commensurate with the guaranteed speed.
  • a nonvolatile storage device including an SD memory card on which NAND flash memory (nonvolatile memory) is mounted
  • the power consumption is 61 mW in the circuit implementation example of the PCIe interface 214a in FIG. 2.
  • the maximum power consumption of the SD Express card equipped with a PCIe interface is 4.00W, which is approximately 65 times the power consumption of the PCIe interface 214a.
  • circuit blocks inside the controller 210 and the NAND flash memory normally operate with a clock that is multiplied and/or divided based on the clock generated (transmitted) by the oscillator 219 shown in FIGS. 2 and 3.
  • the controller 210 divides the clock supplied to the circuit blocks inside the controller 210 in order to keep power consumption as low as possible when no command is issued from the host device (recording device 100) for a certain period of time. , is widely and generally equipped with a mechanism for transitioning to multiple power-saving modes by lowering the clock frequency in stages.
  • the clock supplied to the circuit blocks inside the controller 210 is set to the maximum clock frequency.
  • the "optimal performance operation section" after operating and receiving the set features command Power Management (power consumption management function) setting 700-6 (OMPREQ) set the power consumption state setting value commensurate with the guaranteed speed.
  • an implementation may be considered in which the clock frequency is lowered, that is, the clock frequency is lowered to the minimum clock frequency required to execute speed guaranteed recording.
  • the maximum bus speed in the bus speed mode "UHS-II HD312" is 312 MB/s, while the maximum bus speed in "SD Express PCIe Gen4x2" is 3,938 MB/s. /second, the speed (bus speed) is more than 12 times faster.
  • the maximum power consumption in bus speed mode "UHS-II HD312" is 1.80W, while in “SD Express PCIe Gen4x2" the maximum power consumption is 4.00W. , the power consumption is more than double.
  • the optimum performance operation mode is effective only when the more effective PCIe interface is used and data recording is performed in accordance with the NVMe standard protocol.
  • the recording device of the present disclosure is a recording device that records data on a nonvolatile storage device in a recording mode in which a minimum recording speed is guaranteed,
  • the nonvolatile storage device is removable from the recording device and has a memory that records data in accordance with the NVMe standard and/or the SD memory card standard.
  • Memory has a guaranteed recording speed for continuous stream recording.
  • the recording device includes an interface section that is physically connected to the nonvolatile storage device and can send at least data write commands and control commands to the nonvolatile storage device.
  • the interface unit is capable of transmitting control commands including a data write command for recording data, a command for instructing speed-guaranteed recording, and/or a command for reading and writing registers in the nonvolatile storage device. be.
  • the control command includes information that instructs transition to the optimum performance operating mode during continuous stream recording.
  • the interface unit sends control commands to the nonvolatile storage device to notify information instructing speed-guaranteed recording and shifting to an optimal performance operation mode, and also sends data for performing continuous stream recording. is sent using the data write command.
  • the nonvolatile storage device of the present disclosure is a nonvolatile storage device that can record data in a recording mode with a guaranteed minimum recording speed.
  • the nonvolatile storage device is removable from the recording device.
  • the nonvolatile storage device includes a memory, an interface unit that communicates with the recording device, and a memory control unit that records data in the memory in accordance with the NVMe standard and/or the SD memory card standard.
  • Memory has a guaranteed recording speed for continuous stream recording.
  • the nonvolatile storage device includes an interface unit that is physically connected to the recording device and can receive at least data write commands and control commands from the recording device.
  • the interface unit receives control commands from the recording device, including a data write command for recording data, a command for instructing speed-guaranteed recording, and/or a command for reading and writing registers in the nonvolatile storage device. is possible.
  • the control command includes information that instructs transition to the optimum performance operating mode during continuous stream recording.
  • the interface unit receives a control command, and then receives a data write command and data for recording data.
  • the memory control unit shifts to an operating mode necessary and sufficient to guarantee speed based on the information included in the control command that instructs the transition to the optimal performance operating mode, and performs continuous data recording based on the data write command. I do.
  • the recording method of the present disclosure is a recording method executed in a recording device that records data on a nonvolatile storage device in a recording mode in which a minimum recording speed is guaranteed.
  • the nonvolatile storage device is removable from the recording device and has a memory that records data in accordance with the NVMe standard and/or the SD memory card standard.
  • Memory has a guaranteed recording speed for continuous stream recording.
  • the recording device includes an interface unit that is physically connected to the nonvolatile storage device and can send at least a data write command and a control command to the nonvolatile storage device.
  • the interface unit is capable of transmitting control commands including a data write command for performing data recording, a command for instructing speed-guaranteed recording, and/or a command for reading and writing registers in the nonvolatile storage device. It is.
  • the control command includes information that instructs transition to the optimum performance operating mode during continuous stream recording.
  • the recording method is such that the interface section sends a control command to the nonvolatile storage device to notify the nonvolatile storage device of information instructing speed-guaranteed recording and transitioning to an optimal performance operation mode, and transmitting the control command. After that, it includes sending a data write command and data to perform continuous data recording.
  • OMPREQ is provided as a new command as shown in FIGS. 21 and 22, but it may be integrated into "StartREC".
  • the present disclosure can be suitably used in a storage system that uses a recording device that is a host device and a nonvolatile storage device 20.

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PCT/JP2023/032655 2022-09-16 2023-09-07 記録装置、不揮発性記憶装置、及び記録方法 Ceased WO2024058042A1 (ja)

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JP2010079372A (ja) * 2008-09-24 2010-04-08 Toshiba Corp 記憶装置、バステスト方法、及びデータ転送モード切替方法
US20210382621A1 (en) * 2020-06-08 2021-12-09 Western Digital Technologies, Inc. Attribute Mapping in Multiprotocol Devices
JP2022112909A (ja) * 2021-01-22 2022-08-03 キヤノン株式会社 電子機器、撮像装置およびそれらの制御方法

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JP2010079372A (ja) * 2008-09-24 2010-04-08 Toshiba Corp 記憶装置、バステスト方法、及びデータ転送モード切替方法
US20210382621A1 (en) * 2020-06-08 2021-12-09 Western Digital Technologies, Inc. Attribute Mapping in Multiprotocol Devices
JP2022112909A (ja) * 2021-01-22 2022-08-03 キヤノン株式会社 電子機器、撮像装置およびそれらの制御方法

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