WO2024057591A1 - Rectifier circuit and power supply using same - Google Patents

Rectifier circuit and power supply using same Download PDF

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Publication number
WO2024057591A1
WO2024057591A1 PCT/JP2023/013972 JP2023013972W WO2024057591A1 WO 2024057591 A1 WO2024057591 A1 WO 2024057591A1 JP 2023013972 W JP2023013972 W JP 2023013972W WO 2024057591 A1 WO2024057591 A1 WO 2024057591A1
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Prior art keywords
terminal
switching element
voltage
capacitor
rectifier circuit
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PCT/JP2023/013972
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French (fr)
Japanese (ja)
Inventor
明寛 三輪
浩幸 庄司
順一 坂野
智之 内海
孝裕 樋口
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株式会社日立パワーデバイス
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Publication of WO2024057591A1 publication Critical patent/WO2024057591A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal

Definitions

  • the present invention relates to a rectifier circuit and a power supply using the same.
  • Examples of rectifier circuits that realize synchronous rectification include Patent Document 1 and Patent Document 2.
  • a rectifier circuit that performs synchronous rectification generally includes a MOSFET that is a first switching element for synchronous rectification, a drive circuit for the MOSFET, a capacitor that supplies power to the drive circuit, and a MOSFET that controls the voltage of the capacitor. It has two switching elements and a control circuit for the second switching element.
  • the drive circuit controls on/off of the MOSFET based on a predetermined threshold voltage and the detected drain-source voltage of the MOSFET.
  • FIG. 9 is a diagram showing operating waveforms of a conventional rectifier circuit.
  • the vertical axis represents voltage or current
  • the horizontal axis represents time t.
  • the capacitor that supplies power to the drive circuit connects the drain terminal of the MOSFET to the second switching terminal between time t1 and time t2 after the gate-source voltage Vgs1 of the MOSFET becomes 0 at time t0 and the MOSFET is turned off. It is charged by the current flowing through the source terminal of the element, capacitor, and MOSFET. When charging of the capacitor starts, the voltage Vc1 of the capacitor increases to follow the drain-source voltage Vds1 of the MOSFET.
  • the second switching element inserted between the drain terminal of the MOSFET and the positive terminal of the capacitor is turned off. Cut off the charging current Ic.
  • the capacitor voltage Vc1 is controlled to be equal to or lower than the target voltage Vcref1.
  • the power accumulated in the capacitor is consumed by the standby power of the drive circuit, so the voltage Vc1 of the capacitor decreases. do.
  • the MOSFET is turned on starting from time t5
  • the MOSFET is turned off again at the next time t0 and the capacitor starts charging at time t1.
  • the power accumulated in the capacitor is then consumed by the drive circuit.
  • the voltage on the capacitor continues to decrease as it is used to generate power or the gate-to-source voltage of the MOSFET.
  • the voltage Vc1 of the capacitor is, for example, the guaranteed operation voltage of the drive circuit or the voltage of the MOSFET. It is necessary to set the voltage lower limit value Vcref2 of the capacitor so that it is equal to or higher than the gate threshold voltage, and to select the capacitance of the capacitor so as to satisfy this value.
  • the problem to be solved by the present invention is that in a rectifier circuit using a switching element for rectification, it is possible to reduce the required capacity of a capacitor that supplies power to a drive circuit for driving the switching element for rectification.
  • the object of the present invention is to provide a rectifier circuit that can be made smaller and lower in cost by reducing the volume of a capacitor, and a power supply using the rectifier circuit.
  • a rectifier circuit of the present invention includes, for example, a rectifier circuit having an anode and a cathode, in which a first terminal is connected to the cathode of the rectifier circuit, and a second terminal is connected to the rectifier circuit.
  • a first switching element connected to the anode of the first switching element;
  • a first diode having a cathode connected to the first terminal and an anode connected to the second terminal; and driving the first switching element.
  • the battery is characterized by having a charging stop period.
  • the power supply of the present invention is characterized in that it includes, for example, the above-mentioned rectifier circuit.
  • the capacitor is charged in two times, the first charging period and the second charging period, and the amount of the capacitor discharged during the charging stop period after the first charging period is Since at least a portion of the charge can be compensated for in the second charging period, the required capacitance of the capacitor can be reduced, and as a result, the volume of the capacitor can be reduced, making it possible to realize miniaturization and cost reduction of the rectifier circuit and power supply.
  • FIG. 3 is a circuit diagram of a rectifier circuit of Example 1.
  • 3 is a diagram showing operating waveforms of the rectifier circuit of Example 1.
  • FIG. FIG. 2 is a circuit diagram of a rectifier circuit according to a second embodiment.
  • FIG. 3 is a circuit diagram of a rectifier circuit according to a third embodiment.
  • FIG. 4 is a circuit diagram of a rectifier circuit according to a fourth embodiment.
  • FIG. 7 is a diagram showing an example of a configuration of a rectifier circuit according to a fifth embodiment. 7 is a diagram showing another example of the configuration of the rectifier circuit of Example 5.
  • FIG. FIG. 7 is a circuit diagram of a power supply according to a sixth embodiment. The figure which shows the operating waveform of the conventional rectifier circuit.
  • FIG. 1 is a circuit diagram of the rectifier circuit of Example 1.
  • the rectifier circuit 2 of the first embodiment includes an anode A, a cathode K, a MOSFET Q1 which is a first switching element for rectification, a body diode DQ1 of the MOSFET Q1, and a drive circuit that drives the MOSFET Q1. 1 and a capacitor C1 that supplies power to the drive circuit 1. Furthermore, the rectifier circuit 2 of the first embodiment includes a second switching element MOSFETQ2 for controlling the voltage Vc1 of the capacitor C1, a body diode DQ2 of the MOSFETQ2, a control circuit CTR for controlling the MOSFETQ2, and a diode D. has.
  • the drive circuit 1 includes a comparator Co1 and a gate driver GD1.
  • an n-channel enhancement type MOSFET is used as the MOSFET Q1
  • an n-channel depletion type MOSFET is used as the MOSFET Q2
  • the present invention is not limited to this, and other switching elements may be used.
  • the body diode DQ1 and the body diode DQ2 are not limited to body diodes built into the MOSFET, and other diodes such as external diodes may be used.
  • MOSFET Q1 has a gate terminal that is a control terminal, a drain terminal that is one main terminal, and a source terminal that is the other main terminal.
  • MOSFET Q1 is a switching element for rectification, and has a drain terminal connected to the cathode K of the rectifier circuit 2, a source terminal connected to the anode A of the rectifier circuit 2, and a gate terminal connected to the drive circuit 1.
  • the body diode DQ1 has a cathode connected to the drain terminal of MOSFETQ1, and an anode connected to the source terminal of MOSFETQ1.
  • FIG. 2 is a diagram showing operating waveforms of the rectifier circuit of Example 1.
  • FIG. 2 is a diagram corresponding to FIG. 9, and shows operating waveforms when a resistive load is connected to a bridge circuit configured using four rectifier circuits 2 shown in FIG. 1 and a sine wave voltage is input.
  • the vertical axis indicates the drain-source voltage Vds1 of MOSFET Q1, the gate-source voltage Vgs1 of MOSFET Q1, the charging current Ic of capacitor C1, and the voltage Vc1 of capacitor C1, and the horizontal axis indicates time t.
  • Vgth1 is the gate threshold voltage of MOSFETQ1. Note that illustration and detailed description of the drain-source voltage Vds2 of MOSFETQ2, the gate-source voltage Vgs2 of MOSFETQ2, and the gate threshold voltage Vgth2 of MOSFETQ2 are omitted.
  • the capacitor C1 that supplies power to the drive circuit 1 is connected to the Between the first charging period (from time t1 to time t2) and the second charging period (from time t3 to time t4) during which capacitor C1 of No. 1 is charged, and between the first charging period and the second charging period.
  • the capacitor is charged only once from time t1 to time t2, and thereafter, the capacitor is charged so that the capacitor voltage Vc1 can be maintained at a voltage lower limit value Vcref2 or higher until the next charging period, time t1. It is necessary to select the capacity of
  • the capacitor C1 is charged in two times, the first charging period and the second charging period, and the charging stop period is performed after the first charging period. Since at least a part of the discharged amount can be compensated for in the second charging period, the required capacity of the capacitor C1 can be reduced, and as a result, the volume of the capacitor C1 can be reduced and the rectifier circuit 2 and the rectifier circuit using it can be reduced. It is possible to realize smaller power supplies and lower costs. Further, it becomes possible to use a drive circuit and a control IC that consume a large amount of power during the off period of the MOSFET.
  • the first charging period and the second charging period are periods in which the drain-source voltage Vds1 of MOSFET Q1 is equal to or lower than a predetermined threshold voltage Vref1, and the charging stop period is a period between the drain-source of MOSFET Q1.
  • the period is defined as a period in which the voltage Vds1 is higher than the predetermined threshold voltage Vref1.
  • the first charging period is a period during which the drain-source voltage Vds1 of MOSFET Q1 is increasing
  • the second charging period is a period during which the drain-source voltage Vds1 of MOSFET Q1 is decreasing.
  • the threshold voltage Vref1 is set to the total voltage of the target voltage Vcref1 of the capacitor C1 and the forward voltage Vf of the diode D.
  • the drain-source voltage Vds1 of MOSFETQ1 When capacitor C1 is charged during a period when the drain-source voltage Vds1 of MOSFETQ1 is large, the drain-source voltage Vds2 of MOSFETQ2 on the path also becomes large, and the loss (Vds2 ⁇ Ic) generated in MOSFETQ2 also becomes large. Put it away. Therefore, in the rectifier circuit 2 of the first embodiment, the period in which the drain-source voltage Vds1 of the MOSFET Q1 is higher than the predetermined threshold voltage Vref1 is set as a charging stop period, thereby suppressing the occurrence of loss and increasing the charging efficiency. Furthermore, since the second charging period is a period in which the drain-source voltage Vds1 of MOSFET Q1 is decreasing, the period until the next first charging period can be shortened, reducing the required capacity of the capacitor C1. It is highly effective.
  • MOSFETQ2 has a gate terminal that is a control terminal, a drain terminal that is one main terminal, and a source terminal that is the other main terminal.
  • MOSFETQ2 is a switching element for controlling voltage Vc1 of capacitor C1, and its drain terminal is connected to the drain terminal of MOSFETQ1, its source terminal is connected to capacitor C1 via diode D, and its gate terminal is connected to control circuit CTR. It is connected.
  • the cathode of the body diode DQ2 is connected to the drain terminal of MOSFET Q2, and the anode is connected to the source terminal of MOSFET Q2.
  • the diode D has an anode connected to the source terminal of the MOSFET Q2, and a cathode connected to the positive terminal of the capacitor C1.
  • the positive terminal of the capacitor C1 is connected to the cathode of the diode D, and the negative terminal is connected to the source terminal of the MOSFET Q1.
  • the drive circuit 1 includes a comparator Co1 to which power is supplied from a capacitor C1 and detects the voltage between the source terminal of MOSFETQ2 and the source terminal of MOSFETQ1, an input terminal connected to the output terminal of the comparator Co1, and an output terminal connected to the MOSFETQ1.
  • the MOSFET Q1 is connected to the gate terminal of the MOSFET Q1, is supplied with power from the capacitor C1, and has a gate driver GD1 that controls the MOSFET Q1 based on the output signal of the comparator Co1.
  • the control circuit CTR inputs a signal for controlling MOSFETQ2 to the control terminal of MOSFETQ2. Then, the control circuit CTR controls the MOSFET Q2 to be in the ON state during a period in which the drain-source voltage Vds1 of the MOSFET Q1 is less than or equal to the total voltage (threshold voltage Vref1) of the target voltage Vcref1 of the capacitor C1 and the forward voltage Vf of the diode D.
  • MOSFET Q2 is controlled to be in the off state, so that the voltage Vds1 between the drain and source of MOSFET Q1 is Controls the flowing charging current Ic.
  • the target voltage Vcref1 of the capacitor C1 is set to be sufficiently larger than the gate threshold voltage Vgth1 of the MOSFET Q1 so that the drive circuit 1 can drive the MOSFET Q1. Further, the target voltage Vcref1 of the capacitor C1 is set to be less than or equal to the minimum of the maximum rated voltage of the comparator Co1, the maximum rated voltage of the gate driver GD1, and the maximum rated voltage of the gate-source voltage Vgs1 of the MOSFET Q1. ing. This can prevent the drive circuit 1 and MOSFET Q1 from being destroyed.
  • control circuit CTR may have a configuration including a differentiation circuit for determining the timing to control MOSFETQ2.
  • the charging timing can be determined based on the slope of the drain-source voltage Vds1 of MOSFETQ1.
  • the slope of the drain-source voltage Vds1 of the MOSFET Q1 is not limited to a predetermined range, for example, a predetermined range corresponding to the slope from time t0 to time t2 or from time t1 to time t2, and from time t3 to time t5.
  • MOSFETQ2 may also be controlled by
  • the magnitude of the drain-source voltage Vds1 of MOSFETQ1 is detected, and its slope is also detected by a differential circuit, and the drain-source voltage Vds1 of MOSFETQ1 is equal to or lower than the threshold voltage Vref1, and
  • the capacitor C1 may be controlled to be charged when the slope is within a predetermined slope range that is not too steep. For example, if the drain-source voltage Vds1 of the MOSFET Q1 is not a clean sine wave but contains noise, it may drop below the threshold voltage Vref1 for a moment, but return to the original level immediately. In such a case, if the slope is not taken into account, MOSFET Q2 will turn off immediately after being turned on, resulting in a loss. In this case, since the slope is steeper than usual, malfunctions due to noise can be prevented by detecting the slope with a differential circuit and using it for control.
  • the period from time t0 to time t1 is a non-rectification period, and MOSFET Q1 is off. Furthermore, as the sinusoidal voltage input to the bridge circuit increases, the drain-source voltage Vds1 of MOSFET Q1 increases. Furthermore, during this period, since the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the threshold voltage Vref1, the control circuit CTR turns on the MOSFET Q2. At this time, the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the voltage Vc1 of the capacitor C1, but the diode D prevents current from flowing backward from the positive terminal of the capacitor C1 to the drain terminal of the MOSFET Q1.
  • the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR continues to control MOSFET Q2 to turn on. Further, the drain-source voltage Vds1 of the MOSFET Q1 is larger than the sum of the voltage Vc1 of the capacitor C1 and the forward voltage Vf of the diode D. As a result, charging of the capacitor C1 is started, and the voltage Vc1 of the capacitor C1 increases. The charging current Ic of the capacitor C1 flows through a path including the drain terminal of the MOSFET Q1, the MOSFET Q2, the diode D, the capacitor C1, and the source terminal of the MOSFET Q1.
  • the drain-source voltage Vds1 of MOSFET Q1 is equal to the threshold voltage Vref1.
  • the drain-source voltage Vds1 of MOSFET Q1 is higher than the threshold voltage Vref1, so the control circuit CTR controls MOSFET Q2 to turn off, making it a charging stop period.
  • the charging current Ic of the capacitor C1 is cut off.
  • the power accumulated in the capacitor C1 is consumed as standby power for the drive circuit 1, but since the capacitor C1 is not charged, the voltage Vc1 of the capacitor decreases.
  • the sine wave voltage input to the bridge circuit increases in the first half and decreases in the second half.
  • the drain-source voltage Vds1 of MOSFET Q1 also increases in the first half, and begins to decrease in the second half.
  • the drain-source voltage Vds1 of MOSFET Q1 is equal to the threshold voltage Vref1.
  • the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR turns on MOSFET Q2.
  • the voltage Vc1 of the capacitor C1 decreases, so the drain-source voltage Vds1 of the MOSFET Q1 is greater than the sum of the voltage Vc1 of the capacitor C1 and the forward voltage Vf of the diode D. .
  • the charging current Ic of the capacitor C1 flows through the path of the drain terminal of the MOSFET Q1, the MOSFET Q2, the diode D, the capacitor C1, and the source terminal of the MOSFET Q1, and the voltage Vc1 of the capacitor C1 increases.
  • the difference from the conventional example shown in FIG. 9 is that the capacitor C1 is charged even during this period.
  • Time t4 is when the voltage of MOSFET Q1 becomes equal to the sum of voltage Vc1 of capacitor C1 and forward voltage Vf of diode D.
  • the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR continues to control MOSFET Q2 to turn on. At this time, diode D prevents electric charge from flowing out from the positive terminal of capacitor C1 to the drain terminal of MOSFET Q1.
  • the comparator Co1 of the drive circuit 1 detects the drain-source voltage Vds1 of the MOSFETQ1 from the source terminal of the MOSFETQ2 and the source terminal of the MOSFETQ1. Based on the detected voltage, the drive circuit 1 turns on and turns off the MOSFET Q1.
  • the rectified current flowing from the anode A to the cathode K first flows through the body diode DQ1 of the MOSFET Q1. Due to the voltage drop across the body diode DQ1, the drain-source voltage Vds1 of the MOSFET Q1 takes a negative value.
  • comparator Co1 When the voltage detected by comparator Co1 becomes smaller than the first threshold voltage of comparator Co1, comparator Co1 outputs an on signal, and gate driver GD1 pulls up the gate-source voltage Vgs1 of MOSFET Q1 to the voltage Vc1 of capacitor C1. By doing so, MOSFET Q1 is turned on.
  • the drain-source voltage Vds1 of MOSFETQ1 becomes a voltage determined by the rectified current and the on-resistance of MOSFETQ1.
  • the rectified current decreases.
  • the drain-source voltage Vds1 of MOSFET Q1 increases.
  • the comparator Co1 outputs an off signal, and the gate driver GD1 pulls down the gate-source voltage Vgs1 of MOSFET Q1 to 0V. Then, MOSFETQ1 is turned off.
  • the first threshold voltage and the second threshold voltage of the comparator Co1 may be the same value, or the first threshold voltage may be smaller than the second threshold voltage.
  • the first threshold voltage is lower than the second threshold voltage, it is possible to suppress chattering in which the MOSFET repeatedly turns on and off in short cycles.
  • the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR continues to control MOSFET Q2 to turn on.
  • the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the sum of the voltage Vc1 of the capacitor C1 and the forward voltage Vf of the diode D, the capacitor C1 is not charged.
  • the diode D prevents current from flowing backward from the positive terminal of the capacitor C1 to the drain terminal of the MOSFET Q1.
  • the voltage Vc1 of the capacitor C1 decreases because the power stored in the capacitor C1 is used for the power consumption of the drive circuit 1 and for generating the gate-source voltage Vgs1 of the MOSFET Q1.
  • the rectifier circuit 2 of the first embodiment realizes synchronous rectification.
  • the voltage Vc1 of the capacitor C1 decreases. It is necessary to select the capacitance of the capacitor C1 so that the minimum value of the voltage Vc1 of the capacitor C1 in any period is equal to or higher than the voltage lower limit value Vcref2 of the capacitor C1.
  • the voltage lower limit value Vcref2 of the capacitor C1 is, for example, a value larger than the lowest operating voltage of the drive circuit 1 and larger than the gate threshold voltage Vgth1 of the MOSFET Q1 such that the on-resistance of the MOSFET Q1 becomes sufficiently small.
  • the required capacity of the capacitor C1 can be reduced, and as a result, the volume of the capacitor C1 can be reduced, realizing miniaturization and cost reduction of the rectifier circuit 2 and the power supply. can.
  • FIG. 3 is a circuit diagram of the rectifier circuit of Example 2.
  • Example 2 is a modification of Example 1.
  • the second embodiment differs from the first embodiment in that it shows an example of a specific configuration of the control circuit CTR, and the other configurations and effects are basically the same as the first embodiment. Therefore, in the second embodiment, differences from the first embodiment will be mainly explained, and explanations that overlap with the first embodiment will be omitted.
  • the control circuit CTR of the rectifier circuit 2 of the second embodiment includes a resistor R1 and a resistor R2 that divide the drain-source voltage Vds1 of the MOSFET Q1, and a comparator Co2 that is supplied with power from the capacitor C1 and detects the voltage of the resistor R2. It has a gate driver GD2 whose input terminal is connected to the output terminal of the comparator Co2, whose output terminal is connected to the gate terminal of the MOSFET Q2, to which power is supplied from the capacitor C1, and which controls the MOSFET Q2 based on the output signal of the comparator Co2.
  • the resistor R1 and the resistor R2 are set so that the voltage of the resistor R2 is equal to or lower than the rated voltage of the comparator Co2.
  • Comparator Co2 compares the detected voltage of resistor R2 with threshold voltage Vref2 and outputs a signal to gate driver GD2.
  • the threshold voltage Vref2 is selected so that when the drain-source voltage Vds1 of the MOSFET Q1 becomes equal to the threshold voltage Vref1, the voltage of the resistor R2 becomes equal to the threshold voltage Vref2.
  • FIG. 4 is a circuit diagram of the rectifier circuit of Example 3.
  • Example 3 is a modification of Example 1.
  • the third embodiment differs from the first embodiment in that it includes a resistor R3, and the other configurations and effects are basically the same as the first embodiment. Therefore, in the third embodiment, differences from the first embodiment will be mainly explained, and explanations that overlap with the first embodiment will be omitted. Note that the third embodiment may be applied to the second embodiment.
  • the rectifier circuit 2 of Example 3 has a resistor R3 with one terminal connected to the drain terminal of MOSFET Q1 and the other terminal connected to the drain terminal of MOSFET Q2.
  • the resistor R3 is inserted between the drain terminal of MOSFETQ1 and the drain terminal of MOSFETQ2.
  • the charging current Ic of the capacitor C1 flows through the path of the drain terminal of the MOSFET Q1, the MOSFET Q2, the diode D, the capacitor C1, and the source terminal of the MOSFET Q1.
  • the charging current Ic increases sharply.
  • the efficiency of the rectifier circuit 2 may decrease due to an increase in loss in the path of the charging current Ic, and the temperature of the MOSFET Q2 and the diode D may rise beyond their ratings.
  • a steep increase in the charging current Ic of the capacitor C1 can be suppressed by inserting the resistor R3 in series on the path of the charging current Ic. That is, the resistor R3 functions as an inrush current prevention resistor. Thereby, it is possible to suppress a decrease in efficiency of the rectifier circuit 2 due to an increase in loss in the path of the charging current Ic and a rise in temperature of the MOSFET Q2 and the diode D.
  • FIG. 5 is a circuit diagram of the rectifier circuit of Example 4.
  • Example 4 is a modified example of Example 3.
  • Example 4 differs from Example 3 in that it has a capacitor C2, but other configurations and effects are basically the same as Example 3. Therefore, in Example 4, the differences from Example 3 will be mainly described, and descriptions that overlap with Example 3 will be omitted. Note that Example 4 may be applied to Examples 1 and 2.
  • the rectifier circuit 2 of Example 4 has a capacitor C2 whose positive terminal is connected to the source terminal of MOSFETQ2 and whose negative terminal is connected to the source terminal of MOSFETQ1.
  • the comparator Co1 may malfunction due to high frequency noise contained in the voltage detected by the comparator Co1.
  • MOSFET Q1 may turn off during the rectification period, and the loss reduction effect of synchronous rectification may be impaired.
  • the rectifier circuit 2 of the fourth embodiment high-frequency noise contained in the voltage detected by the comparator Co1 can be suppressed by configuring a low-pass filter with the on-resistance of the MOSFET Q2, the resistor R3, and the capacitor C2. Note that even if the resistor R3 is not inserted, the on-resistance of the MOSFET Q2 and the capacitor C2 constitute a low-pass filter, so it is possible to similarly suppress high-frequency noise contained in the voltage detected by the comparator Co1. Thereby, malfunction of the comparator Co1 and unintended turn-on and turn-off of the MOSFET Q1 can be suppressed, and the loss reduction effect of synchronous rectification is not impaired.
  • FIG. 6 is a diagram showing an example of the configuration of the rectifier circuit of Example 5.
  • FIG. 7 is a diagram showing another example of the configuration of the rectifier circuit according to the fifth embodiment.
  • Example 5 is a modification of Example 1.
  • the fifth embodiment differs from the first embodiment in that the rectifier circuit 2 is built into the semiconductor package, and the other configurations and effects are basically the same as the first embodiment. Therefore, in the fifth embodiment, differences from the first embodiment will be mainly explained, and explanations that overlap with the first embodiment will be omitted. Note that although FIGS. 6 and 7 of Example 5 are explained using an example applied to FIG. May be applied.
  • FIG. 6 shows a configuration in which the rectifier circuit 2 is built into the semiconductor package 3.
  • the semiconductor package 3 has a cathode K and an anode A as external terminals.
  • FIG. 7 shows a configuration in which a plurality of rectifier circuits 2, such as a bridge circuit configured using four rectifier circuits 2, are built into one semiconductor package 4.
  • the semiconductor package 4 has terminals T1 to T4 as external terminals.
  • Example 5 when designing and manufacturing a product that uses a rectifier circuit, it is sufficient to purchase and incorporate a rectifier circuit with a built-in drive circuit and capacitor as in this example, and the design of the drive circuit and capacitor is simple. This has the effect of reducing the overall design and implementation man-hours.
  • FIG. 8 is a circuit diagram of the power supply of Example 6.
  • Example 6 is an example of a power supply to which the rectifier circuit 2 described in Examples 1 to 5 is applied.
  • the scope of application of the rectifier circuits 2 of Examples 1 to 5 is all rectifier circuits used in power supplies.
  • the rectifier circuits of Embodiments 1 to 5 are used as commercial rectifier diodes CRD1 to CRD4, free-wheeling diodes FWD, secondary rectifier diodes SSD1 to SSD2, and backflow prevention diodes BPD. 2 is applicable.

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Abstract

The present invention provides a rectifier circuit which uses a rectifying switching element and which can reduce the required capacitance of a capacitor that supplies power to a drive circuit for driving the rectifying switching element. A rectifier circuit 2 having an anode A and a cathode K comprises: a rectifying switching element (MOSFETQ1); a diode (body diode DQ1); a drive circuit 1 that drives the rectifying switching element (MOSFETQ1); and a capacitor C1 that supplies power to the drive circuit 1, wherein during the period from when the rectifying switching element (MOSFETQ1) turns off until the rectifying switching element (MOSFETQ1) subsequently turns on, the capacitor C1 has a first charging period and a second charging period in which the capacitor C1 is charged, and a charging stop period which is provided between the first charging period and the second charging period and in which charging of the capacitor C1 is stopped.

Description

整流回路およびそれを用いた電源Rectifier circuit and power supply using it
 本発明は、整流回路およびそれを用いた電源に関する。 The present invention relates to a rectifier circuit and a power supply using the same.
 交流を直流に整流する整流回路としては、ダイオードを用いたものや、ダイオードに代えてMOSFET等のスイッチング素子を用いて同期整流を行うものが知られている。 As rectifier circuits that rectify alternating current into direct current, there are known ones that use diodes and ones that perform synchronous rectification using switching elements such as MOSFETs instead of diodes.
 ダイオードを用いた整流の場合は、ダイオードの内蔵ポテンシャルによる電圧降下があるため、損失が大きいという問題がある。これに対し、例えばMOSFETを用いた同期整流は、MOSFETの内蔵ポテンシャルがなく0Vから順方向電流が立ち上がるため、損失が低いという利点がある。したがって、特に、フロントエンド電源等の効率規制の厳しいスイッチング電源において、より低損失に整流するために、主にMOSFETを用いた同期整流が用いられている。 In the case of rectification using diodes, there is a voltage drop due to the built-in potential of the diodes, so there is a problem of large losses. On the other hand, synchronous rectification using a MOSFET, for example, has the advantage of low loss because there is no built-in potential of the MOSFET and the forward current rises from 0V. Therefore, especially in switching power supplies such as front-end power supplies that have strict efficiency regulations, synchronous rectification using MOSFETs is mainly used to achieve lower loss.
 同期整流を実現する整流回路としては、例えば、特許文献1や特許文献2などがある。 Examples of rectifier circuits that realize synchronous rectification include Patent Document 1 and Patent Document 2.
 同期整流を行う整流回路は、一般的に、同期整流用の第1のスイッチング素子であるMOSFETと、その駆動回路と、駆動回路に電力を供給するコンデンサと、コンデンサの電圧を制御するための第2のスイッチング素子と、第2のスイッチング素子の制御回路とを有している。駆動回路は、あらかじめ定められた閾値電圧と、検出したMOSFETのドレイン-ソース間電圧とに基づき、MOSFETのオンオフを制御する。 A rectifier circuit that performs synchronous rectification generally includes a MOSFET that is a first switching element for synchronous rectification, a drive circuit for the MOSFET, a capacitor that supplies power to the drive circuit, and a MOSFET that controls the voltage of the capacitor. It has two switching elements and a control circuit for the second switching element. The drive circuit controls on/off of the MOSFET based on a predetermined threshold voltage and the detected drain-source voltage of the MOSFET.
 図9は、従来の整流回路の動作波形を示す図である。図9において、縦軸は電圧または電流、横軸は時刻tを示している。 FIG. 9 is a diagram showing operating waveforms of a conventional rectifier circuit. In FIG. 9, the vertical axis represents voltage or current, and the horizontal axis represents time t.
 駆動回路に電力を供給するコンデンサは、時刻t0でMOSFETのゲート-ソース間電圧Vgs1が0になってMOSFETがターンオフした後、時刻t1から時刻t2の間に、MOSFETのドレイン端子、第2のスイッチング素子、コンデンサ、MOSFETのソース端子の経路で流れる電流で充電される。コンデンサの充電が開始されると、MOSFETのドレイン-ソース間電圧Vds1に追従するようにコンデンサの電圧Vc1は増加する。 The capacitor that supplies power to the drive circuit connects the drain terminal of the MOSFET to the second switching terminal between time t1 and time t2 after the gate-source voltage Vgs1 of the MOSFET becomes 0 at time t0 and the MOSFET is turned off. It is charged by the current flowing through the source terminal of the element, capacitor, and MOSFET. When charging of the capacitor starts, the voltage Vc1 of the capacitor increases to follow the drain-source voltage Vds1 of the MOSFET.
 この整流回路では、コンデンサの電圧Vc1が時刻t2で目標電圧Vcref1まで達した後、MOSFETのドレイン端子とコンデンサの正極端子との間に挿入された第2のスイッチング素子をターンオフすることで、コンデンサの充電電流Icを遮断する。これにより、コンデンサの電圧Vc1は目標電圧Vcref1以下になるように制御される。 In this rectifier circuit, after the voltage Vc1 of the capacitor reaches the target voltage Vcref1 at time t2, the second switching element inserted between the drain terminal of the MOSFET and the positive terminal of the capacitor is turned off. Cut off the charging current Ic. Thereby, the capacitor voltage Vc1 is controlled to be equal to or lower than the target voltage Vcref1.
特開2001-251861号公報Japanese Patent Application Publication No. 2001-251861 米国特許第10756645号明細書US Patent No. 10756645
 ここで、従来の整流回路では、図9に示すように、時刻t2から時刻t5までの間は、コンデンサに蓄積された電力は駆動回路の待機電力で消費されるため、コンデンサの電圧Vc1は減少する。さらにその後、時刻t5から開始するMOSFETのオン期間を経て、次の時刻t0で再びMOSFETがターンオフして時刻t1でコンデンサの充電が開始されるまで、コンデンサに蓄積された電力は、駆動回路の消費電力、または、MOSFETのゲート-ソース間電圧の生成に使用されるため、コンデンサの電圧は減少し続ける。 Here, in the conventional rectifier circuit, as shown in FIG. 9, from time t2 to time t5, the power accumulated in the capacitor is consumed by the standby power of the drive circuit, so the voltage Vc1 of the capacitor decreases. do. After that, after the MOSFET is turned on starting from time t5, the MOSFET is turned off again at the next time t0 and the capacitor starts charging at time t1.The power accumulated in the capacitor is then consumed by the drive circuit. The voltage on the capacitor continues to decrease as it is used to generate power or the gate-to-source voltage of the MOSFET.
 そのため、時刻t2でコンデンサの充電が完了してから次の時刻t1で再びコンデンサの充電が開始されるまでの期間において、コンデンサの電圧Vc1が、例えば、駆動回路の動作保証電圧、もしくは、MOSFETのゲート閾値電圧以上になるように、コンデンサの電圧下限値Vcref2を設定し、これを満たすようコンデンサの容量を選定する必要がある。 Therefore, during the period from when charging of the capacitor is completed at time t2 until charging of the capacitor starts again at the next time t1, the voltage Vc1 of the capacitor is, for example, the guaranteed operation voltage of the drive circuit or the voltage of the MOSFET. It is necessary to set the voltage lower limit value Vcref2 of the capacitor so that it is equal to or higher than the gate threshold voltage, and to select the capacitance of the capacitor so as to satisfy this value.
 しかしながら、従来の整流回路では、上記の通り同期整流用のMOSFETの駆動回路に電力を供給するコンデンサの容量を確保する必要があるため、コンデンサの体積を小さくするのには限界があり、整流回路の小型化、低コスト化の妨げとなっていた。 However, in conventional rectifier circuits, as mentioned above, it is necessary to ensure the capacity of the capacitor that supplies power to the MOSFET drive circuit for synchronous rectification, so there is a limit to reducing the volume of the capacitor, and the rectifier circuit This has been an obstacle to miniaturization and cost reduction.
 本発明が解決しようとする課題は、整流用のスイッチング素子を用いた整流回路において、整流用のスイッチング素子を駆動するための駆動回路に電力を供給するコンデンサの必要容量を削減することができ、これによってコンデンサの体積を削減して小型化、低コスト化が可能な整流回路およびそれを用いた電源を提供することである。 The problem to be solved by the present invention is that in a rectifier circuit using a switching element for rectification, it is possible to reduce the required capacity of a capacitor that supplies power to a drive circuit for driving the switching element for rectification. The object of the present invention is to provide a rectifier circuit that can be made smaller and lower in cost by reducing the volume of a capacitor, and a power supply using the rectifier circuit.
 上記課題を解決するために、本発明の整流回路は、例えば、アノードとカソードとを有する整流回路において、第1の端子が前記整流回路の前記カソードに接続され、第2の端子が前記整流回路の前記アノードに接続された第1のスイッチング素子と、カソードが前記第1の端子に接続され、アノードが前記第2の端子に接続された第1のダイオードと、前記第1のスイッチング素子を駆動する駆動回路と、前記駆動回路に電力を供給する第1のコンデンサと、を備え、前記第1のコンデンサは、前記第1のスイッチング素子がオフしてから次にオンするまでの期間に、前記第1のコンデンサが充電される第1の充電期間および第2の充電期間と、前記第1の充電期間と前記第2の充電期間との間に設けられ前記第1のコンデンサへの充電が停止される充電停止期間とを有することを特徴とする。 In order to solve the above problems, a rectifier circuit of the present invention includes, for example, a rectifier circuit having an anode and a cathode, in which a first terminal is connected to the cathode of the rectifier circuit, and a second terminal is connected to the rectifier circuit. a first switching element connected to the anode of the first switching element; a first diode having a cathode connected to the first terminal and an anode connected to the second terminal; and driving the first switching element. a drive circuit that supplies power to the drive circuit; and a first capacitor that supplies power to the drive circuit; A first charging period and a second charging period in which the first capacitor is charged, and a charging period provided between the first charging period and the second charging period, in which charging of the first capacitor is stopped. The battery is characterized by having a charging stop period.
 また、本発明の電源は、例えば、上記整流回路を有することを特徴とする。 Furthermore, the power supply of the present invention is characterized in that it includes, for example, the above-mentioned rectifier circuit.
 本発明の整流回路および電源によれば、第1の充電期間と第2の充電期間の2回に分けてコンデンサを充電し、第1の充電期間の後の充電停止期間に放電された分の少なくとも一部を第2の充電期間で補うことができるので、コンデンサの必要容量を削減でき、その結果、コンデンサの体積を削減して整流回路および電源の小型化、低コスト化を実現できる。 According to the rectifier circuit and power supply of the present invention, the capacitor is charged in two times, the first charging period and the second charging period, and the amount of the capacitor discharged during the charging stop period after the first charging period is Since at least a portion of the charge can be compensated for in the second charging period, the required capacitance of the capacitor can be reduced, and as a result, the volume of the capacitor can be reduced, making it possible to realize miniaturization and cost reduction of the rectifier circuit and power supply.
実施例1の整流回路の回路図。FIG. 3 is a circuit diagram of a rectifier circuit of Example 1. 実施例1の整流回路の動作波形を示す図。3 is a diagram showing operating waveforms of the rectifier circuit of Example 1. FIG. 実施例2の整流回路の回路図。FIG. 2 is a circuit diagram of a rectifier circuit according to a second embodiment. 実施例3の整流回路の回路図。FIG. 3 is a circuit diagram of a rectifier circuit according to a third embodiment. 実施例4の整流回路の回路図。FIG. 4 is a circuit diagram of a rectifier circuit according to a fourth embodiment. 実施例5の整流回路の構成の一例を示す図。FIG. 7 is a diagram showing an example of a configuration of a rectifier circuit according to a fifth embodiment. 実施例5の整流回路の構成の他の例を示す図。7 is a diagram showing another example of the configuration of the rectifier circuit of Example 5. FIG. 実施例6の電源の回路図。FIG. 7 is a circuit diagram of a power supply according to a sixth embodiment. 従来の整流回路の動作波形を示す図。The figure which shows the operating waveform of the conventional rectifier circuit.
 以下、図面を用いて本発明の実施例を説明する。各図、各実施例において、同一または類似の構成要素については同じ符号を付け、重複する説明は省略する。 Embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and overlapping explanations will be omitted.
 はじめに、実施例1の基本原理について説明する。 First, the basic principle of Example 1 will be explained.
 図1は、実施例1の整流回路の回路図である。 FIG. 1 is a circuit diagram of the rectifier circuit of Example 1.
 図1に示すように、実施例1の整流回路2は、アノードAと、カソードKと、整流用の第1のスイッチング素子であるMOSFETQ1と、MOSFETQ1のボディダイオードDQ1と、MOSFETQ1を駆動する駆動回路1と、駆動回路1に電力を供給するコンデンサC1とを有する。さらに、実施例1の整流回路2は、コンデンサC1の電圧Vc1を制御するための第2のスイッチング素子であるMOSFETQ2と、MOSFETQ2のボディダイオードDQ2と、MOSFETQ2を制御する制御回路CTRと、ダイオードDとを有する。駆動回路1は、コンパレータCo1と、ゲートドライバGD1とを有する。 As shown in FIG. 1, the rectifier circuit 2 of the first embodiment includes an anode A, a cathode K, a MOSFET Q1 which is a first switching element for rectification, a body diode DQ1 of the MOSFET Q1, and a drive circuit that drives the MOSFET Q1. 1 and a capacitor C1 that supplies power to the drive circuit 1. Furthermore, the rectifier circuit 2 of the first embodiment includes a second switching element MOSFETQ2 for controlling the voltage Vc1 of the capacitor C1, a body diode DQ2 of the MOSFETQ2, a control circuit CTR for controlling the MOSFETQ2, and a diode D. has. The drive circuit 1 includes a comparator Co1 and a gate driver GD1.
 図1では、MOSFETQ1としてnチャネルのエンハンスメント型MOSFETを用い、MOSFETQ2としてnチャネルのデプレッション型MOSFETを用いて表記しているが、これに限られず、他のスイッチング素子を用いてもよい。また、ボディダイオードDQ1とボディダイオードDQ2についても、MOSFETに内蔵されたボディダイオードに限られず、例えば外付けのダイオードなど、他のダイオードを用いてもよい。 In FIG. 1, an n-channel enhancement type MOSFET is used as the MOSFET Q1, and an n-channel depletion type MOSFET is used as the MOSFET Q2, but the present invention is not limited to this, and other switching elements may be used. Further, the body diode DQ1 and the body diode DQ2 are not limited to body diodes built into the MOSFET, and other diodes such as external diodes may be used.
 MOSFETQ1は、制御端子であるゲート端子と、一方の主端子であるドレイン端子と、他方の主端子であるソース端子とを有している。MOSFETQ1は、整流用のスイッチング素子であり、ドレイン端子が整流回路2のカソードKに接続され、ソース端子が整流回路2のアノードAに接続され、ゲート端子が駆動回路1に接続されている。 MOSFET Q1 has a gate terminal that is a control terminal, a drain terminal that is one main terminal, and a source terminal that is the other main terminal. MOSFET Q1 is a switching element for rectification, and has a drain terminal connected to the cathode K of the rectifier circuit 2, a source terminal connected to the anode A of the rectifier circuit 2, and a gate terminal connected to the drive circuit 1.
 ボディダイオードDQ1は、カソードがMOSFETQ1のドレイン端子に接続され、アノードがMOSFETQ1のソース端子に接続されている。 The body diode DQ1 has a cathode connected to the drain terminal of MOSFETQ1, and an anode connected to the source terminal of MOSFETQ1.
 図2は、実施例1の整流回路の動作波形を示す図である。 FIG. 2 is a diagram showing operating waveforms of the rectifier circuit of Example 1.
 図2は、図9に対応する図であり、図1に示した整流回路2を4個使用して構成したブリッジ回路に抵抗負荷を接続し、正弦波電圧を入力した場合の動作波形である。図2において、縦軸は、MOSFETQ1のドレイン-ソース間電圧Vds1、MOSFETQ1のゲート-ソース間電圧Vgs1、コンデンサC1の充電電流Ic、コンデンサC1の電圧Vc1を示しており、横軸は時刻tを示している。また、Vgth1は、MOSFETQ1のゲート閾値電圧である。なお、MOSFETQ2のドレイン-ソース間電圧Vds2、MOSFETQ2のゲート-ソース間電圧Vgs2、MOSFETQ2のゲート閾値電圧Vgth2については図示および詳細な説明を省略する。 FIG. 2 is a diagram corresponding to FIG. 9, and shows operating waveforms when a resistive load is connected to a bridge circuit configured using four rectifier circuits 2 shown in FIG. 1 and a sine wave voltage is input. . In FIG. 2, the vertical axis indicates the drain-source voltage Vds1 of MOSFET Q1, the gate-source voltage Vgs1 of MOSFET Q1, the charging current Ic of capacitor C1, and the voltage Vc1 of capacitor C1, and the horizontal axis indicates time t. ing. Further, Vgth1 is the gate threshold voltage of MOSFETQ1. Note that illustration and detailed description of the drain-source voltage Vds2 of MOSFETQ2, the gate-source voltage Vgs2 of MOSFETQ2, and the gate threshold voltage Vgth2 of MOSFETQ2 are omitted.
 図2に示すように、実施例1の整流回路2では、駆動回路1に電力を供給するコンデンサC1は、MOSFETQ1が時刻t0でオフしてから次に時刻t5でオンするまでの期間に、第1のコンデンサC1が充電される第1の充電期間(時刻t1から時刻t2)および第2の充電期間(時刻t3から時刻t4)と、第1の充電期間と第2の充電期間との間に設けられコンデンサC1への充電が停止される充電停止期間(時刻t2から時刻t3)とを有する点で、従来の図9の動作波形と異なっている。 As shown in FIG. 2, in the rectifier circuit 2 of the first embodiment, the capacitor C1 that supplies power to the drive circuit 1 is connected to the Between the first charging period (from time t1 to time t2) and the second charging period (from time t3 to time t4) during which capacitor C1 of No. 1 is charged, and between the first charging period and the second charging period. This differs from the conventional operating waveform shown in FIG. 9 in that it has a charging stop period (from time t2 to time t3) in which charging of the capacitor C1 is stopped.
 従来の図9では、コンデンサの充電期間は時刻t1から時刻t2の1回のみであり、その後、次の充電期間である時刻t1までコンデンサの電圧Vc1を電圧下限値Vcref2以上に維持できるようにコンデンサの容量を選定する必要がある。これに対して、実施例1の整流回路2によれば、第1の充電期間と第2の充電期間の2回に分けてコンデンサC1を充電し、第1の充電期間の後の充電停止期間に放電された分の少なくとも一部を第2の充電期間で補うことができるので、コンデンサC1の必要容量を削減でき、その結果、コンデンサC1の体積を削減して整流回路2およびそれを用いた電源の小型化、低コスト化を実現できる。また、MOSFETのオフ期間における消費電力が大きい駆動回路や制御ICを使用可能となる。 In the conventional case shown in FIG. 9, the capacitor is charged only once from time t1 to time t2, and thereafter, the capacitor is charged so that the capacitor voltage Vc1 can be maintained at a voltage lower limit value Vcref2 or higher until the next charging period, time t1. It is necessary to select the capacity of On the other hand, according to the rectifier circuit 2 of the first embodiment, the capacitor C1 is charged in two times, the first charging period and the second charging period, and the charging stop period is performed after the first charging period. Since at least a part of the discharged amount can be compensated for in the second charging period, the required capacity of the capacitor C1 can be reduced, and as a result, the volume of the capacitor C1 can be reduced and the rectifier circuit 2 and the rectifier circuit using it can be reduced. It is possible to realize smaller power supplies and lower costs. Further, it becomes possible to use a drive circuit and a control IC that consume a large amount of power during the off period of the MOSFET.
 図2では、一例として、第1の充電期間および第2の充電期間は、MOSFETQ1のドレイン-ソース間電圧Vds1が所定の閾値電圧Vref1以下の期間であり、充電停止期間は、MOSFETQ1のドレイン-ソース間電圧Vds1が所定の閾値電圧Vref1より大きい期間とした。これによって、第1の充電期間は、MOSFETQ1のドレイン-ソース間電圧Vds1が増加中の期間であり、第2の充電期間は、MOSFETQ1のドレイン-ソース間電圧Vds1が減少中の期間となる。図2では、閾値電圧Vref1は、コンデンサC1の目標電圧Vcref1とダイオードDの順方向電圧Vfとの合計電圧に設定されている。 In FIG. 2, as an example, the first charging period and the second charging period are periods in which the drain-source voltage Vds1 of MOSFET Q1 is equal to or lower than a predetermined threshold voltage Vref1, and the charging stop period is a period between the drain-source of MOSFET Q1. The period is defined as a period in which the voltage Vds1 is higher than the predetermined threshold voltage Vref1. As a result, the first charging period is a period during which the drain-source voltage Vds1 of MOSFET Q1 is increasing, and the second charging period is a period during which the drain-source voltage Vds1 of MOSFET Q1 is decreasing. In FIG. 2, the threshold voltage Vref1 is set to the total voltage of the target voltage Vcref1 of the capacitor C1 and the forward voltage Vf of the diode D.
 MOSFETQ1のドレイン-ソース間電圧Vds1が大きい期間にコンデンサC1を充電すると、その途中の経路にあるMOSFETQ2のドレイン-ソース間電圧Vds2も大きくなり、MOSFETQ2で発生する損失(Vds2×Ic)も大きくなってしまう。そこで、実施例1の整流回路2では、MOSFETQ1のドレイン-ソース間電圧Vds1が所定の閾値電圧Vref1より大きい期間では充電停止期間とすることで損失の発生を抑制し、充電効率を高めている。さらに、第2の充電期間は、MOSFETQ1のドレイン-ソース間電圧Vds1が減少中の期間であるため、次の第1の充電期間までの期間を短くすることができ、コンデンサC1の必要容量を削減できる効果が高い。 When capacitor C1 is charged during a period when the drain-source voltage Vds1 of MOSFETQ1 is large, the drain-source voltage Vds2 of MOSFETQ2 on the path also becomes large, and the loss (Vds2×Ic) generated in MOSFETQ2 also becomes large. Put it away. Therefore, in the rectifier circuit 2 of the first embodiment, the period in which the drain-source voltage Vds1 of the MOSFET Q1 is higher than the predetermined threshold voltage Vref1 is set as a charging stop period, thereby suppressing the occurrence of loss and increasing the charging efficiency. Furthermore, since the second charging period is a period in which the drain-source voltage Vds1 of MOSFET Q1 is decreasing, the period until the next first charging period can be shortened, reducing the required capacity of the capacitor C1. It is highly effective.
 次に、図1および図2を用いて、実施例1の詳細な構成と動作について説明する。 Next, the detailed configuration and operation of the first embodiment will be described using FIGS. 1 and 2.
 MOSFETQ2は、制御端子であるゲート端子と、一方の主端子であるドレイン端子と、他方の主端子であるソース端子とを有している。MOSFETQ2は、コンデンサC1の電圧Vc1を制御するためのスイッチング素子であり、ドレイン端子がMOSFETQ1のドレイン端子に接続され、ソース端子がダイオードDを介してコンデンサC1に接続され、ゲート端子が制御回路CTRに接続されている。 MOSFETQ2 has a gate terminal that is a control terminal, a drain terminal that is one main terminal, and a source terminal that is the other main terminal. MOSFETQ2 is a switching element for controlling voltage Vc1 of capacitor C1, and its drain terminal is connected to the drain terminal of MOSFETQ1, its source terminal is connected to capacitor C1 via diode D, and its gate terminal is connected to control circuit CTR. It is connected.
 ボディダイオードDQ2は、カソードがMOSFETQ2のドレイン端子に接続され、アノードがMOSFETQ2のソース端子に接続されている。 The cathode of the body diode DQ2 is connected to the drain terminal of MOSFET Q2, and the anode is connected to the source terminal of MOSFET Q2.
 ダイオードDは、アノードがMOSFETQ2のソース端子に接続され、カソードがコンデンサC1の正極端子に接続されている。 The diode D has an anode connected to the source terminal of the MOSFET Q2, and a cathode connected to the positive terminal of the capacitor C1.
 コンデンサC1は、正極端子がダイオードDのカソードに接続され、負極端子がMOSFETQ1のソース端子に接続されている。 The positive terminal of the capacitor C1 is connected to the cathode of the diode D, and the negative terminal is connected to the source terminal of the MOSFET Q1.
 駆動回路1は、電力がコンデンサC1から供給され、MOSFETQ2のソース端子とMOSFETQ1のソース端子との間の電圧を検出するコンパレータCo1と、入力端子がコンパレータCo1の出力端子に接続され、出力端子がMOSFETQ1のゲート端子に接続され、電力がコンデンサC1から供給され、コンパレータCo1の出力信号に基づいてMOSFETQ1を制御するゲートドライバGD1とを有する。 The drive circuit 1 includes a comparator Co1 to which power is supplied from a capacitor C1 and detects the voltage between the source terminal of MOSFETQ2 and the source terminal of MOSFETQ1, an input terminal connected to the output terminal of the comparator Co1, and an output terminal connected to the MOSFETQ1. The MOSFET Q1 is connected to the gate terminal of the MOSFET Q1, is supplied with power from the capacitor C1, and has a gate driver GD1 that controls the MOSFET Q1 based on the output signal of the comparator Co1.
 制御回路CTRは、MOSFETQ2を制御する信号を、MOSFETQ2の制御端子に入力する。そして、制御回路CTRは、MOSFETQ1のドレイン-ソース間電圧Vds1がコンデンサC1の目標電圧Vcref1とダイオードDの順方向電圧Vfとの合計電圧(閾値電圧Vref1)以下の期間ではMOSFETQ2をオン状態に制御し、MOSFETQ1のドレイン-ソース間電圧Vds1がコンデンサC1の目標電圧Vcref1とダイオードDの順方向電圧Vfとの合計電圧(閾値電圧Vref1)より大きい期間ではMOSFETQ2をオフ状態に制御することで、コンデンサC1へ流れる充電電流Icを制御する。 The control circuit CTR inputs a signal for controlling MOSFETQ2 to the control terminal of MOSFETQ2. Then, the control circuit CTR controls the MOSFET Q2 to be in the ON state during a period in which the drain-source voltage Vds1 of the MOSFET Q1 is less than or equal to the total voltage (threshold voltage Vref1) of the target voltage Vcref1 of the capacitor C1 and the forward voltage Vf of the diode D. , during a period in which the drain-source voltage Vds1 of MOSFET Q1 is greater than the total voltage (threshold voltage Vref1) of the target voltage Vcref1 of capacitor C1 and the forward voltage Vf of diode D, MOSFET Q2 is controlled to be in the off state, so that the voltage Vds1 between the drain and source of MOSFET Q1 is Controls the flowing charging current Ic.
 ここで、コンデンサC1の目標電圧Vcref1は、駆動回路1がMOSFETQ1を駆動できるように、MOSFETQ1のゲート閾値電圧Vgth1より十分大きく設定されている。また、コンデンサC1の目標電圧Vcref1は、コンパレータCo1の最大定格電圧、ゲートドライバGD1の最大定格電圧、MOSFETQ1のゲート-ソース間電圧Vgs1の最大定格電圧のうちの最小のもの以下となるように設定されている。これによって、駆動回路1やMOSFETQ1が破壊されるのを防止できる。 Here, the target voltage Vcref1 of the capacitor C1 is set to be sufficiently larger than the gate threshold voltage Vgth1 of the MOSFET Q1 so that the drive circuit 1 can drive the MOSFET Q1. Further, the target voltage Vcref1 of the capacitor C1 is set to be less than or equal to the minimum of the maximum rated voltage of the comparator Co1, the maximum rated voltage of the gate driver GD1, and the maximum rated voltage of the gate-source voltage Vgs1 of the MOSFET Q1. ing. This can prevent the drive circuit 1 and MOSFET Q1 from being destroyed.
 なお、制御回路CTRは、MOSFETQ2を制御するタイミングを決定するための微分回路を有する構成としてもよい。例えば、MOSFETQ1のドレイン-ソース間電圧Vds1の傾きに基づいて充電タイミングを決定することができる。 Note that the control circuit CTR may have a configuration including a differentiation circuit for determining the timing to control MOSFETQ2. For example, the charging timing can be determined based on the slope of the drain-source voltage Vds1 of MOSFETQ1.
 一例としては、図2において、MOSFETQ1のドレイン-ソース間電圧Vds1の傾きが所定の範囲、例えば、時刻t3における傾きよりも大きく、時刻t2における傾きよりも小さい期間を検出することで、MOSFETQ1のドレイン-ソース間電圧Vds1が閾値電圧Vref1より大きい期間(時刻t2から時刻t3)であることを検出でき、これに基づいてMOSFETQ2を制御することができる。なお、これに限られず、MOSFETQ1のドレイン-ソース間電圧Vds1の傾きが所定の範囲、例えば、時刻t0から時刻t2または時刻t1から時刻t2における傾きに相当する所定の範囲と、時刻t3から時刻t5または時刻t3から時刻t4における傾きに相当する所定の範囲との何れかに入っていることを検出することで、第1の充電期間または第2の充電期間であることを検出し、これに基づいてMOSFETQ2を制御してもよい。 As an example, in FIG. 2, by detecting a period in which the slope of the drain-source voltage Vds1 of MOSFET Q1 is larger than the slope at time t3 and smaller than the slope at time t2, the slope of the drain-source voltage Vds1 of MOSFET Q1 is detected. It is possible to detect the period (from time t2 to time t3) in which the source-to-source voltage Vds1 is higher than the threshold voltage Vref1, and based on this, it is possible to control the MOSFET Q2. Note that the slope of the drain-source voltage Vds1 of the MOSFET Q1 is not limited to a predetermined range, for example, a predetermined range corresponding to the slope from time t0 to time t2 or from time t1 to time t2, and from time t3 to time t5. Alternatively, by detecting that the slope falls within a predetermined range corresponding to the slope from time t3 to time t4, it is detected that it is the first charging period or the second charging period, and based on this, the first charging period or the second charging period is detected. MOSFETQ2 may also be controlled by
 また、他の例としては、MOSFETQ1のドレイン-ソース間電圧Vds1の大きさを検出するとともに、微分回路でその傾きも検出し、MOSFETQ1のドレイン-ソース間電圧Vds1が閾値電圧Vref1以下、かつ、その傾きが急峻すぎない所定の傾きの範囲である場合にコンデンサC1を充電するように制御してもよい。例えばMOSFETQ1のドレイン-ソース間電圧Vds1がきれいな正弦波ではなくノイズが混じっている場合には、一瞬だけ閾値電圧Vref1を下回るが、すぐに元に戻ってしまう可能性がある。このような場合に、傾きを考慮しないと、MOSFETQ2をオンしたあとすぐにオフすることとなり、損失が発生してしまう。この場合は、傾きが通常よりも急峻になっているので、微分回路でその傾きも検出して制御に用いることで、ノイズによる誤動作を防ぐことができる。 In addition, as another example, the magnitude of the drain-source voltage Vds1 of MOSFETQ1 is detected, and its slope is also detected by a differential circuit, and the drain-source voltage Vds1 of MOSFETQ1 is equal to or lower than the threshold voltage Vref1, and The capacitor C1 may be controlled to be charged when the slope is within a predetermined slope range that is not too steep. For example, if the drain-source voltage Vds1 of the MOSFET Q1 is not a clean sine wave but contains noise, it may drop below the threshold voltage Vref1 for a moment, but return to the original level immediately. In such a case, if the slope is not taken into account, MOSFET Q2 will turn off immediately after being turned on, resulting in a loss. In this case, since the slope is steeper than usual, malfunctions due to noise can be prevented by detecting the slope with a differential circuit and using it for control.
 次に、図2に基づいて実施例1の整流回路2の動作を説明する。 Next, the operation of the rectifier circuit 2 of the first embodiment will be explained based on FIG. 2.
 時刻t0では、整流期間が終わり、非整流期間が始まる。 At time t0, the rectification period ends and the non-rectification period begins.
 時刻t0から時刻t1までの期間は、非整流期間であり、MOSFETQ1はオフしている。また、ブリッジ回路に入力される正弦波電圧の増加に伴って、MOSFETQ1のドレイン-ソース間電圧Vds1は増加する。また、本期間において、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1より小さいため、制御回路CTRはMOSFETQ2をオンに制御する。このとき、MOSFETQ1のドレイン-ソース間電圧Vds1はコンデンサC1の電圧Vc1より小さいが、ダイオードDがコンデンサC1の正極端子からMOSFETQ1のドレイン端子への電流の逆流を防ぐ。 The period from time t0 to time t1 is a non-rectification period, and MOSFET Q1 is off. Furthermore, as the sinusoidal voltage input to the bridge circuit increases, the drain-source voltage Vds1 of MOSFET Q1 increases. Furthermore, during this period, since the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the threshold voltage Vref1, the control circuit CTR turns on the MOSFET Q2. At this time, the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the voltage Vc1 of the capacitor C1, but the diode D prevents current from flowing backward from the positive terminal of the capacitor C1 to the drain terminal of the MOSFET Q1.
 時刻t1から時刻t2までの期間は、MOSFETQ1のドレイン-ソース間電圧Vds1が閾値電圧Vref1より小さいため、引き続き制御回路CTRはMOSFETQ2をオンに制御する。また、MOSFETQ1のドレイン-ソース間電圧Vds1がコンデンサC1の電圧Vc1とダイオードDの順方向電圧Vfの合計より大きい。その結果、コンデンサC1への充電が開始され、コンデンサC1の電圧Vc1は増加する。コンデンサC1の充電電流Icは、MOSFETQ1のドレイン端子、MOSFETQ2、ダイオードD、コンデンサC1、MOSFETQ1のソース端子の経路で流れる。 During the period from time t1 to time t2, the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR continues to control MOSFET Q2 to turn on. Further, the drain-source voltage Vds1 of the MOSFET Q1 is larger than the sum of the voltage Vc1 of the capacitor C1 and the forward voltage Vf of the diode D. As a result, charging of the capacitor C1 is started, and the voltage Vc1 of the capacitor C1 increases. The charging current Ic of the capacitor C1 flows through a path including the drain terminal of the MOSFET Q1, the MOSFET Q2, the diode D, the capacitor C1, and the source terminal of the MOSFET Q1.
 時刻t2では、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1に等しい。 At time t2, the drain-source voltage Vds1 of MOSFET Q1 is equal to the threshold voltage Vref1.
 時刻t2から時刻t3までの期間は、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1より大きいため、制御回路CTRはMOSFETQ2をオフに制御し、充電停止期間とする。その結果、コンデンサC1の充電電流Icは遮断される。本期間において、コンデンサC1に蓄積された電力は駆動回路1の待機電力として消費されるが、コンデンサC1は充電されないため、コンデンサの電圧Vc1は減少する。また、本期間において、ブリッジ回路に入力される正弦波電圧は、前半は増加し、後半は減少する。これに伴い、MOSFETQ1のドレイン-ソース間電圧Vds1も前半は増加し、後半は減少に転ずる。 During the period from time t2 to time t3, the drain-source voltage Vds1 of MOSFET Q1 is higher than the threshold voltage Vref1, so the control circuit CTR controls MOSFET Q2 to turn off, making it a charging stop period. As a result, the charging current Ic of the capacitor C1 is cut off. During this period, the power accumulated in the capacitor C1 is consumed as standby power for the drive circuit 1, but since the capacitor C1 is not charged, the voltage Vc1 of the capacitor decreases. Furthermore, during this period, the sine wave voltage input to the bridge circuit increases in the first half and decreases in the second half. Along with this, the drain-source voltage Vds1 of MOSFET Q1 also increases in the first half, and begins to decrease in the second half.
 時刻t3では、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1に等しい。 At time t3, the drain-source voltage Vds1 of MOSFET Q1 is equal to the threshold voltage Vref1.
 時刻t3から時刻t4までの期間は、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1より小さいため、制御回路CTRはMOSFETQ2をオンに制御する。また、時刻t2から時刻t3までの期間において、コンデンサC1の電圧Vc1は減少しているため、MOSFETQ1のドレイン-ソース間電圧Vds1はコンデンサC1の電圧Vc1とダイオードDの順方向電圧Vfの合計より大きい。その結果、コンデンサC1の充電電流Icは、MOSFETQ1のドレイン端子、MOSFETQ2、ダイオードD、コンデンサC1、MOSFETQ1のソース端子の経路で流れ、コンデンサC1の電圧Vc1は増加する。この期間でもコンデンサC1の充電を行う点が従来の図9との相違点である。 During the period from time t3 to time t4, the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR turns on MOSFET Q2. In addition, during the period from time t2 to time t3, the voltage Vc1 of the capacitor C1 decreases, so the drain-source voltage Vds1 of the MOSFET Q1 is greater than the sum of the voltage Vc1 of the capacitor C1 and the forward voltage Vf of the diode D. . As a result, the charging current Ic of the capacitor C1 flows through the path of the drain terminal of the MOSFET Q1, the MOSFET Q2, the diode D, the capacitor C1, and the source terminal of the MOSFET Q1, and the voltage Vc1 of the capacitor C1 increases. The difference from the conventional example shown in FIG. 9 is that the capacitor C1 is charged even during this period.
 時刻t4は、MOSFETQ1の電圧が、コンデンサC1の電圧Vc1とダイオードDの順方向電圧Vfの合計に等しくなった時である。 Time t4 is when the voltage of MOSFET Q1 becomes equal to the sum of voltage Vc1 of capacitor C1 and forward voltage Vf of diode D.
 時刻t4から時刻t5までの期間は、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1より小さいため、引き続き制御回路CTRはMOSFETQ2をオンに制御する。このとき、ダイオードDがコンデンサC1の正極端子からMOSFETQ1のドレイン端子へ電荷が流出することを防ぐ。 During the period from time t4 to time t5, the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR continues to control MOSFET Q2 to turn on. At this time, diode D prevents electric charge from flowing out from the positive terminal of capacitor C1 to the drain terminal of MOSFET Q1.
 最後に、時刻t5から時刻t0までの期間では、再び整流期間となり、駆動回路1がMOSFETQ1をオンして、アノードAからカソードKに整流電流が流れる。 Finally, in the period from time t5 to time t0, there is a rectification period again, and the drive circuit 1 turns on the MOSFET Q1, and a rectified current flows from the anode A to the cathode K.
 ここで、駆動回路1の動作とMOSFETQ1の制御方法について説明する。 Here, the operation of the drive circuit 1 and the control method of MOSFET Q1 will be explained.
 駆動回路1のコンパレータCo1は、MOSFETQ1のドレイン-ソース間電圧Vds1を、MOSFETQ2のソース端子とMOSFETQ1のソース端子から検出する。検出した電圧に基づき、駆動回路1はMOSFETQ1をターンオン、ターンオフする。 The comparator Co1 of the drive circuit 1 detects the drain-source voltage Vds1 of the MOSFETQ1 from the source terminal of the MOSFETQ2 and the source terminal of the MOSFETQ1. Based on the detected voltage, the drive circuit 1 turns on and turns off the MOSFET Q1.
 アノードAからカソードKに流れる整流電流は、まず、MOSFETQ1のボディダイオードDQ1を流れる。ボディダイオードDQ1の電圧降下により、MOSFETQ1のドレイン-ソース間電圧Vds1は負の値となる。 The rectified current flowing from the anode A to the cathode K first flows through the body diode DQ1 of the MOSFET Q1. Due to the voltage drop across the body diode DQ1, the drain-source voltage Vds1 of the MOSFET Q1 takes a negative value.
 コンパレータCo1が検出した電圧がコンパレータCo1の持つ第1の閾値電圧より小さくなると、コンパレータCo1はオン信号を出力し、ゲートドライバGD1がMOSFETQ1のゲート-ソース間電圧Vgs1をコンデンサC1の電圧Vc1までプルアップすることで、MOSFETQ1はターンオンする。 When the voltage detected by comparator Co1 becomes smaller than the first threshold voltage of comparator Co1, comparator Co1 outputs an on signal, and gate driver GD1 pulls up the gate-source voltage Vgs1 of MOSFET Q1 to the voltage Vc1 of capacitor C1. By doing so, MOSFET Q1 is turned on.
 その後、MOSFETQ1のドレイン-ソース間電圧Vds1は、整流電流とMOSFETQ1のオン抵抗で決まる電圧となる。 After that, the drain-source voltage Vds1 of MOSFETQ1 becomes a voltage determined by the rectified current and the on-resistance of MOSFETQ1.
 時間の経過とともに、整流電流が減少する。整流電流の減少に伴い、MOSFETQ1のドレイン-ソース間電圧Vds1は増加する。コンパレータCo1の検出した電圧がコンパレータCo1の持つ第2の閾値電圧より大きくなったとき、コンパレータCo1はオフ信号を出力して、ゲートドライバGD1はMOSFETQ1のゲート-ソース間電圧Vgs1を0Vにプルダウンすることで、MOSFETQ1はターンオフする。 As time passes, the rectified current decreases. As the rectified current decreases, the drain-source voltage Vds1 of MOSFET Q1 increases. When the voltage detected by the comparator Co1 becomes larger than the second threshold voltage of the comparator Co1, the comparator Co1 outputs an off signal, and the gate driver GD1 pulls down the gate-source voltage Vgs1 of MOSFET Q1 to 0V. Then, MOSFETQ1 is turned off.
 コンパレータCo1の持つ第1の閾値電圧と第2の閾値電圧は同じ値でも良いし、第1の閾値電圧が第2の閾値電圧より小さくても良い。第1の閾値電圧が第2の閾値電圧より小さい場合、MOSFETが短周期でオンとオフを繰り返すチャタリングを抑制可能である。 The first threshold voltage and the second threshold voltage of the comparator Co1 may be the same value, or the first threshold voltage may be smaller than the second threshold voltage. When the first threshold voltage is lower than the second threshold voltage, it is possible to suppress chattering in which the MOSFET repeatedly turns on and off in short cycles.
 再び図2の説明に戻る。 Returning to the explanation of FIG. 2 again.
 時刻t5から時刻t0までの期間では、MOSFETQ1のドレイン-ソース間電圧Vds1は閾値電圧Vref1より小さいため、引き続き制御回路CTRはMOSFETQ2をオンに制御する。一方で、MOSFETQ1のドレイン-ソース間電圧Vds1はコンデンサC1の電圧Vc1とダイオードDの順方向電圧Vfの合計より小さいため、コンデンサC1は充電されない。このとき、MOSFETQ1のドレイン-ソース間電圧Vds1がコンデンサC1の電圧Vc1より小さいが、ダイオードDがコンデンサC1の正極端子からMOSFETQ1のドレイン端子への電流の逆流を防ぐ。 During the period from time t5 to time t0, the drain-source voltage Vds1 of MOSFET Q1 is smaller than the threshold voltage Vref1, so the control circuit CTR continues to control MOSFET Q2 to turn on. On the other hand, since the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the sum of the voltage Vc1 of the capacitor C1 and the forward voltage Vf of the diode D, the capacitor C1 is not charged. At this time, although the drain-source voltage Vds1 of the MOSFET Q1 is smaller than the voltage Vc1 of the capacitor C1, the diode D prevents current from flowing backward from the positive terminal of the capacitor C1 to the drain terminal of the MOSFET Q1.
 その結果、本期間では、コンデンサC1に蓄積された電力は駆動回路1の消費電力とMOSFETQ1のゲート-ソース間電圧Vgs1の生成に使用されるため、コンデンサC1の電圧Vc1は減少する。 As a result, in this period, the voltage Vc1 of the capacitor C1 decreases because the power stored in the capacitor C1 is used for the power consumption of the drive circuit 1 and for generating the gate-source voltage Vgs1 of the MOSFET Q1.
 上記の制御を繰り返すことで、実施例1の整流回路2は同期整流を実現する。 By repeating the above control, the rectifier circuit 2 of the first embodiment realizes synchronous rectification.
 上記の制御において、時刻t2から時刻t3までの期間と時刻t4から次の時刻t1までの期間は、コンデンサC1が充電されないため、コンデンサC1の電圧Vc1が減少する。いずれかの期間におけるコンデンサC1の電圧Vc1の最小値が、コンデンサC1の電圧下限値Vcref2以上であるように、コンデンサC1の容量を選定する必要がある。コンデンサC1の電圧下限値Vcref2は、例えば、駆動回路1の最低動作電圧より大きく、かつ、MOSFETQ1のオン抵抗が十分小さくなるようなMOSFETQ1のゲート閾値電圧Vgth1より大きい値である。 In the above control, since the capacitor C1 is not charged during the period from time t2 to time t3 and from time t4 to the next time t1, the voltage Vc1 of the capacitor C1 decreases. It is necessary to select the capacitance of the capacitor C1 so that the minimum value of the voltage Vc1 of the capacitor C1 in any period is equal to or higher than the voltage lower limit value Vcref2 of the capacitor C1. The voltage lower limit value Vcref2 of the capacitor C1 is, for example, a value larger than the lowest operating voltage of the drive circuit 1 and larger than the gate threshold voltage Vgth1 of the MOSFET Q1 such that the on-resistance of the MOSFET Q1 becomes sufficiently small.
 以上説明したとおり、実施例1の整流回路2によれば、コンデンサC1の必要容量を削減でき、その結果、コンデンサC1の体積を削減して整流回路2および電源の小型化、低コスト化を実現できる。 As explained above, according to the rectifier circuit 2 of Example 1, the required capacity of the capacitor C1 can be reduced, and as a result, the volume of the capacitor C1 can be reduced, realizing miniaturization and cost reduction of the rectifier circuit 2 and the power supply. can.
 図3は、実施例2の整流回路の回路図である。 FIG. 3 is a circuit diagram of the rectifier circuit of Example 2.
 実施例2は、実施例1の変形例である。実施例2は、制御回路CTRの具体的な構成の一例を示している点で実施例1と相違し、その他の構成、効果は基本的に実施例1と同様である。したがって、実施例2では、実施例1との相違点を中心に説明し、実施例1と重複する説明は省略する。 Example 2 is a modification of Example 1. The second embodiment differs from the first embodiment in that it shows an example of a specific configuration of the control circuit CTR, and the other configurations and effects are basically the same as the first embodiment. Therefore, in the second embodiment, differences from the first embodiment will be mainly explained, and explanations that overlap with the first embodiment will be omitted.
 実施例2の整流回路2の制御回路CTRは、MOSFETQ1のドレイン-ソース間電圧Vds1を分圧する抵抗R1および抵抗R2と、電力がコンデンサC1から供給され、抵抗R2の電圧を検出するコンパレータCo2と、入力端子がコンパレータCo2の出力端子に接続され、出力端子がMOSFETQ2のゲート端子に接続され、電力がコンデンサC1から供給され、コンパレータCo2の出力信号に基づいてMOSFETQ2を制御するゲートドライバGD2とを有する。 The control circuit CTR of the rectifier circuit 2 of the second embodiment includes a resistor R1 and a resistor R2 that divide the drain-source voltage Vds1 of the MOSFET Q1, and a comparator Co2 that is supplied with power from the capacitor C1 and detects the voltage of the resistor R2. It has a gate driver GD2 whose input terminal is connected to the output terminal of the comparator Co2, whose output terminal is connected to the gate terminal of the MOSFET Q2, to which power is supplied from the capacitor C1, and which controls the MOSFET Q2 based on the output signal of the comparator Co2.
 ここで、抵抗R1および抵抗R2は、抵抗R2の電圧がコンパレータCo2の定格電圧以下となるように設定されている。コンパレータCo2は、検出した抵抗R2の電圧を閾値電圧Vref2と比較し、ゲートドライバGD2に信号を出力する。このとき、MOSFETQ1のドレイン-ソース間電圧Vds1が閾値電圧Vref1と等しくなったときに、抵抗R2の電圧が閾値電圧Vref2と等しくなるように、閾値電圧Vref2を選定しておく。 Here, the resistor R1 and the resistor R2 are set so that the voltage of the resistor R2 is equal to or lower than the rated voltage of the comparator Co2. Comparator Co2 compares the detected voltage of resistor R2 with threshold voltage Vref2 and outputs a signal to gate driver GD2. At this time, the threshold voltage Vref2 is selected so that when the drain-source voltage Vds1 of the MOSFET Q1 becomes equal to the threshold voltage Vref1, the voltage of the resistor R2 becomes equal to the threshold voltage Vref2.
 実施例2の整流回路2によれば、実施例1の図2で説明した動作を実現することができる。 According to the rectifier circuit 2 of the second embodiment, the operation described in FIG. 2 of the first embodiment can be realized.
 図4は、実施例3の整流回路の回路図である。 FIG. 4 is a circuit diagram of the rectifier circuit of Example 3.
 実施例3は、実施例1の変形例である。実施例3は、抵抗R3を有する点で実施例1と相違し、その他の構成、効果は基本的に実施例1と同様である。したがって、実施例3では、実施例1との相違点を中心に説明し、実施例1と重複する説明は省略する。なお、実施例3は、実施例2に適用してもよい。 Example 3 is a modification of Example 1. The third embodiment differs from the first embodiment in that it includes a resistor R3, and the other configurations and effects are basically the same as the first embodiment. Therefore, in the third embodiment, differences from the first embodiment will be mainly explained, and explanations that overlap with the first embodiment will be omitted. Note that the third embodiment may be applied to the second embodiment.
 実施例3の整流回路2は、一方の端子がMOSFETQ1のドレイン端子に接続され、他方の端子がMOSFETQ2のドレイン端子に接続された抵抗R3を有する。換言すれば、MOSFETQ1のドレイン端子とMOSFETQ2のドレイン端子との間に挿入された抵抗R3を有する。 The rectifier circuit 2 of Example 3 has a resistor R3 with one terminal connected to the drain terminal of MOSFET Q1 and the other terminal connected to the drain terminal of MOSFET Q2. In other words, the resistor R3 is inserted between the drain terminal of MOSFETQ1 and the drain terminal of MOSFETQ2.
 実施例1から実施例2の整流回路2では、コンデンサC1が充電されるとき、MOSFETQ1のドレイン端子、MOSFETQ2、ダイオードD、コンデンサC1、MOSFETQ1のソース端子の経路でコンデンサC1の充電電流Icが流れる。特に、コンデンサC1の充電が開始された直後は、充電電流Icが急峻に増加する。その結果、充電電流Icの経路での損失増加による整流回路2の効率低下や、MOSFETQ2やダイオードDの定格を超える温度上昇が生じる場合がある。 In the rectifier circuits 2 of Examples 1 and 2, when the capacitor C1 is charged, the charging current Ic of the capacitor C1 flows through the path of the drain terminal of the MOSFET Q1, the MOSFET Q2, the diode D, the capacitor C1, and the source terminal of the MOSFET Q1. In particular, immediately after charging of the capacitor C1 is started, the charging current Ic increases sharply. As a result, the efficiency of the rectifier circuit 2 may decrease due to an increase in loss in the path of the charging current Ic, and the temperature of the MOSFET Q2 and the diode D may rise beyond their ratings.
 実施例3の整流回路2によれば、充電電流Icの経路上に直列に抵抗R3を挿入することで、コンデンサC1の充電電流Icの急峻な増加を抑制できる。すなわち、抵抗R3は突入電流防止抵抗として機能する。これにより、充電電流Icの経路での損失増加による整流回路2の効率低下と、MOSFETQ2やダイオードDの温度上昇を抑制することができる。 According to the rectifier circuit 2 of the third embodiment, a steep increase in the charging current Ic of the capacitor C1 can be suppressed by inserting the resistor R3 in series on the path of the charging current Ic. That is, the resistor R3 functions as an inrush current prevention resistor. Thereby, it is possible to suppress a decrease in efficiency of the rectifier circuit 2 due to an increase in loss in the path of the charging current Ic and a rise in temperature of the MOSFET Q2 and the diode D.
 図5は、実施例4の整流回路の回路図である。 FIG. 5 is a circuit diagram of the rectifier circuit of Example 4.
 実施例4は、実施例3の変形例である。実施例4は、コンデンサC2を有する点で実施例3と相違し、その他の構成、効果は基本的に実施例3と同様である。したがって、実施例4では、実施例3との相違点を中心に説明し、実施例3と重複する説明は省略する。なお、実施例4は、実施例1から実施例2に適用してもよい。 Example 4 is a modified example of Example 3. Example 4 differs from Example 3 in that it has a capacitor C2, but other configurations and effects are basically the same as Example 3. Therefore, in Example 4, the differences from Example 3 will be mainly described, and descriptions that overlap with Example 3 will be omitted. Note that Example 4 may be applied to Examples 1 and 2.
 実施例4の整流回路2は、正極端子がMOSFETQ2のソース端子に接続され、負極端子がMOSFETQ1のソース端子に接続されたコンデンサC2を有する。 The rectifier circuit 2 of Example 4 has a capacitor C2 whose positive terminal is connected to the source terminal of MOSFETQ2 and whose negative terminal is connected to the source terminal of MOSFETQ1.
 実施例1から実施例3の整流回路では、コンパレータCo1が検出する電圧に含まれる高周波ノイズにより、コンパレータCo1が誤動作する場合がある。その結果、例えば、整流期間中にMOSFETQ1がターンオフしてしまい同期整流による損失低減効果が損なわれる場合がある。 In the rectifier circuits of Examples 1 to 3, the comparator Co1 may malfunction due to high frequency noise contained in the voltage detected by the comparator Co1. As a result, for example, MOSFET Q1 may turn off during the rectification period, and the loss reduction effect of synchronous rectification may be impaired.
 実施例4の整流回路2によれば、MOSFETQ2のオン抵抗、抵抗R3、コンデンサC2でローパスフィルタを構成することで、コンパレータCo1が検出する電圧に含まれる高周波ノイズを抑制可能である。なお、抵抗R3を挿入しない場合でも、MOSFETQ2のオン抵抗とコンデンサC2でローパスフィルタを構成するため、同様に、コンパレータCo1が検出する電圧に含まれる高周波ノイズを抑制可能である。これにより、コンパレータCo1の誤動作とMOSFETQ1の意図しないターンオンとターンオフを抑制することができ、同期整流による損失低減効果が損なわれない。 According to the rectifier circuit 2 of the fourth embodiment, high-frequency noise contained in the voltage detected by the comparator Co1 can be suppressed by configuring a low-pass filter with the on-resistance of the MOSFET Q2, the resistor R3, and the capacitor C2. Note that even if the resistor R3 is not inserted, the on-resistance of the MOSFET Q2 and the capacitor C2 constitute a low-pass filter, so it is possible to similarly suppress high-frequency noise contained in the voltage detected by the comparator Co1. Thereby, malfunction of the comparator Co1 and unintended turn-on and turn-off of the MOSFET Q1 can be suppressed, and the loss reduction effect of synchronous rectification is not impaired.
 図6は、実施例5の整流回路の構成の一例を示す図である。図7は、実施例5の整流回路の構成の他の例を示す図である。 FIG. 6 is a diagram showing an example of the configuration of the rectifier circuit of Example 5. FIG. 7 is a diagram showing another example of the configuration of the rectifier circuit according to the fifth embodiment.
 実施例5は、実施例1の変形例である。実施例5は、整流回路2を半導体パッケージに内蔵する点で実施例1と相違し、その他の構成、効果は基本的に実施例1と同様である。したがって、実施例5では、実施例1との相違点を中心に説明し、実施例1と重複する説明は省略する。なお、実施例5の図6および図7では、実施例1の図1に適用した例で説明しているが、実施例1で説明した種々の変形例や、実施例2から実施例4に適用してもよい。 Example 5 is a modification of Example 1. The fifth embodiment differs from the first embodiment in that the rectifier circuit 2 is built into the semiconductor package, and the other configurations and effects are basically the same as the first embodiment. Therefore, in the fifth embodiment, differences from the first embodiment will be mainly explained, and explanations that overlap with the first embodiment will be omitted. Note that although FIGS. 6 and 7 of Example 5 are explained using an example applied to FIG. May be applied.
 図6は、整流回路2を半導体パッケージ3に内蔵した構成を示している。半導体パッケージ3は、カソードKとアノードAとを外部端子として持つ。 FIG. 6 shows a configuration in which the rectifier circuit 2 is built into the semiconductor package 3. The semiconductor package 3 has a cathode K and an anode A as external terminals.
 図7は、例えば4個の整流回路2を使用して構成したブリッジ回路などの複数の整流回路2を1つの半導体パッケージ4に内蔵した構成を示している。半導体パッケージ4は端子T1~T4を外部端子として持つ。 FIG. 7 shows a configuration in which a plurality of rectifier circuits 2, such as a bridge circuit configured using four rectifier circuits 2, are built into one semiconductor package 4. The semiconductor package 4 has terminals T1 to T4 as external terminals.
 実施例5によれば、整流回路を使用する製品を設計・製造する際に、本実施例のような駆動回路とコンデンサを内蔵した整流回路を購入して組み込めばよく、駆動回路とコンデンサの設計および実装の工数がなくなるため、全体の設計および実装の工数を削減できる効果がある。 According to Example 5, when designing and manufacturing a product that uses a rectifier circuit, it is sufficient to purchase and incorporate a rectifier circuit with a built-in drive circuit and capacitor as in this example, and the design of the drive circuit and capacitor is simple. This has the effect of reducing the overall design and implementation man-hours.
 図8は、実施例6の電源の回路図である。 FIG. 8 is a circuit diagram of the power supply of Example 6.
 実施例6は、実施例1から実施例5で説明した整流回路2の適用対象となる電源の実施例である。 Example 6 is an example of a power supply to which the rectifier circuit 2 described in Examples 1 to 5 is applied.
 実施例1から実施例5の整流回路2の適用範囲は、電源に用いられる整流回路全般である。例えば、図8に示すようなフロントエンド電源においては、商用整流用ダイオードCRD1~CRD4、還流ダイオードFWD、二次側整流ダイオードSSD1~SSD2、逆流防止ダイオードBPDとして実施例1から実施例5の整流回路2を適用可能である。 The scope of application of the rectifier circuits 2 of Examples 1 to 5 is all rectifier circuits used in power supplies. For example, in a front-end power supply as shown in FIG. 8, the rectifier circuits of Embodiments 1 to 5 are used as commercial rectifier diodes CRD1 to CRD4, free-wheeling diodes FWD, secondary rectifier diodes SSD1 to SSD2, and backflow prevention diodes BPD. 2 is applicable.
 実施例1から実施例5の整流回路2を、フロントエンド電源等の電源に適用することにより、電源の小型化やコスト削減に寄与することができる。 By applying the rectifier circuit 2 of Examples 1 to 5 to a power source such as a front-end power source, it is possible to contribute to downsizing and cost reduction of the power source.
 以上、本発明の実施例を説明したが、本発明は実施例に記載された構成に限定されず、本発明の技術的思想の範囲内で種々の変更が可能である。また、各実施例で説明した構成の一部または全部を組み合わせて適用してもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various changes can be made within the scope of the technical idea of the present invention. Further, some or all of the configurations described in each embodiment may be combined and applied.
1:駆動回路、2:整流回路、3、4:半導体パッケージ、T1~T4:端子、K:カソード、A:アノード、C1、C2:コンデンサ、R1、R2、R3:抵抗、Q1、Q2:MOSFET、DQ1、DQ2:ボディダイオード、D:ダイオード、Co1、Co2:コンパレータ、GD1、GD2:ゲートドライバ、CTR:制御回路、t、t0~t5:時刻、Ic:充電電流、Vc1:コンデンサの電圧、Vref1、Vref2:閾値電圧、Vcref1:コンデンサC1の目標電圧、Vcref2:コンデンサC1の電圧下限値、Vf:ダイオードDの順方向電圧、Vds1~Vds2:MOSFETQ1~Q2のドレイン-ソース間電圧、Vgs1~Vgs2:MOSFETQ1~Q2のゲート-ソース間電圧、Vgth1~Vgth2:MOSFETQ1~Q2のゲート閾値電圧、CRD1~CRD4:商用整流用ダイオード、FWD:還流ダイオード、SSD1~SSD2:二次側整流ダイオード、BPD:逆流防止ダイオード 1: Drive circuit, 2: Rectifier circuit, 3, 4: Semiconductor package, T1 to T4: Terminal, K: Cathode, A: Anode, C1, C2: Capacitor, R1, R2, R3: Resistor, Q1, Q2: MOSFET , DQ1, DQ2: body diode, D: diode, Co1, Co2: comparator, GD1, GD2: gate driver, CTR: control circuit, t, t0 to t5: time, Ic: charging current, Vc1: capacitor voltage, Vref1 , Vref2: threshold voltage, Vcref1: target voltage of capacitor C1, Vcref2: lower limit voltage of capacitor C1, Vf: forward voltage of diode D, Vds1 to Vds2: drain-source voltage of MOSFETs Q1 to Q2, Vgs1 to Vgs2: Gate-source voltage of MOSFETQ1~Q2, Vgth1~Vgth2: Gate threshold voltage of MOSFETQ1~Q2, CRD1~CRD4: Commercial rectifier diode, FWD: Freewheeling diode, SSD1~SSD2: Secondary side rectifier diode, BPD: Backflow prevention diode

Claims (16)

  1.  アノードとカソードとを有する整流回路において、
     第1の端子が前記整流回路の前記カソードに接続され、第2の端子が前記整流回路の前記アノードに接続された第1のスイッチング素子と、
     カソードが前記第1の端子に接続され、アノードが前記第2の端子に接続された第1のダイオードと、
     前記第1のスイッチング素子を駆動する駆動回路と、
     前記駆動回路に電力を供給する第1のコンデンサと、を備え、
     前記第1のコンデンサは、前記第1のスイッチング素子がオフしてから次にオンするまでの期間に、前記第1のコンデンサが充電される第1の充電期間および第2の充電期間と、前記第1の充電期間と前記第2の充電期間との間に設けられ前記第1のコンデンサへの充電が停止される充電停止期間とを有することを特徴とする整流回路。
    In a rectifier circuit having an anode and a cathode,
    a first switching element having a first terminal connected to the cathode of the rectifier circuit and a second terminal connected to the anode of the rectifier circuit;
    a first diode having a cathode connected to the first terminal and an anode connected to the second terminal;
    a drive circuit that drives the first switching element;
    a first capacitor that supplies power to the drive circuit;
    The first capacitor has a first charging period and a second charging period in which the first capacitor is charged during a period from when the first switching element is turned off to when it is next turned on, and a second charging period when the first switching element is charged. A rectifier circuit comprising a charging stop period provided between the first charging period and the second charging period in which charging of the first capacitor is stopped.
  2.  請求項1において、
     前記第1の充電期間および前記第2の充電期間は、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧が所定の電圧以下の期間であり、
     前記充電停止期間は、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧が前記所定の電圧より大きい期間であることを特徴とする整流回路。
    In claim 1,
    The first charging period and the second charging period are periods in which the voltage between the first terminal and the second terminal of the first switching element is equal to or lower than a predetermined voltage,
    The rectifier circuit, wherein the charging stop period is a period in which a voltage between the first terminal and the second terminal of the first switching element is higher than the predetermined voltage.
  3.  請求項2において、
     前記第1の充電期間は、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧が増加中の期間であり、
     前記第2の充電期間は、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧が減少中の期間であることを特徴とする整流回路。
    In claim 2,
    The first charging period is a period during which the voltage between the first terminal and the second terminal of the first switching element is increasing,
    The rectifier circuit is characterized in that the second charging period is a period during which a voltage between the first terminal and the second terminal of the first switching element is decreasing.
  4.  請求項2において、
     第3の端子が前記第1のスイッチング素子の前記第1の端子に接続された第2のスイッチング素子と、
     アノードが前記第2のスイッチング素子の第4の端子に接続され、カソードが前記第2のスイッチング素子の前記第3の端子に接続された第2のダイオードと、
     アノードが前記第2のスイッチング素子の前記第4の端子に接続された第3のダイオードと、
     正極端子が前記第3のダイオードのカソードに接続され、負極端子が前記第1のスイッチング素子の前記第2の端子に接続された前記第1のコンデンサと、
     前記第2のスイッチング素子を制御する信号を、前記第2のスイッチング素子の制御端子に入力する制御回路と、を備え、
     前記駆動回路は、電力が前記第1のコンデンサから供給され、前記第2のスイッチング素子の前記第4の端子と前記第1のスイッチング素子の前記第2の端子との間の電圧を検出する第1のコンパレータと、入力端子が前記第1のコンパレータの出力端子に接続され、出力端子が前記第1のスイッチング素子の制御端子に接続され、電力が前記第1のコンデンサから供給され、前記第1のコンパレータの出力信号に基づいて前記第1のスイッチング素子を制御する第1のゲートドライバとを有し、
     前記制御回路は、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧が前記第1のコンデンサの目標電圧と前記第3のダイオードの順方向電圧との合計電圧以下の期間では前記第2のスイッチング素子をオン状態に制御し、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧が前記第1のコンデンサの目標電圧と前記ダイオードの順方向電圧との合計電圧より大きい期間では前記第2のスイッチング素子をオフ状態に制御することで、前記第1のコンデンサへ流れる充電電流を制御することを特徴とする整流回路。
    In claim 2,
    a second switching element whose third terminal is connected to the first terminal of the first switching element;
    a second diode having an anode connected to the fourth terminal of the second switching element and a cathode connected to the third terminal of the second switching element;
    a third diode whose anode is connected to the fourth terminal of the second switching element;
    the first capacitor having a positive terminal connected to the cathode of the third diode and a negative terminal connected to the second terminal of the first switching element;
    a control circuit that inputs a signal for controlling the second switching element to a control terminal of the second switching element,
    The drive circuit receives power from the first capacitor and detects a voltage between the fourth terminal of the second switching element and the second terminal of the first switching element. 1 comparator, an input terminal is connected to an output terminal of the first comparator, an output terminal is connected to a control terminal of the first switching element, power is supplied from the first capacitor, and the first a first gate driver that controls the first switching element based on the output signal of the comparator;
    The control circuit is configured such that a voltage between the first terminal and the second terminal of the first switching element is a sum of a target voltage of the first capacitor and a forward voltage of the third diode. In a period below the voltage, the second switching element is controlled to be on, and the voltage between the first terminal and the second terminal of the first switching element is equal to the target voltage of the first capacitor. A rectifier circuit, characterized in that the charging current flowing to the first capacitor is controlled by controlling the second switching element to be in an off state during a period when the total voltage is greater than the sum of the forward voltage of the diode and the forward voltage of the diode.
  5.  請求項4において、
     前記第1のスイッチング素子は、前記第1の端子がドレイン端子で、前記第2の端子がソース端子で、前記制御端子がゲート端子である第1のMOSFETであり、
     前記第1のダイオードは、前記第1のMOSFETのボディダイオードであることを特徴とする整流回路。
    In claim 4,
    The first switching element is a first MOSFET in which the first terminal is a drain terminal, the second terminal is a source terminal, and the control terminal is a gate terminal,
    The rectifier circuit, wherein the first diode is a body diode of the first MOSFET.
  6.  請求項4において、
     前記第2のスイッチング素子は、前記第3の端子がドレイン端子で、前記第4の端子がソース端子で、前記制御端子がゲート端子である第2のMOSFETであることを特徴とする整流回路。
    In claim 4,
    The rectifier circuit, wherein the second switching element is a second MOSFET in which the third terminal is a drain terminal, the fourth terminal is a source terminal, and the control terminal is a gate terminal.
  7.  請求項6において、
     前記第2のMOSFETはnチャネルのデプレッション型MOSFETであることを特徴とする整流回路。
    In claim 6,
    A rectifier circuit characterized in that the second MOSFET is an n-channel depression type MOSFET.
  8.  請求項4において、
     前記第1のコンデンサの前記目標電圧は、前記第1のコンパレータの最大定格電圧、前記第1のゲートドライバの最大定格電圧、前記第1のスイッチング素子の前記制御端子と前記第2の端子との間の最大定格電圧のうちの最小のもの以下であることを特徴とする整流回路。
    In claim 4,
    The target voltage of the first capacitor is the maximum rated voltage of the first comparator, the maximum rated voltage of the first gate driver, and the voltage between the control terminal and the second terminal of the first switching element. A rectifier circuit characterized in that the voltage is less than or equal to the minimum of the maximum rated voltages between.
  9.  請求項4において、
     前記制御回路は、前記第2のスイッチング素子を制御するタイミングを決定するための微分回路を有することを特徴とする整流回路。
    In claim 4,
    A rectifier circuit characterized in that the control circuit includes a differentiating circuit for determining timing for controlling the second switching element.
  10.  請求項4において、
     前記第1のコンパレータは、第1の閾値電圧と第2の閾値電圧とを有し、検出した前記第2のスイッチング素子の前記第4の端子と前記第1のスイッチング素子の前記第2の端子との間の電圧が前記第1の閾値電圧より小さい場合にオン信号を生成し、前記第2の閾値電圧より大きい場合にオフ信号を生成し、前記第1の閾値電圧は前記第2の閾値電圧以下であることを特徴とする整流回路。
    In claim 4,
    The first comparator has a first threshold voltage and a second threshold voltage, and detects the fourth terminal of the second switching element and the second terminal of the first switching element. an on signal is generated when the voltage between the two voltages is smaller than the first threshold voltage, and an off signal is generated when the voltage is larger than the second threshold voltage, and the first threshold voltage is the second threshold voltage. A rectifier circuit characterized in that the voltage is below.
  11.  請求項4において、
     前記制御回路は、前記第1のスイッチング素子の前記第1の端子と前記第2の端子との間の電圧を分圧する第1の抵抗および第2の抵抗と、電力が前記第1のコンデンサから供給され、前記第2の抵抗の電圧を検出する第2のコンパレータと、入力端子が前記第2のコンパレータの出力端子に接続され、出力端子が前記第2のスイッチング素子の前記制御端子に接続され、電力が前記第1のコンデンサから供給され、前記第2のコンパレータの出力信号に基づいて前記第2のスイッチング素子を制御する第2のゲートドライバとを有することを特徴とする整流回路。 
    In claim 4,
    The control circuit includes a first resistor and a second resistor that divide the voltage between the first terminal and the second terminal of the first switching element; a second comparator that is supplied and detects the voltage of the second resistor, an input terminal connected to the output terminal of the second comparator, and an output terminal connected to the control terminal of the second switching element; and a second gate driver to which power is supplied from the first capacitor and which controls the second switching element based on the output signal of the second comparator.
  12.  請求項4において、
     第5の端子が前記第1のスイッチング素子の前記第1の端子に接続され、第6の端子が前記第2のスイッチング素子の前記第3の端子に接続された第3の抵抗を有することを特徴とする整流回路。
    In claim 4,
    a third resistor having a fifth terminal connected to the first terminal of the first switching element and a sixth terminal connected to the third terminal of the second switching element; Features a rectifier circuit.
  13.  請求項4において、
     正極端子が前記第2のスイッチング素子の前記第4の端子に接続され、負極端子が前記第1のスイッチング素子の前記第2の端子に接続された第2のコンデンサを有することを特徴とする整流回路。
    In claim 4,
    A rectifier comprising a second capacitor having a positive terminal connected to the fourth terminal of the second switching element and a negative terminal connected to the second terminal of the first switching element. circuit.
  14.  請求項1から13の何れかにおいて、
     前記整流回路が半導体パッケージに内蔵され、前記整流回路の前記アノードと前記カソードとが前記半導体パッケージの外部端子であることを特徴とする整流回路。
    In any one of claims 1 to 13,
    A rectifier circuit, wherein the rectifier circuit is built into a semiconductor package, and the anode and cathode of the rectifier circuit are external terminals of the semiconductor package.
  15.  請求項1から13の何れかにおいて、
     複数の前記整流回路が1つの半導体パッケージに内蔵されていることを特徴とする整流回路。
    In any one of claims 1 to 13,
    A rectifier circuit characterized in that a plurality of the rectifier circuits are built into one semiconductor package.
  16.  請求項1から13の何れかに記載の整流回路を有することを特徴とする電源。 A power source comprising the rectifier circuit according to any one of claims 1 to 13.
PCT/JP2023/013972 2022-09-15 2023-04-04 Rectifier circuit and power supply using same WO2024057591A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221141A (en) * 1995-02-14 1996-08-30 Mitsubishi Electric Corp Power supply circuit
JP2001251861A (en) * 2000-02-08 2001-09-14 Vlt Corp Active rectifier
JP2010239736A (en) * 2009-03-31 2010-10-21 Mitsubishi Electric Corp Power conversion apparatus
JP2021520774A (en) * 2018-05-03 2021-08-19 アナログ・ディヴァイシス・インターナショナル・アンリミテッド・カンパニー Self-bias ideal diode circuit
JP2022125705A (en) * 2021-02-17 2022-08-29 株式会社 日立パワーデバイス Rectifier circuit, control method for rectifier circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221141A (en) * 1995-02-14 1996-08-30 Mitsubishi Electric Corp Power supply circuit
JP2001251861A (en) * 2000-02-08 2001-09-14 Vlt Corp Active rectifier
JP2010239736A (en) * 2009-03-31 2010-10-21 Mitsubishi Electric Corp Power conversion apparatus
JP2021520774A (en) * 2018-05-03 2021-08-19 アナログ・ディヴァイシス・インターナショナル・アンリミテッド・カンパニー Self-bias ideal diode circuit
JP2022125705A (en) * 2021-02-17 2022-08-29 株式会社 日立パワーデバイス Rectifier circuit, control method for rectifier circuit

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