WO2024057432A1

WO2024057432A1 - Semiconductor device and semiconductor device manufacturing method

Info

Publication number: WO2024057432A1
Application number: PCT/JP2022/034364
Authority: WO
Inventors: 亮弥白▲濱▼; 誠一郎猪ノ口; 省二斉藤
Original assignee: 三菱電機株式会社
Priority date: 2022-09-14
Filing date: 2022-09-14
Publication date: 2024-03-21

Abstract

This disclosure relates to a semiconductor device comprising: a first heat spreader mounting a first semiconductor element; a first electrode plate coupled to the first heat spreader via a bent portion having an inclination; a second heat spreader mounting a second semiconductor element; and a second electrode plate provided so as to have a step with respect to the second heat spreader. The first electrode plate is arranged at a position higher than that of the first heat spreader. The second electrode plate is arranged at a position higher than that of the second heat spreader. The first and second electrode plates are arranged at the same height. The first and second heat spreaders are arranged at the same height. The second electrode plate is arranged above the first heat spreader. The first electrode plate is arranged above the second heat spreader. The first semiconductor element is joined to the first heat spreader and the second electrode plate. The second semiconductor element is joined to the second heat spreader and the first electrode plate.

Description

Semiconductor devices and semiconductor device manufacturing methods

The present disclosure relates to a semiconductor device, and particularly to a semiconductor device with a direct lead bonding structure in which a semiconductor element and an electrode are directly bonded.

In power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and high voltage diodes, the direct lead bonding (DLB) structure in which semiconductor elements and electrodes are directly bonded is used with transfer mold resin. A sealed semiconductor device module is used.

For example, Patent Document 1 discloses a DLB structure in which a semiconductor element is bonded to a die pad of a lead frame using a bonding member such as solder, and then an upper surface electrode of the semiconductor element and a DLB frame are bonded by a bonding member. .

JP2018-081947A

In the conventional technology, it was necessary to prepare a lead frame and a DLB frame, and to join each with a semiconductor element, which resulted in an increase in the number of parts and manufacturing steps, leading to an increase in manufacturing costs.

The present disclosure has been made to solve the above problems, and aims to provide a semiconductor device with reduced manufacturing costs by reducing the number of parts and manufacturing steps.

A semiconductor device according to the present disclosure includes a first heat spreader on which a first semiconductor element is mounted, a first electrode plate connected to the first heat spreader through an inclined bent part, and a second semiconductor element mounted thereon. a second heat spreader, and a second electrode plate provided with a step on the second heat spreader, the first electrode plate being located at a higher position than the first heat spreader. the second electrode plate is placed at a higher position than the second heat spreader, the first electrode plate and the second electrode plate are placed at the same height, and the second electrode plate is placed at a higher position than the second heat spreader; and the second heat spreader are arranged at the same height, the second electrode plate is arranged above the first heat spreader, and the first electrode plate is arranged above the second heat spreader. The first semiconductor element is bonded to the first heat spreader and the second electrode plate, and the second semiconductor element is bonded to the second heat spreader and the first electrode plate. be done.

According to the semiconductor device according to the present disclosure, the frame is provided such that the first heat spreader and the first electrode plate have a step difference, and the frame is provided such that the second heat spreader and the second heat spreader have a step difference. By preparing the frame, the first semiconductor element is bonded to the first heat spreader and the second electrode plate, and the second semiconductor element is bonded to the second heat spreader and the first electrode plate. Since it is possible to obtain a semiconductor device with a high temperature, there is no need to separately provide a heat spreader and an electrode plate, and the number of parts can be reduced. Furthermore, the number of manufacturing steps can be reduced by bonding the first and second semiconductor elements with the two frames superimposed.

1 is a plan view showing the configuration of a semiconductor device according to a first embodiment; FIG. 1 is a plan view showing a frame for manufacturing the semiconductor device of Embodiment 1. FIG. 1 is a plan view showing a frame for manufacturing the semiconductor device of Embodiment 1. FIG. FIG. 2 is a plan view showing a state in which two frames for manufacturing the semiconductor device of the first embodiment are combined. 1 is a cross-sectional view of a frame for manufacturing the semiconductor device of Embodiment 1. FIG. 1 is a cross-sectional view of a frame for manufacturing the semiconductor device of Embodiment 1. FIG. FIG. 3 is a plan view showing a state in the middle of overlapping two frames for manufacturing the semiconductor device of the first embodiment. 7 is a plan view showing a state in which two frames are combined for manufacturing a semiconductor device according to a second embodiment. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. FIG. FIG. 12 is a plan view showing a state in the middle of superimposing two frames for manufacturing a semiconductor device according to a third embodiment. FIG. 7 is a plan view showing a state in which two frames are combined for manufacturing a semiconductor device according to a third embodiment. 7 is a plan view showing a frame for manufacturing a semiconductor device according to a fourth embodiment. FIG. 7 is a plan view showing a frame for manufacturing a semiconductor device according to a fourth embodiment. FIG. FIG. 7 is a plan view showing a state in which two frames are combined for manufacturing a semiconductor device according to a fourth embodiment. FIG. 7 is a cross-sectional view of a frame for manufacturing a semiconductor device according to a fourth embodiment. FIG. 7 is a cross-sectional view of a frame for manufacturing a semiconductor device according to a fourth embodiment. 7 is a cross-sectional view of a frame for manufacturing a semiconductor device according to a fifth embodiment. FIG. 7 is a cross-sectional view of a frame for manufacturing a semiconductor device according to a fifth embodiment. FIG. 12 is a flowchart illustrating a method for manufacturing a semiconductor device according to a sixth embodiment. FIG. 2 is a plan view illustrating a manufacturing process of a semiconductor device. FIG. 2 is a plan view illustrating a manufacturing process of a semiconductor device. FIG. 2 is a plan view illustrating a manufacturing process of a semiconductor device. FIG. 2 is a plan view illustrating a manufacturing process of a semiconductor device. FIG. 2 is a plan view illustrating a manufacturing process of a semiconductor device. FIG. 12 is a plan view showing a state in the middle of overlapping two frames for manufacturing a semiconductor device according to a seventh embodiment. FIG. 9 is a plan view showing a state in which two frames for manufacturing a semiconductor device according to a seventh embodiment are combined. FIG. 12 is a plan view showing a state in the middle of overlapping two frames in the method for manufacturing a semiconductor device according to the eighth embodiment. FIG. 12 is a plan view showing a state in which two frames are combined in a method for manufacturing a semiconductor device according to an eighth embodiment. FIG. 12 is a plan view showing a state in the middle of overlapping two frames in a method for manufacturing a semiconductor device according to a ninth embodiment. FIG. 12 is a plan view showing a state in which two frames are combined in a method for manufacturing a semiconductor device according to an eighth embodiment. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a tenth embodiment. FIG. 10 is a plan view illustrating a method for manufacturing a semiconductor device according to a tenth embodiment. FIG.

<Embodiment 1>
FIG. 1 is a plan view showing the configuration of a single-phase power inverter 100, which is a semiconductor device according to a first embodiment of the present disclosure. The single-phase inverter 100 shown in FIG. 1 is resin-sealed with a molded resin, but for convenience, the molded resin on the upper surface is omitted and only the molded resin RG on the lower surface is shown. Further, for convenience, only the power semiconductor element 1a (first semiconductor element) and the power semiconductor element 1b (second semiconductor element) are shown, but if these are IGBTs or MOSFETs connected in series, then a single-phase It can be thought of as the basic circuit of an inverter.

As shown in FIG. 1, in the single-phase inverter 100, an electrode plate 4a1 is arranged parallel to a heat spreader 4a2 (first heat spreader) on which power semiconductor elements 1a such as IGBTs, MOSFETs, and high voltage diodes are mounted. (first electrode plate) are connected and have the same electrical potential. The heat spreader 4a2 and the electrode plate 4a1 are connected at a bent portion BP1. The bent portion BP1 has a slope that is higher on the electrode plate 4a1 side and lower on the heat spreader 4a2 side. Therefore, a step exists between the heat spreader 4a2 and the electrode plate 4a1.

Further, the bent portion BP1 is provided along one entire long side of the heat spreader 4a2, and the electrode plate 4a1 and the heat spreader 4a2 are firmly engaged, and the shape of the electrode plate 4a1 is It can be stabilized.

In the power semiconductor element 1a, a first main electrode provided on the lower surface side is joined to the upper surface of the heat spreader 4a2 with a brazing material (not shown) such as solder, and a second main electrode provided on the upper surface side is bonded to the upper surface of the heat spreader 4a2. , is bonded to the lower surface of an electrode plate 4b1 (second electrode plate) disposed above the heat spreader 4a2 (second heat spreader) with a brazing material (not shown) such as solder.

Furthermore, a heat spreader 4b2 on which the power semiconductor element 1b is mounted is arranged below the electrode plate 4a1. In the power semiconductor element 1b, a first main electrode provided on the lower surface side is joined to the upper surface of the heat spreader 4b2 with a brazing material (not shown) such as solder, and a second main electrode provided on the upper surface side is bonded to the upper surface of the heat spreader 4b2. , is bonded to the lower surface of the electrode plate 4a1 with a brazing material (not shown) such as solder.

The heat spreader 4a2 and the heat spreader 4b2 are arranged in parallel in a plan view, and there is no step between them. On the other hand, the electrode plate 4b1 and the heat spreader 4b2 are arranged in parallel in a plan view, but the electrode plate 4b1 is located at a higher position and the heat spreader 4b2 is located at a lower position, and there is a step between them. Existing.

The electrode plate 4b1 has a rectangular shape in plan view, and a main terminal plate T2 is joined to one end thereof, and the main terminal plate T2 protrudes to the outside of the molded resin RG. Note that one end to which the main terminal plate T2 is joined is opposite to the end on which the power semiconductor element 1a of the heat spreader 4a2 is mounted. Further, a bent portion BP2 is provided at one end of the electrode plate 4b1. The bent portion BP2 has an inclination that is higher on the electrode plate 4b1 side and lower on the main terminal plate T2 side. As a result, a step exists between the electrode plate 4b1 and the heat spreader 4b2.

The heat spreader 4a2 has a rectangular shape in plan view, the power semiconductor element 1a is mounted on one end, and is connected to the relay terminal RT1 via the wire WR, and the relay terminal RT1 protrudes to the outside of the molded resin RG. ing.

The heat spreader 4b2 has a rectangular shape in plan view, and a main terminal plate T3 is joined to one end thereof, and the main terminal plate T3 protrudes to the outside of the molded resin RG. Note that one end to which the main terminal plate T3 is joined is on the same side as the end on which the power semiconductor element 1b is mounted. Power semiconductor element 1b is connected to relay terminal RT2 via wire WR, and relay terminal RT2 protrudes to the outside of mold resin RG.

The electrode plate 4a1 has a rectangular shape in plan view, and a main terminal plate T1 is joined to one end thereof, and the main terminal plate T1 protrudes to the outside of the molded resin RG. Note that one end to which the main terminal plate T1 is joined is opposite to the end on which the power semiconductor element 1b of the heat spreader 4b2 is mounted.

As explained above, the single-phase inverter 100 shown in FIG. 1 has a step between the heat spreader 4a2 and the electrode plate 4a1, a step between the electrode plate 4b1 and the heat spreader 4b2, and By arranging the power semiconductor element 1a between the heat spreader 4a2 and the electrode plate 4b1, and arranging the power semiconductor element 1b between the heat spreader 4b2 and the electrode plate 4a1, the power semiconductor element 1a and the power semiconductor element 1b can be connected in series. Can be connected.

Next, a method for manufacturing the main parts of the single-phase inverter 100 will be explained using FIGS. 2 to 6. 2 and 3 are plan views showing a frame 4b and a frame 4a, respectively, for manufacturing the single-phase inverter 100, and FIG. 4 is a plan view showing a frame 4a (first frame) and a frame 4b (second frame). FIG. 3 is a plan view showing a state in which the

As shown in FIG. 2, the frame 4b includes a frame body 4b0 that defines the outline of the frame 4b, an electrode plate 4b1, and a heat spreader 4b2. The frame body 4b0 is a frame having a rectangular shape in plan view, and an electrode plate 4b1 and a heat spreader 4b2 are provided to extend inward from one side of the frame body 4b0. The electrode plate 4b1 and the heat spreader 4b2 are arranged parallel to each other with a gap between them in plan view, and a bent portion BP2 is provided at one end of the electrode plate 4b1. The bent portion BP2 has an inclination that is high on one end side and low on the frame main body 4b0 side. As a result, a step exists between the electrode plate 4b1 and the heat spreader 4b2.

The heat spreader 4b2 is equipped with the power semiconductor element 1b and the power semiconductor element 11b, and the end portion on the side where the power semiconductor element 1b is mounted has a partially narrow width and is integrated with the frame body 4b0. .

As shown in FIG. 3, the frame 4a includes a frame body 4a0 that defines the outline of the frame 4a, an electrode plate 4a1, and a heat spreader 4a2. The frame body 4a0 is a frame having a rectangular shape in plan view, and an electrode plate 4a1 is provided so as to extend inward from one side of the frame body 4a0. The electrode plate 4a1 is connected to a heat spreader 4a2, which is arranged in parallel in a plan view, at a bent portion BP1.

The bent portion BP1 has a slope that is higher on the electrode plate 4a1 side and lower on the heat spreader 4a2 side. Therefore, a step exists between the heat spreader 4a2 and the electrode plate 4a1. The heat spreader 4a2 is equipped with a power semiconductor element 1a and a power semiconductor element 11a. Note that the

frames

4a and 4b can be formed of aluminum (Al) or copper (Cu).

As shown in FIGS. 2 and 3, one side of the frame main body 4b0 on which the electrode plate 4b1 and the heat spreader 4b2 of the frame 4b extend and one side on which the electrode plate 4a1 of the frame 4a extends have an opposing positional relationship. When the frame 4b and the frame 4a are arranged so as to overlap each other, a configuration as shown in FIG. 4 is obtained.

FIG. 4 shows the configuration of a region sealed with mold resin RG of the single-phase inverter 100 shown in FIG. 1, in which

power semiconductor elements

1a and 11a are arranged between a heat spreader 4a2 and an electrode plate 4b1,

Power semiconductor elements

1b and 11b are arranged between heat spreader 4b2 and electrode plate 4a1.

A cross-sectional view taken along line AA in FIG. 4 in the direction of the arrow is shown in FIG. 5, and a cross-sectional view taken along line BB in the direction of the arrow is shown in FIG.

As shown in FIG. 5, the

power semiconductor elements

1a and 11a are joined to the heat spreader 4a2 by a brazing material 2a, and the upper electrode plate 4b1 is joined by a brazing material (first brazing material).

Further, as shown in FIG. 6, the

power semiconductor elements

1b and 11b are bonded to a heat spreader 4b2 by a brazing material 2b, and the upper electrode plate 4a1 is bonded to a brazing material 3b (second brazing material). Ru. For example, solder can be used as the

brazing materials

2a, 3a, 2b, and 3b.

As explained above, the frame 4a is provided with the electrode plate 4a1 and the heat spreader 4a2, the frame 4b is provided with the electrode plate 4b1 and the heat spreader 4b2, and by arranging the

frames

4a and 4b so as to overlap, the heat spreader and There is no need to provide a separate electrode plate, and the number of parts can be reduced. Furthermore, since the

brazing materials

3a and 3b are joined with the

frames

4a and 4b stacked on top of each other, the number of manufacturing steps can be reduced.

Additionally, since the frame shape can be freely designed, the degree of freedom in inductance design increases. Moreover, heat dissipation can also be improved.

Furthermore, by making the outer shapes defined by the frame main body 4a0 of the frame 4a and the frame main body 4b0 of the frame 4b the same size, it becomes easy to align the frames when overlapping them, and the alignment accuracy is also improved.

Here, as for the types of the

power semiconductor elements

1a and 11a, for example, the power semiconductor element 1a is an IGBT, the power semiconductor element 11a is a high voltage diode, and the power semiconductor element 11a is connected in antiparallel to the power semiconductor element 1a. shall be taken as a thing.

Further, as the types of the

power semiconductor elements

1b and 11b, for example, the power semiconductor element 1b is an IGBT, the power semiconductor element 11b is a high voltage diode, and the power semiconductor element 11b is connected in antiparallel to the power semiconductor element 1b. shall be.

By connecting the power semiconductor element 1b and the power semiconductor element 1a in series, the

power semiconductor elements

11b and 11a can configure an inverter that operates as a free wheeling diode.

<Embodiment 2>
Next, a second embodiment of the present disclosure will be described using FIGS. 7 and 8. FIG. 7 is a plan view showing a state in which frames 4b and 4a are overlapped, and FIG. 8 is a plan view showing a state in which frames 4a and 4b are combined. Main parts of a phase inverter 200 are shown.

In FIG. 7, the frame 4b has the same shape as the first embodiment shown in FIG. Rather than being provided along the electrode plate 4a1, it is provided so as to connect a part of one long side with a part of one long side of the electrode plate 4a1. Therefore, it can be said that the bent portion BP1 is provided so as to form a slit between the electrode plate four a1 and the heat spreader four a2.

As shown in FIG. 8, by forming a slit between the electrode plate 4a1 and the heat spreader 4a2, it becomes possible to utilize the gap between the heat spreader 4b2 and the heat spreader 4a2.

FIG. 9 is a schematic cross-sectional view of the single-phase inverter 200 configured by combining the frame 4a and the frame 4b shown in FIG. Corresponds to a directional cross-sectional view.

In FIG. 8, cooling fins 6 are attached to the single-phase inverter 200 resin-sealed with mold resin RG, but by forming slits between the electrode plate 4a1 and the heat spreader 4a2, the electrode plate 4b1 and A through hole TH penetrating the mold resin RG in the thickness direction can be provided between the electrode plate four a1 and between the heat spreader four a2 and the heat spreader four b2. The single-phase inverter 200 can be attached to the cooling fins 6 by passing the screws 7 through the through holes TH. In this way, in the single-phase inverter 200, the threading position of the screw 7 can be secured.

<Embodiment 3>
Next, Embodiment 3 according to the present disclosure will be described using FIGS. 10 and 11. FIG. 10 is a plan view showing a state in which frames 4b and 4a are being overlapped, and FIG. 11 is a plan view showing a state in which frames 4a and 4b are combined. Main parts of phase inverter 300 are shown.

In FIG. 10, the frame 4b has the same shape as the first embodiment shown in FIG. Rather than being provided along the electrode plate 4a1, it is provided so as to connect two portions separated from each other on one long side and two portions separated from each other on one long side of the electrode plate 4a1. Therefore, it can be said that the bent portion BP1 is provided so as to form an opening between the electrode plate four a1 and the heat spreader four a2.

As shown in FIG. 11, by forming an opening between the electrode plate 4a1 and the heat spreader 4a2, it becomes possible to utilize the gap between the heat spreader 4b2 and the heat spreader 4a2.

As explained using FIG. 9 in Embodiment 2, the mode of use is the screw insertion position when attaching the cooling fin to the single-phase inverter 300. Moreover, compared to the case where a slit is formed between the electrode plate 4a1 and the heat spreader 4a2, the engagement between the electrode plate 4a1 and the heat spreader 4a2 becomes stronger, and the shape of the electrode plate 4a1 can be stabilized.

<Embodiment 4>
Next, a fourth embodiment of the present disclosure will be described using FIGS. 12 to 16. 12 and 13 are plan views showing a frame 4b and a frame 4a, respectively, for manufacturing the single-phase inverter 400 of the fourth embodiment, and FIG. 14 shows a state in which the frame 4a and the frame 4b are combined. 3 is a plan view showing main parts of a single-phase inverter 400 according to a fourth embodiment. FIG. Note that in FIGS. 12 to 16, the same components as those in FIGS. 2 to 6 of the first embodiment are denoted by the same reference numerals, and redundant explanations will be omitted.

As shown in FIG. 12, the frame 4b includes a frame main body 4b0 that defines the outline of the frame 4b, an electrode plate 4b1, a heat spreader 4b2, and a relay terminal 4b3 (second relay terminal).

The frame body 4b0 is a frame having a rectangular shape in plan view, and an electrode plate 4b1, a heat spreader 4b2, and a plurality of relay terminals 4b3 are provided so as to extend inward from one side thereof. A terminal hole 4bh is provided at one end of the electrode plate 4b1 at a position closer to the frame body 4b0 than the bent portion BP2. Further, the end of the heat spreader 4b2 on the side where the power semiconductor element 1b is mounted has a partially narrow width and is integrated with the frame body 4b0, and a terminal hole 4bh is provided at a position on the frame body 4b0 side. It is being The portion provided with the terminal hole 4bh functions as a so-called main terminal of the single-phase inverter 400, and the terminal hole 4bh functions as a mounting hole for connecting wiring with the outside. The plurality of relay terminals 4b3 extend to the vicinity of the power semiconductor element 1b on the heat spreader 4b2 in plan view.

As shown in FIG. 13, the frame 4a includes a frame main body 4a0 that defines the outline of the frame 4a, an electrode plate 4a1, a heat spreader 4a2, and a plurality of relay terminals 4a3 (first relay terminals).

The frame body 4a0 is a frame having a rectangular shape in plan view, and an electrode plate 4a1 and a plurality of relay terminals 4a3 are provided to extend inward from one side of the frame body 4a0. A terminal hole 4ah is provided at one end of the electrode plate 4a1 at a position on the frame body 4a0 side. The portion provided with the terminal hole 4ah functions as a so-called main terminal of the single-phase inverter 400, and the terminal hole 4ah functions as a mounting hole for connecting wiring to the outside. The plurality of relay terminals 4b3 extend to the vicinity of the power semiconductor element 1a on the heat spreader 4a2 in plan view. The plurality of relay terminals 4a3 function as terminals for wire connection with the control terminals on the upper surface of the power semiconductor element 1a.

As shown in FIGS. 12 and 13, one side of the frame body 4b0 on which the electrode plate 4b1, the heat spreader 4b2, and the plurality of relay terminals 4b3 of the frame 4b extend, and the electrode plate 4a1 and the plurality of relay terminals 4a3 of the frame 4a extend. The extending sides have a positional relationship that opposes each other, and when the frame 4b and the frame 4a are arranged so as to overlap, a configuration as shown in FIG. 14 is obtained.

FIG. 14 shows the configuration of a region sealed with mold resin RG of the single-phase inverter 100 shown in FIG. 1, in which

power semiconductor elements

1a and 11a are arranged between a heat spreader 4a2 and an electrode plate 4b1,

Power semiconductor elements

1b and 11b are arranged between heat spreader 4b2 and electrode plate 4a1.

FIG. 15 shows a sectional view taken along the line AA in FIG. 14 in the direction of the arrow, and FIG. 16 shows a sectional view taken along the line BB in the direction of the arrow.

As shown in FIG. 15, the

power semiconductor elements

1a and 11a are joined to the heat spreader 4a2 by a brazing material 2a, and the upper electrode plate 4b1 is joined by a brazing material 3a.

Further, as shown in FIG. 16, the

power semiconductor elements

1b and 11b are bonded to the heat spreader 4b2 by a brazing material 2b, and the upper electrode plate 4a1 is bonded to the brazing material 3b.

As explained above, the frame 4a is provided with a plurality of relay terminals 4a3 and a portion that functions as a main terminal, and the frame 4b is provided with a plurality of relay terminals 4b3 and a portion that functions as a main terminal. The number of parts required for assembling inverter 400 can be reduced, and productivity can be improved.

Further, as shown in FIG. 12, the frame 4b has a configuration in which the plurality of relay terminals 4b3 extend to the vicinity of the power semiconductor element 1b on the heat spreader 4b2 in plan view. By using the power semiconductor element 1b near the terminal 4b3 as an IGBT or MOSFET, and using the plurality of relay terminals 4b3 as terminals for wire bonding with the control terminal of the IGBT or MOSFET, wire bonding becomes easy and productivity is increased. can be improved. Note that the power semiconductor element 11b is a high voltage diode.

Similarly, as shown in FIG. 13, the frame 4a has a configuration in which the plurality of relay terminals 4a3 extend to the vicinity of the power semiconductor element 1a on the heat spreader 4a2 in plan view; By using the power semiconductor element 1a near the relay terminal 4a3 as an IGBT or MOSFET, and using the plurality of relay terminals 4a3 as terminals for wire bonding with the control terminal of the IGBT or MOSFET, wire bonding becomes easy and productivity is increased. can be improved. Note that the power semiconductor element 11b is a high voltage diode.

<Embodiment 5>
Next, Embodiment 5 according to the present disclosure will be described using FIGS. 17 and 18. FIG. 17 is a cross-sectional view showing the cross-sectional configuration of a heat spreader 4a2 constituting a single-phase inverter 500 according to the fifth embodiment. Grooves for positioning the

power semiconductor elements

1a and 11a are formed on the mounting surface of the semiconductor elements of the heat spreader 4a2. A GR (first groove) is provided.

The groove GR is formed to have a depth and size that prevents the

power semiconductor elements

1a and 11a placed on the brazing material 2a from shifting from above the brazing material 2a. The groove GR is provided in a direction perpendicular to the arrangement direction of the

power semiconductor elements

1a and 11a, and has a depth capable of accommodating the brazing filler metal 2a and also a portion of the

power semiconductor elements

1a and 11a.

By providing the groove GR, the positioning accuracy when arranging the

power semiconductor elements

1a and 11a on the brazing material 2a is improved, and it is possible to prevent the

power semiconductor elements

1a and 11a from shifting from the brazing material 2a. can.

Although FIG. 17 shows an example in which the heat spreader 4a2 is provided with the groove GR, the heat spreader 4b2 is also provided with the groove GR (second groove) to improve the positioning accuracy of the

power semiconductor elements

1b and 11b and to improve the positioning accuracy of the power semiconductor elements. 1b and 11b can be prevented from shifting.

FIG. 18 is a cross-sectional view showing a configuration in which a protrusion PJ is provided in place of the groove GR on the mounting surface of the semiconductor element of the heat spreader 4a2. As shown in FIG. 18, the protrusion PJ is formed at a height that prevents the

power semiconductor elements

1a and 11a placed on the brazing material 2a from shifting from above the brazing material 2a. The protrusion PJ is provided on the outside of each of the

power semiconductor elements

1a and 11a in a plan view, and has a height that exceeds the thickness of the brazing filler metal 2a and extends to a part of the thickness of the

power semiconductor elements

1a and 11a. In addition. In FIG. 18, the protrusions PJ are provided at the front and rear of each of the

power semiconductor elements

1a and 11a, but they can also be provided at the left and right sides of each of the

power semiconductor elements

1a and 11a, and they can also be provided at the front and rear, left and right sides.

Providing the protrusion PJ improves the positioning accuracy when arranging the

power semiconductor elements

1a and 11a on the brazing material 2a, and prevents the

power semiconductor elements

1a and 11a from shifting from the brazing material 2a. Can be done.

Although FIG. 18 shows an example in which the heat spreader 4a2 is provided with the protrusion PJ, the heat spreader 4b2 is also provided with the protrusion PJ to improve the positioning accuracy of the

power semiconductor elements

1b and 11b and to improve the positioning accuracy of the

power semiconductor elements

1b and 11b. It can prevent slippage.

<Embodiment 6>
Next, as a sixth embodiment of the present disclosure, a method for manufacturing the single-phase inverter 100 shown in FIG. 1 will be described using FIGS. 20 to 24 while referring to the flowchart shown in FIG. 19.

A frame is molded in step S1 shown in FIG. This is a step of preparing

frames

4a and 4b, as shown in FIG. 20, and frames 4a and 4b are formed by punching and bending.

Frames

4a and 4b shown in FIG. 20 are in a state before power semiconductor elements are mounted on frame 4a shown in FIG. 3 and frame 4b shown in FIG. 2, respectively.

Next, in step S2, the power semiconductor element is bonded to the heat spreader using a brazing material. As shown in FIG. 21,

power semiconductor elements

1a and 11a are bonded to a heat spreader 4a2 of a frame 4a via a brazing material 2a (not shown), and

power semiconductor elements

1b and 11b are bonded to a heat spreader 4b2 of a frame 4b. This is a process of joining through a brazing filler metal 2b (not shown), and is a process of melting the brazing filler metal. Note that the

frames

4a and 4b shown in 21 are in the state of the frame 4a shown in FIG. 3 and the frame 4b shown in FIG. A brazing material 3b is placed on the

power semiconductor elements

1b and 11b for the next process.

Next, in step S3, the two frames are overlapped and the electrode plates are joined using the brazing material on the power semiconductor element. As shown in FIG. 22, this is done by overlapping

frames

4a and 4b and joining the brazing material 3a (not shown) on the

power semiconductor elements

1a and 11a of frame 4a to the electrode plate 4b1 of frame 4b. This is a step of joining the brazing material 3b (not shown) on the

power semiconductor elements

1b and 11b of the frame 4b and the electrode plate 4a1 of the frame 4a, and is a step of melting the brazing material. Note that the state in which the

frames

4a and 4b shown in FIG. 22 are superimposed corresponds to the state shown in FIG. 4.

Next, in step S4, the main terminal board and the external frame provided with the relay terminals are joined. This is a process of joining the external frame OF to the

frames

4a and 4b in which the power semiconductor element and the electrode plate have been joined, as shown in FIG. 23.

The external frame OF is joined to the superimposed

frames

4a and 4b so as to be further superimposed, and includes a frame main body OF0 defining the outline of the external frame OF, main terminal plates T1, T2, and T3, and a relay. It is configured with terminals RT1 and RT2.

The frame body OF0 is a frame having a rectangular shape in plan view, and the main terminal plate T1 and the relay terminal RT1 are provided so as to extend inward from one side thereof. The main terminal plate T1 is provided at a position to be joined to the end of the electrode plate 4a1, and the relay terminal RT1 is provided at a position facing the power semiconductor element 1a.

Further, the main terminal plates T2, T3 and the relay terminal RT2 are provided so as to extend inward from one side of the frame body OF0 opposite to the side on which the main terminal plate T1 and the relay terminal RT1 extend. There is. The main terminal plate T2 is provided at a position where it is joined to the end of the electrode plate 4b1, the main terminal board T3 is provided at a position where it is joined to the end of the heat spreader 4b2, and the relay terminal RT2 is connected to the power semiconductor element 1b. It is located opposite to the

Note that ultrasonic (US) bonding can be used to bond the external frame OF and the

frames

4a and 4b. Furthermore, joining via a brazing material can also be used.

Next, in step S5, the relay terminal and the power semiconductor element are connected by wire bonding. This is a step in which the relay terminal RT1 and the control terminal of the power semiconductor element 1a are connected by a wire WR, and the relay terminal RT2 and the control terminal of the power semiconductor element 1b are connected by a wire WR, as shown in FIG. .

After this, unnecessary parts of the frame body OF0 and frame bodies 4a0 and 4b0 are cut, and the main parts of the single-phase inverter 100 are sealed with mold resin RG, thereby obtaining the single-phase inverter 100 shown in FIG. 1.

<Embodiment 7>
Next, Embodiment 7 according to the present disclosure will be described using FIGS. 25 and 26. FIG. 25 is a plan view showing a state where

frames

4b and 4a are being overlapped, and FIG. 26 is a plan view showing a state where

frames

4a and 4b are combined. Main parts of a phase inverter 600 are shown.

In FIG. 25, the frame 4b has the same shape as the first embodiment shown in FIG. 2, but the frame 4a has a notch NP in which a part of the frame body 4a0 is cut out. The notch NP is provided at a position where the end of the electrode plate 4b1 of the frame 4b engages with the frame body 4a0 when the frame 4a and the frame 4b are combined. Therefore, when the frame 4a and the frame 4b are overlapped and joined together, the end portions of the frame main body 4a0 and the electrode plate 4b1 do not overlap, which facilitates joining.

<Embodiment 8>
Next, Embodiment 8 according to the present disclosure will be described using FIGS. 27 and 28. FIG. 27 is a plan view showing a state in which frames 4b and 4a are being overlapped, and FIG. 28 is a plan view showing a state in which frames 4a and 4b are combined.

As shown in FIG. 27, the frame main body 4b0 of the frame 4b has convex portions CV on two sides in the left and right direction parallel to the arrangement of the electrode plate 4b1 and the heat spreader 4b2. The convex portions CV are provided at four corner portions of the frame main body 4b0, and protrude toward the side where the frame 4a is overlapped.

On the other hand, as shown in FIG. 27, the frame main body 4a0 of the frame 4a has openings OP on two sides in the left-right direction parallel to the arrangement of the electrode plate 4a1 and the heat spreader 4a2. The openings OP are provided at four corners of the frame main body 4a0, and as shown in FIG. 28, the convex portions CV are inserted into the openings OP when the frame 4a is stacked on the frame 4b. It is set in. Therefore, the positioning accuracy when overlapping the

frames

4a and 4b is improved.

<Embodiment 9>
Next, a ninth embodiment of the present disclosure will be described using FIGS. 29 and 30. FIG. 29 is a plan view showing a state in which frames 4b and 4a are being overlapped, and FIG. 30 is a plan view showing a state in which frames 4a and 4b are combined.

As shown in FIG. 29, the frame main body 4b0 of the frame 4b has a plurality of dimples DP2 (second dimples) on two sides in the left-right direction parallel to the arrangement of the electrode plate 4b1 and the heat spreader 4b2. The plurality of dimples DP2 are provided in one row along the extending direction of each side on the two sides in the left-right direction.

Similarly, the frame main body 4a0 of the frame 4a also has a plurality of dimples DP1 (first dimples) on two sides in the left and right direction parallel to the arrangement of the electrode plate 4a1 and the heat spreader 4a2. The plurality of dimples DP1 are provided in one row along the extending direction of each side on the two sides in the left-right direction.

The plurality of dimples DP1 and DP2 of the

frames

4a and 4b are provided so as to be recessed in the same direction at the positions where they overlap with each other, as shown in FIG. 30, when the frame 4a is stacked on the frame 4b. Therefore, the positioning accuracy when overlapping the

frames

4a and 4b is improved.

<Embodiment 10>
Next, Embodiment 10 according to the present disclosure will be described using FIGS. 31 and 32. FIG. 31 is a sectional view illustrating a state in which frames 4a and 4b are overlapped and electrode plates are bonded using a brazing material on a power semiconductor element, and is a sectional view corresponding to FIG. 5 described in Embodiment 1. This is a diagram illustrating an improvement in step S3 of the flowchart shown in FIG. 19 in the sixth embodiment.

As shown in FIG. 31, the overlapping

frames

4a and 4b are fixed by the fixing jig JG, and the step of melting the brazing material is carried out. The fixing jig JG is a lower fixing jig JD arranged below the superimposed

frames

4a and 4b, that is, on the heat spreader 4a2 side, and the lower fixing jig JD is arranged above the superimposed

frames

4a and 4b, that is, on the electrode plate 4b1 side. It consists of an upper fixing jig JU.

As shown in FIG. 31, by sandwiching the overlapping

frames

4a and 4b between the lower fixing jig JD and the upper fixing jig JU, the

frames

4a and 4b are prevented from shifting when the brazing material is melted. At the same time, the positioning accuracy of the electrode plate is improved.

Although FIG. 31 shows a configuration in which the entire

superimposed frames

4a and 4b are sandwiched between the fixing jigs JG, the structure is not limited to this, and a configuration in which only part of the frames is sandwiched is also possible.

FIG. 32 is a plan view showing a fixing jig JG that holds only part of the frame. FIG. 32 shows a configuration in which the left and right frame bodies of the superimposed

frames

4a and 4b are sandwiched between a lower fixing jig JD and an upper fixing jig JU. The upper fixing jig JU is arranged only on the left and right frame bodies of the superimposed

frames

4a and 4b. When such a fixing jig JG is used, it is also possible to proceed to the next wire bonding step with the overlapping

frames

4a and 4b sandwiched between the fixing jig JG.

Note that the material of the fixing jig JG includes carbon, which can withstand the temperature during melting of the brazing filler metal and has little deformation.

<Semiconductor materials for power semiconductor devices>
The

power semiconductor devices

1a, 1b, 11a and 11b are not limited to silicon semiconductor devices using silicon (Si), but include silicon carbide semiconductor devices using silicon carbide (SiC) and gallium nitride using gallium nitride (GaN). Wide bandgap semiconductor devices such as semiconductor devices can be used. Compared to silicon semiconductor devices, wide bandgap semiconductor devices can be made smaller, have superior voltage resistance, have a higher allowable current density, and have high heat resistance, so they can operate at high temperatures and are expected to be highly efficient. .

<Modified example>
In the first to tenth embodiments described above, the present disclosure is applied to a single-phase inverter, but the present disclosure is not limited to this, and the present disclosure can also be applied to a three-phase inverter that combines three phases of a single-phase inverter. , it can also be applied to converters for power regeneration.

Note that within the scope of the disclosure, the embodiments of the present disclosure can be freely combined, or the embodiments can be modified or omitted as appropriate.

Although the present disclosure has been described in detail, the above description is illustrative in all aspects, and this disclosure is not limited thereto. It is understood that countless variations not illustrated can be envisioned without departing from the scope of this disclosure.

Claims

a first heat spreader mounting a first semiconductor element;
The first heat spreader includes a first electrode plate connected to the first heat spreader by a bent portion having an inclination;
a second heat spreader mounting a second semiconductor element;
The second heat spreader includes a second electrode plate provided with a step,
the first electrode plate is located at a higher position than the first heat spreader,
the second electrode plate is arranged at a higher position than the second heat spreader,
the first electrode plate and the second electrode plate are arranged at the same height,
the first heat spreader and the second heat spreader are arranged at the same height;
the second electrode plate is arranged above the first heat spreader,
the first electrode plate is arranged above the second heat spreader,
the first semiconductor element is joined to the first heat spreader and the second electrode plate,
In the semiconductor device, the second semiconductor element is joined to the second heat spreader and the first electrode plate.
The first heat spreader and the first electrode plate are in a parallel positional relationship in a plan view, and the bent portion extends along the entire side of the first heat spreader facing the first electrode plate. The semiconductor device according to claim 1 , wherein the semiconductor device is provided with a semiconductor device.
The first heat spreader and the first electrode plate are in a parallel positional relationship in a plan view, and the bent portion is provided on a part of one side of the first heat spreader facing the first electrode plate. 2. The semiconductor device according to claim 1, wherein a slit is formed between the first heat spreader and the first electrode plate.
The first heat spreader and the first electrode plate are in a parallel positional relationship in a plan view, and the bent portion is located at a second portion of the first heat spreader that is spaced apart from one another on one side facing the first electrode plate. 2. The semiconductor device according to claim 1, wherein an opening is provided in a first portion and a second portion, and an opening is formed between the first heat spreader and the first electrode plate.
The first heat spreader and the first electrode plate are in a parallel positional relationship in a plan view, and further includes a plurality of first relay terminals provided in parallel to the first heat spreader in a plan view. ,
The first semiconductor element is arranged on the first heat spreader at a position closer to the plurality of first relay terminals,
The second heat spreader and the second electrode plate are in a parallel positional relationship in a plan view, and further includes a plurality of second relay terminals provided in parallel to the second heat spreader in a plan view. ,
2. The semiconductor device according to claim 1, wherein the second semiconductor element is arranged on the second heat spreader at a position closer to the plurality of second relay terminals.
The semiconductor device according to claim 5, wherein the first and second semiconductor elements are IGBTs or MOSFETs.
The first heat spreader is
having a first groove matching the size of the first semiconductor element in a plan view in a portion where the first semiconductor element is mounted;
The second heat spreader is
2. The semiconductor device according to claim 1, wherein a portion on which the second semiconductor element is mounted has a second groove that matches the size of the second semiconductor element in a plan view.
The first heat spreader is
A portion on which the first semiconductor element is mounted has a plurality of first protrusions provided at positions outside the first semiconductor element in a plan view,
The second heat spreader is
2. The semiconductor device according to claim 1, wherein the portion on which the second semiconductor element is mounted has a plurality of second protrusions provided at positions outside the first semiconductor element in plan view.
The semiconductor device according to claim 1, wherein the first semiconductor element is a silicon carbide semiconductor element.
a first heat spreader to which a first semiconductor element is bonded;
a first frame having a first electrode plate connected to the first heat spreader by an inclined bent portion;
A semiconductor device using a second frame having a second heat spreader to which a second semiconductor element is bonded, and a second electrode plate provided with a step on the second heat spreader. A manufacturing method,
the first electrode plate is located at a higher position than the first heat spreader,
the second electrode plate is arranged at a higher position than the second heat spreader,
the first electrode plate and the second electrode plate are arranged at the same height,
the first heat spreader and the second heat spreader are arranged at the same height;
the second electrode plate is arranged above the first heat spreader,
the first electrode plate is arranged above the second heat spreader,
(a) The first semiconductor element is sandwiched between the first heat spreader and the second electrode plate, and the second semiconductor element is sandwiched between the second heat spreader and the first electrode plate. overlapping the first frame and the second frame so as to be sandwiched between them;
(b) a first brazing material disposed between the first semiconductor element and the second electrode plate; and a second brazing material disposed between the second semiconductor element and the first electrode plate. melting a brazing material, joining the first semiconductor element to the second electrode plate, and joining the second semiconductor element to the first electrode plate. Method of manufacturing the device.
The first frame is
11. The method of manufacturing a semiconductor device according to claim 10, further comprising a cutout portion in a portion that contacts the second electrode plate when the first frame and the second frame are overlapped.
The second frame has a plurality of protrusions,
The first frame is
a plurality of openings provided at positions corresponding to the plurality of convex portions of the second frame;
The step (a) includes:
11. The method of manufacturing a semiconductor device according to claim 10, wherein the first frame and the second frame are overlapped so that the plurality of convex portions are inserted into the plurality of openings.
the second frame has a plurality of second dimples;
The first frame includes:
The second frame has a plurality of first dimples provided at positions corresponding to the plurality of second dimples, and the step (a)
The method for manufacturing a semiconductor device according to claim 10 , further comprising overlapping said first frame and said second frame so that said plurality of first dimples and said plurality of second dimples overlap each other.
The step (b) includes:
11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of pressing the top and bottom of the superimposed first and second frames using a fixing jig.
The first and second frames are
11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor devices have the same external size.