WO2024055141A1

WO2024055141A1 - Semiconductor testing device and method of operating semiconductor testing device

Info

Publication number: WO2024055141A1
Application number: PCT/CN2022/118315
Authority: WO
Inventors: Hanping SUN; Yong Liu; Qiyue Zhao
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-09-13
Filing date: 2022-09-13
Publication date: 2024-03-21
Also published as: CN118076897A

Abstract

The present disclosure provides a semiconductor testing device to test a DUT and a method of operating the semiconductor testing device. The semiconductor testing device includes, a switching element, a sensing resistor, and a pulse generator. The DUT is formed monolithically on a semiconductor die substrate. The sensing resistor is configured to sense a drain source current of the DUT. The pulse generator is coupled to the DUT through a TGV terminal to apply a pulse voltage to the DUT. The semiconductor testing device may detect the drain source current of the DUT through a difference voltage detected across the sensing resistor, the difference voltage may be displayed on the oscilloscope through the differential probe, so the drain source voltage of the DUT at high frequency can be detected.

Description

SEMICONDUCTOR TESTING DEVICE AND METHOD OF OPERATING SEMICONDUCTOR TESTING DEVICE

Field of the Invention:

The present invention generally relates to semiconductor testing device, and more specifically, the present invention relates to current sensing semiconductor testing device for sensing current in a Gallium Nitride (GaN) switching device.

Background of the Invention:

GaN-based switching devices have been widely used for high frequency electrical energy conversion systems because of low power losses and fast switching transition. In comparison with silicon metal oxide semiconductor field effect transistor (MOSFET) , GaN high-electron-mobility transistor (HEMT) has a much better figure of merit and more promising performance for high-power and high-frequency applications.

Several architectures have been proposed to sense the current in a GaN switching device, for an example, the semiconductor testing device for current sensing uses a plurality of probes, a supply measurement unit (SMU) , and a controller to sense the current in the GaN switching device. The controller applies a pulse voltage to the GaN switching device to sense a drain source current (Ids) of the GaN switching device. However, the frequency limitation in the controller may not be suitable for high frequency current sensing in the GaN switching device.

For example, referring to FIG. 1 a block diagram of a conventional semiconductor testing device. The semiconductor testing device 100 used for sensing current in a GaN switching device. The semiconductor testing device 100 includes a semiconductor die substrate 110, a GaN switching device 120 and a controller 140.

The GaN switching device 120 is formed on the semiconductor die substrate 110. The GaN switching device 120 includes a drain D terminal, a source S terminal, and a through GaN via (TGV) terminal.

The controller 140 is a configured to apply a pulse output voltage to the GaN switching device 120 through the TGV terminal and sense a drain source current (Ids) flowing through the drain terminal and source terminal of the GaN switching device 120. The semiconductor testing device 100 uses a plurality of probes from the controller 140 to sense the current in the GaN switching device 120. It is noted that one probe (P1) is connected to the drain terminal and other probe (P2) is connected at the source terminal of the GaN switching device 120. One of the probe (P3) is coupled from the controller 140 and the TGV terminal.

The controller 140 is configured to applied the pulse output voltage at the TGV terminal in the range of 1KHz, and when the amplitude of the pulse is low, that is low pulse voltage, the GaN switching device 120 is turned off and there is no current flows between the drain terminal and the source terminal of the GaN switching device 120, that is Ids=0.

On the other hand, when the applied pulse is high, that is high pulse voltage, which is also in the range of 1KHz from the controller 140 to the TGV terminal, the GaN switching device 120 is turned on and makes the current flows between the drain terminal and the source terminal of the GaN switching device 120, thus the current flows in the GaN switching device 120 is measured.

Based on the above, it is noted that the controller 140 used to give the pulse is in the range of milliseconds. When the TGV terminal increases to a higher frequency, the drain source current (Ids) changes proportional to frequency and the controller 140 may not provide the pulse at the higher frequency, resulting in drain source current (Ids) measurement in the GaN switching device is not possible. On the other hand, when the drain source current (Ids) is small, considering the interference of a parasitic parameters, the controller 140 may not accurately measure the current in the GaN switching device 120.

Along with requirement of current sensing the GaN switching device at higher frequency, it could be desirable to develop the semiconductor testing device to sense the drain source current of the GaN switching device without compromising the accuracy of current sensing for certain applications in the field.

Summary of the Invention:

The semiconductor testing device to test a DUT of the invention includes, a switching element, a sensing resistor, and a pulse generator. The DUT is formed monolithically on the semiconductor die substrate. The sensing resistor is configured to sense a current of the DUT. The pulse generator is configured to generate a pulse output voltage to test the DUT. The pulse generator is coupled to the semiconductor die substrate through a TGV terminal to apply the pulse output voltage to the DUT. The semiconductor testing device is configured to detect a drain source current of the DUT through a difference voltage detected across the sensing resistor.

Based on the above, in the embodiments of the invention, the semiconductor testing device may detect the drain source current of the DUT through the difference voltage detected across the sensing resistor, the difference voltage may be displayed on the oscilloscope through the differential probe, so the drain source voltage of the DUT at high frequency can be detected.

Brief Description of the Drawings:

Aspects of the present disclosure may be readily understood from the following detailed description with reference to the accompanying figures. The illustrations may not necessarily be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Common reference numerals may be used throughout the drawings and the detailed description to indicate the same or similar components.

FIG. 1 illustrates a block diagram of a conventional semiconductor testing device.

FIG. 2 illustrates a circuit diagram of a semiconductor testing device according to an exemplary embodiment of the disclosure.

FIG. 3 illustrates a circuit diagram of a pulse generator according to an exemplary embodiment of the disclosure.

FIG. 4 illustrates a method of operating a semiconductor testing device according to an exemplary embodiment of the disclosure.

Detailed Description:

In the following description, preferred examples of the present disclosure will be set forth as embodiments which are to be regarded as illustrative rather than restrictive. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

It is to be understood that other embodiment may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including, ” “comprising, ” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless limited otherwise, the terms “connected, ” “coupled, ” and “mounted, ” and variations thereof herein are used broadly and encompass direct and indirect connections, couplings, and mountings.

FIG. 2 illustrates a circuit diagram of a semiconductor testing device according to an exemplary embodiment of the disclosure. Referring to FIG. 2, the semiconductor testing device 200 includes a switching element 230, a sensing resistor 240, a pulse generator 250, an operational amplifier 260, and a voltage source 270.

The semiconductor testing device 200 is a current sensing device. The semiconductor testing device 200 is configured to sense a current of a device under test (DUT) 220.

In one embodiment, the DUT 220 may be a GaN switching device 220.

In some embodiments, the DUT to be tested by the semiconductor testing device 200 may be a MOSFET device, a high electron mobility transistor (HEMT) device, and/or an IGBT device, thus the type of the DUT used in the semiconductor testing device 200 is not limited thereto.

In some embodiments, the GaN switching device 220 is formed monolithically on a semiconductor die substrate 210. The GaN switching device 220 may be an enhancement mode (e- GaN) and/or a cascaded depletion mode (d-GaN) . The GaN switching device 220 includes a drain terminal, a source terminal, and a TGV terminal. The TGV terminal may be connected to a gate of the GaN switching device 220. The drain terminal may be coupled to the sensing resistor 240 and the operational amplifier 260. The source terminal may be coupled to a ground potential.

In some embodiments, the switching element 230 may be a MOSFET device, a high electron mobility transistor (HEMT) device, and/or an IGBT device, thus the type of the switching element 230 used in the semiconductor testing device 200 is not limited thereto.

The switching element 230 may be GaN HEMT device.

The switching element 230 may be a complementary metal oxide semiconductor (CMOS) .

In some embodiments, the switching element 230 may be a NMOS transistor.

In some embodiments, the switching element 230 may be a PMOS transistor, thus the type of switching element 230 used in this embodiment is not limited thereto.

The switching element 230 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal of the switching element 230 is coupled to the voltage source 270. The source terminal of the switching element 230 is coupled to the sensing resistor 240. The gate terminal of the switching element 230 is coupled to the operational amplifier 260.

The sensing resistor 240 is a current sense resistor or shunt resistor used to gauge the flow of current in the DUT. The sensing resistor 240 may be designed for low resistance so as to minimize a power consumption of the semiconductor testing device 200. The sensing resistor 240 includes a first side and a second side. The first side of the sensing resistor 240 is coupled to a drain terminal of the GaN switching device 220 and the second side of the sensing resistor 240 is coupled to the source terminal of the switching element 230.

The semiconductor testing device 200 is configured to detect a drain source current (Ids) of the GaN switching device 220 through a difference voltage VR1 detected across the sensing resistor 240. The expression can be written as, VR1= Ids*R1. In other words, a magnification of the drain source current (Ids) of the GaN switching device 220 may be adjusted by adjusting the resistance value of the sensing resistor 240.

The difference voltage VR1 detected across the sensing resistor 240 is measured using the oscilloscope with a probe. The probe may be a differential probe and/or a current probe.

The pulse generator 250 is configured to generate a pulse output voltage to test the GaN switching device 220. In an example of GaN switching device 220 formed on the semiconductor die substrate 210 which is a GaN epi wafer, the vias through the GaN epi wafer may be referred to as a through GaN via (TGV) . The pulse generator 250 is coupled to the semiconductor die substrate 210 through the TGV terminal to apply a pulse output voltage VTGV to the GaN switching device 220.

The pulse generator 250 is configured to generate a first voltage and/or a second voltage to form the pulse output voltage VTGV. In one example, the first voltage of VTGV is a high level at 0V and the second voltage of VTGV is a low level at -200V. It is noted that, the first voltage and the second voltage are not generated at the same time, there is one voltage value generated at a time given as the pulse to the GaN switching device 220. The voltage value of the first voltage and the second voltage is not limited in this disclosure.

In one example, when the first voltage, which is 0V, is applied to the TGV through the semiconductor die substrate 210, the GaN switching device 220 is turned on and make the current flows between the drain terminal and the source terminal of the GaN switching device 220, which is referred to as Ids current of the GaN switching device 220.

In another example, when the second voltage, which is -200V, is applied to the TGV through the semiconductor substrate 210, the GaN switching device 220 is turned off and there is no current flowing between the drain terminal and the source terminal of the GaN switching device, 220, that is Ids=0.

The operational amplifier 260 is configured to drive the switching element 230. The operational amplifier 260 is a single ended differential amplifier. The operational amplifier 260 includes two input terminals and an output terminal. In that two input terminals, one is a positive input terminal and another is a negative input terminal.

In some embodiment, the operational amplifier 260 may be a cascaded amplifier to achieve high gain, high input impedance, low output impedance, and/or high phase margin for better stability.

The positive input terminal of the operational amplifier 260 is coupled to a reference voltage VREF, the negative input terminal is coupled to the drain terminal of the GaN switching device 220. The reference voltage VREF is generated by a reference voltage generator, not shown here. The reference voltage may be a positive voltage or a negative voltage. The output terminal of the operational amplifier 260 is coupled to the gate terminal of the switching element 230. The drain source current (Ids) may be adjusted by adjusting the reference voltage VREF.

The operational amplifier 260 is designed in a way to achieve a high input impedance and the low output impedance, close to the ideal operational amplifier to have a high gain.

When the first voltage, which is 0V, is applied to the TGV terminal of the GaN switching device 220, the GaN switching device 220 is turned on and makes the drain source current (Ids) current flow between the drain terminal and the source terminal of the GaN switching device 220. The switching element 230, the sensing resistor 240, the operational amplifier 260, and the GaN switching device 220 forms a negative feedback loop, which connects the drain terminal of the GaN switching device 220. During this operation, the voltage reference VREF is clamped since the input impedance of the operation amplifier 260 is large, the current flowing into the operational amplifier 260 from the drain of the GaN switching device 220 is small.

When the second voltage, which is -200V, is applied to the TGV through the semiconductor die substrate 210, the GaN switching device 220 is turned off and the negative feedback loop is open, therefore no current flows between drain terminal to source terminal of the GaN switching device 220, that is Ids=0.

The voltage source 270 is a DC voltage source. The voltage source 270 includes a positive terminal and a negative terminal. The positive terminal of the voltage source 270 is coupled to the drain terminal of the switching element 230 and the negative terminal of the voltage source 270 is coupled to the ground potential.

Based on the above configuration, the semiconductor testing device 200 may detect the drain source current (Ids) of the GaN switching device 220 through the difference voltage VR1 detected across the sensing resistor 240, the difference voltage VR1 may be displayed on the oscilloscope through the differential probe, so the drain source voltage (VDS) of the GaN switching device 220 at high frequency can be detected. Furthermore, the magnification of the drain source current (Ids) of the GaN switching device 220 can be adjusted by adjusting the sensing resistor 240, thereby accurately reading the magnitude of the drain source current (Ids) of the GaN switching device 220.

FIG. 3 illustrates a circuit diagram of a pulse generator according to an exemplary embodiment of the disclosure. Referring to FIG. 3, the pulse generator 300 includes a first high electron mobility transistor (HEMT) 310, a second high electron mobility transistor (HEMT) 320, a diode 330, a first resistor 340, a second resistor 350, a first capacitor 360, a second capacitor 370, a load capacitor 380, a load resistor 390, and a voltage source 395.

In some embodiments, the first HEMT transistor 310 and the second HEMT transistor 320 may be GaN HEMT devices.

With reference to FIG. 2, the pulse generator 300 is similar to the pulse generator 250. The pulse generator 300 is configured to generate a pulse output voltage to test the GaN switching device 220. The output of the pulse generator 300 is coupled to the semiconductor die substrate 210 through a TGV terminal.

The first HEMT transistor 310 includes a gate terminal, a drain terminal, and a source terminal.

The second HEMT transistor 320 includes a gate terminal, a drain terminal, and a source terminal. The first HEMT transistor 310 and the second HEMT transistor 320 are serially coupled.

The diode 330 includes a first side and a second side. The first side of the diode 330 is coupled to the source terminal of the first HEMT transistor 310 and the drain terminal of the second HEMT transistor 320. The second side of the diode 330 is coupled to the output of the pulse generator 300.

In one embodiment, the first side of the diode 330 is an anode and the second side of the diode 330 is a cathode.

The first resistor 340 includes a first side and a second side. The first side of the first resistor 340 is coupled to the drain terminal of the first HEMT transistor 310.

The second resistor 350 includes a first side and a second side. The first side of the second resistor 350 is coupled to the ground potential and the second side of the second resistor 350 is coupled to the source terminal of the second HEMT 320.

The first capacitor 360 includes a first side and a second side. The first side of the first capacitor 360 is coupled to the voltage source 395 and the first side of the first resistor 340. The second side of the first capacitor 360 is coupled to the second side of the first resistor 340.

The second capacitor 370 includes a first side and a second side. The first side of the second capacitor 370 is coupled to second side of the first capacitor 360. The second side of the second capacitor 370 is coupled to the ground potential. The first capacitor 360 and the second capacitor 370 are serially coupled.

The load capacitor 380 includes a first side and a second side. The first side of the load capacitor 380 is coupled to the output of the pulse generator 300. The second side of the load capacitor 380 is coupled to the ground potential.

The load resistor 390 includes a first side and a second side. The first side of the load resistor 390 is coupled to the output of the pulse generator 390. The second side of the load capacitor 390 is coupled to the ground potential.

The voltage source 395 is a DC voltage source. The voltage source 395 includes a positive terminal and a negative terminal. The positive terminal of the voltage source 395 is coupled to the first side of the first resistor 340, the first side of the first capacitor 360 and the drain terminal of the first HEMT transistor 310. The negative terminal of the voltage source 395 is coupled to the ground potential.

The resistance of the first resistor 340 and the resistance of the second resistor 350 are equal to divide an input voltage provided by the voltage source 395 of the pulse generator 300.

The first HEMT transistor 310 and the second HEMT transistor 320 are turned on alternately and forms a half-wave rectifier circuit with the diode 330.

The pulse generator 300 is configured to generate a first voltage and a second voltage to form the pulse voltage Vout (or VTGV) at the output. In one example, the first voltage is a high level at 0V and the second voltage is at low level at -200V. The voltage value of the first voltage and the second voltage is not limited in this disclosure.

With reference to FIG. 2, the first voltage is 0V and the second voltage is -200V. It is noted that, the first voltage and the second voltage are not generated at the same time, there is one voltage is generated at a time given as the pulse to the GaN switching device 220.

In one example, the pulse is a pulse width modulation (PWM) signal or a pulse duration modulation (PDM) signal from the pulse generator 300. The duty cycle, frequency, and the amplitude of the PWM signal is not limited in this disclosure.

When the first voltage, which is 0V, is applied to the TGV through the semiconductor die substrate 210, the GaN switching device 220 is turned on and make the current flow between the drain terminal and the source terminal of the GaN switching device 220.

When the second voltage, which is -200V, is applied to the TGV through the semiconductor substrate 210, the GaN switching device 220 is turned off and there is no current flowing between the drain terminal and the source terminal of the GaN switching device, 220, that is Ids=0.

FIG. 4 illustrates a method of operating a semiconductor testing device to test a DUT, the method includes generating a pulse output voltage to test the DUT by a pulse generator in step S410. To be specific with reference to FIG. 2 and FIG. 3, a pulse generator 250 is configured to generate the pulse output voltage to test a DUT 220. In step S420, sensing a difference voltage detected across a sensing resistor. With reference to FIG. 2, the sensing resistor 240 is a current sense resistor or shunt resistor used to gauge the flow of current in the DUT 220. The difference voltage VR1 detected across the sensing resistor 240 is measured using the oscilloscope with a probe. In step S430, detecting a drain source current of the DUT through the difference voltage detected across the sensing resistor. With reference to FIG. 2, the semiconductor testing device 200 is configured to detect a drain source current (Ids) of the DUT 220 through a difference voltage VR1 detected across the sensing resistor 240.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. While the apparatuses disclosed herein have been described with reference to particular structures, shapes, materials, composition of matter and relationships…etc., these descriptions and illustrations are not limiting. Modifications may be made to adapt a particular situation to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto.

Claims

A semiconductor testing device configured to test a DUT, the semiconductor testing device comprising:

a switching element, wherein the switching element comprises a source terminal, a drain terminal, and a gate terminal;

a sensing resistor, configured to sense a current of the DUT, wherein a first side of the sensing resistor is coupled to the DUT and a second side of the sensing resistor is coupled to the source terminal of the switching element; and

a pulse generator configured to generate a pulse output voltage to test the DUT,

wherein the DUT is formed monolithically on a semiconductor die substrate, the DUT comprising a drain terminal, a source terminal, and a gate terminal,

wherein the pulse generator is coupled to the semiconductor die substrate through a TGV to apply the pulse output voltage to the DUT, and

wherein the semiconductor testing device is configured to detect a drain source current of the DUT through a difference voltage detected across the sensing resistor.
The semiconductor testing device of claim 1, wherein the semiconductor testing device is configured to adjust the magnification of the drain source current of the DUT by adjusting a resistance value of the sensing resistor.
The semiconductor testing device of claim 1, further comprising:

an operational amplifier, configured to drive the switching element, wherein the switching element, the sensing resistor, the DUT, and the operational amplifier forms a negative feedback loop.
The semiconductor testing device of claim 3, wherein the operational amplifier is a single ended differential amplifier.
The semiconductor testing device of claim 3, the operational amplifier further comprises:

a positive input terminal, a negative input terminal, and an output terminal, wherein

the positive input terminal is coupled to a reference voltage,

the negative input terminal is coupled to the drain terminal of the DUT, and

the output terminal is coupled to the gate terminal of the switching element.
The semiconductor testing device of claim 1, wherein the DUT is a GaN switching device.
The semiconductor testing device of claim 1, wherein the pulse generator is configured to generate a first voltage and a second voltage to form the pulse output voltage.
The semiconductor testing device of claim 7, wherein when the first voltage is applied to the semiconductor die substrate through the TGV, the DUT is turned on and make the current flows between the source terminal and the drain terminal of the DUT.
The semiconductor testing device of claim 7, wherein when the second voltage is applied to the semiconductor die substrate through the TGV, the DUT is turned off and there is no current flowing between the source terminal and the drain terminal of the DUT.
The semiconductor testing device of claim 1, wherein the pulse generator comprises:

a first HEMT transistor, comprises a gate terminal, a drain terminal, and a source terminal;

a second HEMT transistor, comprises a gate terminal, a drain terminal, and a source terminal, wherein the first HEMT transistor and the second HEMT transistor are serially coupled;

a diode, coupled to the first HEMT transistor, the second HEMT transistor and an output of the pulse generator.

a first resistor, coupled to the drain terminal of the first HEMT transistor;

a second resistor, coupled to the source terminal of the HEMT transistor;

a first capacitor, coupled to the first resistor and the first HEMT transistor;

a second capacitor, coupled to the second resistor and the second HEMT transistor, wherein the first capacitor and the second capacitor are serially coupled;

a load resistor, coupled to the output of the pulse generator;

a load capacitor, coupled to the output of the pulse generator,

wherein a resistance of the first resistor and a resistance of the second resistor are equal to divide an input voltage of the pulse generator.
The semiconductor testing device of claim 10, wherein the first HEMT transistor and the second HEMT transistor are turned on alternately and forms a half-wave rectifier circuit with the diode.
The semiconductor testing device of claim 7, wherein the first voltage is a positive voltage and the second voltage is a negative voltage.
A method of operating a semiconductor testing device to test a DUT comprising:

generating a pulse output voltage to test the DUT by a pulse generator;

sensing a difference voltage detected across a sensing resistor; and

detecting a drain source current of the DUT through the difference voltage detected across the sensing resistor.
The method of claim 13, further comprising:

adjusting the magnification of the drain source current of the DUT by adjusting a resistance value of the sensing resistor.
The method of claim 13, further comprising:

generating a first voltage and a second voltage to form the pulse output voltage at an output of the pulse generator.
The method of claim 15, wherein when the first voltage is applied to the semiconductor die substrate through a TGV, turning on the DUT and make the current flows between a source terminal and a drain terminal of the DUT.
The method of claim 15, wherein when the second voltage is applied to the semiconductor die substrate through a TGV, turning off the DUT and there is no current flowing between a source terminal and a drain terminal of the DUT.
The method of claim 13, wherein the DUT is a GaN switching device.
The method of claim 15, wherein the first voltage is a positive voltage and the second voltage is a negative voltage.
A non-transitory computer readable medium storing a program causing a computer to execute a method of operating a semiconductor testing device to test a DUT, the method comprising:

generating a pulse output voltage to test the DUT by a pulse generator;

sensing a difference voltage detected across a sensing resistor; and

detecting a drain source current of the DUT through the difference voltage detected across the sensing resistor.