WO2024050906A1 - Semiconductor structure, forming method therefor and layout structure - Google Patents

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure, a forming method therefor and a layout structure. The semiconductor structure comprises: a substrate, and transistor structures which are located on the surface of the substrate and are arranged in an array in a first direction and a second direction; the transistor structures comprise first transistors and second transistors; channel structures of the first transistors and channel structures of the second transistors both extend in a third direction; the first direction and the second direction are any two directions in a plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

Description

Semiconductor structure and formation method, layout structure

Cross-references to related applications

This disclosure is based on the Chinese patent application with the application number 202211091001.2, the filing date is September 7, 2022, and the invention name is "Semiconductor Structure and Formation Method, Layout Structure", and claims the priority of the Chinese patent application. The entire contents of the patent application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure, its formation method, and layout structure.

Background technique

At present, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) occupies an important position in the semiconductor industry. It can be used in digital logic circuits, static random access memory (Static Random-Access Memory, SRAM), microprocessors and microcontrollers. Controllers and other fields. As the integration level of CMOS in semiconductor structures becomes larger and larger, the storage density and efficiency of CMOS are also required to continue to increase, which will lead to serious problems such as gate leakage, junction leakage or well leakage in CMOS.

Contents of the invention

In view of this, embodiments of the present disclosure provide a semiconductor structure, a method of forming the same, and a layout structure.

In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, and a transistor structure arranged in an array along a first direction and a second direction on a surface of the substrate, where the transistor structure includes a first transistor and a A second transistor, the channel structure of the first transistor and the channel structure of the second transistor both extend along a third direction; wherein the first direction and the second direction are the plane where the substrate is located Any two directions within the third direction intersect with the plane where the substrate is located.

In some embodiments, the first transistor and the second transistor are different types of transistors.

In some embodiments, the first transistor and the second transistor are arranged in mirror symmetry.

In some embodiments, the gate structures of the first transistor and the second transistor include a gate dielectric layer and a gate conductive layer, and the first transistor and the second transistor share the gate conductive layer. layer.

In some embodiments, the channel structures of the first transistor and the second transistor each have at least one convex portion and/or at least one concave portion;

Wherein, at least one convex portion in the channel structure of the first transistor and at least one convex portion in the channel structure of the second transistor are mirror-symmetrical or staggered; or,

At least one recessed portion in the channel structure of the first transistor and at least one recessed portion in the channel structure of the second transistor are arranged in mirror symmetry or staggered arrangement.

In some embodiments, the semiconductor structure further includes a conductive structure located above the transistor structure, the conductive structure includes a first conductive line, a second conductive line, and a third conductive line, and the drain of the first transistor The drains of the first transistor and the second transistor are connected to the first conductive line, the source of the first transistor is connected to the second conductive line through a conductive plug, and the source of the second transistor is connected to the second conductive line through a conductive plug. The plug is connected to the third conductive wire.

In some embodiments, along the second direction, the sources of a plurality of first transistors are electrically connected to the second conductive line, and the sources of a plurality of second transistors are electrically connected to the third conductive line. Conductive thread.

In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method including:

Provide a substrate;

A transistor structure arranged in an array along a first direction and a second direction is formed on the surface of the substrate. The transistor structure includes a first transistor and a second transistor, a channel structure of the first transistor and a channel structure of the second transistor. The channel structures all extend along the third direction; wherein, the first direction and the second direction are any two directions in the plane where the substrate is located, and the third direction is consistent with the plane where the substrate is located. Planes intersect.

In some embodiments, the transistor structure is formed by the following steps:

Form first source electrodes and second source electrodes spaced apart along the first direction on the surface of the substrate;

Forming a first channel structure and a second channel structure on the surfaces of the first source electrode and the second source electrode respectively;

Forming a first drain electrode and a second drain electrode on top of the first channel structure and the second channel structure respectively;

A common gate structure is formed between the first channel structure and the second channel structure.

In some embodiments, the first channel structure and the second channel structure are formed by the following steps:

Forming a first epitaxial layer and a second epitaxial layer on the surfaces of the first source electrode and the second source electrode respectively;

forming a mask layer in a gap between the first source electrode and the second source electrode and between the first epitaxial layer and the second epitaxial layer;

Forming a third epitaxial layer and a fourth epitaxial layer covering part of the mask layer on the surfaces of the first epitaxial layer and the second epitaxial layer respectively;

The third epitaxial layer and the fourth epitaxial layer are patterned to form the first channel structure and the second channel structure correspondingly.

In some embodiments, along the first direction, the size of the third epitaxial layer formed is larger than the size of the first epitaxial layer, and the size of the fourth epitaxial layer formed is larger than the size of the second epitaxial layer. The size of the layer.

In some embodiments, patterning the third epitaxial layer and the fourth epitaxial layer includes:

Etch and remove part of the sidewalls of the third epitaxial layer and the fourth epitaxial layer to form at least one convex surface on the two opposite sidewall surfaces between the third epitaxial layer and the fourth epitaxial layer. part and/or at least one recess;

Wherein, the first epitaxial layer and the remaining third epitaxial layer form the first channel structure, and the second epitaxial layer and the remaining fourth epitaxial layer form the second channel structure.

In some embodiments, after patterning the third epitaxial layer and the fourth epitaxial layer, the method further includes:

Remove the mask layer;

forming an isolation layer between the remaining third epitaxial layer and the remaining fourth epitaxial layer;

Ion implantation is performed on the tops of the third epitaxial layer and the fourth epitaxial layer to form the first drain electrode and the second drain electrode respectively.

In some embodiments, the first source electrode, the first channel structure and the first drain electrode together form a first active region, the second source electrode, the second channel structure and the The second drain electrodes together constitute a second active region; the method further includes:

Remove the isolation layer to expose sidewall surfaces of the first active region and the second active region, and form a gate dielectric layer on the exposed sidewall surfaces;

A first insulating layer, a gate conductive layer and a second insulating layer are formed in sequence from bottom to top between the first active area having the gate dielectric layer and the second active area having the gate dielectric layer.

In some embodiments, the method further includes:

forming a first conductive line electrically connected to the first drain electrode and the second drain electrode;

Second conductive lines, third conductive lines and a plurality of conductive plugs are formed, the first source electrode is electrically connected to the second conductive line through the conductive plugs, and the second source electrode passes through the conductive plugs. Electrically connect the third conductive wire.

In a third aspect, embodiments of the present disclosure provide a layout structure. The layout structure includes:

A source layer, a channel layer, and a drain layer are arranged in sequence from bottom to top, and the source layer includes a plurality of first source electrodes and a plurality of second source electrodes arranged in an array along the first direction and the second direction, The channel layer includes a plurality of first channel structures and a plurality of second channel structures arranged in an array along the first direction and the second direction, the first channel structure and the second channel structure The channel structures all extend along the third direction, and the drain layer includes a plurality of first drain electrodes and a plurality of second drain electrodes arranged in an array along the first direction and the second direction;

Along the first direction, the first source electrodes and the second source electrodes are alternately arranged at intervals; along the second direction, a plurality of the first source electrodes are arranged at intervals, and a plurality of the first source electrodes are arranged at intervals. Two sources are arranged at intervals;

Each of the first source electrodes is electrically connected to two of the first channel structures, and each of the second source electrodes is electrically connected to two of the second channel structures; each of the first channels is electrically connected to The top of the structure is electrically connected to one of the first drain electrodes, and the top of each of the second channel structures is electrically connected to one of the second drain electrodes; wherein the third direction is connected to the first direction and the The plane on which the second direction lies intersects.

In some embodiments, the layout structure further includes: a gate layer located on the same layer as the channel layer, the gate layer at least includes a plurality of gate conductive layers, and the gate conductive layer is located along the Extending in the second direction; a row of first channel structures and a row of second channel structures adjacently arranged along the first direction share one gate conductive layer.

In some embodiments, the layout structure further includes: a conductive layer located above the drain layer, the conductive layer including first conductive lines, second conductive lines and third conductive lines arranged at intervals;

Along the first direction, two adjacent first drain electrodes and the second drain electrode are electrically connected to the same first conductive line;

Along the second direction, two adjacent first source electrodes are electrically connected to the same second conductive line through a conductive plug, and two adjacent second source electrodes are electrically connected through a conductive plug. Connect the same third conductive wire.

In the semiconductor structure and its formation method and layout structure provided by the embodiments of the present disclosure, since the channel structure of the first transistor and the channel structure of the second transistor in the transistor structure extend along the third direction, therefore, in the embodiments of the present disclosure, The channel structure is vertical. The vertical channel structure not only enables the transistor structure to have a higher arrangement density, but also reduces the size of the transistor structure, thereby improving the integration of the semiconductor structure.

Description of the drawings

In the drawings (which are not necessarily to scale), similar reference characters may describe similar components in the different views. Similar reference numbers with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example, and not limitation.

Figures 1a to 1c are schematic structural diagrams of semiconductor structures provided by embodiments of the present disclosure;

Figures 1d and 1e provide schematic structural diagrams of another channel structure according to an embodiment of the present disclosure;

Figure 1f is a schematic equivalent circuit diagram of the semiconductor structure corresponding to Figures 1b and 1c provided by an embodiment of the present disclosure;

2a and 2b are schematic structural diagrams of another semiconductor structure provided by embodiments of the present disclosure;

Figure 2c is an equivalent circuit schematic diagram of the semiconductor structure corresponding to Figures 2a and 2b provided by an embodiment of the present disclosure;

Figure 3 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure;

4a to 4h are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that a thorough understanding of the disclosure will be provided, and the scope of the disclosure will be fully conveyed to those skilled in the art.

In the following description, numerous details are given in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features that are well known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer , adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily imply the presence of the first element, component, region, layer or section in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

Before introducing the embodiments of the present disclosure, let us first define the three directions that may be used to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite the front side; defining an intersection (eg, perpendicular) with the top and bottom surfaces of the substrate, ignoring the flatness of the top and bottom surfaces. The direction is the third direction. In the direction of the top surface and the bottom surface of the substrate (ie, the plane on which the substrate is located), two directions that intersect each other (for example, are perpendicular to each other) are defined as the first direction and the second direction. For example, the first transistor and the second transistor in the transistor structure can be defined. The second transistor is arranged in a first direction, and the planar direction of the substrate can be determined based on the first direction and the second direction. In the embodiment of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular to each other. In the embodiment of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

Embodiments of the present disclosure provide a semiconductor structure. Figures 1a to 1c are schematic structural diagrams of the semiconductor structure provided by embodiments of the present disclosure. Figure 1b is a layout structure of a transistor structure in the semiconductor structure. Figure 1c is a diagram along 1b. A-a' cross-sectional view, as shown in Figures 1a to 1c, the semiconductor structure 100 includes: a substrate 10, and a transistor structure 200 arranged in an array along the X-axis direction and the Y-axis direction on the surface of the substrate 10. The transistor structure 200 includes a first transistor 14 and a second transistor 15; the channel structures of the first transistor 14 and the second transistor 15 both extend along the Z-axis direction.

In embodiments of the present disclosure, the transistor structure 200 may be a complementary metal oxide semiconductor (CMOS).

In the embodiment of the present disclosure, the substrate 10 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, and the substrate 10 may also include other semiconductor elements, such as germanium (Ge), or a semiconductor Compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys , such as: silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and /or Gallium Indium Arsenide Phosphate (GaInAsP) or combinations thereof.

In some embodiments, the substrate 10 may also include a shallow trench isolation (Shallow Trench Isolation, STI) structure or a local oxidation of silicon (Local Oxidation of Silicon, LOCOS) structure. A shallow trench isolation structure or a silicon local oxidation isolation structure can isolate several active areas in the substrate 10 .

In the embodiment of the present disclosure, the first transistor 14 and the second transistor 15 are of opposite types. For example, the first transistor 14 can be an N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS), and the second transistor 15 can be It is a P-type metal oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS); or the opposite.

In the embodiment of the present disclosure, since the channel structure of the first transistor and the channel structure of the second transistor in the transistor structure extend along the third direction, the channel structure in the embodiment of the present disclosure is vertical. The vertical channel structure not only enables the transistor structure to have a higher arrangement density, but also reduces the size of the transistor structure and improves the integration of the semiconductor structure.

Please continue to refer to Figure 1b and Figure 1c. In the embodiment of the present disclosure, the first transistor 14 and the second transistor 15 are arranged in mirror symmetry; wherein the first transistor 14 includes a first source 141, a first drain 142 and a first Channel structure 143, the second transistor 15 includes a second source 151, a second drain 152 and a second channel structure 153; both the first channel structure 143 and the second channel structure 153 extend along the Z-axis direction; A source electrode 141 and a first drain electrode 142 are respectively located at both ends of the first channel structure 143 along the Z-axis direction. A second source electrode 151 and a second drain electrode 152 are respectively located at both ends of the second channel structure 153 along the Z-axis direction. both ends.

In the embodiment of the present disclosure, both the first channel structure 143 and the second channel structure 153 have one convex part and two recessed parts, or the first channel structure 143 and the second channel structure 153 both have one recessed part (or two convex parts). For example, continuing to refer to FIG. 1 c , the first channel structure 143 and the second channel structure 153 each have one convex portion and two concave portions.

In other embodiments, the first channel structure 143 may have multiple protrusions and/or multiple recesses, and the second channel structure 153 may also have multiple protrusions and/or multiple recesses. Figures 1d and 1e provide schematic structural diagrams of another channel structure according to an embodiment of the present disclosure. As shown in Figure 1d, both the first channel structure 143 and the second channel structure 153 have four concave portions and three convex portions. . As shown in FIG. 1 e , the first channel structure 143 has three protrusions and four recesses, and the second channel structure 153 has three recesses and four protrusions.

It should be noted that the number of convex portions (or concave portions) in the first channel structure 143 and the second channel structure 153 may be the same or different; The convex parts (or concave parts) may be arranged in mirror symmetry (as shown in FIGS. 1c and 1d ), and the convex parts (or concave parts) in the first channel structure 143 and the second channel structure 153 may also be arranged in a staggered manner (as shown in FIG. 1 shown in 1e).

In the embodiment of the present disclosure, the channel structure of the first transistor 14 is set to have at least one convex part and/or at least one recessed part, and the channel structure of the second transistor 15 is set to have at least one convex part and/or at least A recess allows the transistor structure in the embodiment of the present disclosure to have a larger channel structure length, thereby effectively suppressing the short channel effect of the transistor structure and improving the performance of the transistor structure.

In some embodiments, please continue to refer to FIG. 1c. Both the first transistor 14 and the second transistor 15 include a gate structure; the gate structure of the first transistor 14 includes a gate dielectric layer 171 and a gate dielectric layer located on the surface of the gate dielectric layer 171. Gate conductive layer 18, the gate structure of the second transistor 15 includes a gate dielectric layer 172 and a gate conductive layer 18 located on the surface of the gate dielectric layer 172. In the embodiment of the present disclosure, the first transistor 14 and the second transistor 15 The gate conductive layer 18 is shared. Among them, the materials of the gate dielectric layer 171 and the gate dielectric layer 172 can be high dielectric materials (High K) or other suitable materials; the material of the gate conductive layer 18 can be any material with good conductivity. For example, titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu) any of them.

In some embodiments, continuing to refer to FIGS. 1 a and 1 c , the semiconductor structure 100 further includes a first isolation layer 16 between the substrate 10 and the transistor structure 200 . The first isolation layer 16 is used to isolate the transistor structure 200 and the substrate 10 to prevent current leakage.

In some embodiments, please continue to refer to FIG. 1 c. The transistor structure 200 further includes: a first source electrode located within the projection area of the first source electrode 141 of the first transistor 14 and the second source electrode 151 of the second transistor 15 along the X-axis direction. The insulating layer 11 and the second insulating layer 12 are located in the projection area of the first drain electrode 142 of the first transistor 14 and the second drain electrode 152 of the second transistor 15 along the X-axis direction. The first insulating layer 11 is used to prevent the first transistor 14 and the second transistor 15 from being isolated from the substrate when the first isolation layer 16 is broken down, thereby further preventing the first transistor 14 and the second transistor 15 from leaking current. The second insulating layer 12 is used to isolate the first transistor 14 and the second transistor 15 from subsequently formed metal lines to prevent leakage of the first transistor 14 and the second transistor 15 .

In some embodiments, please continue to refer to FIG. 1c, the semiconductor structure further includes: a second isolation layer 13 located between two adjacent transistor structures. The second isolation layer 13 is used to isolate adjacent transistor structures and prevent leakage of the transistor structures.

In the embodiment of the present disclosure, the materials of the first isolation layer 16 , the second isolation layer 13 , the first insulation layer 11 and the second insulation layer 12 can be any suitable insulation material, for example, the first isolation layer 16 and the second insulation layer 12 can be made of any suitable insulation material. The second isolation layer 13 may be made of silicon oxide, and the first insulating layer 11 and the second insulating layer 12 may be made of low dielectric constant (Low K) material.

In some embodiments, please continue to refer to Figures 1b and 1c, the semiconductor structure further includes: a conductive structure located above the transistor structure 200, the conductive structure includes a first conductive line 19, a second conductive line 211 and a third conductive line 212; In the transistor structure 200 , the first drain 142 of the first transistor 14 and the second drain 152 of the second transistor 15 are both connected to the first conductive line 19 ; the first conductive line 19 is used to transmit the output signal of the transistor structure 200 .

In some embodiments, please continue to refer to Figures 1b and 1c, the semiconductor structure further includes: a conductive plug 20; wherein the first source 141 of the first transistor 14 is connected to the second conductive line 211 through the conductive plug 20, The second source 151 of the second transistor 15 is connected to the third conductive line 212 through the conductive plug 20; the second conductive line 211 is used to transmit ground signals, and the third conductive line 212 is used to transmit power signals.

Figure 1f is a schematic diagram of the equivalent circuit of the semiconductor structure corresponding to Figure 1b and Figure 1c. As shown in Figure 1f, the circuit of the semiconductor structure includes a CMOS circuit, and the CMOS circuit includes a PMOS tube and an NMOS tube, where the PMOS tube and the NMOS The gate of the tube is connected as the input terminal, the drain of the PMOS tube and the NMOS tube are connected as the output terminal, the source of the PMOS tube is connected with the power signal, and the source of the NMOS tube is connected with the ground signal.

The semiconductor structure provided by the embodiment of the present disclosure includes a transistor structure arranged in an array along a first direction and a second direction on a substrate surface, and the channel structure of the first transistor and the channel structure of the second transistor in the transistor structure are arranged along the first direction. It extends in three directions, that is to say, the channel structure in the embodiment of the present disclosure is vertical. The vertical channel structure can enable the transistor structure to have a higher arrangement density. In this way, the size of the transistor structure can be reduced and the integration of the semiconductor structure can be improved.

Figures 2a and 2b are schematic structural diagrams of another semiconductor structure provided by an embodiment of the present disclosure, wherein Figure 2a is a layout structure of a transistor structure in the semiconductor structure, and Figure 2b is a cross-sectional view along bb' in Figure 2a As shown in Figure 2a and Figure 2b, the semiconductor structure 100 includes: a substrate 10 and four transistor structures 200 arranged along the Y-axis direction on the surface of the substrate 10. The transistor structure 200 includes a first transistor 14 and a second transistor 15; The channel structures of the first transistor 14 and the second transistor 15 both extend along the Z-axis direction.

In some embodiments, the first transistor 14 may be an NMOS transistor, and the second transistor 15 may be a PMOS transistor.

In some embodiments, please continue to refer to FIG. 2a and FIG. 2b. The first transistor 14 and the second transistor 15 are arranged in a mirror configuration; wherein the first transistor 14 includes a first source 141, a first drain 142 and a first trench. Channel structure 143, the second transistor 15 includes a second source 151, a second drain 152 and a second channel structure 153; both the first channel structure 143 and the second channel structure 153 extend along the Z-axis direction; the first The source electrode 141 and the first drain electrode 142 are respectively located at both ends of the first channel structure 143 along the Z-axis direction. The second source electrode 151 and the second drain electrode 152 are respectively located at both ends of the second channel structure 153 along the Z-axis direction. end.

In this embodiment of the present disclosure, both the first channel structure 143 and the second channel structure 153 have one convex part; in other embodiments, the first channel structure 143 may have multiple convex parts and/or multiple concave parts, The second channel structure 153 may also have a plurality of convex portions and/or a plurality of concave portions (as shown in FIGS. 1d and 1e ).

It should be noted that the number of convex portions (or concave portions) in the first channel structure 143 and the second channel structure 153 may be the same or different; The convex parts (or concave parts) can be arranged in mirror symmetry (as shown in Figure 1c and Figure 1d), or they can be arranged in a staggered manner (as shown in Figure 1e).

In the embodiment of the present disclosure, the channel structure of the first transistor 14 is set to have at least one convex part and/or at least one recessed part, and the channel structure of the second transistor 15 is set to have at least one convex part and/or at least A recess allows the transistor structure in the embodiment of the present disclosure to have a larger channel structure length, thereby effectively suppressing the short channel effect of the transistor structure and improving the performance of the transistor structure.

In the embodiment of the present disclosure, please continue to refer to FIG. 2a and FIG. 2b. The gate structure of the first transistor 14 includes a gate dielectric layer 171 and a gate conductive layer 18 located on the surface of the gate dielectric layer 171. The gate structure of the second transistor 15 The gate structure includes a gate dielectric layer 172 and a gate conductive layer 18 located on the surface of the gate dielectric layer 172 . The first transistor 14 and the second transistor 15 share the gate conductive layer 18 .

In some embodiments, please continue to refer to FIGS. 2 a and 2 b. The semiconductor structure 100 further includes a projection region located in the projection area of the first source electrode 141 of the first transistor 14 and the second source electrode 151 of the second transistor 15 along the X-axis direction. The first insulating layer 11 and the second insulating layer 12 are located in the projection area of the first drain electrode 142 of the first transistor 14 and the second drain electrode 152 of the second transistor 15 along the X-axis direction.

In some embodiments, continuing to refer to FIGS. 2 a and 2 b , the semiconductor structure 100 further includes a first isolation layer 16 between the substrate 10 and the transistor structure 200 .

In some embodiments, please continue to refer to FIGS. 2a and 2b , the semiconductor structure 100 further includes a second isolation layer 13 located between two adjacent transistor structures 200 .

In some embodiments, please continue to refer to FIGS. 2a and 2b , the semiconductor structure 100 further includes four first conductive lines 19 ; a first drain 142 of the first transistor 14 and a second electrode of the second transistor 15 in each transistor structure. The drain electrode 152 is connected to the first conductive line 19; the first conductive line 19 is used to transmit the output signal of the transistor structure 200.

In some embodiments, please continue to refer to FIGS. 2a and 2b , the semiconductor structure 100 further includes four conductive plugs 20 , second conductive lines 211 and third conductive lines 212 . The first source electrode 141 of the first transistor 14 located in the same column along the Y-axis direction is connected to the second conductive line 211 through the conductive plug 20, and the second source electrode 151 of the second transistor 15 located in the same column along the Y-axis direction passes through The conductive plug 20 is connected to a third conductive wire 212, where the second conductive wire 211 is used to transmit ground signals, and the third conductive wire 212 is used to transmit power signals.

In some embodiments, please continue to refer to FIG. 2a and FIG. 2b , every two adjacent first transistors 14 along the Y-axis direction share a first source 141 , or every two adjacent second transistors 141 along the Y-axis direction. 15 share a second source 151.

Figure 2c is a schematic diagram of the equivalent circuit of the semiconductor structure corresponding to Figure 2a and Figure 2b. As shown in Figure 2c, the circuit of the semiconductor structure includes four CMOS circuits. Each CMOS circuit includes a PMOS tube and an NMOS tube. Each CMOS The gates of the PMOS tube and the NMOS tube in the circuit are connected. The gates of the four CMOS circuits are connected as the input terminal. The drains of the PMOS tube and the NMOS tube in each CMOS circuit are connected as the output terminal. The PMOS tube in each CMOS circuit is connected. The source is connected to the power signal, that is, the sources of the four PMOS tubes are connected to the power signal; the source of the NMOS tube in each CMOS circuit is connected to the ground signal, that is, the sources of the four NMOS tubes are connected to the ground signal .

The semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above-mentioned embodiments for understanding, and will not be described again here.

The semiconductor structure provided by the embodiment of the present disclosure includes a transistor structure arranged in an array along a first direction and a second direction on a substrate surface, and the channel structure of the first transistor and the channel structure of the second transistor in the transistor structure are arranged along the first direction. Extending in three directions, that is to say, the channel structure and the transistor structure in the embodiment of the present disclosure are both vertical. In this way, not only can the transistor structure have a higher arrangement density, but also the size of the transistor structure can be reduced, thereby Improve the integration of semiconductor structures.

Embodiments of the present disclosure provide a layout structure. Please continue to refer to FIG. 1b and FIG. 2a. The layout structure includes a source layer, a channel layer and a drain layer arranged in sequence from bottom to top; the source layer includes a A plurality of first source electrodes and a plurality of second source electrodes arranged in an array along the axial direction. The channel layer includes a plurality of first channel structures and a plurality of second channels arranged in an array along the X-axis direction and the Y-axis direction. Structure, the first channel structure and the second channel structure both extend along the Z-axis direction, and the drain layer includes a plurality of first drain electrodes and a plurality of second drain electrodes arranged in an array along the X-axis direction and the Y-axis direction; Along the X-axis direction, the first source electrodes and the second source electrodes are alternately arranged at intervals; along the Y-axis direction, a plurality of first source electrodes are arranged at intervals, and a plurality of second source electrodes are arranged at intervals; each first source electrode Two first channel structures are electrically connected above, and two second channel structures are electrically connected above each second source electrode; a first drain electrode is electrically connected above each first channel structure, and each second channel structure is electrically connected above A second drain is electrically connected above the channel structure.

In the embodiment of the present disclosure, the first source electrode, the first channel structure and the first drain electrode constitute the first transistor 14; the second source electrode, the second channel structure and the second drain electrode constitute the second transistor 15.

In the embodiment of the present disclosure, since the first transistor 14 and the second transistor 15 are both vertical, the transistor structure can have a higher arrangement density, which not only reduces the size of the transistor structure, but also improves the semiconductor structure. degree of integration.

In the embodiment of the present disclosure, the first transistor 14 and the second transistor 15 are of opposite types. For example, the first transistor 14 is an NMOS transistor and the second transistor 15 is a PMOS transistor.

In some embodiments, please continue to refer to FIG. 1 b and FIG. 2 a. The layout structure also includes: a gate layer located on the same layer as the channel layer. The gate layer includes a plurality of first channels located in a row along the X-axis direction. A gate dielectric layer on the surface of the structure, a plurality of gate dielectric layers on the surface of a row of second channel structures along the X-axis direction, and a plurality of gate electrodes located between two adjacent gate dielectric layers in the same transistor structure The conductive layer 18, the gate dielectric layer and the gate conductive layer 18 extend along the Y-axis direction; a row of first channel structures and a row of second channel structures adjacently arranged along the X-axis direction share a gate conductive layer 18 ( That is, the first transistor 14 and the second transistor 15 in the transistor structure share the gate conductive layer 18).

In some embodiments, the layout structure also includes: a conductive layer located above the drain layer, the conductive layer includes first conductive lines 19, second conductive lines 211 and third conductive lines 212 arranged at intervals; along the X-axis direction, Two adjacent first drain electrodes and second drain electrodes are electrically connected to the same first conductive line 19; along the Y-axis direction, two adjacent first source electrodes are electrically connected to the same second conductive line through conductive plugs. Line 211, two adjacent second sources are electrically connected to the same third conductive line 212 through conductive plugs. The first conductive line 19 is used to transmit the output signal of the transistor structure.

In some embodiments, please continue to refer to FIG. 2a, every two adjacent transistors 14 arranged sequentially along the Y-axis direction share a source. Every two adjacent second transistors 15 arranged sequentially along the Y-axis direction share a source.

In some embodiments, please continue to refer to FIG. 1 b and FIG. 2 a, the layout structure further includes: conductive plugs 20 . The first source electrode of the first transistor 14 located in the same column along the Y-axis direction is connected to the second conductive line 211 through the conductive plug 20; the second source electrode of the second transistor 15 located in the same column along the Y-axis direction passes through The conductive plug 20 is connected to the third conductive wire 212 . The second conductive line 211 is used for transmitting power signals, and the third conductive line 212 is used for transmitting ground signals.

It should be noted that the source layer and the drain layer in the embodiment of the present disclosure do not completely overlap in the Z-axis direction, that is, the drain layer needs to expose part of the source layer to form a conductive plug extending along the Z-axis direction. 20, to lead out the source.

In some embodiments, the layout structure further includes an active area layout layer, and a first isolation layer (not shown in Figures 1b and 2a) located between the active area layout layer and the source layer; wherein, the first isolation layer The isolation layer is used to isolate the active area layer and the source layer to prevent leakage of the transistor structure.

In some embodiments, the layout structure further includes: a second isolation layer located between two adjacent transistor structures (not shown in Figures 1b and 2a). The second isolation layer is used to isolate adjacent transistor structures and prevent leakage of the transistor structures.

The transistor structure in the layout structure provided by the embodiment of the present disclosure is similar to the transistor structure in the above-mentioned embodiment. For technical features that are not disclosed in detail in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and will not be described again here.

The layout structure provided by the embodiment of the present disclosure includes a source layer, a channel layer and a drain layer arranged sequentially from bottom to top; the source layer includes a plurality of first source electrodes and a plurality of second source electrodes arranged in an array. The channel layer includes a plurality of first channel structures and a plurality of second channel structures arranged in an array, and the drain layer includes a plurality of first drain electrodes and a plurality of second drain electrodes arranged in an array. Since the first channel structure and the plurality of second channel structures extend along the third direction, that is, the first channel structure and the second channel structure are both vertical, in this way, not only can the size of the transistor structure be reduced, but also the size of the transistor structure can be reduced. The integration level of semiconductor structures can be improved. In addition, since the transistor structures located in the same column along the second direction share a gate structure, and every two adjacent transistor structures along the second direction share a source, the space in the semiconductor structure can be effectively utilized, further achieving Miniaturization of semiconductor structures.

In addition, embodiments of the disclosure also provide a method for forming a semiconductor structure. Figure 3 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 3, the method for forming a semiconductor structure includes the following steps. :

Step S301: Provide a substrate.

Step S302: Form a transistor structure arranged in an array along the first direction and the second direction on the substrate surface. The transistor structure includes a first transistor and a second transistor. The channel structure of the first transistor and the channel structure of the second transistor are both extends in the third direction.

In the embodiment of the present disclosure, the transistor structure 200 may be a complementary metal oxide semiconductor (CMOS); the first transistor and the second transistor are of opposite types. For example, the first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor.

4a to 4h are schematic structural diagrams of the semiconductor structure formation process provided by the embodiment of the present disclosure. The formation process of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 4a to 4h.

In some embodiments, the transistor structure may be formed by the following steps: forming first source electrodes and second source electrodes spaced apart along the first direction on the surface of the substrate; respectively forming first source electrodes and second source electrodes on the surfaces of the first source electrode and the second source electrode. forming a first channel structure and a second channel structure; forming a first drain electrode and a second drain electrode on top of the first channel structure and the second channel structure respectively; A common gate structure is formed between the structures.

In the embodiment of the present disclosure, the first source electrode, the first channel structure and the first drain electrode constitute the first transistor; the second source electrode, the second channel structure and the second drain electrode constitute the second transistor; subsequently, the formed The first transistor is an NMOS transistor, and the formed second transistor is a PMOS transistor, as an example. In other embodiments, the first transistor may be a PMOS transistor, and the second transistor may be an NMOS transistor.

As shown in FIG. 4a, a first isolation material is deposited on the surface of the substrate 10 to form a first isolation layer 16; the first isolation layer 16 is used to isolate the transistor structure 200 and the substrate 10 to prevent leakage. The first isolation material can be any insulating material, such as silicon oxide or silicon oxynitride.

It should be noted that before forming the first isolation layer on the surface of the substrate, the surface of the substrate also needs to be cleaned. During implementation, the substrate can have a clean surface through the following steps: First, form a The sacrificial oxide layer captures defects on the substrate surface through the sacrificial oxide layer; secondly, the sacrificial oxide layer is removed by etching with hydrofluoric acid solution.

Please continue to refer to FIG. 4a. First source electrodes 141 and second source electrodes 151 are formed on the surface of the first isolation layer 16 and are spaced apart along the X-axis direction. For example, an epitaxial semiconductor layer (not shown in FIG. 4 a ) can be epitaxially formed on the surface of the first isolation layer 16 , the left half of the epitaxial semiconductor layer is doped to form an N-well, and the right half of the epitaxial semiconductor layer is doped. Doping forms a P well, and a photoresist layer (not shown in Figure 4a) is formed on the surface of the N well and P well. The photoresist layer exposes part of the N well and part of the P well. The exposed parts are removed by etching the photoresist layer. Part of the N well and part of the P well form the first source electrode 141 and the second source electrode 151 .

In some embodiments, the first channel structure and the second channel structure may be formed by the following steps: forming a first epitaxial layer and a second epitaxial layer on the surfaces of the first source electrode and the second source electrode respectively; A mask layer is formed in the gap between the source electrode and the second source electrode and between the first epitaxial layer and the second epitaxial layer; a mask layer covering part of the mask layer is formed on the surface of the first epitaxial layer and the second epitaxial layer respectively. The third epitaxial layer and the fourth epitaxial layer are patterned to form a first channel structure and a second channel structure correspondingly.

In the embodiment of the present disclosure, as shown in FIG. 4b , the first epitaxial layer 143a can be formed by epitaxially extending P-type silicon on the surface of the first source electrode 141, and epitaxially using N-type silicon on the surface of the second source electrode 151 to form The second epitaxial layer 153a.

In some embodiments, the first epitaxial layer 143a and the second epitaxial layer 153a may be formed in the following two ways:

Method 1: First, as shown in FIG. 4b, the first epitaxial layer 143a and the second epitaxial layer 153a are respectively formed on the surfaces of the first source electrode 141 and the second source electrode 151; electrode 151, the first epitaxial layer 143a, the second epitaxial layer 153a and the barrier layer 24 on the surface of the first isolation layer 16, wherein the barrier layer 24 exposes the first surface a and the first source electrode 141 along the X-axis direction. The second surface b of the epitaxial layer 143a along the X-axis direction, the third surface c of the second source electrode 151 along the X-axis direction, and the fourth surface d of the second epitaxial layer 153a along the X-axis direction; secondly, as shown in FIG. 4c , through the first surface a, the second surface b, the third surface c, and the fourth surface d exposed by the barrier layer 24, the first source electrode 141, the first epitaxial layer 143a, and the first epitaxial layer 143a are laterally etched along the The two source electrodes 151 and the second epitaxial layer 153a are such that the first source electrode 141, the first epitaxial layer 143a, the second source electrode 151 and the second epitaxial layer 153a all have a first preset size L1 in the X-axis direction, forming The first epitaxial layer 143a has a first preset size L1 and the second epitaxial layer 153a has a first preset size L1.

In the embodiment of the present disclosure, the material of the barrier layer 24 may be silicon nitride or silicon carbonitride.

In the embodiment of the present disclosure, the barrier layer 24 can be formed by any of the following deposition processes: chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process, spin coating process, coating process or thin film process, etc.

Method 2: Directly form the first source electrode 141 with the first preset size L1 along the X-axis direction and the second source electrode 151 with the first preset size L1 on the surface of the first isolation layer 16. A first epitaxial layer 143 a with a first preset size L1 and a second epitaxial layer with a first preset size L1 along the X-axis direction are directly epitaxially formed on the first source electrode 141 and the second source electrode 151 of the preset size L1 respectively. Layer 153a.

It should be noted that after forming the first epitaxial layer 143a with the first preset size L1 and the second epitaxial layer 153a with the first preset size L1 in the above manner, the method of forming the semiconductor structure further includes: removing the barrier Layer 24.

As shown in FIG. 4d, between the first source electrode 141 and the second source electrode 151, and between the first epitaxial layer 143a with the first predetermined size L1 and the second epitaxial layer 153a with the first predetermined size L1. A mask layer 25 is formed in the gap. The material of the mask layer 25 may be a spin-on hard mask or silicon oxide.

Please continue to refer to FIG. 4d. A third epitaxial layer 143b covering part of the mask layer 25 is formed on the surface of the first epitaxial layer 143a with the first preset size L1 and the second epitaxial layer 153a with the first preset size L1 respectively. and fourth epitaxial layer 153b.

In the embodiment of the present disclosure, the third epitaxial layer 143b can be formed by epitaxially growing P-type silicon on the surface of the first epitaxial layer 143a, and forming the fourth epitaxial layer 153b by epitaxially growing N-type silicon on the surface of the second epitaxial layer 153a.

In the embodiment of the present disclosure, both the third epitaxial layer 143b and the fourth epitaxial layer 153b have a second preset size L2 in the X-axis direction; the second preset size L2 is larger than the first preset size L1.

Next, the third epitaxial layer 143b and the fourth epitaxial layer 153b are patterned to form a first channel structure and a second channel structure.

In some embodiments, after forming the third epitaxial layer and the fourth epitaxial layer, patterning the third epitaxial layer and the fourth epitaxial layer includes the following steps: etching to remove part of sides of the third epitaxial layer and the fourth epitaxial layer. wall to form at least one convex portion and/or at least one concave portion on the two opposite side wall surfaces between the third epitaxial layer and the fourth epitaxial layer; wherein the first epitaxial layer and the remaining third epitaxial layer form the third epitaxial layer. A channel structure, the second epitaxial layer and the remaining fourth epitaxial layer form the second channel structure.

In the embodiment of the present disclosure, forming a convex portion (or two concave portions) on the two opposite side wall surfaces between the third epitaxial layer 143b and the fourth epitaxial layer 153b is used as an example; in other embodiments, it can also be A plurality of convex portions (or a plurality of concave portions) are formed on the two opposite side wall surfaces between the third epitaxial layer 143b and the fourth epitaxial layer 153b.

As shown in Figure 4e, a photoresist layer 26 with a preset pattern E is formed on the surfaces of the mask layer 25, the third epitaxial layer 143b and the fourth epitaxial layer 153b; the preset pattern E exposes the third epitaxial layer 143b. Part of the sidewall and part of the sidewall of the fourth epitaxial layer 153b.

As shown in FIG. 4f, through the photoresist layer 26, part of the exposed sidewalls of the third epitaxial layer 143b and part of the exposed part of the fourth epitaxial layer 153b are etched away. A convex portion (or two concave portions) is formed on the two opposite side wall surfaces between the four epitaxial layers 153b; the remaining third epitaxial layer 143c and the remaining fourth epitaxial layer 153c are formed. The first epitaxial layer 143a and the remaining third epitaxial layer 143c form the first channel structure 143, and the second epitaxial layer 153a and the remaining fourth epitaxial layer 153c form the second channel structure 153.

In the embodiment of the present disclosure, both the first channel structure 143 and the second channel structure 153 are in a convex shape. The convex-shaped channel structure can make the transistor structure have a larger channel structure length L (as shown in Figure 4g). In this way, the short channel effect of the transistor structure can be effectively suppressed and the performance of the transistor structure can be improved.

In some embodiments, as shown in Figure 4f and Figure 4g, after forming the first channel structure 143 and the second channel structure 153, the method of forming the semiconductor structure further includes: sequentially removing the mask layer 25 and the photoresist. Layer 26. For example, a wet etching process (for example, using strong acid etching such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or a dry etching process (for example, a plasma etching process, a reactive ion etching process, or an ion milling process) can be used. ) remove the mask layer 25 and the photoresist layer 26 in sequence.

In the embodiment of the present disclosure, as shown in Figure 4f and Figure 4g, after removing the mask layer 25 and the photoresist layer 26, the method of forming the semiconductor structure further includes: A second isolation material is filled between the layers to form an isolation layer (not shown), where the second isolation material may be silicon nitride or any other suitable material.

In this disclosed embodiment, please continue to refer to FIG. 4g. P-type ion implantation is performed on the top of the third epitaxial layer 143c to form the first drain electrode 142; N-type ion implantation is performed on the top of the fourth epitaxial layer 153c to form the second drain electrode 142. Drain 152. Among them, N-type ions can be ions of group VA such as phosphorus, arsenic, and antimony, and P-type ions can be ions of group IIIA such as boron and indium.

In the embodiment of the present disclosure, please continue to refer to FIG. 4g. The first source electrode 141, the first channel structure 143 and the first drain electrode 142 together constitute the first active region; the second source electrode 151 and the second channel structure 153 Together with the second drain electrode 152, the second active region is formed.

In some embodiments, the method of forming a semiconductor structure further includes: removing the isolation layer, exposing sidewall surfaces of the first active region and the second active region, and forming a gate dielectric layer on the exposed sidewall surfaces; A first insulating layer, a gate conductive layer and a second insulating layer are formed in sequence from bottom to top between the first active area of the gate dielectric layer and the second active area having the gate dielectric layer.

Please continue to refer to Figure 4g and Figure 4h. The isolation layer is removed to expose the sidewall surface g of the first active region and the sidewall surface h of the second active region. Gate dielectric material is deposited on the sidewall surfaces h of the two active regions to form gate dielectric layer 171 and gate dielectric layer 172 respectively. The first insulating material and the gate conductive material are sequentially deposited between the gate dielectric layer 171 and the gate dielectric layer 172 to form the first insulating layer 11 and the initial gate conductive layer; wherein, the top surface of the initial gate conductive layer is in contact with the first gate conductive layer. The top surface of an active area (or second active area) is flush; the first insulating layer 11 is located within the projection area of the first source electrode 141 and the second source electrode 151 along the X-axis direction.

In the embodiment of the present disclosure, the first insulating layer 11 is used to prevent the first active area and the second active area from being isolated from the substrate when the first isolation layer 16 is broken down, thereby further preventing the first active area and the second active area from being broken down. The second active area leaks electricity.

In the embodiment of the present disclosure, the gate dielectric layer 171, the gate dielectric layer 172 and the initial gate conductive layer can be formed by any one of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process, coating process or film process, etc.

In the embodiment of the present disclosure, the gate dielectric material can be silicon oxide or other suitable materials; the gate conductive material can be any material with good conductivity, such as titanium, titanium nitride, tungsten nitride, tungsten, Any of cobalt, platinum, palladium, ruthenium and copper. The first insulating material may be a Low K material.

In the embodiment of the present disclosure, after forming the initial gate conductive layer, the method of forming the semiconductor structure further includes: etching back the initial gate conductive layer to expose the sidewalls of the first drain electrode 142 and the sidewalls of the second drain electrode 152 (not shown in the figure), the remaining initial gate conductive layer constitutes the gate conductive layer 18; the gate dielectric layer 171 and the gate conductive layer 18 constitute the gate structure, gate dielectric layer 172 and gate of the first transistor 14. The extremely conductive layer 18 forms the gate structure of the second transistor 15 .

In some embodiments, after forming the gate structure, the method of forming the semiconductor structure further includes: depositing a second insulating material in the gap between the first drain electrode 142 and the second drain electrode 152 to form the second insulating layer 12 . The second insulating material may be a Low K material.

In some embodiments, the method of forming the semiconductor structure further includes: forming a first conductive line 19 , the first conductive line 19 is electrically connected to the first drain electrode 142 and the second drain electrode 152 . A second conductive line (not shown in Figure 4h), a third conductive line (not shown in Figure 4h) and a plurality of conductive plugs (not shown in Figure 4h) are formed, through which the first source 141 passes The second conductive line is electrically connected, and the second source 151 is electrically connected to the third conductive line through the conductive plug.

In the embodiment of the present disclosure, the second insulating layer 12 is used to isolate the first active region and the second active region from the first conductive line formed subsequently, to prevent leakage of the first transistor and the second transistor.

In the embodiment of the present disclosure, after forming the first conductive line 19, the second conductive line, and the third conductive line, the method of forming the semiconductor structure further includes: performing an annealing treatment on the semiconductor structure; in this way, the defects of the formed semiconductor structure can be reduced. defect.

In some embodiments, please continue to refer to FIG. 4g and FIG. 4h. The method of forming the semiconductor structure further includes: forming a second isolation layer 13 between two adjacent transistor structures.

In the embodiment of the present disclosure, the second isolation layer 13 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process, coating process or thin film process, etc. . The second isolation layer 13 is used to isolate adjacent transistor structures and prevent leakage of the transistor structures.

The semiconductor structure formed by the method provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above-mentioned embodiments for understanding, and will not be described again here.

The present disclosure implements the method for forming a semiconductor structure provided by forming a transistor structure arranged in an array along the first direction and the second direction on the surface of the substrate. Since the transistor structure includes a channel structure extending along the third direction, through the present disclosure The channel structure of the transistor structure formed by the method for forming the semiconductor structure provided in the embodiment is vertical. The vertical channel structure can enable the transistor structure to have a higher arrangement density, and can also reduce the size of the transistor structure, thereby improving the integration of the semiconductor structure.

In the several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented. In addition, the components shown or discussed are coupled to each other, or directly coupled.

The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, and they should all be covered. within the scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

The channel structures in embodiments of the present disclosure are vertical. The vertical channel structure not only enables the transistor structure to have a higher arrangement density, but also reduces the size of the transistor structure, thereby improving the integration of the semiconductor structure.

Claims (18)

1. A semiconductor structure, including: a substrate, and a transistor structure arranged in an array along a first direction and a second direction on a surface of the substrate; the transistor structure includes a first transistor and a second transistor; the first transistor The channel structure of the second transistor and the channel structure of the second transistor both extend along the third direction; wherein the first direction and the second direction are any two directions in the plane where the substrate is located, and the The third direction intersects the plane of the substrate.
2. The semiconductor structure of claim 1, wherein the first transistor and the second transistor are different types of transistors.
3. The semiconductor structure of claim 2, wherein the first transistor and the second transistor are arranged in mirror symmetry.
4. The semiconductor structure according to claim 1 or 2, wherein the gate structures of the first transistor and the second transistor include a gate dielectric layer and a gate conductive layer, and the first transistor and the second transistor include a gate dielectric layer and a gate conductive layer. The two transistors share the gate conductive layer.
5. The semiconductor structure according to claim 1 or 2, wherein the channel structures of the first transistor and the second transistor each have at least one convex portion and/or at least one concave portion;

   Wherein, at least one convex portion in the channel structure of the first transistor and at least one convex portion in the channel structure of the second transistor are mirror-symmetrical or staggered; or,

   At least one recess in the channel structure of the first transistor and at least one recess in the channel structure of the second transistor are arranged in mirror symmetry or staggered arrangement.
6. The semiconductor structure of claim 1, wherein the semiconductor structure further includes a conductive structure located above the transistor structure, the conductive structure includes a first conductive line, a second conductive line, and a third conductive line, The drain of the first transistor and the drain of the second transistor are both connected to the first conductive line. The source of the first transistor is connected to the second conductive line through a conductive plug. The second The source of the transistor is connected to the third conductive line through a conductive plug.
7. The semiconductor structure of claim 6 , wherein along the second direction, sources of a plurality of first transistors are electrically connected to the second conductive line, and sources of a plurality of second transistors are commonly connected to the second conductive line. Electrically connect the third conductive wire.
8. A method of forming a semiconductor structure, the method comprising:

   Provide a substrate;

   A transistor structure arranged in an array along a first direction and a second direction is formed on the surface of the substrate. The transistor structure includes a first transistor and a second transistor, a channel structure of the first transistor and a channel structure of the second transistor. The channel structures all extend along the third direction; wherein, the first direction and the second direction are any two directions in the plane where the substrate is located, and the third direction is consistent with the plane where the substrate is located. Planes intersect.
9. The method of claim 8, wherein the transistor structure is formed by:

   Form first source electrodes and second source electrodes spaced apart along the first direction on the surface of the substrate;

   Forming a first channel structure and a second channel structure on the surfaces of the first source electrode and the second source electrode respectively;

   Forming a first drain electrode and a second drain electrode on top of the first channel structure and the second channel structure respectively;

   A common gate structure is formed between the first channel structure and the second channel structure.
10. The method of claim 9, wherein the first channel structure and the second channel structure are formed by:

    Forming a first epitaxial layer and a second epitaxial layer on the surfaces of the first source electrode and the second source electrode respectively;

    Forming a mask layer in the gap between the first source electrode and the second source electrode, and between the first epitaxial layer and the second epitaxial layer;

    Forming a third epitaxial layer and a fourth epitaxial layer covering part of the mask layer on the surfaces of the first epitaxial layer and the second epitaxial layer respectively;

    The third epitaxial layer and the fourth epitaxial layer are patterned to form the first channel structure and the second channel structure correspondingly.
11. The method of claim 10 , wherein along the first direction, the size of the third epitaxial layer formed is larger than the size of the first epitaxial layer, and the size of the fourth epitaxial layer formed is larger than that of the first epitaxial layer. The size of the second epitaxial layer.
12. The method of claim 11, wherein patterning the third epitaxial layer and the fourth epitaxial layer includes:

    Etch and remove part of the sidewalls of the third epitaxial layer and the fourth epitaxial layer to form at least one convex surface on the two opposite sidewall surfaces between the third epitaxial layer and the fourth epitaxial layer. part and/or at least one recess;

    Wherein, the first epitaxial layer and the remaining third epitaxial layer form the first channel structure, and the second epitaxial layer and the remaining fourth epitaxial layer form the second channel structure.
13. The method of claim 12, wherein after patterning the third epitaxial layer and the fourth epitaxial layer, the method further includes:

    Remove the mask layer;

    forming an isolation layer between the remaining third epitaxial layer and the remaining fourth epitaxial layer;

    Ion implantation is performed on the tops of the third epitaxial layer and the fourth epitaxial layer to form the first drain electrode and the second drain electrode respectively.
14. The method of claim 13, wherein the first source electrode, the first channel structure and the first drain electrode together form a first active region, the second source electrode, the first drain electrode The two-channel structure and the second drain together constitute a second active region; the method further includes:

    Remove the isolation layer to expose sidewall surfaces of the first active region and the second active region, and form a gate dielectric layer on the exposed sidewall surfaces;

    A first insulating layer, a gate conductive layer and a second insulating layer are formed in sequence from bottom to top between the first active area having the gate dielectric layer and the second active area having the gate dielectric layer.
15. The method of claim 14, wherein the method further includes:

    forming a first conductive line electrically connected to the first drain electrode and the second drain electrode;

    Second conductive lines, third conductive lines and a plurality of conductive plugs are formed, the first source electrode is electrically connected to the second conductive line through the conductive plugs, and the second source electrode passes through the conductive plugs. Electrically connect the third conductive wire.
16. A layout structure, including: a source layer, a channel layer, and a drain layer arranged sequentially from bottom to top. The source layer includes a plurality of first source electrodes and arrays arranged in a first direction and a second direction. A plurality of second source electrodes, the channel layer includes a plurality of first channel structures and a plurality of second channel structures arranged in an array along the first direction and the second direction, the first channel The channel structure and the second channel structure both extend along the third direction, and the drain layer includes a plurality of first drain electrodes and a plurality of second drain electrodes arranged in an array along the first direction and the second direction. drain;

    Along the first direction, the first source electrodes and the second source electrodes are alternately arranged at intervals; along the second direction, a plurality of the first source electrodes are arranged at intervals, and a plurality of the first source electrodes are arranged at intervals. Two sources are arranged at intervals;

    Each of the first source electrodes is electrically connected to two of the first channel structures, and each of the second source electrodes is electrically connected to two of the second channel structures; each of the first channels is electrically connected to The top of the structure is electrically connected to one of the first drain electrodes, and the top of each of the second channel structures is electrically connected to one of the second drain electrodes; wherein the third direction is connected to the first direction and the The plane on which the second direction lies intersects.
17. The layout structure according to claim 16, wherein the layout structure further includes: a gate layer located on the same layer as the channel layer, the gate layer at least includes a plurality of gate conductive layers, the gate The gate conductive layer extends along the second direction; a row of first channel structures and a row of second channel structures adjacently arranged along the first direction share one gate conductive layer.
18. The layout structure according to claim 16, wherein the layout structure further includes: a conductive layer located above the drain layer, the conductive layer includes first conductive lines, second conductive lines and third conductive lines arranged at intervals. conductive thread;

    Along the first direction, two adjacent first drain electrodes and the second drain electrode are electrically connected to the same first conductive line;

    Along the second direction, two adjacent first source electrodes are electrically connected to the same second conductive line through a conductive plug, and two adjacent second source electrodes are electrically connected through a conductive plug. Connect the same third conductive wire.

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