WO2024060333A1 - Semiconductor structure and method for forming same - Google Patents
Semiconductor structure and method for forming same Download PDFInfo
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- WO2024060333A1 WO2024060333A1 PCT/CN2022/124658 CN2022124658W WO2024060333A1 WO 2024060333 A1 WO2024060333 A1 WO 2024060333A1 CN 2022124658 W CN2022124658 W CN 2022124658W WO 2024060333 A1 WO2024060333 A1 WO 2024060333A1
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- layer
- isolation
- semiconductor
- active
- isolation structure
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- 238000000034 method Methods 0.000 title claims abstract description 117
- 238000002955 isolation Methods 0.000 claims abstract description 355
- 239000000758 substrate Substances 0.000 claims abstract description 112
- 229910052751 metal Inorganic materials 0.000 claims description 36
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- 238000005530 etching Methods 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 description 42
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.
- DRAM dynamic random access memory
- a groove is formed by etching the bottom of the active pillar, and the bit line metal material is filled in the groove to form a buried bit line structure. Therefore, in the related art, it is easy to etch the active pillar during the etching process. causing the active column to collapse.
- embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
- an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
- a substrate is provided, the substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any direction in the plane where the substrate is located. both directions;
- An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap within the projection area along the second direction;
- bit line structure is formed.
- the base includes a substrate, and a first isolation layer located on a surface of the substrate;
- the first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
- the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer;
- the active strip is located on the surface of the first N-type semiconductor layer.
- the first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps:
- the second initial semiconductor layer is heavily doped a second time to form the first N-type semiconductor layer.
- the substrate is a P-type doped substrate
- the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate
- the first P-type semiconductor layer is located on the third The surface of the two N-type semiconductor layers.
- the active strip includes a third semiconductor layer located within a projection area of the first gap along the second direction, and after forming the isolation structure, the method further include:
- the bit line structure is formed in the second gap.
- the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; the isolation structure Formed through the following steps:
- the first initial isolation structure is etched back to form the first U-shaped isolation structure; and the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.
- the method further includes:
- the active strip in the projection area of the bit line structure along the second direction is doped to form a drain portion.
- the method further includes:
- bit line structure and the active strip are heat treated to form metal silicide located between the bit line structure and the active strip.
- the method further includes:
- a third isolation structure is formed on the surface of the bit line structure and the surface of the second isolation structure;
- the top surface of the third isolation structure does not exceed the top surface of the active strip.
- a fourth isolation structure is formed on the surface of the third isolation structure
- the top surface of the fourth isolation structure is flush with the top surface of the active strip.
- the active strip and the first trench are formed by the following steps:
- a first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction. , the first sub-pattern exposes part of the semiconductor active layer;
- the exposed portion of the semiconductor active layer of the first sub-pattern is removed to form active strips extending along the first direction and alternately arranged along the second direction. and the first trench.
- the method further includes: forming a second mask layer with a second pattern on the surface of the active strip and the fourth isolation structure;
- the second pattern includes: A plurality of second sub-patterns extending and arranged along the first direction, the second sub-patterns exposing part of the active strip and part of the fourth isolation structure;
- the active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched, or the active strips exposed by the second sub-pattern are etched.
- the source strip and all the fourth isolation structures form second trenches and active isolation layers alternately arranged along the first direction; wherein the size of the second trench along the third direction is less than or equal to the The initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etchings arranged alternately along the second direction.
- the active pillars are insulated from each other;
- a word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.
- the method further includes: doping a portion of the active pillar located outside the projection area of the word line structure along the first direction to form a source portion;
- a capacitor structure connected to the source portion is formed on a top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence.
- embodiments of the present disclosure provide a semiconductor structure, which includes:
- a substrate comprising a drain portion and an isolation structure extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within a plane where the substrate is located;
- a bit line structure is located between the isolation structure and the drain portion.
- the base includes a substrate, and a first isolation layer located on a surface of the substrate;
- the first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
- the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the drain portion located on the surface of the first N-type semiconductor layer.
- the substrate is a P-type doped substrate
- the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate
- the first P-type semiconductor layer is located on the surface of the substrate. the surface of the second N-type semiconductor layer.
- the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure, and the third isolation structure The top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure;
- the first U-shaped isolation structure and the second isolation structure are both in contact with the bit line structure.
- the semiconductor structure further includes:
- a third isolation structure is located on the surface of the bit line structure and the second isolation structure.
- the semiconductor structure further includes:
- the semiconductor structure further includes: active pillars located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and an array located on the active pillar. sidewalls, and word line structures arranged along the first direction and extending along the second direction;
- the top surface of the word line structure does not exceed the top surface of the active pillar.
- the semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion;
- the source portion is located outside the projection area of the active pillar along the second direction;
- the capacitive structure is located on the top surface of the active pillar, and the capacitive structure includes a first electrode layer, a dielectric layer and a second electrode layer.
- part of the bit line structure is located within the projection area of the active pillar along the third direction, or the bit line structure is located within the projection area of the active pillar along the third direction. outside;
- the third direction intersects with the plane where the base is located.
- the active strip does not need to be etched. In this way, the active strip can be made less likely to collapse, thereby making the semiconductor structure Strong stability during the formation process.
- the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
- Figure 1 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure
- Figures 2a to 2o are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure.
- 3a to 3g are structural schematic diagrams of another semiconductor structure forming process provided by embodiments of the present disclosure.
- FIG. 4 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
- the three directions may include the X-axis, Y-axis, and Z-axis directions.
- the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction of intersection (eg, perpendicular) with the top and bottom surfaces of the substrate is defined as third direction.
- the direction of the top surface and the bottom surface of the substrate that is, the plane on which the substrate is located
- two directions that intersect each other for example, are perpendicular to each other
- the direction in which the bit line structure extends can be defined as the first direction, and the direction in which the bit line structure is arranged can be defined.
- the direction is a second direction, and the plane direction of the substrate can be determined based on the first direction and the second direction.
- the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular to each other.
- the first direction is defined as the X-axis direction
- the second direction is defined as the Y-axis direction
- the third direction is defined as the Z-axis direction.
- FIG. 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 1, the method for forming a semiconductor structure includes the following steps:
- Step S101 Provide a substrate, which includes active strips and first trenches extending along a first direction and alternately arranged along a second direction.
- the substrate at least includes a semiconductor substrate.
- the semiconductor substrate may be a silicon substrate.
- the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or a semiconductor compound, such as silicon carbide (SiC). ), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys such as silicon germanium (SiGe) , gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide ( GaInAsP) or a combination thereof.
- germanium germanium
- SiC silicon carbide
- the substrate includes a substrate, and a first isolation layer located on the surface of the substrate; the first isolation layer may include a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer are used to isolate the bit lines. Structure and substrate.
- the first isolation layer may include a semiconductor isolation layer, or the first isolation layer may include an insulating layer, or the first isolation layer may include a semiconductor isolation layer and an insulating layer; wherein, when the first isolation layer includes a semiconductor isolation layer and an insulating layer , the insulating layer may be located on the surface of the semiconductor isolation layer, and the semiconductor isolation layer may also be located on the surface of the insulating layer.
- the material of the insulating layer may be silicon oxide, or other suitable materials.
- the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the active strip is located on the surface of the first N-type semiconductor layer.
- the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction.
- the PN junction is reverse biased and will not be turned on, thereby preventing leakage of the bit line structure.
- the substrate may be a P-type doped silicon substrate
- the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate
- the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer. surface.
- the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction
- the second N-type semiconductor layer and the P-type doped silicon substrate form another PN junction. In this way, the bit line structure is applied At high voltage, both PN junctions are reverse biased, which can more effectively prevent leakage of the bit line structure.
- the active strip may include a third semiconductor layer located within a projection area of the first gap along the second direction, and the third semiconductor layer may be a silicon germanium layer.
- Step S102 Form an isolation structure extending along the first direction at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area along the second direction.
- the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; wherein the first U-shaped isolation structure is used to isolate the subsequently formed bit line structure from the substrate to prevent leakage; and the second isolation structure is used to isolate two adjacent isolation structures subsequently formed.
- Step S103 Form a bit line structure in the first gap.
- a bit line structure can be formed by depositing bit line conductive materials in the first gap; wherein the bit line conductive materials include: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al ), titanium nitride (TiN), titanium-containing metal layers, polysilicon, or any combination thereof.
- the method for forming a semiconductor structure does not require etching the active strip during the formation process of the buried bit line structure. In this way, the active strip is less likely to collapse, thereby making the semiconductor structure less susceptible to collapse during the formation process.
- the stability in the medium is strong.
- the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
- FIGS. 2a to 2o are schematic structural diagrams of the semiconductor structure formation process provided by the embodiment of the present disclosure.
- the formation process of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2a to 2o.
- Figure 2h is a cross-sectional view along c-c'
- Figure 2i is a cross-sectional view along a-a'
- b-b' and d-d' in Figure 2h
- Figure 2l is a cross-sectional view along a-a'
- Figure 2n is a cross-sectional view along e-e' and c-c' in Figure 2l
- Figure 2n is a cross-sectional view along b-b' and d-d' in Figure 2m.
- step S101 is performed to provide a substrate.
- the substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction.
- the base includes a substrate 10 and a first isolation layer located on the surface of the substrate 10, wherein the first isolation layer includes a semiconductor isolation layer 11, and the semiconductor isolation layer 11 includes a first P layer located on the surface of the substrate 10. type semiconductor layer 11a and the first N-type semiconductor layer 11b located on the surface of the first P-type semiconductor layer 11a.
- the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.
- the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b may be formed by the following steps: forming a first initial semiconductor layer (not shown) on the surface of the substrate 10; Perform the first heavy doping to form the first P-type semiconductor layer 11a; form a second initial semiconductor layer (not shown) on the surface of the first P-type semiconductor layer; perform the second heavy doping on the second initial semiconductor layer, The first N-type semiconductor layer 11b is formed.
- the first heavily doped doping element may be a Group III element, such as a trivalent impurity element such as boron, gallium, indium, etc.; the second heavily doped element may be a Group V element, For example, they are pentavalent impurity elements such as phosphorus, antimony, and arsenic.
- the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, the bit line structure is close to the N end of the PN junction.
- the PN junction When a high voltage is applied to the line structure, the PN junction is reverse biased and will not conduct. Since the reverse resistance of the PN junction is very high, this can isolate the bit line structure and the substrate and prevent leakage of the bit line structure.
- FIGS. 2b to 2o For ease of understanding, only the semiconductor isolation layer 11 is shown in FIGS. 2b to 2o , and the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b in the semiconductor isolation layer 11 are not shown.
- the active strip and the first trench may be formed by the following steps: forming a semiconductor active layer on the surface of the first N-type semiconductor layer; forming a first pattern with a first pattern on the surface of the semiconductor active layer.
- Mask layer the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction, and the first sub-pattern exposes part of the semiconductor active layer; through the first mask layer, the first sub-pattern is removed The portion of the semiconductor active layer exposed by the sub-pattern forms active strips and first trenches extending along the first direction and alternately arranged along the second direction.
- a semiconductor active layer 12a is formed on the surface of the first N-type semiconductor layer (ie, the semiconductor isolation layer 11).
- the semiconductor active layer 12a can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or other suitable processes.
- CVD chemical vapor deposition
- PVD Physical vapor deposition
- ALD atomic layer deposition
- a first mask layer 25 having a first pattern is formed on the surface of the semiconductor active layer 12a; the first pattern includes a plurality of first patterns extending along the X-axis direction and arranged along the Y-axis direction.
- a sub-pattern E, the first sub-pattern E exposes part of the semiconductor active layer 12a; through the first mask layer 25, the part of the semiconductor active layer 12a exposed by the first sub-pattern E is removed, forming a And the active strips 12 and the first trenches 13 are alternately arranged along the Y-axis direction.
- the material of the first mask layer 25 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the first mask layer 25 may be made of any suitable material. Formed by deposition process.
- the method of forming the semiconductor structure further includes: removing the first mask layer 25 to expose the upper surface of the active strip 12 .
- step S102 to form an isolation structure extending along the first direction at the bottom of the first trench; wherein, the isolation structure and the active strip have a first projection area along the second direction. gap.
- the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure;
- the isolation structure can be formed by the following steps: The surface of the source bar and the inner wall of the first trench form a first initial isolation structure; a second isolation structure is formed at the bottom of the first trench with the first initial isolation structure; and the first initial isolation structure is carved back to form a first U-shape Isolation structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.
- a first isolation material is deposited on the surface of the active strip 12 and the inner wall of the first trench 13 to form a first initial isolation structure 14a; the first isolation material may be silicon oxide, or other suitable materials.
- a second isolation material is deposited in the first trench 13 with the first initial isolation structure 14a to form a second initial isolation structure (not shown); the second initial isolation structure is etched back to form a second Isolation structure 15; the second isolation material may be silicon nitride, or other suitable materials.
- the etching selectivity ratio between the second isolation material and the substrate is greater than the etching selectivity ratio between the first isolation material and the substrate, for example , the etching selectivity ratio between the second isolation material and the substrate is 3 to 10 times the etching selectivity ratio between the first isolation material and the substrate. In this way, the second initial isolation structure can be etched back without damaging it. First initial isolation structure 14a.
- the first initial isolation structure 14a and the second initial isolation structure may be formed through any suitable deposition process.
- the first initial isolation structure 14a (refer to Figure 2f) is etched back to form the first U-shaped isolation structure 14, which can be achieved by a dry etching process (such as a plasma etching process, a reactive ion etching process or an ion etching process). milling process) to engrave back the first initial isolation structure.
- a dry etching process such as a plasma etching process, a reactive ion etching process or an ion etching process. milling process to engrave back the first initial isolation structure.
- the top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14 .
- the isolation structure is in a convex shape, and a first gap 16 a is present in the projection area between the isolation structure (ie, the second isolation structure 15 ) and the active strip 12 along the Y-axis direction.
- the etching selectivity ratio between the first isolation material and the substrate is greater than the etching selectivity ratio between the second isolation material and the substrate, for example , the etching selectivity ratio between the first isolation material and the substrate is 5 to 10 times the etching selectivity ratio between the second isolation material and the substrate. In this way, it is not necessary to etch back the first initial isolation structure 14a. The second isolation structure 15 is damaged.
- the first U-shaped isolation structure 14 located in the convex-shaped isolation structure is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure;
- the second isolation structure 14 located in the convex-shaped isolation structure 15 is used to isolate two adjacent bit line structures located in the same first trench 13 to prevent leakage of the bit line structures, thereby improving the electrical performance of the semiconductor structure.
- the first U-shaped isolation structure may also be a semiconductor isolation layer, or the first U-shaped isolation structure may also be a composite isolation structure composed of a semiconductor isolation layer and an insulating layer (for example, an oxide layer).
- step S103 is performed to form a bit line structure in the first gap.
- bit line metal material is deposited in the first trench 13 with an isolation structure to form an initial bit line structure (not shown), and the initial bit line structure is etched back to form a bit line structure 16 .
- the bit line metal material includes: tungsten, cobalt, copper, aluminum, titanium nitride, titanium-containing metal layer, polysilicon or any combination thereof.
- the initial bit line structure can be etched back through a dry etching process to form the bit line structure 16 .
- top surface of the bit line structure 16 in the embodiment of the present disclosure does not exceed the top surface of the second isolation structure 15 .
- the top surface of bit line structure 16 may be flush with the top surface of second isolation structure 15 .
- the method of forming the semiconductor structure further includes: removing residual metal located in the first trench 13 through a wet etching process.
- the method of forming the semiconductor structure further includes: thermally oxidizing and growing silicon oxide of a predetermined thickness on the surfaces of the second isolation structure 15 and the bit line structure 16 , silicon oxide is used to further remove residual metal on the sidewalls of the active strip 12 to prevent silicide from forming on the surface of the channel structure during subsequent processes.
- the preset thickness may be 1 to 5 nanometers (nm).
- the method of forming the semiconductor structure further includes: covering the surface of the bit line structure and the surface of the isolation structure to form a third isolation structure; wherein the top surface of the third isolation structure does not exceed the active The top surface of the strip.
- a third isolation material is deposited on the surface of the bit line structure 16 and the second isolation structure 15 to form the third isolation structure 17.
- the third isolation material may be silicon oxide, silicon oxynitride, or other suitable materials. .
- a third isolation material can be deposited through an atomic deposition process to form the third isolation structure 17 to improve the quality of the film layer.
- the method of forming the semiconductor structure further includes: performing heat treatment on the bit line structure 16 and the active strip 12 to form a layer between the bit line structure 16 and the active strip 12 .
- Metal silicide 19 between source bars 12 is not limited to:
- the bit line metal material and the active strip 12 can react with each other through a Rapid Thermal Processing (RTP) process, thereby forming metal silicide 19 on the surface of the active strip 12 . Since the metal silicide has a lower resistance, the contact resistance between the bit line structure 16 and the active strip 12 can be reduced, thereby reducing the power consumption of the semiconductor structure.
- RTP Rapid Thermal Processing
- the formation method of the semiconductor structure also includes: doping the active strip 12 in the projection area of the bit line structure along the Y-axis direction to form a drain portion 26. 26 can be used as the drain D of the transistor structure.
- ions are implanted into the active strip 12 in the projection area of the bit line structure along the Y-axis direction to form the drain D.
- Ion implantation can be achieved through processes such as thermal diffusion and plasma doping.
- the energy and dosage used in the ion implantation process and the type of implanted ions can be determined according to the type of transistor to be formed, for example, P-type metal oxide semiconductor ( P-Metal-Oxide-Semiconductor (PMOS) can perform shallow-depth, heavily doped BF 2+ ion implantation; N-type metal-oxide semiconductor (N-Metal - Oxide-Semiconductor, NMOS) can perform shallow-depth, heavily doped Arsenic ion implantation.
- a high-temperature annealing process can also be included, which can repair the lattice damage caused by the ion implantation and activate the ion-implanted impurities.
- the order in which the drain D, the metal silicide 19 and the third isolation structure 17 are formed is not limited.
- the drain D may be formed first, then the third isolation structure 17 may be formed, and finally Form the metal silicide 19; you can also form the metal silicide 19 first, then form the third isolation structure 17, and finally form the drain D; you can also form the drain D first, then form the metal silicide 19, and finally form the third isolation structure 17.
- the method for forming a semiconductor structure further includes: forming a fourth isolation structure on a surface of the third isolation structure; wherein a top surface of the fourth isolation structure is flush with a top surface of the active strip.
- a fourth isolation material is deposited on the surface of the third isolation structure 17 to form a fourth isolation structure 18.
- the fourth isolation material may be silicon oxide, silicon oxynitride or other suitable materials.
- the third isolation material The material and the fourth isolation material may be the same or different.
- CMP Chemical Mechanical Polishing
- the method of forming the semiconductor structure further includes forming a word line structure, a source portion, and a capacitor structure.
- the word line structure may be formed by the following steps: forming a second mask layer with a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern includes extending along the second direction and extending along the second direction. A plurality of second sub-patterns are arranged in one direction, and the second sub-pattern exposes part of the active strip and part of the fourth isolation structure; through the second mask layer, the active strip and part of the fourth isolation structure exposed by the second sub-pattern are etched.
- the second trench is The size in the third direction is less than or equal to the initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etched pillars alternately arranged along the second direction.
- the fourth isolation structure; the active pillars are insulated from each other; a word line structure is formed on the side wall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.
- a second mask layer 27 with a second pattern is formed on the surface of the active strip 12 and the fourth isolation structure 18; the second pattern includes lines extending along the Y-axis direction and arranged along the X-axis direction.
- a plurality of second sub-patterns F, the second sub-pattern F exposes part of the active strip 12 and part of the fourth isolation structure 18; through the second mask layer 27, the part of the active strip exposed by the second sub-pattern F is etched 12 and part of the fourth isolation structure 18 until the third isolation structure 17 is exposed, forming second trenches 22a and active isolation layers 20 alternately arranged along the X-axis direction; wherein the second trenches 22a extend along the Y-axis direction.
- the active isolation layer 20 includes active pillars 21 alternately arranged along the Y-axis direction and etched fourth isolation structures 18.
- the active pillars 21 are insulated from each other by the fourth isolation structure 18.
- the size d1 of the second trench 22a in the Z-axis direction (as shown in FIG. 2l) is equal to the initial size d2 of the fourth isolation structure 18 in the Z-axis direction (as shown in FIG. 2m).
- part of the active strip 12 and part of the fourth isolation structure 18 exposed by the second sub-pattern F are etched through the second mask layer 27 to form second trenches 22a alternately arranged along the X-axis direction. and active isolation layer 20; wherein, the second trench 22a extends along the Y-axis direction, and the active isolation layer 20 includes an active pillar 21 and a fourth isolation located between two adjacent active pillars 21 along the Y-axis direction.
- the structure 18 and the active pillar 21 are insulated from each other by the fourth isolation structure 18.
- the size of the second trench 22a in the Z-axis direction is smaller than the initial size d2 of the fourth isolation structure 18 in the Z-axis direction.
- the material of the second mask layer 27 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the second mask layer 27 may be made of any suitable material. Formed by deposition process.
- the method of forming the semiconductor structure further includes: removing the second mask layer 27 having the second pattern.
- a gate dielectric layer 221 is sequentially deposited on the sidewall of the second trench 22a, and a gate conductive layer located on the surface of the gate dielectric layer 221, wherein the gate conductive layer can be used as a word
- the top surface of the line structure 22 and the word line structure 22 do not exceed the top surface of the active pillar.
- the active pillar 21 located in the projection area of the word line structure 22 along the X-axis direction forms a channel structure.
- the material of the gate dielectric layer 221 can be silicon oxide or other suitable materials; the material of the gate conductive layer can be any material with good conductivity, such as titanium (Ti), nitride, etc. Any one of titanium (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).
- the gate dielectric layer and the gate conductive layer can be formed by any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.
- the gate structure in the embodiment of the present disclosure is a double gate structure.
- the etched fourth isolation structure 18 between the active pillars 21 can also be removed.
- the surface of 21 forms a full ring gate structure.
- the method of forming the semiconductor structure further includes: depositing a fifth isolation material in the second trench 22a having the word line structure 22 to form a fifth isolation structure 23.
- the isolation material may be silicon oxide or other suitable materials, and the fifth isolation structure 23 is used to isolate two adjacent word line structures 22 .
- the method of forming the semiconductor structure further includes: performing ion implantation on the active pillar 21 outside the projection area of the word line structure 22 along the X-axis direction to form a source electrode. part, wherein the source part may serve as the source S of the transistor structure.
- the source and drain in the embodiment of the present disclosure are located on both sides of the channel structure along the third direction. That is, the transistor structure in the embodiment of the present disclosure is vertical.
- the vertical transistor structure (or channel structure) can
- the semiconductor structure has a higher arrangement density. In this way, the integration level of the semiconductor structure can be improved and shrinkage can be achieved.
- a capacitor structure connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence.
- a capacitor structure 24 connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer 241 , a dielectric layer 242 , and a second electrode layer 243 stacked in sequence.
- the material of the first electrode layer 241 and the material of the second electrode layer 243 may include metal nitride or metal silicide, for example, titanium nitride.
- the material of the dielectric layer 242 may include a high-K dielectric material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), or hafnium silicate.
- lanthanum oxide La 2 O 3
- Al 2 O 3 aluminum oxide
- hafnium oxynitride (HfON) hafnium silicate.
- hafSiO x hafnium oxide
- ZrO 2 zirconium oxide
- the first electrode layer 241, the dielectric layer 242 and the second electrode layer 243 can be formed by any one of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.
- the method for forming a semiconductor structure does not require etching the active strip during the formation process of the buried bit line structure. In this way, the active strip can be less likely to collapse, thereby making the semiconductor structure less susceptible to collapse during the formation process.
- the stability in the medium is strong.
- the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
- 3a to 3g are structural schematic diagrams of the formation process of another semiconductor structure provided by an embodiment of the present disclosure.
- the formation process of another semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 3a to 3g.
- active strips 12 and first trenches 13 are formed extending along the X-axis direction and alternately arranged along the Y-axis direction.
- the base includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10.
- the semiconductor isolation layer 11 includes a first P-type semiconductor layer 11a located on the surface of the substrate 10 and a first P-type semiconductor layer 11a located on the surface of the substrate 10.
- the first N-type semiconductor layer 11b on the surface of 11a.
- FIGS. 3b to 3g For ease of understanding, only the semiconductor isolation layer 11 is shown in FIGS. 3b to 3g , and the first P-type semiconductor layer 11 a and the first N-type semiconductor layer 11 b in the semiconductor isolation layer 11 are not shown.
- the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the subsequently formed bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction, so , when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct, thus preventing leakage of the bit line structure.
- a first semiconductor active layer 121a, a third initial semiconductor layer 122a, and a second semiconductor active layer 123a are sequentially formed;
- the semiconductor active layer 121a, the third initial semiconductor layer 122a, and the second semiconductor active layer 123a constitute the semiconductor active layer 12a.
- the first semiconductor active layer 121a and the second semiconductor active layer 123a may be silicon layers, and the third initial semiconductor layer 122a may be a silicon germanium layer.
- the semiconductor active layer 12 a is etched to form active strips 12 and first trenches 13 extending along the X-axis direction and alternately arranged along the Y-axis direction.
- the active strip 12 includes a first active strip 121, a third semiconductor layer 122, and a second active strip 123 arranged in sequence from bottom to top along the Z-axis direction.
- a first initial isolation structure 14a is formed on the surface of the active strip 12 and the inner wall of the first trench 13; a second initial isolation structure 14a is formed in the first trench 13 having the first initial isolation structure 14a.
- Initial isolation structure (not shown); etching back the second initial isolation structure to form second isolation structure 15 .
- the first initial isolation structure 14a is etched back to form the first U-shaped isolation structure 14.
- the second isolation structure 15 and the first U-shaped isolation structure 14 together form an isolation structure.
- the isolation structure and the third semiconductor layer 122 have a first gap 16a in the projection area along the second direction.
- the first U-shaped isolation structure 14 is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 15 is used to isolate the phases located in the same first trench 13 There are two adjacent bit line structures to prevent leakage of the bit line structure.
- the method of forming the semiconductor structure also includes: laterally etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third semiconductor layer are etched laterally in the second direction.
- the three sub-semiconductor layer has a second gap in the projection area along the second direction, and the second gap includes the first gap; a bit line structure is formed in the second gap.
- the third semiconductor layer 122 is laterally etched along the Y-axis direction to form the third sub-semiconductor layer 28; wherein, the isolation structure is a convex shape, and the isolation structure (or the second isolation structure 15) and The third sub-semiconductor layer 28 has a second gap 16b in the projection area along the Y-axis direction.
- the second gap 16b includes the first gap 16a; the bit line structure 16 is formed in the second gap 16b.
- the isolation structure is in a convex shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structure and the substrate to prevent leakage and improve the electrical performance of the semiconductor structure.
- a wet etching process can be used to laterally etch the third semiconductor layer 122 to form the third sub-semiconductor layer 28;
- the wet etching solution can be hydrofluoric acid (DHF) or diluted
- the mixed solution of hydrofluoric acid and ammonia (NH 4 OH) may also be a mixed solution of diluted hydrofluoric acid and tetramethylammonium hydroxide (TMAH).
- the method of forming the semiconductor structure further includes: rapidly performing a quick process on the bit line structure 16 , the first active strip 121 , the second active strip 123 , and the third sub-semiconductor layer 28 .
- the first metal silicide 191 , the second metal silicide 192 and the third metal silicide 193 constitute the metal silicide 19 .
- the metal silicide 19 since the metal silicide 19 has a lower resistance, the contact resistance between the bit line structure 16 and the second active strip 123 and the bit line structure 16 and the third sub-semiconductor layer can be reduced. In turn, the power consumption of the semiconductor structure can be reduced.
- a third isolation structure is formed covering the surface of the bit line structure 16 and the surface of the second isolation structure 15 .
- the method of forming the semiconductor structure further includes forming a drain portion, a word line structure, a source portion and a capacitor structure.
- the formation method of the drain part, word line structure, source part and capacitor structure in the embodiment of the present disclosure is similar to the formation method of the drain part, word line structure, source part and capacitor structure in the above embodiments.
- the method for forming a semiconductor structure does not require complete etching of the active strip during the formation process of the buried bit line structure. In this way, the active strip is less likely to collapse, and the active strip can be
- a bit line structure is formed between the third sub-semiconductor layer in the strip and the isolation structure, and part of the bit line structure is located in the projection area of the first active strip along the third direction, thus improving the production yield of the semiconductor structure.
- the method of forming a semiconductor structure provided by the embodiments of the present disclosure is similar to the method of forming the semiconductor structure in the above-mentioned embodiments.
- technical features that are not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding, and will not be described again here.
- the embodiment of the present disclosure further provides a semiconductor structure, which is formed by the method for forming the semiconductor structure in the above embodiment.
- Figure 4 is a structural schematic diagram of a semiconductor structure provided by the embodiment of the present disclosure.
- the semiconductor structure 100 includes: a substrate, the substrate includes a drain portion 26 and an isolation structure extending along the X-axis direction and alternately arranged along the Y-axis direction; a bit line structure 16, located between the isolation structure and the drain portion 26, and the drain portion 26 can serve as the drain D of the transistor structure.
- the substrate includes a substrate, and a first isolation layer located on the surface of the substrate; the first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or insulating layer is used to isolate the bit line structure. with substrate.
- the base includes a substrate 10 and a first isolation layer located on the surface of the substrate 10 , wherein the first isolation layer includes a semiconductor isolation layer 11 .
- the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.
- the semiconductor isolation layer 11 is used to isolate the bit line structure 16 and the substrate 10; the semiconductor isolation layer at least includes a first P-type semiconductor layer 11a located on the surface of the substrate and a first P-type semiconductor layer 11a located on the surface of the substrate.
- the first N-type semiconductor layer 11b is located on the surface of the N-type semiconductor layer 11a; the drain portion 26 is located on the surface of the first N-type semiconductor layer 11b.
- the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, the bit line structure is close to the N end of the PN junction.
- the PN junction is reverse biased and will not conduct. In this way, leakage of the bit line structure can be prevented.
- the substrate 10 is a P-type doped substrate
- the semiconductor isolation layer 11 may also include a second N-type semiconductor layer located on the surface of the substrate 10
- the first P-type semiconductor layer is located on the second N-type semiconductor layer. s surface.
- the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction
- the second N-type semiconductor layer and the P-type doped silicon substrate form another PN junction. In this way, the bit line structure is applied At high voltage, both PN junctions are reverse biased, which can more effectively prevent leakage of the bit line structure.
- the isolation structure is convex-shaped, and the isolation structure includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the U-shaped bottom surface of the first U-shaped isolation structure 14, And the top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.
- the isolation structure is in a convex shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structure and the substrate to prevent leakage and improve the electrical performance of the semiconductor structure.
- the semiconductor structure 100 further includes: a third isolation structure 17 , the third isolation structure 17 is located on the surface of the bit line structure 16 and the surface of the second isolation structure 15 .
- the semiconductor structure 100 further includes: a metal silicide 19 located between the bit line structure 16 and the drain portion 26 . Since the metal silicide 19 has a low resistance, the contact resistance between the bit line structure 16 and the drain portion 26 can be reduced, thereby reducing the power consumption of the semiconductor structure.
- the semiconductor structure 100 also includes: an active pillar 21 located on the surface of the drain portion 26 and arranged in an array along the X-axis direction and the Y-axis direction, and a word line structure 22 located on the side wall of the active pillar 21, arranged along the X-axis direction and extending along the Y-axis direction; wherein the top surface of the word line structure 22 does not exceed the top surface of the active pillar 21.
- the semiconductor structure 100 further includes: a fourth isolation structure 18.
- the active pillars 21 and the fourth isolation structures 18 alternately arranged in the Y-axis direction constitute the active isolation layer 20. In other embodiments, the fourth isolation structure 18 may not be included.
- the bit line structure 16 is located outside the projection area of the active pillar 21 along the Z-axis direction.
- the semiconductor structure 100 further includes: a gate structure, the gate structure includes a gate conductive layer on the surface of the gate dielectric layer 221 , wherein the gate conductive layer can serve as the word line structure 22 .
- the semiconductor structure 100 further includes: a source portion and a capacitor structure 24 connected to the source portion.
- the source portion is located within the projection area of the active pillar 21 along the Y-axis direction. Outside; wherein, the source portion can be used as the source S of the transistor structure.
- the capacitive structure 24 is located on the top surface of the active pillar 21 , and the capacitive structure 24 includes a first electrode layer 241 , a dielectric layer 242 and a second electrode layer 243 .
- the semiconductor structure 100 further includes: a fifth isolation structure 23 , the fifth isolation structure 23 is located between the word line structures 22 adjacent to each other along the X-axis direction and between the source portions adjacent to each other along the X-axis direction.
- the semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure formed by the method of forming the semiconductor structure in the above embodiments.
- the semiconductor structure in the embodiment of the present disclosure includes a buried bit line structure.
- the bit line structure is located between the active strip and the isolation structure.
- the bottom of the active strip in the semiconductor structure provided by the embodiment of the present disclosure is at The bit line structure is not etched or completely etched during the formation process. In this way, embodiments of the present disclosure can provide a semiconductor structure with higher stability.
- Embodiments of the present disclosure also provide a semiconductor structure, which is formed by the formation method of the semiconductor structure in the above embodiment. Please continue to refer to FIG. 3g.
- the semiconductor structure includes: a substrate extending along the X-axis direction and alternately arranged along the Y-axis direction.
- the semiconductor structure further includes active pillars located on the surface of the drain portion 26 and arranged in an array along the X-axis direction and the Y-axis direction.
- the drain portion 26 includes a first active strip 121, a third sub-semiconductor layer (not shown in FIG. 3g) and a part of the second active strip 123.
- the semiconductor structure further includes a metal silicide 19.
- the metal silicide 19 includes a first metal silicide 191 between the bit line structure 16 and the first active strip 121.
- the bit line structure The second metal silicide 192 between 16 and the third sub-semiconductor layer, and the third metal silicide 193 between the bit line structure 16 and the second active strip 123 .
- Part of the bit line structure 16 is located in the projection area of the active pillar along the Z-axis direction.
- the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the U-shaped bottom surface of the first U-shaped isolation structure 14, and the The top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.
- the substrate includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10.
- the semiconductor isolation layer 11 is used to isolate the bit line structure 16 from the substrate 10; the semiconductor isolation layer 11 It includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer.
- the semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments.
- technical features that are not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding, and will not be described again here.
- the semiconductor structure in the embodiment of the present disclosure includes a buried bit line structure.
- the bit line structure is located between the third sub-semiconductor layer and the isolation structure in the active strip, and part of the bit line structure is located on the third side of the first active strip.
- the bottom of the active strip in the semiconductor structure provided by the embodiment of the present disclosure is not completely etched during the formation of the bit line structure. In this way, the embodiment of the present disclosure can provide a A highly stable semiconductor structure.
- the disclosed devices and methods can be implemented in a non-target manner.
- the device embodiments described above are only illustrative.
- the division of units is only a logical function division.
- the components shown or discussed are coupled to each other, or directly coupled.
- the active strip does not need to be etched. In this way, the active strip can be made less likely to collapse, thereby making the semiconductor structure Strong stability during the formation process.
- the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
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- Semiconductor Memories (AREA)
Abstract
Provided in the embodiments of the present disclosure are a semiconductor structure and a method for forming the same. The method comprises: providing a substrate, the substrate comprising active strips and first trenches extending in a first direction and alternately arranged in a second direction, and the first direction and the second direction being any two directions in a plane where the substrate is located; forming, at a bottom portion of the first trench, an isolation structure extending in the first direction, wherein the isolation structure and the active strip have a first gap in a projection region along the second direction; and forming a bit line structure in the first gap.
Description
相关申请的交叉引用Cross-references to related applications
本公开基于申请号为202211145434.1、申请日为2022年09月20日、发明名称为“半导体结构及其形成方法”的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本公开作为参考。This disclosure is based on a Chinese patent application with application number 202211145434.1, the filing date is September 20, 2022, and the invention name is "Semiconductor Structure and Formation Method Thereof", and claims the priority of the Chinese patent application. This disclosure is incorporated by reference in its entirety.
本公开涉及半导体技术领域,涉及但不限于一种半导体结构及其形成方法。The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.
当前,通过形成具有埋入式位线结构的动态随机存取存储器(Dynamic Random Access Memory,DRAM),以提高DRAM的集成度,实现微缩。Currently, a dynamic random access memory (DRAM) with a buried bit line structure is formed to improve the integration of DRAM and achieve miniaturization.
然而,相关技术中通过刻蚀有源柱的底部形成凹槽,并在凹槽中填充位线金属材料形成埋入式位线结构,因此,相关技术中在刻蚀有源柱的过程中容易导致有源柱倒塌。However, in the related art, a groove is formed by etching the bottom of the active pillar, and the bit line metal material is filled in the groove to form a buried bit line structure. Therefore, in the related art, it is easy to etch the active pillar during the etching process. causing the active column to collapse.
发明内容Contents of the invention
有鉴于此,本公开实施例提供一种半导体结构及其形成方法。In view of this, embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
第一方面,本公开实施例提供一种半导体结构的形成方法,所述方法包括:In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
提供基底,所述基底包括沿第一方向延伸、且沿第二方向交替排列的有源条和第一沟槽;所述第一方向和所述第二方向为所述基底所在平面内的任意两个方向;A substrate is provided, the substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any direction in the plane where the substrate is located. both directions;
在所述第一沟槽的底部形成沿所述第一方向延伸的隔离结构;其中,所述隔离结构与所述有源条沿所述第二方向投影区域内具有第一空隙;An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap within the projection area along the second direction;
在所述第一空隙中,形成位线结构。In the first gap, a bit line structure is formed.
在一些实施例中,所述基底包括衬底,以及位于所述衬底表面的第一隔离层;In some embodiments, the base includes a substrate, and a first isolation layer located on a surface of the substrate;
所述第一隔离层包括半导体隔离层和/或绝缘层,所述半导体隔离层和/或所述绝缘层用于隔离所述位线结构与所述衬底。The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
在一些实施例中,所述半导体隔离层至少包括位于衬底表面的第一P型半导体层和位于所述第一P型半导体层表面的第一N型半导体层;In some embodiments, the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer;
所述有源条位于所述第一N型半导体层的表面。The active strip is located on the surface of the first N-type semiconductor layer.
在一些实施例中,所述第一P型半导体层和所述第一N型半导体层通过以下步骤形成:In some embodiments, the first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps:
在所述衬底表面形成第一初始半导体层;Forming a first initial semiconductor layer on the surface of the substrate;
对所述第一初始半导体层进行第一重掺杂,形成所述第一P型半导体层;Perform a first heavy doping on the first initial semiconductor layer to form the first P-type semiconductor layer;
在所述第一P型半导体层的表面形成第二初始半导体层;Form a second initial semiconductor layer on the surface of the first P-type semiconductor layer;
对所述第二初始半导体层进行第二重掺杂,形成所述第一N型半导体层。The second initial semiconductor layer is heavily doped a second time to form the first N-type semiconductor layer.
在一些实施例中,所述衬底为P型掺杂的衬底,所述半导体隔离层还包括位于衬底表面的第二N型半导体层,所述第一P型半导体层位于所述第二N型半导体层的表面。In some embodiments, the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, and the first P-type semiconductor layer is located on the third The surface of the two N-type semiconductor layers.
在一些实施例中,所述有源条包括第三半导体层,所述第三半导体层位于所述第一 空隙沿所述第二方向的投影区域内,在形成隔离结构之后,所述方法还包括:In some embodiments, the active strip includes a third semiconductor layer located within a projection area of the first gap along the second direction, and after forming the isolation structure, the method further include:
沿所述第二方向刻蚀所述第三半导体层,形成第三子半导体层;其中,所述隔离结构与所述第三子半导体层沿所述第二方向投影区域内具有第二空隙,所述第二空隙包括所述第一空隙;Etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third sub-semiconductor layer have a second gap in the projection area along the second direction, the second gap includes the first gap;
在所述第二空隙中形成所述位线结构。The bit line structure is formed in the second gap.
在一些实施例中,所述隔离结构为凸字形,且所述隔离结构包括第一U型隔离结构和位于所述第一U型隔离结构U型底部表面的第二隔离结构;所述隔离结构通过以下步骤形成:In some embodiments, the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; the isolation structure Formed through the following steps:
在所述有源条的表面和所述第一沟槽的内壁,形成第一初始隔离结构;Form a first initial isolation structure on the surface of the active strip and the inner wall of the first trench;
在具有所述第一初隔离结构的第一沟槽底部形成所述第二隔离结构;forming the second isolation structure at the bottom of the first trench having the first initial isolation structure;
回刻所述第一初始隔离结构形成所述第一U型隔离结构;所述第二隔离结构的顶表面超出所述第一U型隔离结构的顶表面。The first initial isolation structure is etched back to form the first U-shaped isolation structure; and the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.
在一些实施例中,在形成所述位线结构之后,所述方法还包括:In some embodiments, after forming the bit line structure, the method further includes:
对所述位线结构沿所述第二方向投影区域内的所述有源条进行掺杂,形成漏极部。The active strip in the projection area of the bit line structure along the second direction is doped to form a drain portion.
在一些实施例中,在形成所述位线结构之后,所述方法还包括:In some embodiments, after forming the bit line structure, the method further includes:
对所述位线结构和所述有源条进行热处理,形成位于所述位线结构与所述有源条之间的金属硅化物。The bit line structure and the active strip are heat treated to form metal silicide located between the bit line structure and the active strip.
在一些实施例中,所述方法还包括:In some embodiments, the method further includes:
在所述位线结构表面和所述第二隔离结构表面覆盖形成第三隔离结构;A third isolation structure is formed on the surface of the bit line structure and the surface of the second isolation structure;
其中,所述第三隔离结构的顶表面未超出所述有源条的顶表面。Wherein, the top surface of the third isolation structure does not exceed the top surface of the active strip.
在一些实施例中,在所述第三隔离结构的表面形成第四隔离结构;In some embodiments, a fourth isolation structure is formed on the surface of the third isolation structure;
其中,所述第四隔离结构的顶表面与所述有源条的顶表面齐平。Wherein, the top surface of the fourth isolation structure is flush with the top surface of the active strip.
在一些实施例中,所述有源条和所述第一沟槽通过以下步骤形成:In some embodiments, the active strip and the first trench are formed by the following steps:
在所述第一N型半导体层的表面形成半导体有源层;forming a semiconductor active layer on a surface of the first N-type semiconductor layer;
在所述半导体有源层的表面形成具有第一图案的第一掩膜层;所述第一图案包括沿所述第一方向延伸、且沿所述第二方向排列的多个第一子图案,所述第一子图案暴露出部分所述半导体有源层;A first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction. , the first sub-pattern exposes part of the semiconductor active layer;
通过所述第一掩膜层,去除所述第一子图案暴露出的部分所述半导体有源层,形成沿所述第一方向延伸、且沿所述第二方向交替排列所述有源条和所述第一沟槽。Through the first mask layer, the exposed portion of the semiconductor active layer of the first sub-pattern is removed to form active strips extending along the first direction and alternately arranged along the second direction. and the first trench.
在一些实施例中,所述方法还包括:在所述有源条和所述第四隔离结构表面形成具有第二图案的第二掩膜层;所述第二图案包括沿所述第二方向延伸、且沿所述第一方向排列的多个第二子图案,所述第二子图案暴露出部分所述有源条和部分所述第四隔离结构;In some embodiments, the method further includes: forming a second mask layer with a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern includes: A plurality of second sub-patterns extending and arranged along the first direction, the second sub-patterns exposing part of the active strip and part of the fourth isolation structure;
通过所述第二掩膜层,刻蚀所述第二子图案暴露出的所述有源条和部分所述第四隔离结构,或者,刻蚀所述第二子图案暴露出的所述有源条和全部所述第四隔离结构,形成沿所述第一方向交替排列的第二沟槽和有源隔离层;其中,所述第二沟槽沿第三方向上的尺寸小于或者等于所述第四隔离结构在所述第三方向上的初始尺寸;所述第二沟槽沿所述第二方向延伸,所述有源隔离层包括沿所述第二方向交替排列的有源柱和刻蚀后的第四隔离结构;Through the second mask layer, the active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched, or the active strips exposed by the second sub-pattern are etched. The source strip and all the fourth isolation structures form second trenches and active isolation layers alternately arranged along the first direction; wherein the size of the second trench along the third direction is less than or equal to the The initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etchings arranged alternately along the second direction. The fourth isolation structure behind;
所述有源柱之间彼此绝缘;The active pillars are insulated from each other;
在所述第二沟槽的侧壁形成字线结构,所述字线结构的顶表面未超出所述有源柱的顶表面。A word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.
在一些实施例中,所述方法还包括:对位于所述字线结构沿所述第一方向投影区域之外的部分有源柱进行掺杂,形成源极部;In some embodiments, the method further includes: doping a portion of the active pillar located outside the projection area of the word line structure along the first direction to form a source portion;
在所述有源柱的顶表面形成与所述源极部连接的电容结构,其中,所述电容结构包括依次堆叠的第一电极层、电介质层和第二电极层。A capacitor structure connected to the source portion is formed on a top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence.
第二方面,本公开实施例提供一种半导体结构,所述半导体结构包括:In a second aspect, embodiments of the present disclosure provide a semiconductor structure, which includes:
基底,所述基底包括沿第一方向延伸、且沿第二方向交替排列的漏极部和隔离结构;所述第一方向和所述第二方向为所述基底所在平面内的任意两个方向;A substrate, the substrate comprising a drain portion and an isolation structure extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within a plane where the substrate is located;
位线结构,位于所述隔离结构与所述漏极部之间。A bit line structure is located between the isolation structure and the drain portion.
在一些实施例中,所述基底包括衬底,以及位于所述衬底表面的第一隔离层;In some embodiments, the base includes a substrate, and a first isolation layer located on a surface of the substrate;
所述第一隔离层包括半导体隔离层和/或绝缘层,所述半导体隔离层和/或所述绝缘层用于隔离所述位线结构与所述衬底。The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
在一些实施例中,所述半导体隔离层至少包括位于所述衬底表面的第一P型半导体层和位于所述第一P型半导体层表面的第一N型半导体层;所述漏极部位于所述第一N型半导体层的表面。In some embodiments, the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the drain portion located on the surface of the first N-type semiconductor layer.
在一些实施例中,所述衬底为P型掺杂的衬底,所述半导体隔离层还包括位于所述衬底表面的第二N型半导体层,所述第一P型半导体层位于所述第二N型半导体层的表面。In some embodiments, the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, and the first P-type semiconductor layer is located on the surface of the substrate. the surface of the second N-type semiconductor layer.
在一些实施例中,所述隔离结构为凸字形,且所述隔离结构包括第一U型隔离结构和位于所述第一U型隔离结构U型底部表面的第二隔离结构,且所述第二隔离结构的顶表面超出所述第一U型隔离结构的顶表面;In some embodiments, the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure, and the third isolation structure The top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure;
所述第一U型隔离结构和所述第二隔离结构均与所述位线结构相接触。The first U-shaped isolation structure and the second isolation structure are both in contact with the bit line structure.
在一些实施例中,所述半导体结构还包括:In some embodiments, the semiconductor structure further includes:
第三隔离结构,所述第三隔离结构位于所述位线结构和所述第二隔离结构表面。A third isolation structure is located on the surface of the bit line structure and the second isolation structure.
在一些实施例中,所述半导体结构还包括:In some embodiments, the semiconductor structure further includes:
位于所述位线结构与所述漏极部之间的金属硅化物。Metal suicide between the bit line structure and the drain portion.
在一些实施例中,所述半导体结构还包括:位于所述漏极部表面、且沿所述第一方向和所述第二方向阵列排布的有源柱、以及位于所述有源柱的侧壁、且沿所述第一方向排布、沿所述第二方向延伸的字线结构;In some embodiments, the semiconductor structure further includes: active pillars located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and an array located on the active pillar. sidewalls, and word line structures arranged along the first direction and extending along the second direction;
其中,所述字线结构的顶表面未超出所述有源柱的顶表面。Wherein, the top surface of the word line structure does not exceed the top surface of the active pillar.
在一些实施例中,所述半导体结构还包括:源极部、以及与所述源极部相接的电容结构;In some embodiments, the semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion;
所述源极部位于所述有源柱沿所述第二方向的投影区域之外;The source portion is located outside the projection area of the active pillar along the second direction;
所述电容结构位于所述有源柱的顶表面,且所述电容结构包括第一电极层、电介质层和第二电极层。The capacitive structure is located on the top surface of the active pillar, and the capacitive structure includes a first electrode layer, a dielectric layer and a second electrode layer.
在一些实施例中,部分所述位线结构位于所述有源柱沿第三方向的投影区域内,或者,所述位线结构位于所述有源柱沿所述第三方向的投影区域之外;In some embodiments, part of the bit line structure is located within the projection area of the active pillar along the third direction, or the bit line structure is located within the projection area of the active pillar along the third direction. outside;
所述第三方向与所述基底所在的平面相交。The third direction intersects with the plane where the base is located.
本公开实施例提供的半导体结构及其形成方法,其中,在埋入式位线结构的形成过程中,不用对有源条进行刻蚀,如此,可以使得有源条不易倒塌,从而使得半导体结构在形成过程中的稳定性较强。另外,本公开实施例中,通过在有源条与隔离结构之间的间隙中形成位线结构,可以简化埋入式位线结构的制备工艺过程,降低半导体结构的工艺复杂度。In the semiconductor structure and its formation method provided by embodiments of the present disclosure, during the formation process of the buried bit line structure, the active strip does not need to be etched. In this way, the active strip can be made less likely to collapse, thereby making the semiconductor structure Strong stability during the formation process. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
在附图(其不一定是按比例绘制的)中,相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例 而非限制的方式大体示出了本文中所讨论的各个实施例。In the drawings (which are not necessarily to scale), similar reference characters may describe similar components in the different views. Similar reference numbers with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example, and not limitation.
图1为本公开实施例提供的半导体结构形成方法的流程示意图;Figure 1 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure;
图2a~图2o为本公开实施例提供的半导体结构形成过程中的结构示意图;Figures 2a to 2o are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure;
图3a~图3g为本公开实施例提供的另一种半导体结构形成过程中的结构示意图;3a to 3g are structural schematic diagrams of another semiconductor structure forming process provided by embodiments of the present disclosure;
图4为本公开实施例提供的一种半导体结构的结构示意图。FIG. 4 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开,而不应被这里阐述的具体实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开公开的范围完整的传达给本领域的技术人员。Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that a thorough understanding of the disclosure will be provided, and the scope of the disclosure will be fully conveyed to those skilled in the art.
在下文的描述中,给出了大量的细节以便提供对本公开更为彻底的理解。然而,对于本领域技术人员而言显而易见的是,本公开可以无需一个或多个这些细节而得以实施。在其他的例子中,为了避免与本公开发生混淆,对于本领域公知的一些技术特征未进行描述;即,这里不描述实际实施例的全部特征,不详细描述公知的功能和结构。In the following description, numerous details are given in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features that are well known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.
在附图中,为了清楚,层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.
应当明白,当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其他元件或层时,其可以直接地在其他元件或层上、与之相邻、连接或耦合到其他元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其他元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本公开教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时,并不表明本公开必然存在第一元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer , adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily imply the presence of the first element, component, region, layer or section in the present disclosure.
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其他的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.
在介绍本公开实施例之前,先定义一下以下实施例可能用到的描述立体结构的三个方向,以笛卡尔坐标系为例,三个方向可以包括X轴、Y轴和Z轴方向。基底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面;在忽略顶表面和底表面的平整度的情况下,定义与基底顶表面和底表面的相交(例如垂直)的方向为第三方向。在基底的顶表面和底表面(即基底所在的平面)方向上,定义两彼此相交(例如彼此垂直)的方向,例如可以定义位线结构延伸的方向为第一方向,定义位线结构排列的方向为第二方向,基于第一方向和第二方向可以确定基底的平面方向。本公开实施例中,第一方向、第二方向和第三方向可以两两相互垂直,在其他实施例中,第一方向、第二方向和第三方向也可以不垂直。本公开实施例中,定义第一方向为X轴方向,定义第二方向为Y轴方向,定义第三方向为Z轴方向。Before introducing the embodiments of the present disclosure, let us first define the three directions that may be used to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction of intersection (eg, perpendicular) with the top and bottom surfaces of the substrate is defined as third direction. In the direction of the top surface and the bottom surface of the substrate (that is, the plane on which the substrate is located), two directions that intersect each other (for example, are perpendicular to each other) are defined. For example, the direction in which the bit line structure extends can be defined as the first direction, and the direction in which the bit line structure is arranged can be defined. The direction is a second direction, and the plane direction of the substrate can be determined based on the first direction and the second direction. In the embodiment of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular to each other. In the embodiment of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.
本公开实施例提供一种半导体结构的形成方法,图1为本公开实施例提供的半导体 结构形成方法的流程示意图,如图1所示,半导体结构的形成方法包括以下步骤:An embodiment of the disclosure provides a method for forming a semiconductor structure. Figure 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 1, the method for forming a semiconductor structure includes the following steps:
步骤S101,提供基底,基底包括沿第一方向延伸、且沿第二方向交替排列的有源条和第一沟槽。Step S101: Provide a substrate, which includes active strips and first trenches extending along a first direction and alternately arranged along a second direction.
本公开实施例中,基底至少包括半导体衬底,半导体衬底可以是硅衬底,半导体衬底也可以包括其他半导体元素,例如:锗(Ge),或包括半导体化合物,例如:碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb),或包括其他半导体合金,例如:硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合。In the embodiment of the present disclosure, the substrate at least includes a semiconductor substrate. The semiconductor substrate may be a silicon substrate. The semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or a semiconductor compound, such as silicon carbide (SiC). ), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys such as silicon germanium (SiGe) , gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide ( GaInAsP) or a combination thereof.
在一些实施例中,基底包括衬底,以及位于衬底表面的第一隔离层;第一隔离层可以包括半导体隔离层和/或绝缘层,半导体隔离层和/或绝缘层用于隔离位线结构与衬底。例如,第一隔离层可以包括半导体隔离层,或者第一隔离层可以包括绝缘层,或者第一隔离层可以包括半导体隔离层和绝缘层;其中,当第一隔离层包括半导体隔离层和绝缘层时,绝缘层可以位于半导体隔离层的表面,半导体隔离层也可以位于绝缘层的表面。In some embodiments, the substrate includes a substrate, and a first isolation layer located on the surface of the substrate; the first isolation layer may include a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer are used to isolate the bit lines. Structure and substrate. For example, the first isolation layer may include a semiconductor isolation layer, or the first isolation layer may include an insulating layer, or the first isolation layer may include a semiconductor isolation layer and an insulating layer; wherein, when the first isolation layer includes a semiconductor isolation layer and an insulating layer , the insulating layer may be located on the surface of the semiconductor isolation layer, and the semiconductor isolation layer may also be located on the surface of the insulating layer.
在一些实施例中,绝缘层的材料可以是氧化硅,或者其他适合的材料。半导体隔离层至少包括位于衬底表面的第一P型半导体层和位于第一P型半导体层表面的第一N型半导体层;有源条位于第一N型半导体层的表面。In some embodiments, the material of the insulating layer may be silicon oxide, or other suitable materials. The semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the active strip is located on the surface of the first N-type semiconductor layer.
本公开实施例中,第一P型半导体层与第一N型半导体层可以构成一个PN结,位线结构靠近第一N型半导体层,即位线结构靠近PN结的N端,如此,在位线结构施加高电压时,PN结反向偏置,不会导通,如此,可以防止位线结构的漏电。In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not be turned on, thereby preventing leakage of the bit line structure.
在其他实施例中,衬底可以为P型掺杂的硅衬底,半导体隔离层还包括位于衬底表面的第二N型半导体层,第一P型半导体层位于第二N型半导体层的表面。此时,第一P型半导体层与第一N型半导体层可以构成一个PN结,第二N型半导体层与P型掺杂的硅衬底构成另一个PN结,如此,在位线结构施加高电压时,两个PN结均反向偏置,可以更加有效地防止位线结构的漏电。In other embodiments, the substrate may be a P-type doped silicon substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, and the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer. surface. At this time, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the second N-type semiconductor layer and the P-type doped silicon substrate form another PN junction. In this way, the bit line structure is applied At high voltage, both PN junctions are reverse biased, which can more effectively prevent leakage of the bit line structure.
在一些实施例中,有源条可以包括第三半导体层,第三半导体层位于第一空隙沿第二方向的投影区域内,第三半导体层可以是硅锗层。In some embodiments, the active strip may include a third semiconductor layer located within a projection area of the first gap along the second direction, and the third semiconductor layer may be a silicon germanium layer.
步骤S102,在第一沟槽的底部形成沿第一方向延伸的隔离结构;其中,隔离结构与有源条沿第二方向投影区域内具有第一空隙。Step S102: Form an isolation structure extending along the first direction at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area along the second direction.
本公开实施例中,隔离结构为凸字形,且隔离结构包括第一U型隔离结构和位于第一U型隔离结构U型底部表面的第二隔离结构;其中,第一U型隔离结构用于隔离后续形成的位线结构与衬底,防止漏电;第二隔离结构用于隔离后续形成的相邻的两个隔离结构。In the embodiment of the present disclosure, the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; wherein the first U-shaped isolation structure is used to isolate the subsequently formed bit line structure from the substrate to prevent leakage; and the second isolation structure is used to isolate two adjacent isolation structures subsequently formed.
步骤S103,在第一空隙中,形成位线结构。Step S103: Form a bit line structure in the first gap.
本公开实施例中,可以通过在第一空隙中沉积位线导电材料,形成位线结构;其中,位线导电材料包括:钨(W)、钴(Co)、铜(Cu)、铝(Al)、氮化钛(TiN)、含钛金属层、多晶硅或其任何组合。In embodiments of the present disclosure, a bit line structure can be formed by depositing bit line conductive materials in the first gap; wherein the bit line conductive materials include: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al ), titanium nitride (TiN), titanium-containing metal layers, polysilicon, or any combination thereof.
本公开实施例提供的半导体结构的形成方法,在埋入式位线结构的形成过程中,不用对有源条进行刻蚀,如此,可以使得有源条不易倒塌,从而使得半导体结构在形成过程中的稳定性较强。另外,本公开实施例中,通过在有源条与隔离结构之间的间隙中形成位线结构,可以简化埋入式位线结构的制备工艺过程,降低半导体结构的工艺复杂度。The method for forming a semiconductor structure provided by embodiments of the present disclosure does not require etching the active strip during the formation process of the buried bit line structure. In this way, the active strip is less likely to collapse, thereby making the semiconductor structure less susceptible to collapse during the formation process. The stability in the medium is strong. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
图2a~图2o为本公开实施例提供的半导体结构形成过程中的结构示意图,下面结合图2a~图2o对本公开实施例提供的半导体结构的形成过程进行详细的说明。其中,图2h为沿c-c'的剖视图,图2i为图2h中沿a-a'、b-b'、d-d'的截面图,图2l为a-a'的剖视图, 图2m为图2l中沿e-e'和c-c'的截面图,图2n为图2m中沿b-b'和d-d'的截面图。2a to 2o are schematic structural diagrams of the semiconductor structure formation process provided by the embodiment of the present disclosure. The formation process of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2a to 2o. Among them, Figure 2h is a cross-sectional view along c-c', Figure 2i is a cross-sectional view along a-a', b-b', and d-d' in Figure 2h, Figure 2l is a cross-sectional view along a-a', Figure 2m Figure 2n is a cross-sectional view along e-e' and c-c' in Figure 2l, and Figure 2n is a cross-sectional view along b-b' and d-d' in Figure 2m.
首先,可以参考图2a~图2d,执行步骤S101,提供基底,基底包括沿第一方向延伸、且沿第二方向交替排列的有源条和第一沟槽。First, referring to FIGS. 2a to 2d , step S101 is performed to provide a substrate. The substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction.
如图2a所示,基底包括衬底10、以及位于衬底10表面的第一隔离层,其中,第一隔离层包括半导体隔离层11,半导体隔离层11包括位于衬底10表面的第一P型半导体层11a和位于第一P型半导体层11a表面的第一N型半导体层11b。在其他实施例中,第一隔离层可以包括绝缘层,或者第一隔离层可以包括绝缘层和半导体隔离层。As shown in Figure 2a, the base includes a substrate 10 and a first isolation layer located on the surface of the substrate 10, wherein the first isolation layer includes a semiconductor isolation layer 11, and the semiconductor isolation layer 11 includes a first P layer located on the surface of the substrate 10. type semiconductor layer 11a and the first N-type semiconductor layer 11b located on the surface of the first P-type semiconductor layer 11a. In other embodiments, the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.
在一些实施例中,第一P型半导体层11a和第一N型半导体层11b可以通过以下步骤形成:在衬底10表面形成第一初始半导体层(未示出);对第一初始半导体层进行第一重掺杂,形成第一P型半导体层11a;在第一P型半导体层的表面形成第二初始半导体层(未示出);对第二初始半导体层进行第二重掺杂,形成第一N型半导体层11b。In some embodiments, the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b may be formed by the following steps: forming a first initial semiconductor layer (not shown) on the surface of the substrate 10; Perform the first heavy doping to form the first P-type semiconductor layer 11a; form a second initial semiconductor layer (not shown) on the surface of the first P-type semiconductor layer; perform the second heavy doping on the second initial semiconductor layer, The first N-type semiconductor layer 11b is formed.
本公开实施例中,第一重掺杂的掺杂元素可以是III族元素,例如为硼元素、镓元素、铟元素等三价杂质元素;第二重掺杂的元素可以是V族元素,例如为磷元素、锑元素、砷元素等五价杂质元素。In the embodiment of the present disclosure, the first heavily doped doping element may be a Group III element, such as a trivalent impurity element such as boron, gallium, indium, etc.; the second heavily doped element may be a Group V element, For example, they are pentavalent impurity elements such as phosphorus, antimony, and arsenic.
本公开实施例中,第一P型半导体层与第一N型半导体层可以构成一个PN结,位线结构靠近第一N型半导体层,即位线结构靠近PN结的N端,如此,在位线结构施加高电压时,PN结反向偏置,不会导通,由于PN结的反向电阻很高,如此可以隔离位线结构和衬底,防止位线结构漏电。In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, the bit line structure is close to the N end of the PN junction. When a high voltage is applied to the line structure, the PN junction is reverse biased and will not conduct. Since the reverse resistance of the PN junction is very high, this can isolate the bit line structure and the substrate and prevent leakage of the bit line structure.
为便于理解,图2b~图2o中仅示出半导体隔离层11,未示出半导体隔离层11中的第一P型半导体层11a与第一N型半导体层11b。For ease of understanding, only the semiconductor isolation layer 11 is shown in FIGS. 2b to 2o , and the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b in the semiconductor isolation layer 11 are not shown.
在一些实施例中,有源条和第一沟槽可以通过以下步骤形成:在第一N型半导体层的表面形成半导体有源层;在半导体有源层的表面形成具有第一图案的第一掩膜层;第一图案包括沿第一方向延伸、且沿第二方向排列的多个第一子图案,第一子图案暴露出部分半导体有源层;通过第一掩膜层,去除第一子图案暴露出的部分半导体有源层,形成沿第一方向延伸、且沿第二方向交替排列有源条和第一沟槽。In some embodiments, the active strip and the first trench may be formed by the following steps: forming a semiconductor active layer on the surface of the first N-type semiconductor layer; forming a first pattern with a first pattern on the surface of the semiconductor active layer. Mask layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction, and the first sub-pattern exposes part of the semiconductor active layer; through the first mask layer, the first sub-pattern is removed The portion of the semiconductor active layer exposed by the sub-pattern forms active strips and first trenches extending along the first direction and alternately arranged along the second direction.
如图2b所示,在第一N型半导体层(即半导体隔离层11)的表面形成半导体有源层12a。As shown in FIG. 2b, a semiconductor active layer 12a is formed on the surface of the first N-type semiconductor layer (ie, the semiconductor isolation layer 11).
本公开实施例中,半导体有源层12a可以通过以下任一沉积工艺形成:外延工艺、化学气相沉积(Chemical Vapor Deposition,CVD)工艺、物理气相沉积(Physical Vapor Deposition,PVD)工艺、原子层沉积(Atomic Layer Deposition,ALD)工艺或者其他适合的工艺。In this disclosed embodiment, the semiconductor active layer 12a can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or other suitable processes.
如图2b~图2d所示,在半导体有源层12a的表面形成具有第一图案的第一掩膜层25;第一图案包括沿X轴方向延伸、且沿Y轴方向排列的多个第一子图案E,第一子图案E暴露出部分半导体有源层12a;通过第一掩膜层25,去除第一子图案E暴露出的部分半导体有源层12a,形成沿X轴方向延伸、且沿Y轴方向交替排列有源条12和第一沟槽13。As shown in Figures 2b to 2d, a first mask layer 25 having a first pattern is formed on the surface of the semiconductor active layer 12a; the first pattern includes a plurality of first patterns extending along the X-axis direction and arranged along the Y-axis direction. A sub-pattern E, the first sub-pattern E exposes part of the semiconductor active layer 12a; through the first mask layer 25, the part of the semiconductor active layer 12a exposed by the first sub-pattern E is removed, forming a And the active strips 12 and the first trenches 13 are alternately arranged along the Y-axis direction.
本公开实施例中,第一掩膜层25的材料可以是氧化硅、氮化硅、碳化硅、氮氧化硅中的一种或几种;第一掩膜层25可以通过任意一种合适的沉积工艺形成。In the embodiment of the present disclosure, the material of the first mask layer 25 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the first mask layer 25 may be made of any suitable material. Formed by deposition process.
本公开实施例中,在形成有源条12和第一沟槽13之后,半导体结构的形成方法还包括:去除第一掩膜层25,暴露出有源条12的上表面。In the embodiment of the present disclosure, after forming the active strip 12 and the first trench 13 , the method of forming the semiconductor structure further includes: removing the first mask layer 25 to expose the upper surface of the active strip 12 .
接下来,可以参考图2e~图2g,执行步骤S102,在第一沟槽的底部形成沿第一方向延伸的隔离结构;其中,隔离结构与有源条沿第二方向投影区域内具有第一空隙。Next, refer to FIG. 2e to FIG. 2g to perform step S102 to form an isolation structure extending along the first direction at the bottom of the first trench; wherein, the isolation structure and the active strip have a first projection area along the second direction. gap.
在一些实施例中,隔离结构为凸字形,且隔离结构包括第一U型隔离结构以及位于第一U型隔离结构U型底部表面的第二隔离结构;隔离结构可以通过以下步骤形成: 在有源条的表面和第一沟槽的内壁,形成第一初始隔离结构;在具有第一初隔离结构的第一沟槽底部形成第二隔离结构;回刻第一初始隔离结构形成第一U型隔离结构;第二隔离结构的顶表面超出第一U型隔离结构的顶表面。In some embodiments, the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; the isolation structure can be formed by the following steps: The surface of the source bar and the inner wall of the first trench form a first initial isolation structure; a second isolation structure is formed at the bottom of the first trench with the first initial isolation structure; and the first initial isolation structure is carved back to form a first U-shape Isolation structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.
如图2e所示,在有源条12的表面和第一沟槽13的内壁沉积第一隔离材料,形成第一初始隔离结构14a;第一隔离材料可以是氧化硅,或者其他适合的材料。As shown in Figure 2e, a first isolation material is deposited on the surface of the active strip 12 and the inner wall of the first trench 13 to form a first initial isolation structure 14a; the first isolation material may be silicon oxide, or other suitable materials.
如图2f所示,在具有第一初隔离结构14a的第一沟槽13中沉积第二隔离材料,形成第二初始隔离结构(未示出);回刻第二初始隔离结构,形成第二隔离结构15;第二隔离材料可以是氮化硅,或者其他适合的材料。As shown in Figure 2f, a second isolation material is deposited in the first trench 13 with the first initial isolation structure 14a to form a second initial isolation structure (not shown); the second initial isolation structure is etched back to form a second Isolation structure 15; the second isolation material may be silicon nitride, or other suitable materials.
本公开实施例中,在回刻第二初始隔离结构的工艺过程中,第二隔离材料与衬底之间的刻蚀选择比大于第一隔离材料与衬底之间的刻蚀选择比,例如,第二隔离材料与衬底之间的刻蚀选择比是第一隔离材料与衬底之间的刻蚀选择比的3~10倍,如此,在回刻第二初始隔离结构时可以不损伤第一初始隔离结构14a。In the embodiment of the present disclosure, during the process of etching back the second initial isolation structure, the etching selectivity ratio between the second isolation material and the substrate is greater than the etching selectivity ratio between the first isolation material and the substrate, for example , the etching selectivity ratio between the second isolation material and the substrate is 3 to 10 times the etching selectivity ratio between the first isolation material and the substrate. In this way, the second initial isolation structure can be etched back without damaging it. First initial isolation structure 14a.
本公开实施例中,可以通过任意一种合适的沉积工艺形成第一初始隔离结构14a和第二初始隔离结构。In the embodiment of the present disclosure, the first initial isolation structure 14a and the second initial isolation structure may be formed through any suitable deposition process.
如图2g所示,回刻第一初始隔离结构14a(参考图2f)形成第一U型隔离结构14,可以通过干法刻蚀工艺(例如等离子体刻蚀工艺、反应离子刻蚀工艺或者离子铣工艺)回刻第一初始隔离结构。本公开实施例中,第二隔离结构15的顶表面超出第一U型隔离结构14的顶表面。As shown in Figure 2g, the first initial isolation structure 14a (refer to Figure 2f) is etched back to form the first U-shaped isolation structure 14, which can be achieved by a dry etching process (such as a plasma etching process, a reactive ion etching process or an ion etching process). milling process) to engrave back the first initial isolation structure. In this disclosed embodiment, the top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14 .
本公开实施例中,隔离结构为凸字形,且隔离结构(即第二隔离结构15)与有源条12沿Y轴方向投影区域内具有第一空隙16a。In the disclosed embodiment, the isolation structure is in a convex shape, and a first gap 16 a is present in the projection area between the isolation structure (ie, the second isolation structure 15 ) and the active strip 12 along the Y-axis direction.
本公开实施例中,在回刻第一初始隔离结构的工艺过程中,第一隔离材料与衬底之间的刻蚀选择比大于第二隔离材料与衬底之间的刻蚀选择比,例如,第一隔离材料与衬底之间的刻蚀选择比是第二隔离材料与衬底之间的刻蚀选择比的5~10倍,如此,在回刻第一初始隔离结构14a时可以不损伤第二隔离结构15。In the embodiment of the present disclosure, during the process of etching back the first initial isolation structure, the etching selectivity ratio between the first isolation material and the substrate is greater than the etching selectivity ratio between the second isolation material and the substrate, for example , the etching selectivity ratio between the first isolation material and the substrate is 5 to 10 times the etching selectivity ratio between the second isolation material and the substrate. In this way, it is not necessary to etch back the first initial isolation structure 14a. The second isolation structure 15 is damaged.
本公开实施例中,位于凸字形隔离结构中的第一U型隔离结构14用于隔离后续形成的位线结构和衬底,防止位线结构漏电;位于凸字形隔离结构中的第二隔离结构15用于隔离位于同一第一沟槽13中的相邻两个位线结构,防止位线结构漏电,从而提高了半导体结构的电性能。In the embodiment of the present disclosure, the first U-shaped isolation structure 14 located in the convex-shaped isolation structure is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 14 located in the convex-shaped isolation structure 15 is used to isolate two adjacent bit line structures located in the same first trench 13 to prevent leakage of the bit line structures, thereby improving the electrical performance of the semiconductor structure.
在其它实施例中,第一U型隔离结构还可以为半导体隔离层,或者,第一U型隔离结构还可以为半导体隔离层和绝缘层(例如为氧化物层)构成的复合隔离结构。In other embodiments, the first U-shaped isolation structure may also be a semiconductor isolation layer, or the first U-shaped isolation structure may also be a composite isolation structure composed of a semiconductor isolation layer and an insulating layer (for example, an oxide layer).
最后,可以参考图2h~图2o,执行步骤S103,在第一空隙中,形成位线结构。Finally, referring to Figures 2h to 2o, step S103 is performed to form a bit line structure in the first gap.
如图2h和图2i所示,在具有隔离结构的第一沟槽13中沉积位线金属材料,形成初始位线结构(未示出),回刻初始位线结构,形成位线结构16。As shown in FIGS. 2h and 2i , a bit line metal material is deposited in the first trench 13 with an isolation structure to form an initial bit line structure (not shown), and the initial bit line structure is etched back to form a bit line structure 16 .
本公开实施例中,位线金属材料包括:钨、钴、铜、铝、氮化钛、含钛金属层、多晶硅或其任何组合。In the embodiment of the present disclosure, the bit line metal material includes: tungsten, cobalt, copper, aluminum, titanium nitride, titanium-containing metal layer, polysilicon or any combination thereof.
本公开实施例中,可以通过干法刻蚀工艺回刻初始位线结构,形成位线结构16。In the embodiment of the present disclosure, the initial bit line structure can be etched back through a dry etching process to form the bit line structure 16 .
需要说明的是,本公开实施例中的位线结构16的顶表面未超出第二隔离结构15的顶表面。在其他实施例中,位线结构16的顶表面可以与第二隔离结构15的顶表面齐平。It should be noted that the top surface of the bit line structure 16 in the embodiment of the present disclosure does not exceed the top surface of the second isolation structure 15 . In other embodiments, the top surface of bit line structure 16 may be flush with the top surface of second isolation structure 15 .
在一些实施例中,在形成位线结构之后,半导体结构的形成方法还包括:通过湿法刻蚀工艺去除位于第一沟槽13中的残留金属。In some embodiments, after forming the bit line structure, the method of forming the semiconductor structure further includes: removing residual metal located in the first trench 13 through a wet etching process.
本公开实施例中,在去除位于第一沟槽13中的残留金属之后,半导体结构的形成方法还包括:在第二隔离结构15和位线结构16的表面热氧化生长预设厚度的氧化硅,氧化硅用于进一步去除有源条12侧壁的残留金属,防止后续工艺过程中在沟道结构表面形成硅化物。本公开实施例中,预设厚度可以是1~5纳米(nm)。In the embodiment of the present disclosure, after removing the residual metal located in the first trench 13 , the method of forming the semiconductor structure further includes: thermally oxidizing and growing silicon oxide of a predetermined thickness on the surfaces of the second isolation structure 15 and the bit line structure 16 , silicon oxide is used to further remove residual metal on the sidewalls of the active strip 12 to prevent silicide from forming on the surface of the channel structure during subsequent processes. In embodiments of the present disclosure, the preset thickness may be 1 to 5 nanometers (nm).
在一些实施例中,在去除残留的金属之后,半导体结构的形成方法还包括:在位线结构表面和隔离结构表面覆盖形成第三隔离结构;其中,第三隔离结构的顶表面未超出有源条的顶表面。In some embodiments, after removing the residual metal, the method of forming the semiconductor structure further includes: covering the surface of the bit line structure and the surface of the isolation structure to form a third isolation structure; wherein the top surface of the third isolation structure does not exceed the active The top surface of the strip.
如图2j所示,在位线结构16表面和第二隔离结构15表面沉积第三隔离材料形成第三隔离结构17,其中,第三隔离材料可以是氧化硅、氮氧化硅或者其他适合的材料。As shown in FIG. 2j, a third isolation material is deposited on the surface of the bit line structure 16 and the second isolation structure 15 to form the third isolation structure 17. The third isolation material may be silicon oxide, silicon oxynitride, or other suitable materials. .
本公开实施例中,可以通过原子沉积工艺,沉积第三隔离材料形成第三隔离结构17,以提高膜层质量。In the embodiment of the present disclosure, a third isolation material can be deposited through an atomic deposition process to form the third isolation structure 17 to improve the quality of the film layer.
在一些实施例中,如图2k所示,在形成第三隔离结构17之后,半导体结构的形成方法还包括:对位线结构16和有源条12进行热处理,形成位于位线结构16与有源条12之间的金属硅化物19。In some embodiments, as shown in FIG. 2k , after forming the third isolation structure 17 , the method of forming the semiconductor structure further includes: performing heat treatment on the bit line structure 16 and the active strip 12 to form a layer between the bit line structure 16 and the active strip 12 . Metal silicide 19 between source bars 12 .
本公开实施例中,可以通过快速热处理(Rapid Thermal Processing,RTP)过程使得位线金属材料与有源条12相互反应,从而在有源条12的表面形成金属硅化物19。由于金属硅化物具有较低的阻值,因此可以降低位线结构16与有源条12之间的接触电阻,进而可以降低半导体结构的功耗。In the embodiment of the disclosure, the bit line metal material and the active strip 12 can react with each other through a Rapid Thermal Processing (RTP) process, thereby forming metal silicide 19 on the surface of the active strip 12 . Since the metal silicide has a lower resistance, the contact resistance between the bit line structure 16 and the active strip 12 can be reduced, thereby reducing the power consumption of the semiconductor structure.
请继续参考图2k,在形成金属硅化物之后,半导体结构的形成方法还包括:对位线结构沿Y轴方向投影区域内的有源条12进行掺杂,形成漏极部26,漏极部26可以作为晶体管结构的漏极D。Please continue to refer to FIG. 2k. After forming the metal silicide, the formation method of the semiconductor structure also includes: doping the active strip 12 in the projection area of the bit line structure along the Y-axis direction to form a drain portion 26. 26 can be used as the drain D of the transistor structure.
本公开实施例中,对位线结构沿Y轴方向投影区域内的有源条12进行离子注入,形成漏极D。离子注入可以通过热扩散和等离子体掺杂等工艺来实现,离子注入工艺采用的能量和剂量以及注入的离子的类型可以根据将要形成的晶体管的类型来确定,例如,P型金属氧化物半导体(P-Metal-Oxide-Semiconductor,PMOS)可以进行浅深度、重掺杂的BF
2
+离子注入;N型金属氧化物半导体(N-Metal-Oxide-Semiconductor,NMOS)可以进行浅深度、重掺杂的砷离子注入。离子注入后,还可以包括高温退火过程,如此可以修复离子注入导致的晶格损伤,激活离子注入的杂质。
In the embodiment of the present disclosure, ions are implanted into the active strip 12 in the projection area of the bit line structure along the Y-axis direction to form the drain D. Ion implantation can be achieved through processes such as thermal diffusion and plasma doping. The energy and dosage used in the ion implantation process and the type of implanted ions can be determined according to the type of transistor to be formed, for example, P-type metal oxide semiconductor ( P-Metal-Oxide-Semiconductor (PMOS) can perform shallow-depth, heavily doped BF 2+ ion implantation; N-type metal-oxide semiconductor (N-Metal - Oxide-Semiconductor, NMOS) can perform shallow-depth, heavily doped Arsenic ion implantation. After ion implantation, a high-temperature annealing process can also be included, which can repair the lattice damage caused by the ion implantation and activate the ion-implanted impurities.
需要说明的是,本公开实施例中对形成漏极D、金属硅化物19、第三隔离结构17的顺序不做限定,例如,可以先形成漏极D,然后形成第三隔离结构17,最后形成金属硅化物19;也可以先形成金属硅化物19,再形成第三隔离结构17,最后形成漏极D;也可以先形成漏极D,再形成金属硅化物19,最后形成第三隔离结构17。It should be noted that in the embodiment of the present disclosure, the order in which the drain D, the metal silicide 19 and the third isolation structure 17 are formed is not limited. For example, the drain D may be formed first, then the third isolation structure 17 may be formed, and finally Form the metal silicide 19; you can also form the metal silicide 19 first, then form the third isolation structure 17, and finally form the drain D; you can also form the drain D first, then form the metal silicide 19, and finally form the third isolation structure 17.
在一些实施例中,半导体结构的形成方法还包括:在第三隔离结构的表面形成第四隔离结构;其中,第四隔离结构的顶表面与有源条的顶表面齐平。In some embodiments, the method for forming a semiconductor structure further includes: forming a fourth isolation structure on a surface of the third isolation structure; wherein a top surface of the fourth isolation structure is flush with a top surface of the active strip.
请继续参考图2k,在第三隔离结构17的表面沉积第四隔离材料,形成第四隔离结构18,其中,第四隔离材料可以是氧化硅、氮氧化硅或者其他适合的材料,第三隔离材料和第四隔离材料可以相同,也可以不同。Please continue to refer to FIG. 2k. A fourth isolation material is deposited on the surface of the third isolation structure 17 to form a fourth isolation structure 18. The fourth isolation material may be silicon oxide, silicon oxynitride or other suitable materials. The third isolation material The material and the fourth isolation material may be the same or different.
需要说明的是,在第三隔离结构17的表面沉积第四隔离材料,形成第四隔离结构18的过程中,往往会在有源条12的表面也沉积有部分第四隔离材料,然后会经过化学机械抛光(Chemical Mechanical Polishing,CMP)处理,使得第四隔离结构18的顶表面与有源条12的顶表面齐平。It should be noted that, during the process of depositing the fourth isolation material on the surface of the third isolation structure 17 and forming the fourth isolation structure 18, part of the fourth isolation material is often deposited on the surface of the active strip 12, and then passes through Chemical Mechanical Polishing (CMP) treatment is performed so that the top surface of the fourth isolation structure 18 is flush with the top surface of the active strip 12 .
在一些实施例中,在形成第四隔离结构18之后,半导体结构的形成方法还包括:形成字线结构、源极部和电容结构。In some embodiments, after forming the fourth isolation structure 18 , the method of forming the semiconductor structure further includes forming a word line structure, a source portion, and a capacitor structure.
在一些实施例中,字线结构可以通过以下步骤形成:在有源条和第四隔离结构表面形成具有第二图案的第二掩膜层;第二图案包括沿第二方向延伸、且沿第一方向排列的多个第二子图案,第二子图案暴露出部分有源条和部分第四隔离结构;通过第二掩膜层,刻蚀第二子图案暴露出的有源条和部分第四隔离结构,或者,刻蚀第二子图案暴露出的有源条和全部第四隔离结构,形成沿第一方向交替排列的第二沟槽和有源隔离层;其中, 第二沟槽沿第三方向上的尺寸小于或者等于第四隔离结构在第三方向上的初始尺寸;第二沟槽沿第二方向延伸,有源隔离层包括沿第二方向交替排列的有源柱和刻蚀后的第四隔离结构;有源柱之间彼此绝缘;在第二沟槽的侧壁形成字线结构,字线结构的顶表面未超出有源柱的顶表面。In some embodiments, the word line structure may be formed by the following steps: forming a second mask layer with a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern includes extending along the second direction and extending along the second direction. A plurality of second sub-patterns are arranged in one direction, and the second sub-pattern exposes part of the active strip and part of the fourth isolation structure; through the second mask layer, the active strip and part of the fourth isolation structure exposed by the second sub-pattern are etched. Four isolation structures, or etching the active strips and all fourth isolation structures exposed by the second sub-pattern to form second trenches and active isolation layers alternately arranged along the first direction; wherein, the second trench is The size in the third direction is less than or equal to the initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etched pillars alternately arranged along the second direction. The fourth isolation structure; the active pillars are insulated from each other; a word line structure is formed on the side wall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.
如图2l~图2n示,在有源条12和第四隔离结构18表面形成具有第二图案的第二掩膜层27;第二图案包括沿Y轴方向延伸、且沿X轴方向排列的多个第二子图案F,第二子图案F暴露出部分有源条12和部分第四隔离结构18;通过第二掩膜层27,刻蚀第二子图案F暴露出的部分有源条12和部分第四隔离结构18,直至暴露出第三隔离结构17,形成沿X轴方向交替排列的第二沟槽22a和有源隔离层20;其中,第二沟槽22a沿Y轴方向延伸,有源隔离层20包括沿Y轴方向交替排列的有源柱21和刻蚀后的第四隔离结构18,有源柱21之间通过第四隔离结构18彼此绝缘。本公开实施例中,第二沟槽22a在Z轴方向的尺寸d1(如图2l所示)等于第四隔离结构18在Z轴方向的初始尺寸d2(如图2m所示)。As shown in Figures 2l to 2n, a second mask layer 27 with a second pattern is formed on the surface of the active strip 12 and the fourth isolation structure 18; the second pattern includes lines extending along the Y-axis direction and arranged along the X-axis direction. A plurality of second sub-patterns F, the second sub-pattern F exposes part of the active strip 12 and part of the fourth isolation structure 18; through the second mask layer 27, the part of the active strip exposed by the second sub-pattern F is etched 12 and part of the fourth isolation structure 18 until the third isolation structure 17 is exposed, forming second trenches 22a and active isolation layers 20 alternately arranged along the X-axis direction; wherein the second trenches 22a extend along the Y-axis direction. , the active isolation layer 20 includes active pillars 21 alternately arranged along the Y-axis direction and etched fourth isolation structures 18. The active pillars 21 are insulated from each other by the fourth isolation structure 18. In the embodiment of the present disclosure, the size d1 of the second trench 22a in the Z-axis direction (as shown in FIG. 2l) is equal to the initial size d2 of the fourth isolation structure 18 in the Z-axis direction (as shown in FIG. 2m).
在其他实施例中,通过第二掩膜层27,刻蚀第二子图案F暴露出的部分有源条12和部分第四隔离结构18,形成沿X轴方向交替排列的第二沟槽22a和有源隔离层20;其中,第二沟槽22a沿Y轴方向延伸,有源隔离层20包括有源柱21和位于沿Y轴方向相邻两个有源柱21之间的第四隔离结构18,有源柱21之间通过第四隔离结构18彼此绝缘,第二沟槽22a在Z轴方向的尺寸小于第四隔离结构18在Z轴方向的初始尺寸d2。In other embodiments, part of the active strip 12 and part of the fourth isolation structure 18 exposed by the second sub-pattern F are etched through the second mask layer 27 to form second trenches 22a alternately arranged along the X-axis direction. and active isolation layer 20; wherein, the second trench 22a extends along the Y-axis direction, and the active isolation layer 20 includes an active pillar 21 and a fourth isolation located between two adjacent active pillars 21 along the Y-axis direction. The structure 18 and the active pillar 21 are insulated from each other by the fourth isolation structure 18. The size of the second trench 22a in the Z-axis direction is smaller than the initial size d2 of the fourth isolation structure 18 in the Z-axis direction.
本公开实施例中,第二掩膜层27的材料可以是氧化硅、氮化硅、碳化硅、氮氧化硅中的一种或几种;第二掩膜层27可以通过任意一种合适的沉积工艺形成。In the embodiment of the present disclosure, the material of the second mask layer 27 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the second mask layer 27 may be made of any suitable material. Formed by deposition process.
在一些实施例中,在形成有源隔离层20之后,半导体结构的形成方法还包括:去除具有第二图案的第二掩膜层27。In some embodiments, after the active isolation layer 20 is formed, the method of forming the semiconductor structure further includes: removing the second mask layer 27 having the second pattern.
如图2n和图2o所示,在第二沟槽22a的侧壁形成依次沉积栅极介质层221,以及位于栅极介质层221表面的栅极导电层,其中,栅极导电层可以作为字线结构22,字线结构22的顶表面未超出有源柱的顶表面。本公开实施例中,位于字线结构22沿X轴方向投影区域内的有源柱21构成沟道结构。As shown in Figure 2n and Figure 2o, a gate dielectric layer 221 is sequentially deposited on the sidewall of the second trench 22a, and a gate conductive layer located on the surface of the gate dielectric layer 221, wherein the gate conductive layer can be used as a word The top surface of the line structure 22 and the word line structure 22 do not exceed the top surface of the active pillar. In the embodiment of the present disclosure, the active pillar 21 located in the projection area of the word line structure 22 along the X-axis direction forms a channel structure.
在一些实施例中,栅极介质层221的材料可以是氧化硅或者其他适合的材料;栅极导电层的材料可以是任意一种导电性能较好的材料,例如为钛(Ti)、氮化钛(TiN)、氮化钨(WN)、钨(W)、钴(Co)、铂(Pt)、钯(Pd)、钌(Ru)、铜(Cu)中的任意一种。栅极介质层和栅极导电层可以通过任意一种合适的沉积工艺形成,例如,化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺。In some embodiments, the material of the gate dielectric layer 221 can be silicon oxide or other suitable materials; the material of the gate conductive layer can be any material with good conductivity, such as titanium (Ti), nitride, etc. Any one of titanium (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu). The gate dielectric layer and the gate conductive layer can be formed by any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.
需要说明的是,本公开实施例中的栅极结构为双栅结构,在其他实施例中,还可以去除位于有源柱21之间的刻蚀后的第四隔离结构18,在有源柱21的表面形成全环栅结构。It should be noted that the gate structure in the embodiment of the present disclosure is a double gate structure. In other embodiments, the etched fourth isolation structure 18 between the active pillars 21 can also be removed. The surface of 21 forms a full ring gate structure.
在一些实施例中,在形成字线结构22之后,半导体结构的形成方法还包括:在具有字线结构22的第二沟槽22a中沉积第五隔离材料,形成第五隔离结构23,第五隔离材料可以是氧化硅或其他适合的材料,第五隔离结构23用于隔离相邻两个的字线结构22。In some embodiments, after the word line structure 22 is formed, the method of forming the semiconductor structure further includes: depositing a fifth isolation material in the second trench 22a having the word line structure 22 to form a fifth isolation structure 23. The isolation material may be silicon oxide or other suitable materials, and the fifth isolation structure 23 is used to isolate two adjacent word line structures 22 .
在一些实施例中,参考图2o,在形成字线结构22之后,半导体结构的形成方法还包括:对字线结构22沿X轴方向投影区域外的有源柱21进行离子注入,形成源极部,其中,源极部可以作为晶体管结构的源极S。In some embodiments, referring to FIG. 2o, after forming the word line structure 22, the method of forming the semiconductor structure further includes: performing ion implantation on the active pillar 21 outside the projection area of the word line structure 22 along the X-axis direction to form a source electrode. part, wherein the source part may serve as the source S of the transistor structure.
本公开实施例中的源极和漏极位于沟道结构沿第三方向的两侧,即本公开实施例中的晶体管结构是竖直的,竖直状的晶体管结构(或者沟道结构)可以使半导体结构具有 较高的排布密度,如此,可以提高半导体结构的集成度,实现微缩。The source and drain in the embodiment of the present disclosure are located on both sides of the channel structure along the third direction. That is, the transistor structure in the embodiment of the present disclosure is vertical. The vertical transistor structure (or channel structure) can The semiconductor structure has a higher arrangement density. In this way, the integration level of the semiconductor structure can be improved and shrinkage can be achieved.
在一些实施例中,在形成源极部之后,在有源柱的顶表面形成与源极部连接的电容结构,其中,电容结构包括依次堆叠的第一电极层、电介质层和第二电极层。In some embodiments, after the source portion is formed, a capacitor structure connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence. .
请继续参考图2o,在有源柱的顶表面形成与源极部连接的电容结构24,其中,电容结构包括依次堆叠的第一电极层241、电介质层242和第二电极层243。Please continue to refer to FIG. 2 o , a capacitor structure 24 connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer 241 , a dielectric layer 242 , and a second electrode layer 243 stacked in sequence.
本公开实施例中,第一电极层241的材料和第二电极层243的材料可以包括金属氮化物或金属硅化物,例如,氮化钛。电介质层242的材料可以包括高K介质材料,例如可以是氧化镧(La
2O
3)、氧化铝(Al
2O
3)、氧化铪(HfO
2)、氮氧化铪(HfON)、硅酸铪(HfSiO
x)或氧化锆(ZrO
2)中的一种或任意组合。
In the embodiment of the present disclosure, the material of the first electrode layer 241 and the material of the second electrode layer 243 may include metal nitride or metal silicide, for example, titanium nitride. The material of the dielectric layer 242 may include a high-K dielectric material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), or hafnium silicate. One or any combination of (HfSiO x ) or zirconium oxide (ZrO 2 ).
本公开实施例中,第一电极层241、电介质层242和第二电极层243可以通过以下任意一种沉积工艺形成:化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺。In the embodiment of the present disclosure, the first electrode layer 241, the dielectric layer 242 and the second electrode layer 243 can be formed by any one of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.
本公开实施例提供的半导体结构的形成方法,在埋入式位线结构的形成过程中,不用对有源条进行刻蚀,如此,可以使得有源条不易倒塌,从而使得半导体结构在形成过程中的稳定性较强。另外,本公开实施例中,通过在有源条与隔离结构之间的间隙中形成位线结构,可以简化埋入式位线结构的制备工艺过程,降低半导体结构的工艺复杂度。The method for forming a semiconductor structure provided by embodiments of the present disclosure does not require etching the active strip during the formation process of the buried bit line structure. In this way, the active strip can be less likely to collapse, thereby making the semiconductor structure less susceptible to collapse during the formation process. The stability in the medium is strong. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
图3a~图3g为本公开实施例提供的另一种半导体结构形成过程中的结构示意图,下面结合图3a~图3g对本公开实施例提供的另一种半导体结构的形成过程进行详细的说明。3a to 3g are structural schematic diagrams of the formation process of another semiconductor structure provided by an embodiment of the present disclosure. The formation process of another semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 3a to 3g.
首先,参考图3a和3b,形成沿X轴方向延伸、且沿Y轴方向交替排列有源条12和第一沟槽13。First, referring to FIGS. 3a and 3b , active strips 12 and first trenches 13 are formed extending along the X-axis direction and alternately arranged along the Y-axis direction.
如图3a所示,基底包括衬底10、以及位于衬底10表面的半导体隔离层11,半导体隔离层11包括位于衬底10表面的第一P型半导体层11a和位于第一P型半导体层11a表面的第一N型半导体层11b。As shown in Figure 3a, the base includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10. The semiconductor isolation layer 11 includes a first P-type semiconductor layer 11a located on the surface of the substrate 10 and a first P-type semiconductor layer 11a located on the surface of the substrate 10. The first N-type semiconductor layer 11b on the surface of 11a.
为便于理解,图3b~图3g中仅示出半导体隔离层11,未示出半导体隔离层11中的第一P型半导体层11a与第一N型半导体层11b。For ease of understanding, only the semiconductor isolation layer 11 is shown in FIGS. 3b to 3g , and the first P-type semiconductor layer 11 a and the first N-type semiconductor layer 11 b in the semiconductor isolation layer 11 are not shown.
本公开实施例中,第一P型半导体层与第一N型半导体层可以构成一个PN结,后续形成的位线结构靠近第一N型半导体层,即位线结构靠近PN结的N端,如此,在位线结构施加高电压时,PN结反向偏置,不会导通,如此,可以防止位线结构的漏电。In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the subsequently formed bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction, so , when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct, thus preventing leakage of the bit line structure.
请继续参考图3a,在第一N型半导体层11b(即半导体隔离层11)的表面依次形成第一半导体有源层121a、第三初始半导体层122a、第二半导体有源层123a;第一半导体有源层121a、第三初始半导体层122a、第二半导体有源层123a构成半导体有源层12a。本公开实施例中,第一半导体有源层121a和第二半导体有源层123a可以是硅层,第三初始半导体层122a可以是硅锗层。Please continue to refer to FIG. 3a. On the surface of the first N-type semiconductor layer 11b (ie, the semiconductor isolation layer 11), a first semiconductor active layer 121a, a third initial semiconductor layer 122a, and a second semiconductor active layer 123a are sequentially formed; The semiconductor active layer 121a, the third initial semiconductor layer 122a, and the second semiconductor active layer 123a constitute the semiconductor active layer 12a. In the embodiment of the present disclosure, the first semiconductor active layer 121a and the second semiconductor active layer 123a may be silicon layers, and the third initial semiconductor layer 122a may be a silicon germanium layer.
如图3b所示,刻蚀半导体有源层12a,形成沿X轴方向延伸、且沿Y轴方向交替排列有源条12和第一沟槽13。其中,有源条12包括沿Z轴方向自下而上依次排列的第一有源条121、第三半导体层122、第二有源条123。As shown in FIG. 3 b , the semiconductor active layer 12 a is etched to form active strips 12 and first trenches 13 extending along the X-axis direction and alternately arranged along the Y-axis direction. The active strip 12 includes a first active strip 121, a third semiconductor layer 122, and a second active strip 123 arranged in sequence from bottom to top along the Z-axis direction.
接下来,请参考图3b~图3d,形成隔离结构。Next, please refer to Figure 3b to Figure 3d to form an isolation structure.
请继续参考图3b和图3c,在有源条12的表面和第一沟槽13的内壁形成第一初始隔离结构14a;在具有第一初隔离结构14a的第一沟槽13中形成第二初始隔离结构(未示出);回刻第二初始隔离结构,形成第二隔离结构15。Please continue to refer to FIG. 3b and FIG. 3c. A first initial isolation structure 14a is formed on the surface of the active strip 12 and the inner wall of the first trench 13; a second initial isolation structure 14a is formed in the first trench 13 having the first initial isolation structure 14a. Initial isolation structure (not shown); etching back the second initial isolation structure to form second isolation structure 15 .
如图3d所示,回刻第一初始隔离结构14a形成第一U型隔离结构14。第二隔离结构15和第一U型隔离结构14共同构成隔离结构。其中,隔离结构与第三半导体层122沿第二方向投影区域内具有第一空隙16a。As shown in FIG. 3d , the first initial isolation structure 14a is etched back to form the first U-shaped isolation structure 14. The second isolation structure 15 and the first U-shaped isolation structure 14 together form an isolation structure. The isolation structure and the third semiconductor layer 122 have a first gap 16a in the projection area along the second direction.
本公开实施例中,第一U型隔离结构14用于隔离后续形成的位线结构和衬底,防 止位线结构漏电;第二隔离结构15用于隔离位于同一第一沟槽13中的相邻两个位线结构,防止位线结构漏电。In the embodiment of the present disclosure, the first U-shaped isolation structure 14 is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 15 is used to isolate the phases located in the same first trench 13 There are two adjacent bit line structures to prevent leakage of the bit line structure.
接下来,参考图3e~图3g,在形成隔离结构之后,半导体结构的形成方法还包括:沿第二方向侧向刻蚀第三半导体层,形成第三子半导体层;其中,隔离结构与第三子半导体层沿第二方向投影区域内具有第二空隙,第二空隙包括第一空隙;在第二空隙中形成位线结构。Next, referring to Figures 3e to 3g, after forming the isolation structure, the method of forming the semiconductor structure also includes: laterally etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third semiconductor layer are etched laterally in the second direction. The three sub-semiconductor layer has a second gap in the projection area along the second direction, and the second gap includes the first gap; a bit line structure is formed in the second gap.
如图3e和3f所示,沿Y轴方向侧向刻蚀第三半导体层122,形成第三子半导体层28;其中,隔离结构为凸字形,且隔离结构(或第二隔离结构15)与第三子半导体层28沿Y轴方向投影区域内具有第二空隙16b,第二空隙16b包括第一空隙16a;在第二空隙16b中形成位线结构16。As shown in Figures 3e and 3f, the third semiconductor layer 122 is laterally etched along the Y-axis direction to form the third sub-semiconductor layer 28; wherein, the isolation structure is a convex shape, and the isolation structure (or the second isolation structure 15) and The third sub-semiconductor layer 28 has a second gap 16b in the projection area along the Y-axis direction. The second gap 16b includes the first gap 16a; the bit line structure 16 is formed in the second gap 16b.
本公开实施例中,隔离结构为凸字形,因此,隔离结构不仅可以隔离相邻的位线结构、还可以隔离位线结构与衬底,防止漏电,提高了半导体结构的电性能。In the embodiment of the present disclosure, the isolation structure is in a convex shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structure and the substrate to prevent leakage and improve the electrical performance of the semiconductor structure.
本公开实施例中,可以采用湿法刻蚀工艺侧向刻蚀第三半导体层122,形成第三子半导体层28;湿法刻蚀的溶液可以是氢氟酸(DHF),也可以是稀释氢氟酸与氨水(NH
4OH)的混合溶液,也可以是包括稀释氢氟酸与四甲基氢氧化铵(TMAH)的混合溶液。
In the embodiment of the disclosure, a wet etching process can be used to laterally etch the third semiconductor layer 122 to form the third sub-semiconductor layer 28; the wet etching solution can be hydrofluoric acid (DHF) or diluted The mixed solution of hydrofluoric acid and ammonia (NH 4 OH) may also be a mixed solution of diluted hydrofluoric acid and tetramethylammonium hydroxide (TMAH).
如图3g所示,在形成位线结构16之后,半导体结构的形成方法还包括:对位线结构16、第一有源条121、第二有源条123、第三子半导体层28进行快速热处理,形成位于位线结构16与第一有源条121之间的第一金属硅化物191,位于位线结构16与第二有源条123之间的第三金属硅化物193,以及位于位线结构16与第三子半导体层28(图3g中未示出)之间的第二金属硅化物192。其中,第一金属硅化物191、第二金属硅化物192和第三金属硅化物193构成金属硅化物19。本公开实施例中,由于金属硅化物19具有较低的阻值,因此可以降低位线结构16与第二有源条123、以及位线结构16与第三子半导体层之间的接触电阻,进而可以降低半导体结构的功耗。As shown in FIG. 3g , after forming the bit line structure 16 , the method of forming the semiconductor structure further includes: rapidly performing a quick process on the bit line structure 16 , the first active strip 121 , the second active strip 123 , and the third sub-semiconductor layer 28 . Heat treatment to form the first metal silicide 191 between the bit line structure 16 and the first active strip 121 , the third metal silicide 193 between the bit line structure 16 and the second active strip 123 , and the A second metal suicide 192 between the line structure 16 and the third sub-semiconductor layer 28 (not shown in Figure 3g). Among them, the first metal silicide 191 , the second metal silicide 192 and the third metal silicide 193 constitute the metal silicide 19 . In the embodiment of the present disclosure, since the metal silicide 19 has a lower resistance, the contact resistance between the bit line structure 16 and the second active strip 123 and the bit line structure 16 and the third sub-semiconductor layer can be reduced. In turn, the power consumption of the semiconductor structure can be reduced.
本公开实施例中,在位线结构16表面和第二隔离结构15表面覆盖形成第三隔离结构。In the embodiment of the present disclosure, a third isolation structure is formed covering the surface of the bit line structure 16 and the surface of the second isolation structure 15 .
在一些实施例中,半导体结构的形成方法还包括:形成漏极部、字线结构、源极部和电容结构。In some embodiments, the method of forming the semiconductor structure further includes forming a drain portion, a word line structure, a source portion and a capacitor structure.
本公开实施例中的漏极部、字线结构、源极部和电容结构的形成方法与上述实施例中的漏极部、字线结构、源极部和电容结构的形成方法类似,具体请参考上述实施例进行理解。The formation method of the drain part, word line structure, source part and capacitor structure in the embodiment of the present disclosure is similar to the formation method of the drain part, word line structure, source part and capacitor structure in the above embodiments. For details, please Please refer to the above embodiments for understanding.
本公开实施例提供的半导体结构的形成方法,在埋入式位线结构的形成过程中,不用对有源条进行完全刻蚀,如此,从而可以使得有源条不易倒塌,且可以在有源条中的第三子半导体层与隔离结构之间形成位线结构,部分位线结构位于第一有源条沿第三方向的投影区域内,进而提高了半导体结构的制备良率。The method for forming a semiconductor structure provided by embodiments of the present disclosure does not require complete etching of the active strip during the formation process of the buried bit line structure. In this way, the active strip is less likely to collapse, and the active strip can be A bit line structure is formed between the third sub-semiconductor layer in the strip and the isolation structure, and part of the bit line structure is located in the projection area of the first active strip along the third direction, thus improving the production yield of the semiconductor structure.
本公开实施例提供的半导体结构的形成方法与上述实施例中的半导体结构的形成方法类似,对于本公开实施例未详尽披露的技术特征,请参照上述实施例进行理解,这里,不再赘述。The method of forming a semiconductor structure provided by the embodiments of the present disclosure is similar to the method of forming the semiconductor structure in the above-mentioned embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above-mentioned embodiments for understanding, and will not be described again here.
除此之外,本公开实施例还提供一种半导体结构,半导体结构通过上述实施例中半导体结构的形成方法形成,图4为本公开实施例提供的一种半导体结构的结构示意图,半导体结构100包括:基底,基底包括沿X轴方向延伸、且沿Y轴方向交替排列的漏极部26和隔离结构;位线结构16,位于隔离结构与漏极部26之间,漏极部26可以作为晶体管结构的漏极D。In addition, the embodiment of the present disclosure further provides a semiconductor structure, which is formed by the method for forming the semiconductor structure in the above embodiment. Figure 4 is a structural schematic diagram of a semiconductor structure provided by the embodiment of the present disclosure. The semiconductor structure 100 includes: a substrate, the substrate includes a drain portion 26 and an isolation structure extending along the X-axis direction and alternately arranged along the Y-axis direction; a bit line structure 16, located between the isolation structure and the drain portion 26, and the drain portion 26 can serve as the drain D of the transistor structure.
在一些实施例中,基底包括衬底,以及位于衬底表面的第一隔离层;第一隔离层包 括半导体隔离层和/或绝缘层,半导体隔离层和/或绝缘层用于隔离位线结构与衬底。In some embodiments, the substrate includes a substrate, and a first isolation layer located on the surface of the substrate; the first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or insulating layer is used to isolate the bit line structure. with substrate.
本公开实施例中,请继续参考图4,基底包括衬底10,以及位于衬底10表面的第一隔离层,其中,第一隔离层包括半导体隔离层11。In the embodiment of the present disclosure, please continue to refer to FIG. 4 , the base includes a substrate 10 and a first isolation layer located on the surface of the substrate 10 , wherein the first isolation layer includes a semiconductor isolation layer 11 .
在其他实施例中,第一隔离层可以包括绝缘层,或者,第一隔离层可以包括绝缘层和半导体隔离层。In other embodiments, the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.
本公开实施例中,请继续参考图4,半导体隔离层11用于隔离位线结构16与衬底10;半导体隔离层至少包括位于衬底表面的第一P型半导体层11a和位于第一P型半导体层11a表面的第一N型半导体层11b;漏极部26位于第一N型半导体层11b的表面。In this disclosed embodiment, please continue to refer to FIG. 4 , the semiconductor isolation layer 11 is used to isolate the bit line structure 16 and the substrate 10; the semiconductor isolation layer at least includes a first P-type semiconductor layer 11a located on the surface of the substrate and a first P-type semiconductor layer 11a located on the surface of the substrate. The first N-type semiconductor layer 11b is located on the surface of the N-type semiconductor layer 11a; the drain portion 26 is located on the surface of the first N-type semiconductor layer 11b.
本公开实施例中,第一P型半导体层与第一N型半导体层可以构成一个PN结,位线结构靠近第一N型半导体层,即位线结构靠近PN结的N端,如此,在位线结构施加高电压时,PN结反向偏置,不会导通,如此,可以防止位线结构的漏电。In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, the bit line structure is close to the N end of the PN junction. When a high voltage is applied to the line structure, the PN junction is reverse biased and will not conduct. In this way, leakage of the bit line structure can be prevented.
其他实施例中,衬底10为P型掺杂的衬底,半导体隔离层11还可以包括位于衬底10表面的第二N型半导体层,第一P型半导体层位于第二N型半导体层的表面。此时,第一P型半导体层与第一N型半导体层可以构成一个PN结,第二N型半导体层与P型掺杂的硅衬底构成另一个PN结,如此,在位线结构施加高电压时,两个PN结均反向偏置,可以更加有效地防止位线结构的漏电。In other embodiments, the substrate 10 is a P-type doped substrate, the semiconductor isolation layer 11 may also include a second N-type semiconductor layer located on the surface of the substrate 10, and the first P-type semiconductor layer is located on the second N-type semiconductor layer. s surface. At this time, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the second N-type semiconductor layer and the P-type doped silicon substrate form another PN junction. In this way, the bit line structure is applied At high voltage, both PN junctions are reverse biased, which can more effectively prevent leakage of the bit line structure.
在一些实施例中,请继续参考图4,隔离结构为凸字形,且隔离结构包括第一U型隔离结构14和位于第一U型隔离结构14的U型底部表面的第二隔离结构15,且第二隔离结构15的顶表面超出第一U型隔离结构14的顶表面;第一U型隔离结构14和第二隔离结构15均与位线结构16相接触。In some embodiments, please continue to refer to Figure 4, the isolation structure is convex-shaped, and the isolation structure includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the U-shaped bottom surface of the first U-shaped isolation structure 14, And the top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.
本公开实施例中,隔离结构为凸字形,因此,隔离结构不仅可以隔离相邻的位线结构、还可以隔离位线结构与衬底,防止漏电,提高了半导体结构的电性能。In the embodiment of the present disclosure, the isolation structure is in a convex shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structure and the substrate to prevent leakage and improve the electrical performance of the semiconductor structure.
在一些实施例中,请继续参考图4,半导体结构100还包括:第三隔离结构17,第三隔离结构17位于位线结构16表面和第二隔离结构15表面。In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a third isolation structure 17 , the third isolation structure 17 is located on the surface of the bit line structure 16 and the surface of the second isolation structure 15 .
在一些实施例中,请继续参考图4,半导体结构100还包括:位于位线结构16与漏极部26之间的金属硅化物19。由于金属硅化物19具有较低的阻值,因此可以降低位线结构16与漏极部26之间的接触电阻,进而可以降低半导体结构的功耗。In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a metal silicide 19 located between the bit line structure 16 and the drain portion 26 . Since the metal silicide 19 has a low resistance, the contact resistance between the bit line structure 16 and the drain portion 26 can be reduced, thereby reducing the power consumption of the semiconductor structure.
在一些实施例中,请继续参考图4,半导体结构100还包括:位于漏极部26表面、且沿X轴方向和Y轴方向阵列排布的有源柱21、以及位于有源柱21的侧壁、且沿X轴方向排布、沿Y轴向延伸的字线结构22;其中,字线结构22的顶表面未超出有源柱21的顶表面。In some embodiments, please continue to refer to Figure 4, the semiconductor structure 100 also includes: an active pillar 21 located on the surface of the drain portion 26 and arranged in an array along the X-axis direction and the Y-axis direction, and a word line structure 22 located on the side wall of the active pillar 21, arranged along the X-axis direction and extending along the Y-axis direction; wherein the top surface of the word line structure 22 does not exceed the top surface of the active pillar 21.
本公开实施例中,半导体结构100还包括:第四隔离结构18,Y轴方向交替排列的有源柱21和第四隔离结构18构成有源隔离层20。在其他实施例中,还可以不包括第四隔离结构18。In the embodiment of the present disclosure, the semiconductor structure 100 further includes: a fourth isolation structure 18. The active pillars 21 and the fourth isolation structures 18 alternately arranged in the Y-axis direction constitute the active isolation layer 20. In other embodiments, the fourth isolation structure 18 may not be included.
本公开实施例中,位线结构16位于有源柱21沿Z轴方向的投影区域之外。In the embodiment of the present disclosure, the bit line structure 16 is located outside the projection area of the active pillar 21 along the Z-axis direction.
在一些实施例中,请继续参考图4,半导体结构100还包括:栅极结构,栅极结构包括栅极介质层221表面的栅极导电层,其中,栅极导电层可以作为字线结构22。In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a gate structure, the gate structure includes a gate conductive layer on the surface of the gate dielectric layer 221 , wherein the gate conductive layer can serve as the word line structure 22 .
在一些实施例中,请继续参考图4,半导体结构100还包括:源极部、以及与源极部相接的电容结构24,源极部位于有源柱21沿Y轴方向的投影区域之外;其中,源极部可以作为晶体管结构的源极S。电容结构24位于有源柱21的顶表面,且电容结构24包括第一电极层241、电介质层242和第二电极层243。In some embodiments, please continue to refer to FIG. 4 . The semiconductor structure 100 further includes: a source portion and a capacitor structure 24 connected to the source portion. The source portion is located within the projection area of the active pillar 21 along the Y-axis direction. Outside; wherein, the source portion can be used as the source S of the transistor structure. The capacitive structure 24 is located on the top surface of the active pillar 21 , and the capacitive structure 24 includes a first electrode layer 241 , a dielectric layer 242 and a second electrode layer 243 .
在一些实施例中,请继续参考图4,半导体结构100还包括:第五隔离结构23,第五隔离结构23位于沿X轴方向相邻的字线结构22之间、以及沿X轴方向相邻的源极部之间。In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a fifth isolation structure 23 , the fifth isolation structure 23 is located between the word line structures 22 adjacent to each other along the X-axis direction and between the source portions adjacent to each other along the X-axis direction.
本公开实施例提供的半导体结构与上述实施例中的半导体结构的形成方法形成的半导体结构类似,对于本公开实施例未详尽披露的技术特征,请参照上述实施例进行理解,这里,不再赘述。The semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure formed by the method of forming the semiconductor structure in the above embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and will not be described again here. .
本公开实施例中的半导体结构包括埋入式位线结构,位线结构位于有源条与隔离结构之间,相比于相关技术,本公开实施例提供的半导体结构中的有源条底部在位线结构的形成过程中未被刻蚀或者未被完全刻蚀断,如此,本公开实施例可以提供一种稳定性较高的半导体结构。The semiconductor structure in the embodiment of the present disclosure includes a buried bit line structure. The bit line structure is located between the active strip and the isolation structure. Compared with the related art, the bottom of the active strip in the semiconductor structure provided by the embodiment of the present disclosure is at The bit line structure is not etched or completely etched during the formation process. In this way, embodiments of the present disclosure can provide a semiconductor structure with higher stability.
本公开实施例还提供一种半导体结构,通过上述实施例中半导体结构的形成方法形成,请继续参考图3g,半导体结构包括:基底,基底包括沿X轴方向延伸、且沿Y轴方向交替排列的漏极部26和隔离结构;位线结构16,位于隔离结构与漏极部26之间,漏极部26可以作为晶体管结构的漏极。Embodiments of the present disclosure also provide a semiconductor structure, which is formed by the formation method of the semiconductor structure in the above embodiment. Please continue to refer to FIG. 3g. The semiconductor structure includes: a substrate extending along the X-axis direction and alternately arranged along the Y-axis direction. The drain portion 26 and the isolation structure; the bit line structure 16 is located between the isolation structure and the drain portion 26, and the drain portion 26 can serve as the drain of the transistor structure.
本公开实施例中,请继续参考图3g,半导体结构还包括位于漏极部26表面、且沿X轴方向和Y轴方向阵列排布的有源柱。In the embodiment of the present disclosure, please continue to refer to FIG. 3g. The semiconductor structure further includes active pillars located on the surface of the drain portion 26 and arranged in an array along the X-axis direction and the Y-axis direction.
本公开实施例中,请继续参考图3g,漏极部26包括第一有源条121、第三子半导体层(图3g中未示出)和部分第二有源条123。In the embodiment of the present disclosure, please continue to refer to FIG. 3g. The drain portion 26 includes a first active strip 121, a third sub-semiconductor layer (not shown in FIG. 3g) and a part of the second active strip 123.
本公开实施例中,请继续参考图3g,半导体结构还包括金属硅化物19,金属硅化物19包括位线结构16与第一有源条121之间的第一金属硅化物191、位线结构16和第三子半导体层之间第二金属硅化物192、位线结构16与第二有源条123之间的第三金属硅化物193。In this disclosed embodiment, please continue to refer to FIG. 3g. The semiconductor structure further includes a metal silicide 19. The metal silicide 19 includes a first metal silicide 191 between the bit line structure 16 and the first active strip 121. The bit line structure The second metal silicide 192 between 16 and the third sub-semiconductor layer, and the third metal silicide 193 between the bit line structure 16 and the second active strip 123 .
本公开实施例中,请继续参考图3g,部分位线结构16位于有源柱沿Z轴方向的投影区域内。In the embodiment of the present disclosure, please continue to refer to FIG. 3g. Part of the bit line structure 16 is located in the projection area of the active pillar along the Z-axis direction.
本公开实施例中,请继续参考图3g,隔离结构为凸字形,且隔离结构包括第一U型隔离结构14和位于第一U型隔离结构14U型底部表面的第二隔离结构15,且第二隔离结构15的顶表面超出第一U型隔离结构14的顶表面;第一U型隔离结构14和第二隔离结构15均与位线结构16相接触。In the embodiment of the present disclosure, please continue to refer to FIG. 3g. The isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the U-shaped bottom surface of the first U-shaped isolation structure 14, and the The top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.
在一些实施例中,请继续参考图3g,基底包括衬底10,以及位于衬底10表面的半导体隔离层11,半导体隔离层11用于隔离位线结构16与衬底10;半导体隔离层11包括位于衬底表面的第一P型半导体层和位于第一P型半导体层表面的第一N型半导体层。In some embodiments, please continue to refer to FIG. 3g. The substrate includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10. The semiconductor isolation layer 11 is used to isolate the bit line structure 16 from the substrate 10; the semiconductor isolation layer 11 It includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer.
本公开实施例提供的半导体结构与上述实施例中的半导体结构类似,对于本公开实施例未详尽披露的技术特征,请参照上述实施例进行理解,这里,不再赘述。The semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above-mentioned embodiments for understanding, and will not be described again here.
本公开实施例中的半导体结构包括埋入式位线结构,位线结构位于有源条中的第三子半导体层与隔离结构之间,且部分位线结构位于第一有源条沿第三方向的投影区域内,相比于相关技术,本公开实施例提供的半导体结构中的有源条底部在位线结构的形成过程中未被完全刻蚀断,如此,本公开实施例可以提供一种稳定性较高的半导体结构。The semiconductor structure in the embodiment of the present disclosure includes a buried bit line structure. The bit line structure is located between the third sub-semiconductor layer and the isolation structure in the active strip, and part of the bit line structure is located on the third side of the first active strip. In the projection area of the direction, compared with the related art, the bottom of the active strip in the semiconductor structure provided by the embodiment of the present disclosure is not completely etched during the formation of the bit line structure. In this way, the embodiment of the present disclosure can provide a A highly stable semiconductor structure.
在本公开所提供的几个实施例中,应该理解到,所揭露的设备和方法,可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的,例如,单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,如:多个单元或组件可以结合,或可以集成到另一个系统,或一些特征可以忽略,或不执行。另外,所显示或讨论的各组成部分相互之间的耦合、或直接耦合。In the several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented. In addition, the components shown or discussed are coupled to each other, or directly coupled.
本公开所提供的几个方法或设备实施例中所揭露的特征,在不冲突的情况下可以任意组合,得到新的方法实施例或设备实施例。The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.
以上,仅为本公开的一些实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖 在本公开的保护范围之内。因此,本公开的保护范围应以权利要求的保护范围为准。The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, and they should all be covered. within the scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.
本公开实施例提供的半导体结构及其形成方法,其中,在埋入式位线结构的形成过程中,不用对有源条进行刻蚀,如此,可以使得有源条不易倒塌,从而使得半导体结构在形成过程中的稳定性较强。另外,本公开实施例中,通过在有源条与隔离结构之间的间隙中形成位线结构,可以简化埋入式位线结构的制备工艺过程,降低半导体结构的工艺复杂度。In the semiconductor structure and its formation method provided by embodiments of the present disclosure, during the formation process of the buried bit line structure, the active strip does not need to be etched. In this way, the active strip can be made less likely to collapse, thereby making the semiconductor structure Strong stability during the formation process. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.
Claims (24)
- 一种半导体结构的形成方法,所述方法包括:A method of forming a semiconductor structure, the method comprising:提供基底,所述基底包括沿第一方向延伸、且沿第二方向交替排列的有源条和第一沟槽;所述第一方向和所述第二方向为所述基底所在平面内的任意两个方向;A substrate is provided, the substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any direction in the plane where the substrate is located. both directions;在所述第一沟槽的底部形成沿所述第一方向延伸的隔离结构;其中,所述隔离结构与所述有源条沿所述第二方向投影区域内具有第一空隙;An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap within the projection area along the second direction;在所述第一空隙中,形成位线结构。In the first gap, a bit line structure is formed.
- 根据权利要求1所述的方法,其中,所述基底包括衬底,以及位于所述衬底表面的第一隔离层;The method of claim 1, wherein the substrate includes a substrate, and a first isolation layer located on a surface of the substrate;所述第一隔离层包括半导体隔离层和/或绝缘层,所述半导体隔离层和/或所述绝缘层用于隔离所述位线结构与所述衬底。The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
- 根据权利要求2所述的方法,其中,所述半导体隔离层至少包括位于衬底表面的第一P型半导体层和位于所述第一P型半导体层表面的第一N型半导体层;The method of claim 2, wherein the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer;所述有源条位于所述第一N型半导体层的表面。The active strip is located on the surface of the first N-type semiconductor layer.
- 根据权利要求3所述的方法,其中,所述第一P型半导体层和所述第一N型半导体层通过以下步骤形成:The method of claim 3, wherein the first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps:在所述衬底表面形成第一初始半导体层;Forming a first initial semiconductor layer on the surface of the substrate;对所述第一初始半导体层进行第一重掺杂,形成所述第一P型半导体层;Perform a first heavy doping on the first initial semiconductor layer to form the first P-type semiconductor layer;在所述第一P型半导体层的表面形成第二初始半导体层;Form a second initial semiconductor layer on the surface of the first P-type semiconductor layer;对所述第二初始半导体层进行第二重掺杂,形成所述第一N型半导体层。The second initial semiconductor layer is heavily doped a second time to form the first N-type semiconductor layer.
- 根据权利要求3所述的方法,其中,所述衬底为P型掺杂的衬底,所述半导体隔离层还包括位于衬底表面的第二N型半导体层,所述第一P型半导体层位于所述第二N型半导体层的表面。The method according to claim 3, wherein the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, the first P-type semiconductor A layer is located on the surface of the second N-type semiconductor layer.
- 根据权利要求3至5任一项所述的方法,其中,所述有源条包括第三半导体层,所述第三半导体层位于所述第一空隙沿所述第二方向的投影区域内,在形成隔离结构之后,所述方法还包括:The method according to any one of claims 3 to 5, wherein the active strip includes a third semiconductor layer located within a projection area of the first gap along the second direction, After forming the isolation structure, the method further includes:沿所述第二方向刻蚀所述第三半导体层,形成第三子半导体层;其中,所述隔离结构与所述第三子半导体层沿所述第二方向投影区域内具有第二空隙,所述第二空隙包括所述第一空隙;Etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third sub-semiconductor layer have a second gap in the projection area along the second direction, the second gap includes the first gap;在所述第二空隙中形成所述位线结构。The bit line structure is formed in the second gap.
- 根据权利要求6所述的方法,其中,所述隔离结构为凸字形,且所述隔离结构包括第一U型隔离结构和位于所述第一U型隔离结构U型底部表面的第二隔离结构;所述隔离结构通过以下步骤形成:The method of claim 6, wherein the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure. ; The isolation structure is formed by the following steps:在所述有源条的表面和所述第一沟槽的内壁,形成第一初始隔离结构;Form a first initial isolation structure on the surface of the active strip and the inner wall of the first trench;在具有所述第一初隔离结构的第一沟槽底部形成所述第二隔离结构;forming the second isolation structure at the bottom of the first trench having the first preliminary isolation structure;回刻所述第一初始隔离结构形成所述第一U型隔离结构;所述第二隔离结构的顶表面超出所述第一U型隔离结构的顶表面。The first initial isolation structure is etched back to form the first U-shaped isolation structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.
- 根据权利要求7所述的方法,其中,在形成所述位线结构之后,所述方法还包括:The method according to claim 7, wherein after forming the bit line structure, the method further comprises:对所述位线结构沿所述第二方向投影区域内的所述有源条进行掺杂,形成漏极部。The active strip in the projection area of the bit line structure along the second direction is doped to form a drain portion.
- 根据权利要求7所述的方法,其中,在形成所述位线结构之后,所述方法还包括:The method of claim 7, wherein after forming the bit line structure, the method further includes:对所述位线结构和所述有源条进行热处理,形成位于所述位线结构与所述有源条之 间的金属硅化物。The bit line structure and the active strip are heat treated to form metal silicide between the bit line structure and the active strip.
- 根据权利要求9所述的方法,其中,所述方法还包括:The method of claim 9, further comprising:在所述位线结构表面和所述第二隔离结构表面覆盖形成第三隔离结构;Forming a third isolation structure covering the surface of the bit line structure and the surface of the second isolation structure;其中,所述第三隔离结构的顶表面未超出所述有源条的顶表面。Wherein, the top surface of the third isolation structure does not exceed the top surface of the active strip.
- 根据权利要求10所述的方法,其中,在所述第三隔离结构的表面形成第四隔离结构;The method of claim 10, wherein a fourth isolation structure is formed on the surface of the third isolation structure;其中,所述第四隔离结构的顶表面与所述有源条的顶表面齐平。Wherein, the top surface of the fourth isolation structure is flush with the top surface of the active strip.
- 根据权利要求11所述的方法,其中,所述有源条和所述第一沟槽通过以下步骤形成:The method of claim 11, wherein the active strip and the first trench are formed by:在所述第一N型半导体层的表面形成半导体有源层;Form a semiconductor active layer on the surface of the first N-type semiconductor layer;在所述半导体有源层的表面形成具有第一图案的第一掩膜层;所述第一图案包括沿所述第一方向延伸、且沿所述第二方向排列的多个第一子图案,所述第一子图案暴露出部分所述半导体有源层;A first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction. , the first sub-pattern exposes part of the semiconductor active layer;通过所述第一掩膜层,去除所述第一子图案暴露出的部分所述半导体有源层,形成沿所述第一方向延伸、且沿所述第二方向交替排列所述有源条和所述第一沟槽。Through the first mask layer, the exposed portion of the semiconductor active layer of the first sub-pattern is removed to form active strips extending along the first direction and alternately arranged along the second direction. and the first trench.
- 根据权利要求12所述的方法,其中,所述方法还包括:The method according to claim 12, wherein the method further comprises:在所述有源条和所述第四隔离结构表面形成具有第二图案的第二掩膜层;所述第二图案包括沿所述第二方向延伸、且沿所述第一方向排列的多个第二子图案,所述第二子图案暴露出部分所述有源条和部分所述第四隔离结构;forming a second mask layer having a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern comprises a plurality of second sub-patterns extending along the second direction and arranged along the first direction, and the second sub-patterns expose a portion of the active strip and a portion of the fourth isolation structure;通过所述第二掩膜层,刻蚀所述第二子图案暴露出的所述有源条和部分所述第四隔离结构,或者,刻蚀所述第二子图案暴露出的所述有源条和全部所述第四隔离结构,形成沿所述第一方向交替排列的第二沟槽和有源隔离层;其中,所述第二沟槽沿第三方向上的尺寸小于或者等于所述第四隔离结构在所述第三方向上的初始尺寸;所述第二沟槽沿所述第二方向延伸,所述有源隔离层包括沿所述第二方向交替排列的有源柱和刻蚀后的第四隔离结构;Through the second mask layer, the active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched, or the active strips exposed by the second sub-pattern are etched. The source strip and all the fourth isolation structures form second trenches and active isolation layers alternately arranged along the first direction; wherein the size of the second trench along the third direction is less than or equal to the The initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etchings arranged alternately along the second direction. The fourth isolation structure behind;所述有源柱之间彼此绝缘;The active pillars are insulated from each other;在所述第二沟槽的侧壁形成字线结构,所述字线结构的顶表面未超出所述有源柱的顶表面。A word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.
- 根据权利要求13所述的方法,其中,所述方法还包括:The method of claim 13, wherein the method further includes:对位于所述字线结构沿所述第一方向投影区域之外的部分有源柱进行掺杂,形成源极部;Doping part of the active pillars located outside the projection area of the word line structure along the first direction to form a source portion;在所述有源柱的顶表面形成与所述源极部连接的电容结构,其中,所述电容结构包括依次堆叠的第一电极层、电介质层和第二电极层。A capacitor structure connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence.
- 一种半导体结构,包括:A semiconductor structure including:基底,所述基底包括沿第一方向延伸、且沿第二方向交替排列的漏极部和隔离结构;所述第一方向和所述第二方向为所述基底所在平面内的任意两个方向;A substrate, the substrate includes drain portions and isolation structures extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions in a plane where the substrate is located ;位线结构,位于所述隔离结构与所述漏极部之间。A bit line structure is located between the isolation structure and the drain portion.
- 根据权利要求15所述的半导体结构,其中,所述基底包括衬底,以及位于所述衬底表面的第一隔离层;The semiconductor structure of claim 15, wherein the base includes a substrate, and a first isolation layer located on a surface of the substrate;所述第一隔离层包括半导体隔离层和/或绝缘层,所述半导体隔离层和/或所述绝缘层用于隔离所述位线结构与所述衬底。The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
- 根据权利要求16所述的半导体结构,其中,所述半导体隔离层至少包括位于所述衬底表面的第一P型半导体层和位于所述第一P型半导体层表面的第一N型半导体层;所述漏极部位于所述第一N型半导体层的表面。The semiconductor structure of claim 16, wherein the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer. ; The drain portion is located on the surface of the first N-type semiconductor layer.
- 根据权利要求17所述的半导体结构,其中,所述衬底为P型掺杂的衬底,所述半导体隔离层还包括位于所述衬底表面的第二N型半导体层,所述第一P型半导体层位于所述第二N型半导体层的表面。The semiconductor structure according to claim 17, wherein the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, the first The P-type semiconductor layer is located on the surface of the second N-type semiconductor layer.
- 根据权利要求18所述的半导体结构,其中,所述隔离结构为凸字形,且所述隔离结构包括第一U型隔离结构和位于所述第一U型隔离结构U型底部表面的第二隔离结构;所述第二隔离结构的顶表面超出所述第一U型隔离结构的顶表面;The semiconductor structure according to claim 18, wherein the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation located on the U-shaped bottom surface of the first U-shaped isolation structure. Structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure;所述第一U型隔离结构和所述第二隔离结构均与所述位线结构相接触。The first U-shaped isolation structure and the second isolation structure are both in contact with the bit line structure.
- 根据权利要求19所述的半导体结构,其中,所述半导体结构还包括:The semiconductor structure of claim 19, wherein the semiconductor structure further comprises:第三隔离结构,所述第三隔离结构位于所述位线结构和所述第二隔离结构表面。A third isolation structure is located on the surface of the bit line structure and the second isolation structure.
- 根据权利要求20所述的半导体结构,其中,所述半导体结构还包括:The semiconductor structure of claim 20, wherein the semiconductor structure further comprises:位于所述位线结构与所述漏极部之间的金属硅化物。A metal silicide is located between the bit line structure and the drain portion.
- 根据权利要求21所述的半导体结构,其中,所述半导体结构还包括:位于所述漏极部表面、且沿所述第一方向和所述第二方向阵列排布的有源柱、以及位于所述有源柱的侧壁、且沿所述第一方向排布、沿所述第二方向延伸的字线结构;The semiconductor structure according to claim 21, wherein the semiconductor structure further comprises: active pillars located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and located on the surface of the drain portion. The sidewalls of the active pillars and word line structures arranged along the first direction and extending along the second direction;其中,所述字线结构的顶表面未超出所述有源柱的顶表面。Wherein, the top surface of the word line structure does not exceed the top surface of the active pillar.
- 根据权利要求22所述的半导体结构,其中,所述半导体结构还包括:源极部、以及与所述源极部相接的电容结构;The semiconductor structure according to claim 22, wherein the semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion;所述源极部位于所述有源柱沿所述第二方向的投影区域之外;The source portion is located outside the projection area of the active pillar along the second direction;所述电容结构位于所述有源柱的顶表面,且所述电容结构包括第一电极层、电介质层和第二电极层。The capacitor structure is located on the top surface of the active pillar, and the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer.
- 根据权利要求23所述的半导体结构,其中,部分所述位线结构位于所述有源柱沿第三方向的投影区域内,或者,所述位线结构位于所述有源柱沿所述第三方向的投影区域之外;The semiconductor structure of claim 23, wherein part of the bit line structure is located within a projection area of the active pillar along the third direction, or the bit line structure is located within the projection area of the active pillar along the third direction. Outside the projection area in three directions;所述第三方向与所述基底所在的平面相交。The third direction intersects the plane of the base.
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EP0453998A1 (en) * | 1990-04-21 | 1991-10-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a bit line constituted by a semiconductor layer |
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CN102339831A (en) * | 2010-07-20 | 2012-02-01 | 力晶科技股份有限公司 | Vertical channel transistor array and manufacturing method thereof |
CN114927523A (en) * | 2022-05-19 | 2022-08-19 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
CN115020468A (en) * | 2022-05-17 | 2022-09-06 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
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EP0453998A1 (en) * | 1990-04-21 | 1991-10-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a bit line constituted by a semiconductor layer |
US20070080385A1 (en) * | 2005-10-10 | 2007-04-12 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical transistor and method of fabricating the same |
CN102339831A (en) * | 2010-07-20 | 2012-02-01 | 力晶科技股份有限公司 | Vertical channel transistor array and manufacturing method thereof |
CN115020468A (en) * | 2022-05-17 | 2022-09-06 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
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