WO2024060333A1 - Semiconductor structure and method for forming same - Google Patents

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure and a method for forming the same. The method comprises: providing a substrate, the substrate comprising active strips and first trenches extending in a first direction and alternately arranged in a second direction, and the first direction and the second direction being any two directions in a plane where the substrate is located; forming, at a bottom portion of the first trench, an isolation structure extending in the first direction, wherein the isolation structure and the active strip have a first gap in a projection region along the second direction; and forming a bit line structure in the first gap.

Description

Semiconductor structures and methods of forming them

Cross-references to related applications

This disclosure is based on a Chinese patent application with application number 202211145434.1, the filing date is September 20, 2022, and the invention name is "Semiconductor Structure and Formation Method Thereof", and claims the priority of the Chinese patent application. This disclosure is incorporated by reference in its entirety.

Technical field

The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.

Background technique

Currently, a dynamic random access memory (DRAM) with a buried bit line structure is formed to improve the integration of DRAM and achieve miniaturization.

However, in the related art, a groove is formed by etching the bottom of the active pillar, and the bit line metal material is filled in the groove to form a buried bit line structure. Therefore, in the related art, it is easy to etch the active pillar during the etching process. causing the active column to collapse.

Contents of the invention

In view of this, embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.

In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:

A substrate is provided, the substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any direction in the plane where the substrate is located. both directions;

An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap within the projection area along the second direction;

In the first gap, a bit line structure is formed.

In some embodiments, the base includes a substrate, and a first isolation layer located on a surface of the substrate;

The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.

In some embodiments, the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer;

The active strip is located on the surface of the first N-type semiconductor layer.

In some embodiments, the first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps:

Forming a first initial semiconductor layer on the surface of the substrate;

Perform a first heavy doping on the first initial semiconductor layer to form the first P-type semiconductor layer;

Form a second initial semiconductor layer on the surface of the first P-type semiconductor layer;

The second initial semiconductor layer is heavily doped a second time to form the first N-type semiconductor layer.

In some embodiments, the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, and the first P-type semiconductor layer is located on the third The surface of the two N-type semiconductor layers.

In some embodiments, the active strip includes a third semiconductor layer located within a projection area of the first gap along the second direction, and after forming the isolation structure, the method further include:

Etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third sub-semiconductor layer have a second gap in the projection area along the second direction, the second gap includes the first gap;

The bit line structure is formed in the second gap.

In some embodiments, the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; the isolation structure Formed through the following steps:

Form a first initial isolation structure on the surface of the active strip and the inner wall of the first trench;

forming the second isolation structure at the bottom of the first trench having the first initial isolation structure;

The first initial isolation structure is etched back to form the first U-shaped isolation structure; and the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.

In some embodiments, after forming the bit line structure, the method further includes:

The active strip in the projection area of the bit line structure along the second direction is doped to form a drain portion.

In some embodiments, after forming the bit line structure, the method further includes:

The bit line structure and the active strip are heat treated to form metal silicide located between the bit line structure and the active strip.

In some embodiments, the method further includes:

A third isolation structure is formed on the surface of the bit line structure and the surface of the second isolation structure;

Wherein, the top surface of the third isolation structure does not exceed the top surface of the active strip.

In some embodiments, a fourth isolation structure is formed on the surface of the third isolation structure;

Wherein, the top surface of the fourth isolation structure is flush with the top surface of the active strip.

In some embodiments, the active strip and the first trench are formed by the following steps:

forming a semiconductor active layer on a surface of the first N-type semiconductor layer;

A first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction. , the first sub-pattern exposes part of the semiconductor active layer;

Through the first mask layer, the exposed portion of the semiconductor active layer of the first sub-pattern is removed to form active strips extending along the first direction and alternately arranged along the second direction. and the first trench.

In some embodiments, the method further includes: forming a second mask layer with a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern includes: A plurality of second sub-patterns extending and arranged along the first direction, the second sub-patterns exposing part of the active strip and part of the fourth isolation structure;

Through the second mask layer, the active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched, or the active strips exposed by the second sub-pattern are etched. The source strip and all the fourth isolation structures form second trenches and active isolation layers alternately arranged along the first direction; wherein the size of the second trench along the third direction is less than or equal to the The initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etchings arranged alternately along the second direction. The fourth isolation structure behind;

The active pillars are insulated from each other;

A word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.

In some embodiments, the method further includes: doping a portion of the active pillar located outside the projection area of the word line structure along the first direction to form a source portion;

A capacitor structure connected to the source portion is formed on a top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure, which includes:

A substrate, the substrate comprising a drain portion and an isolation structure extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within a plane where the substrate is located;

A bit line structure is located between the isolation structure and the drain portion.

In some embodiments, the base includes a substrate, and a first isolation layer located on a surface of the substrate;

The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.

In some embodiments, the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the drain portion located on the surface of the first N-type semiconductor layer.

In some embodiments, the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, and the first P-type semiconductor layer is located on the surface of the substrate. the surface of the second N-type semiconductor layer.

In some embodiments, the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure, and the third isolation structure The top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure;

The first U-shaped isolation structure and the second isolation structure are both in contact with the bit line structure.

In some embodiments, the semiconductor structure further includes:

A third isolation structure is located on the surface of the bit line structure and the second isolation structure.

In some embodiments, the semiconductor structure further includes:

Metal suicide between the bit line structure and the drain portion.

In some embodiments, the semiconductor structure further includes: active pillars located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and an array located on the active pillar. sidewalls, and word line structures arranged along the first direction and extending along the second direction;

Wherein, the top surface of the word line structure does not exceed the top surface of the active pillar.

In some embodiments, the semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion;

The source portion is located outside the projection area of the active pillar along the second direction;

The capacitive structure is located on the top surface of the active pillar, and the capacitive structure includes a first electrode layer, a dielectric layer and a second electrode layer.

In some embodiments, part of the bit line structure is located within the projection area of the active pillar along the third direction, or the bit line structure is located within the projection area of the active pillar along the third direction. outside;

The third direction intersects with the plane where the base is located.

In the semiconductor structure and its formation method provided by embodiments of the present disclosure, during the formation process of the buried bit line structure, the active strip does not need to be etched. In this way, the active strip can be made less likely to collapse, thereby making the semiconductor structure Strong stability during the formation process. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.

Description of the drawings

In the drawings (which are not necessarily to scale), similar reference characters may describe similar components in the different views. Similar reference numbers with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example, and not limitation.

Figure 1 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure;

Figures 2a to 2o are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure;

3a to 3g are structural schematic diagrams of another semiconductor structure forming process provided by embodiments of the present disclosure;

FIG. 4 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that a thorough understanding of the disclosure will be provided, and the scope of the disclosure will be fully conveyed to those skilled in the art.

In the following description, numerous details are given in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features that are well known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer , adjacent, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily imply the presence of the first element, component, region, layer or section in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

Before introducing the embodiments of the present disclosure, let us first define the three directions that may be used to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction of intersection (eg, perpendicular) with the top and bottom surfaces of the substrate is defined as third direction. In the direction of the top surface and the bottom surface of the substrate (that is, the plane on which the substrate is located), two directions that intersect each other (for example, are perpendicular to each other) are defined. For example, the direction in which the bit line structure extends can be defined as the first direction, and the direction in which the bit line structure is arranged can be defined. The direction is a second direction, and the plane direction of the substrate can be determined based on the first direction and the second direction. In the embodiment of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular to each other. In the embodiment of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

An embodiment of the disclosure provides a method for forming a semiconductor structure. Figure 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 1, the method for forming a semiconductor structure includes the following steps:

Step S101: Provide a substrate, which includes active strips and first trenches extending along a first direction and alternately arranged along a second direction.

In the embodiment of the present disclosure, the substrate at least includes a semiconductor substrate. The semiconductor substrate may be a silicon substrate. The semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or a semiconductor compound, such as silicon carbide (SiC). ), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys such as silicon germanium (SiGe) , gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide ( GaInAsP) or a combination thereof.

In some embodiments, the substrate includes a substrate, and a first isolation layer located on the surface of the substrate; the first isolation layer may include a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer are used to isolate the bit lines. Structure and substrate. For example, the first isolation layer may include a semiconductor isolation layer, or the first isolation layer may include an insulating layer, or the first isolation layer may include a semiconductor isolation layer and an insulating layer; wherein, when the first isolation layer includes a semiconductor isolation layer and an insulating layer , the insulating layer may be located on the surface of the semiconductor isolation layer, and the semiconductor isolation layer may also be located on the surface of the insulating layer.

In some embodiments, the material of the insulating layer may be silicon oxide, or other suitable materials. The semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the active strip is located on the surface of the first N-type semiconductor layer.

In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not be turned on, thereby preventing leakage of the bit line structure.

In other embodiments, the substrate may be a P-type doped silicon substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, and the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer. surface. At this time, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the second N-type semiconductor layer and the P-type doped silicon substrate form another PN junction. In this way, the bit line structure is applied At high voltage, both PN junctions are reverse biased, which can more effectively prevent leakage of the bit line structure.

In some embodiments, the active strip may include a third semiconductor layer located within a projection area of the first gap along the second direction, and the third semiconductor layer may be a silicon germanium layer.

Step S102: Form an isolation structure extending along the first direction at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area along the second direction.

In the embodiment of the present disclosure, the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; wherein the first U-shaped isolation structure is used to isolate the subsequently formed bit line structure from the substrate to prevent leakage; and the second isolation structure is used to isolate two adjacent isolation structures subsequently formed.

Step S103: Form a bit line structure in the first gap.

In embodiments of the present disclosure, a bit line structure can be formed by depositing bit line conductive materials in the first gap; wherein the bit line conductive materials include: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al ), titanium nitride (TiN), titanium-containing metal layers, polysilicon, or any combination thereof.

The method for forming a semiconductor structure provided by embodiments of the present disclosure does not require etching the active strip during the formation process of the buried bit line structure. In this way, the active strip is less likely to collapse, thereby making the semiconductor structure less susceptible to collapse during the formation process. The stability in the medium is strong. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.

2a to 2o are schematic structural diagrams of the semiconductor structure formation process provided by the embodiment of the present disclosure. The formation process of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2a to 2o. Among them, Figure 2h is a cross-sectional view along c-c', Figure 2i is a cross-sectional view along a-a', b-b', and d-d' in Figure 2h, Figure 2l is a cross-sectional view along a-a', Figure 2m Figure 2n is a cross-sectional view along e-e' and c-c' in Figure 2l, and Figure 2n is a cross-sectional view along b-b' and d-d' in Figure 2m.

First, referring to FIGS. 2a to 2d , step S101 is performed to provide a substrate. The substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction.

As shown in Figure 2a, the base includes a substrate 10 and a first isolation layer located on the surface of the substrate 10, wherein the first isolation layer includes a semiconductor isolation layer 11, and the semiconductor isolation layer 11 includes a first P layer located on the surface of the substrate 10. type semiconductor layer 11a and the first N-type semiconductor layer 11b located on the surface of the first P-type semiconductor layer 11a. In other embodiments, the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.

In some embodiments, the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b may be formed by the following steps: forming a first initial semiconductor layer (not shown) on the surface of the substrate 10; Perform the first heavy doping to form the first P-type semiconductor layer 11a; form a second initial semiconductor layer (not shown) on the surface of the first P-type semiconductor layer; perform the second heavy doping on the second initial semiconductor layer, The first N-type semiconductor layer 11b is formed.

In the embodiment of the present disclosure, the first heavily doped doping element may be a Group III element, such as a trivalent impurity element such as boron, gallium, indium, etc.; the second heavily doped element may be a Group V element, For example, they are pentavalent impurity elements such as phosphorus, antimony, and arsenic.

In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, the bit line structure is close to the N end of the PN junction. When a high voltage is applied to the line structure, the PN junction is reverse biased and will not conduct. Since the reverse resistance of the PN junction is very high, this can isolate the bit line structure and the substrate and prevent leakage of the bit line structure.

For ease of understanding, only the semiconductor isolation layer 11 is shown in FIGS. 2b to 2o , and the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b in the semiconductor isolation layer 11 are not shown.

In some embodiments, the active strip and the first trench may be formed by the following steps: forming a semiconductor active layer on the surface of the first N-type semiconductor layer; forming a first pattern with a first pattern on the surface of the semiconductor active layer. Mask layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction, and the first sub-pattern exposes part of the semiconductor active layer; through the first mask layer, the first sub-pattern is removed The portion of the semiconductor active layer exposed by the sub-pattern forms active strips and first trenches extending along the first direction and alternately arranged along the second direction.

As shown in FIG. 2b, a semiconductor active layer 12a is formed on the surface of the first N-type semiconductor layer (ie, the semiconductor isolation layer 11).

In this disclosed embodiment, the semiconductor active layer 12a can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or other suitable processes.

As shown in Figures 2b to 2d, a first mask layer 25 having a first pattern is formed on the surface of the semiconductor active layer 12a; the first pattern includes a plurality of first patterns extending along the X-axis direction and arranged along the Y-axis direction. A sub-pattern E, the first sub-pattern E exposes part of the semiconductor active layer 12a; through the first mask layer 25, the part of the semiconductor active layer 12a exposed by the first sub-pattern E is removed, forming a And the active strips 12 and the first trenches 13 are alternately arranged along the Y-axis direction.

In the embodiment of the present disclosure, the material of the first mask layer 25 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the first mask layer 25 may be made of any suitable material. Formed by deposition process.

In the embodiment of the present disclosure, after forming the active strip 12 and the first trench 13 , the method of forming the semiconductor structure further includes: removing the first mask layer 25 to expose the upper surface of the active strip 12 .

Next, refer to FIG. 2e to FIG. 2g to perform step S102 to form an isolation structure extending along the first direction at the bottom of the first trench; wherein, the isolation structure and the active strip have a first projection area along the second direction. gap.

In some embodiments, the isolation structure is convex, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure; the isolation structure can be formed by the following steps: The surface of the source bar and the inner wall of the first trench form a first initial isolation structure; a second isolation structure is formed at the bottom of the first trench with the first initial isolation structure; and the first initial isolation structure is carved back to form a first U-shape Isolation structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.

As shown in Figure 2e, a first isolation material is deposited on the surface of the active strip 12 and the inner wall of the first trench 13 to form a first initial isolation structure 14a; the first isolation material may be silicon oxide, or other suitable materials.

As shown in Figure 2f, a second isolation material is deposited in the first trench 13 with the first initial isolation structure 14a to form a second initial isolation structure (not shown); the second initial isolation structure is etched back to form a second Isolation structure 15; the second isolation material may be silicon nitride, or other suitable materials.

In the embodiment of the present disclosure, during the process of etching back the second initial isolation structure, the etching selectivity ratio between the second isolation material and the substrate is greater than the etching selectivity ratio between the first isolation material and the substrate, for example , the etching selectivity ratio between the second isolation material and the substrate is 3 to 10 times the etching selectivity ratio between the first isolation material and the substrate. In this way, the second initial isolation structure can be etched back without damaging it. First initial isolation structure 14a.

In the embodiment of the present disclosure, the first initial isolation structure 14a and the second initial isolation structure may be formed through any suitable deposition process.

As shown in Figure 2g, the first initial isolation structure 14a (refer to Figure 2f) is etched back to form the first U-shaped isolation structure 14, which can be achieved by a dry etching process (such as a plasma etching process, a reactive ion etching process or an ion etching process). milling process) to engrave back the first initial isolation structure. In this disclosed embodiment, the top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14 .

In the disclosed embodiment, the isolation structure is in a convex shape, and a first gap 16 a is present in the projection area between the isolation structure (ie, the second isolation structure 15 ) and the active strip 12 along the Y-axis direction.

In the embodiment of the present disclosure, during the process of etching back the first initial isolation structure, the etching selectivity ratio between the first isolation material and the substrate is greater than the etching selectivity ratio between the second isolation material and the substrate, for example , the etching selectivity ratio between the first isolation material and the substrate is 5 to 10 times the etching selectivity ratio between the second isolation material and the substrate. In this way, it is not necessary to etch back the first initial isolation structure 14a. The second isolation structure 15 is damaged.

In the embodiment of the present disclosure, the first U-shaped isolation structure 14 located in the convex-shaped isolation structure is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 14 located in the convex-shaped isolation structure 15 is used to isolate two adjacent bit line structures located in the same first trench 13 to prevent leakage of the bit line structures, thereby improving the electrical performance of the semiconductor structure.

In other embodiments, the first U-shaped isolation structure may also be a semiconductor isolation layer, or the first U-shaped isolation structure may also be a composite isolation structure composed of a semiconductor isolation layer and an insulating layer (for example, an oxide layer).

Finally, referring to Figures 2h to 2o, step S103 is performed to form a bit line structure in the first gap.

As shown in FIGS. 2h and 2i , a bit line metal material is deposited in the first trench 13 with an isolation structure to form an initial bit line structure (not shown), and the initial bit line structure is etched back to form a bit line structure 16 .

In the embodiment of the present disclosure, the bit line metal material includes: tungsten, cobalt, copper, aluminum, titanium nitride, titanium-containing metal layer, polysilicon or any combination thereof.

In the embodiment of the present disclosure, the initial bit line structure can be etched back through a dry etching process to form the bit line structure 16 .

It should be noted that the top surface of the bit line structure 16 in the embodiment of the present disclosure does not exceed the top surface of the second isolation structure 15 . In other embodiments, the top surface of bit line structure 16 may be flush with the top surface of second isolation structure 15 .

In some embodiments, after forming the bit line structure, the method of forming the semiconductor structure further includes: removing residual metal located in the first trench 13 through a wet etching process.

In the embodiment of the present disclosure, after removing the residual metal located in the first trench 13 , the method of forming the semiconductor structure further includes: thermally oxidizing and growing silicon oxide of a predetermined thickness on the surfaces of the second isolation structure 15 and the bit line structure 16 , silicon oxide is used to further remove residual metal on the sidewalls of the active strip 12 to prevent silicide from forming on the surface of the channel structure during subsequent processes. In embodiments of the present disclosure, the preset thickness may be 1 to 5 nanometers (nm).

In some embodiments, after removing the residual metal, the method of forming the semiconductor structure further includes: covering the surface of the bit line structure and the surface of the isolation structure to form a third isolation structure; wherein the top surface of the third isolation structure does not exceed the active The top surface of the strip.

As shown in FIG. 2j, a third isolation material is deposited on the surface of the bit line structure 16 and the second isolation structure 15 to form the third isolation structure 17. The third isolation material may be silicon oxide, silicon oxynitride, or other suitable materials. .

In the embodiment of the present disclosure, a third isolation material can be deposited through an atomic deposition process to form the third isolation structure 17 to improve the quality of the film layer.

In some embodiments, as shown in FIG. 2k , after forming the third isolation structure 17 , the method of forming the semiconductor structure further includes: performing heat treatment on the bit line structure 16 and the active strip 12 to form a layer between the bit line structure 16 and the active strip 12 . Metal silicide 19 between source bars 12 .

In the embodiment of the disclosure, the bit line metal material and the active strip 12 can react with each other through a Rapid Thermal Processing (RTP) process, thereby forming metal silicide 19 on the surface of the active strip 12 . Since the metal silicide has a lower resistance, the contact resistance between the bit line structure 16 and the active strip 12 can be reduced, thereby reducing the power consumption of the semiconductor structure.

Please continue to refer to FIG. 2k. After forming the metal silicide, the formation method of the semiconductor structure also includes: doping the active strip 12 in the projection area of the bit line structure along the Y-axis direction to form a drain portion 26. 26 can be used as the drain D of the transistor structure.

In the embodiment of the present disclosure, ions are implanted into the active strip 12 in the projection area of the bit line structure along the Y-axis direction to form the drain D. Ion implantation can be achieved through processes such as thermal diffusion and plasma doping. The energy and dosage used in the ion implantation process and the type of implanted ions can be determined according to the type of transistor to be formed, for example, P-type metal oxide semiconductor ( P-Metal-Oxide-Semiconductor (PMOS) can perform shallow-depth, heavily doped BF ₂₊ ion implantation; N-type metal-oxide semiconductor (N-Metal ^- Oxide-Semiconductor, NMOS) can perform shallow-depth, heavily doped Arsenic ion implantation. After ion implantation, a high-temperature annealing process can also be included, which can repair the lattice damage caused by the ion implantation and activate the ion-implanted impurities.

It should be noted that in the embodiment of the present disclosure, the order in which the drain D, the metal silicide 19 and the third isolation structure 17 are formed is not limited. For example, the drain D may be formed first, then the third isolation structure 17 may be formed, and finally Form the metal silicide 19; you can also form the metal silicide 19 first, then form the third isolation structure 17, and finally form the drain D; you can also form the drain D first, then form the metal silicide 19, and finally form the third isolation structure 17.

In some embodiments, the method for forming a semiconductor structure further includes: forming a fourth isolation structure on a surface of the third isolation structure; wherein a top surface of the fourth isolation structure is flush with a top surface of the active strip.

Please continue to refer to FIG. 2k. A fourth isolation material is deposited on the surface of the third isolation structure 17 to form a fourth isolation structure 18. The fourth isolation material may be silicon oxide, silicon oxynitride or other suitable materials. The third isolation material The material and the fourth isolation material may be the same or different.

It should be noted that, during the process of depositing the fourth isolation material on the surface of the third isolation structure 17 and forming the fourth isolation structure 18, part of the fourth isolation material is often deposited on the surface of the active strip 12, and then passes through Chemical Mechanical Polishing (CMP) treatment is performed so that the top surface of the fourth isolation structure 18 is flush with the top surface of the active strip 12 .

In some embodiments, after forming the fourth isolation structure 18 , the method of forming the semiconductor structure further includes forming a word line structure, a source portion, and a capacitor structure.

In some embodiments, the word line structure may be formed by the following steps: forming a second mask layer with a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern includes extending along the second direction and extending along the second direction. A plurality of second sub-patterns are arranged in one direction, and the second sub-pattern exposes part of the active strip and part of the fourth isolation structure; through the second mask layer, the active strip and part of the fourth isolation structure exposed by the second sub-pattern are etched. Four isolation structures, or etching the active strips and all fourth isolation structures exposed by the second sub-pattern to form second trenches and active isolation layers alternately arranged along the first direction; wherein, the second trench is The size in the third direction is less than or equal to the initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etched pillars alternately arranged along the second direction. The fourth isolation structure; the active pillars are insulated from each other; a word line structure is formed on the side wall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.

As shown in Figures 2l to 2n, a second mask layer 27 with a second pattern is formed on the surface of the active strip 12 and the fourth isolation structure 18; the second pattern includes lines extending along the Y-axis direction and arranged along the X-axis direction. A plurality of second sub-patterns F, the second sub-pattern F exposes part of the active strip 12 and part of the fourth isolation structure 18; through the second mask layer 27, the part of the active strip exposed by the second sub-pattern F is etched 12 and part of the fourth isolation structure 18 until the third isolation structure 17 is exposed, forming second trenches 22a and active isolation layers 20 alternately arranged along the X-axis direction; wherein the second trenches 22a extend along the Y-axis direction. , the active isolation layer 20 includes active pillars 21 alternately arranged along the Y-axis direction and etched fourth isolation structures 18. The active pillars 21 are insulated from each other by the fourth isolation structure 18. In the embodiment of the present disclosure, the size d1 of the second trench 22a in the Z-axis direction (as shown in FIG. 2l) is equal to the initial size d2 of the fourth isolation structure 18 in the Z-axis direction (as shown in FIG. 2m).

In other embodiments, part of the active strip 12 and part of the fourth isolation structure 18 exposed by the second sub-pattern F are etched through the second mask layer 27 to form second trenches 22a alternately arranged along the X-axis direction. and active isolation layer 20; wherein, the second trench 22a extends along the Y-axis direction, and the active isolation layer 20 includes an active pillar 21 and a fourth isolation located between two adjacent active pillars 21 along the Y-axis direction. The structure 18 and the active pillar 21 are insulated from each other by the fourth isolation structure 18. The size of the second trench 22a in the Z-axis direction is smaller than the initial size d2 of the fourth isolation structure 18 in the Z-axis direction.

In the embodiment of the present disclosure, the material of the second mask layer 27 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the second mask layer 27 may be made of any suitable material. Formed by deposition process.

In some embodiments, after the active isolation layer 20 is formed, the method of forming the semiconductor structure further includes: removing the second mask layer 27 having the second pattern.

As shown in Figure 2n and Figure 2o, a gate dielectric layer 221 is sequentially deposited on the sidewall of the second trench 22a, and a gate conductive layer located on the surface of the gate dielectric layer 221, wherein the gate conductive layer can be used as a word The top surface of the line structure 22 and the word line structure 22 do not exceed the top surface of the active pillar. In the embodiment of the present disclosure, the active pillar 21 located in the projection area of the word line structure 22 along the X-axis direction forms a channel structure.

In some embodiments, the material of the gate dielectric layer 221 can be silicon oxide or other suitable materials; the material of the gate conductive layer can be any material with good conductivity, such as titanium (Ti), nitride, etc. Any one of titanium (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu). The gate dielectric layer and the gate conductive layer can be formed by any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.

It should be noted that the gate structure in the embodiment of the present disclosure is a double gate structure. In other embodiments, the etched fourth isolation structure 18 between the active pillars 21 can also be removed. The surface of 21 forms a full ring gate structure.

In some embodiments, after the word line structure 22 is formed, the method of forming the semiconductor structure further includes: depositing a fifth isolation material in the second trench 22a having the word line structure 22 to form a fifth isolation structure 23. The isolation material may be silicon oxide or other suitable materials, and the fifth isolation structure 23 is used to isolate two adjacent word line structures 22 .

In some embodiments, referring to FIG. 2o, after forming the word line structure 22, the method of forming the semiconductor structure further includes: performing ion implantation on the active pillar 21 outside the projection area of the word line structure 22 along the X-axis direction to form a source electrode. part, wherein the source part may serve as the source S of the transistor structure.

The source and drain in the embodiment of the present disclosure are located on both sides of the channel structure along the third direction. That is, the transistor structure in the embodiment of the present disclosure is vertical. The vertical transistor structure (or channel structure) can The semiconductor structure has a higher arrangement density. In this way, the integration level of the semiconductor structure can be improved and shrinkage can be achieved.

In some embodiments, after the source portion is formed, a capacitor structure connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence. .

Please continue to refer to FIG. 2 o , a capacitor structure 24 connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer 241 , a dielectric layer 242 , and a second electrode layer 243 stacked in sequence.

In the embodiment of the present disclosure, the material of the first electrode layer 241 and the material of the second electrode layer 243 may include metal nitride or metal silicide, for example, titanium nitride. The material of the dielectric layer 242 may include a high-K dielectric material, such as lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), or hafnium silicate. One or any combination of (HfSiO _x ) or zirconium oxide (ZrO ₂ ).

In the embodiment of the present disclosure, the first electrode layer 241, the dielectric layer 242 and the second electrode layer 243 can be formed by any one of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.

The method for forming a semiconductor structure provided by embodiments of the present disclosure does not require etching the active strip during the formation process of the buried bit line structure. In this way, the active strip can be less likely to collapse, thereby making the semiconductor structure less susceptible to collapse during the formation process. The stability in the medium is strong. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.

3a to 3g are structural schematic diagrams of the formation process of another semiconductor structure provided by an embodiment of the present disclosure. The formation process of another semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 3a to 3g.

First, referring to FIGS. 3a and 3b , active strips 12 and first trenches 13 are formed extending along the X-axis direction and alternately arranged along the Y-axis direction.

As shown in Figure 3a, the base includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10. The semiconductor isolation layer 11 includes a first P-type semiconductor layer 11a located on the surface of the substrate 10 and a first P-type semiconductor layer 11a located on the surface of the substrate 10. The first N-type semiconductor layer 11b on the surface of 11a.

For ease of understanding, only the semiconductor isolation layer 11 is shown in FIGS. 3b to 3g , and the first P-type semiconductor layer 11 a and the first N-type semiconductor layer 11 b in the semiconductor isolation layer 11 are not shown.

In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the subsequently formed bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction, so , when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct, thus preventing leakage of the bit line structure.

Please continue to refer to FIG. 3a. On the surface of the first N-type semiconductor layer 11b (ie, the semiconductor isolation layer 11), a first semiconductor active layer 121a, a third initial semiconductor layer 122a, and a second semiconductor active layer 123a are sequentially formed; The semiconductor active layer 121a, the third initial semiconductor layer 122a, and the second semiconductor active layer 123a constitute the semiconductor active layer 12a. In the embodiment of the present disclosure, the first semiconductor active layer 121a and the second semiconductor active layer 123a may be silicon layers, and the third initial semiconductor layer 122a may be a silicon germanium layer.

As shown in FIG. 3 b , the semiconductor active layer 12 a is etched to form active strips 12 and first trenches 13 extending along the X-axis direction and alternately arranged along the Y-axis direction. The active strip 12 includes a first active strip 121, a third semiconductor layer 122, and a second active strip 123 arranged in sequence from bottom to top along the Z-axis direction.

Next, please refer to Figure 3b to Figure 3d to form an isolation structure.

Please continue to refer to FIG. 3b and FIG. 3c. A first initial isolation structure 14a is formed on the surface of the active strip 12 and the inner wall of the first trench 13; a second initial isolation structure 14a is formed in the first trench 13 having the first initial isolation structure 14a. Initial isolation structure (not shown); etching back the second initial isolation structure to form second isolation structure 15 .

As shown in FIG. 3d , the first initial isolation structure 14a is etched back to form the first U-shaped isolation structure 14. The second isolation structure 15 and the first U-shaped isolation structure 14 together form an isolation structure. The isolation structure and the third semiconductor layer 122 have a first gap 16a in the projection area along the second direction.

In the embodiment of the present disclosure, the first U-shaped isolation structure 14 is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 15 is used to isolate the phases located in the same first trench 13 There are two adjacent bit line structures to prevent leakage of the bit line structure.

Next, referring to Figures 3e to 3g, after forming the isolation structure, the method of forming the semiconductor structure also includes: laterally etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third semiconductor layer are etched laterally in the second direction. The three sub-semiconductor layer has a second gap in the projection area along the second direction, and the second gap includes the first gap; a bit line structure is formed in the second gap.

As shown in Figures 3e and 3f, the third semiconductor layer 122 is laterally etched along the Y-axis direction to form the third sub-semiconductor layer 28; wherein, the isolation structure is a convex shape, and the isolation structure (or the second isolation structure 15) and The third sub-semiconductor layer 28 has a second gap 16b in the projection area along the Y-axis direction. The second gap 16b includes the first gap 16a; the bit line structure 16 is formed in the second gap 16b.

In the embodiment of the present disclosure, the isolation structure is in a convex shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structure and the substrate to prevent leakage and improve the electrical performance of the semiconductor structure.

In the embodiment of the disclosure, a wet etching process can be used to laterally etch the third semiconductor layer 122 to form the third sub-semiconductor layer 28; the wet etching solution can be hydrofluoric acid (DHF) or diluted The mixed solution of hydrofluoric acid and ammonia (NH ₄ OH) may also be a mixed solution of diluted hydrofluoric acid and tetramethylammonium hydroxide (TMAH).

As shown in FIG. 3g , after forming the bit line structure 16 , the method of forming the semiconductor structure further includes: rapidly performing a quick process on the bit line structure 16 , the first active strip 121 , the second active strip 123 , and the third sub-semiconductor layer 28 . Heat treatment to form the first metal silicide 191 between the bit line structure 16 and the first active strip 121 , the third metal silicide 193 between the bit line structure 16 and the second active strip 123 , and the A second metal suicide 192 between the line structure 16 and the third sub-semiconductor layer 28 (not shown in Figure 3g). Among them, the first metal silicide 191 , the second metal silicide 192 and the third metal silicide 193 constitute the metal silicide 19 . In the embodiment of the present disclosure, since the metal silicide 19 has a lower resistance, the contact resistance between the bit line structure 16 and the second active strip 123 and the bit line structure 16 and the third sub-semiconductor layer can be reduced. In turn, the power consumption of the semiconductor structure can be reduced.

In the embodiment of the present disclosure, a third isolation structure is formed covering the surface of the bit line structure 16 and the surface of the second isolation structure 15 .

In some embodiments, the method of forming the semiconductor structure further includes forming a drain portion, a word line structure, a source portion and a capacitor structure.

The formation method of the drain part, word line structure, source part and capacitor structure in the embodiment of the present disclosure is similar to the formation method of the drain part, word line structure, source part and capacitor structure in the above embodiments. For details, please Please refer to the above embodiments for understanding.

The method for forming a semiconductor structure provided by embodiments of the present disclosure does not require complete etching of the active strip during the formation process of the buried bit line structure. In this way, the active strip is less likely to collapse, and the active strip can be A bit line structure is formed between the third sub-semiconductor layer in the strip and the isolation structure, and part of the bit line structure is located in the projection area of the first active strip along the third direction, thus improving the production yield of the semiconductor structure.

The method of forming a semiconductor structure provided by the embodiments of the present disclosure is similar to the method of forming the semiconductor structure in the above-mentioned embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above-mentioned embodiments for understanding, and will not be described again here.

In addition, the embodiment of the present disclosure further provides a semiconductor structure, which is formed by the method for forming the semiconductor structure in the above embodiment. Figure 4 is a structural schematic diagram of a semiconductor structure provided by the embodiment of the present disclosure. The semiconductor structure 100 includes: a substrate, the substrate includes a drain portion 26 and an isolation structure extending along the X-axis direction and alternately arranged along the Y-axis direction; a bit line structure 16, located between the isolation structure and the drain portion 26, and the drain portion 26 can serve as the drain D of the transistor structure.

In some embodiments, the substrate includes a substrate, and a first isolation layer located on the surface of the substrate; the first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or insulating layer is used to isolate the bit line structure. with substrate.

In the embodiment of the present disclosure, please continue to refer to FIG. 4 , the base includes a substrate 10 and a first isolation layer located on the surface of the substrate 10 , wherein the first isolation layer includes a semiconductor isolation layer 11 .

In other embodiments, the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.

In this disclosed embodiment, please continue to refer to FIG. 4 , the semiconductor isolation layer 11 is used to isolate the bit line structure 16 and the substrate 10; the semiconductor isolation layer at least includes a first P-type semiconductor layer 11a located on the surface of the substrate and a first P-type semiconductor layer 11a located on the surface of the substrate. The first N-type semiconductor layer 11b is located on the surface of the N-type semiconductor layer 11a; the drain portion 26 is located on the surface of the first N-type semiconductor layer 11b.

In the embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer may form a PN junction, and the bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, the bit line structure is close to the N end of the PN junction. When a high voltage is applied to the line structure, the PN junction is reverse biased and will not conduct. In this way, leakage of the bit line structure can be prevented.

In other embodiments, the substrate 10 is a P-type doped substrate, the semiconductor isolation layer 11 may also include a second N-type semiconductor layer located on the surface of the substrate 10, and the first P-type semiconductor layer is located on the second N-type semiconductor layer. s surface. At this time, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the second N-type semiconductor layer and the P-type doped silicon substrate form another PN junction. In this way, the bit line structure is applied At high voltage, both PN junctions are reverse biased, which can more effectively prevent leakage of the bit line structure.

In some embodiments, please continue to refer to Figure 4, the isolation structure is convex-shaped, and the isolation structure includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the U-shaped bottom surface of the first U-shaped isolation structure 14, And the top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.

In the embodiment of the present disclosure, the isolation structure is in a convex shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structure and the substrate to prevent leakage and improve the electrical performance of the semiconductor structure.

In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a third isolation structure 17 , the third isolation structure 17 is located on the surface of the bit line structure 16 and the surface of the second isolation structure 15 .

In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a metal silicide 19 located between the bit line structure 16 and the drain portion 26 . Since the metal silicide 19 has a low resistance, the contact resistance between the bit line structure 16 and the drain portion 26 can be reduced, thereby reducing the power consumption of the semiconductor structure.

In some embodiments, please continue to refer to Figure 4, the semiconductor structure 100 also includes: an active pillar 21 located on the surface of the drain portion 26 and arranged in an array along the X-axis direction and the Y-axis direction, and a word line structure 22 located on the side wall of the active pillar 21, arranged along the X-axis direction and extending along the Y-axis direction; wherein the top surface of the word line structure 22 does not exceed the top surface of the active pillar 21.

In the embodiment of the present disclosure, the semiconductor structure 100 further includes: a fourth isolation structure 18. The active pillars 21 and the fourth isolation structures 18 alternately arranged in the Y-axis direction constitute the active isolation layer 20. In other embodiments, the fourth isolation structure 18 may not be included.

In the embodiment of the present disclosure, the bit line structure 16 is located outside the projection area of the active pillar 21 along the Z-axis direction.

In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a gate structure, the gate structure includes a gate conductive layer on the surface of the gate dielectric layer 221 , wherein the gate conductive layer can serve as the word line structure 22 .

In some embodiments, please continue to refer to FIG. 4 . The semiconductor structure 100 further includes: a source portion and a capacitor structure 24 connected to the source portion. The source portion is located within the projection area of the active pillar 21 along the Y-axis direction. Outside; wherein, the source portion can be used as the source S of the transistor structure. The capacitive structure 24 is located on the top surface of the active pillar 21 , and the capacitive structure 24 includes a first electrode layer 241 , a dielectric layer 242 and a second electrode layer 243 .

In some embodiments, please continue to refer to FIG. 4 , the semiconductor structure 100 further includes: a fifth isolation structure 23 , the fifth isolation structure 23 is located between the word line structures 22 adjacent to each other along the X-axis direction and between the source portions adjacent to each other along the X-axis direction.

The semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure formed by the method of forming the semiconductor structure in the above embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and will not be described again here. .

The semiconductor structure in the embodiment of the present disclosure includes a buried bit line structure. The bit line structure is located between the active strip and the isolation structure. Compared with the related art, the bottom of the active strip in the semiconductor structure provided by the embodiment of the present disclosure is at The bit line structure is not etched or completely etched during the formation process. In this way, embodiments of the present disclosure can provide a semiconductor structure with higher stability.

Embodiments of the present disclosure also provide a semiconductor structure, which is formed by the formation method of the semiconductor structure in the above embodiment. Please continue to refer to FIG. 3g. The semiconductor structure includes: a substrate extending along the X-axis direction and alternately arranged along the Y-axis direction. The drain portion 26 and the isolation structure; the bit line structure 16 is located between the isolation structure and the drain portion 26, and the drain portion 26 can serve as the drain of the transistor structure.

In the embodiment of the present disclosure, please continue to refer to FIG. 3g. The semiconductor structure further includes active pillars located on the surface of the drain portion 26 and arranged in an array along the X-axis direction and the Y-axis direction.

In the embodiment of the present disclosure, please continue to refer to FIG. 3g. The drain portion 26 includes a first active strip 121, a third sub-semiconductor layer (not shown in FIG. 3g) and a part of the second active strip 123.

In this disclosed embodiment, please continue to refer to FIG. 3g. The semiconductor structure further includes a metal silicide 19. The metal silicide 19 includes a first metal silicide 191 between the bit line structure 16 and the first active strip 121. The bit line structure The second metal silicide 192 between 16 and the third sub-semiconductor layer, and the third metal silicide 193 between the bit line structure 16 and the second active strip 123 .

In the embodiment of the present disclosure, please continue to refer to FIG. 3g. Part of the bit line structure 16 is located in the projection area of the active pillar along the Z-axis direction.

In the embodiment of the present disclosure, please continue to refer to FIG. 3g. The isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the U-shaped bottom surface of the first U-shaped isolation structure 14, and the The top surface of the second isolation structure 15 exceeds the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.

In some embodiments, please continue to refer to FIG. 3g. The substrate includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10. The semiconductor isolation layer 11 is used to isolate the bit line structure 16 from the substrate 10; the semiconductor isolation layer 11 It includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer.

The semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments. For technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above-mentioned embodiments for understanding, and will not be described again here.

The semiconductor structure in the embodiment of the present disclosure includes a buried bit line structure. The bit line structure is located between the third sub-semiconductor layer and the isolation structure in the active strip, and part of the bit line structure is located on the third side of the first active strip. In the projection area of the direction, compared with the related art, the bottom of the active strip in the semiconductor structure provided by the embodiment of the present disclosure is not completely etched during the formation of the bit line structure. In this way, the embodiment of the present disclosure can provide a A highly stable semiconductor structure.

In the several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented. In addition, the components shown or discussed are coupled to each other, or directly coupled.

The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, and they should all be covered. within the scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

In the semiconductor structure and its formation method provided by embodiments of the present disclosure, during the formation process of the buried bit line structure, the active strip does not need to be etched. In this way, the active strip can be made less likely to collapse, thereby making the semiconductor structure Strong stability during the formation process. In addition, in embodiments of the present disclosure, by forming a bit line structure in the gap between the active strip and the isolation structure, the preparation process of the buried bit line structure can be simplified and the process complexity of the semiconductor structure can be reduced.

Claims (24)

1. A method of forming a semiconductor structure, the method comprising:

   A substrate is provided, the substrate includes active strips and first trenches extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any direction in the plane where the substrate is located. both directions;

   An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap within the projection area along the second direction;

   In the first gap, a bit line structure is formed.
2. The method of claim 1, wherein the substrate includes a substrate, and a first isolation layer located on a surface of the substrate;

   The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
3. The method of claim 2, wherein the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer;

   The active strip is located on the surface of the first N-type semiconductor layer.
4. The method of claim 3, wherein the first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps:

   Forming a first initial semiconductor layer on the surface of the substrate;

   Perform a first heavy doping on the first initial semiconductor layer to form the first P-type semiconductor layer;

   Form a second initial semiconductor layer on the surface of the first P-type semiconductor layer;

   The second initial semiconductor layer is heavily doped a second time to form the first N-type semiconductor layer.
5. The method according to claim 3, wherein the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, the first P-type semiconductor A layer is located on the surface of the second N-type semiconductor layer.
6. The method according to any one of claims 3 to 5, wherein the active strip includes a third semiconductor layer located within a projection area of the first gap along the second direction, After forming the isolation structure, the method further includes:

   Etching the third semiconductor layer along the second direction to form a third sub-semiconductor layer; wherein the isolation structure and the third sub-semiconductor layer have a second gap in the projection area along the second direction, the second gap includes the first gap;

   The bit line structure is formed in the second gap.
7. The method of claim 6, wherein the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the U-shaped bottom surface of the first U-shaped isolation structure. ; The isolation structure is formed by the following steps:

   Form a first initial isolation structure on the surface of the active strip and the inner wall of the first trench;

   forming the second isolation structure at the bottom of the first trench having the first preliminary isolation structure;

   The first initial isolation structure is etched back to form the first U-shaped isolation structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure.
8. The method according to claim 7, wherein after forming the bit line structure, the method further comprises:

   The active strip in the projection area of the bit line structure along the second direction is doped to form a drain portion.
9. The method of claim 7, wherein after forming the bit line structure, the method further includes:

   The bit line structure and the active strip are heat treated to form metal silicide between the bit line structure and the active strip.
10. The method of claim 9, further comprising:

    Forming a third isolation structure covering the surface of the bit line structure and the surface of the second isolation structure;

    Wherein, the top surface of the third isolation structure does not exceed the top surface of the active strip.
11. The method of claim 10, wherein a fourth isolation structure is formed on the surface of the third isolation structure;

    Wherein, the top surface of the fourth isolation structure is flush with the top surface of the active strip.
12. The method of claim 11, wherein the active strip and the first trench are formed by:

    Form a semiconductor active layer on the surface of the first N-type semiconductor layer;

    A first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction. , the first sub-pattern exposes part of the semiconductor active layer;

    Through the first mask layer, the exposed portion of the semiconductor active layer of the first sub-pattern is removed to form active strips extending along the first direction and alternately arranged along the second direction. and the first trench.
13. The method according to claim 12, wherein the method further comprises:

    forming a second mask layer having a second pattern on the surface of the active strip and the fourth isolation structure; the second pattern comprises a plurality of second sub-patterns extending along the second direction and arranged along the first direction, and the second sub-patterns expose a portion of the active strip and a portion of the fourth isolation structure;

    Through the second mask layer, the active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched, or the active strips exposed by the second sub-pattern are etched. The source strip and all the fourth isolation structures form second trenches and active isolation layers alternately arranged along the first direction; wherein the size of the second trench along the third direction is less than or equal to the The initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etchings arranged alternately along the second direction. The fourth isolation structure behind;

    The active pillars are insulated from each other;

    A word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not exceed the top surface of the active pillar.
14. The method of claim 13, wherein the method further includes:

    Doping part of the active pillars located outside the projection area of the word line structure along the first direction to form a source portion;

    A capacitor structure connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence.
15. A semiconductor structure including:

    A substrate, the substrate includes drain portions and isolation structures extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions in a plane where the substrate is located ;

    A bit line structure is located between the isolation structure and the drain portion.
16. The semiconductor structure of claim 15, wherein the base includes a substrate, and a first isolation layer located on a surface of the substrate;

    The first isolation layer includes a semiconductor isolation layer and/or an insulating layer, and the semiconductor isolation layer and/or the insulating layer is used to isolate the bit line structure and the substrate.
17. The semiconductor structure of claim 16, wherein the semiconductor isolation layer at least includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer. ; The drain portion is located on the surface of the first N-type semiconductor layer.
18. The semiconductor structure according to claim 17, wherein the substrate is a P-type doped substrate, the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, the first The P-type semiconductor layer is located on the surface of the second N-type semiconductor layer.
19. The semiconductor structure according to claim 18, wherein the isolation structure is in a convex shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation located on the U-shaped bottom surface of the first U-shaped isolation structure. Structure; the top surface of the second isolation structure exceeds the top surface of the first U-shaped isolation structure;

    The first U-shaped isolation structure and the second isolation structure are both in contact with the bit line structure.
20. The semiconductor structure of claim 19, wherein the semiconductor structure further comprises:

    A third isolation structure is located on the surface of the bit line structure and the second isolation structure.
21. The semiconductor structure of claim 20, wherein the semiconductor structure further comprises:

    A metal silicide is located between the bit line structure and the drain portion.
22. The semiconductor structure according to claim 21, wherein the semiconductor structure further comprises: active pillars located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and located on the surface of the drain portion. The sidewalls of the active pillars and word line structures arranged along the first direction and extending along the second direction;

    Wherein, the top surface of the word line structure does not exceed the top surface of the active pillar.
23. The semiconductor structure according to claim 22, wherein the semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion;

    The source portion is located outside the projection area of the active pillar along the second direction;

    The capacitor structure is located on the top surface of the active pillar, and the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer.
24. The semiconductor structure of claim 23, wherein part of the bit line structure is located within a projection area of the active pillar along the third direction, or the bit line structure is located within the projection area of the active pillar along the third direction. Outside the projection area in three directions;

    The third direction intersects the plane of the base.

Images