CN117712147A - Semiconductor structure, forming method thereof and layout structure - Google Patents

Semiconductor structure, forming method thereof and layout structure Download PDF

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Publication number
CN117712147A
CN117712147A CN202211091001.2A CN202211091001A CN117712147A CN 117712147 A CN117712147 A CN 117712147A CN 202211091001 A CN202211091001 A CN 202211091001A CN 117712147 A CN117712147 A CN 117712147A
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transistor
layer
epitaxial layer
conductive
channel
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廖昱程
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211091001.2A priority Critical patent/CN117712147A/en
Priority to PCT/CN2022/123896 priority patent/WO2024050906A1/en
Publication of CN117712147A publication Critical patent/CN117712147A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The embodiment of the disclosure provides a semiconductor structure, a forming method thereof and a layout structure, wherein the semiconductor structure comprises: the transistor structure comprises a first transistor and a second transistor, and the channel structure of the first transistor and the channel structure of the second transistor extend along a third direction; the first direction and the second direction are any two directions in the plane of the substrate, and the third direction intersects with the plane of the substrate.

Description

Semiconductor structure, forming method thereof and layout structure
Technical Field
The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a method of forming the same, and a layout structure.
Background
Currently, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) plays an important role in the semiconductor industry, and it can be applied to the fields of digital logic circuits, static Random-Access memories (SRAMs), microprocessors, microcontrollers, and the like. As the integration level of CMOS in semiconductor structures is increased, the storage density and efficiency of CMOS are required to be improved, which causes serious problems such as gate leakage, junction leakage or well leakage.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a semiconductor structure, a forming method thereof, and a layout structure.
In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising: the transistor structure comprises a first transistor and a second transistor, and the channel structure of the first transistor and the channel structure of the second transistor extend along a third direction; the first direction and the second direction are any two directions in the plane of the substrate, and the third direction intersects with the plane of the substrate.
In some embodiments, the first transistor and the second transistor are different types of transistors.
In some embodiments, the first transistor and the second transistor are arranged in mirror symmetry.
In some embodiments, the gate structures of the first transistor and the second transistor include a gate dielectric layer and a gate conductive layer, and the first transistor and the second transistor share the gate conductive layer.
In some embodiments, the channel structures of the first transistor and the second transistor each have at least one protrusion and/or at least one recess;
At least one convex part in the channel structure of the first transistor and at least one convex part in the channel structure of the second transistor are in mirror symmetry or staggered arrangement; or,
at least one concave part in the channel structure of the first transistor and at least one concave part in the channel structure of the second transistor are in mirror symmetry or staggered arrangement.
In some embodiments, the semiconductor structure further comprises a conductive structure over the transistor structure, the conductive structure comprising a first conductive line, a second conductive line, and a third conductive line, the drain of the first transistor and the drain of the second transistor both being connected to the first conductive line, the source of the first transistor being connected to the second conductive line through a conductive plug, the source of the second transistor being connected to the third conductive line through a conductive plug.
In some embodiments, along the second direction, sources of the plurality of first transistors are commonly electrically connected to the second conductive line, and sources of the plurality of second transistors are commonly electrically connected to the third conductive line.
In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising:
Providing a substrate;
forming a transistor structure which is arranged in an array along a first direction and a second direction on the surface of the substrate, wherein the transistor structure comprises a first transistor and a second transistor, and a channel structure of the first transistor and a channel structure of the second transistor extend along a third direction; the first direction and the second direction are any two directions in the plane of the substrate, and the third direction intersects with the plane of the substrate.
In some embodiments, the transistor structure is formed by:
forming first and second source electrodes spaced apart from each other along the first direction on a surface of the substrate;
forming a first channel structure and a second channel structure on the surfaces of the first source electrode and the second source electrode respectively;
forming a first drain and a second drain on top of the first channel structure and the second channel structure, respectively;
a common gate structure is formed between the first channel structure and the second channel structure.
In some embodiments, the first channel structure and the second channel structure are formed by:
forming a first epitaxial layer and a second epitaxial layer on the surfaces of the first source electrode and the second source electrode respectively;
Forming a mask layer in gaps between the first source electrode and the second source electrode and between the first epitaxial layer and the second epitaxial layer;
forming a third epitaxial layer and a fourth epitaxial layer which cover part of the mask layer on the surfaces of the first epitaxial layer and the second epitaxial layer respectively;
and patterning the third epitaxial layer and the fourth epitaxial layer to correspondingly form the first channel structure and the second channel structure.
In some embodiments, the third epitaxial layer is formed to have a dimension greater than the dimension of the first epitaxial layer and the fourth epitaxial layer is formed to have a dimension greater than the dimension of the second epitaxial layer in the first direction.
In some embodiments, patterning the third epitaxial layer and the fourth epitaxial layer includes:
etching to remove part of the side walls of the third epitaxial layer and the fourth epitaxial layer so as to form at least one convex part and/or at least one concave part on the two opposite side wall surfaces between the third epitaxial layer and the fourth epitaxial layer;
the first epitaxial layer and the rest of the third epitaxial layer form the first channel structure, and the second epitaxial layer and the rest of the fourth epitaxial layer form the second channel structure.
In some embodiments, after patterning the third epitaxial layer and the fourth epitaxial layer, the method further comprises:
removing the mask layer;
forming an isolation layer between the remaining third epitaxial layer and the remaining fourth epitaxial layer;
and performing ion implantation on the tops of the third epitaxial layer and the fourth epitaxial layer to form the first drain electrode and the second drain electrode respectively.
In some embodiments, the first source, the first channel structure, and the first drain together comprise a first active region, and the second source, the second channel structure, and the second drain together comprise a second active region; the method further comprises the steps of:
removing the isolation layer, exposing the side wall surfaces of the first active region and the second active region, and forming a gate dielectric layer on the exposed side wall surfaces;
and forming a first insulating layer, a gate conducting layer and a second insulating layer between the first active region with the gate dielectric layer and the second active region with the gate dielectric layer in sequence from bottom to top.
In some embodiments, the method further comprises:
forming a first conductive line electrically connected to the first drain electrode and the second drain electrode;
And forming a second conductive wire, a third conductive wire and a plurality of conductive plugs, wherein the first source electrode is electrically connected with the second conductive wire through the conductive plugs, and the second source electrode is electrically connected with the third conductive wire through the conductive plugs.
In a third aspect, an embodiment of the present disclosure provides a layout structure, including:
the source electrode layer comprises a plurality of first source electrodes and a plurality of second source electrodes which are arrayed along a first direction and a second direction, the channel layer comprises a plurality of first channel structures and a plurality of second channel structures which are arrayed along the first direction and the second direction, the first channel structures and the second channel structures extend along a third direction, and the drain electrode layer comprises a plurality of first drain electrodes and a plurality of second drain electrodes which are arrayed along the first direction and the second direction;
the first source electrodes and the second source electrodes are alternately arranged at intervals in sequence along the first direction; a plurality of the first source electrodes are arranged at intervals along the second direction, and a plurality of the second source electrodes are arranged at intervals;
two first channel structures are electrically connected above each first source electrode, and two second channel structures are electrically connected above each second source electrode; the upper part of each first channel structure is electrically connected with one first drain electrode, and the upper part of each second channel structure is electrically connected with one second drain electrode; wherein the third direction intersects a plane in which the first direction and the second direction are located.
In some embodiments, the layout structure further comprises: a gate layer located on the same layer as the channel layer, the gate layer including at least a plurality of gate conductive layers, the gate conductive layers extending along the second direction; one column of the first channel structures and one column of the second channel structures adjacently arranged in the first direction share one of the gate conductive layers.
In some embodiments, the layout structure further comprises: a conductive layer over the drain layer, the conductive layer including first, second, and third conductive lines disposed at intervals;
two adjacent first drains and second drains are electrically connected to the same first conductive line along the first direction;
along the second direction, two adjacent first sources are electrically connected with the same second conductive wire through conductive plugs, and two adjacent second sources are electrically connected with the same third conductive wire through conductive plugs.
The semiconductor structure, the forming method thereof and the layout structure provided by the embodiment of the disclosure, because the channel structure of the first transistor and the channel structure of the second transistor in the transistor structure extend along the third direction, the channel structure in the embodiment of the disclosure is vertical. The vertical channel structure not only can enable the transistor structure to have higher arrangement density, but also can reduce the size of the transistor structure, thereby improving the integration level of the semiconductor structure.
Drawings
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
Fig. 1a to 1c are schematic structural diagrams of a semiconductor structure according to an embodiment of the disclosure;
FIGS. 1d and 1e are schematic diagrams of structures providing another channel structure according to embodiments of the present disclosure;
fig. 1f is an equivalent circuit schematic diagram of the semiconductor structure corresponding to fig. 1b and 1c provided in an embodiment of the present disclosure;
FIGS. 2a and 2b are schematic diagrams illustrating another semiconductor structure according to embodiments of the present disclosure;
fig. 2c is an equivalent circuit schematic diagram of the semiconductor structure corresponding to fig. 2a and 2b provided in an embodiment of the disclosure;
fig. 3 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;
fig. 4a to 4h are schematic structural diagrams during the formation of a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Before describing the embodiments of the present disclosure, three directions describing the three-dimensional structure that may be used in the following embodiments are defined, and may include X-axis, Y-axis, and Z-axis directions, for example, in a cartesian coordinate system. The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction of intersection (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the third direction, ignoring the flatness of the top and bottom surfaces. In the direction of the top surface and the bottom surface (i.e., the plane in which the base is located) of the substrate, two directions intersecting each other (e.g., perpendicular to each other) are defined as a first direction and a second direction, for example, the first direction may be defined as an arrangement direction of a first transistor and a second transistor in a transistor structure, and the plane direction of the substrate may be determined based on the first direction and the second direction. In the embodiment of the disclosure, the first direction, the second direction and the third direction may be perpendicular to each other, and in other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiment of the disclosure, the first direction is defined as an X-axis direction, the second direction is defined as a Y-axis direction, and the third direction is defined as a Z-axis direction.
An embodiment of the present disclosure provides a semiconductor structure, and fig. 1a to 1c are schematic structural diagrams of the semiconductor structure provided in the embodiment of the present disclosure, where fig. 1b is a layout structure of one transistor structure in the semiconductor structure, fig. 1c is a cross-sectional view along a-a' in fig. 1b, and as shown in fig. 1a to 1c, the semiconductor structure 100 includes: a substrate 10, and a transistor structure 200 arranged on the surface of the substrate 10 in an array along the X-axis direction and the Y-axis direction, the transistor structure 200 including a first transistor 14 and a second transistor 15; the channel structures of the first transistor 14 and the second transistor 15 each extend in the Z-axis direction.
In an embodiment of the present disclosure, the transistor structure 200 may be a Complementary Metal Oxide Semiconductor (CMOS).
In the disclosed embodiment, the substrate 10 may be a Silicon substrate, a Silicon-On-Insulator (SOI) substrate, and the substrate 10 may also include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.
In some embodiments, shallow trench isolation (Shallow Trench Isolation, STI) structures or silicon local oxidation isolation (Local Oxidation of Silicon, LOCOS) structures may also be included in the substrate 10. A shallow trench isolation structure or a silicon local oxidation isolation structure may isolate several active regions in the substrate 10.
In the embodiment of the disclosure, the types of the first transistor 14 and the second transistor 15 are opposite, for example, the first transistor 14 may be an N-type Metal-Oxide-Semiconductor (NMOS), and the second transistor 15 may be a P-type Metal-Oxide-Semiconductor (PMOS); or vice versa.
In the embodiments of the present disclosure, since the channel structure of the first transistor and the channel structure of the second transistor among the transistor structures extend in the third direction, the channel structures in the embodiments of the present disclosure are vertical. The vertical channel structure not only can enable the transistor structure to have higher arrangement density, but also can reduce the size of the transistor structure and improve the integration level of the semiconductor structure.
With continued reference to fig. 1b and 1c, in the embodiment of the disclosure, the first transistor 14 and the second transistor 15 are disposed in mirror symmetry; wherein the first transistor 14 includes a first source 141, a first drain 142, and a first channel structure 143, and the second transistor 15 includes a second source 151, a second drain 152, and a second channel structure 153; the first channel structure 143 and the second channel structure 153 each extend in the Z-axis direction; the first source electrode 141 and the first drain electrode 142 are respectively located at both ends of the first channel structure 143 along the Z-axis direction, and the second source electrode 151 and the second drain electrode 152 are respectively located at both ends of the second channel structure 153 along the Z-axis direction.
In the embodiment of the present disclosure, the first channel structure 143 and the second channel structure 153 each have one convex portion and two concave portions, or the first channel structure 143 and the second channel structure 153 each have one concave portion (or two convex portions). For example, with continued reference to fig. 1c, the first channel structure 143 and the second channel structure 153 each have one convex portion and two concave portions.
In other embodiments, the first channel structure 143 may have a plurality of protrusions and/or a plurality of recesses, and the second channel structure 153 may also have a plurality of protrusions and/or a plurality of recesses. Fig. 1d and 1e are schematic structural views of another channel structure according to an embodiment of the present disclosure, and as shown in fig. 1d, each of the first channel structure 143 and the second channel structure 153 has four concave portions and three convex portions. As shown in fig. 1e, the first channel structure 143 has three protrusions and four recesses, and the second channel structure 153 has three recesses and four protrusions.
The number of the convex portions (or concave portions) in the first channel structure 143 and the second channel structure 153 may be the same or different; the protrusions (or recesses) in the first and second channel structures 143 and 153 may be disposed in mirror symmetry (as shown in fig. 1c and 1 d), and the protrusions (or recesses) in the first and second channel structures 143 and 153 may be disposed alternately (as shown in fig. 1 e).
In the embodiment of the present disclosure, the channel structure of the first transistor 14 is configured to have at least one protrusion and/or at least one recess, and the channel structure of the second transistor 15 is configured to have at least one protrusion and/or at least one recess, so that the transistor structure in the embodiment of the present disclosure has a larger channel structure length, thereby effectively suppressing the short channel effect of the transistor structure and improving the performance of the transistor structure.
In some embodiments, referring to fig. 1c, the first transistor 14 and the second transistor 15 each include a gate structure; the gate structure of the first transistor 14 includes a gate dielectric layer 171 and a gate conductive layer 18 on a surface of the gate dielectric layer 171, and the gate structure of the second transistor 15 includes a gate dielectric layer 172 and a gate conductive layer 18 on a surface of the gate dielectric layer 172, and in the embodiment of the present disclosure, the first transistor 14 and the second transistor 15 share the gate conductive layer 18. The materials of the gate dielectric layer 171 and the gate dielectric layer 172 may be a High dielectric material (High K) or other suitable materials; the material of the gate conductive layer 18 may be any material having good conductivity, for example, any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).
In some embodiments, referring to fig. 1a and 1c, the semiconductor structure 100 further comprises a first isolation layer 16 between the substrate 10 and the transistor structure 200. The first isolation layer 16 is used to isolate the transistor structure 200 from the substrate 10 to prevent leakage.
In some embodiments, referring to fig. 1c, the transistor structure 200 further comprises: the first insulating layer 11 located in the X-axis direction projection area of the first source 141 of the first transistor 14 and the second source 151 of the second transistor 15, and the second insulating layer 12 located in the X-axis direction projection area of the first drain 142 of the first transistor 14 and the second drain 152 of the second transistor 15. The first insulating layer 11 serves to prevent the first transistor 14 and the second transistor 15 from being isolated from the substrate when the first isolation layer 16 is broken down, thereby further preventing the first transistor 14 and the second transistor 15 from leaking. The second insulating layer 12 is used to isolate the first transistor 14 and the second transistor 15 from metal lines formed later, and prevent leakage of the first transistor 14 and the second transistor 15.
In some embodiments, referring still to fig. 1c, the semiconductor structure further comprises: a second isolation layer 13 between two adjacent transistor structures. The second isolation layer 13 is used to isolate adjacent transistor structures and prevent leakage of the transistor structures.
In the embodiment of the present disclosure, the materials of the first isolation layer 16, the second isolation layer 13, the first insulation layer 11 and the second insulation layer 12 may be any suitable insulation material, for example, the first isolation layer 16 and the second isolation layer 13 may be silicon oxide, and the first insulation layer 11 and the second insulation layer 12 may be Low dielectric constant (Low K) materials.
In some embodiments, referring to fig. 1b and 1c, the semiconductor structure further comprises: a conductive structure over the transistor structure 200, the conductive structure including a first conductive line 19, a second conductive line 211, and a third conductive line 212; the first drain 142 of the first transistor 14 and the second drain 152 of the second transistor 15 in the transistor structure 200 are both connected to the first conductive line 19; the first conductive line 19 is used for transmitting the output signal of the transistor structure 200.
In some embodiments, referring to fig. 1b and 1c, the semiconductor structure further comprises: a conductive plug 20; wherein, the first source 141 of the first transistor 14 is connected with the second conductive line 211 through the conductive plug 20, and the second source 151 of the second transistor 15 is connected with the third conductive line 212 through the conductive plug 20; the second conductive line 211 is used for transmitting a ground signal, and the third conductive line 212 is used for transmitting a power signal.
Fig. 1f is an equivalent circuit schematic diagram of the semiconductor structure corresponding to fig. 1b and 1c, where, as shown in fig. 1f, the circuit of the semiconductor structure includes a CMOS circuit, the CMOS circuit includes a PMOS transistor and an NMOS transistor, gates of the PMOS transistor and the NMOS transistor are connected as input ends, drains of the PMOS transistor and the NMOS transistor are connected as output ends, a source of the PMOS transistor is connected with a power signal, and a source of the NMOS transistor is connected with a ground signal.
The semiconductor structure provided by the embodiment of the disclosure comprises transistor structures arranged on the surface of the substrate in an array manner along a first direction and a second direction, and the channel structure of a first transistor and the channel structure of a second transistor in the transistor structures extend along a third direction, that is, the channel structures in the embodiment of the disclosure are vertical. The vertical channel structure can enable the transistor structure to have higher arrangement density, so that the size of the transistor structure can be reduced, and the integration level of the semiconductor structure can be improved.
Fig. 2a and 2b are schematic structural diagrams of another semiconductor structure according to an embodiment of the present disclosure, where fig. 2a is a layout structure of a transistor structure in the semiconductor structure, fig. 2b is a cross-sectional view along b-b' in fig. 2a, and fig. 2a and 2b, and the semiconductor structure 100 includes: a substrate 10, and 4 transistor structures 200 arranged along the Y-axis direction on the surface of the substrate 10, the transistor structures 200 including a first transistor 14 and a second transistor 15; the channel structures of the first transistor 14 and the second transistor 15 each extend in the Z-axis direction.
In some embodiments, the first transistor 14 may be an NMOS transistor and the second transistor 15 may be a PMOS transistor.
In some embodiments, referring to fig. 2a and 2b, the first transistor 14 and the second transistor 15 are mirror-disposed; wherein the first transistor 14 includes a first source 141, a first drain 142, and a first channel structure 143, and the second transistor 15 includes a second source 151, a second drain 152, and a second channel structure 153; the first channel structure 143 and the second channel structure 153 each extend in the Z-axis direction; the first source electrode 141 and the first drain electrode 142 are respectively located at both ends of the first channel structure 143 along the Z-axis direction, and the second source electrode 151 and the second drain electrode 152 are respectively located at both ends of the second channel structure 153 along the Z-axis direction.
In the embodiment of the present disclosure, each of the first channel structure 143 and the second channel structure 153 has one protrusion; in other embodiments, the first channel structure 143 may have a plurality of protrusions and/or a plurality of recesses, and the second channel structure 153 may also have a plurality of protrusions and/or a plurality of recesses (as shown in fig. 1d and 1 e).
The number of the convex portions (or concave portions) in the first channel structure 143 and the second channel structure 153 may be the same or different; the protrusions (or recesses) in the first channel structure 143 and the second channel structure 153 may be arranged in a mirror symmetry manner (as shown in fig. 1c and 1 d), or may be arranged in a staggered manner (as shown in fig. 1 e).
In the embodiment of the present disclosure, the channel structure of the first transistor 14 is configured to have at least one protrusion and/or at least one recess, and the channel structure of the second transistor 15 is configured to have at least one protrusion and/or at least one recess, so that the transistor structure in the embodiment of the present disclosure has a larger channel structure length, thereby effectively suppressing the short channel effect of the transistor structure and improving the performance of the transistor structure.
In the embodiment of the present disclosure, referring to fig. 2a and 2b, the gate structure of the first transistor 14 includes a gate dielectric layer 171 and a gate conductive layer 18 on the surface of the gate dielectric layer 171, and the gate structure of the second transistor 15 includes a gate dielectric layer 172 and a gate conductive layer 18 on the surface of the gate dielectric layer 172. The first transistor 14 and the second transistor 15 share a gate conductive layer 18.
In some embodiments, referring to fig. 2a and 2b, the semiconductor structure 100 further includes a first insulating layer 11 located in a projection area of the first source 141 of the first transistor 14 and the second source 151 of the second transistor 15 along the X-axis direction, and a second insulating layer 12 located in a projection area of the first drain 142 of the first transistor 14 and the second drain 152 of the second transistor 15 along the X-axis direction.
In some embodiments, referring to fig. 2a and 2b, the semiconductor structure 100 further comprises a first isolation layer 16 between the substrate 10 and the transistor structure 200.
In some embodiments, referring to fig. 2a and 2b, the semiconductor structure 100 further comprises a second isolation layer 13 between two adjacent transistor structures 200.
In some embodiments, referring to fig. 2a and 2b, the semiconductor structure 100 further includes four first conductive lines 19; the first drain 142 of the first transistor 14 and the second drain 152 of the second transistor 15 in each transistor structure are connected to the first conductive line 19; the first conductive line 19 is used for transmitting the output signal of the transistor structure 200.
In some embodiments, referring to fig. 2a and 2b, the semiconductor structure 100 further includes four conductive plugs 20, a second conductive line 211, and a third conductive line 212. The first source electrodes 141 of the first transistors 14 located in the same column in the Y-axis direction are connected to the second conductive lines 211 through the conductive plugs 20, and the first source electrodes 151 of the second transistors 15 located in the same column in the Y-axis direction are connected to the third conductive lines 212 through the conductive plugs 20, wherein the second conductive lines 211 are used for transmitting ground signals, and the third conductive lines 212 are used for transmitting power signals.
In some embodiments, please continue to refer to fig. 2a and 2b, each two adjacent first transistors 14 share a first source 141 along the Y-axis direction, or each two adjacent second transistors 15 share a second source 151 along the Y-axis direction.
Fig. 2c is an equivalent circuit schematic diagram of the semiconductor structure corresponding to fig. 2a and 2b, where, as shown in fig. 2c, the circuit of the semiconductor structure includes four CMOS circuits, each CMOS circuit includes a PMOS transistor and an NMOS transistor, gates of the PMOS transistor and the NMOS transistor in each CMOS circuit are connected, gates of the four CMOS circuits are connected as input ends, drains of the PMOS transistor and the NMOS transistor in each CMOS circuit are connected as output ends, and sources of the PMOS transistor in each CMOS circuit are connected with a power signal, that is, sources of the four PMOS transistors are connected with the power signal; the sources of the NMOS transistors in each CMOS circuit are connected with a ground signal, namely, the sources of the four NMOS transistors are connected with the ground signal.
The semiconductor structure provided in the embodiments of the present disclosure is similar to the semiconductor structure in the above embodiments, and for technical features that are not fully disclosed in the embodiments of the present disclosure, reference is made to the above embodiments for understanding, and details are not repeated here.
The semiconductor structure provided by the embodiment of the disclosure comprises the transistor structures arranged on the surface of the substrate in the array along the first direction and the second direction, and the channel structure of the first transistor and the channel structure of the second transistor in the transistor structures extend along the third direction, that is, the channel structure and the transistor structures in the embodiment of the disclosure are vertical, so that the transistor structures have higher arrangement density, the size of the transistor structures can be reduced, and the integration level of the semiconductor structure is improved.
The embodiment of the disclosure provides a layout structure, please continue to refer to fig. 1b and fig. 2a, wherein the layout structure comprises a source electrode layer, a channel layer and a drain electrode layer which are sequentially arranged from bottom to top; the source electrode layer comprises a plurality of first source electrodes and a plurality of second source electrodes which are arranged in an array along an X-axis direction and a Y-axis direction, the channel layer comprises a plurality of first channel structures and a plurality of second channel structures which are arranged in an array along the X-axis direction and the Y-axis direction, the first channel structures and the second channel structures extend along a Z-axis direction, and the drain electrode layer comprises a plurality of first drain electrodes and a plurality of second drain electrodes which are arranged in an array along the X-axis direction and the Y-axis direction; the first source electrodes and the second source electrodes are alternately arranged at intervals in sequence along the X-axis direction; a plurality of first source electrodes arranged at intervals along the Y-axis direction, and a plurality of second source electrodes arranged at intervals; two first channel structures are electrically connected above each first source electrode, and two second channel structures are electrically connected above each second source electrode; the upper side of each first channel structure is electrically connected with a first drain electrode, and the upper side of each second channel structure is electrically connected with a second drain electrode.
In the disclosed embodiment, the first source, the first channel structure, and the first drain constitute the first transistor 14; the second source, the second channel structure and the second drain constitute a second transistor 15.
In the embodiment of the disclosure, since the first transistor 14 and the second transistor 15 are both vertical, the transistor structure can have a higher arrangement density, which not only reduces the size of the transistor structure, but also improves the integration level of the semiconductor structure.
In the embodiment of the disclosure, the types of the first transistor 14 and the second transistor 15 are opposite, for example, the first transistor 14 is an NMOS transistor and the second transistor 15 is a PMOS transistor.
In some embodiments, please continue to refer to fig. 1b and fig. 2a, the layout structure further includes: a gate layer located on the same layer as the channel layer, the gate layer including a plurality of gate dielectric layers located on a row of first channel structure surfaces in an X-axis direction, a plurality of gate dielectric layers located on a row of second channel structure surfaces in the X-axis direction, and a plurality of gate conductive layers 18 located between two adjacent gate dielectric layers in the same transistor structure, the gate dielectric layers and the gate conductive layers 18 extending in a Y-axis direction; a column of first channel structures and a column of second channel structures arranged adjacently in the X-axis direction share one gate conductive layer 18 (i.e., the first transistor 14 and the second transistor 15 in the transistor structure share the gate conductive layer 18).
In some embodiments, the layout structure further comprises: a conductive layer over the drain layer, the conductive layer including first, second and third conductive lines 19, 211 and 212 disposed at intervals; two adjacent first and second drains are electrically connected to the same first conductive line 19 along the X-axis direction; in the Y-axis direction, two adjacent first sources are electrically connected to the same second conductive line 211 through conductive plugs, and two adjacent second sources are electrically connected to the same third conductive line 212 through conductive plugs. The first conductive line 19 is used for transmitting the output signal of the transistor structure.
In some embodiments, with continued reference to fig. 2a, every adjacent two of the transistors 14, which are sequentially aligned along the Y-axis, share a source. Each adjacent two of the second transistors 15 sequentially arranged in the Y-axis direction share a source.
In some embodiments, please continue to refer to fig. 1b and fig. 2a, the layout structure further includes: conductive plugs 20. The first source of the first transistor 14 located in the same column in the Y-axis direction is connected to the second conductive line 211 through the conductive plug 20; the second sources of the second transistors 15 located in the same column in the Y-axis direction are connected to the third conductive line 212 through the conductive plugs 20. The second conductive line 211 is used for transmitting a power signal, and the third conductive line 212 is used for transmitting a ground signal.
It should be noted that the source layer and the drain layer in the embodiments of the present disclosure do not completely overlap in the Z-axis direction, that is, the drain layer needs to expose a portion of the source layer for forming the conductive plug 20 extending along the Z-axis direction, so as to achieve the extraction of the source.
In some embodiments, the layout structure further includes an active region layout layer, and a first isolation layer (not shown in fig. 1b and 2 a) located between the active region layout layer and the source layer; the first isolation layer is used for isolating the active region layout layer and the source electrode layer and preventing the electric leakage of the transistor structure.
In some embodiments, the layout structure further comprises: a second isolation layer (not shown in fig. 1b and 2 a) between two adjacent transistor structures. The second isolation layer is used for isolating the adjacent transistor structure and preventing the transistor structure from electric leakage.
The transistor structure in the layout structure provided by the embodiment of the present disclosure is similar to the transistor structure in the above embodiment, and for technical features that are not disclosed in detail in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and a detailed description is omitted here.
The layout structure provided by the embodiment of the disclosure comprises a source electrode layer, a channel layer and a drain electrode layer which are sequentially arranged from bottom to top; the source layer comprises a plurality of first source electrodes and a plurality of second source electrodes which are arranged in an array mode, the channel layer comprises a plurality of first channel structures and a plurality of second channel structures which are arranged in an array mode, and the drain layer comprises a plurality of first drain electrodes and a plurality of second drain electrodes which are arranged in an array mode. Because the first channel structure and the plurality of second channel structures extend along the third direction, namely the first channel structure and the second channel structures are vertical, not only can the size of the transistor structure be reduced, but also the integration level of the semiconductor structure can be improved. In addition, since the transistor structures located in the same column along the second direction share the gate structure and every two adjacent transistor structures along the second direction share the source, the space in the semiconductor structure can be effectively utilized, and the miniaturization of the semiconductor structure is further realized.
In addition, an embodiment of the present disclosure further provides a method for forming a semiconductor structure, and fig. 3 is a schematic flow chart of the method for forming a semiconductor structure according to the embodiment of the present disclosure, as shown in fig. 3, the method for forming a semiconductor structure includes the following steps:
step S301, providing a substrate.
In step S302, transistor structures arranged in an array along a first direction and a second direction are formed on a surface of a substrate, where the transistor structures include a first transistor and a second transistor, and channel structures of the first transistor and the second transistor extend along a third direction.
In an embodiment of the present disclosure, the transistor structure 200 may be a Complementary Metal Oxide Semiconductor (CMOS); the first transistor and the second transistor are of opposite types, for example, the first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor.
Fig. 4a to 4h are schematic structural views of a semiconductor structure in a forming process according to an embodiment of the present disclosure, and the forming process of the semiconductor structure according to the embodiment of the present disclosure is described in detail below with reference to fig. 4a to 4 h.
In some embodiments, the transistor structure may be formed by: forming first source electrodes and second source electrodes which are arranged at intervals along a first direction on the surface of a substrate; forming a first channel structure and a second channel structure on the surfaces of the first source electrode and the second source electrode respectively; forming a first drain and a second drain on top of the first channel structure and the second channel structure, respectively; a common gate structure is formed between the first channel structure and the second channel structure.
In an embodiment of the disclosure, the first source, the first channel structure, and the first drain constitute a first transistor; the second source electrode, the second channel structure and the second drain electrode form a second transistor; the following description will take the first transistor formed as an NMOS transistor and the second transistor formed as a PMOS transistor as an example. In other embodiments, the first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor.
As shown in fig. 4a, a first isolation layer 16 is formed by depositing a first isolation material on the surface of the substrate 10; the first isolation layer 16 is used to isolate the transistor structure 200 from the substrate 10 to prevent leakage. The first isolation material may be any insulating material, such as silicon oxide or silicon oxynitride.
Before the first isolation layer is formed on the surface of the substrate, the surface of the substrate needs to be cleaned, and when the cleaning process is performed, the substrate can be provided with a clean surface by the following steps: firstly, forming a sacrificial oxide layer on the surface of a substrate, and capturing defects on the surface of the substrate through the sacrificial oxide layer; and then, etching the sacrificial oxide layer by using hydrofluoric acid solution.
With continued reference to fig. 4a, first source electrodes 141 and second source electrodes 151 are formed on the surface of the first isolation layer 16 at intervals along the X-axis direction. For example, an epitaxial semiconductor layer (not shown in fig. 4 a) may be epitaxially formed on the surface of the first isolation layer 16, an N-well may be formed by doping a left half portion of the epitaxial semiconductor layer, a P-well may be formed by doping a right half portion of the epitaxial semiconductor layer, a photoresist layer (not shown in fig. 4 a) may be formed on the surfaces of the N-well and the P-well, the photoresist layer exposing a portion of the N-well and a portion of the P-well, and the exposed portion of the N-well and portion of the P-well may be removed by photoresist layer etching to form the first source electrode 141 and the second source electrode 151.
In some embodiments, the first channel structure and the second channel structure may be formed by: forming a first epitaxial layer and a second epitaxial layer on the surfaces of the first source electrode and the second source electrode respectively; forming a mask layer in a gap between the first source electrode and the second source electrode and between the first epitaxial layer and the second epitaxial layer; forming a third epitaxial layer and a fourth epitaxial layer which cover part of the mask layer on the surfaces of the first epitaxial layer and the second epitaxial layer respectively; and patterning the third epitaxial layer and the fourth epitaxial layer to correspondingly form a first channel structure and a second channel structure.
In the embodiment of the present disclosure, as shown in fig. 4b, the first epitaxial layer 143a may be formed by epitaxially growing P-type silicon on the surface of the first source electrode 141, and the second epitaxial layer 153a may be formed by epitaxially growing N-type silicon on the surface of the second source electrode 151.
In some embodiments, the first epitaxial layer 143a and the second epitaxial layer 153a may be formed by:
mode one: first, as shown in fig. 4b, a first epitaxial layer 143a and a second epitaxial layer 153a are formed on the surfaces of the first source electrode 141 and the second source electrode 151, respectively; forming a barrier layer 24 covering surfaces of the first source electrode 141, the second source electrode 151, the first epitaxial layer 143a, the second epitaxial layer 153a, and the first isolation layer 16, wherein the barrier layer 24 exposes a first surface a of the first source electrode 141 in the X-axis direction, a second surface b of the first epitaxial layer 143a in the X-axis direction, a third surface c of the second source electrode 151 in the X-axis direction, and a fourth surface d of the second epitaxial layer 153a in the X-axis direction; next, as shown in fig. 4c, the first, second, third, and fourth surfaces a, b, c, and d exposed through the barrier layer 24 are etched laterally in the X-axis direction to etch the first, second, and third source electrodes 141, 143a, 151, and 153a such that the first, second, and third source electrodes 141, 143a, 151, and 153a each have a first preset size L1 in the X-axis direction, forming the first and second epitaxial layers 143a and 153a having the first preset size L1.
In the disclosed embodiment, the material of the barrier layer 24 may be silicon nitride or silicon carbonitride.
In embodiments of the present disclosure, barrier layer 24 may be formed by any one of the following deposition processes: a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a spin-on process, a coating process, a thin film process, or the like.
Mode two: a first source electrode 141 having a first preset size L1 and a second source electrode 151 having a first preset size L1 are directly formed on the surface of the first isolation layer 16, and a first epitaxial layer 143a having the first preset size L1 and a second epitaxial layer 153a having the first preset size L1 are directly epitaxially formed on the first source electrode 141 and the second source electrode 151 having the first preset size L1, respectively, in the X-axis direction.
It should be noted that, after forming the first epitaxial layer 143a having the first preset dimension L1 and the second epitaxial layer 153a having the first preset dimension L1 in the above manner, the method for forming a semiconductor structure further includes: the barrier layer 24 is removed.
As shown in fig. 4d, the mask layer 25 is formed in the gaps between the first source electrode 141 and the second source electrode 151, and between the first epitaxial layer 143a having the first preset size L1 and the second epitaxial layer 153a having the first preset size L1. The material of the mask layer 25 may be spin-on hard mask or silicon oxide.
With continued reference to fig. 4d, a third epitaxial layer 143b and a fourth epitaxial layer 153b are formed on the surfaces of the first epitaxial layer 143a having the first preset dimension L1 and the second epitaxial layer 153a having the first preset dimension L1, respectively, to cover a portion of the mask layer 25.
In the embodiment of the present disclosure, the third epitaxial layer 143b may be formed by epitaxially growing P-type silicon on the surface of the first epitaxial layer 143a, and the fourth epitaxial layer 153b may be formed by epitaxially growing N-type silicon on the surface of the second epitaxial layer 153 a.
In the embodiment of the disclosure, the third epitaxial layer 143b and the fourth epitaxial layer 153b each have a second preset dimension L2 in the X-axis direction; the second preset dimension L2 is greater than the first preset dimension L1.
Next, the third epitaxial layer 143b and the fourth epitaxial layer 153b are patterned to form a first channel structure and a second channel structure.
In some embodiments, after forming the third epitaxial layer and the fourth epitaxial layer, patterning the third epitaxial layer and the fourth epitaxial layer includes the steps of: etching to remove part of the side walls of the third epitaxial layer and the fourth epitaxial layer so as to form at least one convex part and/or at least one concave part on the surfaces of the two opposite side walls between the third epitaxial layer and the fourth epitaxial layer; the first epitaxial layer and the rest of the third epitaxial layer form a first channel structure, and the second epitaxial layer and the rest of the fourth epitaxial layer form a second channel structure.
In the embodiment of the present disclosure, one convex portion (or two concave portions) is formed on two opposite sidewall surfaces between the third epitaxial layer 143b and the fourth epitaxial layer 153 b; in other embodiments, a plurality of convex portions (or a plurality of concave portions) may also be formed on opposite side wall surfaces between the third epitaxial layer 143b and the fourth epitaxial layer 153 b.
As shown in fig. 4E, a photoresist layer 26 having a predetermined pattern E is formed on the surfaces of the mask layer 25, the third epitaxial layer 143b, and the fourth epitaxial layer 153 b; the preset pattern E exposes a portion of the sidewall of the third epitaxial layer 143b and a portion of the sidewall of the fourth epitaxial layer 153 b.
As shown in fig. 4f, a portion of the exposed sidewall of the third epitaxial layer 143b and a portion of the exposed sidewall of the fourth epitaxial layer 153b are etched away by the photoresist layer 26, and a protrusion (or two recesses) is formed on the opposite sidewall surfaces between the third epitaxial layer 143b and the fourth epitaxial layer 153 b; a remaining third epitaxial layer 143c and a remaining fourth epitaxial layer 153c are formed. Wherein the first epitaxial layer 143a and the remaining third epitaxial layer 143c constitute a first channel structure 143, and the second epitaxial layer 153a and the remaining fourth epitaxial layer 153c constitute a second channel structure 153.
In the embodiment of the present disclosure, the first channel structure 143 and the second channel structure 153 are both in a convex shape. The convex channel structure can enable the transistor structure to have a larger channel structure length L (as shown in fig. 4 g), so that the short channel effect of the transistor structure can be effectively restrained, and the performance of the transistor structure is improved.
In some embodiments, as shown in fig. 4f and 4g, after forming the first channel structure 143 and the second channel structure 153, the method of forming a semiconductor structure further includes: the mask layer 25 and the photoresist layer 26 are sequentially removed. For example, the mask layer 25 and the photoresist layer 26 may be sequentially removed by a wet etching process (e.g., strong acid etching using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or a dry etching process (e.g., a plasma etching process, a reactive ion etching process, or an ion milling process).
In the embodiment of the present disclosure, as shown in fig. 4f and 4g, after removing the mask layer 25 and the photoresist layer 26, the method for forming a semiconductor structure further includes: a second isolation material, which may be silicon nitride or any suitable material, is filled between the remaining third epitaxial layer and the remaining fourth epitaxial layer to form an isolation layer (not shown).
In the embodiment of the disclosure, please continue to refer to fig. 4g, P-type ion implantation is performed on top of the third epitaxial layer 143c to form the first drain 142; an N-type ion implantation is performed on top of the fourth epitaxial layer 153c to form the second drain electrode 152. The N-type ion may be VA-group ion such as phosphorus, arsenic, antimony, etc., and the P-type ion may be IIIA-group ion such as boron, indium, etc.
In the embodiment of the disclosure, please continue to refer to fig. 4g, the first source electrode 141, the first channel structure 143, and the first drain electrode 142 together form a first active region; the second source 151, the second channel structure 153, and the second drain 152 together constitute a second active region.
In some embodiments, the method of forming a semiconductor structure further comprises: removing the isolation layer, exposing the side wall surfaces of the first active region and the second active region, and forming a gate dielectric layer on the exposed side wall surfaces; a first insulating layer, a gate conductive layer and a second insulating layer are sequentially formed from bottom to top between a first active region having a gate dielectric layer and a second active region having a gate dielectric layer.
With continued reference to fig. 4g and 4h, the isolation layer is removed, the sidewall surface g of the first active region and the sidewall surface h of the second active region are exposed, and a gate dielectric material is deposited on the sidewall surface g of the first active region and the sidewall surface h of the second active region, thereby forming a gate dielectric layer 171 and a gate dielectric layer 172, respectively. Sequentially depositing a first insulating material and a gate conductive material between the gate dielectric layer 171 and the gate dielectric layer 172 to form a first insulating layer 11 and an initial gate conductive layer; wherein a top surface of the initial gate conductive layer is flush with a top surface of the first active region (or the second active region); the first insulating layer 11 is located in a projection region of the first source electrode 141 and the second source electrode 151 in the X-axis direction.
In the embodiment of the present disclosure, the first insulating layer 11 is used to prevent the first active region and the second active region from being isolated from the substrate when the first isolation layer 16 is broken down, thereby further preventing the first active region and the second active region from leaking.
In the embodiment of the present disclosure, the gate dielectric layer 171, the gate dielectric layer 172 and the initial gate conductive layer may be formed by any one of the following deposition processes: chemical vapor deposition processes, physical vapor deposition processes, atomic layer deposition processes, spin-on processes, coating processes, or thin film processes, and the like.
In embodiments of the present disclosure, the gate dielectric material may be silicon oxide or other suitable material; the gate conductive material may be any material with good conductivity, for example, any one of titanium, titanium nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper. The first insulating material may be a Low K material.
In an embodiment of the present disclosure, after forming the initial gate conductive layer, the method for forming a semiconductor structure further includes: etching back the initial gate conductive layer to expose sidewalls of the first drain electrode 142 and sidewalls of the second drain electrode 152 (not shown), and forming a gate conductive layer 18 from the remaining initial gate conductive layer; the gate dielectric layer 171 and the gate conductive layer 18 constitute a gate structure of the first transistor 14, and the gate dielectric layer 172 and the gate conductive layer 18 constitute a gate structure of the second transistor 15.
In some embodiments, after forming the gate structure, the method of forming the semiconductor structure further comprises: a second insulating material is deposited in the gap between the first drain electrode 142 and the second drain electrode 152, forming a second insulating layer 12. The second insulating material may be a Low K material.
In some embodiments, the method of forming a semiconductor structure further comprises: a first conductive line 19 is formed, and the first conductive line 19 is electrically connected to the first drain electrode 142 and the second drain electrode 152. A second conductive line (not shown in fig. 4 h), a third conductive line (not shown in fig. 4 h), and a plurality of conductive plugs (not shown in fig. 4 h) are formed, the first source electrode 141 is electrically connected to the second conductive line through the conductive plugs, and the second source electrode 151 is electrically connected to the third conductive line through the conductive plugs.
In the embodiment of the present disclosure, the second insulating layer 12 is used to isolate the first active region and the second active region from the first conductive line formed later, so as to prevent the leakage of the first transistor and the second transistor.
In the embodiment of the present disclosure, after forming the first conductive line 19, the second conductive line, and the third conductive line, the method for forming a semiconductor structure further includes: annealing the semiconductor structure; in this manner, defects of the formed semiconductor structure may be reduced.
In some embodiments, referring to fig. 4g and 4h, the method for forming a semiconductor structure further includes: a second isolation layer 13 is formed between two adjacent transistor structures.
In the embodiment of the present disclosure, the second isolation layer 13 may be formed by any one of the following deposition processes: an epitaxial process, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin-on process, a coating process, a thin film process, or the like. The second isolation layer 13 is used to isolate adjacent transistor structures and prevent leakage of the transistor structures.
The semiconductor structure formed by the method provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above embodiments, and for technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and a detailed description is omitted here.
The method for forming the semiconductor structure provided by the embodiment of the present disclosure forms transistor structures arranged in an array along a first direction and a second direction on a surface of a substrate, and because the transistor structures include channel structures extending along a third direction, the channel structures of the transistor structures formed by the method for forming the semiconductor structure provided by the embodiment of the present disclosure are vertical. The vertical channel structure can enable the transistor structure to have higher arrangement density, and can reduce the size of the transistor structure, so that the integration level of the semiconductor structure is improved.
In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of units is only one logical function division, and there may be other divisions in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.
The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (18)

1. A semiconductor structure, comprising: the transistor structure comprises a first transistor and a second transistor, and the channel structure of the first transistor and the channel structure of the second transistor extend along a third direction; the first direction and the second direction are any two directions in the plane of the substrate, and the third direction intersects with the plane of the substrate.
2. The semiconductor structure of claim 1, wherein the first transistor and the second transistor are different types of transistors.
3. The semiconductor structure of claim 2, wherein the first transistor and the second transistor are arranged in mirror symmetry.
4. The semiconductor structure of claim 1 or 2, wherein the gate structures of the first transistor and the second transistor comprise a gate dielectric layer and a gate conductive layer, and the first transistor and the second transistor share the gate conductive layer.
5. The semiconductor structure according to claim 1 or 2, wherein the channel structures of the first transistor and the second transistor each have at least one protrusion and/or at least one recess;
at least one convex part in the channel structure of the first transistor and at least one convex part in the channel structure of the second transistor are in mirror symmetry or staggered arrangement; or,
at least one concave part in the channel structure of the first transistor and at least one concave part in the channel structure of the second transistor are in mirror symmetry or staggered arrangement.
6. The semiconductor structure of claim 1, further comprising a conductive structure over the transistor structure, the conductive structure comprising a first conductive line, a second conductive line, and a third conductive line, the drain of the first transistor and the drain of the second transistor each being connected to the first conductive line, the source of the first transistor being connected to the second conductive line through a conductive plug, the source of the second transistor being connected to the third conductive line through a conductive plug.
7. The semiconductor structure of claim 6, wherein sources of a plurality of the first transistors are commonly electrically connected to the second conductive line and sources of a plurality of the second transistors are commonly electrically connected to the third conductive line in the second direction.
8. A method of forming a semiconductor structure, the method comprising:
providing a substrate;
forming a transistor structure which is arranged in an array along a first direction and a second direction on the surface of the substrate, wherein the transistor structure comprises a first transistor and a second transistor, and a channel structure of the first transistor and a channel structure of the second transistor extend along a third direction; the first direction and the second direction are any two directions in the plane of the substrate, and the third direction intersects with the plane of the substrate.
9. The method of claim 8, wherein the transistor structure is formed by:
forming first and second source electrodes spaced apart from each other along the first direction on a surface of the substrate;
forming a first channel structure and a second channel structure on the surfaces of the first source electrode and the second source electrode respectively;
forming a first drain and a second drain on top of the first channel structure and the second channel structure, respectively;
a common gate structure is formed between the first channel structure and the second channel structure.
10. The method of claim 9, wherein the first channel structure and the second channel structure are formed by:
forming a first epitaxial layer and a second epitaxial layer on the surfaces of the first source electrode and the second source electrode respectively;
forming a mask layer in gaps between the first source electrode and the second source electrode and between the first epitaxial layer and the second epitaxial layer;
forming a third epitaxial layer and a fourth epitaxial layer which cover part of the mask layer on the surfaces of the first epitaxial layer and the second epitaxial layer respectively;
and patterning the third epitaxial layer and the fourth epitaxial layer to correspondingly form the first channel structure and the second channel structure.
11. The method of claim 10, wherein the third epitaxial layer is formed to have a dimension greater than the dimension of the first epitaxial layer and the fourth epitaxial layer is formed to have a dimension greater than the dimension of the second epitaxial layer in the first direction.
12. The method of claim 11, wherein patterning the third epitaxial layer and the fourth epitaxial layer comprises:
etching to remove part of the side walls of the third epitaxial layer and the fourth epitaxial layer so as to form at least one convex part and/or at least one concave part on the two opposite side wall surfaces between the third epitaxial layer and the fourth epitaxial layer;
the first epitaxial layer and the rest of the third epitaxial layer form the first channel structure, and the second epitaxial layer and the rest of the fourth epitaxial layer form the second channel structure.
13. The method of claim 12, wherein after patterning the third epitaxial layer and the fourth epitaxial layer, the method further comprises:
removing the mask layer;
forming an isolation layer between the remaining third epitaxial layer and the remaining fourth epitaxial layer;
And performing ion implantation on the tops of the third epitaxial layer and the fourth epitaxial layer to form the first drain electrode and the second drain electrode respectively.
14. The method of claim 13, wherein the first source, the first channel structure, and the first drain together comprise a first active region, and the second source, the second channel structure, and the second drain together comprise a second active region; the method further comprises the steps of:
removing the isolation layer, exposing the side wall surfaces of the first active region and the second active region, and forming a gate dielectric layer on the exposed side wall surfaces;
and forming a first insulating layer, a gate conducting layer and a second insulating layer between the first active region with the gate dielectric layer and the second active region with the gate dielectric layer in sequence from bottom to top.
15. The method of claim 14, wherein the method further comprises:
forming a first conductive line electrically connected to the first drain electrode and the second drain electrode;
and forming a second conductive wire, a third conductive wire and a plurality of conductive plugs, wherein the first source electrode is electrically connected with the second conductive wire through the conductive plugs, and the second source electrode is electrically connected with the third conductive wire through the conductive plugs.
16. A layout structure, comprising: the source electrode layer comprises a plurality of first source electrodes and a plurality of second source electrodes which are arrayed along a first direction and a second direction, the channel layer comprises a plurality of first channel structures and a plurality of second channel structures which are arrayed along the first direction and the second direction, the first channel structures and the second channel structures extend along a third direction, and the drain electrode layer comprises a plurality of first drain electrodes and a plurality of second drain electrodes which are arrayed along the first direction and the second direction;
the first source electrodes and the second source electrodes are alternately arranged at intervals in sequence along the first direction; a plurality of the first source electrodes are arranged at intervals along the second direction, and a plurality of the second source electrodes are arranged at intervals;
two first channel structures are electrically connected above each first source electrode, and two second channel structures are electrically connected above each second source electrode; the upper part of each first channel structure is electrically connected with one first drain electrode, and the upper part of each second channel structure is electrically connected with one second drain electrode; wherein the third direction intersects a plane in which the first direction and the second direction are located.
17. The layout structure according to claim 16, further comprising: a gate layer located on the same layer as the channel layer, the gate layer including at least a plurality of gate conductive layers, the gate conductive layers extending along the second direction; one column of the first channel structures and one column of the second channel structures adjacently arranged in the first direction share one of the gate conductive layers.
18. The layout structure according to claim 16, further comprising: a conductive layer over the drain layer, the conductive layer including first, second, and third conductive lines disposed at intervals;
two adjacent first drains and second drains are electrically connected to the same first conductive line along the first direction;
along the second direction, two adjacent first sources are electrically connected with the same second conductive wire through conductive plugs, and two adjacent second sources are electrically connected with the same third conductive wire through conductive plugs.
CN202211091001.2A 2022-09-07 2022-09-07 Semiconductor structure, forming method thereof and layout structure Pending CN117712147A (en)

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