WO2024045354A1 - 存储器的时钟架构及存储器 - Google Patents

存储器的时钟架构及存储器 Download PDF

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Publication number
WO2024045354A1
WO2024045354A1 PCT/CN2022/132406 CN2022132406W WO2024045354A1 WO 2024045354 A1 WO2024045354 A1 WO 2024045354A1 CN 2022132406 W CN2022132406 W CN 2022132406W WO 2024045354 A1 WO2024045354 A1 WO 2024045354A1
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Prior art keywords
signal
oscillation signal
oscillation
clock
output
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PCT/CN2022/132406
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English (en)
French (fr)
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程景伟
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长鑫存储技术有限公司
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Priority to US18/509,485 priority Critical patent/US20240079044A1/en
Publication of WO2024045354A1 publication Critical patent/WO2024045354A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present disclosure relates to, but is not limited to, a clock architecture of a memory and a memory.
  • the data rate of 6400Mbps means that the data DQ rate transmitted on the data input/output bus of the memory is approximately 6400Mbps; data It is sampled by a double-edge clock, that is, the frequency of the read clock RDQS_t and RDQS_c and the write clock WCK_t and WCL_c is about 3200MHz; during the high-speed data transmission process of LPDDR5, the frequency of the read clock RDQS_t and RDQS_c and the write clock WCK_t and WCL_c is about the address/command clock The frequency of CK_t and CK_c is 4 times, that is, the frequency of address/command clock CK_t and CK_c is about 800MHz; the address/command signal CA is also double-edge sampling, that is, the data rate of the address/command signal is about 1600Mbps.
  • LPDDDR5 can process high-speed data at a smaller clock frequency by sampling address/command signals and reading and writing data on both edges, improving the data storage speed of the memory; however, based on the data mode of dual-edge sampling, Changes in the duty cycle of the clock signal have a greater impact on the eye diagrams of read operations and write operations.
  • the duty cycle of the clock signal needs to be additionally adjusted to stabilize the duty cycle of each clock signal.
  • the present disclosure provides a memory clock architecture and a memory that uses a low-speed clock signal to complete high-speed data processing while avoiding the impact of clock signal synchronization and duty cycle on memory reading and writing.
  • a first aspect of the present disclosure provides a data access verification method, including: an on-chip system configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal with the same frequency and amplitude. Oscillation signal; wherein, the phase difference between the first oscillation signal and the second oscillation signal is 90°, the phase difference between the first oscillation signal and the third oscillation signal is 180°, and the phase difference between the first oscillation signal and the fourth oscillation signal is 270°;
  • the memory chip is configured to output a data signal based on the signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and the memory chip is further configured to output the data signal based on the first oscillation signal and the third oscillation signal.
  • the signal edge of the signal outputs the command/address signal; the signal edge is a rising edge or a falling edge.
  • a second aspect of the present disclosure provides a memory built based on the memory clock structure provided in the above embodiment to output data signals and command/address signals.
  • Figure 1 is a schematic structural diagram of a clock structure of a memory provided by an embodiment of the present disclosure
  • Figure 2 is a timing diagram of a memory chip inputting data signals and command/address signals based on a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal according to an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a signal generation module provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a voltage controlled oscillator provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic connection diagram of the first frequency divider, the second frequency divider and the signal generation module provided by an embodiment of the present disclosure
  • Figure 6 is a schematic structural diagram of a signal conversion module provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic circuit structure diagram of a first driver provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of another signal conversion module provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of a first control module provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a second control module provided by an embodiment of the present disclosure.
  • 100. On-chip system 101. Oscillation generation unit; 102. Signal generation module; 200. Memory chip; 201. First control module; 202. Second control signal; 203. Signal conversion module; 301. Phase detector; 302. Low-pass filter; 303, voltage-controlled oscillator; 304, feedback divider; 401, first frequency divider; 402, second frequency divider; 501, first data module; 502, second data module; 503 , the third data module; 504, the fourth data module; 601, the first command/address module; 602, the second command/address module;
  • LPDDDR5 can process high-speed data at a smaller clock frequency through dual-edge sampling of address/command signals and reading and writing data, thereby improving the data storage speed of the memory; however, based on the data mode of dual-edge sampling, Changes in the duty cycle of the clock signal have a greater impact on the eye diagrams of read operations and write operations.
  • the duty cycle of the clock signal needs to be additionally adjusted to stabilize the duty cycle of each clock signal.
  • An embodiment of the present disclosure provides a memory clock architecture that uses a low-speed clock signal to complete high-speed data processing while avoiding the impact of clock signal synchronization and duty cycle on memory reading and writing.
  • Figure 1 is a schematic structural diagram of the clock structure of the memory provided in this embodiment.
  • Figure 2 is a memory chip provided in this embodiment that performs data signal summing based on the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal. Timing diagram of command/address signal input.
  • Figure 3 is a schematic structural diagram of the signal generation module provided in this embodiment.
  • Figure 4 is a schematic structural diagram of the voltage controlled oscillator provided in this embodiment.
  • Figure 5 is a first schematic diagram of the voltage controlled oscillator provided in this embodiment.
  • Figure 6 is a schematic structural diagram of a signal conversion module provided in this embodiment.
  • Figure 7 is a schematic circuit structure diagram of the first driver provided in this embodiment.
  • Figure 8 is a schematic structural diagram of another signal conversion module provided in this embodiment.
  • Figure 9 is a schematic structural diagram of the first control module provided in this embodiment.
  • Figure 10 is a schematic structural diagram of the second control module provided in this embodiment.
  • the clock architecture of the memory provided in this embodiment will be described in detail below with reference to the accompanying drawings, as follows:
  • the memory clock architecture includes:
  • the system-on-chip 100 is configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal with the same frequency and amplitude; wherein the first oscillation signal and the second oscillation signal have a phase difference of 90 °, the phase difference between the first oscillation signal and the third oscillation signal is 180°, and the phase difference between the first oscillation signal and the fourth oscillation signal is 270°.
  • the memory chip 200 is configured to output a data signal based on rising edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal.
  • the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal serve as the read clock/write clock of the memory chip 200 to control the memory chip 200 to write/read data.
  • the memory chip 200 is further configured to output a command/address signal based on rising edges of the first oscillation signal and the third oscillation signal.
  • the first oscillation signal and the third oscillation signal serve as address/command clocks of the memory chip 200 to control the memory chip 200 to control the command signal and address signal.
  • the memory chip 200 samples based on the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal to output a data signal, such that the rate of the data signal is 4 times the frequency of the first oscillation signal;
  • the memory chip 200 samples the first oscillation signal and the third oscillation signal to output a command/address signal, so that the frequency of the command/address signal is twice the frequency of the first oscillation signal, thereby achieving high-speed operation with a lower frequency clock signal. Processing of data.
  • This embodiment generates a four-phase first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal through an on-chip system.
  • the frequency of the first oscillation signal is about 1600 MHz.
  • the second oscillation signal After sampling the signal, the third oscillation signal and the fourth oscillation signal, the data rate obtained is about 6400Mbps.
  • the rate of the address/command signal obtained is about 3200Mbps.
  • the rising edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal are used to output the data signal and the command/address signal as an example for detailed description. does not constitute a limitation to this embodiment; in some embodiments, it can be adjusted accordingly to output the data signal based on the falling edge of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal and based on the first
  • the command/address signal is output on the falling edge of the oscillation signal and the third oscillation signal, whether the data signal and the command/address are output based on the rising edge or the falling edge of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal. signals all fall within the protection scope of this disclosure.
  • the system-on-chip 100 includes: an oscillation generation unit 101 for generating an initial oscillation signal, a signal generation module 102 connected to the oscillation generation unit 101, Configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal based on the initial oscillation signal.
  • the oscillation generation unit 101 can generate an initial oscillation signal based on a ring oscillator; in another example, the oscillation generation unit 101 can generate an initial oscillation signal based on a crystal oscillator.
  • the crystal oscillator can be a quartz crystal resonator or a clock oscillator.
  • the signal generation module 102 includes:
  • the phase detector 301 is configured to detect the phase difference between the initial oscillation signal and the output signal of the voltage controlled oscillator 303, and convert the phase difference into an initial voltage signal for output.
  • the low-pass filter 302 connected to the phase detector 301, is configured to filter the initial voltage signal to generate a control voltage signal.
  • the voltage controlled oscillator 303 connected to the low-pass filter 302, is configured to adjust the frequencies of the generated first, second, third and fourth oscillation signals based on the control voltage signal.
  • the feedback divider 304 is connected to the voltage-controlled oscillator 303 and the phase detector 301, and is configured to adjust the frequency of the first oscillation signal by N times before inputting it into the phase detector, where N is a positive number.
  • the phase detector 301 is usually composed of an analog multiplier. Assume that the initial oscillation signal is:
  • ⁇ i in the formula (1) is the instantaneous oscillation angular frequency of the input signal
  • ⁇ 0 in the formula (2) is the oscillation angular frequency of the voltage-controlled oscillator 303 when the input control voltage is zero or DC voltage, which is called voltage-controlled oscillation.
  • the natural oscillation angular frequency of the oscillator 303, ⁇ i(t) is the instantaneous phase of the initial oscillation signal, and ⁇ 0(t) is the instantaneous phase of the output signal of the voltage controlled oscillator 303.
  • ⁇ d in the equation (5) is the phase difference between the initial oscillation signal and the output signal of the voltage controlled oscillator 303 .
  • Equation (5) is equal to 0, indicating that the signal generation module 102 enters a phase-locked state.
  • the frequency and phase of the initial oscillation signal and the output signal of the voltage-controlled oscillator 303 remain constant, and Ud is a constant value;
  • (5 ) is not equal to 0, indicating that the signal generation module 102 has not entered a phase-locked state.
  • the frequency and phase of the initial oscillation signal and the output signal of the voltage-controlled oscillator 303 are different, and Ud changes with time.
  • a feedback divider 304 is set on the feedback path of the voltage-controlled oscillator 303 so that the frequency of the output signal of the voltage-controlled oscillator 303 is N times the frequency of the initial oscillation signal; specifically, when N is set to a positive number greater than 1 When N is set to a positive number less than 1, the frequency of the output signal of the voltage-controlled oscillator 303 is amplified compared to the frequency of the initial oscillation signal. The frequency of the signal is reduced.
  • the voltage-controlled oscillator 303 includes: a first inverter F1, the input terminal is connected to the input terminal of the fourth inverter, and the output terminal is connected to the second inverter F1.
  • the input terminal of the inverter; the input terminal of the second inverter F2 is used to output one of the third oscillation signal and the fourth oscillation signal, and the output terminal is used to output one of the first oscillation signal and the second oscillation signal;
  • the input terminal of the third inverter F3 is connected to the output terminal of the second inverter F2, and the output terminal is connected to the input terminal of the fourth inverter F4;
  • the input terminal of the fourth inverter F4 is used to output the third oscillation signal and
  • the output terminal of the other of the fourth oscillation signal is used to output the other of the first oscillation signal and the second oscillation signal;
  • the input terminal of the fifth inverter F5 is connected to the output terminal of the fourth inverter F4, and the output terminal Connect the input terminal of the second inverter F2;
  • the sixth inverter F6 the input terminal is connected to the output terminal of the second inverter F2, and the output terminal is connected to the input terminal of the fourth inverter F4;
  • control voltage signal is used to control the first inverter F1, the second inverter F2, the third inverter F3, the fourth inverter F4, the fifth inverter F5, the sixth inverter F6, Delay of the seventh inverter F7 and the eighth inverter F8.
  • the output terminal of the first inverter F1 outputs the third oscillation signal through the first output inverter S1
  • the output terminal of the second inverter F2 outputs the first signal through the second output inverter S2 .
  • the output terminal of the third inverter F3 outputs the fourth oscillation signal through the third output inverter S3, and the output terminal of the fourth inverter F4 outputs the second oscillation signal through the fourth output inverter S4;
  • the first oscillation signal may be directly output through the output terminal of the first inverter
  • the third oscillation signal may be directly output through the output terminal of the second inverter
  • the second oscillation signal may be directly output through the output terminal of the third inverter.
  • the output terminal of the fourth inverter directly outputs the fourth oscillation signal.
  • the system-on-chip 100 also includes: a first frequency divider 401, connected to the signal generation module 102, configured to adjust the frequency of the initial oscillation signal R times and then input the signal generation module, R is a positive number.
  • a first frequency divider 401 By setting the first frequency divider 401 so that the frequencies of the generated first oscillation signal, second oscillation signal, third oscillation signal and fourth oscillation signal are N/R times of the initial oscillation signal, the generated first oscillation signal can be flexibly adjusted. Frequencies of the oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal.
  • the frequency of the output signal of the voltage controlled oscillator 303 is reduced compared to the frequency of the initial oscillation signal; when R is set to a positive number smaller than N, The frequency of the output signal of the voltage controlled oscillator 303 is amplified compared to the frequency of the initial oscillation signal.
  • the system-on-chip 100 further includes: a second frequency divider 402 connected to the signal generation module 102, configured to convert the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal
  • the frequency is adjusted by O times and then output, O is a positive number.
  • the second frequency divider 402 By setting the second frequency divider 402 so that the frequencies of the generated first oscillation signal, second oscillation signal, third oscillation signal and fourth oscillation signal are N/O times of the initial oscillation signal, the generated first oscillation signal can be flexibly adjusted. Frequencies of the oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal.
  • the frequency of the output signal of the voltage-controlled oscillator 303 is reduced compared with the frequency of the initial oscillation signal; when O is set to a positive number smaller than N, the voltage-controlled oscillation The frequency of the output signal of the device 303 is amplified compared to the frequency of the initial oscillation signal.
  • the frequencies of the generated first oscillation signal, second oscillation signal, third oscillation signal and fourth oscillation signal are N/( of the initial oscillation signal O*R) times to further adjust the frequencies of the generated first oscillation signal, second oscillation signal, third oscillation signal and fourth oscillation signal.
  • O*R is set to a positive number greater than N
  • the frequency of the output signal of the voltage controlled oscillator 303 is reduced compared to the frequency of the initial oscillation signal
  • O*R is set to a positive number less than N
  • the frequency of the output signal of the voltage controlled oscillator 303 is amplified compared to the frequency of the initial oscillation signal.
  • the memory chip 200 includes: a signal conversion module 203 configured to adjust the first oscillation signal, the second oscillation signal, and the third oscillation signal. signal and the amplitude of the fourth oscillation signal to generate the corresponding first clock signal, second clock signal, third clock signal and fourth clock signal; the first control module 201, connected to the signal conversion module 203, is configured as, Based on the rising edges of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, the initial data signal is sampled to output a data signal; the second control signal 202 is connected to the signal conversion module 203 and is configured as, Based on rising edges of the first clock signal and the third clock signal, the initial command/address signal is sampled to output the command/address signal.
  • the amplitudes of the first, second, third and fourth oscillation signals are adjusted through the signal conversion module 203 to generate corresponding first, second, third and fourth clock signals.
  • the clock signal such that the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal serve as clock signals of the memory chip 200, controls the generation of data signals and command/address signals.
  • the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are generated based on differential input.
  • the signal conversion module 203 includes: the first driver Q1, The second driver Q2 is configured to generate the first clock signal and the third clock signal based on the first oscillation signal and the third oscillation signal; the second driver Q2 is configured to generate the second clock signal and the third clock signal based on the second oscillation signal and the fourth oscillation signal.
  • the first clock signal and the third clock signal generated through differential input are more accurate, thereby accurately controlling the memory chip 200 to generate data signals and command/address signals.
  • the first driver Q1 includes: a first P-type transistor P1, the gate is used to receive the third oscillation signal, the source is connected to the drain of the third switching transistor K3, and the drain is connected to the first N-type transistor N1
  • the drain of the second P-type transistor P2 the gate is used to receive the first oscillation signal, the source is connected to the drain of the third switching transistor K3, and the drain is connected to the drain of the second N-type transistor N2;
  • the first N-type The gate of the transistor N1 is connected to the drain of the fourth switching transistor K4 and the drain of the first P-type transistor P1, and the source is grounded;
  • the gate of the second N-type transistor N2 is connected to the drain of the fourth switching transistor K4, The source is grounded, and the drain is connected to the output transmission line;
  • the gate of the third switching transistor K3 is used to receive the enable signal, and the source is used to receive the power supply voltage Vcc;
  • the gate of the fourth switching transistor K4 is used to receive the enable signal, and the source
  • the third switching transistor K3 when the enable signal is high level, the third switching transistor K3 is turned off, and the fourth switching transistor K4 is turned on. At this time, no matter whether the inputs of the first oscillation signal and the second oscillation signal are high level or low level, level, the output first clock signal and the second clock signal are low level; when the enable signal is low level, the third switching transistor K3 is turned on, and the fourth switching transistor K4 is turned off.
  • the first oscillation The signal is high level, then the third oscillation signal is low level, the first P-type transistor P1 is turned on, and the gate potentials of the first N-type transistor N1 and the second N-type transistor N2 are pulled up, and the second N-type transistor N2 is turned on, pulling down the level of the output transmission line, the third clock signal output is low level, and the first clock signal is high level; if the first oscillation signal is low level, the third oscillation signal is high level , the second P-type transistor P2 is turned on, pulling up the level of the output transmission line, the third clock signal output is high level, and the first clock signal is low level.
  • the first driver Q1 further includes: a first switching transistor K1, the gate is used to receive the enable signal, the source is used to receive the power supply voltage Vcc, and the drain is connected to the source of the first adjustment transistor T1;
  • the gate of an adjustment transistor T1 is used to receive the first adjustment signal, and the drain is connected to the drain of the third switching transistor K3;
  • the gate of the second switching transistor K2 is used to receive the enable signal, and the source is used to receive the power supply voltage Vcc.
  • the drain is connected to the source of the second adjustment transistor T2, the gate of the second adjustment transistor T2 is used to receive the second adjustment signal, and the drain is connected to the drain of the third switching transistor K3.
  • the first adjustment transistor T1 when the enable signal is low level, the first adjustment transistor T1 is turned on through the first adjustment signal, thereby increasing the source voltages of the first P-type transistor P1 and the second P-type transistor P2, or through the second The adjustment signal turns on the second adjustment transistor T2, thereby increasing the source voltages of the first P-type transistor P1 and the second P-type transistor P2.
  • the source voltages of the first P-type transistor P1 and the second P-type transistor P2 are increased, thereby The amplitudes of the generated first clock signal and the third clock signal are changed.
  • the gradient improvement of the source voltage of the first P-type transistor P1 and the second P-type transistor P2 can be achieved by changing the ratio of the first adjustment transistor T1 and the second adjustment transistor T2.
  • the opening degree of the first adjustment transistor T1 and the second adjustment transistor T2 can be controlled by changing the magnitude of the first adjustment signal and the second adjustment signal, thereby realizing the adjustment of the first P-type transistor P1 and the second P-type transistor P1.
  • the gradient of the source voltage of transistor P2 increases.
  • the first driver Q1 also includes: a first reset transistor W1, a gate for receiving the first reset signal, a source for receiving the power supply voltage, and a drain connected to the output transmission line; a second reset transistor W2, The gate is used to receive the second reset signal, the source is connected to ground, and the drain is connected to the output transmission line.
  • the first reset transistor W1 when the first reset signal is low level, the first reset transistor W1 is turned on, and the level of the output transmission line is forcibly pulled high; when the second reset signal is high level, the second reset transistor W2 is turned on, and the output The level of the transmission line is forced low.
  • the structure of the second driver Q2 is the same as that of the first driver Q1.
  • the structure of the first driver Q1 is not be described again in this embodiment.
  • the first, second, third and fourth clock signals are directly generated based on the corresponding first, second, third and fourth oscillation signals;
  • the signal conversion module 203 includes: a first driver Q1 configured to generate a first clock signal based on the first oscillation signal; a second driver Q2 configured to generate a second clock signal based on the second oscillation signal ;
  • the third driver Q3 is configured to generate a third clock signal based on the third oscillation signal;
  • the fourth driver Q4 is configured to generate a fourth clock signal based on the fourth oscillation signal.
  • the first control module 201 includes: a first data module 501, used to receive an initial data signal, a first reference signal and a first clock signal, configured to, based on the first clock The rising edge of the signal compares the initial data signal and the first reference signal to generate a data signal;
  • the second data module 502 is used to receive the initial data signal, the first reference signal and the second clock signal, and is configured to, based on the second The rising edge of the clock signal compares the initial data signal and the first reference signal to generate a data signal;
  • the third data module 503 is used to receive the initial data signal, the first reference signal and the third clock signal, and is configured to, based on the The rising edge of the three clock signals compares the initial data signal and the first reference signal to generate a data signal;
  • the fourth data module 504 is used to receive the initial data signal, the first reference signal and the fourth clock signal, and is configured to, based on The rising edge of the fourth clock signal compares the initial data signal and the first reference signal to
  • the first data module 501 is driven based on the rising edge of the first clock signal
  • the second data module 502 is driven based on the rising edge of the second clock signal
  • the third data module 503 is driven based on the rising edge of the third clock signal
  • the fourth data module 503 is driven based on the rising edge of the third clock signal.
  • the data module 504 is driven based on the rising edge of the fourth clock signal
  • the first data module 501, the second data module 502, the third data module 503 or the fourth data module 504 that is turned on is based on the comparison between the initial data signal and the first reference signal. As a result, a data signal is generated.
  • the generated data signal if the level of the initial data signal is greater than or equal to the first reference signal, the generated data signal is high level; if the level of the initial data signal is less than the first reference signal, the generated data signal is low level.
  • the second control module 202 includes: a first command/address module 601, used to receive an initial command/address signal, a second reference signal and a first clock signal, and is configured as, Based on the rising edge of the first clock signal, compare the initial command/address signal and the second reference signal to generate a command/address signal; the second command/address module 602 is used to receive the initial command/address signal, the second reference signal and The third clock signal is configured to compare the initial command/address signal and the second reference signal based on the rising edge of the third clock signal to generate the command/address signal.
  • a first command/address module 601 used to receive an initial command/address signal, a second reference signal and a first clock signal, and is configured as, Based on the rising edge of the first clock signal, compare the initial command/address signal and the second reference signal to generate a command/address signal
  • the second command/address module 602 is used to receive the initial command/address
  • the first command/address module 601 is driven based on the rising edge of the first clock signal
  • the second command/address module 602 is driven based on the rising edge of the third clock signal.
  • the first command/address module 601 or the second one is turned on.
  • the command/address module 602 generates a command/address signal based on a comparison result of the initial command/address signal and the second reference signal.
  • the generated command/address signal is high level. If the level of the initial command/address signal is less than the second reference signal, the generated command /address signal is low.
  • the first reference signal and the second reference signal may be set based on the same reference level; in other embodiments, the first reference signal and The reference level of the second reference signal may be set to different levels.
  • this embodiment uses the first clock signal (first oscillation signal) and the third clock signal (third oscillation signal) to control the output of the command/address signal as an example for detailed description.
  • the command / The output of the address signal may be controlled based on the second clock signal and the fourth clock signal.
  • This embodiment generates a four-phase first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal through an on-chip system.
  • the frequency of the first oscillation signal is about 1600 MHz.
  • the second oscillation signal After sampling the signal, the third oscillation signal and the fourth oscillation signal, the data rate obtained is about 6400Mbps.
  • the rate of the address/command signal obtained is about 3200Mbps.
  • Another embodiment of the present disclosure provides a memory based on the memory clock structure provided in the above embodiment to output data signals and command/address signals, complete high-speed data processing through low-speed clock signals, and avoid synchronization and occupation of clock signals. The impact of space ratio on memory reading and writing.
  • the four-phase first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal are generated through the on-chip system. Assuming that the frequency of the first oscillation signal is about 1600MHz, based on the first oscillation signal, the second oscillation signal After sampling the signal, the third oscillation signal and the fourth oscillation signal, the data rate obtained is about 6400Mbps. After the address/command signal is sampled based on the first oscillation signal and the third oscillation signal, the rate of the address/command signal obtained is about 3200Mbps.
  • the memory may be a memory unit or device based on a semiconductor device or component.
  • the memory device may be a volatile memory such as dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory Access memory LPDDR SDRAM, graphics double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, dual Double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, thyristor random access memory TRAM, etc.; or it can be a non-volatile memory, such as phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory Access memory RRAM, etc.
  • the four-phase first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal are generated by the on-chip system, thereby realizing a clock with a lower frequency.
  • the signal performs high-speed data processing; in addition, since the data is only sampled based on one of the rising edge and the falling edge, the duty cycle of the clock signal has little impact on the eye diagram of the read operation and write operation, and there is no need to process the clock signal
  • the synchronization is conducive to the subsequent improvement of the memory read and write rate.

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Abstract

本公开提供一种存储器的时钟架构及存储器，涉及半导体电路设计领域，存储器的时钟架构包括：片上系统，被配置为，产生频率和幅值相同的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号；其中，第一振荡信号和第二振荡信号的相位相差90°，第一振荡信号和第三振荡信号的相位相差180°，第一振荡信号和第四振荡信号的相位相差270°；存储芯片，被配置为，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的信号沿输出数据信号，且基于第一振荡信号和第三振荡信号的信号沿输出命令/地址信号，信号沿为上升沿或下降沿。

Description

存储器的时钟架构及存储器
本公开基于申请号为202211065406.9、申请日为2022年08月31日、申请名称为“存储器的时钟架构及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种存储器的时钟架构及存储器。
背景技术
对于LPDDR5的存储器，在进行数据读出时，基于读时钟RDQS_t以及RDQS_c双边沿采样以完成数据读出；在进行数据写入时，基于写时钟WCK_t以及WCL_c双边沿采样以完成数据写入；在进行命令/地址信号CA输入时，基于地址/命令时钟CK_t以及CK_c双边沿一样以完成命令/地址信号的输入控制。
在一个例子中，对于8引脚4通道的LPDDR5存储器，以存储模式下读写6400Mbps数据速率为例示例，数据速率6400Mbps即存储器的数据输入/输出总线上传输的数据DQ速率约为6400Mbps；数据由双边沿时钟采样，即读时钟RDQS_t以及RDQS_c和写时钟WCK_t以及WCL_c的频率约为3200MHz；LPDDR5在高速数据传输过程中，读时钟RDQS_t以及RDQS_c和写时钟WCK_t以及WCL_c的频率约地址/命令时钟CK_t以及CK_c频率的4倍，即地址/命令时钟CK_t以及CK_c频率约为800MHz；地址/命令信号CA同样为双边沿采样，即地址/命令信号的数据速率约为1600Mbps。
由上述举例可知，LPDDDR5通过双边沿采样地址/命令信号以及读写数据，可以以较小的时钟频率进行高速数据的处理，提高了存储器的数据存储速度；然而，基于双边沿采样的数据模式，时钟信号的占空比变化对读操作和写操作的眼图的影响较大，需要额外调节时钟信号的占空比，以稳定各时钟信号的占空比；另外，在这种采样模式下，还需进行读时钟RDQS_t和RDQS_c的同步、写时钟WCK_t和WCL_c的同步以及地址/命令时钟CK_t和CK_c的同步，在一定程度上，影响了后续对存储器读写速率的提升。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种存储器的时钟架构及存储器，通过低速时钟信号完成高速数据处理的同时，避免时钟信号的同步以及占空比对存储器读写的影响。
本公开的第一方面提供了一种数据存取校验方法，包括：片上系统，被配置为，产生频率和幅值相同的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号；其中，第一振荡信号和第二振荡信号的相位相差90°，第一振荡信号和第三振荡信号的相位相差180°，第一振荡信号和第四振荡信号的相位相差270°；存储芯片，被配置为，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的信号沿输出数据信号，存储芯片还被配置为，基于第一振荡信号和第三振荡信号的信号沿输出命令/地址信号；所述信号沿为上升沿或下降沿。
本公开的第二方面提供了一种存储器，基于上述实施例提供的存储器时钟结构构建，以输出数据信号以及命令/地址信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与 描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的存储器的时钟结构的结构示意图；
图2为本公开一实施例提供的存储芯片基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号进行数据信号和命令/地址信号输入的时序示意图；
图3为本公开一实施例提供的信号产生模块的结构示意图；
图4为本公开一实施例提供的压控振荡器的结构示意图；
图5为本公开一实施例提供的第一分频器、第二分频器和信号产生模块的连接示意图；
图6为本公开一实施例提供的一种信号转换模块的结构示意图；
图7为本公开一实施例提供的第一驱动器的电路结构示意图；
图8为本公开一实施例提供的另一种信号转换模块的结构示意图；
图9为本公开一实施例提供的第一控制模块的结构示意图；
图10为本公开一实施例提供的第二控制模块的结构示意图。
附图标记：
100、片上系统；101、振荡产生单元；102、信号产生模块；200、存储芯片；201、第一控制模块；202、第二控制信号；203、信号转换模块；301、鉴相器；302、低通滤波器；303、压控振荡器；304、反馈分频器；401、第一分频器；402、第二分频器；501、第一数据模块；502、第二数据模块；503、第三数据模块；504、第四数据模块；601、第一命令/地址模块；602、第二命令/地址模块；
F1、第一反相器；F2、第二反相器；F3、第三反相器；F4、第四反相器；F5、第五反相器；F6、第六反相器；F7、第七反相器；F8、第八反相器；S1、第一输出反相器；S2、第二输出反相器；S3、第三输出反相器；S4、第四输出反相器；S5、输出反相器；Q1、第一驱动器；Q2、第二驱动器；Q3、第三驱动器；P1、第一P型晶体管；P2、第二P型晶体管；N1、第一N型晶体管；N2、第二N型晶体管；K1、第一开关晶体管；K2、第二开关晶体管；K3、第三开关晶体管；K4、第四开关晶体管；T1、第一调整晶体管；T2、第二调整晶体管；W1、第一复位晶体管；W2、第二复位晶体管。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，LPDDDR5通过双边沿采样地址/命令信号以及读写数据，可以以较小的时钟频率进行高速数据的处理，提高了存储器的数据存储速度；然而，基于双边沿采样的数据模式，时钟信号的占空比变化对读操作和写操作的眼图的影响较大，需要额外调节时钟信号的占空比，以稳定各时钟信号的占空比；另外，在这种采样模式下，还需进行读时钟RDQS_t和RDQS_c的同步、写时钟WCK_t和WCL_c的同步以及地址/命令时钟CK_t和CK_c的同步，在一定程度上，影响了后续对存储器读写速率的提升。
本公开一实施例提供了一种存储器的时钟架构，通过低速时钟信号完成高速数据处理的同时，避免时钟信号的同步以及占空比对存储器读写的影响。
图1为本实施例提供的存储器的时钟结构的结构示意图，图2为本实施例提供的存储芯片基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号进行数据信号和命令/地址信号输入的时序示意图，图3为本实施例提供的信号产生模块的结构示意图，图4为本实施例提供的压控振荡器的结构示意图，图5为本实施例提供的第一分频器、第二分频器和信号产生模块的连接示意图，图6为本实施例提供的一种信号转换模块的结构示意图，图7为本实施例提供的第一驱动器的电路结构示意图，图8为本实施例提供的另一种信号转换模块的结构示意图，图9为本实施例提供的第一控制模块的结构示意图，图10为本实施例提供的第二控制模块的结构示意图，以下结合附图对本实施例提供的存储器的时钟架构进行详细说明，具体如下：
参考图1，存储器的时钟架构，包括：
片上系统100，被配置为，产生频率和幅值相同的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号；其中，第一振荡信号和第二振荡信号的相位相差90°，第一振荡信号和第三振荡信号的相位相差180°，第一振荡信号和第四振荡信号的相位相差270°。
存储芯片200，被配置为，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的上升沿输出数据信号。具体地，第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号作为存储芯片200的读时钟/写时钟，控制存储芯片200进行数据的写入/读出。
存储芯片200还被配置为，基于第一振荡信号和第三振荡信号的上升沿输出命令/地址信号。具体地，第一振荡信号和第三振荡信号作为存储芯片200的地址/命令时钟，控制存储芯片200进行命令信号和地址信号的控制。
具体参考图2，存储芯片200基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号采样以输出数据信号，使得数据信号的速率为第一振荡信号的频率的4倍；存储芯片200基于第一振荡信号和第三振荡信号采样以输出命令/地址信号，使得命令/地址信号的频率为第一振荡信号的频率的2倍，实现了以较低频率的时钟信号进行高速数据的处理。
本实施例通过片上系统产生四相位的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号，假设第一振荡信号的频率约为1600MHz，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号采样后获取的数据速率约为6400Mbps，地址/命令信号基于第一振荡信号和第三振荡信号采样后，获取的地址/命令信号的速率约为3200Mbps，实现了以较低频率的时钟信号进行高速数据的处理；另外，由于数据仅基于上升沿和下降沿的其中一者进行采样，时钟信号的占空比对读操作和写操作的眼图影响较小，且无需在进行时钟信号的同步，有利于后续对存储器读写速率的提升。
需要说明的是，在本实施例的描述中，以第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的上升沿输出数据信号和命令/地址信号为例进行详细说明，并不构成对本实施例的限定；在一些实施例中，可以相应调整为，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的下降沿输出数据信号并基于第一振荡信号和第三振荡信号的下降沿输出命令/地址信号，无论基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的上升沿还是下降沿输出数据信号和命令/地址信号，皆属于本公开的保护范围。
继续参考图1，对于本实施例提供的片上系统100，在一些实施例中，片上系统100，包括：振荡产生单元101，用于产生初始振荡信号，信号产生模块102，连接振荡产生单元101，被配置为，基于初始振荡信号，产生第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号。
在一个例子中，振荡产生单元101可以基于环形振荡器产生初始振荡信号；在另一个例子中，振荡产生单元101可以基于晶振产生初始振荡信号，相应地，晶振可以为石英晶体谐振器、时钟振荡器、温补晶振、压控晶振或恒温晶振的其中一种。
对于信号产生模块102，在一些实施例中，参考图3，信号产生模块102，包括：
鉴相器301，被配置为，检测初始振荡信号和压控振荡器303的输出信号的相位差，并将相位差转换为初始电压信号输出。
低通滤波器302，连接鉴相器301，被配置为，对初始电压信号滤波以生成控制电压信号。
压控振荡器303，连接低通滤波器302，被配置为，基于控制电压信号，调节生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率。
反馈分频器304，连接压控振荡器303和鉴相器301，被配置为，将第一振荡信号的频率调节N倍后输入鉴相器，N为正数。
具体地，鉴相器301通常由模拟乘法器组成，假设初始振荡信号为：
Ui(t)＝Um*Sin[ωit+θi(t)]      (1)
压控振荡器303的输出信号为：Uo(t)＝Uom*Cos[ω0t+θ0(t)]      (2)
(1)式中的ωi为输入信号的瞬时振荡角频率，(2)式中的ω0为压控振荡器303在输入控制电压为零或为直流电压时的振荡角频率，称为压控振荡器303的固有振荡角频率，θi(t)为初始振荡信号瞬时相位，θ0(t)为压控振荡器303输出信号的瞬时相位。
鉴相器301的输出为：Ud＝K*Ui(t)*Uo(t)＝K*Um*Uom*Sin[ωit+θi(t)]*Cos[ω0t+θ0(t)]＝K/2*Um*Uom*Sin[ωit+θi(t)+ω0t+θ0(t)]+K/2*Um*Uom*Sin{[ωit+θi(t)]-[ω0t+θ0(t)]}     (3)
(3)式经过低通滤波器302后过滤掉和频分量，差频分量作为压控振荡器303的控制电压信号。
根据向量关系可得瞬时频率和瞬时相位的关系为：ω(t)＝dθi(t)/dt     (4)
结合(3)和(4)式可得：dθd/dt＝d(ωi-ω0)t/dt-d[θi(t)-θ0(t)]/dt     (5)
(5)式中的θd为初始振荡信号和压控振荡器303的输出信号的相位差。
(5)式等于0，说明信号产生模块102进入相位锁定的状态，此时初始振荡信号和压控振荡器303的输出信号的频率和相位保持恒定不变的状态，Ud为恒定值；(5)式不等于0，说明信号产生模块102未进入相位锁定的状态，此时初始振荡信号和压控振荡器303的输出信号的频率和相位不同，Ud随时间变化。
在压控振荡器303的反馈通路上设置反馈分频器304，使得压控振荡器303的输出信号的频率为初始振荡信号的频率的N倍；具体地，当N设置为大于1的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了放大；当N设置为小于1的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了缩小。
对于压控振荡器303，参考图4，在一些实施例中，压控振荡器303包括：第一反相器F1，输入端连接第四反相器的输入端，输出端连接第二反相器的输入端；第二反相器F2的输入端用于输出第三振荡信号和第四振荡信号的其中一者，输出端用于输出第一振荡信号和第二振荡信号的其中一者；第三反相器F3，输入端连接第二反相器F2的输出端，输出端连接第四反相器F4的输入端；第四反相器F4的输入端用于输出第三振荡信号和第四振荡信号的另外一者，输出端用于输出第一振荡信号和第二振荡信号的另外一者；第五反相器F5，输入端连接第四反相器F4的输出端，输出端连接第二反相器F2的输入端；第六反相器F6，输入端连接第二反相器F2的输出端，输出端连接第四反相器F4的输入端；第七反相器F7，输入端连接第三反相器F3的 输出端，输出端连接第一反相器F1的输入端；第八反相器F8，输入端连接第一反相器F1的输出端，输出端连接第三反相器F3的输入端。
其中，控制电压信号用于控制第一反相器F1、第二反相器F2、第三反相器F3、第四反相器F4、第五反相器F5、第六反相器F6、第七反相器F7和第八反相器F8的延迟。
在图4的示例中，第一反相器F1的输出端通过第一输出反相器S1输出第三振荡信号，第二反相器F2的输出端通过第二输出反相器S2输出第一振荡信号，第三反相器F3的输出端通过第三输出反相器S3输出第四振荡信号，第四反相器F4的输出端通过第四输出反相器S4输出第二振荡信号；在其他实施例中，也可以通过第一反相器的输出端直接输出第一振荡信号，第二反相器的输出端直接输出第三振荡信号，第三反相器的输出端直接输出第二振荡信号，第四反相器的输出端直接输出第四振荡信号。
在一些实施例中，参考图5，片上系统100，还包括：第一分频器401，连接信号产生模块102，被配置为，将初始振荡信号的频率调节R倍后输入信号产生模块，R为正数。通过设置第一分频器401，使得生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率为初始振荡信号的N/R倍，以灵活调节生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率。具体地，具体地，当R设置为大于N的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了缩小；当R设置为小于N的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了放大。
在一些实施例中，片上系统100，还包括：第二分频器402，连接信号产生模块102，被配置为，将第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率调节O倍后输出，O为正数。通过设置第二分频器402，使得生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率为初始振荡信号的N/O倍，以灵活调节生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率。具体地，当O设置为大于N的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了缩小；当O设置为小于N的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了放大。
另外，通过设置第一分频器401和第二分频器402，使得生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率为初始振荡信号的N/(O*R)倍，以进一步调节生成的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的频率。具体地，当O*R设置为大于N的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了缩小；当O*R设置为小于N的正数时，压控振荡器303的输出信号的频率相较于初始振荡信号的频率进行了放大。
继续参考图1，对于本实施例提供的存储芯片200，在一些实施例中，存储芯片200，包括：信号转换模块203，被配置为，调节第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的幅值，以生成相应的第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；第一控制模块201，连接信号转换模块203，被配置为，基于第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的上升沿，采样初始数据信号，以输出数据信号；第二控制信号202，连接信号转换模块203，被配置为，基于第一时钟信号和第三时钟信号的上升沿，采样初始命令/地址信号，以输出命令/地址信号。
通过信号转换模块203调节第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号的幅值，以生成相应的第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，从而使得第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号作 为存储芯片200的时钟信号，控制数据信号以及命令/地址信号的生成。
在一些实施例中，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号基于查差分输入的方式生成；参考图6，信号转换模块203，包括：第一驱动器Q1，被配置为，基于第一振荡信号和第三振荡信号产生第一时钟信号和第三时钟信号；第二驱动器Q2，被配置为，基于第二振荡信号和第四振荡信号产生第二时钟信号和第四时钟信号。通过差分输入的方式生成的第一时钟信号和第三时钟信号的更加准确，从而准确控制存储芯片200对于数据信号以及命令/地址信号的生成。
对于第一驱动器Q1，第一驱动器Q1包括：第一P型晶体管P1，栅极用于接收第三振荡信号，源极连接第三开关晶体管K3的漏极，漏极连接第一N型晶体管N1的漏极；第二P型晶体管P2，栅极用于接收第一振荡信号，源极连接第三开关晶体管K3的漏极，漏极连接第二N型晶体管N2的漏极；第一N型晶体管N1的栅极连接第四开关晶体管K4的漏极，且连接第一P型晶体管P1的漏极，源极接地；第二N型晶体管N2的栅极连接第四开关晶体管K4的漏极，源极接地，漏极连接输出传输线；第三开关晶体管K3的栅极用于接收使能信号，源极用于接收电源电压Vcc；第四开关晶体管K4的栅极用于接收使能信号，源极接地；输出传输线用于输出第三时钟信号，且输出传输先通过输出反相器S5输出第一时钟信号。
具体地，当使能信号为高电平，第三开关晶体管K3关断，第四开关晶体管K4导通，此时，无论第一振荡信号和第二振荡信号的输入为高电平还是低电平，输出的第一时钟信号和第二时钟信号为低电平；当使能信号为低电平，第三开关晶体管K3导通，第四开关晶体管K4关断，此时，若第一振荡信号为高电平，则第三振荡信号为低电平，第一P型晶体管P1导通，上拉第一N型晶体管N1和第二N型晶体管N2的栅极电位，第二N型晶体管N2导通，下拉输出传输线的电平，输出的第三时钟信号为低电平，第一时钟信号为高电平；若第一振荡信号为低电平，则第三振荡信号为高电平，第二P型晶体管P2导通，上拉输出传输线的电平，输出的第三时钟信号为高电平，第一时钟信号为低电平。在一些实施例中，第一驱动器Q1还包括：第一开关晶体管K1，栅极用于接收使能信号，源极用于接收电源电压Vcc，漏极连接第一调整晶体管T1的源极；第一调整晶体管T1的栅极用于接收第一调整信号，漏极连接第三开关晶体管K3的漏极；第二开关晶体管K2，栅极用于接收使能信号，源极用于接收电源电压Vcc，漏极连接第二调整晶体管T2的源极，第二调整晶体管T2的栅极用于接收第二调整信号，漏极连接第三开关晶体管K3的漏极。
具体地，当使能信号为低电平时，通过第一调整信号导通第一调整晶体管T1，从而增大第一P型晶体管P1和第二P型晶体管P2的源极电压，或通过第二调整信号导通第二调整晶体管T2，从而增大第一P型晶体管P1和第二P型晶体管P2的源极电压。
通过第一开关晶体管K1、第二开关晶体管K2、第一调整晶体管T1和第二调整晶体管T2的协调控制，以增大第一P型晶体管P1和第二P型晶体管P2的源极电压，从而改变生成的第一时钟信号和第三时钟信号的幅值。在一些实施例中，可以通过改变第一调整晶体管T1和第二调整晶体管T2的宽敞比，从而实现对第一P型晶体管P1和第二P型晶体管P2的源极电压的梯度提高，在一些实施例中，可以通过改变第一调整信号和第二调整信号的大小，从而控制第一调整晶体管T1和第二调整晶体管T2的开启程度，从而实现对第一P型晶体管P1和第二P型晶体管P2的源极电压的梯度提高。
在一些实施例中，第一驱动器Q1，还包括：第一复位晶体管W1，栅极用于接收第一复位信号，源极用于接收电源电压，漏极连接输出传输线；第二复位晶体管W2，栅极用于接收第二复位信号，源极接地，漏极连接输出传输线。
具体地，当第一复位信号为低电平，第一复位晶体管W1导通，输出传输线的电平强制拉高；当第二复位电平为高电平，第二复位晶体管W2导通，输出传输线的电平强制拉低。
需要说明的是，第二驱动器Q2的结构与第一驱动器Q1的结构相同，对于第二驱动器Q2的描述参考上述第一驱动器Q1的结构，本实施例不再赘述。
在一些实施例中，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号基于相应的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号直接生成；参考图8，信号转换模块203，包括：第一驱动器Q1，被配置为，基于第一振荡信号产生第一时钟信号；第二驱动器Q2，被配置为，基于第二振荡信号产生第二时钟信号；第三驱动器Q3，被配置为，基于第三振荡信号产生第三时钟信号；第四驱动器Q4，被配置为，基于第四振荡信号产生第四时钟信号。
对于第一控制模块201，参考图9，第一控制模块201，包括：第一数据模块501，用于接收初始数据信号、第一参考信号和第一时钟信号，被配置为，基于第一时钟信号的上升沿，比较初始数据信号和第一参考信号，以生成数据信号；第二数据模块502，用于接收初始数据信号、第一参考信号和第二时钟信号，被配置为，基于第二时钟信号的上升沿，比较初始数据信号和第一参考信号，以生成数据信号；第三数据模块503，用于接收初始数据信号、第一参考信号和第三时钟信号，被配置为，基于第三时钟信号的上升沿，比较初始数据信号和第一参考信号，以生成数据信号；第四数据模块504，用于接收初始数据信号、第一参考信号和第四时钟信号，被配置为，基于第四时钟信号的上升沿，比较初始数据信号和第一参考信号，以生成数据信号；
具体地，第一数据模块501基于第一时钟信号的上升沿驱动，第二数据模块502基于第二时钟信号的上升沿驱动，第三数据模块503基于第三时钟信号的上升沿驱动，第四数据模块504基于第四时钟信号的上升沿驱动，导通的第一数据模块501、第二数据模块502、第三数据模块503或第四数据模块504基于初始数据信号和第一参考信号的比较结果，生成数据信号。
在一个例子中，若初始数据信号的电平大于等于第一参考信号，生成的数据信号为高电平，若初始数据信号的电平小于第一参考信号，生成的数据信号为低电平。
对于第二控制模块202，参考图10，第二控制模块202，包括：第一命令/地址模块601，用于接收初始命令/地址信号、第二参考信号和第一时钟信号，被配置为，基于第一时钟信号的上升沿，比较初始命令/地址信号和第二参考信号，以生成命令/地址信号；第二命令/地址模块602，用于接收初始命令/地址信号、第二参考信号和第三时钟信号，被配置为，基于第三时钟信号的上升沿，比较初始命令/地址信号和第二参考信号，以生成命令/地址信号。
具体地，第一命令/地址模块601基于第一时钟信号的上升沿驱动，第二命令/地址模块602基于第三时钟信号的上升沿驱动，导通的第一命令/地址模块601或第二命令/地址模块602基于初始命令/地址信号和第二参考信号的比较结果，生成命令/地址信号。
在一个例子中，若初始命令/地址信号的电平大于等于第二参考信号，生成的命令/地址信号为高电平，若初始命令/地址信号的电平小于第二参考信号，生成的命令/地址信号为低电平。
对于上述提及的第一参考信号和第二参考信号，在一些实施例中，第一参考信号和第二参考信号可基于同一参考电平设置；在另一些实施例中，第一参考信号和第二参考信号的参考电平可以设置为不同电平。
需要说明的是，本实施例以第一时钟信号(第一振荡信号)和第三时钟信号(第三振荡信号)控制命令/地址信号的输出为例进行具体说明，在一些实施例中，命令/ 地址信号的输出可以基于第二时钟信号和第四时钟信号的控制。
本实施例通过片上系统产生四相位的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号，假设第一振荡信号的频率约为1600MHz，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号采样后获取的数据速率约为6400Mbps，地址/命令信号基于第一振荡信号和第三振荡信号采样后，获取的地址/命令信号的速率约为3200Mbps，实现了以较低频率的时钟信号进行高速数据的处理；另外，由于数据仅基于上升沿和下降沿的其中一者进行采样，时钟信号的占空比对读操作和写操作的眼图影响较小，且无需在进行时钟信号的同步，有利于后续对存储器读写速率的提升。
需要说明的是，上述实施例所提供的存储器的时钟架构中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的存储器的时钟架构实施例。
本公开另一实施例提供一种存储器，基于上述实施例提供的存储器时钟结构构建，以输出数据信号以及命令/地址信号，通过低速时钟信号完成高速数据处理的同时，避免时钟信号的同步以及占空比对存储器读写的影响。
具体地，通过片上系统产生四相位的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号，假设第一振荡信号的频率约为1600MHz，基于第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号采样后获取的数据速率约为6400Mbps，地址/命令信号基于第一振荡信号和第三振荡信号采样后，获取的地址/命令信号的速率约为3200Mbps，实现了以较低频率的时钟信号进行高速数据的处理；另外，由于数据仅基于上升沿和下降沿的其中一者进行采样，时钟信号的占空比对读操作和写操作的眼图影响较小，且无需在进行时钟信号的同步，有利于后续对存储器读写速率的提升。
在一些例子中，存储器可以是基于半导体装置或组件的存储单元或装置。例如，存储器装置可以是易失性存储器，例如动态随机存取存储器DRAM、同步动态随机存取存储器SDRAM、双倍数据速率同步动态随机存取存储器DDR SDRAM、低功率双倍数据速率同步动态随机存取存储器LPDDR SDRAM、图形双倍数据速率同步动态随机存取存储器GDDR SDRAM、双倍数据速率类型双同步动态随机存取存储器DDR2 SDRAM、双倍数据速率类型三同步动态随机存取存储器DDR3 SDRAM、双倍数据速率第四代同步动态随机存取存储器DDR4 SDRAM、晶闸管随机存取存储器TRAM等；或者可以是非易失性存储器，例如相变随机存取存储器PRAM、磁性随机存取存储器MRAM、电阻式随机存取存储器RRAM等。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描 述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的存储器的时钟架构及存储器中，通过片上系统产生四相位的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号，实现了以较低频率的时钟信号进行高速数据的处理；另外，由于数据仅基于上升沿和下降沿的其中一者进行采样，时钟信号的占空比对读操作和写操作的眼图影响较小，且无需在进行时钟信号的同步，有利于后续对存储器读写速率的提升。

Claims (15)

  1. 一种存储器的时钟架构，包括：
    片上系统，被配置为，产生频率和幅值相同的第一振荡信号、第二振荡信号、第三振荡信号和第四振荡信号；
    其中，所述第一振荡信号和所述第二振荡信号的相位相差90°，所述第一振荡信号和所述第三振荡信号的相位相差180°，所述第一振荡信号和所述第四振荡信号的相位相差270°；
    存储芯片，被配置为，基于所述第一振荡信号、所述第二振荡信号、所述第三振荡信号和所述第四振荡信号的信号沿输出数据信号，所述存储芯片还被配置为，基于所述第一振荡信号和所述第三振荡信号的信号沿输出命令/地址信号；所述信号沿为上升沿或下降沿。
  2. 根据权利要求1所述的存储器的时钟架构，其中，所述片上系统，包括：
    振荡产生单元，用于产生初始振荡信号；
    信号产生模块，连接振荡产生单元，被配置为，基于所述初始振荡信号，产生所述第一振荡信号、所述第二振荡信号、所述第三振荡信号和所述第四振荡信号。
  3. 根据权利要求2所述的存储器的时钟架构，其中，所述信号产生模块，包括：
    鉴相器，被配置为，检测所述初始振荡信号和压控振荡器的输出信号的相位差，并将所述相位差转换为初始电压信号输出；
    低通滤波器，连接所述鉴相器，被配置为，对所述初始电压信号滤波以生成控制电压信号；
    所述压控振荡器，连接所述低通滤波器，被配置为，基于所述控制电压信号，调节生成的所述第一振荡信号、所述第二振荡信号、所述第三振荡信号和所述第四振荡信号的频率；
    反馈分频器，连接所述压控振荡器和所述鉴相器，被配置为，将所述第一振荡信号的频率调节N倍后输入所述鉴相器，所述N为正数。
  4. 根据权利要求3所述的存储器的时钟架构，其中，所述压控振荡器，包括：
    第一反相器，输入端连接第四反相器的输出端，输出端连接第二反相器的输入端；
    所述第二反相器的输入端用于输出所述第三振荡信号和所述第四振荡信号的其中一者，输出端用于输出所述第一振荡信号和所述第二振荡信号的其中一者；
    第三反相器，输入端连接所述第二反相器的输出端，输出端连接所述第四反相器的输入端；
    所述第四反相器的输入端用于输出所述第三振荡信号和所述第四振荡信号的另外一者，输出端用于输出所述第一振荡信号和所述第二振荡信号的另外一者；
    第五反相器，输入端连接所述第四反相器的输出端，输出端连接所述第二反相器的输入端；
    第六反相器，输入端连接所述第二反相器的输出端，输出端连接所述第四反相器的输 入端；
    第七反相器，输入端连接所述第三反相器的输出端，输出端连接所述第一反相器的输入端；
    第八反相器，输入端连接所述第一反相器的输出端，输出端连接所述第三反相器的输入端。
  5. 根据权利要求2所述的存储器的时钟架构，其中，所述片上系统，还包括：
    第一分频器，连接所述信号产生模块，被配置为，将所述初始振荡信号的频率调节R倍后输入所述信号产生模块，所述R为正数。
  6. 根据权利要求2所述的存储器的时钟架构，其特征在于，所述片上系统，还包括：
    第二分频器，连接所述信号产生模块，被配置为，将所述第一振荡信号、所述第二振荡信号、所述第三振荡信号和所述第四振荡信号的频率调节O倍后输出，所述O为正数。
  7. 根据权利要求1所述的存储器的时钟架构，其中，所述存储芯片，包括：
    信号转换模块，被配置为，调节所述第一振荡信号、所述第二振荡信号、所述第三振荡信号和所述第四振荡信号的幅值，以生成相应的第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    第一控制模块，连接所述信号转换模块，被配置为，基于所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的信号沿，采样初始数据信号，以输出数据信号；
    第二控制信号，连接所述信号转换模块，被配置为，基于所述第一时钟信号和所述第三时钟信号的信号沿，采样初始命令/地址信号，以输出命令/地址信号。
  8. 根据权利要求7所述的存储器的时钟架构，其中，所述信号转换模块，包括：
    第一驱动器，被配置为，基于所述第一振荡信号和所述第三振荡信号产生所述第一时钟信号和所述第三时钟信号；
    第二驱动器，被配置为，基于所述第二振荡信号和所述第四振荡信号产生所述第二时钟信号和所述第四时钟信号。
  9. 根据权利要求8所述的存储器的时钟架构，其中，所述第一驱动器，包括：
    第一P型晶体管，栅极用于接收所述第三振荡信号，源极连接第三开关晶体管的漏极，漏极连接第一N型晶体管的漏极；
    第二P型晶体管，栅极用于接收所述第一振荡信号，源极连接所述第三开关晶体管的漏极，漏极连接第二N型晶体管的漏极；
    所述第一N型晶体管的栅极连接第四开关晶体管的漏极，且连接所述第一P型晶体管的漏极，源极接地；
    所述第二N型晶体管的栅极连接所述第四开关晶体管的漏极，源极接地，漏极连接输出传输线；
    所述第三开关晶体管的栅极用于接收使能信号，源极用于接收电源电压；
    所述第四开关晶体管的栅极用于接收所述使能信号，源极接地；
    所述输出传输线用于输出所述第三时钟信号，且所述输出传输线通过输出反相器输出 所述第一时钟信号。
  10. 根据权利要求8所述的存储器的时钟架构，其中，所述第一驱动器，还包括：
    第一开关晶体管，栅极用于接收所述使能信号，源极用于接收所述电源电压，漏极连接第一调整晶体管的源极；
    所述第一调整晶体管的栅极用于接收第一调整信号，漏极连接所述第三开关晶体管的漏极；
    第二开关晶体管，栅极用于接收所述使能信号，源极用于接收所述电源电压，漏极连接第二调整晶体管的源极；
    所述第二调整晶体管的栅极用于接收第二调整信号，漏极连接所述第三开关晶体管的漏极。
  11. 根据权利要求9或10所述的存储器的时钟架构，其中，所述第一驱动器，还包括：
    第一复位晶体管，栅极用于接收第一复位信号，源极用于接收电源电压，漏极连接所述输出传输线；
    第二复位晶体管，栅极用于接收第二复位信号，源极接地，漏极连接所述输出传输线。
  12. 根据权利要求7所述的存储器的时钟架构，其特征在于，所述信号转换模块，包括：
    第一驱动器，被配置为，基于所述第一振荡信号产生所述第一时钟信号；
    第二驱动器，被配置为，基于所述第二振荡信号产生所述第二时钟信号；
    第三驱动器，被配置为，基于所述第三振荡信号产生所述第三时钟信号；
    第四驱动器，被配置为，基于所述第四振荡信号产生所述第四时钟信号。
  13. 根据权利要求7所述的存储器的时钟架构，其中，所述第一控制模块，包括：
    第一数据模块，用于接收所述初始数据信号、第一参考信号和所述第一时钟信号，被配置为，基于所述第一时钟信号的信号沿，比较所述初始数据信号和所述第一参考信号，以生成所述数据信号；
    第二数据模块，用于接收所述初始数据信号、所述第一参考信号和所述第二时钟信号，被配置为，基于所述第二时钟信号的信号沿，比较所述初始数据信号和所述第一参考信号，以生成所述数据信号；
    第三数据模块，用于接收所述初始数据信号、所述第一参考信号和所述第三时钟信号，被配置为，基于所述第三时钟信号的信号沿，比较所述初始数据信号和所述第一参考信号，以生成所述数据信号；
    第四数据模块，用于接收所述初始数据信号、所述第一参考信号和所述第四时钟信号，被配置为，基于所述第四时钟信号的信号沿，比较所述初始数据信号和所述第一参考信号，以生成所述数据信号。
  14. 根据权利要求7所述的存储器的时钟架构，其中，所述第二控制模块，包括：
    第一命令/地址模块，用于接收所述初始命令/地址信号、第二参考信号和所述第一时钟信号，被配置为，基于所述第一时钟信号的信号沿，比较所述初始命令/地址信号和所 述第二参考信号，以生成所述命令/地址信号；
    第二命令/地址模块，用于接收所述初始命令/地址信号、所述第二参考信号和所述第三时钟信号，被配置为，基于所述第三时钟信号的信号沿，比较所述初始命令/地址信号和所述第二参考信号，以生成所述命令/地址信号。
  15. 一种存储器，基于权利要求1～14任一项所述的存储器的时钟架构构建，以输出数据信号以及命令/地址信号。
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