WO2024044906A1

WO2024044906A1 - Vacuum-encapsulated semiconductor chip and manufacturing method therefor

Info

Publication number: WO2024044906A1
Application number: PCT/CN2022/115575
Authority: WO
Inventors: 罗志鹏
Original assignee: 华为技术有限公司
Priority date: 2022-08-29
Filing date: 2022-08-29
Publication date: 2024-03-07

Abstract

The present application relates to the technical field of vacuum encapsulation, and provides a vacuum-encapsulated semiconductor chip and a manufacturing method therefor, for use in solving the problems in the prior art that vacuum micro-nano-electronic tubes have leakage currents on substrates thereof and cannot be integrally manufactured. The semiconductor chip comprises at least one semiconductor device. The semiconductor device comprises a substrate, a plurality of insulating supporting portions, a cathode structure, and an anode structure. The plurality of insulating supporting portions are arranged in a same layer and are arranged on the substrate at intervals. The cathode structure is arranged on at least one of the insulating supporting portions. A part of the anode structure is arranged on an insulating supporting portion, and the other part of the anode structure is suspended above the cathode structure, so that a vacuum gap is formed between the anode structure and the cathode structure. Because the anode structure is designed to be suspended above the cathode structure, part of the anode structure can be vacuum isolated from the substrate, thereby reducing the contact area between the anode structure and the substrate. Thus, the insulation of the semiconductor device is improved, and the leakage current on the substrate is reduced.

Description

Vacuum-encapsulated semiconductor chip and manufacturing method thereof

Technical field

The present application relates to the field of vacuum packaging technology, and in particular, to a vacuum-packaged semiconductor chip and a manufacturing method thereof.

Background technique

With the widespread application of semiconductor technology, higher performance and efficiency requirements have been put forward for semiconductor chips. Take vacuum electron tubes as an example. Vacuum electron tubes have good performance and efficiency, and can prepare nanoscale vacuum electronic structures through micro-nano processing technology to solve the problems of large size and high voltage.

A vacuum micro-nano electron tube in the related art includes a cathode and an anode, and there is an interelectrode vacuum channel between the cathode and the anode. Under the action of the electric field, electrons are emitted from the cathode and reach the anode through the interelectrode vacuum channel, thereby forming an electric current. The electrons form ballistic transport during conduction in the interpolar vacuum channel, which does not reduce efficiency due to collisions between electrons and atoms in semiconductors. Moreover, the nanoscale inter-electrode vacuum channel can significantly reduce the operating voltage of vacuum micro-nano electron tubes. At the same time, in the nanoscale inter-electrode vacuum channel, the number of gas particles is extremely small, which can reduce the requirements for vacuum packaging.

However, in the above-mentioned vacuum micro-nano electron tube, both the cathode and the anode need to be disposed on the substrate through a dielectric layer. Affected by parameters such as dielectric layer material, thickness, and manufacturing process, the dielectric layer cannot guarantee to provide excellent insulation properties for vacuum micro-nano electron tubes, resulting in a certain leakage current of vacuum micro-nano electron tubes on the substrate. Moreover, the inter-electrode vacuum channel in the vacuum micro-nano electron tube needs to be produced using processes such as electron beam lithography or ion beam etching. However, electron beam lithography or ion beam etching processes cannot be used for mass production and manufacturing, so vacuum micro-nano electron tubes cannot be integrated into the manufacturing process.

Contents of the invention

Embodiments of the present application provide a vacuum-encapsulated semiconductor chip and a manufacturing method thereof, which can solve the problem in the prior art that vacuum micro-nano electron tubes have leakage current on the substrate and cannot be integratedly manufactured.

In a first aspect, the present application provides a vacuum-encapsulated semiconductor chip. The semiconductor chip can be a discrete device, such as a vacuum diode, a vacuum triode, etc., or an integrated chip made of multiple discrete devices and vacuum-packaged, or a chip that is vacuum-packaged with other chips and circuits, such as It has functional chips such as power conversion and signal processing. A semiconductor chip includes one or more (multiple refers to two or more) semiconductor devices. The semiconductor device includes a substrate, a plurality of insulating supports, a cathode structure and an anode structure. Wherein, a plurality of insulating support parts are arranged on the substrate in the same layer and at intervals. The cathode structure is disposed on one or more insulating supports. Moreover, the cathode structure is only provided on part of the insulating support parts, not all of the insulating support parts. A part of the anode structure is disposed on one or more of the remaining insulating supports, and another part of the anode structure is disposed suspended above the cathode structure, so that a vacuum gap is formed between the anode structure and the cathode structure. Therefore, the semiconductor device is a vacuum semiconductor device (such as a vacuum electron tube). Moreover, by designing the anode structure to be suspended above the cathode structure, only part of the anode structure is disposed on the substrate through the insulating support part, and the remaining parts of the anode structure are spaced apart from the substrate. Therefore, some areas of the anode structure can be vacuum isolated from the substrate, reducing the contact area between the anode structure and the substrate. Therefore, the insulation of the semiconductor device is improved and the leakage current on the substrate is reduced. Moreover, the vacuum gap between the anode structure and the cathode structure can be formed by making a sacrificial layer using the existing complementary metal oxide semiconductor (COMS) process, thereby enabling the integrated production of vacuum-encapsulated semiconductor devices.

In some embodiments, the above-mentioned cathode structure includes a cathode array, and the cathode array is formed by an array arrangement of a plurality of electron emitting parts. Furthermore, the plurality of electron emission parts and the anode structure are arranged opposite to each other. A cathode array having a plurality of electron emitting parts has more electron emitting positions, thereby increasing the total current of the cathode structure. Moreover, the cathode structure has a small area and a compact structure.

Based on the cathode structure having a cathode array, in some embodiments, the cathode structure further includes a connecting portion, and the connecting portion is disposed on the insulating support portion. Furthermore, the connecting portion is connected to the plurality of electron-emitting portions in the cathode array, so that the cathode array is suspended above the substrate. The connection part can serve as a support structure for multiple electron emitting parts in the cathode array, so that the multiple electron emitting parts can be completely suspended on the substrate, thereby reducing the contact area between the cathode array and the substrate. The cathode array can be vacuum isolated from the substrate. As a result, the insulation of the semiconductor device is further improved and leakage problems are reduced.

The electron emitting part may emit electrons in a linear emission or angular emission manner. Therefore, the electron emitting part in the embodiment of the present application may be in a long strip shape, or may be in a shape composed of multiple circles or multiple rounded rectangles connected in sequence, or may be in a serpentine coiled shape, etc. All three shapes achieve line emission of electrons. In some embodiments, the above-mentioned electron emitting part may be in a shape composed of multiple triangles connected in sequence, and this shape can realize emitting electrons in an angular emission manner. Thus, different physical property requirements for cathode structures are met.

In addition, in some other embodiments of the present application, the above-mentioned cathode structure may also include only one electron emitting part. The electron emission part may be arranged in a serpentine shape above the substrate, and a part of the electron emission part may be arranged on the insulating support part. The electron-emitting part coiled in a serpentine shape has more emission sites and a larger emission current, and is suspended on the substrate and has less leakage current on the substrate. In addition, the electron emitting part may also be directly wound around an insulating support part.

In order to facilitate the production of the anode structure, in some embodiments of the present application, the above-mentioned semiconductor device includes an anode support part, and the anode support part is disposed between the insulating support part and the anode structure. When the anode structure is manufactured using a lift-off process, adding an anode support part can reduce the thickness of the anode structure that needs to be manufactured.

Moreover, in some embodiments, the above-mentioned anode support part and the cathode structure are made of the same layer and the same material. Therefore, the anode support part and the cathode structure can be manufactured through a patterning process, and the process flow is simple.

The semiconductor device in the above embodiment is a vacuum diode, and the semiconductor device in the embodiment of the present application can also be used to make a vacuum triode. In some embodiments, the above-mentioned semiconductor device further includes a gate structure, and the gate structure is disposed on the substrate. The gate structure is in the same layer as the cathode structure and is spaced apart, and is diffracted outside the cathode structure. Therefore, the semiconductor device is a vacuum triode. When a voltage is applied to the anode structure, an electric field is generated on the surface of the cathode structure, and electrons escape from the cathode structure and reach the anode structure through the vacuum gap, thereby forming an electric current. The electric field strength of the cathode structure can be modulated by applying different voltages to the gate structure in the vacuum triode. Thus, the emission intensity of the electron flow in the cathode structure is changed. Furthermore, the magnitude and switching of the current in the semiconductor device are controlled.

In some embodiments, the gate structure in the above-mentioned semiconductor device can also exchange positions with the cathode structure. In other words, the gate structure is suspended on the substrate, while the cathode structure is directly placed on the substrate.

Based on the structure of the semiconductor device in the above embodiments, in some embodiments of the present application, the semiconductor chip includes a plurality of semiconductor devices, and a plurality of semiconductor device arrays are arranged on the substrate. The semiconductor chip can produce multiple semiconductor devices with vertical cathode structures and anode structures on a substrate through existing CMOS processes, thereby improving the integration of vacuum-encapsulated semiconductor devices. Among them, the vacuum gap between the cathode structure and the anode structure in multiple vacuum-packaged semiconductor devices can be precisely controlled through the same atomic layer deposition (ALD) process.

In a second aspect, embodiments of the present application also include a method for manufacturing a vacuum-encapsulated semiconductor chip. The manufacturing method includes the following steps: obtaining a substrate with a cathode material layer, an insulating layer, and a substrate stacked sequentially from top to bottom. A cathode structure is formed on the layer of cathode material in the substrate. A sacrificial portion for supporting the suspended region of the anode structure is formed on the cathode structure and the insulating layer. An anode structure is formed above the sacrificial portion. The sacrificial part is removed to obtain a cathode structure, an anode structure suspended on the cathode structure, and a vacuum gap between the anode structure and the cathode structure. Partial areas of the insulating layer are removed to obtain multiple insulating support parts.

The manufacturing method of the embodiment of the present application can realize the manufacturing of the vacuum-encapsulated semiconductor chip in the above embodiment. Among them, by arranging the sacrificial part, the fabrication of the suspended anode structure and the fabrication of the vacuum gap between the anode structure and the cathode structure are realized.

In some embodiments, forming the sacrificial portion corresponding to the suspended area of the anode structure on the cathode structure and the insulating layer specifically includes: forming a first sacrificial layer on the layer where the cathode structure is located through a spin coating process and a polishing process. A second sacrificial layer is formed on the first sacrificial layer and the cathode structure through an atomic layer deposition process. A sacrificial portion for supporting the suspended region of the anode structure is formed on the second sacrificial layer through a photolithography process. The atomic layer deposition process can precisely control the material composition and morphology of the second sacrificial layer at the nanometer scale, thereby accurately controlling the vacuum gap between the anode structure and the cathode structure.

In some embodiments, removing a portion of the insulating layer to obtain a plurality of insulating support portions includes: removing a portion of the insulating layer below the cathode structure to obtain a suspended cathode structure.

In some embodiments, forming the cathode structure on the cathode material layer in the substrate specifically includes: forming the cathode structure and the anode support part on the cathode material layer in the substrate through a photolithography process. The cathode structure and the anode support part can be manufactured using the same photolithography process, and the process flow is simple.

The above-mentioned substrate can be obtained directly, or can be produced through special processing technology. Therefore, in some embodiments, the above-mentioned substrate is an SOI (silicon-on-insulator, silicon on insulating substrate) substrate. The SOI substrate can be obtained directly without using multiple processing techniques to manufacture, reducing the processing flow.

In other embodiments, the above-mentioned obtaining of a substrate having a cathode material layer, an insulating layer, and a substrate that are stacked sequentially from top to bottom specifically includes: obtaining the substrate. A gate structure is formed on the substrate. An insulating layer is formed above the substrate, above the gate structure and on the sidewalls. A layer of cathode material is formed on the insulating layer. The above manufacturing steps can first form a gate structure on the substrate, so that the vacuum triode can be manufactured.

Furthermore, forming the anode structure above the sacrificial part specifically includes: forming the anode structure above the sacrificial part through a lift-off process. The anode structure adopts a peel-off process, which can save the etching step and reduce the production cost of vacuum-encapsulated semiconductor chips.

Description of drawings

Figure 1 is a schematic three-dimensional structural diagram of a semiconductor chip according to an embodiment of the present application;

Figure 2 is a schematic cross-sectional view of a semiconductor chip in related art 1;

Figure 3 is a schematic three-dimensional structural diagram of a semiconductor device in a semiconductor chip according to an embodiment of the present application;

Figure 4 is a cross-sectional view along line A-A in Figure 3;

Figure 5 is a current-voltage characteristic diagram in a linear coordinate system in which the semiconductor device in the semiconductor chip of the embodiment of the present application is a vacuum micro-nano diode;

Figure 6 is a current-voltage characteristic diagram in a logarithmic coordinate system in which the semiconductor device in the semiconductor chip of the embodiment of the present application is a vacuum micro-nano diode;

7 is a schematic structural diagram of a cathode structure of a semiconductor device including multiple elongated electron emission parts in a semiconductor chip according to an embodiment of the present application;

8 is a schematic structural diagram of a semiconductor device having a cathode structure with multiple elongated electron emission parts in a semiconductor chip according to an embodiment of the present application;

Figure 9 is a schematic structural diagram of a cathode structure in which a semiconductor device in a semiconductor chip according to an embodiment of the present application includes a plurality of electron-emitting portions composed of a plurality of circles connected in sequence;

Figure 10 is a schematic structural diagram of a cathode structure in which a semiconductor device in a semiconductor chip according to an embodiment of the present application includes a plurality of electron-emitting portions composed of a plurality of rounded rectangles connected in sequence;

Figure 11 is a schematic structural diagram of a cathode structure in which a semiconductor device in a semiconductor chip according to an embodiment of the present application includes a plurality of electron-emitting portions composed of multiple triangles connected in sequence;

Figure 12 is a perspective view of a semiconductor device having multiple electron emitting parts arranged in a rectangular array in a semiconductor chip according to an embodiment of the present application;

Figure 13 is a perspective view of a semiconductor device having multiple electron emitting parts arranged in a circular array in a semiconductor chip according to an embodiment of the present application;

Figure 14 is a perspective view of a semiconductor device having a serpentine coiled electron emission portion integrally disposed on an insulating support portion in a semiconductor chip according to an embodiment of the present application;

Figure 15 is a perspective view of a semiconductor device having a serpentine coiled electron emission portion partially disposed on an insulating support portion in the semiconductor chip according to the embodiment of the present application;

Figure 16 is a schematic structural diagram of a semiconductor device with an anode support part in a semiconductor chip according to an embodiment of the present application;

Figure 17 is a schematic diagram of the B-B cross-section in Figure 16;

Figure 18 is a schematic structural diagram of a semiconductor device with an anode structure in which the area opposite to the cathode structure 2 is recessed downward in the semiconductor chip according to the embodiment of the present application;

Figure 19 is a schematic cross-sectional view of C-C in Figure 18;

Figure 20 is a schematic three-dimensional structural diagram of a semiconductor chip with multiple vacuum micro-nano diodes according to an embodiment of the present application;

Figure 21 is a top view of a semiconductor chip with multiple vacuum micro-nano diodes according to an embodiment of the present application;

(a), (b), (c), (d), (e), (f), and (g) in Figure 22 are respectively the manufacturing method of a semiconductor chip with multiple vacuum micro-nano diodes according to the embodiment of the present application. Structural diagrams corresponding to various process steps;

In Figure 23, (a), (b), (c), (d), and (e) are respectively various methods for manufacturing the first sacrificial portion in a semiconductor chip with multiple vacuum micro-nano diodes according to the embodiment of the present application. Structural diagram corresponding to the process steps;

Figure 24 is a schematic structural diagram of a semiconductor chip with an anode structure supported by a second sacrificial portion in an embodiment of the present application;

(a), (b), (c), (d), (e), (f), (g), and (h) in Figure 25 are semiconductor chips with multiple vacuum micro-nano diodes according to embodiments of the present application. Structural diagrams corresponding to various process steps in the second sacrificial part manufacturing method;

Figure 26 is a schematic three-dimensional structural diagram of a vacuum triode as the semiconductor device in the semiconductor chip according to the embodiment of the present application;

Figure 27 is a schematic diagram of the D-D cross-section in Figure 26;

Figure 28 is an output characteristic diagram of a vacuum micro-nano transistor in which the semiconductor device in the semiconductor chip according to the embodiment of the present application is at different gate voltages;

Figure 29 is a transfer characteristic diagram of a vacuum micro-nano transistor where the semiconductor device in the semiconductor chip according to the embodiment of the present application;

Figure 30 is a schematic cross-sectional view of a semiconductor device with a suspended cathode structure in a semiconductor chip according to an embodiment of the present application;

Figure 31 is a partial structural schematic diagram of a vacuum micro-nano triode with multiple circular electron-emitting parts in a semiconductor chip according to an embodiment of the present application;

Figure 32 is a partial structural schematic diagram of a vacuum micro-nano triode with multiple rounded rectangular electron emission parts in a semiconductor chip according to an embodiment of the present application;

Figure 33 is a partial structural schematic diagram of a vacuum micro-nano triode with multiple triangular electron-emitting parts in a semiconductor chip according to an embodiment of the present application;

Figure 34 is a partial structural schematic diagram of a vacuum micro-nano triode with a serpentine coiled electron emission part in a semiconductor chip according to an embodiment of the present application;

Figure 35 is a schematic three-dimensional structural diagram of a semiconductor chip with multiple vacuum micro-nano transistors according to an embodiment of the present application;

Figure 36 is a top view of a semiconductor chip with multiple vacuum micro-nano transistors according to an embodiment of the present application;

Figure 37 is a schematic cross-sectional view of a semiconductor chip in related art 2;

(a), (b), (c), (d), (e), (f), and (g) in Figure 38 are respectively the manufacturing method of a semiconductor chip with multiple vacuum micro-nano transistors according to the embodiment of the present application. Structural diagrams corresponding to various process steps;

(a), (b), (c), (d), (e), (f), (g), and (h) in Figure 39 are respectively semiconductor chips with multiple vacuum micro-nano transistors according to embodiments of the present application. Structural diagram corresponding to various process steps in the manufacturing method of the sacrificial part;

(a), (b), (c), (d), (e), (f), and (g) in Figure 40 are respectively the fabrication of the substrate in the semiconductor chip with multiple vacuum micro-nano transistors according to the embodiment of the present application. Structural diagram corresponding to various process steps in the method.

Reference signs:

1000-semiconductor chip, 100-semiconductor device, 1-substrate, 10-base, 01-dielectric layer, 2-cathode structure, 20-cathode material layer, 21-cathode array, 211-electron emission part, 22, 22a , 22b-connection part, 3-anode structure, 4-insulation support part, 40, 40a, 40b-insulation layer, 5-anode support part, 6-gate structure, 7-sacrificial part, 71-first sacrificial part, 72a-transitional sacrificial part, 72-second sacrificial part, 701, 701a-first sacrificial layer, 702-second sacrificial layer, 703-third sacrificial layer, 101, 102, 103-photoresist pattern.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application more clear, the technical solutions in this application will be clearly described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, and Not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description, embodiments, claims and drawings of this application are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating. Or suggestive order. "Connect", "connect" and other similar words are used to express the interconnection or interaction between different components, which can include direct connection or indirect connection through other components. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. , which may change accordingly according to changes in the orientation in which the components in the drawings are placed.

It should be understood that in this application, "at least one (item)" refers to one or more, and "plurality" refers to two or more. "And/or" is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, "A and/or B" can mean: only A exists, only B exists, and A and B exist simultaneously. , where A and B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ”, where a, b, c can be single or multiple.

Embodiments of the present application include a vacuum-encapsulated semiconductor chip. The semiconductor chip can be a discrete device, such as a vacuum diode, a vacuum triode, etc., or it can be an integrated chip made of multiple discrete devices and vacuum-packaged, or it can be a chip mold that is vacuum-packaged with other chips and circuits. Groups, such as functional element chips with power conversion, signal processing, etc. As a discrete device, the semiconductor chip of the embodiment of the present application may include only one semiconductor device. As an integrated circuit chip, the semiconductor chip in the embodiment of the present application includes multiple semiconductor devices.

Take the semiconductor device in the semiconductor chip shown in Figure 1 as a vacuum electron tube as an example. The structure of the semiconductor device 100 according to the embodiment of the present application, the semiconductor device 100 includes a substrate 1, a cathode structure 2 and an anode structure 3. Among them, the substrate 1 can be any one of intrinsic semiconductor material, reverse PN junction or insulating material. Both the cathode structure 2 and the anode structure 3 can be made of any one of single crystal silicon, metal materials, N-type semiconductor materials, polycrystalline silicon, etc. In order to expand the one-way conduction characteristics of the semiconductor device 100 and ensure that electrons only escape from the cathode structure 2 , the work function or Fermi level can be adjusted by selecting appropriate electrode materials or doping the semiconductor electrode, thereby adjusting different cathode structures 2 The difficulty of electrons escaping increases the one-way conductivity of the semiconductor device 100 and reduces the operating voltage of the semiconductor device 100 .

In order to facilitate the following description, X, Y, and Z coordinate systems can be established in some drawings. The plane of the substrate 1 shown in Figure 1 can be an XY plane. Taking the substrate 1 shown in Figure 1 as a rectangle as an example, the X axis can be the length direction of the substrate 1, and the Y axis can be the length direction of the substrate 1. In the width direction, the Z-axis is perpendicular or approximately perpendicular to the substrate 1 within the manufacturing tolerance range. It can be understood that the width dimension of the substrate 1 is smaller than the length dimension of the substrate 1 .

As shown in Figure 2, if the cathode structure 2 and the anode structure 3 are arranged on the same layer and are both arranged on the substrate 1 through the dielectric layer 01, the dielectric layer will be affected by the material, thickness, manufacturing process and other parameters of the dielectric layer 01. Layer 01 cannot guarantee good insulation properties between cathode structure 2, anode structure 3 and substrate 1. Therefore, the cathode structure 2 and the anode structure 3 will have a certain leakage current on the substrate 1 .

In order to solve this problem, the semiconductor device 100 in the embodiment of the present application also includes a plurality of insulating support parts 4 as shown in FIG. 3 . The plurality of insulating support parts 4 are arranged in the same layer and spaced apart on the substrate 1 . The insulating support part 4 can be made of SiO ₂ material. The above-mentioned cathode structure 2 is provided on one or more of the above-mentioned insulating supports 4 . Moreover, the cathode structure 2 is only provided on some of the above-mentioned insulating support parts 4 , rather than on all of the insulating support parts 4 . A part of the anode structure 3 is disposed on the remaining part of the insulating support part 4 as the support area of the anode structure 3 . Another part of the anode structure 3 is suspended above the cathode structure 2, so that a vacuum gap δ as shown in Figure 4 is formed between the anode structure 3 and the cathode structure 2. The anode structure 3 and the cathode structure 2 are vertical structures. The cathode structure 2 is grounded, and when a positive voltage is applied to the anode structure 3, a certain electric field is generated on the surface of the cathode structure 2. When the electric field is strong enough, electrons escape from the cathode structure 2 and reach the anode structure 3 to generate current. Thus, the function of a vacuum electron tube is realized.

Therefore, after the semiconductor chip 1000 is vacuum-packaged, only part of the anode structure 3 is disposed on the substrate 1 through the insulating support part 4 , and other parts of the anode structure 3 are suspended above the cathode structure 2 . Therefore, the partial area provided in the air on the anode structure 3 can be isolated from the substrate 1 by vacuum, thereby reducing the contact area between the anode structure 3 and the substrate 1 . The insulating properties of vacuum are better than those of dielectric layer 01. Therefore, the insulation performance of the semiconductor device 100 can be improved, and the leakage current on the substrate 1 can be reduced.

Moreover, the plurality of insulating support portions 4, cathode structures 2 and anode structures 3 in the semiconductor device 100 in the embodiment of the present application can all be integrated and manufactured using the existing COMS process. Moreover, the vertical structure of the anode structure 3 and the cathode structure 2 can enable more semiconductor devices 100 to be integrated on the same area of the substrate 1, thereby increasing the integration level of the semiconductor chip 1000. Among them, the suspended anode structure 3 can be formed by making a sacrificial layer. Therefore, the semiconductor device 100 can be manufactured at the nanoscale, that is, the semiconductor device 100 is a vacuum micro-nano electron tube. Among them, the vacuum micro-nano electron tube having only the cathode structure 2 and the anode structure 3 is a vacuum micro-nano diode.

Figure 5 shows the current-voltage relationship of a vacuum micro-nano diode in linear coordinates. Figure 6 shows the current-voltage relationship of a vacuum micro-nano diode in logarithmic coordinates. It can be seen from Figure 5 that in linear coordinates, the relationship between the current and voltage of the vacuum micro-nano diode is super linear. As can be seen from Figure 6, in logarithmic coordinates, the relationship between current and voltage is between the exponential relationship and the linear straight-line relationship.

In addition, the above-mentioned cathode structure 2 may be directly disposed on the substrate as shown in FIG. 3 , or may be disposed partially on the substrate 1 as shown in FIG. 7 . Therefore, the cathode structure 2 shown in Figure 7 is suspended on the substrate 1, which reduces the contact area between the cathode structure 2 and the substrate 1. The cathode structure 2 can also be isolated from the substrate 1 in a vacuum. Therefore, the insulation of the semiconductor device 100 is further improved and leakage problems are reduced.

Moreover, the cathode structure 2 in the above-mentioned vacuum micro-nano electron (diode) tube can be made into a variety of structures. By changing the shape of the cathode structure 2, the accumulation of the electric field in the cathode structure 2 can be changed, thereby changing the electrical properties of the semiconductor device 100. performance. This application does not limit this. The cathode structure 2 is suspended on the substrate 1 for illustration below.

In some embodiments, as shown in FIG. 7 , the cathode structure 2 includes a cathode array 21 , and the cathode array 21 is formed by an array arrangement of a plurality of electron emitting parts 211 . Furthermore, the plurality of electron emission parts 211 and the anode structure 3 are arranged opposite to each other. The cathode array 21 having multiple electron emitting parts 211 has a longer side length and more electron emitting positions, thereby increasing the total current of the cathode structure 2 . Moreover, the cathode structure 2 has a small area, compact structure, and high processing output.

Moreover, in some examples, the above-mentioned cathode structure 2 further includes a connection part 22 as shown in FIG. 7 , and the connection part 22 is connected to the plurality of electron emission parts 211 in the cathode array 21 . Moreover, the connection part 22 is directly provided on the insulating support part 4, and the connection part 22 can be used as a support structure of the cathode structure 2, as shown in Figure 8, so that the plurality of electron emission parts 211 in the cathode array 21 are suspended on the substrate. above 1. Therefore, the plurality of electron emission parts 211 can be completely suspended on the substrate 1 , thereby reducing the contact area between the cathode structure 2 and the substrate 1 . The plurality of electron emission parts 211 may be vacuum isolated from the substrate 1 . Therefore, the insulation of the semiconductor device 100 is further improved and leakage problems are reduced.

The electron emission part 211 in the above-mentioned cathode array 21 can be designed to have a shape with sharp edges and corners, so that electrons can easily escape from the cathode structure 2 . The electron emitting part 211 can emit electrons in a linear emission or angular emission manner, which can be selected according to actual electron emission requirements.

Therefore, the electron emission part 211 may be in a long strip shape as shown in FIG. 8 , or may be in a shape composed of a plurality of circles connected in sequence as shown in FIG. 9 , or may be in a shape of a plurality of circles as shown in FIG. 10 . The shape formed by connecting rounded rectangles in sequence can also be a shape formed by connecting multiple triangles in sequence as shown in Figure 11. The electric field is more easily concentrated at the corners of the triangle, resulting in higher electron emission efficiency. Furthermore, the plurality of electron emission parts 211 may be distributed in parallel and spaced apart. The plurality of electron emission parts 211 shown in FIGS. 8 to 10 are all arranged at intervals along the direction of the X-axis. Correspondingly, the cathode structure 2 may include two

connection parts

22a and 22b, which are respectively provided at both ends of the plurality of electron emission parts 211. One connection part 22a is connected to one end of the plurality of electron emitting parts 211, and the other connection part 22b is connected to the other ends of the plurality of electron emitting parts 211. In addition, the plurality of electron emission parts 211 in the above-mentioned cathode array 21 may also be distributed in other forms. For example, the plurality of electron emission parts 211 shown in FIG. 12 are distributed in a rectangular array. As another example, the plurality of electron emission parts 211 shown in FIG. 13 are distributed in a rectangular array and a circular array. Furthermore, in FIGS. 12 and 13 , the cathode structure 2 has a plurality of connecting portions 22 , and the plurality of connecting portions 22 respectively connect two adjacent electron emission portions 211 . This application does not limit the distribution form of the plurality of electron emission parts 211 . In other embodiments, the above-mentioned cathode structure 2 only includes one electron emission part 211, and the electron emission part 211 may adopt a shape with more emission sites. For example, the electron emission portion 211 has various shapes such as a serpentine coil. The electron emission part 211 shown in FIG. 14 has a rectangular shape and is extended and coiled in the width direction of the substrate 1 . In addition, the electron emission part 211 may also be coiled on the substrate 1 from the inside to the outside in a circular shape. This application does not limit this.

Furthermore, the electron-emitting part 211 coiled in a serpentine shape may be integrally disposed on the insulating support part 4, as shown in FIG. 14 . Alternatively, since the size of the electron emission part 211 is relatively large, as shown in FIG. 15 , a part of the electron emission part 211 may be provided on the insulating support part 4 as a support point. Therefore, other partial areas of the electron emission part 211 can be suspended on the substrate 1 , which can also reduce the leakage current on the substrate 1 .

The above mainly describes the structure of the cathode structure 2, and the anode structure 3 in the embodiment of the present application will be described below. In some embodiments, the anode structure 3 can be made into an approximate "gate" shape as shown in FIG. 15 . The surface of the anode structure 3 is flat, the electric field is uniform and small in value, and it is difficult for electrons to escape, so no current will be generated.

Moreover, the above-mentioned anode structure 3 can be manufactured using a peel-off process. Since the anode structure 3 is directly fabricated on the insulating support part 4, the thickness of the anode structure 3 that needs to be fabricated is relatively large. Therefore, in some embodiments of the present application, the semiconductor device 100 includes the anode support 5 as shown in FIGS. 16 and 17 , and the anode support 5 is disposed between the insulating support 4 and the anode structure 3 . When the anode structure 3 is made on the anode support part 5 through a peel-off process, the thickness of the anode structure 3 that needs to be made is smaller, thereby saving material.

Moreover, in some embodiments, the above-mentioned anode support part 5 and the cathode structure 2 are made of the same layer and the same material. The anode support part 5 and the cathode structure 2 are made through a patterning process, and the process flow is simple. In some embodiments of the present application, the patterning process may include a photolithography process, or include a photolithography process and an etching step; the photolithography process may refer to a process using photolithography including film formation, exposure, development, etc. Glue, mask, exposure machine, etc. are used to form patterns. The corresponding patterning process can be selected according to the structure formed in this application.

Among them, the one-time patterning process in the embodiment of the present application is to form different exposure areas through a mask exposure process, and then perform multiple etching, ashing and other removal processes on the different exposure areas to finally obtain the expected pattern. instructions.

"Same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process. Depending on the specific pattern, the same patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.

In addition, in addition to the shape shown in FIG. 17 , the anode structure 2 may also be designed to be recessed downward only in the area opposite to the cathode structure 2 , as shown in FIGS. 18 and 19 . This application does not limit this.

The above only describes the structure of a single semiconductor device 100. In some embodiments of the present application, as shown in Figures 20 and 21, the semiconductor chip 1000 includes a plurality of the above-mentioned semiconductor devices 100 configured as vacuum diodes, and an array of multiple semiconductor devices 100 arranged on substrate 1. Multiple semiconductor devices 100 in the semiconductor chip 1000 can be integrated and manufactured using the existing COMS process, and have better dimensional consistency, higher production efficiency, higher output and higher lifespan. Therefore, the semiconductor chip 1000 can integrate higher density semiconductor devices 100 on the same area of the substrate 1, and the integration level is high, which increases the total current of the semiconductor chip 1000.

It should be noted that the semiconductor chip 1000 having a plurality of the above vacuum diodes can be manufactured using the following manufacturing method. As shown in Figure 22, the production method includes the following steps:

S100: Obtain the substrate 10 with the cathode material layer 20, the insulating layer 40 and the substrate 1 stacked in sequence from top to bottom.

For example, as shown in (a) of FIG. 22 , the substrate 10 can be obtained directly. For example, if the substrate 10 is an SOI substrate, the processing flow can be reduced. The material of the cathode material layer 20 and the material of the substrate 1 are both single crystal silicon, and the insulating layer 40 is an oxide layer. For example, the oxide layer is SiO ₂ material.

S200: Form the cathode structure 2 on the cathode material layer 20 in the substrate 10.

For example, as shown in (b) and (c) in FIG. 22 , the cathode structure 2 is formed on the cathode material layer 20 in the substrate 10 through a photolithography process. As shown in (b) of FIG. 22 , a photoresist pattern 101 may be first formed on the cathode material layer 20 in the substrate 10 by dry etching. Afterwards, as shown in (c) of FIG. 22 , the photoresist pattern 101 is transferred to the cathode material layer 20 to form the cathode structure 2 .

It should be noted that if it is necessary to manufacture the semiconductor chip 1000 with the anode support part 5, the cathode structure 2 can be formed simultaneously on the cathode material layer 20 in the substrate 10 through the same photolithography process as shown in FIG. 22(c) and anode support part 5.

S300: Form the sacrificial portion 7 for supporting the suspended area of the anode structure 3 on the cathode structure 2 and the insulating layer 40.

For example, as shown in (d) of FIG. 22 , a sacrificial portion 7 for supporting the suspended region of the anode structure 3 can be formed on the cathode structure 2 and the insulating layer 40 through multiple processes.

S400: Form the anode structure 3 above the sacrificial part 7.

For example, the anode structure 3 as shown in (e) in FIG. 22 can be formed above the sacrificial part 7 through a lift-off process. The anode structure 3 is manufactured using a peel-off process, which can save the etching step and reduce the manufacturing cost of the vacuum-encapsulated semiconductor chip 1000.

S500: Remove the sacrificial part 7 to obtain the cathode structure 2, the anode structure 3 suspended on the cathode structure 2, and the vacuum gap δ between the anode structure 3 and the cathode structure 2.

For example, as shown in (f) of FIG. 22 , the sacrificial portion 7 can be removed through an etching process. Thereby, the cathode structure 2, the anode structure 3 suspended on the cathode structure 2, and the vacuum gap δ between the anode structure 3 and the cathode structure 2 are obtained.

S600: Form a plurality of insulating support portions 4 on the insulating layer 40 in the substrate 10.

For example, as shown in (g) of FIG. 22 , part of the insulating layer 40 may be removed through an etching process. Thereby, a plurality of insulating support portions 4 are obtained. At the same time, during the etching process, a portion of the insulating layer 40 located below the cathode structure 2 can also be removed, thereby obtaining the cathode structure 2 arranged in the air.

In some embodiments, as shown in Figure 23, the above S300 specifically includes:

S301: Form the first sacrificial layer 70 on the layer where the cathode structure 2 is located through a spin coating process and a polishing process.

For example, as shown in FIG. 23(a) , the first sacrificial layer 701a is first formed on the layer where the cathode structure 2 is located through a spin coating process. The first sacrificial layer 701a can completely fill the gaps between the plurality of electron emission parts 211 in the cathode structure 2, and the upper surface of the first sacrificial layer 701a is higher than the cathode structure 2. The first sacrificial layer 701a can be made of SiN material.

After that, the first sacrificial layer 701a can be planarized through a chemical mechanical polishing process, and the top surfaces of the cathode structure 2 and the anode support 5 can be exposed to obtain the first sacrificial layer 701 as shown in (b) of FIG. 23 .

S302: Form the second sacrificial layer 702 on the first sacrificial layer 701 and the cathode structure 2 through an atomic layer deposition process.

For example, as shown in (c) of FIG. 23 , the second sacrificial layer 702 may be formed on the cathode structure 2 and the first sacrificial layer 701 through an atomic layer deposition process. Specifically, the material of the second sacrificial layer 702 may also be SiN material. The atomic layer deposition process can precisely control the material composition and morphology of the second sacrificial layer 702 on the nanometer scale, thereby accurately controlling the size of the vacuum gap δ between the anode structure 3 and the cathode structure 2 .

It should be noted that only the first sacrificial layer 701 and the second sacrificial layer 702 need to be formed, which can be used to fabricate the anode structure 3 with an approximately "gate"-shaped cross section. As for the anode structure 3 which has a "gate" shape in cross section and is recessed downward in the area opposite to the cathode structure 2, as shown in (a) to (d) in Figure 25, in addition to making the first sacrificial layer 701 and the For the second sacrificial layer 702, it is also necessary to form a third sacrificial layer 703 on the second sacrificial layer 702. The third sacrificial material layer 703 may specifically be SiO ₂ .

S303: Form the sacrificial portion 7 for supporting the suspended area of the anode structure 3 on the second sacrificial layer 702 through a photolithography process.

For example, in some embodiments, as shown in (d) of FIG. 23 , the photoresist pattern 102 may first be formed on the second sacrificial layer 702 by dry etching. Afterwards, as shown in (e) of FIG. 23 , the photoresist pattern 102 can be transferred to the second sacrificial layer 702 to form the sacrificial portion 7 . The sacrificial part 7 is used to support the anode structure 3 as shown in Figure 24.

In other embodiments, as shown in (e) of FIG. 25 , the photoresist pattern 102 may be first formed on the second sacrificial layer 702 and the third sacrificial layer 703 by dry etching. After that, as shown in (f) of FIG. 25 , the photoresist pattern 102 can be transferred to the second sacrificial layer 702 and the third sacrificial layer 703 to obtain the first sacrificial part 71 and the transition sacrificial part 72a. Then, as shown in (g) of FIG. 26 , a photoresist pattern 103 may be formed on the transition sacrificial portion 72 a by dry etching. Finally, as shown in (h) of FIG. 26 , the photoresist pattern 103 can be transferred to the transition sacrificial portion 72 a to obtain the second sacrificial portion 72 . The sacrificial part 7 having the first sacrificial part 71 and the second sacrificial part 72 is used to support the anode structure 3 as shown in (e) of FIG. 22 .

It should be noted that FIG. 22 , FIG. 23 , FIG. 24 and FIG. 25 only show the production of one semiconductor device in the semiconductor chip 1000 . It can be understood that the structures of each layer of the multiple semiconductor devices in the semiconductor chip 1000 can be fabricated simultaneously under the same process, and will not be described in detail here.

The above embodiments are all described by taking the semiconductor device 100 as a vacuum diode as an example. The semiconductor device 100 may also be a vacuum triode. Therefore, in some embodiments of the present application, the above-mentioned semiconductor device 100 further includes a gate structure 6 as shown in FIGS. 26 and 27 , and the gate structure 6 is disposed on the substrate 1 . Moreover, the gate structure 6 is in the same layer as the cathode structure 2 and is arranged at intervals, and is diffracted outside the cathode structure 2 . Thus, a vacuum three-stage tube is obtained.

When a voltage is applied to the anode structure 3, an electric field is generated on the surface of the cathode structure 2, and electrons escape from the cathode structure 2 and reach the anode structure 3 through the vacuum gap δ to form a current. In the above process, the intensity of the electron flow emitted by the cathode structure 2 can be changed by applying different voltages to the gate structure 6 to modulate the electric field intensity of the cathode structure 2 . Thereby, the magnitude and switching of the current in the semiconductor device 100 are controlled. The input voltage of the gate structure 6 should be between the input voltage of the cathode structure 2 and the input voltage of the anode structure 3 . The vacuum triode can also be made using existing CMOS technology to achieve nanoscale technology. Therefore, the vacuum triode is a vacuum micro-nano triode.

Figure 28 shows the output characteristics of the vacuum micro-nano triode. The gate voltages of line 1 to line 6 in Figure 28 are different. The gate voltage of line 1 is the largest, and the gate voltage of line 6 is the smallest. It can be seen from Figure 28 that the vacuum micro-nano triode has the following physical characteristics: the greater the voltage of the gate structure 6, the lower the voltage of the anode structure 3 required for the cathode structure 2 to emit electrons, and the faster the current of the cathode structure 2 increases. . Figure 29 shows the transfer characteristics of the vacuum micro-nano triode. It can be seen from Figure 29 that the vacuum micro-nano triode has the following physical characteristics: the greater the voltage of the gate structure 6, the greater the current of the cathode structure 2.

It should be noted that in some embodiments, as shown in FIG. 27 , the above-mentioned cathode structure 2 is directly disposed on the substrate 1 . The gate structure 6 is suspended on the substrate 1 and is provided in the same layer and material as the anode support 5 . In other embodiments, the above-mentioned gate structure 6 may be interchanged with the cathode structure 2 . As shown in FIG. 30 , the gate structure 6 is directly provided on the substrate 1 . The cathode structure 2 is suspended on the substrate 1 and is of the same layer and material as the anode support part 5 . This application does not limit this.

Moreover, as shown in FIGS. 31 to 34 , the structure and shape of the cathode structure 2 in the above-mentioned vacuum triode may be similar to the structure and shape of the cathode structure 2 in the vacuum diode. FIG. 31 shows that the cathode structure 2 in the vacuum triode includes a plurality of circular electron-emitting parts 211. FIG. 32 shows that the cathode structure 2 in the vacuum triode includes a plurality of rounded rectangular electron emission parts 211 . FIG. 33 shows that the cathode structure 2 in the vacuum triode includes a plurality of triangular electron-emitting parts 211. Figure 34 shows that the cathode structure 2 in the vacuum triode includes a serpentine coiled electron emission part 211.

For the semiconductor device 100 with the above structure, in some embodiments of the present application, as shown in FIGS. 35 and 36 , the above semiconductor chip 1000 includes a plurality of the above semiconductor devices 100 configured as vacuum triodes, and the plurality of semiconductor devices 100 are arranged in an array. on substrate 1. Multiple semiconductor devices 100 in the semiconductor chip 1000 can be integrated and manufactured using the existing COMS process, and have better dimensional consistency, higher production efficiency, higher output and higher lifespan. Therefore, the semiconductor chip 1000 can integrate higher density semiconductor devices 100 on the same area of the substrate 1 , and the integration level is high, which increases the total current of the semiconductor chip 1000 .

Moreover, compared with the semiconductor device 100 shown in FIG. 37 , the anode structure 3 and the cathode structure 2 in the semiconductor device 100 are arranged on the same layer, and at the same time, tips for discharge are processed on the opposite surfaces of the anode structure 3 and the cathode structure 2 structure. Since the thickness of the cathode structure 2 and the anode structure 3 is small (the thickness direction is the Z-axis direction in FIG. 37), it is more difficult to process the tip structure. However, the cathode structure 2 and the anode structure 3 in the semiconductor device 100 in the embodiment of the present application do not need to be finely processed on their own sides, and the processing difficulty is relatively low.

It should be noted that the semiconductor chip 1000 in the embodiment of the present application may also include a plurality of the above-mentioned semiconductor devices 100 configured as vacuum triodes, and a plurality of the above-mentioned vacuum diodes. Moreover, the semiconductor chip 1000 may also include other semiconductor devices, which is not limited in this application.

In addition, embodiments of the present application also include a method of manufacturing a semiconductor chip 1000 having a plurality of the above vacuum triodes. (a) to (g) in FIG. 38 are schematic structural diagrams corresponding to various process steps in the manufacturing method of the semiconductor chip 1000 of the vacuum triode. (a) to (h) in FIG. 39 are schematic structural diagrams corresponding to various process steps of the sacrificial portion in the manufacturing method of the semiconductor chip 1000 of the vacuum triode. It can be seen from FIG. 38 and FIG. 39 that the manufacturing method of the semiconductor chip 1000 having multiple vacuum triodes is similar to the manufacturing method of the semiconductor chip 1000 having multiple vacuum diodes. The difference is that in the manufacturing method of the semiconductor chip 1000 having a plurality of the above-mentioned vacuum triodes, referring to FIG. 40, the above-mentioned step S100 specifically includes:

The above-mentioned S100 specifically includes:

S101: Obtain substrate 1.

For example, as shown in (a) of Figure 40, the substrate 1 can be a silicon substrate, and the upper surface 1a of the substrate 1 is heavily doped with N-type to ensure the conductivity of the upper surface of the silicon substrate 1. properties and a higher Fermi level.

S102: Form gate structure 6 on substrate 1.

For example, the gate structure 6 as shown in (b) of FIG. 40 can be formed on the substrate 1 through a photolithography process.

S103: Form an insulating layer 40 above the substrate 1, above the gate structure 6 and on the side walls.

For example, the insulating layer 40a as shown in (c) in FIG. 40 may be first formed on the substrate 1 having the gate structure 6 through a spin coating process. The insulation layer can be made of glass material. So, in other words, the insulating layer 40a is formed on the substrate 1 having the gate structure 6 using a spin on glass (SOG) method. The insulating layer 40a is thicker at the recesses (ie, on the substrate 1), while the insulating layer 40a is thinner at the protrusions (ie, on the gate structure 6).

Then, the insulating layer 40a on the substrate 1 can be thinned through an etching back process, while the insulating layer 40a on the gate structure 6 is retained, to obtain the insulating layer 40b as shown in (d) of FIG. 40 .

Afterwards, as shown in (e) of FIG. 40 , an atomic layer deposition process can be used to form an insulating layer 40 above and on the sidewalls of the gate structure 6 . Thus, the insulating layer 40 is formed above the substrate 1, above the gate structure 6, and on the side walls. Among them, the atomic layer deposition process can accurately control the thickness of the insulating layer 40 formed, thereby accurately controlling the gap between the gate structure 6 and the cathode structure 2 .

S104: Form the cathode material layer 20 on the insulating layer 40.

For example, as shown in (f) of FIG. 40 , the cathode material layer 20 can be first formed through a deposition process (such as a physical vapor deposition process or a chemical vapor deposition process). The cathode material layer 20 can completely fill the gap in the insulating layer 40 . Specifically, the cathode material layer 20 may be polysilicon material.

After that, the cathode material layer 20 can be planarized through a chemical mechanical polishing (CMP) process as shown in (g) of FIG. 40 , and the top surface of the gate structure 6 can be exposed. Thereby, the cathode material layer 20 is obtained.

Therefore, the substrate 10 having the cathode material layer 20, the insulating layer 40 and the substrate 1 stacked sequentially from top to bottom can be manufactured through the above-mentioned multi-channel CMOS process.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A vacuum-encapsulated semiconductor chip is characterized in that it includes at least one semiconductor device, and the semiconductor device includes:

substrate;

A plurality of insulating support parts in the same layer and spaced apart, the plurality of insulating support parts are all provided on the substrate;

a cathode structure, the cathode structure being disposed on at least one of the insulating supports;

An anode structure, a part of the anode structure is arranged on the insulating support part, and the other part of the anode structure is suspended above the cathode structure, so that a vacuum is formed between the anode structure and the cathode structure gap.
The vacuum-encapsulated semiconductor chip according to claim 1, wherein the cathode structure includes:

The cathode array is formed by an array arrangement of a plurality of electron emitting parts, and the plurality of electron emitting parts are arranged opposite to the anode structure.
The vacuum-encapsulated semiconductor chip according to claim 2, wherein the cathode structure further includes:

A connection part is provided on the insulating support part and is connected to a plurality of electron emission parts in the cathode array, so that the cathode array is suspended above the substrate.
The vacuum-encapsulated semiconductor chip according to claim 2 or 3, characterized in that the electron emission parts are all in a long strip shape, or are composed of any one of a plurality of triangles, a plurality of circles and a plurality of rounded rectangles. Connect the resulting shapes in sequence.
The vacuum-encapsulated semiconductor chip according to claim 1, wherein the cathode structure includes an electron-emitting part arranged in a serpentine coil, and a part of the electron-emitting part is arranged on the insulating support part.
The vacuum-encapsulated semiconductor chip according to any one of claims 1-5, wherein the semiconductor device includes:

An anode support part is provided between the insulating support part and the anode structure.
The vacuum-encapsulated semiconductor chip according to claim 6, wherein the cathode structure and the anode support part are in the same layer and made of the same material.
The vacuum-encapsulated semiconductor chip according to claims 1-7, wherein the semiconductor device further includes:

A gate structure is provided on the substrate; the gate structure is in the same layer and spaced apart from the cathode structure, and is diffracted outside the cathode structure.
The vacuum-encapsulated semiconductor chip according to any one of claims 1 to 8, characterized in that it includes a plurality of the semiconductor devices, and a plurality of the semiconductor device arrays are distributed on the substrate.
A manufacturing method for manufacturing the vacuum-encapsulated semiconductor chip according to any one of the above claims 1-9, characterized in that it includes the following steps:

Obtain a substrate with a cathode material layer, an insulating layer, and a substrate stacked sequentially from top to bottom;

forming a cathode structure on the cathode material layer in the substrate;

forming a sacrificial portion for supporting a suspended region of the anode structure on the cathode structure and the insulating layer;

forming an anode structure above the sacrificial part;

Remove the sacrificial part to obtain a cathode structure, an anode structure suspended on the cathode structure, and a vacuum gap between the anode structure and the cathode structure;

Partial areas of the insulating layer are removed to obtain a plurality of insulating support parts.
The method of manufacturing a vacuum-encapsulated semiconductor chip according to claim 10, wherein forming a sacrificial portion corresponding to the suspended region of the anode structure on the cathode structure and the insulating layer specifically includes:

Form a first sacrificial layer on the layer where the cathode structure is located through a spin coating process and a polishing process;

forming a second sacrificial layer on the first sacrificial layer and the cathode structure through an atomic layer deposition process;

A sacrificial portion for supporting the suspended region of the anode structure is formed on the second sacrificial layer through a photolithography process.
The method for manufacturing a vacuum-encapsulated semiconductor chip according to claim 10 or 11, wherein removing part of the insulating layer to obtain a plurality of insulating support parts includes:

A portion of the insulating layer located below the cathode structure is removed to obtain a suspended cathode structure.
The method for manufacturing a vacuum-encapsulated semiconductor chip according to claim 10 or 11, wherein forming a cathode structure on the cathode material layer in the substrate specifically includes:

A cathode structure and an anode support are formed on the cathode material layer in the substrate through a photolithography process.
The method for manufacturing a vacuum-encapsulated semiconductor chip according to any one of claims 10 to 13, wherein the substrate is an SOI substrate.
The method for manufacturing a vacuum-encapsulated semiconductor chip according to any one of claims 10 to 13, wherein the step of obtaining a substrate having a cathode material layer, an insulating layer, and a substrate that are stacked sequentially from top to bottom is specifically include:

Get the substrate;

forming a gate structure on the substrate;

forming an insulating layer above the substrate, above the gate structure and on the sidewalls;

A layer of cathode material is formed on the insulating layer.
The method for manufacturing a vacuum-encapsulated semiconductor chip according to any one of claims 10 to 15, wherein forming an anode structure above the sacrificial part specifically includes:

An anode structure is formed above the sacrificial part through a lift-off process.