CN108389907B - Transistor structure and manufacturing method thereof - Google Patents
Transistor structure and manufacturing method thereof Download PDFInfo
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- CN108389907B CN108389907B CN201810310318.8A CN201810310318A CN108389907B CN 108389907 B CN108389907 B CN 108389907B CN 201810310318 A CN201810310318 A CN 201810310318A CN 108389907 B CN108389907 B CN 108389907B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 106
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 106
- 239000010703 silicon Substances 0.000 claims abstract description 106
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 53
- 230000008569 process Effects 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 32
- 239000006227 byproduct Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000002074 nanoribbon Substances 0.000 description 20
- 238000010586 diagram Methods 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000002127 nanobelt Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention discloses a transistor structure, comprising: a semiconductor substrate; the channel layer protrudes upwards from the surface of the semiconductor substrate; the grid oxide layer and the grid electrode sequentially surround the side face and the top face of the channel layer; the source electrode and the drain electrode are respectively arranged at two ends of the channel layer on the semiconductor substrate; the channel layer is of a laminated structure formed by alternately arranging silicon strips with a first width and silicon strips with a second width in the vertical direction, and the source electrode and the drain electrode are provided with source-drain silicon strip laminated structures corresponding to all layers of the channel layer; wherein the first width is greater than the second width; the invention enables the formed channel to have larger width, thereby improving the performance of the transistor. The invention also discloses a manufacturing method of the transistor structure.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a high-performance transistor structure and a manufacturing method thereof.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the development of ICs, functional density (i.e., the number of interconnected devices per chip area) is typically increased, while geometry size (i.e., the smallest device or interconnect line that can be fabricated using a fabrication process) is reduced. Improvements in IC performance have been achieved primarily by the ever shrinking dimensions of integrated circuit devices to increase their speed. This scaled down process has the advantage of improving production efficiency and reducing associated costs. At the same time, this scaling down process also increases the complexity of handling and manufacturing the ICs.
In the process of seeking higher device density, higher performance, and lower cost, as integrated circuit processes continue to evolve into nanotechnology process nodes, some manufacturers have begun considering how to transition from planar CMOS transistors to three-dimensional fin field effect transistor (FinFET) device structures in order to overcome short channel effects and increase drive current density per unit area. A FinFET device is a multi-gate MOS device that has a very outstanding short channel control and high drive current due to more gate control area, narrower channel depletion region. Compared with a planar transistor, the FinFET device can better control carriers in an active region and provide larger driving current compared with a traditional MOS structure, so that the device performance is improved. Also, the FinFET device reduces short channel effects due to improved control over the channel.
However, FinFET devices require bulk fabrication above the substrate and form a uniform structure; because the non-planar process in the FinFET device manufacturing is difficult to be compatible with the existing CMOS planar process, the forming process of the FinFET device is very complex and high in cost, and the rapid development of the FinFET device to low-cost and high-efficiency production is restricted.
Therefore, there is a need for a new transistor structure that enhances transistor performance while avoiding the complex non-planar processes involved in the fabrication of FinFET devices.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a high performance transistor structure and a method for fabricating the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a transistor structure comprising:
a semiconductor substrate;
the channel layer protrudes upwards from the surface of the semiconductor substrate;
the grid oxide layer and the grid electrode sequentially surround the side face and the top face of the channel layer;
the source electrode and the drain electrode are respectively arranged at two ends of the channel layer on the semiconductor substrate;
the channel layer is of a laminated structure formed by alternately arranging silicon strips with a first width and silicon strips with a second width in the vertical direction, and the source electrode and the drain electrode are provided with source-drain silicon strip laminated structures corresponding to all layers of the channel layer; wherein the first width is greater than the second width.
Preferably, the channel layer has a side profile in an alternating concavo-convex shape.
Preferably, the semiconductor substrate material is monocrystalline silicon, the silicon strips with the first width are silicon nano strips with the first width, the silicon strips with the second width are silicon nano strips with the second width, the silicon nano strips with the first width and the silicon nano strips with the second width are alternately stacked to form a channel layer laminated structure with a concave-convex alternate shape side profile, and the source-drain silicon strips of each layer are source-drain silicon nano strips.
Preferably, the profile of the alternating concave-convex shape has an alternating concave-convex rectangular, trapezoidal or arc-shaped edge shape.
Preferably, the lowermost layer in the source and drain stack structure has a first area, and the other layers above the lowermost layer have a second area; wherein the first area is larger than the second area.
A method of fabricating a transistor structure, comprising:
providing a semiconductor substrate, covering a dielectric layer on the surface of the semiconductor substrate, forming a groove with a first width communicated with the semiconductor substrate in the dielectric layer, and forming a first layer of source-drain grooves at two ends of the groove with the first width;
forming silicon nano-strips with a first width in the grooves with the first width by adopting an epitaxial process, and forming first layer of source-drain silicon nano-strips in the first layer of source-drain grooves;
continuously covering the dielectric layer on the surface of the structure, forming a groove with a second width communicated with the groove with the first width in the new dielectric layer, forming second layer source-drain grooves at two ends of the groove with the second width, forming a silicon nano strip with the second width in the groove with the second width, and forming a second layer source-drain silicon nano strip in the second layer source-drain grooves;
repeating the steps until a channel layer with a concave-convex alternative shape side profile formed by alternately overlapping the silicon nano-strips with the first width and the silicon nano-strips with the second width and a laminated structure of a plurality of layers of source-drain silicon nano-strips are correspondingly formed;
and removing all the dielectric layers, sequentially forming a gate oxide layer and a gate electrode on the side surface and the top surface of the channel layer, and forming a source electrode and a drain electrode at the positions of the multilayer source-drain silicon nano-strips at the two ends of the channel layer.
Preferably, when forming each layer of source-drain trenches, the first layer of source-drain trenches have a first area, and the second layer of source-drain trenches and other layers of source-drain trenches above the second layer of source-drain trenches have a second area, so as to form a source-drain laminated structure with a first area at the lowest layer and a second area at other layers above the lowest layer; wherein the first area is larger than the second area.
Preferably, the channel layer with the profile of the side surface having the shape of alternating concave and convex has a trapezoidal edge shape with alternating concave and convex, and the method for forming the trapezoidal edge shape is as follows: in the etching process when the groove with the first width and the groove with the second width are formed, the opening of the formed groove etching graph is gradually reduced by utilizing the by-products deposited on the side wall of the groove, and after the etching is finished, the by-products deposited on the side wall of the groove are removed, so that the trapezoid edge shape with the inclined side wall is obtained.
Preferably, the channel layer with the profile of the side surface having the shape of alternating concave and convex has a trapezoidal edge shape with alternating concave and convex, and the method for forming the trapezoidal edge shape is as follows: in the etching process when the groove with the first width and the groove with the second width are formed, the groove is etched with partial depth, and then O is utilized2And (3) expanding the photoresist pattern outside the groove pattern by using gas to expose the pattern vertex angle of the groove, and then obtaining the trapezoidal edge shape with the inclined side wall by using an etching process with a bombardment effect and a method for simultaneously etching and bombarding the pattern vertex angle of the groove.
Preferably, the channel layer with the profile of the side surface having the shape of the alternating concave and convex has an arc-shaped edge shape having the alternating concave and convex, and the arc-shaped edge shape is formed by: in the etching process when forming the trench of the first width and the trench of the second width, the trench sidewall is isotropically etched by using an isotropic etching gas or liquid, resulting in an arc-shaped edge shape having an arc-shaped sidewall.
According to the technical scheme, the channel layer laminated structure formed by alternately arranging the silicon strips with the first width and the silicon strips with the second width which are different in width in the vertical direction are arranged on the surface of the semiconductor substrate in a protruding mode, so that the formed channel layer has the side profile which is in the shape of concave-convex alternation in the vertical direction, the formed channel has a larger width, and the transistor performance is improved.
Drawings
FIG. 1 is a diagram of a transistor structure according to a preferred embodiment of the present invention;
FIG. 2 is a diagram of a transistor structure according to a preferred embodiment of the present invention;
FIG. 3 is a third schematic diagram of a transistor structure according to a preferred embodiment of the present invention;
FIGS. 4-6 are schematic plan views of the channel layer and different layers in the source and drain of FIG. 2;
fig. 7-10 are schematic process structure diagrams illustrating a method for fabricating a transistor structure according to a preferred embodiment of the invention;
fig. 11-12 are schematic views illustrating a process for forming a channel layer having a trapezoidal edge shape according to a preferred embodiment of the present invention;
fig. 13-14 are schematic views illustrating a process for forming a channel layer having an arc-shaped edge according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 1-3, in which fig. 1 is a schematic diagram of a transistor structure according to a preferred embodiment of the present invention, fig. 2 is a schematic diagram of a transistor structure according to a preferred embodiment of the present invention, and fig. 3 is a schematic diagram of a transistor structure according to a preferred embodiment of the present invention. As shown in fig. 1 to 3, a transistor structure of the present invention includes: a semiconductor substrate 10, a channel layer 13, source and drain electrodes 17, a gate oxide layer 11, a gate electrode 12, and the like.
Please refer to fig. 1. The semiconductor substrate 10 may be formed of a single crystalline silicon material. Alternatively, other suitable semiconductors may be used.
The channel layer 13 is provided protruding upward on the surface of the semiconductor substrate 10. The gate oxide layer 11 is disposed around the side and top surfaces of the channel layer 13 and closely attached to the surfaces of the side and top surfaces of the channel layer 13. The gate electrode 12 is also disposed on the side and top surfaces of the channel layer 13, and is located outside the gate oxide layer 11, closely attached to the surface of the gate oxide layer 11. The lower ends of the gate oxide layer 11 and the gate electrode 12 are connected to the surface of the semiconductor substrate 10.
Please refer to fig. 1. The channel layer is a laminated structure formed by alternately arranging silicon strips with a first width and silicon strips with a second width in the vertical direction; wherein the first width is greater than the second width. Namely, the channel layer is a laminated structure of strip-shaped silicon strips formed by alternately arranging wide silicon strips and narrow silicon strips in the vertical direction.
The channel layer 13 has a side profile in a vertically alternating concavo-convex shape as viewed in a side cross section of the channel layer 13. The gate oxide layer 11 is closely attached to the surface of the channel layer 13 with the shape of the alternating concave-convex side surface, and may have the same contour structure with the shape of the alternating concave-convex side surface. The inner side of the gate electrode 12 closely conforms to the surface of the gate oxide layer 11, and the outer side of the gate electrode 12 may have a flat surface profile.
The profile of the channel layer 13 in the shape of alternating recesses and projections is formed by a continuous stacked structure of silicon strips of a first width and silicon strips of a second width, which are alternately arranged in the vertical direction in a width-wise manner, in the channel layer 13.
The stacked structure of the silicon strips with the first width and the silicon strips with the second width can be formed by multiple layers of silicon nano- strips 131 and 132 which are alternately stacked in width and width. Namely, the silicon strips with the first width are silicon nano strips with the first width, the silicon strips with the second width are silicon nano strips with the second width, and the silicon nano strips with the first width and the silicon nano strips with the second width are alternately stacked to form a channel layer laminated structure with a concave-convex alternate shape side profile.
For example, silicon nanoribbons 131 having a first width may be disposed upward from the surface of the semiconductor substrate 10, and silicon nanoribbons 132 having a second width may be disposed on the silicon nanoribbons 131 having the first width; wherein the width of the silicon nanoribbon 132 of the second width is smaller than the width of the silicon nanoribbon 131 of the first width. The silicon nanoribbon 131 having the first width and the silicon nanoribbon 132 having the second width are sequentially disposed on the silicon nanoribbon 132 having the second width, and the disposition may be repeated until a channel layer 13 stacked structure having a desired width is obtained. The channel layer 13 thus obtained may have a side profile of a concavo-convex alternating shape of a rectangular shape as illustrated.
In order to further increase the channel width, the profile of the channel layer 13 may be formed to have an edge shape such as a trapezoid (as shown in fig. 6 and 7) or an arc (as shown in fig. 8 and 9) in which the channel layer has an alternating concavo-convex shape. Through the structure, the channel width can be effectively increased, so that the device performance is improved.
Please refer to fig. 2. The source electrode and the drain electrode 17 are respectively arranged at two ends of the channel layer 13 on the semiconductor substrate 10; the source and drain electrodes 17 have a source-drain silicon strip laminated structure corresponding to each layer of the channel layer 13, and the layers are tightly connected with each other to form an integral structure, that is, the source and drain electrodes 17 are formed by overlapping multiple layers of silicon strips. The source-drain silicon strips of each layer are source-drain silicon nano strips, that is, the silicon strips for forming the source electrode and the drain electrode 17 are silicon nano strips. Thus, the source and drain electrodes 17 belong to structural extensions of the channel layer 13.
Referring to fig. 2 and fig. 4-6, a planar structure of a first layer located at the lowermost layer, a second layer located above the first layer, and a third layer in a stacked structure of the source and drain electrodes 17 and the channel layer 13 is shown. Wherein, the first layer 171 positioned at the lowermost layer in the stacked structure of the source and drain electrodes 17 has a first area, which is the same layer as the silicon nanoribbon 131 of the first width of the channel layer 13, and other layers, such as the second layer and the third layer 172, above the first layer 171 of the lowermost layer have a second area, which are sequentially the same layer as the silicon nanoribbon 132 of the second width of the channel layer 13, the silicon nanoribbon 131 of the first width, respectively; wherein the first area is larger than the second area.
Please refer to fig. 3. The first layer 171 having the first area in the stacked structure of the source and drain electrodes 17 exposes an area portion of other layers above it, for example, the second layer and the third layer 172, and can be used to connect the contact hole 18 upward. The portion of the structure above the silicon substrate 10 in the entire transistor may be in the dielectric layer 19.
The method for fabricating the transistor structure according to the present invention is described in detail below with reference to the accompanying drawings.
Referring to fig. 7-10, fig. 7-10 are schematic process structure diagrams illustrating a method for fabricating a transistor structure according to a preferred embodiment of the invention. As shown in fig. 7-10, a method for fabricating a transistor structure according to the present invention can be used for fabricating the transistor structure, and includes:
as shown in fig. 7, a semiconductor substrate 10 is provided, for example, the semiconductor substrate 10 may be formed by using a single crystal silicon material. First, a dielectric layer 14, such as SiO, is deposited on the surface of the semiconductor substrate 102The surface of the semiconductor substrate 10 is covered.
Next, a trench 16 with a first width may be formed in the dielectric layer 14 through photolithography and etching processes, and a first layer of source/drain trenches with a first area may be formed at two ends of the trench 16 with the first width (the process steps for forming the source and the drain are omitted, and the structure of fig. 2 and fig. 4-6 is referred to for understanding, and the same is applied below), and the trench 16 with the first width, the first layer of source/drain trenches, and the surface of the semiconductor substrate 10 are communicated through etching. The trenches 16 of the first width are stripe-shaped trench structures.
Then, silicon nanoribbon 131 with the first width is fabricated and formed in trench 16 with the first width, and a first layer of source-drain silicon nanoribbon is formed in the first layer of source-drain trench, for example, silicon nanoribbon 131 with the first width may be formed by using an epitaxial process in trench 16 with the first width, and the first layer of source-drain silicon nanoribbon may be formed by using an epitaxial process in the first layer of source-drain trench (the same below). Thereby connecting the silicon nanoribbon 131 with the first width and the first layer of source-drain silicon nanoribbon with the surface of the semiconductor substrate 10.
As shown in fig. 8, a dielectric layer 14 is further deposited on the surface of the formed structure to cover the surface of the formed structure. Then, forming a trench 15 with a second width communicated with the trench 16 with the first width in the dielectric layer 14 newly deposited above the trench 16 with the first width through photoetching and etching processes, and forming a second layer source-drain trench with a second area at two ends of the trench 15 with the second width, wherein the trench 15 with the second width is also in a strip-shaped trench structure; and extending in the trench 15 with the second width to form a silicon nano-strip 132 with the second width smaller than the silicon nano-strip 131 with the first width, and extending in the second layer of source-drain trenches to form a second layer of source-drain silicon nano-strip, so that the silicon nano-strip 132 with the second width is connected with the silicon nano-strip 131 with the first width, and the second layer of source-drain silicon nano-strip is connected with the first layer of source-drain silicon nano-strip.
As shown in fig. 9-10, the above steps are repeated, by continuously depositing a new dielectric layer 14, a new groove 16 with the first width and a groove 15 with the second width, a new third layer source drain groove and a new fourth layer source drain groove are formed on the groove 15 with the second width in sequence, and sequentially continuing to epitaxially form the silicon nanoribbon 131 with the first width and the silicon nanoribbon 132 with the second width on the silicon nanoribbon 132 with the second width in the trench 15 with the second width, and epitaxially forming a third layer of source-drain silicon nano-strips and a fourth layer of source-drain silicon nano-strips in the third layer of source-drain trenches and the fourth layer of source-drain trenches until a channel layer 13 with a concave-convex alternate shape side profile formed by alternately overlapping the first width silicon nano-strips 131 and the second width silicon nano-strips 132 and a laminated structure of the multilayer source-drain silicon nano-strips are correspondingly formed (please refer to fig. 1-6 for understanding).
Thereafter, all of the dielectric layer 14 may be removed using HF. Then, a gate oxide layer 11 and a gate electrode 12 are sequentially grown and formed on the side surface and the top surface of the channel layer 13, and a source and a drain 17 are formed by implantation at the position of the multilayer source-drain silicon nano-strip at two ends of the channel layer 13. A new dielectric layer 19 may be further formed on the device structure, and a contact hole 18 may be formed in the dielectric layer on the exposed portion of the first layer of source-drain silicon nano-strips 171.
This results in a transistor with a larger channel width (as shown in fig. 1) and improved transistor performance.
In the laminated structure of the source and the drain 17, the area of the first layer of source-drain grooves is larger than that of the source-drain grooves above the second layer, so that the area of the first layer of source-drain silicon nano-strips 171 is larger than that of the second layer of source-drain silicon nano-strips 172. Thus, when source and drain injection for forming the source and drain 17 is carried out, doping of relevant levels of the source and drain and the source and drain extension region can be realized through large-angle injection, and even if the structure (fin) of the channel layer is wider, so that the source and drain region is very thick and very wide, doping of the source and drain can be conveniently realized.
The obtained channel layer 13 may have a side profile of an approximately rectangular concavo-convex alternating shape as shown in fig. 1.
In order to further increase the channel width, the profile of the channel layer 13 with an alternating concavo-convex shape may be formed to have an edge shape such as a trapezoid or an arc with an alternating concavo-convex shape.
Referring to fig. 11-12, fig. 11-12 are schematic views illustrating a process for forming a channel layer having a trapezoidal edge shape according to a preferred embodiment of the invention. As shown in fig. 11-12, a byproduct (polymer) is generally generated during etching, so that when it is required to make the profile of the channel layer 13 with the concave-convex alternating shape have a trapezoidal edge shape, an etching gas configuration with a heavier byproduct, such as C, may be introduced during the etching process when forming the trenches of the first width and the trenches of the second width4F6Or C4F8Isoetch of SiO2A dielectric layer; the by-products are continuously deposited on the side wall of the groove in the etching process, so that the opening of the formed groove etching graph is gradually reduced by using the by-products deposited on the side wall of the groove; after the etching is finished, by-products deposited on the side wall of the groove are removed, and the trapezoid edge shape with the side wall with a large inclined angle can be obtained.
In addition, in the etching process when forming the trench with the first width and the trench with the second width, the trench may be etched partially, for example, half of the trench may be etched first, and then O may be used2Expanding the photoresist pattern outside the groove pattern by the gas to expose and etch half of the top angle of the groove pattern; then, the bombardment action in the etching gas, i.e. the bombardment component is heavier (Ar, etc.)Higher gas proportion), and a trapezoidal edge shape with a side wall with a large inclination angle is obtained by a method of bombarding the top angle of the groove graph while etching.
Thereafter, the silicon nanobelts 131, 132 may be formed by employing an epitaxial process in the trenches 16, 15 having the edge shape of the trapezoid.
Referring to fig. 13-14, fig. 13-14 are schematic views illustrating a process for forming a channel layer having an arc-shaped edge according to a preferred embodiment of the invention. As shown in fig. 13 to 14, when it is required to form the channel layer 13 having the shape of the curved edge on the side profile of the concavo-convex alternating shape, the SiO may be etched by using an isotropic etching gas or an etching liquid (e.g., VHF — HF in a gas state, or wet hydrofluoric acid) in the etching process when forming the trenches of the first width and the trenches of the second width2And isotropically etching the side wall of the dielectric layer groove to obtain an arc-shaped edge shape with an arc-shaped side wall. Thereafter, the silicon nanobelts 131, 132 may be formed by employing an epitaxial process in the trenches 16, 15 having the edge shape of the trapezoid.
In summary, the channel layer laminated structure formed by alternately arranging the silicon strips with the first width and the silicon strips with the second width which are different in width on the surface of the semiconductor substrate in the vertical direction in a protruding mode is arranged on the surface of the semiconductor substrate, so that the formed channel layer has the side profile which is in the shape of concave-convex alternation in the vertical direction, the formed channel has a larger width, and the transistor performance is improved.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (8)
1. A method of fabricating a transistor structure, comprising:
providing a semiconductor substrate, covering a dielectric layer on the surface of the semiconductor substrate, forming a groove with a first width communicated with the semiconductor substrate in the dielectric layer, and forming a first layer of source-drain grooves at two ends of the groove with the first width;
forming silicon nano-strips with a first width in the grooves with the first width by adopting an epitaxial process, and forming first layer of source-drain silicon nano-strips in the first layer of source-drain grooves;
continuously covering the dielectric layer on the surface of the structure, forming a groove with a second width communicated with the groove with the first width in the new dielectric layer, forming second layer source-drain grooves at two ends of the groove with the second width, forming a silicon nano strip with the second width in the groove with the second width, and forming a second layer source-drain silicon nano strip in the second layer source-drain grooves;
repeating the steps until a channel layer with a concave-convex alternative shape side profile formed by alternately overlapping the silicon nano-strips with the first width and the silicon nano-strips with the second width and a laminated structure of a plurality of layers of source-drain silicon nano-strips are correspondingly formed;
and removing all the dielectric layers, sequentially forming a gate oxide layer and a gate electrode on the side surface and the top surface of the channel layer, and forming a source electrode and a drain electrode at the positions of the multilayer source-drain silicon nano-strips at the two ends of the channel layer.
2. The method for manufacturing the transistor structure according to claim 1, wherein when the source-drain trenches of each layer are formed, the source-drain trench of the first layer is made to have a first area, and the source-drain trench of the second layer and the source-drain trenches of other layers above the second layer are made to have a second area, so as to form a source-drain stacked structure in which the lowest layer has a first area and the other layers above the lowest layer have a second area; wherein the first area is larger than the second area.
3. The method for manufacturing a transistor structure according to claim 1, wherein the channel layer having the profile with alternating concave-convex sides has an alternating concave-convex trapezoidal edge shape, and the trapezoidal edge shape is formed by: in the etching process when the groove with the first width and the groove with the second width are formed, the opening of the formed groove etching graph is gradually reduced by utilizing the by-products deposited on the side wall of the groove, and after the etching is finished, the by-products deposited on the side wall of the groove are removed, so that the trapezoid edge shape with the inclined side wall is obtained.
4. The method for manufacturing a transistor structure according to claim 1, wherein the channel layer having the profile with alternating concave-convex sides has an alternating concave-convex trapezoidal edge shape, and the trapezoidal edge shape is formed by: in the etching process when the groove with the first width and the groove with the second width are formed, the groove is etched with partial depth, and then O is utilized2And (3) expanding the photoresist pattern outside the groove pattern by using gas to expose the pattern vertex angle of the groove, and then obtaining the trapezoidal edge shape with the inclined side wall by using an etching process with a bombardment effect and a method for simultaneously etching and bombarding the pattern vertex angle of the groove.
5. The method for manufacturing a transistor structure according to claim 1, wherein the channel layer with the profile of the alternating concave-convex side surface has an alternating concave-convex arc-shaped edge shape, and the arc-shaped edge shape is formed by: in the etching process when forming the trench of the first width and the trench of the second width, the trench sidewall is isotropically etched by using an isotropic etching gas or liquid, resulting in an arc-shaped edge shape having an arc-shaped sidewall.
6. The method of claim 1, wherein the channel layer with the profile of the alternating concavo-convex side has an alternating concavo-convex rectangular edge shape.
7. A transistor structure formed by the method of forming a transistor structure according to any of claims 1-6, the transistor comprising:
a semiconductor substrate;
the channel layer protrudes upwards from the surface of the semiconductor substrate;
the grid oxide layer and the grid electrode sequentially surround the side face and the top face of the channel layer;
the source electrode and the drain electrode are respectively arranged at two ends of the channel layer on the semiconductor substrate;
the channel layer is of a laminated structure formed by alternately arranging silicon strips with a first width and silicon strips with a second width in the vertical direction, and the source electrode and the drain electrode are provided with source-drain silicon strip laminated structures corresponding to all layers of the channel layer; wherein the first width is greater than the second width.
8. The transistor structure according to claim 7, wherein the semiconductor substrate material is single crystal silicon, the silicon strips with the first width are silicon nano strips with the first width, the silicon strips with the second width are silicon nano strips with the second width, the silicon nano strips with the first width and the silicon nano strips with the second width are alternately stacked to form a channel layer stacked structure with a concave-convex alternate shape side profile, and the source-drain silicon strips of each layer are source-drain silicon nano strips.
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