WO2024040854A1

WO2024040854A1 - Circuit layout structure and chip

Info

Publication number: WO2024040854A1
Application number: PCT/CN2023/070539
Authority: WO
Inventors: 郭迎冬; 姜伟; 徐静
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-24
Filing date: 2023-01-04
Publication date: 2024-02-29
Also published as: CN117669462A

Abstract

A circuit layout structure and a chip. The structure comprises: a first-stage circuit module (1), a second-stage circuit module (2), a third-stage circuit module (3) and a fourth-stage circuit module (4), inputs and outputs of which are annularly connected in series, wherein the modules are arranged in a first direction; the first-stage circuit module (1) and the third-stage circuit module (3), or the second-stage circuit module (2) and the fourth-stage circuit module (4) are respectively located at two edges in the first direction; and the first-stage circuit module (1) and the second-stage circuit module (2) are connected by means of a first group of signal lines (S1), the second-stage circuit module (2) and the third-stage circuit module (3) are connected by means of a second group of signal lines (S2), the third-stage circuit module (3) and the fourth-stage circuit module (4) are connected by means of a third group of signal lines (S3), the fourth-stage circuit module (4) and the first-stage circuit module (1) are connected by means of a fourth groups of signal lines, the first group of signal lines (S1) and the third group of signal lines (S3) each have a first length, and the second group of signal lines (S2) and the fourth group of signal lines (S4) each have a second length. The trace length of an annular series circuit module can be equalized.

Description

Circuit layout structure and chip

cross reference

This disclosure claims priority to the Chinese patent application with application number 202211021848.3 and titled "Circuit Layout Structure and Chip" filed on August 24, 2020. The entire content of this Chinese patent application is incorporated herein by reference.

Technical field

The present disclosure relates to the technical field of integrated circuit modules, and specifically to a circuit layout structure capable of balancing the trace lengths between ring-shaped series-connected circuit modules and a chip applying the circuit layout structure.

Background technique

The Decision Feedback Equalization (DFE) function was introduced for the first time in the DDR5/LPDDR5 design specifications of DRAM. DFE is a technique that provides better equalization to reduce inter-symbol interference by using feedback from the memory bus receiver to open the data eye after the receiver has latched the data. , which not only achieves better signal equalization, but also enables the clearer signal transmission required for the DDR5/LPDDR5 memory bus to operate at higher transmission rates without any glitches.

Since the signal processing of the DFE module has high phase requirements, during the circuit layout (layout), the corresponding trace lengths of the DFE modules should not differ too much. However, according to the connection sequence of each DFE module, there will always be a signal line. The length difference from other signal lines is too large, resulting in a decrease in signal transmission quality.

It should be noted that the information disclosed in the above background section is only used to enhance understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of this disclosure is to provide a circuit layout structure and a chip applying the circuit layout structure, which are used to reduce the difference in wiring length between DFE circuit modules at least to a certain extent and improve signal quality.

According to a first aspect of the present disclosure, a circuit layout structure is provided, including: a first-level circuit module, a second-level circuit module, a third-level circuit module, and a fourth-level circuit module with input and output annular series connections. The first-level circuit module The first-level circuit module, the second-level circuit module, the third-level circuit module, and the fourth-level circuit module are arranged along the first direction. The first-level circuit module and the third-level circuit module are respectively located at The two edges in the first direction, or the second-level circuit module and the fourth-level circuit module are respectively located on the two edges in the first direction; wherein, the first-level circuit module The second-level circuit module is connected to the second-level circuit module through a first set of signal lines. The second-level circuit module and the third-level circuit module are connected to the third-level circuit module through a second set of signal lines. The third-level circuit module The fourth-level circuit module is connected to the fourth-level circuit module through a third set of signal lines. The fourth-level circuit module is connected to the first-level circuit module through a fourth-level set of signal lines. The first set of signal lines The second set of signal lines and the third set of signal lines each have a first length, and the second set of signal lines and the fourth set of signal lines each have a second length.

In an exemplary embodiment of the present disclosure, the first-level circuit module, the second-level circuit module, the fourth-level circuit module, and the third-level circuit module are arranged in the first direction or They are arranged sequentially in the opposite direction of the first direction.

In an exemplary embodiment of the present disclosure, the first-level circuit module, the fourth-level circuit module, the second-level circuit module, and the third-level circuit module are arranged in the first direction or They are arranged sequentially in the opposite direction of the first direction.

In an exemplary embodiment of the present disclosure, the output terminal of the first-stage circuit module, the input terminal of the second-stage circuit module, the output terminal of the second-stage circuit module, the third-stage circuit module The input terminals of the circuit modules are arranged along the first row; the input terminals of the first-level circuit modules, the output terminals of the fourth-level circuit modules, the input terminals of the fourth-level circuit modules, the third-level circuit modules The output ends of the modules are arranged along the second row; the first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.

In an exemplary embodiment of the present disclosure, the first group of signal lines and the second group of signal lines are arranged along the first row, and the third group of signal lines and the fourth group of signal lines arranged along the second row.

In an exemplary embodiment of the present disclosure, the input terminal of the first-stage circuit module, the output terminal of the fourth-stage circuit module, the input terminal of the fourth-stage circuit module, the third-stage circuit module The output terminals of the circuit modules are arranged along the first row; the output terminals of the first-level circuit module, the input terminals of the second-level circuit modules, the output terminals of the second-level circuit modules, and the third-level circuit The input ends of the modules are arranged along the second row; the first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.

In an exemplary embodiment of the present disclosure, the first group of signal lines and the second group of signal lines are arranged along the second row, and the third group of signal lines and the fourth group of signal lines are arranged along the second row. arranged along the first row.

In an exemplary embodiment of the present disclosure, the output terminal of the first-stage circuit module, the input terminal of the first-stage circuit module, the output terminal of the fourth-stage circuit module, the fourth-stage circuit module The input terminals of the circuit modules are arranged along the first row; the input terminals of the second-level circuit modules, the output terminals of the second-level circuit modules, the input terminals of the third-level circuit modules, the third-level circuit modules The output terminals of the module are arranged along the second row; the second set of signal lines are arranged along the second row, and the fourth set of signal lines are arranged along the first row; the first row and the second The rows are parallel to each other and arranged in a second direction, said second direction being perpendicular to said first direction.

In an exemplary embodiment of the present disclosure, the input terminal of the second-stage circuit module, the output terminal of the second-stage circuit module, the input terminal of the third-stage circuit module, the third-stage circuit module The output terminals of the circuit modules are arranged along the first row; the output terminals of the first-level circuit modules, the input terminals of the first-level circuit modules, the output terminals of the fourth-level circuit modules, the fourth-level circuit modules The input terminals of the module are arranged along the second row; the second set of signal lines are arranged along the first row, and the fourth set of signal lines are arranged along the second row; the first row and the second The rows are parallel to each other and arranged in a second direction, said second direction being perpendicular to said first direction.

In an exemplary embodiment of the present disclosure, the first group of signal lines includes a first wiring portion arranged in the first row, a second wiring portion arranged in the second row, and a first wiring portion arranged along the first row. A first winding portion arranged in two directions, the first wiring portion and the second wiring portion are connected through the first winding portion; the third group of signal lines includes a third group of signal lines arranged in the second row. Three wiring parts, a fourth wiring part arranged in the first row and a second winding part arranged along the second direction, the third wiring part and the fourth wiring part pass through the second winding part. The line portion is connected; wherein the first length and the second length are equal.

In an exemplary embodiment of the present disclosure, the input terminal of the first-stage circuit module, the output terminal of the first-stage circuit module, the input terminal of the second-stage circuit module, the second-stage circuit module The output terminals of the circuit modules are arranged along the first row; the input terminals of the third-level circuit module, the output terminals of the third-level circuit modules, the input terminals of the fourth-level circuit modules, the fourth-level circuit modules The output terminals of the module are arranged along the second row; the first set of signal lines are arranged along the first row, and the third set of signal lines are arranged along the second row; the first row and the second The rows are parallel to each other and arranged in a second direction, said second direction being perpendicular to said first direction.

In an exemplary embodiment of the present disclosure, the input end of the third-level circuit module, the output end of the third-level circuit module, the input end of the fourth-level circuit module, the fourth-level circuit module The output terminals of the circuit modules are arranged along the first row; the input terminals of the first-level circuit modules, the output terminals of the first-level circuit modules, the input terminals of the second-level circuit modules, the second-level circuit modules The output terminals of the module are arranged along the second row; the third set of signal lines are arranged along the first row, and the first set of signal lines are arranged along the second row; the first row and the second The rows are parallel to each other and arranged in a second direction, said second direction being perpendicular to said first direction.

In an exemplary embodiment of the present disclosure, the second group of signal lines includes a fifth wiring portion arranged in the first row, a sixth wiring portion arranged in the second row, and a fifth wiring portion arranged along the first row. A third winding portion arranged in two directions, the fifth wiring portion and the sixth wiring portion are connected through the third winding portion; the fourth group of signal lines includes a third wiring portion arranged in the first row. Seven wiring parts, an eighth wiring part arranged in the second row, and a fourth winding part arranged along the second direction, the seventh wiring part and the eighth wiring part pass through the fourth winding part. The line portion is connected; wherein the first length is equal to the second length.

In an exemplary embodiment of the present disclosure, the first group of signal lines, the second group of signal lines, the third group of signal lines, and the fourth group of signal lines each include two lines with a distance equal to The default value is equal width of the signal lines.

In an exemplary embodiment of the present disclosure, the first-level circuit module is an odd-bit rising edge sampling module, the second-level circuit module is an odd-bit falling edge sampling module, and the third-level circuit module is Even-numbered rising edge sampling module, the fourth-level circuit module is an even-numbered falling edge sampling module, the first group of signal lines, the second group of signal lines, the third group of signal lines, the fourth The group of signal lines all include decision feedback equalization signal lines.

According to a second aspect of the present disclosure, a chip is provided, including the circuit layout structure as described in any one of the above.

By adjusting the circuit layout structure sequence of the ring-shaped series-connected multi-level circuit modules, the embodiments of the present disclosure can avoid the occurrence of wiring lengths between any two circuit modules that are much longer than the wiring lengths between other circuit modules, effectively and evenly related circuits. The length of traces between modules improves signal quality.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

1A to 1H are schematic layout diagrams of circuit modules corresponding to the circuit layout structure in embodiments of the present disclosure.

2A and 2B are schematic wiring diagrams of the circuit layout structure shown in FIG. 1A in one embodiment of the present disclosure.

3A and 3B are schematic wiring diagrams of the circuit layout structure shown in FIG. 1C in one embodiment of the present disclosure.

4A and 4B are schematic wiring diagrams of the circuit layout structure shown in FIG. 1A in another embodiment of the present disclosure.

5A and 5B are schematic wiring diagrams of the circuit layout structure shown in FIG. 1C in another embodiment of the present disclosure.

6A and 6B are schematic diagrams of wiring in one embodiment of the present disclosure.

7A and 7B are schematic diagrams of circuit modules corresponding to the circuit layout structure in another embodiment of the present disclosure.

8A to 8D are schematic diagrams of the layout and wiring of three circuit modules connected in annular series in an embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.

In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

Example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Referring to Figures 1A to 1H, the first-level circuit module 1, the second-level circuit module 2, the third-level circuit module 3, and the fourth-level circuit module 4 are connected in annular series with input and output. The first-level circuit module 1, the second-level circuit module The circuit module 2, the third-level circuit module 3, and the fourth-level circuit module 4 are arranged along the first direction, and the first-level circuit module 1 and the third-level circuit module 3 are respectively located at two edges in the first direction, or, The secondary circuit module 2 and the fourth-level circuit module 4 are respectively located on the two edges in the first direction.

Among them, in the embodiment shown in FIGS. 1A to 1D , the first-level circuit module 1 and the third-level circuit module 3 are respectively located at two edges in the first direction; in the embodiment shown in FIGS. 1E to 1H , the second-level circuit module 1 The first-level circuit module 2 and the fourth-level circuit module 4 are respectively located on two edges in the first direction.

Referring to FIG. 1A , the first-level circuit module 1 , the second-level circuit module 2 , the fourth-level circuit module 4 , and the third-level circuit module 3 are arranged in sequence in the first direction.

Referring to FIG. 1B , the first-level circuit module 1 , the second-level circuit module 2 , the fourth-level circuit module 4 , and the third-level circuit module 3 are sequentially arranged in the opposite direction to the first direction.

Referring to FIG. 1C , the first-level circuit module 1 , the fourth-level circuit module 4 , the second-level circuit module 2 , and the third-level circuit module 3 are arranged in sequence in the first direction.

Referring to FIG. 1D , the first-level circuit module 1 , the fourth-level circuit module 4 , the second-level circuit module 2 , and the third-level circuit module 3 are sequentially arranged in the opposite direction to the first direction.

Referring to Figure 1E, the second-level circuit module 2, the first-level circuit module 1, the third-level circuit module 3, and the fourth-level circuit module 4 are arranged in sequence in the first direction.

Referring to FIG. 1F , the second-level circuit module 2 , the first-level circuit module 1 , the third-level circuit module 3 , and the fourth-level circuit module 4 are sequentially arranged in the opposite direction to the first direction.

Referring to Figure 1G, the second-level circuit module 2, the third-level circuit module 3, the first-level circuit module 1, and the fourth-level circuit module 4 are arranged in sequence in the first direction.

Referring to FIG. 1H , the second-level circuit module 2 , the third-level circuit module 3 , the first-level circuit module 1 , and the fourth-level circuit module 4 are sequentially arranged in the opposite direction to the first direction.

Among them, the first-level circuit module 1 and the second-level circuit module 2 are connected through a first set of signal lines S1 (not shown), and the second-level circuit module 2 and the third-level circuit module 3 are connected through a second set of signal lines S1 (not shown). A set of signal lines S2 (not shown yet) is connected to each other. The third-level circuit module 3 and the fourth-level circuit module 4 are connected to each other through a third set of signal lines S3 (not shown yet). The fourth-level circuit module 4 and the fourth-level circuit module 4 are connected to each other through a third set of signal lines S3 (not shown yet). The first-level circuit modules 1 are connected through a fourth-level group of signal lines S4 (not shown yet). The first group of signal lines S1 and the third group of signal lines S3 both have a first length L1. The second group of signal lines S2 and Each of the fourth group of signal lines S4 has a second length L2.

In the embodiment shown in FIGS. 1A to 1H , the circuit modules at each level are not arranged sequentially according to the input and output sequence of the ring series. Instead, the two-level circuit modules that do not have a direct connection relationship are arranged on the edge in the arrangement direction, so that Make the connections between each level of circuit modules uniform (in the following figures, the first group of signal lines S1 and the third group of signal lines S3 both have a first length L1, the second group of signal lines S2 and the fourth group of signal lines S4 both have a second length L2).

Below, detailed embodiments are used to introduce the uniform adjustment effect of the circuit layout structure provided by the present disclosure on the trace lengths between circuit modules at all levels.

Referring to Figure 2A, in one embodiment, when the first-level circuit module 1, the second-level circuit module 2, the fourth-level circuit module 4, and the third-level circuit module 3 are arranged in sequence in the first direction, it can be set The output end of the first-level circuit module 1, the input end of the second-level circuit module 2, the output end of the second-level circuit module 2, and the input end of the third-level circuit module 3 are arranged along the first row; the first-level circuit module The input end of 1, the output end of the fourth-level circuit module 4, the input end of the fourth-level circuit module 4, and the output end of the third-level circuit module 3 are arranged along the second row; the first row and the second row are parallel to each other and Arranged along a second direction, the second direction is perpendicular to the first direction.

At this time, according to the ring input and output connection sequence of the circuits at each level, the first group of signal lines S1 and the second group of signal lines S2 are arranged along the first row, and the third group of signal lines S3 and the fourth group of signal lines S4 are arranged along the second row. layout. Wherein, the first group of signal lines S1 and the third group of signal lines S3 both have a first length L1, and the second group of signal lines S2 and the fourth group of signal lines S4 both have a second length L2.

Referring to Figure 2B, different from the arrangement direction of Figure 2A, the input end of the first-level circuit module 1, the output end of the fourth-level circuit module 4, the input end of the fourth-level circuit module 4, and the third-level circuit module can be set The output terminals of 3 are arranged along the first row; the output terminal of the first-stage circuit module 1, the input terminal of the second-stage circuit module 2, the output terminal of the second-stage circuit module 2, and the input terminal of the third-stage circuit module 3 are arranged along the Second row layout.

At this time, according to the ring input and output connection sequence of the circuits at each level, the first group of signal lines S1 and the second group of signal lines S2 are arranged along the second row, and the third group of signal lines S3 and the fourth group of signal lines S4 are arranged along the first row. layout. Similarly, at this time, the first group of signal lines S1 and the third group of signal lines S3 both have the first length L1, and the second group of signal lines S2 and the fourth group of signal lines S4 both have the second length L2.

The wiring methods shown in Figures 2A and 2B can also be applied to the circuit layout structure of Figure 1B, and can be adjusted symmetrically to the left and right, and will not be described again here.

In the embodiment shown in FIG. 2A and FIG. 2B , as long as the first-level circuit module 1 , the second-level circuit module 2 , the fourth-level circuit module 4 , and the third-level circuit module 3 are arranged equidistantly, the first group can be maintained. The signal lines S1 and the third group of signal lines S3 have the same length, the second group of signal lines S2 and the fourth group of signal lines S4 have the same length, and the lengths of the signal lines are more uniform. This effectively avoids data delays and timing disorders caused by uneven signal routing. When applied to DFE signal lines, it can effectively balance the phases between DFE functional modules.

Referring to FIG. 3A , in one embodiment, when the first-level circuit module 1 , the fourth-level circuit module 4 , the second-level circuit module 2 , and the third-level circuit module 3 are arranged in sequence in the first direction, the same method can be used. The output terminal of the first-level circuit module 1, the input terminal of the second-level circuit module 2, the output terminal of the second-level circuit module 2, and the input terminal of the third-level circuit module 3 are arranged along the first row; the first-level circuit The input terminal of module 1, the output terminal of the fourth-level circuit module 4, the input terminal of the fourth-level circuit module 4, and the output terminal of the third-level circuit module 3 are arranged along the second row.

At this time, according to the ring input and output connection sequence of the circuits at each level, the first group of signal lines S1 and the second group of signal lines S2 are arranged along the first row, and the third group of signal lines S3 and the fourth group of signal lines S4 are arranged along the second row. layout.

Referring to Figure 3B, different from the arrangement direction of Figure 3A, the input end of the first-level circuit module 1, the output end of the fourth-level circuit module 4, the input end of the fourth-level circuit module 4, and the third-level circuit module can be set The output terminals of 3 are arranged along the first row; the output terminal of the first-stage circuit module 1, the input terminal of the second-stage circuit module 2, the output terminal of the second-stage circuit module 2, and the input terminal of the third-stage circuit module 3 are along the Second row layout.

At this time, according to the ring input and output connection sequence of the circuits at each level, the first group of signal lines S1 and the second group of signal lines S2 are arranged along the second row, and the third group of signal lines S3 and the fourth group of signal lines S4 are arranged along the first row. layout.

The wiring methods shown in Figure 3A and Figure 3B can also be applied to the circuit layout structure of Figure 1D, and can be adjusted symmetrically to the left and right, and will not be described again here.

In the embodiment shown in FIG. 3A and FIG. 3B , as long as the first-level circuit module 1 , the fourth-level circuit module 4 , the second-level circuit module 2 , and the third-level circuit module 3 are arranged equidistantly, the first group can be maintained. The signal lines S1 and the third group of signal lines S3 have the same length, the second group of signal lines S2 and the fourth group of signal lines S4 have the same length, and the lengths of the signal lines are more uniform.

The layouts shown in Figures 1E to 1H can also be configured with reference to Figures 2A, 2B, 3A, and 3B, and are not shown one by one.

In other embodiments of the present disclosure, the lengths of the first group of signal lines S1, the second group of signal lines S2, the third group of signal lines S3, and the fourth group of signal lines can be made completely the same.

Referring to Figure 4A, when the first-level circuit module 1, the second-level circuit module 2, the fourth-level circuit module 4, and the third-level circuit module 3 are arranged in sequence in the first direction, the first-level circuit module 1 can be set The output end, the input end of the first-level circuit module 1, the output end of the fourth-level circuit module 4, and the input end of the fourth-level circuit module 4 are arranged along the first row; the input end of the second-level circuit module 2, the The output terminal of the second-level circuit module 2, the input terminal of the third-level circuit module 3, and the output terminal of the third-level circuit module 3 are arranged along the second row.

At this time, the second group of signal lines S2 is arranged along the second row, and the fourth group of signal lines S4 is arranged along the first row.

Or, as shown in Figure 4B, the input terminal of the second-stage circuit module 2, the output terminal of the second-stage circuit module 2, the input terminal of the third-stage circuit module 3, and the output terminal of the third-stage circuit module 3 are arranged along the first Arranged in one row; the output end of the first-level circuit module 1, the input end of the first-level circuit module 1, the output end of the fourth-level circuit module 4, and the input end of the fourth-level circuit module 4 are arranged along the second row.

At this time, the second group of signal lines S2 is arranged along the first row, and the fourth group of signal lines S4 is arranged along the second row.

In the embodiment shown in FIG. 4A and FIG. 4B , the first group of signal lines S1 each includes a first wiring portion S11 arranged in the first row, a second wiring portion S13 arranged in the second row, and a first wiring portion S13 arranged in the second direction. The first winding part S12, the first wiring part S11 and the second wiring part S13 are connected through the first winding part S12; the third group of signal lines S3 includes a third wiring part S31 arranged in the first row, and a third wiring part S31 arranged in the second row. The third wiring portion S31 and the fourth wiring portion S33 are connected through the second winding portion S32.

At this time, the first length L1 of the first group of signal lines S1 and the third group of signal lines S3 is equal to the second length L2 of the second group of signal lines S2 and the fourth group of signal lines S4, that is, the length of each signal line is equal. Achieve optimal trace length balancing. By adding a winding section to a shorter signal line, the length of each signal line can be equalized, thereby effectively balancing the length of the signal line connection between the ring series circuits and minimizing the signal delay caused by the signal line.

The shape of each winding portion includes but is not limited to a U-shaped bend. In other embodiments, for example, when the first length L1 is much larger than the second length L2, the shape of the winding portion can also be set to be more curved, or more curved. Large angle bends, such as arc bends, multiple interconnected U-shaped bends, rectangular fold lines, acute angle fold lines, obtuse angle fold lines, etc., etc., the shape of the winding portion in the embodiment of the present disclosure is only an example. In actual implementation, You only need to ensure that the length of each signal line is equal through winding.

The wiring methods shown in Figure 4A and Figure 4B can also be applied to the circuit layout structure shown in Figure 1B, and only need to be adjusted symmetrically to the left and right, and will not be described again here.

Referring to Figure 5A, when the first-level circuit module 1, the fourth-level circuit module 4, the second-level circuit module 2, and the third-level circuit module 3 are arranged in sequence in the first direction, the first-level circuit module 1 can be set The input end, the output end of the first-level circuit module 1, the input end of the second-level circuit module 2, and the output end of the second-level circuit module 2 are arranged along the first row; the input end of the third-level circuit module 3, the The output terminal of the third-level circuit module 3, the input terminal of the fourth-level circuit module 4, and the output terminal of the fourth-level circuit module 4 are arranged along the second row.

At this time, the first group of signal lines S1 is arranged along the first row, and the third group of signal lines S3 is arranged along the second row.

Or, as shown in Figure 5B, the input terminal of the third-level circuit module 3, the output terminal of the third-level circuit module 3, the input terminal of the fourth-level circuit module 4, and the output terminal of the fourth-level circuit module 4 are arranged along the first row. Arrangement: The input terminal of the first-stage circuit module 1, the output terminal of the first-stage circuit module 1, the input terminal of the second-stage circuit module 2, and the output terminal of the second-stage circuit module 2 are arranged along the second row.

At this time, the third group of signal lines S3 is arranged along the first row, and the first group of signal lines S1 is arranged along the second row.

In the embodiment shown in FIG. 5A and FIG. 5B , the second group of signal lines S2 each includes a fifth wiring portion S21 arranged in the first row, a sixth wiring portion S23 arranged in the second row, and a fifth wiring portion S23 arranged in the second direction. The third winding part S22, the fifth wiring part S21 and the sixth wiring part S23 are connected through the third winding part S22; the fourth group of signal lines S4 each includes a seventh wiring part S41 arranged in the first row, a seventh wiring part S41 arranged in the first row, and a seventh wiring part S41 arranged in the first row. There are two rows of eighth wiring portions S43 and fourth winding portions S42 arranged along the second direction. The seventh wiring portion S41 and the eighth wiring portion S43 are connected through the fourth winding portions.

At this time, the first length L1 of the first group of signal lines S1 and the third group of signal lines S3 is equal to the second length L2 of the second group of signal lines S2 and the fourth group of signal lines S4, that is, the length of each signal line is equal. Achieve optimal trace length balancing.

The wiring methods shown in Figure 5A and Figure 5B can also be applied to the circuit layout structure shown in Figure 1D, and only need to be adjusted symmetrically to the left and right, and will not be described again here.

The layouts shown in Figures 1E to 1H can also be configured with reference to Figures 4A, 4B, 5A, and 5B, and are not shown one by one.

Referring to FIGS. 6A and 6B , in another embodiment of the present disclosure, the first group of signal lines S1 , the second group of signal lines S2 , the third group of signal lines S3 , and the fourth group of signal lines S4 each include two pitches. Signal lines of equal width equal to the preset value.

In the embodiment shown in FIG. 6A, when the first-level circuit module 1, the second-level circuit module 2, the fourth-level circuit module 4, and the third-level circuit module 3 are arranged sequentially in the first direction, the third group The two signal lines in the signal line S3 have unequal lengths of the first row extending portions, unequal lengths of the winding portions, and unequal lengths of the second row extending portions. The first row of the two signal lines in the first group of signal lines S1 has different lengths. The row extensions are unequal lengths, the winding portions are unequal lengths, and the second row extensions are unequal lengths.

In the embodiment shown in Figure 6B, when the first-level circuit module 1, the fourth-level circuit module 4, the second-level circuit module 2, and the third-level circuit module 3 are arranged in sequence in the first direction, the second group The extension parts of the first row of the two signal lines in the signal line S2 are of different lengths, the winding parts are of different lengths, and the extension parts of the second row are of different lengths. The first row of the two signal lines of the fourth group of signal lines S4 are of different lengths. The row extensions are unequal lengths, the winding portions are unequal lengths, and the second row extensions are unequal lengths.

By adjusting the length of the parallel signal lines in each part of a group of signal lines including the winding part, the impact of bending on the length of the parallel signal lines at different locations can be reduced, so that the lengths of the signal lines within a group of signal lines are completely consistent.

Although the embodiment shown in FIGS. 6A and 6B only illustrates two parallel signal lines, in actual applications, when the group of signal lines contains more parallel signal lines, the method shown in FIGS. 6A and 6B can be used. The principle of the embodiment adjusts the length of the signal lines at various locations, so that the lengths of the signal lines in a group of signal lines are completely consistent.

Embodiments of the present disclosure can make the wiring lengths between circuit modules at all levels uniform by adjusting the arrangement sequence between the input and output annular series circuit modules and the layout of the input terminals and output terminals.

In one embodiment, the first-level circuit module 1, the second-level circuit module 2, the third-level circuit module 3, and the fourth-level circuit module 4 are DFEs in the data input buffer circuit (Data Queue Input Buffer, DQ IB) Circuit module, the first-level circuit module 1 is an odd-numbered rising edge sampling module, the second-level circuit module 2 is an odd-numbered falling edge sampling module, the third-level circuit module 3 is an even-numbered rising edge sampling module, and the fourth-level circuit module 4 is an even-numbered falling edge sampling module. The first group of signal lines S1, the second group of signal lines S2, the third group of signal lines S3, and the fourth group of signal lines S4 are all DFE signal lines.

In other embodiments of the present disclosure, the first-level circuit module 1, the second-level circuit module 2, the third-level circuit module 3, and the fourth-level circuit module 4 can also be other ring-shaped series circuit modules, such as a ring oscillator. The number of oscillation units is not limited to four.

7A and 7B are schematic diagrams of circuit modules corresponding to the circuit layout structure in an embodiment of the present disclosure.

Referring to FIG. 7A and FIG. 7B , in one embodiment, N-level circuit modules 71 having input and output annular series connections are connected through N sets of signal lines 72 . The N-level circuit modules 71 are arranged along the first direction. The N-level circuit modules 71 Any level in is set as the first level circuit module. The circuit module connected to the input end of the i-th level circuit module is called the input circuit module of the i-th level circuit module. The circuit module connected to the output end of the i-th level circuit module is called is the output circuit module of the i-th level circuit module, 1≤i≤N.

The N-level circuit module 71 includes two edge circuit modules A located on the edge in the first direction and an intermediate circuit module B not located on the edge. The edge circuit module A, the input circuit module of the edge circuit module A, and the output of the edge circuit module A The circuit modules are arranged adjacently in the first direction or the opposite direction of the first direction. The types of input circuit modules and output circuit modules of the edge circuit module A include edge circuit module A and intermediate circuit module B.

If an intermediate circuit module B is not connected to the edge circuit module A, in the first direction, there is one circuit module B between the intermediate circuit module B and the input circuit module of the intermediate circuit module B, and the intermediate circuit module B and the intermediate circuit module B The output circuit modules are separated by one circuit module, N≥3.

At this time, the first set of edge signal lines connected to the edge circuit module A can be set to extend along the first direction and have a third length L3, and are arranged in the first row in the second direction; the second set of edge signal lines connected to the edge circuit module A can be set The signal line includes a first portion extending along the first direction. The first portion is arranged in the second row in the second direction and has a fourth length L4, and the fourth length L4 is smaller than the third length L3.

At this time, if an intermediate circuit module B is not connected to the edge circuit module A, then the two sets of signal lines connected to the intermediate circuit module B both extend along the first direction and have a third length, and the two sets of signal lines are respectively arranged on the first row and second row.

In the embodiment shown in FIG. 7A , the input terminal and the output terminal of each edge circuit module A are respectively located in the first and second rows in the second direction, and the input terminal and the output terminal of each intermediate circuit module B are located in the second row. arranged side by side.

In the embodiment shown in FIG. 7B , in each edge circuit module A, the input terminal and the output terminal are arranged side by side in the first direction, and in each intermediate circuit module B, the input terminal and the output terminal are arranged in the first direction. Side by side settings. At this time, the signal lines of the second group of signal lines connected to the edge circuit module A also include a second part C. The second part is a curve. The first end of the curve is connected to the first part. The second end of the curve is located at a different point from the first part. One line.

The shape of the curve includes but is not limited to a U-shaped bend (as shown in Figure 7B). In other embodiments, for example, when the third length L3 is much larger than the fourth length L4, the winding group signal line A can also be The shape is set to more bends, or bends with larger angles, such as arc bends, multiple interconnected U-shaped bends, rectangular polylines, acute-angled polylines, obtuse-angled polylines, etc. The embodiments of the present disclosure do not limit the specific shape of the curves. , only need to ensure that one end of the winding group signal line is in the first or second row, and the other end is in the second or first row.

When the number of circuit modules is greater than 4, you can directly add circuit modules according to the embodiment shown in Figure 7A and Figure 7B, and adjust the length of the signal line according to the wiring method shown in Figures 2A to 6B. The expansion here is relatively simple and no longer required. Repeat.

But when the number of circuit modules is 3, the wiring will be somewhat different.

Referring to Figures 8A to 8D,

circuit modules

1, 2, and 3 are connected in series in a ring shape. The layout method can be as shown in Figures 8A and 8B with 1, 2, and 3 arranged along the first direction, or as shown in Figures 8C and 8B. As shown in 8D, the 1, 3, and 2 layout is performed along the first direction. Alternatively, the layout may also be carried out in the opposite direction of the first direction, which is not shown one by one here.

When corresponding to the wiring, curves can be set in a group of signal lines connected to the edge circuit module so that the signal line lengths of each group of signal lines are equal. The specific shape of the curve can be shown in Figures 8A to 8D.

When the embodiment shown in FIGS. 8A to 8D includes multiple parallel signal lines, the length of the signal lines can also be adjusted in the embodiment shown in FIGS. 6A and 6B , which will not be described again.

According to a second aspect of the present disclosure, a chip is provided, including any of the above circuit layout structures.

To sum up, chips using the circuit layout structure and wiring provided by embodiments of the present disclosure have better signal balancing effects. When each circuit module includes a DFE function, the wiring lengths between the DFE modules can be effectively balanced. Ensure phase accuracy and improve signal quality.

It should be noted that although several modules or units of equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into being embodied by multiple modules or units.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Industrial applicability

Claims

A circuit layout structure including:

The first-level circuit module, the second-level circuit module, the third-level circuit module, and the fourth-level circuit module are input and output in annular series. The first-level circuit module, the second-level circuit module, the third-level circuit module The circuit module and the fourth-level circuit module are arranged along the first direction, and the first-level circuit module and the third-level circuit module are respectively located at two edges in the first direction, or the second The first-level circuit module and the fourth-level circuit module are respectively located on two edges in the first direction;

Wherein, the first-level circuit module and the second-level circuit module are connected through a first set of signal lines, and the second-level circuit module and the third-level circuit module are connected through a second set of signal lines. The third-level circuit module and the fourth-level circuit module are connected through a third group of signal lines, and the fourth-level circuit module and the first-level circuit module are connected through a fourth group of signal lines. The first group of signal lines and the third group of signal lines each have a first length, and the second group of signal lines and the fourth group of signal lines each have a second length.
The circuit layout structure of claim 1, wherein the first-level circuit module, the second-level circuit module, the fourth-level circuit module, and the third-level circuit module are arranged in the first direction. Or they are arranged sequentially in the opposite direction of the first direction.
The circuit layout structure of claim 1, wherein the first-level circuit module, the fourth-level circuit module, the second-level circuit module, and the third-level circuit module are arranged in the first direction. Or they are arranged sequentially in the opposite direction of the first direction.
The circuit layout structure according to claim 2 or 3, wherein,

The output end of the first-level circuit module, the input end of the second-level circuit module, the output end of the second-level circuit module, and the input end of the third-level circuit module are arranged along the first row;

The input end of the first-level circuit module, the output end of the fourth-level circuit module, the input end of the fourth-level circuit module, and the output end of the third-level circuit module are arranged along the second row;

The first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.
The circuit layout structure of claim 4, wherein the first group of signal lines and the second group of signal lines are arranged along the first row, and the third group of signal lines and the fourth group of signal lines are arranged along the first row. The lines are arranged along the second row.
The circuit layout structure according to claim 2 or 3, wherein,

The input end of the first-level circuit module, the output end of the fourth-level circuit module, the input end of the fourth-level circuit module, and the output end of the third-level circuit module are arranged along the first row;

The output end of the first-level circuit module, the input end of the second-level circuit module, the output end of the second-level circuit module, and the input end of the third-level circuit module are arranged along the second row;

The first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.
The circuit layout structure of claim 6, wherein the first group of signal lines and the second group of signal lines are arranged along the second row, and the third group of signal lines and the fourth group of signal lines are arranged along the second row. The lines are laid out along the first row.
The circuit layout structure according to claim 2, wherein,

The output end of the first-level circuit module, the input end of the first-level circuit module, the output end of the fourth-level circuit module, and the input end of the fourth-level circuit module are arranged along the first row;

The input end of the second-level circuit module, the output end of the second-level circuit module, the input end of the third-level circuit module, and the output end of the third-level circuit module are arranged along the second row;

The second group of signal lines is arranged along the second row, and the fourth group of signal lines is arranged along the first row;

The first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.
The circuit layout structure according to claim 2, wherein,

The input end of the second-level circuit module, the output end of the second-level circuit module, the input end of the third-level circuit module, and the output end of the third-level circuit module are arranged along the first row;

The output end of the first-level circuit module, the input end of the first-level circuit module, the output end of the fourth-level circuit module, and the input end of the fourth-level circuit module are arranged along the second row;

The second group of signal lines is arranged along the first row, and the fourth group of signal lines is arranged along the second row;

The first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.
The circuit layout structure according to claim 8 or 9, wherein,

The first group of signal lines includes a first wiring portion arranged in the first row, a second wiring portion arranged in the second row, and a first winding portion arranged along the second direction, the The first wiring part and the second wiring part are connected through the first winding part;

The third group of signal lines includes a third wiring portion arranged in the second row, a fourth wiring portion arranged in the first row, and a second winding portion arranged along the second direction, the The third wiring part and the fourth wiring part are connected through the second winding part;

Wherein, the first length is equal to the second length.
The circuit layout structure according to claim 3, wherein,

The input end of the first-level circuit module, the output end of the first-level circuit module, the input end of the second-level circuit module, and the output end of the second-level circuit module are arranged along the first row;

The input end of the third-level circuit module, the output end of the third-level circuit module, the input end of the fourth-level circuit module, and the output end of the fourth-level circuit module are arranged along the second row;

The first group of signal lines is arranged along the first row, and the third group of signal lines is arranged along the second row;

The first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.
The circuit layout structure according to claim 3, wherein,

The input end of the third-level circuit module, the output end of the third-level circuit module, the input end of the fourth-level circuit module, and the output end of the fourth-level circuit module are arranged along the first row;

The input end of the first-level circuit module, the output end of the first-level circuit module, the input end of the second-level circuit module, and the output end of the second-level circuit module are arranged along the second row;

The third group of signal lines is arranged along the first row, and the first group of signal lines is arranged along the second row;

The first row and the second row are parallel to each other and arranged along a second direction, and the second direction is perpendicular to the first direction.
The circuit layout structure as claimed in claim 11 or 12, wherein,

The second group of signal lines includes a fifth wiring portion arranged in the first row, a sixth wiring portion arranged in the second row, and a third winding portion arranged along the second direction, the The fifth wiring part and the sixth wiring part are connected through the third winding part;

The fourth group of signal lines includes a seventh wiring portion arranged in the first row, an eighth wiring portion arranged in the second row, and a fourth winding portion arranged along the second direction, the The seventh wiring part and the eighth wiring part are connected through the fourth winding part;

Wherein, the first length is equal to the second length.
The circuit layout structure of claim 1, wherein the first group of signal lines, the second group of signal lines, the third group of signal lines, and the fourth group of signal lines each include two intervals at Signal lines of equal width equal to the preset value.
The circuit layout structure of claim 1, wherein the first-level circuit module is an odd-numbered rising edge sampling module, the second-level circuit module is an odd-numbered falling edge sampling module, and the third-level circuit module is an even-numbered rising edge sampling module, the fourth-level circuit module is an even-numbered falling edge sampling module, the first set of signal lines, the second set of signal lines, the third set of signal lines, the third The four sets of signal lines all include decision feedback equalization signal lines.
A chip including the circuit layout structure according to any one of claims 1 to 15.