KR100353810B1 - Input buffer having the best suited set-up and hold time in semiconductor memory device - Google Patents

Abstract

The present invention relates to a method for optimizing the set-up and hold time of an input buffer stage in a semiconductor memory device. More particularly, the present invention relates to a method of optimizing the input buffer stage near a pad. Changes in the manufacturing process by having a constant set-up and hold time in a way to be input to the latch stage with the same time delay while having a delay and delay by line rather than by inverter or capacitor. The present invention relates to a method for having an optimal set-up and hold time regardless of a change in power supply voltage and temperature. To this end, the present invention is an input buffer unit consisting of an input buffer stage and a latch stage, a buffer for receiving a signal through a pad to which an external signal is input and a latch unit for inputting the buffer output through a line delay, the two input to the latch unit When the two input signals are input to the latch portions through different paths, the same line delay from the buffer receiving the signals through the pads to the latch portions is included.

Description

Input buffer having the best suited set-up and hold time in semiconductor memory device

TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly, to an input buffer having an optimal set-up and hold time.

In general, in a semiconductor memory device, a set-up and hold time is determined due to a difference in time delay between two different signals coming out of a pad to a latch unit. .

1 is a unit block diagram of an input buffer according to the prior art, in which signals input through the pads 1 and 5 are input to the latch unit 4 via the buffers 2 and 6, from the pad 1. In order to adjust the difference in time delay between the incoming signal 1 and the incoming signal 2 from the pad 5, the delay circuit 3 composed of an inverter and a capacitor is latched with a buffer 2 and a latch. It is adopted between the sections (4). The output terminal of the signal 1 having passed through the delay circuit 3 and the signal 2 having passed through the line delay 6 flows into the latch portion 4, while the latch portion 4 is receiving the signal 1 as an input. When is applied, the logic state of signal 1 is latched. At this time, the state in which the logic level of the signal 1 is received as an input by the latch unit 4 is a set-up state, and the signal has a hold time from the time when the signal 2 is input and the logic state of the signal 1 is latched.

However, if the delay circuit 3 implemented with such an inverter and capacitor is used, the time delay value is changed due to factors in the manufacturing process. Therefore, it is necessary to redesign to adjust the time delay, from the pad 1 to the buffer 2. Since the delay of the coming line (Line) and the line input from the pad (5) to the buffer 6 is different from each other, this problem has to be adjusted by using a delay circuit (3) consisting of an inverter or a capacitor.

In order to solve the above problem, the set-up and hold determined by the difference in the time delay of the two signals by making the two input signals have the same time delay to equalize the time delay from the pad to the latch portion. The goal is to make the time constant and to optimize the set-up and hold times regardless of changes in the manufacturing process, supply voltage, or temperature.

1 is a unit block diagram of an input buffer according to the prior art;

2 is a unit block diagram of a plurality of input buffers according to the prior art;

3 is an input buffer unit block diagram of the present invention;

Figure 4 is a block diagram of a plurality of input buffer unit of the present invention.

* Description of the main parts of the drawing

11: pad 12: buffer

13: Line delay 18: Buffer and latch part

An input buffer of the present invention for achieving the above object, the input buffer of the semiconductor memory device, the first buffer for receiving the first input signal from the first pad; A second buffer receiving a second input signal from a second pad; And a latch unit configured to receive outputs of the first buffer and the second buffer, respectively, and the delay from the first pad to the latch unit is the same as the delay from the second pad to the latch unit. .

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a conceptual block diagram of an input buffer for receiving an input signal in a semiconductor memory device, and a buffer 12 for receiving a signal 1 and a signal 2 passing through pads 11 and 15 receiving an external input signal as an input, And a latch 14 for receiving a signal passing through the line delays 13 and 17 as an input. If the input capacitances seen from the pads are equal by making the lengths of the lines of the signal 1 output through the pad 11 and the signal 2 output through the pad 15 the same, the time delay between the signal 1 and the signal 2 is the same. The signal 1 and the signal 2 having the same time delay value are input to the buffers 12 and 16 designed with the same layout, and the signals input to the buffer are buffered to have the same time delay. It is input to the latch unit 14 via the line delay 13 and the line delay 17 laid out in the same length.

The set-up time and the hold time are determined by the difference between the two input signals in the latch unit 14 which inputs the two input signals, and the time delay value from the pads of the two signals input to the latch unit 14 is determined. If not by inverter or capacitor, but by line, the set-up and hold times are independent of process changes, power supply voltages, and temperature changes.If they are the same, the set-up and hold times are constant from pad to latch. Having a value allows for optimal set-up and hold times.

4 shows a signal (signal 2, signal 3, signal 4, signal 5) input from a plurality of pads 21a, 21b, 21d, and 21e and a signal 1 input from one pad 21c. 18a, 18b, 18c, 18d) is a conceptual block diagram showing input. Here, the buffer and latch units 18a, 18b, 18c, and 18d are referred to as a group of buffers, line delays, and latches in FIG. The line delay 19a having the signal 1 through the buffer 20 located near the pad 18b is the same as the line delay laid out in the buffer and latch unit 18 to which the signal 1 is input. Therefore, the time delay from the pads 21a, 21b, 21d, and 21e to the buffer and latch portions 18a, 18b, 18c, and 18d is the same as the time delay from the pad 21c to the buffer and latch portion 18. Done. Differences in the time delay between signals 1, 2, 3, 4 and 5 in buffers and latches 18a, 18b, 18c, and 18d to which signals 1, 2, 3, 4 and 5 are inputted The set-up and hold time, which is determined as, consists of delays due to lines with constant time delays, so they are constant regardless of process changes or supply voltage and temperature changes.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention equalizes the time delay for the two signals input to the input buffer of the semiconductor memory device to reach the latch unit by using the delay caused by the line, regardless of the change in the manufacturing process, power supply voltage, and temperature. It is possible to optimize the set-up and hold time and to have a constant set-up and hold time at all times by equalizing the delay by the line from the buffer to the latch section between the two input signals.

Claims (6)

In the input buffer of the semiconductor memory device, A first buffer receiving a first input signal from the first pad; A second buffer receiving a second input signal from a second pad; And a latch unit configured to receive outputs of the first buffer and the second buffer, respectively. Equipped with And the delay from the first pad to the latch unit is the same as the delay from the second pad to the latch unit. The method of claim 1, And a signal line delay from the first buffer to the latch portion and a signal line delay from the second buffer to the latch portion are equal to each other. The method of claim 1, An input buffer of a semiconductor memory device, characterized in that the first buffer and the second buffer are designed with the same layout. In a semiconductor memory device, A first buffer receiving a first input signal from the first pad; A second buffer receiving a second input signal from a second pad; A third buffer receiving a third input signal from a third pad; And a latch unit configured to receive output signals from the first pad, the second pad, and the third pad without a delay circuit. Delays from the first pad, the second pad, and the third pad to the latch portion are designed to be identical to each other. A third from the first pad to the first buffer when the first signal line delay from the second pad to the second buffer is greater than the second signal line delay from the third pad to the third buffer. The input buffer of the semiconductor memory device, characterized in that the signal line delay is laid out in the same manner as the first signal line delay. The method of claim 4, wherein The first buffer, the second buffer, and the third buffer are identically laid out to each other. The method of claim 4, wherein And a fourth signal line from the first buffer to the latch unit and a fifth signal line from the second buffer to the latch unit are laid out to have the same delay.