KR102277464B1 - Method and Apparatus for Transmitting Data using Finite Impulse Response - Google Patents

Abstract

Disclosed are a data transmission method using a finite impulse response and an apparatus therefor. According to an embodiment of the present invention, a transmitter using a finite impulse response comprises: a data sequence generating unit for generating a parallelized data sequence; a serializer that receives the data sequence and serializes it and generates a serial data pair generated based on serialized serial data; a tap signal generating unit receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and a transmission driver that receives the tap control signal, calculates a weight for each of one or more tap signals, and outputs a channel loss compensation signal, in which a channel loss is compensated, to a receiving terminal by applying the weight.

Description

Method and Apparatus for Transmitting Data using Finite Impulse Response

The present invention relates to a method and apparatus for transmitting data using a finite impulse response in a high-speed wired data transmission environment.

The content described in this section merely provides background information on the embodiments of the present invention and does not constitute the prior art.

Recently, although the data requirement for chip-to-chip communication is gradually increasing, the increase in the number of pads to solve the finite channel bandwidth is insufficient. Limited package and channel bandwidth can compensate for losses by utilizing various equalization techniques on the chip. The application of equalization technology in a wired data transmitter has the following advantages. (1) In most digital blocks, the advantage of speed due to the channel minimization of CMOS can be taken as it is. (2) It has an efficient pre-emphasis coefficient in consideration of various channel conditions by utilizing the segment structure in the driver to which FIR is applied. (3) Well-aligned clock timing information can be used for high-speed timing design without clock recovery. However, when an equalization technique is applied in a wired data transmitter, the complexity of the circuit increases according to the implementation of the equalization circuit, and more power is consumed due to an increase in load loading due to the segment structure.

The present invention generates at least one tap signal based on a serial data pair in which a data sequence is serialized, and outputs a channel loss compensation signal in which the channel loss is compensated by applying a weight generated to each of the at least one tap signal to the receiving terminal. A main object is to provide a method for transmitting data using a finite impulse response and an apparatus therefor.

According to an aspect of the present invention, a transmitter using a finite impulse response for achieving the above object includes: a data sequence generator for generating a parallelized data sequence; a serializer that receives the data sequence and serializes it, and generates a serial data pair generated based on the serialized serial data; a tap signal generator receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and a transmission driver that receives the tap control signal, calculates a weight for each of the at least one tap signal, and outputs a channel loss compensation signal in which the channel loss is compensated by applying the weight to the receiving terminal.

Further, according to another aspect of the present invention, there is provided a data transmission method using a finite impulse response for achieving the above object, comprising: a data sequence generating step of generating a parallelized data sequence; a serialization step of receiving the data sequence and serializing it, and generating a serial data pair generated based on the serialized serial data; a tap signal generating step of receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and a driver driving step of receiving the tap control signal, calculating a weight for each of the at least one tap signal, and outputting a channel loss compensation signal in which the channel loss is compensated to a receiving terminal.

According to another aspect of the present invention, a high-speed wired data communication system for achieving the above object includes: a first chip for generating data; a second chip for obtaining a channel loss compensation signal in which the channel loss of the data is compensated, and determining and storing data to be stored; and a data sequence generator generating a parallelized data sequence based on the data. a serializer that receives the data sequence and serializes it, and generates a serial data pair generated based on the serialized serial data; a tap signal generator receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and a transmitter including a transmission driver receiving the tap control signal, calculating a weight for each of the at least one tap signal, and outputting the channel loss compensation signal in which the channel loss is compensated.

As described above, the present invention has an effect of increasing data transmission accuracy in a high-speed wired data communication environment.

In addition, the present invention has an effect of minimizing inter-signal interference (ISI) noise that inevitably occurs due to a load of a channel in a high-speed data transmission/reception situation by applying a finite impulse response filter to the transmitter.

1 is a block diagram schematically showing a high-speed wired data communication system according to an embodiment of the present invention.
2 is a block diagram schematically showing a transmitter using a finite impulse response according to the first embodiment of the present invention.
3 is a block diagram schematically showing a transmitter using a finite impulse response according to a second embodiment of the present invention.
4 is a flowchart illustrating a data transmission method using a finite impulse response according to an embodiment of the present invention.
5 is a block diagram schematically showing the configuration of a memory interworking with a transmitter according to an embodiment of the present invention.
6 is a diagram illustrating an operation of a transmitter using a finite impulse response according to an embodiment of the present invention.
7A and 7B are diagrams for explaining the configuration and operation of a tap signal generator according to an embodiment of the present invention.
8A and 8B are diagrams for explaining the configuration and operation of a transmission driver according to an embodiment of the present invention.
9A and 9B are diagrams illustrating measurement results of a transmitter using a finite impulse response according to an embodiment of the present invention.
10 is an exemplary diagram illustrating a transmitter and a measuring apparatus using a finite impulse response according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, preferred embodiments of the present invention will be described below, but the technical spirit of the present invention is not limited thereto and may be variously implemented by those skilled in the art without being limited thereto. Hereinafter, a data transmission method using a finite impulse response proposed by the present invention and an apparatus therefor will be described in detail with reference to the drawings.

1 is a block diagram schematically showing a high-speed wired data communication system according to an embodiment of the present invention.

The high-speed wired data communication system 100 according to the present embodiment includes a first chip 110 , a transmitter 120 , and a second chip 130 . The high-speed wired data communication system 100 of FIG. 1 is according to an embodiment, and not all blocks shown in FIG. 1 are essential components, and some blocks included in the high-speed wired data communication system 100 in another embodiment. These may be added, changed or deleted.

The first chip 110 refers to a chip of the transmitting end for high-speed wired data transmission. The first chip 110 generates and outputs data to be transmitted to the second chip 130 via the transmitter 120 .

The first chip 110 may be a module for controlling components of an electronic device. The first chip 110 controls an operation of installing or executing a program, and may execute a program stored in the memory, read data stored in the memory, or store new data in the memory. For example, the first chip 110 may include a central processing unit (CPU), a microprocessor, a processor core, a multiprocessor, an application-specific integrated circuit (ASIC), It may be a processing device such as a field programmable gate array (FPGA), but is not necessarily limited thereto.

The transmitter 120 transmits data between the first chip 110 and the second chip 130 .

The transmitter 120 generates at least one tap signal based on a serial data pair in which a data sequence is serialized, and outputs a channel loss compensation signal in which a channel loss is compensated by applying a weight generated to each of the at least one tap signal. perform the action A detailed description of the transmitter 120 according to this embodiment will be described in FIG. 2 .

Meanwhile, the transmitter 120 illustrated in FIG. 1 is described as performing only transmission, but is not necessarily limited thereto, and may be implemented as a transceiver that performs transmission or reception.

The second chip 130 refers to a chip of the receiving end for receiving high-speed wired data. The second chip 130 receives data generated by the first chip 110 from the transmitter 120 and stores the received data.

The second chip 130 may temporarily or permanently store data processed by the electronic device. For example, the second chip 130 may be a volatile memory device or a nonvolatile memory device, or may include both a volatile memory device and a nonvolatile memory device, but is not limited thereto. Among them, non-volatile memory is a read-only memory (ROM), a programmable memory (Programmable ROM, PROM), a volatile programmable memory (Erasable PROM, EPROM), an electrically volatile programmable memory (Electrically EPROM, EEPROM) or can be flash The volatile memory may be random access memory (RAM), which is used as an external high-speed cache.

2 is a block diagram schematically showing a transmitter using a finite impulse response according to the first embodiment of the present invention.

The transmitter 120 according to the first embodiment of the present invention includes a data sequence generator 201 , a serializer 210 , a tap signal generator 220 , and a transmission driver 230 . The transmitter 120 of FIG. 2 is according to an embodiment, and not all blocks shown in FIG. 2 are essential components, and in other embodiments, some blocks included in the transmitter 120 may be added, changed, or deleted. have.

The data sequence generator 201 generates and outputs a plurality of independent data sequences having a preset data transmission rate. Here, the data sequence generator 201 may generate a plurality of parallelized data sequences based on data obtained from the first chip 110 . Specifically, according to an embodiment of the present invention, it is possible to generate 16 independent data sequences each having a data transmission rate of 750 Mbit/s, which is a preset data transmission rate, and the above-described 16 independent data sequences are performed in parallel. They can be listed and printed. However, the above-described example is only an example for explaining an embodiment of the present invention and is not limited thereto, and the data sequence generator 201 may generate a plurality of independent data sequences having various transmission rates, It is also possible to generate one independent bit data.

The serializer 210 according to an embodiment of the present invention receives the data sequence generated by the data sequence generator 110 and serializes the applied data sequence at a preset data rate to n (n is a natural number equal to or greater than 2). ) can be output as serial data. Here, the preset data transfer rate of the serializer 210 is 1/4 of the data transfer rate of the transmitter 120 and means a data transfer rate that is 1/2 of the rate of the clock signal.

The serializer 210 receives and serializes a data sequence, and generates and outputs a serial data pair generated based on the serialized serial data.

The serializer 210 according to an embodiment of the present invention receives an applied data sequence for each input port, serializes it at a preset data rate, and outputs the first serial data and the second serial data, which are two serial data sequences. can Specifically, the serializer 210 may output a serial data pair including first serial data obtained by combining an even-numbered data sequence among serial data and second serial data obtained by combining an odd-numbered data sequence among the serial data. .

The serializer 210 outputs a serial data pair including the first serial data and the second serial data to the tap signal generator 220 to generate a tap signal.

The tap signal generator 220 receives a serial data pair from the serializer 210, generates a plurality of tap signals from the serial data pair according to a predetermined method, and combines the generated tap signals to obtain a tap control signal. to output

The tap signal generator 220 receives a serial data pair, generates and outputs a tap control signal including at least one tap signal generated through a timing delay. Specifically, the tap signal generator 220 receives a serial data pair including the first serial data and the second serial data, delays the timing of the serial data pair to generate a plurality of nodes, and at each of the plurality of nodes A data sequence responding to one clock signal is extracted as a plurality of tap signals, and a tap control signal is generated by combining the extracted tap signals.

The tap signal generator 220 generates each of three serial data sequences in response to one clock signal at each of a plurality of nodes including serial data pairs delayed at different timings to a plurality of tap signals PRE TAP, MAIN TAP, and POST. TAP). The tap signal generator 220 may generate a tap control signal by sequentially combining a plurality of tap signals according to a sequence order.

The tap signal generator 220 may generate a plurality of tap control signals for each of a rising edge or a falling edge of the clock signal. Here, the speed of the clock signal of the tap signal generator 220 is preferably 1/2 of the data transmission speed of the transmitter 120 , but is not limited thereto.

The tap signal generator 220 is configured to generate a first tap control signal that is an even-numbered tap control signal and a second tap control signal that is an odd-numbered tap control signal based on a sequence of a specific tap signal MAIN TAP of each of the plurality of tap control signals. may be transmitted to the transmission driver 230 . Here, the tap signal generator 220 may transmit the first tap control signal and the second tap control signal to the transmission driver 230 at the same time, but is not limited thereto, and a specific tap signal ( It may be transmitted alternately according to the sequence order of the MAIN TAP).

The transmission driver 230 receives the tap control signal output from the tap signal generator 220 , calculates a weight for the tap control signal, and applies the calculated weight to output a channel loss compensation signal in which the channel loss is compensated. . The transmitting driver 230 transmits the output channel loss compensation signal to the receiving end through the channel. Here, the channel loss compensation signal means a data transmission signal for which the channel loss is compensated.

The transmission driver 230 may calculate a weight for each of the plurality of tap signals included in the tap control signal, and apply each of the calculated weights to each of the plurality of tap signals to compensate for the channel loss.

The transmission driver 230 includes a plurality of segment driver groups, and each segment driver group includes a plurality of segment drivers. Here, the segment driver may include a plurality of transistors, and the plurality of transistors may be turned on or off by receiving a tap control signal output from the tap signal generator 220 . Each of the plurality of transistors may be implemented as a metal oxide semiconductor field effect transistor (MOSFET), which is a three-terminal semiconductor device. Specifically, each of the plurality of metal oxide semiconductor field effect transistors may be an NMOS or a PMOS configured as a channel of an N-type semiconductor or a P-type semiconductor.

The transmission driver 230 may include the same number of segment driver groups as the number of tap signals included in the tap control signal.

Each of the plurality of segment driver groups included in the transmission driver 230 receives each of at least one tap signal included in the tap control signal, and calculates a weight of each tap signal based on each of the at least one tap signal and the clock signal. Calculate.

The transmission driver 230 applies a weight of each tap signal to each of the at least one tap signal, sums the at least one tap signal to which the weight is applied, and calculates and outputs a channel loss compensation signal. The transmitting driver 230 transmits the calculated channel loss compensation signal to the receiving end through the channel. Here, the receiving end may be the second chip 130 , but is not limited thereto.

The transmission driver 230 according to the present embodiment may include a first segment driver group, a second segment driver group, and a third segment driver group. Here, each of the at least one tap signal included in the tap control signal is input to a different segment driver group, and each of the different segment driver groups may calculate a weight for the input tap signal. For example, when the first tap signal PRE TAP, the second tap signal MAIN TAP, and the third tap signal POST TAP are included in the tap control signal, the first segment driver group includes the first tap signal ( PRE TAP), the second segment driver group calculates a weight for the second tap signal MAIN TAP, and the third segment driver group calculates a weight for the third tap signal POST TAP can do.

3 is a block diagram schematically showing a transmitter using a finite impulse response according to a second embodiment of the present invention.

The transmitter 120 according to the second embodiment of the present invention includes a data sequence generator 201 , a serializer 210 , a tap signal generator 220 , a first segment driver 310 , and a second segment driver 320 . ) is included. The transmitter 120 of FIG. 2 is according to an embodiment, and not all blocks shown in FIG. 2 are essential components, and in other embodiments, some blocks included in the transmitter 120 may be added, changed, or deleted. have.

The operations of the data sequence generator 201 , the serializer 210 , and the tap signal generator 220 of the transmitter 120 according to the second embodiment are the same as those of the transmitter 120 according to the first embodiment described in FIG. 2 . Descriptions that are the same and overlap with those described in the transmitter 120 according to the first embodiment will be omitted.

The first transmission driver 310 has the same structure as the transmission driver 300 included in the transmitter 120 according to the first embodiment. That is, the first transmission driver 310 receives the tap control signal output from the tap signal generator 220 , calculates a weight for the tap control signal, and applies the calculated weight to compensate for the channel loss. output a signal.

Meanwhile, the second transmission driver 320 has a structure designed to output a channel loss inverse compensation signal having an opposite value to the channel loss compensation signal. In other words, when the channel loss compensation signal is 0.75, the second transmission driver 320 outputs 0.25, which is a value obtained by subtracting the channel loss compensation signal from 1.

The channel loss compensation signal and the inverse channel loss compensation signal output from the first segment driver 310 and the second segment driver 320 are transmitted to the receiving terminal 130 .

4 is a flowchart illustrating a data transmission method using a finite impulse response according to an embodiment of the present invention.

The data sequence generator 201 of the transmitter 120 generates a parallelized data sequence based on the data acquired from the first chip 110 (S410).

The serializer 210 of the transmitter 120 receives and serializes a data sequence, and generates and outputs a serial data pair generated based on the serialized serial data (S420). The serializer 210 may receive the applied data sequence for each input port, serialize it at a preset data rate, and output first serial data and second serial data, which are two serial data sequences.

The tap signal generator 220 of the transmitter 120 receives a serial data pair and generates a tap control signal including a plurality of tap signals (S430). The tap signal generator 220 receives a serial data pair, generates a plurality of nodes by delaying the timing of the serial data pair, and converts a data sequence responding to one clock signal at each of the plurality of nodes into a plurality of tap signals. extracted, and combining the plurality of extracted tap signals to generate a tap control signal.

The transmission driver 230 of the transmitter 120 calculates a weight for each tap signal and applies the weight to generate a channel loss compensation signal (S440). The transmission driver 230 calculates a weight of each of the plurality of tap signals included in the tap control signal, and applies each of the calculated weights to each of the plurality of tap signals to generate and output a channel loss compensation signal for compensating for channel loss. do.

Data is stored at the receiving end based on the channel loss compensation signal (S450).

Although it is described that each step is sequentially executed in FIG. 4 , the present invention is not limited thereto. In other words, since it may be applicable to changing and executing the steps described in FIG. 4 or executing one or more steps in parallel, FIG. 4 is not limited to a time-series order.

The data transmission method using the finite impulse response according to the present embodiment illustrated in FIG. 4 may be implemented as an application (or program) and recorded in a terminal device (or computer) readable recording medium. An application (or program) for implementing the data transmission method using a finite impulse response according to the present embodiment is recorded, and a terminal device (or computer) readable recording medium is any storage medium in which data readable by a computing system is stored. Recording devices or media of any kind.

5 is a block diagram schematically showing the configuration of a memory interworking with a transmitter according to an embodiment of the present invention.

5A shows the configuration of the memory 130 interworking with the transmitter 120 according to the first embodiment. The memory 130 according to the first embodiment of the present invention includes a first comparison unit 510 , a first determination unit 520 , and a storage unit 530 .

The memory 130 of FIG. 5A receives the channel loss compensation signal from the transmitter 120, compares a preset reference value with the result value of the channel loss compensation signal, determines and stores data to be stored.

The first comparator 510 obtains a channel loss compensation signal from the transmitter 120 and compares the channel loss compensation signal with a preset reference value (eg, 0.5).

The first determination unit 520 determines the data to be stored based on the comparison result of the first comparison unit 510 and stores it in the storage unit 530 .

If the value of the channel loss compensation signal is equal to or greater than the reference value according to the comparison result, the first determination unit 520 determines that the stored data is '1' and stores it. On the other hand, if the value of the channel loss compensation signal is less than the reference value according to the comparison result, the first determination unit 520 determines that the stored data is '0' and stores it.

5B shows the configuration of the memory 130 interworking with the transmitter 120 according to the second embodiment. The memory 130 according to the second embodiment of the present invention includes a second comparison unit 512 , a second determination unit 522 , and a storage unit 530 .

The memory 130 of FIG. 5B receives the channel loss compensation signal and the channel loss inverse compensation signal from the transmitter 120, and data to be stored based on the difference between the channel loss compensation signal and the inverse channel loss compensation signal judged and saved.

The second comparator 512 obtains the channel loss compensation signal and the inverse channel loss compensation signal from the transmitter 120, calculates a difference value between the channel loss compensation signal and the inverse channel loss compensation signal, and calculates the sign value of the difference. print out

The second determination unit 522 determines data to be stored based on the sign value obtained from the second comparison unit 512 , and stores it in the storage unit 530 .

If the acquired sign value is a positive sign, the second determining unit 522 determines that the stored data is '1' and stores it. On the other hand, when the acquired sign value is a negative sign, the second determining unit 522 determines that the stored data is '0' and stores it.

6 is a diagram illustrating an operation of a transmitter using a finite impulse response according to an embodiment of the present invention.

In FIG. 6, the half-rate transmitter 600 using a finite impulse response based on 12 Gbit/s will be described. Here, the half-rate transmitter 600 may be the same as the transmitter 120 of FIG. 2 .

The transmitter 600 according to the present invention includes a PRBS generator 610 , a serializer 620 , a tap signal generator 630 , a transmission driver 640 , and a clock signal generator 650 . Here, the PRBS generator 610 of FIG. 6 may correspond to the data sequence generator 201 , and the serializer 620 of FIG. 6 may correspond to the serializer 210 . Also, the tap signal generator 630 of FIG. 6 may correspond to the tap signal generator 220 , and the transmission driver 640 of FIG. 6 may correspond to the transmission driver 230 .

The PRBS generator 610 generates 16 x 750 Mbit/s parallel PRBS data patterns (data sequences) having ^{2 15} -1 patterns and 2 ^{31 -1 patterns.}

The serializer 620 serializes 16 parallel PRBS data patterns into first serial data DIN0 which is even-numbered data and second serial data DIN1 which is odd-numbered data at a high speed.

The tap signal generator 630 receives the first serial data and the second serial data serialized from the serializer 620, delays 6 Gbit/s data with an appropriate timing, DODD corresponding to a predetermined clock signal, A first tap signal PRE TAP, a second tap signal MAIN TAP, and a third tap signal POST TAP are generated with respect to the data of the DEVEN node, respectively. The tap signal generator 630 transmits a tap control signal in which the first tap signal PRE TAP, the second tap signal MAIN TAP, and the third tap signal POST TAP are combined to the transmission driver 640 .

The transmission driver 640 outputs a channel loss compensation signal using a tap control signal and a clock signal of 6 GHz, which is half of a data transmission rate of 12 Gbit/s. The transmission driver 640 uses a tap control signal and a clock signal, and transmits pre-emphasis 12 Gbit/s data in order to minimize the mutual sign interference noise generated by the channel, the package, and the pad. implement

The clock signal generator 650 applies a clock signal to each of the PRBS generator 610 , the serializer 620 , the tap signal generator 630 , and the transmission driver 640 . The clock signal generator 650 generates a first clock signal of 6 GHz, which is half of the data transmission rate of 12 Gbit/s, from the PPL 656 and inputs it to the tap signal generator 630 .

In addition, the clock signal generator 650 passes the clock signal generated by the PPL 656 through the first divider 654 to generate a second clock signal of 3 GHz, which is half of the data transfer rate of the first clock signal of 6 Gbit/s. input to the serializer 620 .

In addition, the clock signal generator 650 passes the clock signal distributed by the first divider 654 through the second divider 654 .

A third clock signal of 750 MHz, which is half of the data transfer rate of the second clock signal of 3 Gbit/s, is input to the PRBS generator 610 .

7A and 7B are diagrams for explaining the configuration and operation of a tap signal generator according to an embodiment of the present invention.

7A shows a circuit of the tap signal generator 220 for implementing pre-emphasis.

Referring to FIG. 7A , the tap signal generator 630 serializes 16 parallelized PRBS data patterns generated by the PRBS generator 610 at a rate of 6 Gbit/s. First serial data DIN0 and second serial data (DIN1) is received as an input, and the first serial data DIN0 and the second serial data DIN1 are delayed by 83ps (0.5 UI) through each latch.

The tap signal generator 630 generates a first tap signal PRE TAP, a second tap signal MAIN TAP, and a third tap signal POST TAP with respect to data of the DODD and DEVEN nodes corresponding to the predetermined clock signal, respectively. create That is, the tap signal generator 630 outputs a first tap control signal including even data, DEVEN POST, DEVEN MAIN, and DEVEN PRE, and a second tap control signal, including odd data, DODD POST, DODD MAIN, and DODD PRE. do.

7B (a) shows a timing diagram of a latch output signal.

In the tap signal generator 630, the first serial data DIN0 and the second serial data DIN1 are delayed by 0.5 UI for nodes A and B that have passed through only one stage of latching, and nodes C and D that have passed two stages are delayed by 1 UI E and F nodes that have passed through the three stages are delayed by 1.5 UI, and G and H that have passed four stages are delayed by 2 UI.

The tap signal generator 630 combines the plurality of nodes A, B, C, D, E, F, G, and H in which the first serial data DIN0 and the second serial data DIN1 are delayed to obtain odd and even numbers. Each of the data can generate a 3-Tap Signal at the same time.

In (a) of FIG. 7B , nodes E-F-A and nodes H-C-D are three consecutive data streams (eg, D0/D1/D2, D1/D2/D3).

FIG. 7B (b) is an enlarged view of six nodes and clock signals to be used as inputs in the transmission driver stage among all the nodes listed in FIG. 7B (a).

The tap signal generator 630 uses a half-rate clock to serialize data at the final 12 Gbit/s rate, which is a 3-tap signal, PRE/MAIN/POST of DODD on the EFA node, and PRE/MAIN/PRE/MAIN/ of DEVEN on the HCD node. Indicates the data alignment of POST.

In addition, when the tap signal generator 630 views the MAIN signal of DODD and the MAIN signal of DEVEN from the reference of the 6 GHz clock, in the order of D1, D2, D3, and D4, the sequence of data columns is 12 Gbit in sequential data order without inversion. It can be serialized at the speed of /s.

The data arranged as shown in (b) of FIG. 7b is a sequence of three tap signals generated using a speed clock signal of 6 GHz, which is half of the transmission rate, and then the pre-emphasis (pre-emphasis) signal in the transmission driver 640 block. emphasis) can be used.

8A and 8B are diagrams for explaining the configuration and operation of a transmission driver according to an embodiment of the present invention.

8A shows a circuit of a transmit driver 640 for pre-emphasis by applying a finite impulse response (FIR) vector.

Referring to FIG. 8A , the transmission driver 640 obtains a tap control signal including a 3-tap signal from the tap signal generator 630, and a finite impulse response (FIR) filter using the obtained 3-tap signal is applied. It is a pre-emphasis driver.

The total number of segment drivers included in the transmission driver 640 is 25. The transmit driver 640 includes a segment driver group including a plurality of segment drivers. Here, the transmission driver 640 may include a first segment driver group 810 , a second segment driver group 820 , and a third segment driver group 830 . For example, the first segment driver group 810 includes 7 segment drivers, the second segment driver group 820 includes 15 segment drivers, and the third segment driver group 830 includes 3 segment drivers. Drivers may be included.

During the operation of the transmission driver 640 , the number of segment drivers actually used may be manually adjusted through a PU SEG signal outside the chip through SPI communication.

The transmission driver 640 operates with data signals DODD and DEVEN of 6 Gbit/s and clock signals CODD and CEVEN of 6 GHz as inputs.

When the wired data transmitter 600 according to the present embodiment transmits a differential signal, output values OUTP and OUTN may exist as a pair.

, CEVEN,

에 대한 버퍼 회로이다. 8B (a) shows a metastable buffer structure for minimizing jitter noise. 8b (a) is a clock signal CODD and

, CEVEN,

for the buffer circuit.

Referring to (a) of FIG. 8B , a clock signal of 6 GHz coming to CLK IN is received as an input, and CLKs of 0° and 180° phase are generated two by two to distribute the loading load.

사이 혹은 CEVEN과

사이의 발생하는 오차는 드라이버 출력 데이터 상에 직접적으로 지터(Jitter)로 반영된다. 이를 위해 인버터 소자 사이에 작은 사이즈의 인버터 두 개를 Meta-stable한 관계로 추가하여 반전된 신호끼리의 게인(Gain)을 더욱 높여 두 반전된 신호 사이의 오차를 최소화 하여 출력을 최소화한다. Also, CODD and

Between or with CEVEN

The error that occurs between them is directly reflected as jitter on the driver output data. To this end, two small-sized inverters are added between the inverter elements in a meta-stable relationship to further increase the gain between the inverted signals to minimize the error between the two inverted signals to minimize the output.

The transmission driver 640 uses the buffer structure as well as minimizes the length of the connection signal lines in the layout and makes the length and shape of the inverted signal lines the same, thereby reducing the load on the clock buffer and reducing the error occurring between the inverted signals. Signal quality can be improved.

8B (b) shows an operation of serializing data using a half-rate clock signal, and a timing diagram in a situation where data is transmitted at 12 Gbit/s using a half-rate clock of 6 GHz.

혹은 CEVEN과

의 반전된 위상의 오차가 지터(Jitter)와 EYE 다이어그램 성능에 영향을 미친다. 이러한 결과는 최종적으로 유선 데이터 송수신 상황에서 데이터 전송 정확도인 BER에도 영향을 미치게 된다. 뿐만 아니라 PVT 요인에 따른 변동도 생각 해주기 위해 DEVEN과 DODD의 데이터 변화 타이밍이 클락의 안정구간이 이른 타이밍에 발생할수록 PVT 요인에 적은 영향을 받으며 높은 품질의 신호를 유지할 수 있다. Referring to (b) of Figure 8b, CODD and

Or with CEVEN

The error of the inverted phase of EYE affects jitter and EYE diagram performance. This result ultimately affects the BER, which is the data transmission accuracy, in the wired data transmission/reception situation. In addition, in order to take into account the fluctuations caused by PVT factors, the earlier the clock stabilization period occurs, the less affected by the PVT factor and the higher the quality of the signal can be maintained.

9A and 9B are diagrams illustrating measurement results of a transmitter using a finite impulse response according to an embodiment of the present invention.

9A shows a data eye pattern diagram (EYE diagram) of 12 Gbit/s and a BER measurement result.

(a) of FIG. 9A shows the eye-opening of an eye pattern of 12 Gbit/s for a conventional transmitter that does not use the FIR function.

In (a) of FIG. 9A, pre-emphasis, that is, a finite impulse response filter function is turned off (PRE:MAIN:POST=0:15:0), and is a measurement result. The eye pattern of the measured conventional transmitter output data is completely closed due to mutual sign interference (ISI) noise due to the load of the corresponding chip's channel and pad and package.

Figure 9a (b) shows the eye-opening of the eye pattern of 12 Gbit/s for the transmitter of the present invention using the FIR function.

In (b) of FIG. 9A, pre-emphasis, that is, a finite impulse response filter function is turned on (PRE:MAIN:POST=1:10:4), and measurement results are obtained. The measured eye pattern of the transmitter output data of the present invention can confirm that the vertical axis opening is increased by 43.8% (171.3 mV / 391.2 mV) compared to the conventional one. By applying the finite impulse response filter according to the present embodiment to the transmitter, it is possible to minimize noise for mutual code interference (ISI) that is inevitably generated due to a load of a channel in a high-speed data transmission/reception situation.

FIG. 9B (a) shows a horizontal-axis bathtub curve measured when the transmitter of the present invention transmits 12 Gbit/s. FIG. 9B (a) shows a horizontal-axis bathtub curve for bit error rate (BER) for data transmission of 12 Gbit/s using the FIR function. Here, it can be seen that (a) of FIG. 9b has a horizontal axis opening of 0.204 UI based on ^{BER: 10 -12.}

(b) of FIG. 9b shows the measurement result according to the weight adjustment of the tap signal in the transmitter of the present invention, and (b) of 9b shows the pre-emphasis (pre-emphasis) pattern by fixing the data transmission pattern to 0011 in the low-speed transmission and reception situation. It can be seen that the weight adjustment of emphasis) is successfully operated. In addition, it can be seen that the performance of the Root Mean Square (RMS) jitter measured in the transmitter using the clock buffer using the meta-stable structure is 9.31 ps at the 12 Gbit/s rate.

10 is an exemplary diagram illustrating a transmitter and a measuring apparatus using a finite impulse response according to an embodiment of the present invention.

FIG. 10 (a) shows the transmitter 120 according to the present invention operating at 12 Gbit/s using a finite impulse response filter, and FIG. 10 (b) shows the measurement environment of the transmitter 120 according to the present invention. indicates. In Figure 10 (b), the transceiver fabricated through the TSMC 65-nm CMOS process ^{occupies an area of 0.042 mm 2} (excluding the area of PLL) (PG: 0.007 mm ² , Serializer/Tap. Gen./FIR Driver) : 0.035 mm ² ), transmitter operating power consumption including PLL is 19 mW.

The above description is merely illustrative of the technical idea of the embodiment of the present invention, and those of ordinary skill in the art to which the embodiment of the present invention pertains may make various modifications and changes within the scope not departing from the essential characteristics of the embodiment of the present invention. transformation will be possible. Accordingly, the embodiments of the present invention are not intended to limit the technical spirit of the embodiment of the present invention, but to explain, and the scope of the technical spirit of the embodiment of the present invention is not limited by these embodiments. The protection scope of the embodiment of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

110, 130: Chip 120: Transmitter
201: data sequence generator 210: serializer
220: tap signal generator 230: transmit driver

Claims (15)

a data sequence generator generating a parallelized data sequence;
a serializer that receives the data sequence and serializes it, and generates a serial data pair generated based on the serialized serial data;
a tap signal generator receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and
a transmitting driver receiving the tap control signal, calculating a weight for each of the at least one tap signal, and outputting a channel loss compensation signal in which the channel loss is compensated by applying the weight to a receiving end;
The tap signal generator receives the serial data pair, and generates each of three consecutive serial data sequences corresponding to each of the clock signals of the rising edge at each of the plurality of nodes generated including the serial data pair delayed at different timings. Three-tap signals (PRE TAP, MAIN TAP, POST TAP) are extracted, and each of three consecutive serial data sequences corresponding to the clock signal on the falling edge are converted into 3-tap signals (PRE TAP, MAIN TAP, POST TAP). extracting to generate a plurality of tap control signals, and based on a sequence of a main tap signal (MAIN TAP) of each of the plurality of tap control signals, a first tap control signal that is an even-numbered tap control signal and a first tap control signal that is an odd-numbered tap control signal 2 Transmits a tap control signal to the transmission driver,
The transmission driver includes a plurality of segment driver groups, each segment driver group includes a plurality of segment drivers, and the transmission driver includes a number of three-tap signals equal to the number of three-tap signals included in each of the plurality of tap control signals. A transmitter using a finite impulse response comprising a number of segment driver groups. According to claim 1,
The serializer is
and outputting the serial data pair including first serial data obtained by combining an even-numbered data sequence among the serial data and second serial data obtained by combining an odd-numbered data sequence among the serial data to the tap signal generator. Transmitter with finite impulse response. delete delete delete delete According to claim 1,
Each of the plurality of segment driver groups,
receiving each of the at least one tap signal included in the tap control signal, and calculating a weight of each of the tap signals based on each of the at least one tap signal and a clock signal;
and the transmission driver outputs the channel loss compensation signal calculated by applying a weight of each of the tap signals to each of the tap signals. 8. The method of claim 7,
The transmission driver is
a first segment driver group, a second segment driver group, and a third segment driver group, wherein each of the at least one tap signal included in the tap control signal is input to a different segment driver group;
The first segment driver group calculates a weight for the first tap signal PRE TAP, the second segment driver group calculates a weight for the second tap signal MAIN TAP, and the third segment driver group calculates a third A transmitter using a finite impulse response, characterized in that it calculates a weight for the tap signal (POST TAP). 8. The method of claim 7,
The transmission driver is
The transmitter using a finite impulse response, characterized in that by outputting the channel loss compensation signal to a receiving end, the data to be stored is determined by comparing a preset reference value and a result value of the channel loss compensation signal at the receiving end. A method for transmitting data in a transmitter using a finite impulse response, comprising:
a data sequence generating step of generating a parallelized data sequence;
a serialization step of receiving the data sequence and serializing it, and generating a serial data pair generated based on the serialized serial data;
a tap signal generating step of receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and
a driver driving step of receiving the tap control signal from a transmitting driver, calculating a weight for each of the at least one tap signal, and outputting a channel loss compensation signal for which the channel loss is compensated to a receiving end;
In the step of generating the tap signal, the serial data pair is input, and each of three consecutive serial data sequences corresponding to the clock signal of the rising edge at each of the plurality of nodes generated including the serial data pair delayed at different timings respectively is extracted as a 3-tap signal (PRE TAP, MAIN TAP, POST TAP), and each of three consecutive serial data sequences corresponding to the clock signal of the falling edge is converted into a 3-tap signal (PRE TAP, MAIN TAP, POST TAP) is extracted to generate a plurality of tap control signals, and based on a sequence of a main tap signal (MAIN TAP) of each of the plurality of tap control signals, a first tap control signal that is an even tap control signal and a first tap control signal that is an odd tap control signal transmitting a second tap control signal to the transmission driver;
In the driver driving step, the transmission driver includes a plurality of segment driver groups, each segment driver group includes a plurality of segment drivers, and the transmission driver includes a 3-tap included in each of the plurality of tap control signals. A data transmission method using a finite impulse response, comprising a number of segment driver groups equal to the number of signals. 11. The method of claim 10,
The serialization step is
and outputting the serial data pair including first serial data obtained by combining an even-numbered data sequence among the serial data and second serial data obtained by combining an odd-numbered data sequence among the serial data. How to send data. delete delete 11. The method of claim 10,
Each of the plurality of segment driver groups,
receiving each of the at least one tap signal included in the tap control signal, and calculating a weight of each of the tap signals based on each of the at least one tap signal and a clock signal;
The driving of the driver comprises outputting the channel loss compensation signal calculated by applying a weight of each of the tap signals to each of the tap signals. a first chip that generates data;
a second chip for obtaining a channel loss compensation signal in which the channel loss of the data is compensated, and determining and storing data to be stored; and
a data sequence generator generating a parallelized data sequence based on the data; a serializer that receives the data sequence and serializes it, and generates a serial data pair generated based on the serialized serial data; a tap signal generator receiving the serial data pair and generating a tap control signal including at least one tap signal generated through a timing delay; and a transmitter including a transmission driver receiving the tap control signal, calculating a weight for each of the at least one tap signal, and outputting the channel loss compensation signal in which the channel loss is compensated,
The tap signal generator receives the serial data pair, and generates each of three consecutive serial data sequences corresponding to each of the clock signals of the rising edge at each of the plurality of nodes generated including the serial data pair delayed at different timings. Three-tap signals (PRE TAP, MAIN TAP, POST TAP) are extracted, and each of three consecutive serial data sequences corresponding to the clock signal on the falling edge are converted into 3-tap signals (PRE TAP, MAIN TAP, POST TAP). extracting to generate a plurality of tap control signals, and based on a sequence of a main tap signal (MAIN TAP) of each of the plurality of tap control signals, a first tap control signal that is an even-numbered tap control signal and a first tap control signal that is an odd-numbered tap control signal 2 Transmits a tap control signal to the transmission driver,
The transmission driver includes a plurality of segment driver groups, each segment driver group includes a plurality of segment drivers, and the transmission driver includes a number of three-tap signals equal to the number of three-tap signals included in each of the plurality of tap control signals. A high-speed wired data communication system comprising a number of segment driver groups.

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