WO2024040483A1 - 一种调频方法和装置 - Google Patents

一种调频方法和装置 Download PDF

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Publication number
WO2024040483A1
WO2024040483A1 PCT/CN2022/114623 CN2022114623W WO2024040483A1 WO 2024040483 A1 WO2024040483 A1 WO 2024040483A1 CN 2022114623 W CN2022114623 W CN 2022114623W WO 2024040483 A1 WO2024040483 A1 WO 2024040483A1
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Prior art keywords
die
frequency
frequency switching
switching request
circuit
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PCT/CN2022/114623
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English (en)
French (fr)
Inventor
罗亦林
罗毅
尹海丰
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华为技术有限公司
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Priority to PCT/CN2022/114623 priority Critical patent/WO2024040483A1/zh
Publication of WO2024040483A1 publication Critical patent/WO2024040483A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Definitions

  • the present application relates to the field of chip technology, and in particular, to a frequency modulation method and device.
  • the clock frequency of the die-to-die interconnect interface in the chiplet can be the same as the clock frequency of the SoC domain (domain). Synchronous design reduces the increase in delay caused by asynchronous processing. At this time, when the SoC domain clock frequency is adjusted, the clock frequency of the interconnect interface also needs to be adjusted synchronously.
  • Embodiments of the present application provide a frequency modulation method and device, which can realize rapid switching of the clock frequency of the SoC domain and the interconnection interface in the chiplet system, and reduce the cache space required for service data.
  • a frequency modulation method is provided.
  • the method is applied to a chip system.
  • the chip system includes a first die and a second die.
  • the method includes: the first die sends a frequency switching request to the second die, and the frequency switches The request includes information indicating the frequency level after switching; the second die adjusts the operating frequency of the receiving circuit of the second die according to the frequency level.
  • the frequency level in this application may also be called a frequency gear.
  • This application is equivalent to training the frequency levels between die chips in the chip system in advance, and each frequency level corresponds to an operating frequency.
  • the first die and the second die are transmitting service data, if the operating frequency of the transmitting circuit of the first die is switched, the second die needs to be adaptable to adjust the operating frequency of the receiving circuit.
  • the present application sends information indicating the switched frequency level to the second die through the first die, the second die can quickly perform the receiving circuit operation corresponding to the frequency level based on the information of the switched frequency level. Frequency adjustment.
  • this application when this application performs rate switching in the PCIE link, it is also necessary to enter the recovery state each time for link retraining and then switch back to the L0 state, which causes a long switching delay.
  • This application performs frequency switching. The delay is shorter.
  • this application directly realizes the operating frequency switching through the exchange of information indicating the frequency level between dies. When the operating frequency is switched, the interface power consumption can be adjusted accordingly.
  • this application can also reduce the cache space required for business data caching.
  • the transmitting circuit of the first die and the receiving circuit of the second die are in the same clock domain.
  • the SoC domain, transmitting circuit of the first die and the receiving circuit of the second die are all in the same clock domain.
  • the digital logic of the first die and the second die at the data link layer can dynamically adjust the voltage according to the frequency change of the SoC domain, and thus can further reduce power consumption.
  • the method before the first die sends a frequency switching request to the second die, the method further includes: the first die receives a frequency mode configuration command sent by the application layer, and the frequency mode configuration command includes the first Indication information, the first indication information is used to indicate the frequency level after switching; the first die generates a frequency switching request according to the frequency mode configuration command.
  • the application layer of the first die determines to change the operating frequency of the first die, it may send a frequency mode configuration command to the first die to indicate the frequency level after switching.
  • the application layer stores frequency levels corresponding to different service types.
  • the method before the second die adjusts the operating frequency of the receiving circuit of the second die, the method further includes: the first die stops receiving service data from the application layer.
  • the application layer of the first die determines that frequency modulation is to be performed, the application layer of the first die stops sending service data to the SoC domain of the first die so that the first die can perform frequency adjustment and communicate with the third die.
  • the frequency level after the two die are switched interactively.
  • sending the frequency switching request from the first die to the second die includes: the first die sends the frequency switching request to the second die through the first low-power control word LPW flow control unit or the first sideband control command.
  • the chip sends a frequency switching request; the method further includes: the first die receiving a frequency switching response sent by the second die through the second LPW flow control unit or the second sideband control command.
  • the first LPW flit can be understood as being sent by the first die to the second die through the data link.
  • the first sideband control command can be understood as being sent by the first die to the second die through the sideband control channel.
  • the second LPW flit is sent from the second die to the first die through the data link.
  • the second sideband control command is sent by the second die to the first die through the sideband control channel.
  • the first LPW flow control unit includes a flow control unit header field, a flow control unit content field, and a flow control unit tail field; where the flow control unit content field includes a type subfield and a command subfield, and the type The subfield is used to indicate that the first LPW flow control unit is a frequency switching command, and the command subfield is used to indicate the frequency level.
  • the first sideband control command includes a field indicating a message type, a field indicating a message encoding, a field indicating a path identification, and a field indicating a check bit; wherein the field indicating the message type is used to indicate
  • the first sideband control command is a frequency switching command.
  • the method before the second die adjusts the operating frequency of the receiving circuit of the second die, the method further includes: the first die stops sending the associated clock to the second die, and adjusts the associated clock according to the frequency level. Adjust the operating frequency of the transmitting circuit of the first die.
  • a clock Lane may exist between the first die and the second die.
  • the receiving circuit in the second die receives the service data sent by the transmitting circuit of the first die based on the first die through the clock Lane.
  • the clock frequency of the sent associated clock is received. If the first die needs to perform frequency switching, it can stop sending the associated clock to the second die, so that after switching the operating frequency of the sending circuit of the first die, the clock Lane can be used to send the clock to the third die at the new operating frequency.
  • the second die sends the associated clock with the new operating frequency. In this way, the clock frequency of the receiving circuit of the second die is adjusted accordingly.
  • the method before the second die adjusts the operating frequency of the receiving circuit of the second die, the method further includes: the first die continues to send empty flow control units to the second die until receiving Frequency switching response sent to the second die.
  • the first die continues to send frequency switching commands to the second die until receiving a frequency switching response sent by the second die.
  • the method before the second die adjusts the operating frequency of the receiving circuit of the second die, the method further includes: after the first die determines to complete frequency switching negotiation with the second die, report to the application layer Response frequency switching negotiation completed.
  • the first die After the first die receives the frequency switching configuration command sent by the application layer, if the first die completes the frequency switching negotiation with the second die, it can respond to the application layer of the first die that the frequency switching negotiation is completed. So that the application layer initiates the frequency switching of the SoC domain of the first die.
  • the method before the second die adjusts the operating frequency of the receiving circuit of the second die, the method further includes: the first die sends a frequency switching instruction to the second die, and the frequency switching instruction is used to Instructs the second die to perform frequency switching.
  • the first die When the first die sends a frequency switching instruction to the second die, the first die may start to switch the operating frequency of the transmitting circuit of the first die, or may be in the process of switching the operating frequency of the transmitting circuit of the first die. Switching may also complete the switching of the operating frequency of the transmitting circuit of the first die.
  • the second die receives the frequency switching instruction, the second die can start frequency switching of the receiving circuit of the second die.
  • the first die switches the frequency of the sending circuit of the first die, which can be understood as the first die determines the circuit configuration parameters of the sending circuit according to the frequency level, and performs the switching of the sending circuit according to the circuit configuration parameters of the sending circuit.
  • Circuit parameter configuration Similarly, the second die performs frequency switching of the receiving circuit of the second die, which can be understood as the second die determines the circuit configuration parameters of the receiving circuit based on the frequency level, and performs the circuit configuration of the receiving circuit based on the circuit configuration parameters of the receiving circuit. Parameter configuration.
  • the method further includes: after the first die waits for a fixed delay, starting the associated clock of the first die.
  • the fixed delay should cover the stabilization time after the second die switches the operating frequency and the stabilization time after the first die switches the operating frequency. In this way, it is equivalent to giving the first die and the second die enough time to complete the frequency switch, so that after both parties complete the frequency switch, the first die starts the associated clock at the new operating frequency and starts communicating with the second die. slices for business data interaction.
  • the method further includes: the first die sending data to the second die at a frequency level; and the second die receiving the data sent by the first die at a frequency level.
  • a frequency modulation method is provided.
  • the method is applied to a chip system.
  • the chip system includes a first die and a second die.
  • the method includes: the second die receives a frequency switching request sent by the first die.
  • the switching request includes information indicating a frequency level after switching; the second die adjusts the operating frequency of the receiving circuit of the second die according to the frequency level.
  • the transmitting circuit of the first die and the receiving circuit of the second die are in the same clock domain.
  • the second die receiving the frequency switching request sent by the first die includes: the second die receiving the first low power consumption control word LPW flow control unit or the first sideband control command.
  • the die sends a frequency switching request; the method further includes: the second die sends a frequency switching response to the first die through a second LPW flow control unit or a second sideband control command.
  • the method further includes: when the second die receives the frequency switching request sent by the first die, recording information indicating the frequency level after switching.
  • the method before the second die adjusts the operating frequency of the receiving circuit of the second die according to the frequency level, the method further includes: the second die receives the frequency switching instruction sent by the first die, the frequency The switching instruction is used to instruct the second die to perform frequency switching.
  • a frequency modulation method is provided.
  • the method is applied to a chip system.
  • the chip system includes a first die and a second die.
  • the method includes: the first die sends a frequency switching request to the second die, and the frequency switches
  • the request includes information indicating a frequency level after switching; the first die adjusts the operating frequency of the transmitting circuit of the first die according to the frequency level.
  • the transmitting circuit of the first die and the receiving circuit of the second die are in the same clock domain.
  • sending the frequency switching request from the first die to the second die includes: the first die sends the frequency switching request to the second die through the first low-power control word LPW flow control unit or the first sideband control command.
  • the chip sends a frequency switching request; the method further includes: the first die receiving a frequency switching response sent by the second die through the second LPW flow control unit or the second sideband control command.
  • a chip system in a fourth aspect, includes a first die and a second die, wherein: the first die is used to send a frequency switching request to the second die, and the frequency switching request includes an instruction after switching. Frequency level information; the second die is used to adjust the operating frequency of the receiving circuit of the second die based on the frequency level.
  • the transmitting circuit of the first die and the receiving circuit of the second die are in the same clock domain.
  • the first bare chip is used to: receive a frequency mode configuration command sent by the application layer, the frequency mode configuration command includes first indication information, and the first indication information is used to indicate the frequency level after switching; according to the frequency The mode configuration command generates a frequency switching request.
  • the first die is used to: send a frequency switching request to the second die through a first low-power control word LPW flow control unit or a first sideband control command; and use the second LPW flow control
  • the unit or second sideband control command receives the frequency switching response sent by the second die.
  • a second die in a fifth aspect, includes a first die and a second die.
  • the second die includes: a receiver for receiving a frequency switching request sent by the first die.
  • the frequency switching request including information indicating the frequency level after switching; a processor configured to adjust the operating frequency of the receiving circuit of the second die according to the frequency level.
  • the transmitting circuit of the first die and the receiving circuit of the second die are in the same clock domain.
  • the receiver is configured to: receive the frequency switching request sent by the first die through the first low-power control word LPW flow control unit or the first sideband control command; the receiver is also configured to: The second LPW flow control unit or the second sideband control command sends a frequency switching response to the first die.
  • the processor is further configured to: when the receiver receives the frequency switching request sent by the first die, record information indicating the frequency level after switching.
  • the receiver is further configured to: receive a frequency switching instruction sent by the first die, and the frequency switching instruction is used to instruct the second die to perform frequency switching.
  • a first die is provided.
  • the chip system includes a first die and a second die.
  • the first die includes: a transmitter for sending a frequency switching request to the second die.
  • the frequency switching request includes: Information indicating the frequency level after switching; a processor configured to adjust the operating frequency of the transmitting circuit of the first die according to the frequency level.
  • the transmitting circuit of the first die and the receiving circuit of the second die are in the same clock domain.
  • the transmitter is configured to: send a frequency switching request to the second die through a first low-power control word LPW flow control unit or a first sideband control command; and further includes a receiver, configured to The frequency switching response sent by the second die is received through the second LPW flow control unit or the second sideband control command.
  • inventions of the present application provide a chip system.
  • the chip system includes a die as described in any possible design of the first to third aspects; the chip system includes a plurality of die, Each die includes an interface circuit and a processor (SoC domain); the interface circuit and the processor are interconnected through lines; the processor receives and executes computer instructions from a memory outside the chip system through the interface circuit.
  • SoC domain SoC domain
  • embodiments of the present application provide a computer-readable storage medium that includes computer instructions.
  • the computer instructions When the computer instructions are run on an electronic device, the electronic device causes the electronic device to execute the above-mentioned first aspect and any possible design of the first aspect. the method described.
  • embodiments of the present application provide a computer-readable storage medium that includes computer instructions.
  • the computer instructions When the computer instructions are run on an electronic device, the electronic device causes the electronic device to execute the above-mentioned second aspect and any possible design of the second aspect. the method described.
  • embodiments of the present application provide a computer-readable storage medium that includes computer instructions.
  • the computer instructions When the computer instructions are run on an electronic device, the electronic device causes the electronic device to execute the above third aspect and any possible design of the third aspect. the method described.
  • embodiments of the present application provide a computer program product.
  • the computer program product When the computer program product is run on a computer or processor, it causes the computer or processor to execute the method in the above first aspect and any possible implementation manner. .
  • embodiments of the present application provide a computer program product.
  • the computer program product When the computer program product is run on a computer or processor, it causes the computer or processor to execute the method in the above second aspect and any possible implementation manner. .
  • embodiments of the present application provide a computer program product.
  • the computer program product When the computer program product is run on a computer or processor, it causes the computer or processor to execute the method in the above third aspect and any possible implementation manner. .
  • any of the first die, second die, chip system, computer-readable storage medium or computer program product provided above can be applied to the corresponding method provided above. Therefore, it The beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods, and will not be described again here.
  • Figure 1 is a schematic diagram of a coupling circuit between dies provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of state switching for frequency switching in a PCIE link provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of the purpose of achieving a switching rate by adapting different Lanes between dies according to an embodiment of the present application
  • Figure 4 is a schematic diagram of a chip system provided by an embodiment of the present application.
  • Figure 5 is a schematic flow chart of a frequency modulation method provided by an embodiment of the present application.
  • Figure 6 is a schematic circuit diagram of an interconnection interface between dies and SoC domain coupling provided by an embodiment of the present application
  • Figure 7 is a schematic flow chart of a frequency modulation method provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of the sideband signal interface interconnection between dies provided by an embodiment of the present application.
  • Figure 9 is a timing diagram of a sideband signal interface provided by an embodiment of the present application for transmission in the form of messages;
  • Figure 10 is a schematic diagram of the format of a sideband control signal provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a bare chip provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a bare chip provided by an embodiment of the present application.
  • Figure 13 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this embodiment, unless otherwise specified, “plurality” means two or more.
  • a chiplet system also known as a chip system, is a combination of dies with different functions. In a sense, it is also a combination of different IPs. Starting from the system side, complex functions are first decomposed, and then a variety of Bare chips with a single specific function that can be modularly assembled with each other, such as realizing functions such as data storage, computing, signal processing, data flow management, etc., and ultimately based on this, a Chiplet chip network is established. Alternatively, it can also be understood as a mode in which multiple module chips and underlying basic chips are packaged together through die-to-die internal interconnection technology to form a multi-functional heterogeneous System in Packages (SiPs) chip.
  • SiPs System in Packages
  • the clock frequency of the interconnect interface can be designed synchronously with the SoC domain in the die to reduce the increase in latency caused by asynchronous processing.
  • the die includes the SoC domain and interconnect interface circuitry.
  • the interconnection interface circuit includes a transmitting circuit, a receiving circuit and a sideband control channel.
  • the SoC domain can transmit application data (application data), that is, business data, to the transmit circuit of the interconnect interface circuit.
  • the SoC domain can also transmit control signals through the sideband control channel of the interconnect interface circuit.
  • the SoC domain in die 1, the transmitting circuit of die 1 in the interconnection interface, and the receiving circuit in the interconnection interface of die 2 are in the same clock domain.
  • the clock frequencies of the transmitting circuit of die 1 in the interconnect interface and the receiving circuit of die 2 in the interconnect interface also need to be adjusted synchronously.
  • the sending circuit of die 1 in the interconnection interface can be used as the link master of die 1, and the receiving circuit of die 2 in the interconnection interface can be used as the link slave of die 2. ).
  • the SoC domain in die 2 the transmitting circuit of die 2 in the interconnect interface, and the receiving circuit of die 1 in the interconnect interface are in the same clock domain.
  • the clock frequencies of the transmitting circuit in the interconnect interface of die 2 and the receiving circuit in the interconnect interface of die 1 also need to be adjusted synchronously.
  • the sending circuit of die 2 in the interconnection interface can be used as the link master of die 2
  • the receiving circuit of die 1 in the interconnection interface can be used as the link slave of die 1.
  • FIG. 1 Also shown in Figure 1 is an asynchronous circuit coupling between the SoC domain in Die 1 and the receiving circuitry in Die 1 in the interconnect interface.
  • asynchronous circuits are mainly combinational logic circuits and do not use clock pulses for synchronization, data synchronization, communication and operation sequences between different components are generally achieved through handshake protocols.
  • the asynchronous circuit receives the data from the receiving circuit, it needs to send data to the SoC domain in die 1 according to the handshake protocol. Therefore, the clocks of the SoC domain in Die 1 and the receiving circuit in Die 1 are asynchronous clock domains. Similarly, the clocks of the SoC domain in die 2 and the receiving circuit in the interconnect interface of die 2 are also asynchronous clock domains.
  • Die 1 and Die 2 can transmit sideband signals through the sideband control channel.
  • the transmit circuit in die 1 can send downstream data to the receive circuit in die 2 through the downstream link.
  • the transmit circuit in die 2 Upstream data can be sent to the link slave in die 1 through the upstream link.
  • upstream data and downstream data can be transmitted between die 1 and die 2 through a flow control unit (flit).
  • reducing handover delay helps reduce cache space and also reduces service delays caused during the handover process.
  • the state machine needs to switch the L0 state to the reset (Recovery) state for link re-training (Re-Training). After training is completed, switch back to L0 state.
  • the L0 state is the normal working state of the PCIE link. In this state, the PCIE link can send and receive data normally.
  • the switching rate can be achieved by adapting the number of different paths (lanes).
  • the interconnection interface and the SoC domain are coupled through an asynchronous circuit.
  • the clock domain of the interconnection interface and the clock domain of the SoC domain in a single die are different clock domains, which is an asynchronous clock. Domain, the clock domain of the interconnect interface and the clock domain of the SoC domain do not use clock pulse synchronization.
  • the interconnection interface works at a fixed frequency. When the clock frequency of the SoC domain is adjusted, the clock frequency of the interconnection interface remains unchanged.
  • the number of Lanes of the interconnection interface is adjusted to match the rate of the interconnection interface. In this scenario, this asynchronous processing adds latency.
  • the interconnection interface matches the rate change based on the number of lanes.
  • the rate of the interconnection interface decreases, the digital part of the interconnection interface cannot follow the decrease in speed to reduce the operating voltage, and the power consumption performance of the interconnection interface is poor.
  • this application provides a frequency modulation method that can dynamically adjust the frequency of the interconnection interface in a chiplet. By exchanging different frequency level indication information between die chips, rapid switching of frequency gears is achieved and link switching delay is reduced.
  • the operating frequency of the SoC domain when the operating frequency of the SoC domain changes, the operating frequency of the interconnection interface between the die also changes accordingly.
  • the circuit configuration parameters of the interconnection interface at each frequency level can be trained separately during the initialization process, and the training results can be saved in each die.
  • the sending end When the sending end needs to follow the operating frequency of the SoC domain to adjust the frequency of the interconnect interface, the sending end informs the receiving end of the frequency level indication that needs to be switched through the interactive process.
  • the receiving end can query the corresponding circuit from the training parameters according to the frequency level indication. Configure parameters to switch to this frequency level.
  • the embodiments of this application can be applied to chiplet systems.
  • the Chiplet system includes multiple bare chips with specific functions that can be modularly assembled with each other.
  • the bare chips can implement functions such as data storage, computing, signal processing, and data flow management.
  • Chiplet System has proposed the concept of IP as a Chiplet (IaaC), aiming to achieve "plug and play" of special function IP with bare chips.
  • the die can be graphics processor (Graphics Processing Unit, GPU) IP, neural network processor (Neural-network Unit, NPU) IP, video processor (Video Processing Unit, VPU) IP , digital signal processing (DSP) IP, image signal processor (Image Signal Processor, ISP) IP and display processor IP, etc.
  • the bare chips can also be digital-analog hybrid IP and radio frequency IP.
  • the chiplet system in this application is a chip system, which can also be called a small chip system or a chip system.
  • the die can also be called a chiplet, and in a chip system, the die can also be called a die.
  • the Chiplet system can be applied to a System-on-a-Chip (SoC), where bare chips with multiple functions are integrated on the SoC.
  • SoC System-on-a-Chip
  • the chip system includes a first die as shown in Figure 4 die and the second die.
  • the first die can transmit business data/application data with the second die through a data channel.
  • the data channel includes the above-mentioned downstream link and upstream link.
  • the first die may transmit control signals with the second die through a sideband control channel.
  • the operating frequency of the transmitting circuit of the first die changes, information indicating the switched frequency level may be sent to the second die.
  • the second die can adjust the operating frequency of the receiving circuit according to the frequency level to achieve rapid frequency switching between die.
  • the first die and the second die may be understood as two chips with different functions in initialization and power management.
  • the first die is a host processor chip, and the host can start the flow to enter a low-power state and perform frequency switching in conjunction with the low-power state.
  • the second die is the chip connected to the host processor chip as the slave processor chip.
  • the second die is a memory chip.
  • the slave processor chip generally cannot start the flow to enter the low-power state, but can respond to the flow of the host processor chip to enter the low-power state.
  • Embodiments of the present application provide a frequency modulation method, which is applied to a chip system (Chiplet system).
  • the chip system includes a first die and a second die, as shown in Figure 5.
  • the method includes the following processes.
  • the first die sends a frequency switching request to the second die, where the frequency switching request includes information indicating the frequency level after switching.
  • information indicating the switched frequency level may be sent to the second die so that the second die also synchronously switches the operating frequency of the receiving circuit.
  • frequency level can also be understood as frequency gear.
  • the frequency level in this application is used to indicate a preset frequency mode or frequency parameter corresponding to the service.
  • circuit configuration parameters corresponding to the frequency mode or frequency parameters may be pre-stored. In this way, when the second die determines the corresponding circuit configuration parameters according to the frequency mode or frequency parameters, the second die can adjust the device parameters in the receiving circuit according to the determined circuit configuration parameters, thereby adjusting the operating frequency of the receiving circuit, so that the receiving circuit The circuit is capable of processing data at the corresponding service rate.
  • the device parameters here include, for example, parameters such as capacitance, resistance, inductance, or register configuration, and may also include parameters related to receiving filters and receiving levels.
  • the second die adjusts the operating frequency of the receiving circuit of the second die according to the frequency level.
  • the second die adjusts the operating frequency of the receiving circuit according to the frequency level, which can be understood as the second die adjusts the circuit configuration parameters of the receiving circuit according to the frequency level.
  • each training parameter can be obtained through prior training, and each training parameter includes a circuit configuration parameter corresponding to a frequency level.
  • the corresponding circuit configuration parameters can be determined according to the information indicating the frequency level after switching, so as to complete the circuit configuration according to the circuit configuration parameters.
  • the transmitting circuit of the first die and the receiving circuit of the second die have completed the adjustment of the circuit configuration parameters, the frequency switching of the first die and the second die is completed, and the sending circuit of the first die is switched after the switching. Data is sent at the frequency, and the receiving circuit of the second die receives data at the switched frequency.
  • the interconnection interface between dies and the SoC domain are in the same clock domain, and the SoC domain does not need to perform asynchronous processing when transmitting data through the interconnection interface.
  • the SoC domain of the first die, the transmitting circuit in the first die, and the receiving circuit in the second die are in the same clock domain, which is marked as clock domain 1.
  • clock domain 1 When the SoC domain in the first die switches the clock frequency, both the transmitting circuit in the first die and the receiving circuit in the second die need to switch the clock frequency.
  • the first die can perform circuit configuration on the transmitting circuit of the first die based on the pre-stored training parameters, that is, the circuit configuration parameters corresponding to the frequency level, and the second die can also perform circuit configuration on the second die based on the circuit configuration parameters corresponding to the frequency level.
  • the receiving circuit performs circuit configuration.
  • the SoC domain in the second die, the transmitting circuit in the second die, and the receiving circuit in the first die are in the same clock domain, denoted as clock domain 2.
  • clock domain 2 When the SoC domain in the second die switches the clock frequency, both the transmitting circuit in the second die and the receiving circuit in the first die need to switch the clock frequency.
  • the training parameters that can be prestored in the first die are to perform circuit configuration on the transmitting circuit of the first die according to the circuit configuration parameters corresponding to the frequency level, and the second die also performs circuit configuration on the second die based on the circuit configuration parameters corresponding to the frequency level.
  • the receiving circuit performs circuit configuration.
  • the first die when it needs to perform frequency switching according to the application layer, it can also be the transmitting circuit in the first die, the receiving circuit in the first die, and the receiving circuit in the second die.
  • the operating frequency is reconfigured for both the transmitting circuit and the transmitting circuit in the second bare chip, that is, the circuit configuration parameters are reconfigured.
  • Embodiments of the present application provide a frequency modulation method, which is applied to a chip system (Chiplet system).
  • the chip system includes a first die and a second die, as shown in Figure 7.
  • the method includes the following process.
  • the first die receives a frequency mode configuration command sent by the application layer.
  • the frequency mode configuration command includes first indication information, and the first indication information is used to indicate the frequency level after switching.
  • the application layer can be understood as the application service of the first die.
  • the application layer can send a frequency mode configuration command to the first die to The chip indicates the frequency level after switching. For example, the application layer sends a frequency mode configuration command to the SoC domain of the first die.
  • the first die generates a frequency switching request according to the frequency mode configuration command, and sends the frequency to the second die through the first low power word (LPW) flit or the first sideband control (sideband command) command.
  • LPF low power word
  • sideband command sideband command
  • the second die receives the frequency switching request sent by the first die through the first LPW flit or the first sideband control command.
  • LPW can be understood as a signal that communicates through low power consumption, low data rate and low cost.
  • Sideband refers to the modulated signal. That is, a frequency band is generated on both sides of the central carrier frequency, called sidebands. Sideband control commands are control commands transmitted through sidebands. The sideband control command is generally transmitted through the sideband address.
  • the first die when sending the first LPW flit, stops sending service data to the second die. After the first die sends the frequency switching request, it can continue to send service data to the second die normally.
  • the first die when sending the first sideband control command, can normally send service data to the second die, that is, the sending of normal service data is not affected.
  • the SoC domain of the first die sends the first LPW flit to the receiving circuit of the second die through the transmitting circuit of the first die, and the first LPW flit is equivalent to the switching request in this application.
  • the first LPW flit is sent by the sending circuit of the first die to the second die through the downstream link.
  • the downstream link and the upstream link may be high-speed data channels.
  • the interconnection interface is a high-speed serial interface, such as PCIE or Universal Serial Bus (USB)
  • PCIE or USB can transmit business data between dies through high-speed data channels.
  • the PCIE of the first die can transmit the first LPW flit to the PCIE of the second die through the high-speed data channel.
  • the first LPW flit includes a flit header (Header) field, a flit content (payload) field and a flit tail (Tail) field, and the flit payload field includes a type subfield (SUB_TYPE) and a command subfield (CMD),
  • the type subfield is used to indicate that the first LPW flit is a frequency switching command
  • the command subfield is used to indicate a frequency level.
  • Table 1 shows an example of the format of LPW flit.
  • the bit value of the Type subfield in the Flit Header field When the bit value of the Type subfield in the Flit Header field is "0", it indicates that the first LPW flit is a control flit, which can be used to instruct the second die to execute the control command indicated by the first LPW flit.
  • the bit value of the SUB_TYPE subfield in the Flit payload field When the bit value of the SUB_TYPE subfield in the Flit payload field is "1100", it indicates that the first LPW flit is a frequency switching command.
  • the bit value of the CMD subfield in the Flit payload field can also be one of multiple bit values ('b00000000 ⁇ 'b11111111), used to indicate frequency level N, where N is an integer. For example, when the bit value of the CMD subfield is 00000001, the value of N is 1, and the operating frequency indicated by frequency level 1 is 2/256 of the highest frequency.
  • This application does not limit the bit value of the CMD subfield used to indicate the frequency level.
  • the SoC domain in the first die sends a frequency switching request to the second die through the sideband control channel of the first die.
  • the sideband control channel of the second die sends a frequency switching request.
  • the first sideband control command may be interacted through a sideband signal interface between dies.
  • the sideband signal interface includes SBC_TXC for transmitting the clock frequency of the transmitting side, SBC_TXD for transmitting serial data on the transmitting side, SBC_RXC for transmitting the clock frequency of the receiving side, and SBC_RXC for transmitting the clock frequency of the receiving side. SBC_RXD of the serial data on the receiving side.
  • this sideband signal interface is used for the interaction of control signals and status between two dies.
  • the control signal is, for example, the first sideband control command in this application.
  • the sideband signal interface can use serial transmission.
  • the sideband signal of each die includes the sideband signal in the sending direction and the sideband signal in the receiving direction.
  • Each sideband signal can use 1 clock.
  • the signal is connected to a data signal.
  • Figure 8 shows a schematic diagram of the sideband signal interface interconnection between dies. The description of each sideband signal interface can be found in Table 2.
  • SBC_TXC in Table 2 represents the clock signal of the sideband control signal in the transmitting direction; SBC_TXD represents the data (control command) of the sideband control signal in the transmitting direction; SBC_RXC represents the clock signal of the sideband control signal in the receiving direction; SBC_RXD represents the sideband Control signal data (control command) in the receiving direction.
  • the first die can send the first sideband control signal to the SBC_RXD of the second die through SBC_TXD.
  • the first die sends the first sideband control signal at SBC_TXC. is sent at the clock frequency indicated by SBC_RXC and the second die is received at the clock frequency indicated by SBC_RXC.
  • the clock frequency SBC_TXC and SBC_RXC of the sideband signal and the sideband control signal (data) can be in a synchronous timing relationship, and the rising edge of the clock is aligned with the transition edge of the data.
  • FIG. 9 shows a timing diagram of a sideband signal interface transmitting in the form of messages.
  • each clock cycle can use Single Data Rate (SDR) to transmit 1 bit data, and each continuous transmission of 16 bit data (D0 ⁇ D15) (16 clock cycles (cycle)) forms a report
  • SDR Single Data Rate
  • D0 ⁇ D15 16 bit data
  • D0 ⁇ D15 16 clock cycles (cycle)
  • SBC_TXC can be maintained at a low level
  • the data I/O (SBC_TXD) can be in a low power consumption state.
  • the first sideband control command in this application can be sent to the second die through these 16 clock cycles, occupying 16 bits.
  • the message format of the sideband signal in this application for example, when the format of the first sideband control signal is 16 bit, the format can be referred to Figure 10.
  • the functions of each field in this format can be found in Table 3.
  • the above-mentioned SBC_SYNC_IND can be used by the first die to notify the second die that the frequency switching of the first die is completed, and the second die can start frequency switching synchronously.
  • the second die When receiving the frequency switching request, the second die records information indicating the frequency level after switching.
  • the receiving circuit in the second die stops receiving service data from the downstream link and records the frequency level indicating the frequency level after switching. information.
  • the second die stops receiving service data if the second die completes frequency switching, the second die can receive service data of the service type at the new operating frequency.
  • the second die can receive service data normally and record information indicating the frequency level after switching.
  • the second die sends a frequency switching response to the first die.
  • the second die sends a frequency switching response to the first die through a second LPW flit or a second sideband control command.
  • the first die receives the frequency switching response sent by the second die through the second LPW flit or the second sideband control command.
  • the first die may be waiting to receive a frequency switching response.
  • the format of the second LPW flit is similar to the format of the first LPW flit shown in Table 1. The difference is that, referring to Table 1, the bit value of SUB_TYPE is 4'b1111, indicating that the second LPW flit is a switching frequency. Respond to commands.
  • the format of the second sideband control command is similar to the format of the sideband signal shown in Table 3, where the bit value of the type[2:0] field may be 011.
  • the second die may stop sending service data to the first die when sending the second LPW flit. After the second die completes sending the second LPW flit, it can continue to send service data to the first die normally.
  • the second die can normally send service data to the first die, that is, it does not affect the sending of normal service data by the second die.
  • a timer can be started. If the first die does not receive a frequency switching response within the timed time, the first die passes the data link (downstream link ) can send the frequency switching request again, or the first die continues to send empty flow control units (NULL flit) to the second die through the data link until the frequency switching response sent by the second die is received.
  • NULL flit empty flow control units
  • the timing time is greater than the two-way transmission delay of the interconnection interface and can be configured during the specific implementation process.
  • the business between the first die and the second die can be maintained uninterrupted, and the first die and the second die can transfer the received business
  • the data is cached.
  • the second die when the second die receives the first LPW flit, the second die may adjust the priority of the second LPW flit to be sent to the highest priority to send the first LPW flit to the first die first. Two LPW flits.
  • the first die determines to complete the frequency switching negotiation with the second die, it responds to the application layer that the frequency switching negotiation is completed.
  • steps 701 to 704 can be understood as completing frequency switching negotiation at the data link layer of the first die and the second die.
  • the first die When the first die receives the frequency switching response, it determines that frequency negotiation is completed with the second die, and may respond to the application layer of the first die that the frequency switching negotiation is completed.
  • the response here can be understood as a response to the frequency mode configuration command in step 701.
  • the application layer of the first die stops sending service data to the first die, and switches the working clock frequency of the SoC domain of the first die.
  • the data link layer of the first die stops receiving service data from the application layer.
  • the first die may cache the service data that has been received but has not yet been sent to the second die.
  • the SoC domain of the first die continues to send service data (service packets) to the second die.
  • the working clock frequency of the SoC domain of the first die switched here includes the transmit clock frequency of the SoC domain in the first die.
  • the first die chip stops sending the associated clock to the second die chip, and adjusts the operating frequency of the sending circuit of the first die chip according to the frequency level.
  • the clock of the transmitting circuit in the first die can be connected to the clock of the receiving circuit in the second die through a clock line.
  • the clock of the receiving circuit in the second bare chip is a clock associated with the clock of the transmitting circuit in the first bare chip.
  • the first die adjusts the operating frequency of the transmitting circuit of the first die according to the frequency level. It can be understood that the first die adjusts the operating frequency of the transmission circuit of the first die according to the training parameters pre-stored in the interconnection interface circuit of the first die, that is, the frequency level and the circuit configuration parameters. The corresponding relationship is to determine the circuit configuration parameters under the new frequency level, so as to configure the circuit parameters of the first die according to the circuit configuration parameters, so that the configured circuit parameters of the first die adapt to the new frequency level.
  • the circuit configuration parameters in the training parameters of the first die can be understood as the circuit configuration parameters of the transmitting circuit in the interconnection interface circuit of the first die.
  • the training parameters may be pre-stored before the die is shipped.
  • the first die sends a frequency switching instruction to the second die.
  • the first die may send a frequency switching indication to the second die through a sideband signal command (SBC_SYNC_IND), and the frequency switching indication is used to instruct the second die to perform frequency switching.
  • SBC_SYNC_IND sideband signal command
  • This sideband signal command can be found in Table 3 and Table 5. Among them, the value of the type[2:0] field in the sideband signal command can be "111", and the value of the opcode[7:0] field can be "11111111".
  • the second die adjusts the operating frequency of the receiving circuit of the second die according to the frequency level.
  • the second die determines circuit configuration parameters based on the information indicating the frequency level after switching, and configures circuit parameters for the receiving circuit in the interconnection interface circuit of the second die based on the circuit configuration parameters.
  • the second die adjusting the operating frequency of the transmitting circuit of the second die according to the frequency level can be understood as the second die adjusting the operating frequency of the transmitting circuit of the second die according to the pre-stored training parameters in the interconnection interface circuit of the second die, that is, the frequency level and circuit
  • the corresponding relationship between the configuration parameters is determined to determine the circuit configuration parameters under the new frequency level, so as to configure the circuit parameters of the receiving circuit of the second bare chip according to the circuit configuration parameters, so that the configured circuit parameters of the receiving circuit of the second bare chip are suitable. Configure new frequency level.
  • the training parameters of the first die and the training parameters of the second die may be the same or different.
  • the training parameters of the first die and the training parameters of the second die are different, it can be understood that the training parameters of the first die and the training parameters of the second die are the same at multiple frequency levels. Circuits at the same frequency level The configuration parameters are different.
  • the training parameters of the first die and the training parameters of the second die are the same, it may also be that when the first die and the second die are powered on and initialized, the first die will store the training parameters. The parameters are sent to the second die.
  • the circuit parameter configuration of the first die may be completed before the first die sends a frequency switching request to the second die, or before the first die sends a frequency switching request to the second die.
  • the configuration is completed during the process, or the first die is configured after receiving the frequency switching response, or the configuration is completed after the application layer switches the clock frequency of the SoC domain. That is, the time when the first die and the second die complete circuit parameter configuration may not be synchronized.
  • the first die After waiting for a fixed delay, the first die starts the associated clock of the first die.
  • the fixed delay needs to cover the stabilization time after the second die switches the frequency and the stabilization time after the first die switches the frequency.
  • the first die sends data to the second die at the frequency level.
  • the second die receives the data sent by the first die at the frequency level.
  • the first die when the first die receives an indication from the second die that the circuit parameter configuration is completed, and when the first die also completes the circuit parameter configuration, the first die may operate at the switched frequency level. , sending service data to the second die.
  • the training parameters of the interconnection interface of the die can be pre-stored in the circuit of the die, and can be processed through the high-speed data channel or edge.
  • both dies can call the stored training parameters according to the frequency level to complete the fast switching of the frequency level.
  • the switching processing delay can be reduced when achieving fast switching at the frequency level, which is equivalent to reducing the backpressure time for service data.
  • the digital logic of the digital link layer of the first die can be based on the SoC domain. Dynamic voltage adjustment is performed based on frequency changes to achieve Dynamic Voltage and Frequency Scaling (DVFS), which can further reduce the power consumption of the first die. Similarly, the power consumption of the second die can also be reduced.
  • DVFS Dynamic Voltage and Frequency Scaling
  • the above-mentioned bare chip includes corresponding hardware structures and/or software modules for executing each function.
  • Persons skilled in the art should easily realize that, in conjunction with the units and algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software driving the hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.
  • Embodiments of the present application can divide the above-mentioned bare chip into functional modules according to the above-mentioned method examples.
  • each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. In actual implementation, there may be other division methods.
  • Figure 11 shows a possible composition diagram of the bare chip 110 involved in the above embodiment.
  • the bare chip 110 may include: a sending unit 1101, adjustment unit 1102 and receiving unit 1103.
  • the sending unit 1101 can be used to implement the sending circuit function of the interconnection interface in the above-mentioned bare chip
  • the receiving unit 1103 can be used to implement the sending function of the receiving circuit in the interconnection interface in the above-mentioned bare chip
  • the adjustment unit 1102 may be used to implement the function of switching the operating frequency of the SoC domain, the operating frequency of the transmitting circuit, and the operating frequency of the receiving circuit in the above-mentioned die.
  • the sending unit 1101 may be used to support the die 110 to perform the above steps 501, 702, 704, 705, 708, 711, etc., and/or other processes for the technology described herein.
  • the adjustment unit 1102 may be used to support the die 110 in performing the above-described steps 502, 703, 706, 707, 709, 710, etc., and/or other processes for the techniques described herein.
  • the receiving unit 1103 may be used to support the die 110 in performing steps 701, etc. described above, and/or other processes for the techniques described herein.
  • the bare chip 110 provided in this embodiment is used to perform the above frequency adjustment method, and therefore can achieve the same effect as the above implementation method.
  • the embodiment of the present application discloses a bare chip 120.
  • the bare chip 120 can be the chip system in the above embodiment, such as a small chip/die of a chiplet system.
  • Die 120 may include processing modules, memory modules, and communications modules.
  • the processing module may be used to control and manage the actions of the bare chip 120 , for example, may be used to support the bare chip 120 in executing the process of the adjustment unit 1102 .
  • the memory module can be used to support the die 120 to store program code, data, etc.
  • the storage module stores the training data in this application, including circuit configuration parameters corresponding to frequency levels.
  • the communication module can be used to support communication between the die 120 and other die.
  • the communication module may include the interconnection interface in this application.
  • the unit modules in the above-mentioned bare chip 120 include but are not limited to the above-mentioned processing modules, storage modules and communication modules.
  • the die 120 may also include a power module and the like. The power module is used to power the die 120 .
  • the processing module may be a processor or a controller. It may implement or execute the various illustrative logical blocks, modules, and circuits described in connection with this disclosure.
  • a processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc.
  • the storage module may be a memory.
  • the communication module may specifically be a device such as a chip interface that interacts with other external devices.
  • the processing module is the processor 1301, the storage module can be the memory 1302, and the communication module can be called the communication interface 1303, such as the interconnection interface in this application.
  • the bare chip 120 provided in the embodiment of the present application may be the chip 130 shown in FIG. 13 .
  • the above-mentioned processors, memories, communication interfaces, etc. may be connected together, for example, through a bus.
  • An embodiment of the present application also provides a communication device, including one or more processors and one or more memories.
  • the one or more memories are coupled to one or more processors, and the one or more memories are used to store computer program codes.
  • the computer program codes include computer instructions that, when executed by the one or more processors, cause the communication device to perform The above related method steps implement the frequency modulation method in the above embodiment.
  • Embodiments of the present application also provide a computer-readable storage medium.
  • Computer program code is stored in the computer-readable storage medium.
  • the communication device executes the frequency modulation method in the above embodiment.
  • Embodiments of the present application also provide a computer program product.
  • the computer program product When the computer program product is run on a computer, it causes the computer to perform the above related steps to implement the frequency modulation method performed by the communication device in the above embodiment.
  • the communication device provided by this embodiment such as a bare chip, a computer storage medium, a computer program product or a chip, is used to execute the corresponding method provided above. Therefore, the beneficial effects it can achieve can be referred to the above. The beneficial effects of the corresponding methods provided will not be described again here.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be The combination can either be integrated into another device, or some features can be omitted, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated.
  • the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or contribute to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium , including several instructions to cause a device (which can be a microcontroller, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code.

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Abstract

本申请实施例公开了一种调频方法和装置，涉及芯片技术领域，能够实现Chiplet系统中SoC域和互联接口的时钟频率的快速切换，减小业务数据所需的缓存空间。该方法应用于芯片系统，芯片系统包括第一裸片和第二裸片，该方法包括：第一裸片向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息；第二裸片根据频率级别调整第二裸片的接收电路的工作频率。本申请实施例用于对芯片系统中的裸片进行调频。

Description

一种调频方法和装置 技术领域
本申请涉及芯片技术领域，尤其涉及一种调频方法和装置。
背景技术
在芯片系统(Chiplet)中，为了实现整个Chiplet中通路的低延时，Chiplet中裸片与裸片(die-to-die)的互联接口的时钟频率可与SoC域(domain)的时钟频率采用同步设计，减小因异步处理带来的延时增加。此时，当SoC域时钟频率调整时，互联接口的时钟频率也需要同步调整。
在动态调频过程中，业务数据依然存在，SoC域的时钟频率切换时，业务数据需要在系统中进行缓存。当切换延时较大时，不仅导致业务延时较大，也会增加业务数据的缓存空间。因此，如何降低Chiplet中的时钟频率切换延时是一个亟待解决的问题。
发明内容
本申请实施例提供一种调频方法和装置，能够实现Chiplet系统中SoC域和互联接口的时钟频率的快速切换，减小业务数据所需的缓存空间。
为达到上述目的，本申请实施例采用如下技术方案：
第一方面，提供一种调频方法，该方法应用于芯片系统，芯片系统包括第一裸片和第二裸片，该方法包括：第一裸片向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息；第二裸片根据频率级别调整第二裸片的接收电路的工作频率。
本申请中的频率级别也可称为频率档位。本申请相当于将芯片系统中裸片间的频率级别提前训练好，每种频率级别对应一种工作频率。当第一裸片和第二裸片在进行业务数据传输过程中，如果第一裸片的发送电路的工作频率切换，需要第二裸片和适应性进行接收电路的工作频率的调整。本申请在通过第一裸片向第二裸片发送了指示切换后的频率级别的信息时，可使得第二裸片根据该切换后的频率级别的信息快速进行该频率级别对应的接收电路工作频率的调整。
因此，本申请相对于PCIE链路中进行速率的切换时，还需要每次进入recovery状态进行链路重新训练后再切换回L0状态，从而使得切换延时较长的问题，本申请进行频率切换的延时较短。此外，本申请相对于通过调整互联接口间的Lane数量进行裸片间的速率切换带来的接口功耗无法优化的问题，直接通过裸片间交互指示频率级别的信息实现工作频率切换，在进行工作频率切换时，可使得接口功耗相应得到调整。
而且，通常，在进行裸片间的频率切换时，为了保持业务流不间断，需要对业务数据进行缓存。在本申请在实现裸片间的频率快速切换的基础上，也可使得业务数据缓存所需的缓存空间减小。
在一种可能的设计中，第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中。或者说，第一裸片的SoC域、发送电路和第二裸片的接收电路都在同一个时钟域中。这样，当第一裸片的SoC域、发送电路的工作频率调制时，第一裸片和第二裸 片在数据链路层的数字逻辑能够根据SoC域的频率变化进行动态电压调整，进而能够进一步降低功耗。
在一种可能的设计中，在第一裸片向第二裸片发送频率切换请求之前，该方法还包括：第一裸片接收应用层发送的频率模式配置命令，频率模式配置命令包括第一指示信息，第一指示信息用于指示切换后的频率级别；第一裸片根据频率模式配置命令生成频率切换请求。
该设计中，当第一裸片的应用层的业务类型变化时，第一裸片对该业务类型的业务流处理的工作频率也会相应变化，以使得变化后的工作频率适应新的业务类型。因此，当第一裸片的应用层确定要变更第一裸片的工作频率时，可向第一裸片发送频率模式配置命令，以指示切换后的频率级别。例如，在应用层保存有不同的业务类型对应的频率级别。
在一种可能的设计中，在第二裸片调整第二裸片的接收电路的工作频率之前，该方法还包括：第一裸片停止从应用层接收业务数据。
或者说，第一裸片的应用层确定要进行频率调制时，第一裸片的应用层停止向第一裸片的SoC域发送业务数据，以便第一裸片可进行频率调整，以及与第二裸片进行交互切换后的频率级别。
在一种可能的设计中，第一裸片向第二裸片发送频率切换请求包括：第一裸片通过第一低功耗控制字LPW流控制单元或第一边带控制命令向第二裸片发送频率切换请求；该方法还包括：第一裸片通过第二LPW流控制单元或第二边带控制命令接收第二裸片发送的频率切换响应。
其中，第一LPW flit可理解为第一裸片通过数据链路向第二裸片发送的。第一边带控制命令可理解为第一裸片通过边带控制通道向第二裸片发送的。相应地，第二LPW flit为第二裸片通过数据链路向第一裸片发送的。第二边带控制命令是第二裸片通过边带控制通道向第一裸片发送的。
在一种可能的设计中，第一LPW流控制单元包括流控制单元头字段、流控制单元内容字段和流控制单元尾字段；其中，流控制单元内容字段包括类型子字段和命令子字段，类型子字段用于指示第一LPW流控制单元为频率切换命令，命令子字段用于指示频率级别。
在一种可能的设计中，第一边带控制命令包括指示消息类型的字段、指示消息编码的字段、指示路径标识的字段和指示校验位的字段；其中，指示消息类型的字段用于指示第一边带控制命令为频率切换命令。
在一种可能的设计中，在第二裸片调整第二裸片的接收电路的工作频率之前，该方法还包括：第一裸片停止向第二裸片发送随路时钟，并根据频率级别调整第一裸片的发送电路的工作频率。
该设计中，第一裸片和第二裸片间可存在时钟Lane，第二裸片中的接收电路接收第一裸片的发送电路发送的业务数据，是根据第一裸片通过该时钟Lane发送的随路时钟的时钟频率接收的。如果第一裸片要进行频率切换时，可停止向第二裸片发送随路时钟，以便在切换第一裸片的发送电路的工作频率后，在新的工作频率下通过该时钟Lane向第二裸片发送新的工作频率的随路时钟。这样，第二裸片的接收电路的时钟频 率也相应地得到调整。
在一种可能的设计中，在第二裸片调整第二裸片的接收电路的工作频率之前，该方法还包括：第一裸片持续向第二裸片发送空的流控制单元，直至接收到第二裸片发送的频率切换响应。
或者，第一裸片持续向第二裸片发送频率切换命令，直至接收到第二裸片发送的频率切换响应。
在一种可能的设计中，在第二裸片调整第二裸片的接收电路的工作频率之前，该方法还包括：第一裸片确定与第二裸片完成频率切换协商后，向应用层响应频率切换协商完成。
即在第一裸片接收到应用层发送的频率切换配置命令后，如果第一裸片完成与第二裸片的频率切换协商后，可向第一裸片的应用层响应频率切换协商完成，以便应用层启动第一裸片的SoC域的频率切换。
在一种可能的设计中，在第二裸片调整第二裸片的接收电路的工作频率之前，该方法还包括：第一裸片向第二裸片发送频率切换指示，频率切换指示用于指示第二裸片进行频率切换。
这里第一裸片向第二裸片发送频率切换指示时，第一裸片有可能开始进行第一裸片的发送电路的工作频率切换，也可能正在进行第一裸片的发送电路的工作频率切换，也有可能完成了第一裸片的发送电路的工作频率切换。当第二裸片接收到频率切换指示时，第二裸片便可开始进行第二裸片的接收电路的频率切换。
本申请中，第一裸片进行第一裸片的发送电路的频率切换，可理解为第一裸片根据频率级别确定发送电路的电路配置参数，并根据发送电路的电路配置参数进行发送电路的电路参数配置。类似的，第二裸片进行第二裸片的接收电路的频率切换，可理解为第二裸片根据频率级别确定接收电路的电路配置参数，并根据接收电路的电路配置参数进行接收电路的电路参数配置。
在一种可能的设计中，该方法还包括：第一裸片等待固定延时后，启动第一裸片的随路时钟。
通常，该固定延时应覆盖第二裸片切换工作频率后的稳定时间以及第一裸片切换工作频率后的稳定时间。这样，相当于给了第一裸片和第二裸片足够的时间完成频率切换，以便在双方完成频率切换后，第一裸片启动新的工作频率下的随路时钟，开始和第二裸片进行业务数据交互。
在一种可能的设计中，该方法还包括：第一裸片在频率级别下，向第二裸片发送数据；第二裸片在频率级别下，接收第一裸片发送的数据。
如此一来，第一裸片和第二裸片通过频率级别的信息的交互完成工作频率切换后，在新的工作频率下进行业务数据的交互。
第二方面，提供一种调频方法，该方法应用于芯片系统，芯片系统包括第一裸片和第二裸片，该方法包括：第二裸片接收第一裸片发送的频率切换请求，频率切换请求包括指示切换后的频率级别的信息；第二裸片根据频率级别调整第二裸片的接收电路的工作频率。
第二方面的有益效果可参见第一方面的说明。
在一种可能的设计中，第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中。
在一种可能的设计中，第二裸片接收第一裸片发送的频率切换请求包括：第二裸片通过第一低功耗控制字LPW流控制单元或第一边带控制命令接收第一裸片发送频率切换请求；该方法还包括：第二裸片通过第二LPW流控制单元或第二边带控制命令向第一裸片发送频率切换响应。
在一种可能的设计中，该方法还包括：第二裸片接收到第一裸片发送的频率切换请求时，记录指示切换后的频率级别的信息。
在一种可能的设计中，在第二裸片根据频率级别调整第二裸片的接收电路的工作频率之前，该方法还包括：第二裸片接收第一裸片发送的频率切换指示，频率切换指示用于指示第二裸片进行频率切换。
第三方面，提供一种调频方法，该方法应用于芯片系统，芯片系统包括第一裸片和第二裸片，该方法包括：第一裸片向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息；第一裸片根据频率级别调整第一裸片的发送电路的工作频率。
第三方面的有益效果可参见第一方面的说明。
在一种可能的设计中，第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中。
在一种可能的设计中，第一裸片向第二裸片发送频率切换请求包括：第一裸片通过第一低功耗控制字LPW流控制单元或第一边带控制命令向第二裸片发送频率切换请求；该方法还包括：第一裸片通过第二LPW流控制单元或第二边带控制命令接收第二裸片发送的频率切换响应。
第四方面，提供一种芯片系统，芯片系统包括第一裸片和第二裸片，其中：第一裸片，用于向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息；第二裸片，用于根据频率级别调整第二裸片的接收电路的工作频率。
第四方面的有益效果可参见第一方面的说明。
在一种可能的设计中，第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中。
在一种可能的设计中，第一裸片用于：接收应用层发送的频率模式配置命令，频率模式配置命令包括第一指示信息，第一指示信息用于指示切换后的频率级别；根据频率模式配置命令生成频率切换请求。
在一种可能的设计中，第一裸片用于：通过第一低功耗控制字LPW流控制单元或第一边带控制命令向第二裸片发送频率切换请求；通过第二LPW流控制单元或第二边带控制命令接收第二裸片发送的频率切换响应。
第五方面，提供一种第二裸片，芯片系统包括第一裸片和第二裸片，第二裸片包括：接收器，用于接收第一裸片发送的频率切换请求，频率切换请求包括指示切换后的频率级别的信息；处理器，用于根据频率级别调整第二裸片的接收电路的工作频率。
在一种可能的设计中，第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中。
在一种可能的设计中，接收器，用于：通过第一低功耗控制字LPW流控制单元或第一边带控制命令接收第一裸片发送频率切换请求；接收器还用于：通过第二LPW流控制单元或第二边带控制命令向第一裸片发送频率切换响应。
在一种可能的设计中，处理器，还用于：在接收器用于接收到第一裸片发送的频率切换请求时，记录指示切换后的频率级别的信息。
在一种可能的设计中，接收器，还用于：接收第一裸片发送的频率切换指示，频率切换指示用于指示第二裸片进行频率切换。
第六方面，提供一种第一裸片，芯片系统包括第一裸片和第二裸片，第一裸片包括：发射器，用于向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息；处理器，用于根据频率级别调整第一裸片的发送电路的工作频率。
在一种可能的设计中，第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中。
在一种可能的设计中，发送器，用于：通过第一低功耗控制字LPW流控制单元或第一边带控制命令向第二裸片发送频率切换请求；还包括接收器，用于通过第二LPW流控制单元或第二边带控制命令接收第二裸片发送的频率切换响应。
第七方面，本申请实施例提供一种芯片系统，所述芯片系统包括如第一方面至第三方面的任一种可能的设计所述的裸片；所述芯片系统包括多个裸片，每个裸片包括接口电路和处理器(SoC域)；该接口电路和该处理器通过线路互联；所述处理器通过所述接口电路从芯片系统外的存储器接收并执行计算机指令。
第八方面，本申请实施例提供一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述第一方面以及第一方面的任一种可能的设计所述的方法。
第九方面，本申请实施例提供一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述第二方面以及第二方面的任一种可能的设计所述的方法。
第十方面，本申请实施例提供一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述第三方面以及第三方面的任一种可能的设计所述的方法。
第十一方面，本申请实施例提供一种计算机程序产品，当计算机程序产品在计算机或处理器上运行时，使得计算机或处理器执行上述第一方面及任一项可能的实现方式中的方法。
第十二方面，本申请实施例提供一种计算机程序产品，当计算机程序产品在计算机或处理器上运行时，使得计算机或处理器执行上述第二方面及任一项可能的实现方式中的方法。
第十三方面，本申请实施例提供一种计算机程序产品，当计算机程序产品在计算机或处理器上运行时，使得计算机或处理器执行上述第三方面及任一项可能的实现方式中的方法。
可以理解的是，上述提供的任一种第一裸片、第二裸片、芯片系统、计算机可读存储介质或计算机程序产品等均可以应用于上文所提供的对应的方法，因此，其所能 达到的有益效果可参考对应的方法中的有益效果，此处不再赘述。
本申请的这些方面或其他方面在以下的描述中会更加简明易懂。
附图说明
图1为本申请实施例提供的一种裸片间耦合的电路示意图；
图2为本申请实施例提供的一种PCIE链路中进行频率切换的状态切换示意图；
图3为本申请实施例提供的一种裸片间通过适配不同的Lane达到切换速率的目的示意图；
图4为本申请实施例提供的一种芯片系统示意图；
图5为本申请实施例提供的一种调频方法流程示意图；
图6为本申请实施例提供的一种裸片间的互联接口和SoC域耦合的电路示意图；
图7为本申请实施例提供的一种调频方法流程示意图；
图8为本申请实施例提供的一种裸片间的边带信号接口互联示意图；
图9为本申请实施例提供的一种边带信号接口以报文的方式进行传输时的时序示意图；
图10为本申请实施例提供的一种边带控制信号的格式示意图；
图11为本申请实施例提供的一种裸片的结构示意图；
图12为本申请实施例提供的一种裸片的结构示意图；
图13为本申请实施例提供的一种芯片的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请实施例的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，在本申请实施例的描述中，“多个”是指两个或多于两个。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
Chiplet系统，也可以称为芯片系统，是不同功能裸片(die)的拼搭，某种意义上也是不同IP的拼搭，从系统端出发，首先将复杂功能进行分解，然后开发出多种具有单一特定功能、可相互进行模块化组装的裸片，如实现数据存储、计算、信号处理、数据流管理等功能，并最终以此为基础，建立一个Chiplet的芯片网络。或者，还可以理解为是通过die-to-die内部互联技术将多个模块芯片与底层基础芯片封装在一起，构成多功能的异构System in Packages(SiPs)芯片的模式。
在Chiplet系统中，低延时和低功耗为关键特性。在实际工作场景中，die-to-die的互联接口的带宽会跟随业务带宽的变化而变化。接口功耗也会跟随带宽的变化而变化，在低业务带宽时可实现功耗等比例降低。
同时，为了实现整个die-to-die通路的低延时，互联接口的时钟频率可以与die中的SoC域采用同步设计，以减小因异步处理带来的延时增加。如图1所示，裸片包括 SoC域和互联接口电路。互联接口电路包括发送电路、接收电路和边带控制信道。SoC域可向互联接口电路的发送电路传输应用数据(application data)，即业务数据。SoC域还可通过互联接口电路的边带控制信道传输控制信号。
其中，裸片1中的SoC域、裸片1在互联接口中的发送电路，以及裸片2在互联接口中的接收电路，在同一个时钟域中。当裸片1中的SoC域的时钟频率变化时，裸片1在互联接口中的发送电路和裸片2在互联接口中的接收电路的时钟频率也需要同步调整。其中，裸片1在互联接口中的发送电路可作为裸片1的链路主设备(link master)，裸片2在互联接口中的接收电路可作为裸片2的链路从设备(link slave)。
同理，裸片2中的SoC域、裸片2在互联接口中的发送电路，以及裸片1在互联接口中的接收电路，在同一个时钟域中。当裸片2中的SoC域的发送电路的时钟频率变化时，裸片2互联接口中的发送电路和裸片1在互联接口中的接收电路的时钟频率也需要同步调整。其中，裸片2在互联接口中的发送电路可作为裸片2的link master，裸片1在互联接口中的接收电路可作为裸片1的link slave。
图1中还示出了裸片1中的SoC域和裸片1在互联接口中的接收电路间通过异步电路耦合。考虑到异步电路主要是组合逻辑电路，不使用时钟脉冲做同步，一般通过握手协议实现不同部件之间的数据同步、通信以及运算顺序。当该异步电路接收到该接收电路的数据时，需按照握手协议向裸片1中的SoC域发送数据。因此，裸片1中的SoC域与裸片1中的接收电路的时钟为异步时钟域。类似的，裸片2中的SoC域与裸片2在互联接口中的接收电路的时钟也为异步时钟域。裸片1和裸片2可通过边带控制信道(sideband control channel)传输边带信号(sideband signal)。当裸片1为主芯片，裸片2为从芯片时，裸片1中的发送电路可通过下游链路(downstream link)向裸片2的接收电路发送下游数据，裸片2中的发送电路可通过上游链路(upstream link)向裸片1中的link slave发送上游数据。其中，裸片1和裸片2间可通过流控制单元(flow control unit，flit)传输上游数据和下游数据。
另外，在调频过程中，业务数据依然存在，切换过程中的业务数据需进行缓存。因此，降低切换延时有助于减小缓存空间，同时也可减小切换过程中造成的业务延时。
目前，在高速互联方案中，不同时钟频率切换后，为了保持时延的稳定性以及链路状态传输性能的稳定，在高速串行计算机扩展总线标准(peripheral component interconnect express，PCIE)链路中，时钟频率变化时，状态机需要将L0状态切换进入重置(Recovery)状态进行链路重新训练(Re-Training)。在训练完成后，再切换回L0状态。如图2所示，其中，L0状态是PCIE链路的正常工作状态，在该状态下，PCIE链路可以正常发送和接收数据。
但是，该方案中，重新训练的过程需要的时间较长，会导致不同时钟频率切换到链路稳定的时间较长。而且，频率切换过程中业务数据依然存在，会增加业务数据所需的缓存空间，不适用于对链路切换实时性要求高的场景。
在一种匹配速率切换的方案中，可通过适配不同的路径(lane)数量达到切换速率的目的。但是，这种场景中，如图3所示，互联接口与SoC域间通过异步电路耦合，单个裸片中的互联接口的时钟域与SoC域的时钟域为不同的时钟域，即为异步时钟域，互联接口的时钟域与SoC域的时钟域不使用时钟脉冲同步。互联接口工作在固定的频 率上，SoC域的时钟频率调整时，互联接口的时钟频率保持不变，通过调整互联接口的Lane数量匹配互联接口的速率。在该方案中，这种异步处理会增加延时。并且，互联接口是根据不同的Lane数量匹配速率的变化的，当互联接口的速率降低时，互联接口的数字部分无法跟随速率的降低来降低工作电压，互联接口的功耗性能较差。
由此，本申请提供一种调频方法，能够在Chiplet中实现动态调整互联接口频率。通过裸片间交互不同的频率级别的指示信息，实现频率档位的快速切换，降低链路切换时延。
本申请的调频方法中，当SoC域的工作频率变化时，裸片间的互联接口的工作频率也随之变化。在调频之前，可对每个频率级别下的互联接口的电路配置参数在初始化过程中分别进行训练，并在每个裸片中保存训练结果。当发送端需要跟随SoC域的工作频率进行互联接口的频率调整时，发送端通过交互流程告知接收端需要切换的频率级别的指示，接收端可根据频率级别的指示从训练参数中查询对应的电路配置参数，以切换至该频率级别。
本申请实施例可应用于Chiplet系统中。在该Chiplet系统中，包括多个具有特定功能、可相互进行模块化组装的裸片，如裸片可实现数据存储、计算、信号处理、数据流管理等功能。基于丰富的IP储备，Chiplet系统提出了IP芯片化(IP as a Chiplet，IaaC)的理念，旨在以裸片实现特殊功能IP的“即插即用”。例如，对于一些核心处理器IP，裸片可为图形处理器(Graphics Processing Unit，GPU)IP、神经网络处理器(Neural-network Unit，NPU)IP、视频处理器(Video Processing Unit，VPU)IP、数字信号处理器(digital signal processing，DSP)IP、图像信号处理器(Image Signal Processor，ISP)IP和显示处理器IP等。此外，裸片还可以是数模混合IP和射频IP等。
本申请中的Chiplet系统，即芯片系统，还可以称为小芯片系统或芯粒系统。在小芯片系统中，裸片还可以称为小芯片，在芯粒系统中，裸片还可以称为芯粒。
示例性的，该Chiplet系统可以应用在系统级芯片(System-on-a-Chip，SoC)，在SoC上集成有多种功能的裸片，例如芯片系统包括如图4所示的第一裸片和第二裸片。第一裸片可通过数据信道与第二裸片进行业务数据/应用数据的传输，数据信道包括上文中的下游链路和上游链路。第一裸片可通过边带控制信道与所述第二裸片进行控制信号的传输。
当第一裸片的发送电路的工作频率变化时，可向第二裸片发送指示切换后的频率级别的信息。第二裸片可根据频率级别调整接收电路的工作频率，实现裸片间的频率快速切换。
在一些实施例中，第一裸片和第二裸片可理解为初始化和电源管理中具有不同功能的两个芯片的角色。例如，第一裸片为主机处理器芯片，主机可启动流以进入低功耗状态，并配合低功耗状态进行频率切换。第二裸片为连接到主机处理器芯片的芯片，作为从处理器芯片。例如，第二裸片为内存芯片。从处理器芯片一般不能启动流进入低功耗状态，可响应主机处理器芯片的流进入低功耗状态。
下面对本申请的调频方法进行介绍。
本申请实施例提供一种调频方法，该方法应用于芯片系统(Chiplet系统)，芯片 系统包括第一裸片和第二裸片，如图5所示，该方法包括以下流程。
501、第一裸片向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息。
示例性的，当第一裸片中的SoC域的工作频率切换时，可向第二裸片发送指示切换后的频率级别的信息，以便第二裸片也同步切换接收电路的工作频率。
其中，频率级别也可以理解为频率档位。
在一些实施例中，本申请中的频率级别用于指示预设的与业务对应的频率模式或频率参数。在第二裸片中，可预存有频率模式或频率参数对应的电路配置参数。这样当第二裸片在根据频率模式或频率参数确定对应的电路配置参数时，第二裸片可根据确定的电路配置参数调整接收电路中的器件参数，从而调整接收电路的工作频率，使得接收电路能够处理对应的业务速率下的数据。
示例性的，这里的器件参数例如包括电容、电阻、电感或寄存器配置等参数，还可包括接收滤波器和接收电平相关的参数等。
502、第二裸片根据频率级别调整第二裸片的接收电路的工作频率。
第二裸片在根据频率级别调整接收电路的工作频率，可理解为第二裸片根据频率级别调整接收电路的电路配置参数。
在一些实施例中，可与先训练得到多种训练参数，每种训练参数包括一种频率级别对应的电路配置参数。当第二裸片接收到指示切换后的频率级别的信息时，可根据指示切换后的频率级别的信息确定对应的电路配置参数，以根据电路配置参数完成电路配置。
当第一裸片的发送电路和第二裸片的接收电路都完成了电路配置参数的调整后，第一裸片和第二裸片切换频率完成，第一裸片的发送电路在切换后的频率下发送数据，第二裸片的接收电路在切换后的频率下接收数据。
由此，在本申请中，在Chiplet系统裸片间的频率级别和调整工作频率的参数提前训练好的情况下，通过裸片间交互频率级别切换的信息，裸片进行工作频率切换时，可根据指示切换后的频率级别的信息调用存储的训练参数完成频率的快速切换。
在一些实施例中，本申请的调频方法中，裸片间的互联接口和SoC域在同一个时钟域中，SoC域通过互联接口传输数据时不需要进行异步处理。如图6所示，第一裸片的SoC域、第一裸片中的发送电路和第二裸片中的接收电路在同一个时钟域中，记为时钟域1。当第一裸片中的SoC域进行时钟频率切换时，第一裸片中的发送电路和第二裸片中的接收电路都需要进行时钟频率切换。第一裸片可根据预存的训练参数，即频率级别对应的电路配置参数对第一裸片的发送电路进行电路配置，第二裸片也根据频率级别对应的电路配置参数对第二裸片的接收电路进行电路配置。
类似的，第二裸片中的SoC域、第二裸片中的发送电路和第一裸片中的接收电路在同一个时钟域中，记为时钟域2。当第二裸片中的SoC域进行时钟频率切换时，第二裸片中的发送电路和第一裸片中的接收电路都需要进行时钟频率切换。第一裸片可预存的训练参数，即根据频率级别对应的电路配置参数对第一裸片的发送电路进行电路配置，第二裸片也根据频率级别对应的电路配置参数对第二裸片的接收电路进行电路配置。
在一些实施例中，当第一裸片根据应用层确定需进行频率切换时，也可以是第一裸片中的发送电路、第一裸片中的接收电路、第二裸片中的接收电路和第二裸片中的发送电路都进行工作频率的重配置，即都进行电路配置参数的重配置。
下面对本申请实施例进一步进行说明。
本申请实施例提供一种调频方法，该方法应用于芯片系统(Chiplet系统)，芯片系统包括第一裸片和第二裸片，如图7所示，该方法包括以下流程。
701、第一裸片接收应用层发送的频率模式配置命令，频率模式配置命令包括第一指示信息，第一指示信息用于指示切换后的频率级别。
该应用层可理解为第一裸片的应用服务。
示例性的，当应用层确定业务类型变化，且业务类型的业务数据需要在新的频率级别下传输时，应用层可向第一裸片发送频率模式(frequency mode)配置命令，向第一裸片指示切换后的频率级别。例如应用层向第一裸片的SoC域发送频率模式配置命令。
702、第一裸片根据频率模式配置命令生成频率切换请求，通过第一低功耗控制字(low power word，LPW)flit或第一边带控制(sideband command)命令向第二裸片发送频率切换请求，频率切换请求包括指示切换后的频率级别的信息。
相应地，第二裸片通过第一LPW flit或第一边带控制命令接收第一裸片发送的频率切换请求。
其中，LPW可理解为通过低功耗、低数据速率和低成本进行通信的信号。
边带(Sideband)是指调制后的信号。即在中心载频的上下两侧各产生一个频带，称作边带。边带控制命令即为通过边带传输的控制命令。一般通过边带地址(Sideband Address)传输该边带控制命令。
在一些实施例中，第一裸片在发送第一LPW flit时，停止向第二裸片发送业务数据。当第一裸片在发送完频率切换请求后，可继续正常向第二裸片发送业务数据。
在一些实施例中，第一裸片在发送第一边带控制命令时，可正常向第二裸片发送业务数据，即不影响正常的业务数据的发送。
在一些实施例中，第一裸片的SoC域通过第一裸片的发送电路向第二裸片的接收电路发送第一LPW flit，第一LPW flit相当于本申请中的切换请求。结合图6的说明，第一LPW flit是第一裸片的发送电路通过下游链路向第二裸片发送的。
其中，下游链路和上游链路可为高速数据信道。例如当互联接口为高速串行接口时，高速串行接口例如为PCIE或通用串行总线(Universal Serial Bus，USB)等，PCIE或USB可通过高速数据信道在裸片间传输业务数据。
这种情况下，以高速串行接口为PCIE为例，第一裸片的PCIE可通过高速数据信道向第二裸片的PCIE传输第一LPW flit。
示例性的，第一LPW flit包括flit头(Header)字段、flit内容(payload)字段和flit尾(Tail)字段，所述flit payload字段包括类型子字段(SUB_TYPE)和命令子字段(CMD)，所述类型子字段用于指示所述第一LPW flit为频率切换命令，所述命令子字段用于指示频率级别。如表1所示为一种LPW flit的格式示例。
表1 LPW flit的格式
Figure PCTCN2022114623-appb-000001
当Flit Header字段中的Type子字段的比特值为“0”时，指示第一LPW flit为控制flit，可用于向第二裸片指示执行第一LPW flit指示的控制命令。当Flit payload字段中的SUB_TYPE子字段的比特值为“1100”时，指示第一LPW flit为频率切换命令。Flit payload字段中的CMD子字段的比特值也可以为多种比特值(’b00000000～‘b11111111)中的一种，用于指示频率级别N，N为整数。例如CMD子字段的比特值为N为00000001时，N的值为1，频率级别1指示的工作频率为最高频率的2/256。
本申请不对用于指示频率级别的CMD子字段的比特值进行限定。
在一些实施例中，第一裸片通过第一边带控制命令向第二裸片发送频率切换请求时，可理解为第一裸片中的SoC域通过第一裸片的边带控制信道向第二裸片的边带控制信道发送频率切换请求。
示例性的，第一边带控制命令可通过裸片间的边带信号接口进行交互。例如对于单个裸片来说，边带信号接口包括用于传输发送侧的时钟频率的SBC_TXC、用于传输发送侧的串行数据的SBC_TXD、用于传输接收侧的时钟频率的SBC_RXC以及用于传输接收侧的串行数据的SBC_RXD。
总之，该边带信号接口用于两个裸片间用于控制信号和状态的交互。控制信号例如为本申请中的第一边带控制命令。在Chiplet系统中，该边带信号接口可采用串行传输方式，每个裸片的边带信号包括发送方向的边带信号和接收方向的边带信号，每个边带信号可使用1个时钟信号和1个数据信号进行对接。
图8示出了一种裸片间的边带信号接口互联的示意图。其中每个边带信号接口的说明可参见表2。
表2边带信号接口
Figure PCTCN2022114623-appb-000002
表2中的SBC_TXC表示边带控制信号在发送方向的时钟信号；SBC_TXD表示边带控制信号在发送方向的数据(控制命令)；SBC_RXC表示边带控制信号在接收方向的时钟信号；SBC_RXD表示边带控制信号在接收方向的数据(控制命令)。
在表2示出的边带信号接口的示例中，第一裸片可通过SBC_TXD向第二裸片的SBC_RXD发送第一边带控制信号，第一裸片发送第一边带控制信号是在SBC_TXC指示的时钟频率下发送的，第二裸片是在SBC_RXC指示的时钟频率下接收的。
其中，边带信号的时钟频率SBC_TXC和SBC_RXC，与边带控制信号(数据)之间可为同步时序关系，时钟上升沿和数据跳变沿对齐。
如图9示出了一种边带信号接口以报文的方式进行传输时的时序示意图。从图9可看出，每个时钟周期可采用单数据率(Single Data Rate，SDR)传输1bit数据，每次连续传输16bit数据(D0～D15)(16个时钟周期(cycle))组成一个报文(packet)，两个报文(例如图9中的报文0和报文1)之间至少间隔8个时钟周期。在两个报文之间的间隙，SBC_TXC可维持在低电平，数据I/O(SBC_TXD)可处于低功耗状态。
本申请中的第一边带控制命令可通过这16个时钟周期，占用16bit向第二裸片进行发送。
示例性的，本申请的边带信号的报文格式，例如第一边带控制信号的格式为16bit 时，格式可参考图10。该格式下的每个域的功能可参见表3的说明。
表3
Figure PCTCN2022114623-appb-000003
应用图10和表3的示例，本申请的第一边带控制命令在占用16bit的报文格式进行传输时，type[2:0]这个域的比特值可为100。
示例性的，上述数据链路层的频率切换命令的操作码(opcode)，即type＝100时的定义可参见表4，实现方式与表1中的CMD字段类似。
表4
Figure PCTCN2022114623-appb-000004
在一些实施例中，表3中的数据链路层的其他控制信息的opcode，即type＝111时的定义可参见表5。
表5
opcode[7:0]取值 功能说明
11111111 SBC_SYNC_IND：数据同步指示。
其他 保留
上述SBC_SYNC_IND，例如可用于第一裸片向第二裸片通知第一裸片进行频率切换完成，第二裸片可同步开始进行频率切换。
703、第二裸片在接收到频率切换请求时，记录指示切换后的频率级别的信息。
在一些实施例中，对应步骤702，如果第二裸片接收到的是第一LPW flit，第二裸片中的接收电路停止从下游链路接收业务数据，并记录指示切换后的频率级别的信息。当第二裸片停止接收业务数据时，如果第二裸片完成了频率切换，第二裸片可在新的工作频率下接收该业务类型下的业务数据。
对应步骤702，如果第二裸片接收到的是第一边带控制命令，第二裸片可正常接收业务数据，并记录指示切换后的频率级别的信息。
704、第二裸片向第一裸片发送频率切换响应。
示例性的，第二裸片通过第二LPW flit或第二边带控制命令向第一裸片发送频率 切换响应。
相应地，第一裸片通过第二LPW flit或第二边带控制命令接收第二裸片发送的频率切换响应。
此时，第一裸片可正在等待接收频率切换响应。
示例性的，第二LPW flit的格式与表1示出的第一LPW flit的格式类似，不同的是，参考表1，SUB_TYPE的比特值为4’b1111，指示第二LPW flit为切换频率的响应命令。
第二边带控制命令的格式与表3中示出的边带信号的格式类似，其中，type[2:0]这个域的比特值可为011。
在一些实施例中，第二裸片在发送第二LPW flit时，可停止向第一裸片发送业务数据。当第二裸片完成第二LPW flit的发送后，可继续正常向第一裸片发送业务数据。
第二裸片在发送第二边带控制命令时，可正常向第一裸片发送业务数据，即不影响第二裸片对正常的业务数据的发送。
在一些实施例中，当第一裸片发出频率切换请求时，可开启定时器，如果第一裸片在定时时间内未接收到频率切换响应，第一裸片通过数据链路(下游链路)可再次发送频率切换请求，或者，第一裸片通过数据链路持续向第二裸片发送空的流控制单元(NULL flit)，直至接收到第二裸片发送的频率切换响应。
其中，定时时间大于互联接口的双向传输时延，在具体实施过程中可配置。
当第一裸片在定时时间内持续发送频率切换请求或NULL flit，可维持第一裸片和第二裸片间业务不间断，第一裸片和第二裸片可将已经接收到的业务数据缓存下来。
在一些实施例中，当第二裸片接收到第一LPW flit时，第二裸片可将待发送的第二LPW flit的优先级调整为最高优先级，以优先向第一裸片发送第二LPW flit。
705、第一裸片确定与第二裸片完成频率切换协商后，向应用层响应频率切换协商完成。
上述步骤701～704可理解为是在第一裸片和第二裸片的数据链路层完成频率切换协商的。
当第一裸片接收到频率切换响应时，确定与第二裸片完成频率协商，可向第一裸片的应用层响应频率切换协商完成。这里的响应可理解为是对步骤701中的频率模式配置命令的响应。
706、第一裸片的应用层停止向第一裸片发送业务数据，并切换第一裸片的SoC域的工作时钟频率。
相应地的，第一裸片的数据链路层停止从应用层接收业务数据。示例性的，第一裸片可将已经接收到的但是还未发送给第二裸片的业务数据进行缓存。当完成频率切换时，第一裸片的SoC域再继续向第二裸片发送业务数据(业务报文)。
这里切换的第一裸片的SoC域的工作时钟频率包括第一裸片中的SoC域的发送时钟频率。
707、第一裸片停止向第二裸片发送随路时钟，并根据频率级别调整第一裸片的发送电路的工作频率。
其中，第一裸片中的发送电路的时钟可与第二裸片中的接收电路的时钟通过时钟 线连接。第二裸片中的接收电路的时钟为第一裸片中的发送电路备的时钟的随路时钟。当第一裸片中的发送电路的时钟频率变化时，第二裸片中的接收电路的随路时钟也会跟随变化。
第一裸片根据频率级别调整第一裸片的发送电路的工作频率可理解为，第一裸片根据第一裸片的互联接口电路中预先存储的训练参数，即频率级别和电路配置参数的对应关系，确定新的频率级别下的电路配置参数，以根据电路配置参数进行第一裸片的电路参数配置，使得配置后的第一裸片的电路参数适配新的频率级别。
其中，第一裸片的训练参数中的电路配置参数可理解为第一裸片的互联接口电路中的发送电路的电路配置参数。
在一些实施例中，训练参数可以是在裸片出厂是预先存储的。
708、第一裸片向第二裸片发送频率切换指示。
在一些实施例中，第一裸片可通过边带信号命令(SBC_SYNC_IND)向第二裸片发送频率切换指示，频率切换指示用于指示第二裸片进行频率切换。
该边带信号命令的格式可参见表3和表5中说明。其中，边带信号命令中的type[2:0]这个域的值可为“111”，opcode[7:0]这个域的值为“11111111”。
709、第二裸片在接收到频率切换指示时，第二裸片根据频率级别调整第二裸片的接收电路的工作频率。
第二裸片根据指示切换后的频率级别的信息确定电路配置参数，并根据电路配置参数对第二裸片的互联接口电路中的接收电路进行电路参数配置。
类似的，第二裸片根据频率级别调整第二裸片的发送电路的工作频率可理解为，第二裸片根据第二裸片的互联接口电路中预先存储的训练参数，即频率级别和电路配置参数的对应关系，确定新的频率级别下的电路配置参数，以根据电路配置参数进行第二裸片的接收电路的电路参数配置，使得配置后的第二裸片的接收电路的电路参数适配新的频率级别。
在一些实施例中，第一裸片的训练参数和第二裸片的训练参数可能相同，也可能不同。第一裸片的训练参数和第二裸片的训练参数不同时，可理解为第一裸片的训练参数和第二裸片的训练参数中的多种频率级别相同，同一频率级别下的电路配置参数不同。
在一些实施例中，第一裸片的训练参数和第二裸片的训练参数相同时，也可以是第一裸片和第二裸片在上电初始化时，第一裸片将存储的训练参数发送给第二裸片。
在一些实施例中，第一裸片进行电路参数配置可以是在第一裸片向第二裸片发送频率切换请求前完成配置的，或者在第一裸片向第二裸片发送频率切换请求过程中完成配置的，或者是第一裸片在接收到频率切换响应后完成配置的，或者是在应用层切换SoC域的时钟频率后完成配置的。即第一裸片和第二裸片完成电路参数配置的时间可能不是同步的。
710、第一裸片等待固定延时后，启动第一裸片的随路时钟。
其中，该固定延时需覆盖第二裸片切换频率后的稳定时间以及第一裸片切换频率的稳定时间。
711、第一裸片在频率级别下，向第二裸片发送数据。
相应地，第二裸片在频率级别下，接收第一裸片发送的数据。
在一些实施例中，当第一裸片接收到第二裸片的完成电路参数配置的指示，且当第一裸片也完成电路参数配置时，第一裸片可在切换后的频率级别下，向第二裸片发送业务数据。
由此，在本申请的调频方法中，在SoC域与互联接口在同一个时钟域的情况下，可将裸片的互联接口的训练参数预存在裸片的电路中，通过高速数据通道或者边带控制通道交互切换后的频率级别的指示信息，两个裸片均可根据频率级别调用存储的训练参数完成频率级别的快速切换。
另外，在本申请中，考虑到频率切换过程中需要停止从应用层接收业务数据，并且保持业务流不间断，当实现频率级别的快速切换时，有利于减少业务数据的缓存。
当频率切换过程中停止发送和接收业务数据时，在实现频率级别的快速切换时，可减小切换处理延迟，相当于减少对业务数据的反压时间。
而且，当第一裸片的SoC域与第一裸片的发送电路和第二裸片的接收电路在同一个时钟域中时，第一裸片的数字链路层的数字逻辑能够根据SoC域的频率变化进行动态电压调整，实现动态电压频率调整(Dynamic Voltage and Frequency Scaling，DVFS)，能够进降低第一裸片的功耗。类似的，也可以降低第二裸片的功耗。
可以理解的是，上述裸片为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
本申请实施例可以根据上述方法示例对上述裸片进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图11示出了上述实施例中涉及的裸片110的一种可能的组成示意图，如图11所示，该裸片110可以包括：发送单元1101、调整单元1102和接收单元1103。
发送单元1101可用于实现上述裸片中的互联接口的发送电路的功能，接收单元1103可用于实现上述裸片中的互联接口中的接收电路发送功能。调整单元1102可用于实现上述裸片中切换SoC域工作频率、发送电路的工作频率和接收电路的工作频率的功能。
其中，发送单元1101可以用于支持裸片110执行上述步骤501、702、704、705、708、711等，和/或用于本文所描述的技术的其他过程。
调整单元1102可以用于支持裸片110执行上述步骤502、703、706、707、709、710等，和/或用于本文所描述的技术的其他过程。
接收单元1103可以用于支持裸片110执行上述步骤701等，和/或用于本文所描 述的技术的其他过程。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本实施例提供的裸片110，用于执行上述频率调整方法，因此可以达到与上述实现方法相同的效果。
在采用集成的单元的情况下，如图12所示，本申请实施例公开了一种裸片120，该裸片120可以为上述实施例中的芯片系统，例如chiplet系统的小芯片/芯粒。裸片120可以包括处理模块、存储模块和通信模块。其中，处理模块可以用于对裸片120的动作进行控制管理，例如，可以用于支持裸片120执行上述调整单元1102的过程。存储模块可以用于支持裸片120存储程序代码和数据等。例如存储模块存储有本申请中的训练数据，包括频率级别对应的电路配置参数。通信模块，可以用于支持裸片120与其他裸片间的通信。该通信模块可以包括本申请中的互联接口。
当然，上述裸片120中的单元模块包括但不限于上述处理模块、存储模块和通信模块。例如，裸片120还可以包括电源模块等。电源模块用于对裸片120供电。
其中，处理模块可以是处理器或控制器。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理(digital signal processing，DSP)和微处理器的组合等等。存储模块可以是存储器。通信模块具体可以为芯片接口等与其他外部设备交互的设备。
例如，处理模块为处理器1301，存储模块可以为存储器1302，通信模块可以称为通信接口1303，例如本申请中的互联接口。本申请实施例所提供的裸片120可以为图13所示的芯片130。其中，上述处理器、存储器、通信接口等可以连接在一起，例如通过总线连接。
本申请实施例还提供一种通信装置，包括一个或多个处理器以及一个或多个存储器。该一个或多个存储器与一个或多个处理器耦合，一个或多个存储器用于存储计算机程序代码，计算机程序代码包括计算机指令，当一个或多个处理器执行计算机指令时，使得通信装置执行上述相关方法步骤实现上述实施例中的调频方法。
本申请实施例还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序代码，当处理器执行该计算机程序代码时，通信装置执行上述实施例中调频方法。
本申请的实施例还提供了一种计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行上述相关步骤，以实现上述实施例中通信装置执行的调频方法。
其中，本实施例提供的通信装置，例如裸片、计算机存储介质、计算机程序产品或芯片均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
通过以上实施方式的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完 成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (36)

  1. 一种调频方法，其特征在于，所述方法应用于芯片系统，所述芯片系统包括第一裸片和第二裸片，所述方法包括：
    所述第一裸片向所述第二裸片发送频率切换请求，所述频率切换请求包括指示切换后的频率级别的信息；
    所述第二裸片根据所述频率级别调整所述第二裸片的接收电路的工作频率。
  2. 根据权利要求1所述的方法，其特征在于，所述第一裸片的发送电路和所述第二裸片的接收电路在同一个时钟域中。
  3. 根据权利要求1或2所述的方法，其特征在于，在所述第一裸片向所述第二裸片发送频率切换请求之前，所述方法还包括：
    所述第一裸片接收应用层发送的频率模式配置命令，所述频率模式配置命令包括第一指示信息，所述第一指示信息用于指示所述切换后的频率级别；
    所述第一裸片根据所述频率模式配置命令生成所述频率切换请求。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，在所述第二裸片调整所述第二裸片的接收电路的工作频率之前，所述方法还包括：
    所述第一裸片停止从应用层接收业务数据。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述第一裸片向所述第二裸片发送频率切换请求包括：
    所述第一裸片通过第一低功耗控制字LPW流控制单元或第一边带控制命令向所述第二裸片发送所述频率切换请求；
    所述方法还包括：
    所述第一裸片通过第二LPW流控制单元或第二边带控制命令接收所述第二裸片发送的频率切换响应。
  6. 根据权利要求5所述的方法，其特征在于，所述第一LPW流控制单元包括流控制单元头字段、流控制单元内容字段和流控制单元尾字段；
    其中，所述流控制单元内容字段包括类型子字段和命令子字段，所述类型子字段用于指示所述第一LPW流控制单元为频率切换命令，所述命令子字段用于指示所述频率级别。
  7. 根据权利要求5所述的方法，其特征在于，所述第一边带控制命令包括指示消息类型的字段、指示消息编码的字段、指示路径标识的字段和指示校验位的字段；
    其中，所述指示消息类型的字段用于指示所述第一边带控制命令为频率切换命令。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，在所述第二裸片调整所述第二裸片的接收电路的工作频率之前，所述方法还包括：
    所述第一裸片停止向所述第二裸片发送随路时钟，并根据所述频率级别调整所述第一裸片的发送电路的工作频率。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，在所述第二裸片调整所述第二裸片的接收电路的工作频率之前，所述方法还包括：
    所述第一裸片持续向所述第二裸片发送空的流控制单元，直至接收到所述第二裸片发送的频率切换响应。
  10. 根据权利要求1-9任一项所述的方法，其特征在于，在所述第二裸片调整所述第二裸片的接收电路的工作频率之前，所述方法还包括：
    所述第一裸片确定与所述第二裸片完成频率切换协商后，向应用层响应频率切换协商完成。
  11. 根据权利要求1-10任一项所述的方法，其特征在于，在所述第二裸片调整所述第二裸片的接收电路的工作频率之前，所述方法还包括：
    所述第一裸片向所述第二裸片发送频率切换指示，所述频率切换指示用于指示所述第二裸片进行频率切换。
  12. 根据权利要求1-11任一项所述的方法，其特征在于，所述方法还包括：
    所述第一裸片等待固定延时后，启动所述第一裸片的随路时钟。
  13. 根据权利要求1-12任一项所述的方法，其特征在于，所述方法还包括：
    所述第一裸片在所述频率级别下，向所述第二裸片发送数据；
    所述第二裸片在所述频率级别下，接收所述第一裸片发送的数据。
  14. 一种调频方法，其特征在于，所述方法应用于芯片系统，所述芯片系统包括第一裸片和第二裸片，所述方法包括：
    所述第二裸片接收所述第一裸片发送的频率切换请求，所述频率切换请求包括指示切换后的频率级别的信息；
    所述第二裸片根据所述频率级别调整所述第二裸片的接收电路的工作频率。
  15. 根据权利要求14所述的方法，其特征在于，所述第一裸片的发送电路和所述第二裸片的接收电路在同一个时钟域中。
  16. 根据权利要求14或15所述的方法，其特征在于，所述第二裸片接收所述第一裸片发送的频率切换请求包括：
    所述第二裸片通过第一低功耗控制字LPW流控制单元或第一边带控制命令接收所述第一裸片发送所述频率切换请求；
    所述方法还包括：
    所述第二裸片通过第二LPW流控制单元或第二边带控制命令向所述第一裸片发送频率切换响应。
  17. 根据权利要求15-16任一项所述的方法，其特征在于，所述方法还包括：
    所述第二裸片接收到所述第一裸片发送的频率切换请求时，记录所述指示切换后的频率级别的信息。
  18. 根据权利要求15-17任一项所述的方法，其特征在于，在所述第二裸片根据所述频率级别调整所述第二裸片的接收电路的工作频率之前，所述方法还包括：
    所述第二裸片接收所述第一裸片发送的频率切换指示，所述频率切换指示用于指示所述第二裸片进行频率切换。
  19. 一种调频方法，其特征在于，所述方法应用于芯片系统，所述芯片系统包括第一裸片和第二裸片，所述方法包括：
    所述第一裸片向所述第二裸片发送频率切换请求，所述频率切换请求包括指示切换后的频率级别的信息；
    所述第一裸片根据所述频率级别调整所述第一裸片的发送电路的工作频率。
  20. 根据权利要求19所述的方法，其特征在于，所述第一裸片的发送电路和所述第二裸片的接收电路在同一个时钟域中。
  21. 根据权利要求19或20所述的方法，其特征在于，所述第一裸片向所述第二裸片发送频率切换请求包括：
    所述第一裸片通过第一低功耗控制字LPW流控制单元或第一边带控制命令向所述第二裸片发送所述频率切换请求；
    所述方法还包括：
    所述第一裸片通过第二LPW流控制单元或第二边带控制命令接收所述第二裸片发送的频率切换响应。
  22. 一种芯片系统，其特征在于，所述芯片系统包括第一裸片和第二裸片，其中：
    所述第一裸片，用于向所述第二裸片发送频率切换请求，所述频率切换请求包括指示切换后的频率级别的信息；
    所述第二裸片，用于根据所述频率级别调整所述第二裸片的接收电路的工作频率。
  23. 根据权利要求22所述的芯片系统，其特征在于，所述第一裸片的发送电路和所述第二裸片的接收电路在同一个时钟域中。
  24. 根据权利要求22或23所述的芯片系统，其特征在于，所述第一裸片用于：
    接收应用层发送的频率模式配置命令，所述频率模式配置命令包括第一指示信息，所述第一指示信息用于指示所述切换后的频率级别；
    根据所述频率模式配置命令生成所述频率切换请求。
  25. 根据权利要求22-24任一项所述的芯片系统，其特征在于，所述第一裸片用于：
    通过第一低功耗控制字LPW流控制单元或第一边带控制命令向所述第二裸片发送所述频率切换请求；
    通过第二LPW流控制单元或第二边带控制命令接收所述第二裸片发送的频率切换响应。
  26. 一种第二裸片，其特征在于，芯片系统包括第一裸片和所述第二裸片，所述第二裸片包括：
    接收器，用于接收所述第一裸片发送的频率切换请求，所述频率切换请求包括指示切换后的频率级别的信息；
    处理器，用于根据所述频率级别调整所述第二裸片的接收电路的工作频率。
  27. 根据权利要求26所述的第二裸片，其特征在于，所述第一裸片的发送电路和所述第二裸片的接收电路在同一个时钟域中。
  28. 根据权利要求26或27所述的第二裸片，其特征在于，所述接收器，用于：
    通过第一低功耗控制字LPW流控制单元或第一边带控制命令接收所述第一裸片发送所述频率切换请求；
    所述接收器还用于：
    通过第二LPW流控制单元或第二边带控制命令向所述第一裸片发送频率切换响应。
  29. 根据权利要求26-28任一项所述的第二裸片，其特征在于，所述处理器，还用于：
    在所述接收器用于接收到所述第一裸片发送的频率切换请求时，记录所述指示切换后的频率级别的信息。
  30. 根据权利要求26-29任一项所述的第二裸片，其特征在于，所述接收器，还用于：接收所述第一裸片发送的频率切换指示，所述频率切换指示用于指示所述第二裸片进行频率切换。
  31. 一种第一裸片，其特征在于，芯片系统包括所述第一裸片和第二裸片，所述第一裸片包括：
    发射器，用于向所述第二裸片发送频率切换请求，所述频率切换请求包括指示切换后的频率级别的信息；
    处理器，用于根据所述频率级别调整所述第一裸片的发送电路的工作频率。
  32. 根据权利要求31所述的第一裸片，其特征在于，所述第一裸片的发送电路和所述第二裸片的接收电路在同一个时钟域中。
  33. 根据权利要求31或32所述的第一裸片，其特征在于，所述发射器，用于：
    通过第一低功耗控制字LPW流控制单元或第一边带控制命令向所述第二裸片发送所述频率切换请求；
    还包括接收器，用于通过第二LPW流控制单元或第二边带控制命令接收所述第二裸片发送的频率切换响应。
  34. 一种计算机可读存储介质，其特征在于，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述权利要求1-13中的任一项所述的方法。
  35. 一种计算机可读存储介质，其特征在于，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述权利要求14-18中的任一项所述的方法。
  36. 一种计算机可读存储介质，其特征在于，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述权利要求19-21中的任一项所述的方法。
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CN103227638A (zh) * 2012-01-30 2013-07-31 意法半导体(格勒诺布尔2)公司 方法和布置
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CN111737186A (zh) * 2016-10-10 2020-10-02 英特尔公司 多管芯硬件处理器和方法
US20220222198A1 (en) * 2021-12-22 2022-07-14 Narasimha Lanka Sideband interface for die-to-die interconnects
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CN103227638A (zh) * 2012-01-30 2013-07-31 意法半导体(格勒诺布尔2)公司 方法和布置
US20150126128A1 (en) * 2013-11-07 2015-05-07 Silicon Laboratories Inc. Die-To-Die Communication Links For Receiver Integrated Circuit Dies And Related Methods
CN107544938A (zh) * 2016-06-28 2018-01-05 台湾积体电路制造股份有限公司 用于裸片对裸片通信的系统与方法
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