WO2024037347A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024037347A1
WO2024037347A1 PCT/CN2023/110898 CN2023110898W WO2024037347A1 WO 2024037347 A1 WO2024037347 A1 WO 2024037347A1 CN 2023110898 W CN2023110898 W CN 2023110898W WO 2024037347 A1 WO2024037347 A1 WO 2024037347A1
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Prior art keywords
layer
region
semiconductor
opening
insulating layer
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English (en)
French (fr)
Inventor
林超
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections

Definitions

  • the present disclosure relates to the field of memory, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then passes through the bit line. Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • transistors in the existing 3D DRAM manufacturing process usually adopt a multi-layer stacked lateral transistor structure.
  • the channel areas of the lateral transistors are floating, charges are easily accumulated in the channel area, causing a floating body effect.
  • the floating body effect will bring many adverse consequences, seriously affecting the performance of the device, and even causing the device to fail.
  • Some embodiments of the present disclosure provide a method for forming a semiconductor structure, including:
  • Line-shaped semiconductor patterns extending along the first direction and arranged in arrays in the second direction and the vertical direction are formed on the semiconductor substrate, and a first insulating layer is formed between the line-shaped semiconductor patterns; the lines
  • the semiconductor pattern includes a channel region and a drain region connected to the channel region; a portion of the first insulating layer on one side of the drain region is etched to form a first opening, and the first opening is exposed Expose the first sidewalls of a plurality of drain regions arranged in the vertical direction, and the bottom of the first opening exposes a portion of the surface of the semiconductor substrate;
  • the drain region exposed by the first opening is ion doped to form a ground doped region in the drain region, the ground doped region is connected to the channel region, and is connected to the channel region. Regions have the same doping type;
  • Conductive material is filled in the first opening to form a grounded conductive plug, and the grounded conductive plug is electrically connected to the ground doped region and the semiconductor substrate.
  • Some embodiments of the present disclosure also provide a semiconductor structure, including:
  • each layer of the linear semiconductor pattern layer includes a plurality of parallel linear semiconductor patterns extending along the first direction,
  • the linear semiconductor pattern includes a channel region and a ground doping region connected to the channel region; and the ground doping region and the channel region have the same doping type;
  • a grounded conductive plug is located between adjacent linear semiconductor patterns, the grounded conductive plug penetrates the stacked structure in a vertical direction and is connected to the semiconductor substrate, and the grounded conductive plug is in a second direction One side is connected to the ground doped region.
  • the method of forming a semiconductor structure in some of the foregoing embodiments of the present disclosure enables the channel region to be grounded by forming a ground doping region and a ground conductive plug, thereby passing the charges accumulated in the channel region through the ground doping region and the ground conductive plug.
  • the grounded conductive plug is released to prevent the floating body effect and improve the device's reliability. performance, and the ground doping region is formed in the drain region, and the ground conductive plug is formed in the first trench, which does not occupy additional area and can ensure the integration of the formed 3D DRAM device.
  • 1-52 is a structural schematic diagram of the formation process of a semiconductor structure in some embodiments of the present disclosure.
  • Some embodiments of the present disclosure first provide a method for forming a semiconductor structure. The forming method will be described in detail below with reference to the accompanying drawings.
  • Figure 2 is a schematic cross-sectional structural view of Figure 1 along the direction of cutting line AA1
  • Figure 3 is a schematic cross-sectional structural view of Figure 1 along the direction of cutting line BB1
  • Figure 4 is a cross-sectional view of Figure 1 along the direction of cutting line CC1.
  • Structural diagram it should be noted that, for better illustration, the topmost sacrificial layer 202 is not shown in FIG. 1 , but a semiconductor layer 233 at the bottom of the topmost sacrificial layer 202 is directly shown).
  • the method of forming a semiconductor structure includes: providing a semiconductor substrate 200; forming a stack structure 201 on the semiconductor substrate 200 in which the sacrificial layer 202 and the semiconductor layer 233 are alternately stacked in a vertical direction, and the vertical direction is perpendicular to the upper surface of the semiconductor substrate. direction.
  • the material of the semiconductor substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it may also be silicon on insulator (SOI) or germanium on insulator (GOI). ); or it can also be other materials, such as gallium arsenide and other Group III-V compounds.
  • the material of the semiconductor substrate 200 is single crystal silicon (Si).
  • the stacked structure 201 includes sacrificial layers 202 and semiconductor layers 233 that are alternately stacked in the vertical direction.
  • the sacrificial layer 202 and the semiconductor layer 233 are alternately stacked in the vertical direction. This means that after a sacrificial layer 202 is formed, the sacrificial layer 202 is A semiconductor layer 233 is formed on the surface of 202, and then the steps of forming the sacrificial layer 202 and the semiconductor layer 233 located on the sacrificial layer 202 are sequentially performed.
  • the number of layers of the sacrificial layer 202 and the semiconductor layer 233 can be determined according to actual needs.
  • the sacrificial layer 202 has four layers, and the semiconductor layer 233 has four layers as an example.
  • the bottom layer and the top layer of the stacked structure 201 are each one sacrificial layer 202 .
  • the number of layers of the sacrificial layer 202 and the semiconductor layer 233 may be other numbers.
  • the semiconductor layer 233 is subsequently used to form linear semiconductor patterns.
  • the sacrificial layer 202 serves as a sacrificial material and will be removed in subsequent processes, or part of the sacrificial layer 202 can directly serve as a part of the insulating layer.
  • the material of the sacrificial layer 202 is different from the material of the semiconductor layer 233, so that when the sacrificial layer 202 is subsequently removed, the sacrificial layer 202 has a high etching selectivity ratio (etching selectivity ratio) relative to the semiconductor layer 233 (or linear semiconductor pattern). greater than 2:1), so that when the sacrificial layer 202 is removed, the semiconductor layer 233 (or linear semiconductor pattern) will not be etched or the etched amount will be small.
  • the material of the semiconductor layer 233 is silicon or silicon germanium
  • the material of the sacrificial layer 202 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, amorphous silicon, amorphous carbon, polycrystalline silicon, silicon germanium one of them.
  • the material of the semiconductor layer 233 is silicon
  • the material of the sacrificial layer 202 is silicon germanium.
  • the material of the sacrificial layer 202 is silicon oxide, silicon hydroxide, silicon nitride , etc.
  • the material of the semiconductor layer 233 is an oxide semiconductor , for example, InxGayZnzO , InxGaySiz O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga y O or a combination of the above materials.
  • the semiconductor layer 233 is a doped semiconductor layer 233, that is, the semiconductor layer 233 is pre-doped with impurity ions.
  • the impurity ions may be N-type impurity ions or P-type impurity ions.
  • the P-type impurity ions are one or more of boron, gallium, and indium
  • the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.
  • the impurity ions doped in the semiconductor layer 233 are P-type impurity ions.
  • the semiconductor layer 233 may also be an undoped semiconductor layer 233.
  • the sacrificial layer 202 and the semiconductor layer 233 are respectively formed through a deposition process.
  • Deposition processes include epitaxial processes.
  • Figure 6 is a schematic cross-sectional structural view of Figure 5 along the direction of cutting line AA1
  • Figure 7 is a schematic cross-sectional structural view of Figure 5 along the direction of cutting line BB1
  • Figure 8 is a cross-sectional view of Figure 5 along the direction of cutting line CC1.
  • the stack structure 201 is etched to form a plurality of first trenches 204 penetrating the stack structure in a first direction and a vertical direction, and the remaining semiconductor layer extending along the first direction between adjacent first trenches 204 It is a linear semiconductor pattern 203.
  • the linear semiconductor patterns 203 extend along the first direction and are arranged in an array in the second direction and the vertical direction.
  • Each linear semiconductor pattern 203 includes a channel region 21 and a channel region 21 respectively located in the channel region 21.
  • the first direction and the second direction of the source region 23 and the drain region 22 (refer to FIGS. 5 and 6 ), which are both ends and are connected to the channel region 21 , are perpendicular and parallel to the upper surface of the semiconductor substrate 200 .
  • the plurality of first grooves 204 penetrate the stacked structure 201 in the vertical direction.
  • the plurality of first grooves 204 are parallel to each other, and the formed first grooves 204 extend along the first direction.
  • the direction of the cutting line AA1 is parallel to the first direction.
  • the semiconductor substrate 200 when forming the first trench 204, is over-etched so that the bottom of the first trench 204 is located in the semiconductor substrate 200 (refer to FIG. 8).
  • a patterned first mask layer (not shown in the figure) is formed on the surface of the stacked structure 201, and the patterned first mask layer has a pattern along the first direction.
  • an anisotropic dry etching process such as an anisotropic plasma etching process, may be used to etch the stacked structure 201 .
  • each layer 233 After being etched, the semiconductor layer 233 of each layer 233 (refer to FIGS. 1-4 ) will form a plurality of linear semiconductor patterns 203 extending along the first direction and parallel to each other.
  • the multiple linear semiconductor patterns of each layer 203 constitutes a linear semiconductor pattern layer.
  • Each linear semiconductor pattern 203 includes a channel region 21 and a source region 23 and a drain region 22 respectively located at both ends of the channel region 21 and connected to the channel region 21 (refer to FIGS. 5 and 6 ).
  • the channel region 21 is subsequently used as the channel region of the lateral transistor
  • the source region 23 is subsequently used to form the source region of the lateral transistor
  • a part of the drain region 22 is used to form the drain region of the lateral transistor
  • the other part of the drain region 22 is used to form the
  • the channel region 21 is connected to the ground doped region.
  • Figure 10 is a schematic cross-sectional structural view of Figure 9 along the direction of cutting line AA1
  • Figure 11 is a schematic cross-sectional structural view of Figure 9 along the direction of cutting line BB1
  • Figure 12 is a cross-sectional view of Figure 9 along the direction of cutting line CC1.
  • a first insulating layer 206 filling the first trench is formed in the first trench 204.
  • the first insulating layer 206 serves for electrical isolation between subsequently formed devices.
  • the material of the first insulating layer 206 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide). Silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), one or more of low dielectric constant (K less than 2.5) materials.
  • the material of the first insulating layer 206 is silicon oxide
  • the process of forming the first insulating layer 206 is a chemical vapor deposition process.
  • the sacrificial layer 202 is made of non-insulating material (for example, when the sacrificial layer material is silicon germanium), before forming the first insulating layer 206 , the space between the adjacent drain regions 22 is removed along the first trench 204 .
  • the sacrificial layer forms the first cavity.
  • a wet etching process may be used.
  • Areas other than the drain area can be covered by a mask layer (such as a photoresist mask layer or other suitable mask layer); forming a first insulating layer 206 that fills the first cavity and the first trench. .
  • the sacrificial layer 202 when the sacrificial layer 202 is made of insulating material (such as silicon oxide or silicon nitride), before forming the first insulating layer 206 , the sacrificial layer between adjacent drain regions 22 may not be removed, and the sacrificial layer may be directly formed. The sacrificial layer between adjacent drain regions 22 is used as a part of the first insulating layer. Before forming the first insulating layer 206 , the sacrificial layer between adjacent drain regions 22 may also be removed along the first trench 204 to form a first cavity; and then a first cavity filled with the first cavity and the first trench may be formed. First insulating layer 206.
  • insulating material such as silicon oxide or silicon nitride
  • FIGS. 13-16 where FIG. 14 is a schematic cross-sectional structural view of FIG. 13 along the cutting line AA1 direction, FIG. 15 is a schematic cross-sectional structural view of FIG. 13 along the cutting line BB1 direction, and FIG. 16 is a schematic cross-sectional structural view of FIG. 13 along the cutting line BB1 direction.
  • Part of the first insulating layer 206 and part of the sacrificial layer 202 are removed to form multiple support structures 207 extending in the vertical direction and the second direction.
  • the support structures are filled between the linear semiconductor patterns 203.
  • the material of the support structure 207 is different from the materials of the first insulating layer 206 and the sacrificial layer 202 .
  • the support structure 207 is used to support the linear semiconductor pattern 203 in subsequent processes to prevent the linear semiconductor pattern 203 from being deformed due to suspension.
  • the material of the support structure 207 is different from the material of the first insulating layer 206 and the sacrificial layer 202, so that when the first insulating layer 206 and the sacrificial layer 202 are subsequently etched, the etching rate of the support structure 207 is very low, ensuring support. Structure 207 complete.
  • the material of the support structure 207 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, or silicon carbonitride. In this embodiment, the material of the support structure 207 is silicon nitride.
  • the sacrificial layer 202 and the first insulating layer 206 need to be etched to form at least two openings extending in the second direction in the sacrificial layer 202 and the first insulating layer 206.
  • a support structure 207 filling the opening is formed in the opening.
  • the second direction is located in a direction with a certain angle between the first direction.
  • the second direction is perpendicular to the first direction, or the angle between the second direction and the first direction is 90°.
  • FIGS. 17-20 wherein FIG. 18 is a schematic cross-sectional structural view of FIG. 17 along the cutting line AA1 direction, FIG. 19 is a schematic cross-sectional structural view of FIG. 17 along the cutting line BB1 direction, and FIG. 20 is a schematic cross-sectional structural view of FIG. 17 along the cutting line BB1 direction.
  • the first insulating layer 206 in the middle part of the first trench 204 between the adjacent drain regions 22 is etched to remove the first insulating layer 206 in the first trench 204.
  • a second opening 208 extending along the first direction is formed in 206 , and the bottom of the second opening 208 exposes a portion of the surface of the semiconductor substrate 200 .
  • the second opening 208 is subsequently used to form an isolation layer.
  • the isolation layer is used for electrical isolation and bit lines and ground conductive plugs are respectively formed on both sides of the isolation layer.
  • An anisotropic dry etching process is used to form the second opening 208.
  • a patterned mask layer is formed on the surface of the stacked structure. The patterned mask layer is used as a mask to etch the second opening 208. Etch the first insulating layer 206 in the middle portion of the first trench 204 between adjacent drain regions 22 to form a second opening extending in the first direction in the first insulating layer 206 in the first trench 204 208.
  • the size of the second opening 208 is 10%-20% of the size of the first trench 204, while ensuring the electrical isolation performance of the isolation layer formed in the subsequent second opening 208, while ensuring the electrical isolation performance of the isolation layer on both sides of the isolation layer.
  • the sides expose enough space to form bit lines and ground conductive plugs respectively.
  • the size of the second opening 208 is The vertical distance between the two side walls of the second opening 208 along the second direction, and the size of the first trench 204 is the vertical distance between the two side walls of the first trench 204 along the second direction.
  • Figures 21-24 wherein Figure 22 is a schematic cross-sectional structural view of Figure 21 along the direction of cutting line AA1, Figure 23 is a schematic cross-sectional structural view of Figure 21 along the direction of cutting line BB1, and Figure 24 is a schematic cross-sectional structural view of Figure 21 along the direction of cutting line BB1.
  • the schematic cross-sectional structural diagram in the direction of cutting line CC1 forms an isolation layer 209 that fills the second opening.
  • the material of the isolation layer 209 is different from the material of the first insulating layer 206.
  • the material of the isolation layer 209 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, or silicon carbonitride. In this embodiment, the material of the isolation layer 209 is silicon nitride.
  • FIGS. 25-28 wherein FIG. 26 is a schematic cross-sectional structural view of FIG. 25 along the cutting line AA1 direction, FIG. 27 is a schematic cross-sectional structural view of FIG. 25 along the cutting line BB1 direction, and FIG. 28 is a schematic cross-sectional structural view of FIG. 25 along the cutting line BB1 direction.
  • the sacrificial layer and the first insulating layer between adjacent channel regions 21 are removed, and a second cavity is formed at the position where the sacrificial layer is removed.
  • the second cavity is connected to the first trench.
  • the channel region 21 is pre-doped with P-type impurity ions, and the channel region 21 is directly used as the channel region of the lateral transistor.
  • the channel region is doped with impurity ions to form a channel region of the lateral transistor in the channel region 21 .
  • the metal word lines are horizontal word lines (the horizontal word lines are arranged horizontally and parallel to the surface of the semiconductor substrate 200).
  • the channel areas 21 of multiple linear semiconductor patterns in each layer are connected to one metal word line.
  • the metal word lines 210 of adjacent layers are discrete or separated.
  • the metal word lines 210 have a surrounding gate structure, and each metal word line 210 surrounds the surface of a plurality of channel regions 21 arranged along the second direction in a certain layer.
  • the metal word line may have a double-layer gate structure, and the double-layer gates in each metal word line are respectively located on the upper and lower surfaces of multiple channel regions arranged along the second direction in a certain layer.
  • the material of the word line dielectric layer may be silicon oxide or a high-K (K greater than 2.5) dielectric material
  • the material of the metal word line may be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN , TaN, Ta, TaC, TaSiN, one or more of W, WN, Wsi.
  • the formed metal word lines are vertical word lines (the vertical word lines are arranged vertically, perpendicular to the surface of the semiconductor substrate 200 ), and each metal word line surrounds multiple channel regions in the vertical direction. 21 on the surface of the word line dielectric layer, or on the surface of the word line dielectric layer on the surface of multiple channel regions 21 in the vertical direction, and the two adjacent metal word lines are discrete or separated.
  • the remaining first trench and the second cavity are filled with the second insulating layer 211 (refer to FIGS. 26 and 27 ).
  • the word line dielectric layer and the metal word line 210 are formed before the subsequently formed bit lines and ground conductor plugs. In other embodiments, the wordline dielectric layer and metal wordline 210 are formed after the bitline and ground conductor plugs are formed.
  • Figure 39 is a schematic cross-sectional structural view of Figure 29 along the direction of cutting line AA1
  • Figure 31 is a schematic cross-sectional structural view of Figure 29 along the direction of cutting line BB1
  • Figure 32 is a cross-sectional view of Figure 29 along the direction of cutting line CC1.
  • Structural diagram etching and removing part of the first insulating layer 206 on the other side of the isolation layer 209 (the other side is the side of the isolation layer 209 that is not in contact with the subsequently formed bit lines) to form the third opening 212.
  • the side surfaces of the opening 212 expose the second side surfaces of the plurality of drain regions 22 in the vertical direction.
  • Each drain region includes opposite first and second sides along the second direction.
  • the third opening 212 is subsequently used to form a bit line, and the third opening 212 is also used as a window for doping the drain region to form a drain region.
  • Figure 34 is a schematic cross-sectional structural view of Figure 33 along the direction of cutting line AA1
  • Figure 35 is a schematic cross-sectional structural view of Figure 33 along the direction of cutting line BB1
  • Figure 36 is a cross-sectional view of Figure 33 along the direction of cutting line CC1.
  • multiple drain regions 22 in the vertical direction exposed by the third opening 212 are doped to form a drain region 213 in the drain region 22.
  • the drain region 213 is connected to the subsequently formed ground.
  • the doping regions are adjacent, and the doping type of the drain region 213 is opposite to the doping type of the ground doping region and the channel region 21 .
  • an ion implantation process is performed on the drain region 22 exposed by the third opening 212 to form a drain region 213.
  • the drain region 213 is only formed in a part of the drain region 22 (a part close to the third opening 212). , another part of the drain region 22 is subsequently used to form a ground doped region.
  • the impurity ions doped in the drain region 213 may be N-type impurity ions or P-type impurity ions.
  • the P-type impurity ions are one or more of boron, gallium, and indium
  • the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.
  • the impurity ions doped in the semiconductor layer 233 are N-type impurity ions.
  • Figure 38 is a schematic cross-sectional structural view of Figure 37 along the direction of cutting line AA1
  • Figure 39 is a schematic cross-sectional structural view of Figure 37 along the direction of cutting line BB1
  • Figure 40 is a cross-sectional view of Figure 37 along the direction of cutting line CC1.
  • a bit line 214 filling the third opening is formed in the third opening, and the bit line 214 is connected to a plurality of drain regions 213 .
  • Each bit line 214 is connected to a plurality of drain regions 213 exposed in the third opening.
  • the material of the bit line 214 is metal, and the metal can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.
  • the bit line 214 is formed in the first trench and connected to the side surface of the drain region 213 (the side surface of the drain region is a surface parallel to the first direction).
  • the bit line may be formed at an end of the drain region 213 or in the drain region 213 by forming a through hole penetrating the drain region 213 and then filling the through hole with a conductive material.
  • each metal word line when the formed metal word lines are vertical word lines (the vertical word lines are arranged vertically, perpendicular to the surface of the semiconductor substrate 200), each metal word line surrounds multiple channels in the vertical direction.
  • the word line dielectric layer on the surface of the region 21, or the word line dielectric layer on the surface of multiple channel regions 21 in the vertical direction, and the two adjacent metal word lines are discrete or separated, are formed.
  • the bit lines of The drain regions are connected together, and the horizontal bit lines are not connected to the subsequently formed ground doped region.
  • Figure 42 is a schematic cross-sectional structural view of Figure 41 along the direction of cutting line AA1
  • Figure 43 is a schematic cross-sectional structural view of Figure 41 along the direction of cutting line BB1
  • Figure 44 is a cross-sectional view of Figure 41 along the direction of cutting line CC1.
  • Schematic structural diagram etching part of the first insulating layer 206 in the first trench on one side of the drain region 22, forming a first opening 215 in the first insulating layer 206, and exposing the sides of the first opening 215 in the vertical direction. On one side wall of the plurality of drain regions 22, the bottom of the first opening 215 exposes a portion of the surface of the semiconductor substrate.
  • part of the first insulating layer on one side of the isolation layer 209 is removed by etching to form the first opening 215.
  • a grounded conductive plug is subsequently formed in the first opening 215, and the first opening is used as a base for forming the ground doped region. ion implantation window.
  • the first opening 215 and the third opening formed above are respectively located on both sides of the isolation layer 209. Therefore, the ground conductive plug formed by the first opening 215 and the bit line formed in the third opening are also located on both sides of the isolation layer 209.
  • Figure 46 is a cross-sectional structural diagram along the cutting line AA1 of Figure 45.
  • Figure 47 is a schematic cross-sectional structural diagram of Figure 45 along the direction of cutting line BB1.
  • Figure 48 is a schematic cross-sectional structural diagram of Figure 45 along the direction of cutting line CC1.
  • the drain region 22 exposed by the first opening 215 is ion doped to
  • a ground doping region 216 is formed in the drain region 22 .
  • the ground doping region 216 is connected to the channel region 21 and has the same doping type as the channel region 21 .
  • ground doped region 216 is only formed in a part of the drain region 22 (near the first opening 215). part of the region), and the ground doped region 216 is located on one side of the drain region 213.
  • the impurity ions doped in the ground doping region 216 may be N-type impurity ions or P-type impurity ions.
  • the P-type impurity ions are one or more of boron, gallium, and indium
  • the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.
  • the impurity ions doped in the ground doping region 216 are P-type impurity ions.
  • the ground doped region 216 is connected to the channel region 21 and has the same doping type as the channel region 21, so that the ground doped region 216 and the channel region 21 are conductive. Subsequently, in the first After the ground conductive plug is formed in the opening, the ground conductive plug and the ground doped region 216 are connected and conductive. Therefore, the channel region 21 can be grounded by forming the ground doped region 216 and the ground conductive plug, thereby connecting the ground conductive plug to the ground conductive plug. The charges accumulated in the channel region 21 are released through the ground doping region 216 and the ground conductive plug, preventing the floating body effect and improving the performance of the device.
  • the ground doping region 216 is formed in the drain region, and the ground conductive plug The plug is formed in the first trench, does not occupy additional area, and can ensure the integration of the formed DRAM device.
  • Figure 50 is a schematic cross-sectional structural view of Figure 49 along the direction of cutting line AA1
  • Figure 51 is a schematic cross-sectional structural view of Figure 49 along the direction of cutting line BB1
  • Figure 52 is a cross-sectional view of Figure 49 along the direction of cutting line CC1.
  • a schematic structural diagram shows that the first opening is filled with conductive material to form a grounded conductive plug 217 , and the grounded conductive plug 217 is connected to the ground doped region 216 and the semiconductor substrate 200 .
  • the material of the ground conductive plug 217 is metal or doped polysilicon.
  • the metal can be one of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi. species or several species.
  • the ground doped region is formed by forming a ground terminal.
  • the impurity region 216 and the ground conductive plug 217 allow the channel region 21 to be grounded, thereby releasing the charges accumulated in the channel region 21 through the ground doping region 216 and the ground conductive plug 217, preventing the floating body effect from occurring, and improving the performance of the device. performance, and the ground doping region 216 is formed in the drain region 22, and the ground conductive plug 217 is formed in the first trench 204, which does not occupy additional area and can ensure the integration of the formed 3D DRAM device. .
  • the grounded conductive plug 217 and the bit line 214 are both formed in the first trench.
  • the grounded conductive plug 217 and the bit line 214 are isolated by the isolation layer 209.
  • the grounded conductive plug 217 and the bit line 214 It does not occupy additional area and is conducive to improving device integration.
  • ground conductive plug 217 is formed after bit line 214 . In other embodiments, ground conductive plug 217 may be formed before bit line 214 .
  • the method further includes: doping the source region 23 to form a source region (not shown in the figure), the doping type of the source region being the same as the doping type of the drain region; removing The sacrificial layer and the isolation layer between the source regions form a capacitor (not shown in the figure) connected to the source region in the area where the sacrificial layer and the isolation layer are removed.
  • Figure 50 is a schematic cross-sectional structural view along the cutting line AA1 of Figure 49
  • Figure 51 is a schematic cross-sectional structural view along the cutting line BB1 of Figure 49
  • Figure 52 is a schematic cross-sectional structural diagram along the cutting line CC1 in Figure 49, include:
  • Each linear semiconductor pattern layer includes a plurality of parallel linear semiconductor patterns 203 extending along the first direction.
  • the linear semiconductor pattern 203 includes a channel region and a ground doping region 216 connected to the channel region; and the ground doping region 216 and the channel region have the same doping type;
  • the grounded conductive plug 217 is located between adjacent linear semiconductor patterns 203 .
  • the grounded conductive plug 217 penetrates the stacked structure in the vertical direction and connects to the semiconductor substrate 200 .
  • the grounded conductive plug 217 is connected to the grounded conductive plug 217 on one side in the second direction.
  • Ground doped region 216 is connected.
  • the linear semiconductor pattern 203 also includes a drain region 213 connected to the channel region.
  • the drain region 213 is located on one side of the ground doping region 216, and the doping type of the drain region 213 is the same as the ground doping.
  • the doping type of the region 216 and the channel region is opposite;
  • the isolation layer 209 is located on the side of the ground conductive plug 217 away from the side that contacts the ground doped region 216;;
  • the isolation layer 209 is located on the second direction away from the ground conductive
  • the bit line 214 on one side of the plug 217 runs through the stacked structure in a vertical direction, and the bit line 214 is connected to a plurality of drain regions 213 .
  • isolation layer 209 and insulating layer (206) are made of different materials.
  • the size of isolation layer 209 is 10%-20% of the size of first trench 204 .
  • the method further includes: a word line dielectric layer (not shown in the figure) formed on the surface of the channel region; and a metal layer extending along the second direction on the word line dielectric layer of the channel region of each layer.
  • Word lines 210; the area between adjacent metal word lines 210 is filled with an insulating layer.
  • the metal word lines 210 have a surrounding gate structure, and each metal word line 210 surrounds the surface of a plurality of channel regions arranged along the second direction in a certain layer.
  • the metal word line has a double-layer gate structure, and the double-layer gates in each metal word line are respectively located on the upper and lower surfaces of a plurality of channel regions arranged along the second direction in a certain layer.
  • it also includes: a plurality of support structures 207 extending in the second direction located in the plurality of insulating layers and on the surface of the top linear semiconductor pattern 203.
  • the material of the support structures 207 is different from that of the insulating layer.
  • ground conductive plug 217 is metal or doped polysilicon.
  • it also includes: a source region (not shown in the figure) located in the source region 23, the doping type of the source region is the same as the doping type of the drain region; a capacitor connected to the source region (not shown in the figure) not shown).

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  • Semiconductor Memories (AREA)

Abstract

一种半导体结构及其形成方法，其中，半导体结构的形成方法包括：在半导体衬底（200）上形成沿第一方向延伸、且在第二方向和竖直方向阵列排布的线状半导体图形（203），包括沟道区域（21）和与沟道区域（21）连接的漏极区域（22），线状半导体图形（203）之间形成有第一绝缘层（206）；刻蚀漏极区域（22）一侧的部分第一绝缘层（206），以形成第一开口（215）；对第一开口（215）暴露的漏极区域（22）进行离子掺杂，以在漏极区域（22）中形成接地掺杂区（216），接地掺杂区（216）与沟道区域（21）连接；在第一开口（215）中填充导电材料，形成接地导电插塞（217），接地导电插塞（217）与接地掺杂区（216）和半导体衬底（200）电连接。

Description

半导体结构及其形成方法
相关申请引用说明
本公开要求于2022年08月19日递交的中国专利申请号202210997518.1，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及存储器领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
为了提高集成度，现有3D DRAM制作过程中晶体管通常会采用多层堆叠的横向晶体管结构。而多层堆叠的横向晶体管结构中由于横向晶体管的沟道区域都是浮空的，电荷容易在沟道区域积累带来浮体效应，浮体效应会带来很多不良后果，严重影响器件的性能，甚至使器件失效。
发明内容
本公开一些实施例提供了一种半导体结构的形成方法，包括：
提供半导体衬底；
在所述半导体衬底上形成沿第一方向延伸、且在第二方向和竖直方向阵列排布的线状半导体图形，所述线状半导体图形之间形成有第一绝缘层；所述线状半导体图形包括沟道区域和与所述沟道区域连接的漏极区域；刻蚀所述漏极区域一侧的部分所述第一绝缘层，以形成第一开口，所述第一开口暴露出竖直方向上排布的多个漏极区域的第一侧壁，所述第一开口底部暴露出所述半导体衬底的部分表面；
对所述第一开口暴露的漏极区域进行离子掺杂，以在所述漏极区域中形成接地掺杂区，所述接地掺杂区与所述沟道区域连接，且与所述沟道区域具有相同的掺杂类型；
在所述第一开口中填充导电材料，形成接地导电插塞，所述接地导电插塞与所述接地掺杂区和所述半导体衬底电连接。
本公开一些实施例还提供了一种半导体结构，包括：
半导体衬底；
位于所述半导体衬底上的绝缘层和线状半导体图形层交替层叠的堆叠结构，每一层所述线状半导体图形层包括沿第一方向延伸的多个平行的线状半导体图形，所述线状半导体图形包括沟道区和与所述沟道区连接的接地掺杂区；且所述接地掺杂区与所述沟道区具有相同的掺杂类型；
位于相邻线状半导体图形之间的接地导电插塞，所述接地导电插塞沿竖直方向贯穿所述堆叠结构且连接所述半导体衬底，且所述接地导电插塞在第二方向的一侧与所述接地掺杂区连接。
本公开前述一些实施例中的半导体结构的形成方法，通过形成接地掺杂区和接地导电插塞使得所述沟道区域可以接地，从而将所述沟道区域积累的电荷通过接地掺杂区和接地导电插塞释放掉，防止浮体效应的产生，提高了器件的 性能，并且所述接地掺杂区是形成在漏极区域中，接地导电插塞是形成在第一沟槽中，不会占据额外的面积，能保证形成的3D DRAM器件的集成度。
附图说明
图1-52为本公开一些实施例中半导体结构的形成过程的结构示意图。
具体实施方式
下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
本公开一些实施例首先提供了一种半导体结构的形成方法，下面结合附图对所述形成方法进行详细的描述。
参考图1-图4，其中图2为图1沿切割线AA1方向的剖面结构示意图，图3为图1沿切割线BB1方向的剖面结构示意图，图4为图1沿切割线CC1方向的剖面结构示意图(需要说明的是，为了更好的示意，图1中未示出最顶层的一层牺牲层202，直接示出了最顶层的牺牲层202底部的一层半导体层233)。半导体结构的形成方法包括：提供半导体衬底200；在半导体衬底200上形成牺牲层202和半导体层233在竖直方向上交替层叠的堆叠结构201，竖直方向为垂直于半导体衬底上表面的方向。
半导体衬底200的材料可以为单晶硅(Si)、单晶锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，半导体衬底200的材料为单晶硅(Si)。
堆叠结构201包括在竖直方向上交替层叠的牺牲层202和半导体层233，牺牲层202和半导体层233在竖直方向上交替层叠是指：在形成一层牺牲层202后，在该牺牲层202的表面形成一层半导体层233，然后依次循环进行形成牺牲层202和位于牺牲层202上的半导体层233的步骤。牺牲层202和半导体层233的层数可以根据实际需要进行确定。本实施例中，以牺牲层202为四层，半导体层233为四层作为示例进行说明，堆叠结构201的最底层和最顶层均为一层牺牲层202。在其他实施例中，牺牲层202和半导体层233的层数可以为其他数量。
半导体层233后续用于形成线状半导体图形。牺牲层202作为牺牲材料在后续工艺中会被去除，或者部分牺牲层202后续可以直接作为绝缘层的一部分。牺牲层202的材料与半导体层233的材料不相同，以在后续去除牺牲层202时，牺牲层202相对于半导体层233(或线状半导体图形)具有高的刻蚀选择比(刻蚀选择比大于2:1)，从而使得牺牲层202被去除的同时，半导体层233(或线状半导体图形)不会被刻蚀或者被刻蚀的量较小。
在一些实施例中，半导体层233的材料为硅或锗硅，牺牲层202的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅、无定型硅、无定形碳、多晶硅、锗硅中的一种。本实施例中，半导体层233的材料为硅，牺牲层202的材料为锗硅。在其他实施例中，牺牲层202的材料为氧化硅、氢氧化硅、氮化硅等，半导体层233的材料为氧化物半导体，例如，InxGayZnzO、InxGaySizO、InxSnyZnzO、InxZnyO、ZnxO、ZnxSnyO、ZnxOyN、ZrxZnySnzO、SnxO、HfxInyZnzO、GaxZnySnzO、AlxZnySnzO、YbxGayZnzO、InxGayO或以上材料的组合。
在一些实施例中，半导体层233为掺杂的半导体层233，即半导体层233中预掺杂有杂质离子。杂质离子可以为N型杂质离子或P型杂质离子。在一 些实施例中，P型杂质离子为硼、镓、铟其中的一种或几种，N型杂质离子包括磷、砷、锑其中的一种或几种。本实施例中，半导体层233中掺杂的杂质离子为P型杂质离子。在其他实施例中，半导体层233也可以为未掺杂的半导体层233。
牺牲层202和半导体层233分别通过沉积工艺形成。沉积工艺包括外延工艺。
参考图5-图8，其中图6为图5沿切割线AA1方向的剖面结构示意图，图7为图5沿切割线BB1方向的剖面结构示意图，图8为图5沿切割线CC1方向的剖面结构示意图，刻蚀堆叠结构201，以形成在第一方向和竖直方向贯穿堆叠结构的多个第一沟槽204，相邻第一沟槽204之间剩余的沿第一方向延伸的半导体层为线状半导体图形203，线状半导体图形203沿第一方向延伸、且在第二方向和竖直方向阵列排布，每一个线状半导体图形203包括沟道区域21和分别位于沟道区域21两端并与沟道区域21连接的源极区域23和漏极区域22(参考图5和图6)，第一方向与第二方向垂直且均平行于半导体衬底200上表面。
多个第一沟槽204沿竖直方向贯穿堆叠结构201，多个第一沟槽204之间是相互平行的，且形成的第一沟槽204是沿第一方向延伸的。本公开中，切割线AA1的方向平行于第一方向。
在一些实施例中，在形成第一沟槽204时，过刻蚀半导体衬底200，使得第一沟槽204的底部位于半导体衬底200中(参考图8)。
在一些实施例中，刻蚀堆叠结构201前，在堆叠结构201表面上形成图形化的第一掩膜层(图中未示出)，图形化的第一掩膜层中具有沿第一方向延伸的多个开口，多个开口的位置与待形成的多个第一沟槽的位置对应；以图形化的第一掩膜层为掩膜，沿开口刻蚀堆叠结构201，在堆叠结构中形成沿第一方向延伸的多个平行的第一沟槽204；去除图形化的第一掩膜层。
在一些实施例中，刻蚀堆叠结构201可以采用各向异性的干法刻蚀工艺，比如各向异性的等离子体刻蚀工艺。
每一层的半导体层233(参考图1-图4)在被刻蚀后均会形成多个沿第一方向延伸且相互平行的线状半导体图形203，每一层的多个线状半导体图形203构成一层线状半导体图形层。
每一个线状半导体图形203包括沟道区域21和分别位于沟道区域21两端并与沟道区域21连接的源极区域23和漏极区域22(参考图5和图6)，沟道区域21后续作为横向晶体管的沟道区，源极区域23后续用于形成横向晶体管的源区，漏极区域22的一部分用于形成横向晶体管的漏区，漏极区域22的另一部分用于形成与沟道区域21连接的接地掺杂区。
参考图9-图12，其中图10为图9沿切割线AA1方向的剖面结构示意图，图11为图9沿切割线BB1方向的剖面结构示意图，图12为图9沿切割线CC1方向的剖面结构示意图，在第一沟槽204中形成填充满第一沟槽的第一绝缘层206。
第一绝缘层206用于后续形成的器件之间的电学隔离。
在一些实施例中，第一绝缘层206的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)、低介电常数(K小于2.5)材料中的一种或几种。本实施例中，第一绝缘层206的材料为氧化硅，形成第一绝缘层206的工艺为化学气相沉积工艺。
在一些实施例中，当牺牲层202采用非绝缘材料(比如牺牲层材料为锗硅时)，在形成第一绝缘层206之前，沿第一沟槽204去除相邻漏极区域22之间的牺牲层，形成第一空腔，去除相邻漏极区域22之间的牺牲层可以采用湿法刻蚀工艺，在一些实施例中，在去除相邻漏极区域22之间的牺牲层之前，将漏极区域之外的其他区域可以通过掩膜层(比如光刻胶掩膜层或其他合适的掩膜层)覆盖；形成填充满第一空腔和第一沟槽的第一绝缘层206。
在其他一些实施例中，当牺牲层202采用绝缘材料(比如氧化硅或氮化硅时)，在形成第一绝缘层206之前，可以不去除相邻漏极区域22之间的牺牲层，直接将相邻漏极区域22之间的牺牲层作为第一绝缘层的一部分。在形成第一绝缘层206之前，也可以沿第一沟槽204去除相邻漏极区域22之间的牺牲层，形成第一空腔；然后形成填充满第一空腔和第一沟槽的第一绝缘层206。
在一些实施例中，参考图13-图16，其中图14为图13沿切割线AA1方向的剖面结构示意图，图15为图13沿切割线BB1方向的剖面结构示意图，图16为图13沿切割线CC1方向的剖面结构示意图，去除部分第一绝缘层206和部分牺牲层202，形成沿竖直方向和第二方向延伸的多个支撑结构207，支撑结构填充于线状半导体图形203之间，支撑结构207的材料与第一绝缘层206和牺牲层202的材料不相同。
支撑结构207在后续工艺中用于支撑线状半导体图形203，防止线状半导体图形203由于悬空而变形。
在一实施例中，支撑结构207至少为两个，两个支撑结构207分别位于沟道区域21的两端。支撑结构207的材料与第一绝缘层206和牺牲层202的材料不相同，使得后续在刻蚀第一绝缘层206和牺牲层202时，对支撑结构207的刻蚀速率很低，保证了支撑结构207的完整。
在一些实施例中，支撑结构207的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅。本实施例中，支撑结构207的材料为氮化硅。
在一些实施例中，在形成支撑结构207之前，需要刻蚀牺牲层202和第一绝缘层206，在牺牲层202和第一绝缘层206中形成沿第二方向延伸的至少两个开口，在开口中形成填充满开口的支撑结构207。
第二方向位于第一方向具有一定夹角的方向，本实施例中，第二方向与第一方向垂直，或者第二方向与第一方向的夹角为90°。
在一实施例中，参考图17-图20，其中图18为图17沿切割线AA1方向的剖面结构示意图，图19为图17沿切割线BB1方向的剖面结构示意图，图20为图17沿切割线CC1方向的剖面结构示意图，刻蚀去除相邻漏极区域22之间的第一沟槽204中的中间部分的第一绝缘层206，以在第一沟槽204中的第一绝缘层206中形成沿第一方向延伸的第二开口208，第二开口208底部暴露出半导体衬底200的部分表面。
第二开口208中后续用于形成隔离层，隔离层用于电学隔离在隔离层两侧分别形成位线和接地导电插塞。形成第二开口208采用各向异性的干法刻蚀工艺，在刻蚀第一绝缘层206之前，在堆叠结构表面形成图形化的掩膜层，以图形化的掩膜层为掩膜，刻蚀相邻漏极区域22之间的第一沟槽204中的中间部分的第一绝缘层206，在第一沟槽204中的第一绝缘层206中形成沿第一方向延伸的第二开口208。
在一些实施例中，第二开口208的尺寸为第一沟槽204尺寸的10％-20％，在保证后续第二开口208中形成的隔离层的电学隔离性能的同时，在隔离层的两侧暴露足够的空间以分别形成位线和接地导电插塞。第二开口208的尺寸为 沿第二方向上第二开口208两侧壁之间的垂直距离，第一沟槽204的尺寸为沿第二方向上第一沟槽204两侧壁之间的垂直距离
在一些实施例中，参考图21-图24，其中图22为图21沿切割线AA1方向的剖面结构示意图，图23为图21沿切割线BB1方向的剖面结构示意图，图24为图21沿切割线CC1方向的剖面结构示意图，形成填充满第二开口的隔离层209。
隔离层209的材料与第一绝缘层206的材料不相同，隔离层209的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅。本实施例中，隔离层209的材料为氮化硅。
在一实施例中，参考图25-图28，其中图26为图25沿切割线AA1方向的剖面结构示意图，图27为图25沿切割线BB1方向的剖面结构示意图，图28为图25沿切割线CC1方向的剖面结构示意图，去除相邻沟道区域21之间的牺牲层和第一绝缘层，在去除牺牲层的位置形成第二空腔，第二空腔与第一沟槽连通，使沟道区域21悬空；在沟道区域的表面形成字线介质层(图中未示出)；在每一层的沟道区域的字线介质层上形成沿第二方向延伸的金属字线210。
本实施例中，沟道区域21预掺杂有P型杂质离子，将沟道区域21直接作为横向晶体管的沟道区。在其他实施例中，在形成字线介质层之前，对沟道区域进行杂质离子掺杂，在沟道区域21中形成横向晶体管的沟道区。
本实施例中，金属字线为水平字线(水平字线呈水平设置，平行于半导体衬底200表面)，每一层中的多个线状半导体图形的沟道区域21都与一个金属字线210对应，相邻层的金属字线210是分立或分开的。
本实施例中，金属字线210为环绕栅结构，每一个金属字线210环绕某一层中沿第二方向排布的多个沟道区域21表面上。
在其他实施例中，金属字线可以为双层栅结构，每一个金属字线中的双层栅分别位于某一层中沿第二方向排布的多个沟道区域的上下表面上。
在一实施例中，字线介质层的材料可以为氧化硅或高K(K大于2.5)介电材料，金属字线的材料可以为Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、Wsi中的一种或几种。
在其他实施例中，形成的金属字线为垂直字线(垂直字线呈竖直设置，垂直于半导体衬底200的表面)，每一个金属字线环绕竖直方向上的多个沟道区域21表面的字线介质层，或者位于竖直方向上的多个沟道区域21表面的字线介质层的表面上，且相邻的额两个金属字线是分立或分开的。
在一些实施例中，形成金属字线210后，在剩余的第一沟槽和第二空腔填充满第二绝缘层211(参考图26和图27)。
本实施例中，字线介质层和金属字线210先于后续形成的位线和接地导线插塞形成。在其他实施例中，字线介质层和金属字线210在形成位线和接地导线插塞之后形成。
参考图29-图32，其中图39为图29沿切割线AA1方向的剖面结构示意图，图31为图29沿切割线BB1方向的剖面结构示意图，图32为图29沿切割线CC1方向的剖面结构示意图，刻蚀去除隔离层209另一侧(另一侧为隔离层209的不与后续形成的位线相接触的一侧)的部分第一绝缘层206，形成第三开口212，第三开口212的侧面暴露出竖直方向上的多个漏极区域22的第二侧面。
每一个漏极区域沿第二方向上均包括相对的第一侧面和第二侧面。
第三开口212中后续用于形成位线，并且第三开口212还用于作为对漏极区域进行掺杂形成漏区的窗口。
参考图33-图36，其中图34为图33沿切割线AA1方向的剖面结构示意图，图35为图33沿切割线BB1方向的剖面结构示意图，图36为图33沿切割线CC1方向的剖面结构示意图，沿第三开口212，对第三开口212暴露的竖直方向上的多个漏极区域22进行掺杂，在漏极区域22中形成漏区213，漏区213与后续形成的接地掺杂区邻接，且漏区213的掺杂类型与接地掺杂区和沟道区域21的掺杂类型相反。
沿第三开口212，对第三开口212暴露的漏极区域22进行离子注入工艺形成漏区213，漏区213仅形成在漏极区域22的一部分区域(靠近第三开口212的部分区域)中，漏极区域22另一部分区域后续用于形成接地掺杂区。
漏区213中掺杂的杂质离子可以为N型杂质离子或P型杂质离子。在一些实施例中，P型杂质离子为硼、镓、铟其中的一种或几种，N型杂质离子包括磷、砷、锑其中的一种或几种。本实施例中，半导体层233中掺杂的杂质离子为N型杂质离子。
参考图37-图40，其中图38为图37沿切割线AA1方向的剖面结构示意图，图39为图37沿切割线BB1方向的剖面结构示意图，图40为图37沿切割线CC1方向的剖面结构示意图，在第三开口中形成填充满第三开口的位线214，位线214与多个漏区213连接。
每一根位线214与第三开口中暴露的多个漏区213连接。位线214的材料为金属，金属可以为Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、Wsi中的一种或几种。
本实施例中，位线214形成在第一沟槽中，与漏区213的侧面(漏区侧面为平行于第一方向的表面)连接。在其他实施例中，位线可以形成在漏区213的端部或漏区213中，通过形成贯穿漏区213的通孔后，在通孔中填充满导电材料形成。
在其他实施例中，当形成的金属字线为垂直字线(垂直字线呈竖直设置，垂直于半导体衬底200的表面)，每一个金属字线环绕竖直方向上的多个沟道区域21表面的字线介质层，或者位于竖直方向上的多个沟道区域21表面的字线介质层的表面上，且相邻的额两个金属字线是分立或分开的时，形成的位线可以为多个水平位线(水平位线呈水平设置，平行于半导体衬底200的表面)，多个水平位线为分立的，每一个水平位线将某一层中的多个漏区连接在一起，且水平位线不会与后续形成的接地掺杂区存在连接。
参考图41-图44，其中图42为图41沿切割线AA1方向的剖面结构示意图，图43为图41沿切割线BB1方向的剖面结构示意图，图44为图41沿切割线CC1方向的剖面结构示意图，刻蚀漏极区域22一侧的第一沟槽中的部分第一绝缘层206，在第一绝缘层206中形成第一开口215，第一开口215的侧面暴露出竖直方向上的多个漏极区域22的一侧侧壁，第一开口215底部暴露出半导体衬底的部分表面。
本实施例中，刻蚀去除隔离层209一侧的部分第一绝缘层，形成第一开口215，第一开口215中后续形成接地导电插塞，且第一开口作为形成接地掺杂区时的离子注入的窗口。第一开口215与前述形成的第三开口分别位于隔离层209的两侧，因而第一开口215形成的接地导电插塞和第三开口中形成的位线也分别位于隔离层209的两侧。
参考图45-图48，其中图46为图45沿切割线AA1方向的剖面结构示意 图，图47为图45沿切割线BB1方向的剖面结构示意图，图48为图45沿切割线CC1方向的剖面结构示意图，对第一开口215暴露的漏极区域22进行离子掺杂，以在漏极区域22中形成接地掺杂区216，接地掺杂区216与沟道区域21连接，且与沟道区域21具有相同的掺杂类型。
沿第一开口215，对第一开口215暴露的漏极区域22进行离子注入工艺形成接地掺杂区216，接地掺杂区216仅形成在漏极区域22的一部分区域(靠近第一开口215的部分区域)中，且接地掺杂区216位于漏区213一侧。
接地掺杂区216中掺杂的杂质离子可以为N型杂质离子或P型杂质离子。在一些实施例中，P型杂质离子为硼、镓、铟其中的一种或几种，N型杂质离子包括磷、砷、锑其中的一种或几种。本实施例中，接地掺杂区216中掺杂的杂质离子为P型杂质离子。
本实施例中，接地掺杂区216与沟道区域21连接，且与沟道区域21具有相同的掺杂类型，使得接地掺杂区216与沟道区域21是导通的，后续在第一开口中形成接地导电插塞后，接地导电插塞与接地掺杂区216之间是连接导通的，因而通过形成接地掺杂区216和接地导电插塞使得沟道区域21可以接地，从而将沟道区域21积累的电荷通过接地掺杂区216和接地导电插塞释放掉，防止浮体效应的产生，提高了器件的性能，并且接地掺杂区216是形成在漏极区域中，接地导电插塞是形成在第一沟槽中，不会占据额外的面积，能保证形成的DRAM器件的集成度。
参考图49-图52，其中图50为图49沿切割线AA1方向的剖面结构示意图，图51为图49沿切割线BB1方向的剖面结构示意图，图52为图49沿切割线CC1方向的剖面结构示意图，在第一开口中填充导电材料，形成接地导电插塞217，接地导电插塞217与接地掺杂区216和半导体衬底200连接。
接地导电插塞217的材料为金属或掺杂的多晶硅，金属可以为Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、Wsi中的一种或几种。
半导体衬底上具有接地端，接地导电插塞217的上端与接地掺杂区216连接，接地导电插塞217的底端与半导体衬底200上的接地端连接，因而本公开中通过形成接地掺杂区216和接地导电插塞217使得沟道区域21可以接地，从而将沟道区域21积累的电荷通过接地掺杂区216和接地导电插塞217释放掉，防止浮体效应的产生，提高了器件的性能，并且接地掺杂区216是形成在漏极区域22中，接地导电插塞217是形成在第一沟槽204中，不会占据额外的面积，能保证形成的3D DRAM器件的集成度。
本实施例中，接地导电插塞217和位线214都是形成在第一沟槽中，接地导电插塞217和位线214之间通过隔离层209隔离，接地导电插塞217和位线214不会占据额外的面积，有利于提高器件的集成度。
本实施例中，接地导电插塞217在位线214之后形成。在其他实施例中，接地导电插塞217可以在位线214之前形成。
在一实施例中，还包括：对源极区域23进行掺杂，在源极区域中形成源区(图中未示出)，源区的掺杂类型与漏区的掺杂类型相同；去除源区之间的牺牲层和隔离层，在去除牺牲层和隔离层的区域形成与源区连接的电容器(图中未示出)。
本公开一些实施例还提供了一种半导体结构，参考图49-图52，其中图50为图49沿切割线AA1方向的剖面结构示意图，图51为图49沿切割线BB1方向的剖面结构示意图，图52为图49沿切割线CC1方向的剖面结构示意图， 包括：
半导体衬底200；
位于半导体衬底200上的绝缘层(206/211)和线状半导体图形层交替层叠的堆叠结构，每一层线状半导体图形层包括沿第一方向延伸的多个平行的线状半导体图形203，线状半导体图形203包括沟道区和与沟道区连接的接地掺杂区216；且接地掺杂区216与沟道区具有相同的掺杂类型；
位于相邻线状半导体图形203之间的接地导电插塞217，接地导电插塞217沿竖直方向贯穿堆叠结构且连接半导体衬底200，且接地导电插塞217在第二方向的一侧与接地掺杂区216连接。
在一些实施例中，还包括：线状半导体图形203还包括与沟道区连接的漏区213，漏区213位于接地掺杂区216一侧，且漏区213的掺杂类型与接地掺杂区216和沟道区的掺杂类型相反；位于接地导电插塞217的远离与接地掺杂区216接触的一侧侧面的隔离层209；；位于隔离层209的在第二方向的远离接地导电插塞217一侧的位线214，位线214沿竖直方向贯穿堆叠结构且位线214与多个漏区213连接。在一些实施例中，隔离层209与绝缘层(206)的材料不相同。
在一些实施例中，隔离层209的尺寸为第一沟槽204尺寸的10％-20％。
在一些实施例中，还包括：位于沟道区的表面形成字线介质层(图中未示出)；位于每一层的沟道区的字线介质层上的沿第二方向延伸的金属字线210；相邻金属字线210之间的区域被绝缘层填充。
在一些实施例中，金属字线210为环绕栅结构，每一个金属字线210环绕某一层中沿第二方向排布的多个沟道区表面上。
在一些实施例中，金属字线为双层栅结构，每一个金属字线中的双层栅分别位于某一层中沿第二方向排布的多个沟道区的上下表面上。
在一些实施例中，还包括：位于多个绝缘层中以及顶层的线状半导体图形203的表面上的沿第二方向延伸的多个支撑结构207，支撑结构207的材料与绝缘层不相同。
在一些实施例中，接地导电插塞217的材料为金属或掺杂的多晶硅。
在一些实施例中，还包括：位于源极区域23中的源区(图中未示出)，源区的掺杂类型与漏区的掺杂类型相同；与源区连接的电容器(图中未示出)。
需要说明的是，前述半导体结构的一些实施例中与前述半导体结构形成方法的一些实施例中相同或相似部分的限定或描述在此不再赘述，具体请参考前述半导体结构形成方法的一些实施例中相应部分的限定或描述。
本公开虽然已以较佳实施例公开如上，但其并不是用来限定本公开，任何本领域技术人员在不脱离本公开的精神和范围内，都可以利用上述揭示的方法和技术内容对本公开技术方案做出可能的变动和修改，因此，凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本公开技术方案的保护范围。

Claims (20)

  1. 一种半导体结构的形成方法，其中，包括：
    提供半导体衬底(200)；
    在所述半导体衬底(200)上形成沿第一方向延伸、且在第二方向和竖直方向阵列排布的线状半导体图形(203)，所述线状半导体图形(203)之间形成有第一绝缘层(206)；所述线状半导体图形(203)包括沟道区域(21)和与所述沟道区域(21)连接的漏极区域(22)；刻蚀所述漏极区域(22)一侧的部分所述第一绝缘层(206)，以形成第一开口(215)，所述第一开口(215)暴露出竖直方向上排布的多个漏极区域(22)的第一侧壁，所述第一开口(215)底部暴露出所述半导体衬底(200)的部分表面；
    对所述第一开口(215)暴露的漏极区域(22)进行离子掺杂，以在所述漏极区域(22)中形成接地掺杂区(216)，所述接地掺杂区(216)与所述沟道区域(21)连接，且与所述沟道区域(21)具有相同的掺杂类型；
    在所述第一开口(215)中填充导电材料，形成接地导电插塞(217)，所述接地导电插塞(217)与所述接地掺杂区(216)和所述半导体衬底(200)电连接。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在所述半导体衬底(200)上形成沿第一方向延伸、且在第二方向和竖直方向阵列排布的线状半导体图形(203)，包括：
    在所述半导体衬底(200)上形成牺牲层和半导体层在所述竖直方向上交替层叠的堆叠结构；
    刻蚀所述堆叠结构，以形成在所述第一方向和竖直方向贯穿所述堆叠结构的多个第一沟槽(204)，相邻所述第一沟槽(204)之间剩余的半导体层为线状半导体图形(203)，所述竖直方向垂直于所述半导体衬底(200)上表面，所述第一方向与所述第二方向垂直且均平行于所述半导体衬底(200)上表面；
    在所述线状半导体图形(203)之间填充所述第一绝缘层(206)。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述在形成所述第一开口(215)之前，还包括：刻蚀去除所述相邻漏极区域(22)之间的第一沟槽(204)中的中间部分的第一绝缘层(206)，以在所述第一沟槽(204)中的第一绝缘层(206)中形成沿第一方向延伸的第二开口(208)，所述第二开口(208)底部暴露出所述半导体衬底(200)的部分表面；形成填充满所述第二开口(208)的隔离层(209)。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述刻蚀所述漏极区域(22)一侧的部分第一绝缘层(206)，包括：
    刻蚀去除所述隔离层(209)一侧的部分第一绝缘层(206)，形成所述第一开口(215)。
  5. 根据权利要求3所述的半导体结构的形成方法，其中，所述方法还包括：
    刻蚀去除所述隔离层(209)另一侧的部分第一绝缘层(206)，形成第三开口(212)，所述第三开口(212)暴露出竖直方向上排布的多个漏极区域(22)的第二侧壁；沿第三开口(212)，对所述第三开口(212)暴露的竖直方向上的多个漏极区域(22)进行掺杂，在所述漏极区域(22)中形成漏区(213)，所述漏区(213)与所述接地掺杂区(216)邻接，且所述漏区(213)的掺杂类型与所述接地掺杂区(216)和所述沟道区域(21)的掺杂类型相反；在所述第三开口(212)中形成填充满所述第三开口(212)的位线(214)，所述位线(214)与所述多个漏区(213)连接。
  6. 根据权利要求4所述的半导体结构的形成方法，其中，所述方法还包括：
    去除所述相邻沟道区域(21)之间的所述牺牲层和所述第一绝缘层(206)，在去除所述牺牲层的位置形成第二空腔，所述第二空腔与所述第一沟槽(204)连通，使所述沟道区域(21)悬空；在所述沟道区域(21)的表面形成字线介质层；在每一层的所述沟道区域(21)的字线介质层上形成沿第二方向延伸的金属字线(210)；在剩余的所述第一沟槽(204)和第二空腔填充满第二绝缘层(211)。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述金属字线(210)为环绕栅结构，每一个所述金属字线(210)环绕同一层沿第二方向排布的所述多个沟道区域(21)表面。
  8. 根据权利要求6所述的半导体结构的形成方法，其中，所述金属字线(210)为双层栅结构，每一个所述金属字线(210)中的双层栅分别位于同一层沿第二方向排布的所述多个沟道区域(21)的上下表面上。
  9. 根据权利要求2所述的半导体结构的形成方法，其中，所述方法还包括：
    去除部分所述第一绝缘层(206)和部分所述牺牲层，形成沿所述竖直方向和所述第二方向延伸的多个支撑结构(207)，所述支撑结构(207)填充于线状半导体图形(203)之间，所述支撑结构(207)的材料与所述第一绝缘层(206)和所述牺牲层的材料不相同。
  10. 根据权利要求2所述的半导体结构的形成方法，其中，在所述线状半导体图形(203)之间填充所述第一绝缘层(206)之前，还包括：沿所述第一沟槽(204)去除相邻所述漏极区域(22)之间的牺牲层，形成第一空腔；所述第一绝缘层(206)还填充满所述第一空腔。
  11. 根据权利要求5所述的半导体结构的形成方法，其中，所述线状半导体图形(203)还包括与所述沟道区域(21)连接的源极区域(23)；所述源极区域(23)和漏极区域(22)分别位于所述沟道区域(21)两端，所述方法还包括：对所述源极区域(23)进行掺杂，在所述源极区域(23)中形成源区，所述源区的掺杂类型与所述漏区(213)的掺杂类型相同；去除所述源极区域(23)之间的牺牲层和隔离层(209)，在去除所述牺牲层和隔离层(209)的区域形成与所述源区电连接的电容器。
  12. 一种半导体结构，其中，包括：
    半导体衬底(200)；
    位于所述半导体衬底(200)上的绝缘层和线状半导体图形(203)层交替层叠的堆叠结构，每一层所述线状半导体图形(203)层包括沿第一方向延伸的多个平行的线状半导体图形(203)，所述线状半导体图形(203)包括沟道区和与所述沟道区连接的接地掺杂区(216)；且所述接地掺杂区(216)与所述沟道区具有相同的掺杂类型；
    位于相邻线状半导体图形(203)之间的接地导电插塞(217)，所述接地导电插塞(217)沿竖直方向贯穿所述堆叠结构且连接所述半导体衬底(200)，且所述接地导电插塞(217)在第二方向的一侧与所述接地掺杂区(216)连接。
  13. 根据权利要求12所述的半导体结构，其中，还包括：所述线状半导体图形(203)还包括与所述沟道区连接的漏区(213)；位于所述接地导电插塞(217)的远离与所述接地掺杂区(216)接触的一侧侧面的隔离层(209)；
    位于所述隔离层(209)的在所述第二方向的远离所述接地导电插塞(217)一侧的位线(214)，所述位线(214)沿竖直方向贯穿所述堆叠结构且所 述位线(214)与所述多个漏区(213)连接。
  14. 根据权利要求13所述的半导体结构，其中，所述隔离层(209)与所述绝缘层的材料不相同。
  15. 根据权利要求13所述的半导体结构，其中，还包括：位于所述沟道区的表面的字线介质层；位于每一层的所述沟道区的字线介质层上的沿第二方向延伸的金属字线(210)；相邻所述金属字线(210)之间的区域被绝缘层填充。
  16. 根据权利要求15所述的半导体结构，其中，所述金属字线(210)为环绕栅结构，每一个所述金属字线(210)环绕某一层中沿第二方向排布的所述多个沟道区表面上。
  17. 根据权利要求15所述的半导体结构，其中，所述金属字线(210)为双层栅结构，每一个所述金属字线(210)中的双层栅分别位于某一层中沿第二方向排布的所述多个沟道区的上下表面上。
  18. 根据权利要求15所述的半导体结构，其中，位于所述绝缘层中以及顶层的线状半导体图形(203)的表面上的沿第二方向延伸的多个支撑结构(207)，所述支撑结构(207)的材料与所述绝缘层不相同。
  19. 根据权利要求12所述的半导体结构，其中，所述接地导电插塞(217)的材料为金属或掺杂的多晶硅。
  20. 根据权利要求13所述的半导体结构，其中，还包括：位于所述源极区域(23)中的源区，所述源区的掺杂类型与所述漏区(213)的掺杂类型相同；与所述源区连接的电容器。
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