WO2024035404A1

WO2024035404A1 - Apparatus and method for wideband channel estimation

Info

Publication number: WO2024035404A1
Application number: PCT/US2022/040010
Authority: WO
Inventors: Chengzhi LI
Original assignee: Zeku, Inc.
Priority date: 2022-08-10
Filing date: 2022-08-10
Publication date: 2024-02-15

Abstract

Apparatuses and methods for wideband channel estimation are disclosed. According to one aspect of the present disclosure, a baseband is provided. The baseband chip includes a processor and memory coupled to the processor and storing instructions. The processor is configured to identify one or more interference ports using a de-orthogonal cover code (de-OCC) operation on an original virtual port. The de-OCC operation is an inverse of an orthogonal cover code (OCC) operation. The original virtual port is obtained based on a demodulation reference signal (DMRS). A virtual port for the one or more interference ports is reconstructed based on the OCC operation. Channel estimation for one or more serving ports is obtained based on the virtual port for the one or more interference ports.

Description

APPARATUS AND METHOD FOR WIDEBAND CHANNEL ESTIMATION

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-gen eration (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), channel estimation plays a particularly important role in the performance of wireless communication systems. It can be conducted in different ways, such as using frequency and/or timing correlation properties in the wireless channel. In the meantime, the 3rd Generation Partnership Project (3GPP) also defines various solutions for channel estimation using reference signals.

SUMMARY

[0003] Embodiments of apparatus and method for channel estimation are disclosed herein.

[0004] According to one aspect of the present disclosure, a baseband is provided. The baseband chip includes a processor and memory coupled to the processor and storing instructions. The processor is configured to identify one or more interference ports using a de-orthogonal cover code (de-OCC) operation on an original virtual port. The original virtual port is obtained based on a demodulation reference signal (DMRS). The de-OCC operation is an inverse of an orthogonal cover code (OCC) operation. A virtual port for the one or more interference ports is reconstructed based on the OCC operation and the one or more interference ports. Channel estimation for one or more serving ports is obtained based on the virtual port for the one or more interference ports.

[0005] According to one aspect of the present disclosure, another baseband chip is provided. The baseband chip includes a processor and memory coupled to the processor and storing instructions. The processor is configured to identify one or more interference ports using a de- orthogonal cover code (de-OCC) operation on an original virtual port. The original virtual port is obtained based on a demodulation reference signal (DMRS). The de-OCC operation is an inverse of an orthogonal cover code (OCC) operation. A first virtual port for the one or more interference ports is reconstructed based on the one or more interference ports and the OCC operation. A second virtual port for one or more serving ports is reconstructed based on the first virtual port. Channel estimation for the one or more interference ports is obtained based on the second virtual port.

[0006] According to one aspect of the present disclosure, a method of wideband channel estimation is provided. One or more interference ports are identified using a de-orthogonal cover code (de-OCC) operation on an original virtual port. The original virtual port is obtained based on a demodulation reference signal (DMRS). The de-OCC operation is an inverse of an OCC operation. A virtual port for the one or more interference ports is reconstructed based on the one or more interference ports and the OCC operation. Channel estimation for one or more serving ports is obtained based on the virtual port for the one or more interference ports.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates the orthogonal cover codes (OCCs) in double-symbol demodulation reference signal (DMRS) configuration type 1 and double-symbol DMRS configuration type 2, respectively.

[0009] FIG. 2 illustrates an exemplary wireless network, in which some aspects of the present disclosure may be implemented, according to some implementations of the present disclosure.

[0010] FIG. 3 illustrates a block diagram of an exemplary node, according to some implementations of the present disclosure.

[0011] FIG. 4 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some implementations of the present disclosure.

[0012] FIG. 5 illustrates a block diagram of an exemplary wideband (WB) channel estimation unit, according to some implementations of the present disclosure.

[0013] FIG. 6 illustrates a flow chart of an exemplary method of WB channel estimation, according to some implementations of the present disclosure.

[0014] FIG. 7 illustrates a block diagram of another exemplary WB channel estimation unit, according to some implementations of the present disclosure.

[0015] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0016] Although specific configurations and arrangements are discussed, it should be understood that they are provided for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0017] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” “an example,” “some examples,” “an instance,” “some instances,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0018] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for the existence of additional factors not necessarily expressly described, again, depending at least in part on the context.

[0019] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0020] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0021] One important consideration in the field of wireless communication is related to channel performance/estimation. Channel performance may be estimated using reference signals, such as demodulation reference signals (DMRS). The DMRS has been employed in the 5G NR recently. The DMRS for physical downlink shared channel (PDSCH) or for physical uplink shared channel (PUSCH) is a special type of physical layer signals. The DMRS for PDSCH is configured for coherent channel estimation at a device, while the DMRS for PUSCH is configured for a base station to coherently demodulate/decode the PUSCH. The DMRS is present only in resource blocks (RBs) used for the PDSCH transmission and PUSCH transmission, respectively. A resource block (RB) is the smallest unit of resources that can be allocated to a user equipment (UE).

[0022] In the multi-user, multiple-input, multiple-output technology (MU-MIMO) for the 5G NR, the setting and the number of interference UEs may vary from one RB to another RB when a serving UE is configured to apply a wideband (WB) DMRS. For the reason that the statistics of the interference channels may vary in each RB, the virtual ports may be thus composed of different logic ports that are combined by the orthogonal cover code (OCC). As a result, the WB channel estimation for the serving UE cannot be directly applied to the original virtual ports.

[0023] For a multiple-input, multiple-output (MIMO) communication system with M transmitting antennas and N receiving antennas, the corresponding discrete-time channel model can be given by: y[k] = Hx[k] + n[fc] (1), where & denotes a discrete time index, //represents the (Nx.M) MEMO channel matrix, x[/] denotes the transmitted vector at time instant k, y\k\ denotes the received vector at time instant k, and n[k\ denotes a vector that accounts for noise and interference.

[0024] In a system described by Equation (1), a UE may estimate the channel performance based on the effective channel matrix H. In an MU-MIMO system for multiple users, however, when a serving UE is set to use the WB DMRS, the channel matrix H for a serving UE may also include the interference from other UEs, i.e., from the interference UEs. The setting and the number of the interference UEs may vary from one RB to another, depending on a multiplied combination of the OCC. As a result, it may become relatively complicated to acquire an accurate WB channel estimation.

[0025] FIG. 1 illustrates the orthogonal cover codes (OCCs) in double-symbol DMRS configuration type 1 and double-symbol DMRS configuration type 2, respectively. The DMRS configuration type 1 may support a single layer up to 8-layer transmission with orthogonal DMRS ports, while the DMRS configuration type 2 may support up to 12-layer. One DMRS port is for each layer. As shown in FIG. 1, the two double-symbol DMRS configurations have two adjacent DMRS symbols in a time domain, where the type 1 supports up to eight DMRS ports, and the type 2 supports up to 12 DMRS ports. The type 1 includes length-2 OCC in the frequency domain and length-2 OCC in the time domain, while the type 2 is associated with length-2 OCC in the time domain and length-3 OCC in the frequency domain.

[0026] As used herein, the terms “DMRS ports” and “logic ports” may be used to refer to the antenna ports for each layer in the DMRS configurations, as shown in FIG. 1. Therefore, the terms “DMRS ports,” “logic ports,” and “antenna ports” may be used interchangeably in the following description of the present disclosure. On the other hand, the original “virtual ports,” based on the received DMRS REs, may refer to a multiplied combination of the “logic ports” based on the OCC. In other words, the original “virtual ports” may include combined channel estimation for both the serving UE and the interference UE(s).

[0027] Further, the term “serving port” may be used to refer to a DMRS port that corresponds to a serving UE, whereas the term “interference port” may be used to refer to a DMRS port associated with a UE other than the serving UE, i.e., an interference UE.

[0028] As shown in FIG. 1, in the type 1, antenna ports 1000 and 1001 may use odd- numbered subcarriers in the frequency domain and are separated from each other by multiplying different length-2 OCC in the frequency domain, thereby transmitting two orthogonal reference signals for the two antenna ports at a time instant.

[0029] Generally speaking, for a subcarrier at frequency tone z, a channel matrix for virtual ports, corresponding to all the antenna ports, can be expressed by:

U — ’ ^oij ij j eantenna ports

(2), where oy denotes an OCC corresponding to antenna port j at tone z, h_Lj denotes a channel estimation for antenna port j at tone z, and j belongs to all the antenna ports.

[0030] When the MU-MIMO is enabled, interference ports are mixed with serving ports due to the use of the OCC. Therefore, the channel matrix will include the components of all the antenna ports, including the serving ports and the interference ports, according to Equation (2). Under that circumstance, the channel estimation for the serving UE cannot be obtained directly based on the channel matrix

in Equation (2).

[0031] To address one or more of the above challenges, some approaches proposed channel estimation by using filters. Among them, in one approach, once the DMRS is received, a 2- dimensional (2D) Wiener filter may be used on each RB of the DMRS in the frequency domain. The purpose of the Wiener filter is to limit the frequency of the filtering operation within the frequency boundary of the RB, in an attempt to increase the accuracy of channel estimation. Due to the limited length, however, the channel estimation using the Wiener filter needs to be individually performed for each RB. As a result, the performance of this approach is relatively poor.

[0032] In view of this and other issues in the art, the present disclosure exploits a WB channel estimation scheme where the components of interference ports may be removed from the original virtual ports in advance of the channel estimation. Consequently, various WB channel estimation methods, such as direct Fourier Transform -based channel estimation, can be directly applied to the serving ports as obtained. Therefore, the performance of the system can be substantially enhanced. Additional details of the WB channel estimation scheme according to some embodiments of the present disclosure are provided below in connection with FIGs. 2-5.

[0033] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some implementation of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment (UE) 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that UE 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0034] Access node 204 may be a device that communicates with UE 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to UE 202, a wireless connection to UE 202, or any combination thereof. Access node 204 may be connected to UE 202 by multiple connections, and UE 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with UE 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with UE 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0035] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0036] Core network element 206 may serve access node 204 and UE 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between UE 202 and the 5GC. Generally, the AMF provides quality-of- service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0037] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from UE 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 may provide additional examples of possible user equipments, and router 214 may provide an example of another possible access node.

[0038] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0039] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is UE 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[0040] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to UE 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0041] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0042] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0043] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0044] In some embodiments, a suitable node of wireless network 200 (e.g., UE 202) in FIG. 2 can implement the WB channel estimation scheme at the downlink, according to some implementations of the present disclosure. In accordance with the scope of the present disclosure, the interference ports can be accurately identified and removed in advance of the channel estimation. Accordingly, various channel estimation methods, such as direct Fourier Transformbased channel estimation, can be directly applied to the serving ports as obtained. It can be expected that the throughput of the system can be substantially increased.

[0045] FIG. 4 illustrates a block diagram of an exemplary apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some implementations of the present disclosure. Apparatus 400 may be implemented as UE 202 of wireless network 200 in FIG. 2. As shown in FIG. 4, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 may be implemented by processor 302 and memory 304, and RF chip 404 may be implemented by processor 302, memory 304, and transceiver 306, as described above with respect to FIG. 3. Besides the on-chip memory (also known as “internal memory,” e.g., registers, buffers, or caches), on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4, it is understood that in some examples, baseband chip 402 and RF chip 404 may be integrated as one SoC; in still some examples, baseband chip 402 and host chip 406 may be integrated as one SoC; in other examples, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC, as described above.

[0046] In the uplink, host chip 406 may generate raw data and send the data to baseband chip 402 for encoding, modulation, and mapping. An interface unit (not shown) of baseband chip 402 may be configured to receive the data from host chip 406. Baseband chip 402 may also be configured to access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via the interface unit. RF chip 404, through a transmitter TX, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or samplerate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by transmitter TX of RF chip 404.

[0047] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device in the network. The RF signals may be passed to a receiver RX of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402.

[0048] In the downlink, baseband chip 402 may include a wideband (WB) channel estimation unit 4022 and a demodulation unit 4024, as depicted in FIG. 4, to arrive at the proposed WB channel estimation scheme. In accordance with the scope of the present disclosure, WB channel estimation unit 4022 may be configured to perform port detection based on the DMRS as received. Further, WB channel estimation unit 4022 may reconstruct virtual ports according to the port detection. Based on the reconstructed virtual ports, WB channel estimation unit 4022 may perform channel estimation for a serving UE. Subsequently, demodulation unit 4024 may perform demodulation based on the channel estimation of the serving UE.

[0049] WB channel estimation unit 4022 can be implemented as hardware, firmware, software, or any combination thereof, depending upon the particular application and design constraints imposed on the overall system. In some embodiments, WB channel estimation unit 4022 may be embodied by memory 304 and processor 302, as shown in FIG. 3. Processor 302 can be a baseband processor. Memory 304 may be an on-chip memory 4026 locally in baseband chip 402 and configured to store instructions regarding functions according to some embodiments of the present disclosure. If implemented in software, the functions may be stored on or encoded as instructions or codes on a non-transitory computer-readable medium. Computer-readable media may include computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0050] In still some embodiments, at least part of WB channel estimation unit 4022 may be implemented as hardware. In other words, at least a portion of the functions can be done by a hardware implementation using a physical device or an electronic circuit. The hardware implementation is usually faster in operation and may include, e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), or the like.

[0051] Baseband chip 402 may further include other functional units configured to perform other functions. In some embodiments, baseband chip 402 may further include a routine channel estimation circuit (not shown). The channel estimation circuit may include, e.g., a discrete Fourier transform (DFT) circuit, an inverse discrete Fourier transform (IDFT) circuit, a filter, a noise estimation circuit, etc., and may be configured to receive reference signals for regular channel estimation. The channel estimation circuit may transmit channel estimation signals to demodulation unit 4024 for subsequent processing. WB channel estimation unit 4022 can be compatible with the routine channel estimation circuit. WB channel estimation unit 4022 may share a portion of components from the channel estimation circuit or may be a part of the channel estimation circuit. In still some embodiments, WB channel estimation unit 4022 may be a standalone unit, separate from the routine channel estimation circuit, as shown in FIG. 4.

[0052] FIG. 5 illustrates a block diagram of an exemplary wideband (WB) channel estimation unit 4022, according to some implementations of the present disclosure. FIG. 6 illustrates a flow chart of an exemplary method of WB channel estimation, according to some embodiments of the present disclosure. Additional details of the operations performed by WB channel estimation unit 4022 are provided below in connection with FIGs. 5 and 6.

[0053] Referring to FIG. 5, WB channel estimation unit 4022 may include a port detection module 502, an interference port channel estimation module 504, a virtual port reconstruction module 506, and an adder 508. Operations of these modules in FIG. 5 will be described with reference to FIG. 6.

[0054] WB channel estimation unit 4022 may be configured to receive DMRS resource elements as inputs. A resource element (RE) is the smallest discrete part of a DMRS signal, as annotated in FIG. 1, which is in one subcarrier by one symbol. An RE can serve as the unit for identifying enabled ports for one subcarrier. An RE may include a single value that represents the data from the DMRS signal. Multiple REs can aggregate into one RB, as shown in FIG. 1, and thus an RB includes multiple subcarriers by multiple symbols.

[0055] At 602 in FIG. 6, at each tone, port detection module 502 may detect which antenna ports are enabled in one RB for one subcarrier, based on the received DMRS REs. The configurations of interference ports may be different for different RBs. For example, some RBs may only include one interference port, but with different port indices, while other RBs may include multiple interference ports. Accordingly, port detection module 502 may be configured to identify the enabled antenna ports in each RB.

[0056] In some embodiments, a de-OCC (de-orthogonal cover code) algorithm may be applied, e.g., in port detection module 502. More specifically, a de-OCC operation may be performed on the original virtual port to get a raw channel for all enabled antenna ports. As described above, the original virtual port may represent the multiplied combination of the enabled antenna ports with the OCC. The de-OCC operation is an inverse (opposite) operation of the OCC operation. By employing the de-OCC, the effect of the OCC can be removed. In some embodiments, WB channel estimation unit 4022 may be configured to receive OCC information from, e.g., a base station. The OCC information may indicate an OCC operation that was performed on the received DMRS REs. The de-OCC operation may be obtained based on an inverse of the OCC operation.

[0057] The term “enabled port” as used herein may refer to an open port that receives the DMRS. Based on the enabled ports, a threshold may be pre-set to identify the interference ports. By comparing at least one of the power or the signal -to-noise ratio (SNR) associated with each enabled port to the pre-set threshold(s), it may be determined which interference ports indeed exist. [0058] In accordance with the scope of the present disclosure, port detection module 502 may apply techniques other than the de-OCC technique to identify the interference ports, and the present disclosure does not limit thereto. [0059] Further, at 604 in FIG. 6, interference port channel estimation module 504 may perform channel estimation for each interference port as obtained. In some embodiments, a moving average estimator, a minimum mean square error (MMSE) estimator, a least-square (LS) estimator, or the like may be imposed on the interference ports to obtain the channel estimation for each interference port. These estimators may be respectively configured to minimize an estimation error of the channel based on different indices. For example, the MMSE estimator may estimate the channel to minimize the mean square error (MSE) of the updated channel. Now that each interference port is distinguished, any suitable channel estimation method may be applied at 604 in FIG. 6, and the present disclosure does not limit thereto.

[0060] At 606 in FIG. 6, based on only the interference ports, virtual port reconstruction module 506 may reconstruct a new virtual port (i.e., combined channel estimation based on the interference ports only and their corresponding OCCs). That is, once the channel estimation for each interference port is available, for a subcarrier at tone z, the new virtual port for only the interference ports (denoted as vlt) can be obtained by:

(3), where o,k denotes an OCC corresponding to antenna port k at tone z, h_ik denotes the channel estimation for interference port k at tone z, and k includes only the interference ports.

[0061] As used herein, the term “reconstruct” or “reconstruction” may refer to a combination of multiplying the channel estimation for each interference port with a corresponding OCC of the interference port. Further, the term “virtual port” may be used to refer to combined channel estimation based on a raw channel and its corresponding OCC in a reconstruction.

[0062] An original virtual port that represents the estimation of the channel based on the OCC may be obtained based on the received DMRS. As described above, the original virtual port is composed of the components from both the interference ports and the serving ports. Accordingly, the impact of the interference ports is required to be removed from the original virtual ports in Equation (2), such that the channel estimation for the serving ports can be obtained. At 608 in FIG. 6, for that purpose, adder 508 may be configured to perform a removing operation. That is, the reconstructed virtual ports based on the interference ports can be subtracted from the original virtual port to obtain the channel estimation for the serving ports. At tone z, the virtual port that is composed only of the serving ports vS_t can be expressed as: vSt = v_i - vl_i (4), where vl denotes the new virtual port reconstructed on only the interference ports according to Equation (3), and

denotes the original virtual port based on the received DMRS.

[0063] Subsequently, at 610 in FIG. 6, the channel estimation composed only of the serving ports, denoted as vS_t, can be obtained. Demodulation unit 4024 may receive the channel estimation based on the serving ports only, the channel estimation based on the interference ports only, and the port information to perform demodulation at 620 in FIG. 6.

[0064] In some embodiments, an iteration may be applied to the WB channel estimation scheme as described above to improve its accuracy. FIG. 7 illustrates a block diagram of another exemplary WB channel estimation unit, according to some implementations of the present disclosure. Similar to the illustration in FIG. 5, WB channel estimation unit 4022 in FIG. 7 may include a port detection module 502, an interference port channel estimation module 504, a first virtual port reconstruction module 506, and a first adder 508. Based on the structure, configuration, and functions of WB channel estimation unit in FIG. 5, WB channel estimation unit 4022 in FIG. 7 may further include a second virtual port reconstruction module 702 and a second adder 704.

[0065] In some embodiments, with respect to FIG. 7, first virtual port reconstruction module 506 and first adder 508 may be identical to second virtual port reconstruction module 702 and second adder 704. By suitable internal wiring within WB channel estimation unit 4022, first virtual port reconstruction module 506 and first adder 508 may be reused as second virtual port reconstruction module 702 and second adder 704 to reduce hardware implementation. In some embodiments, first virtual port reconstruction module 506 and first adder 508 may be different from second virtual port reconstruction module 702 and second adder 704.

[0066] Once the channel estimation for each serving port is obtained, it can be used iteratively to obtain a more accurate virtual port for only the interference ports. Returning to FIG. 6, at 612 in FIG. 6, a new virtual port for the serving ports only may be reconstructed at second virtual port reconstruction module 702.

[0067] Further, at 614 in FIG. 6, the reconstructed virtual ports for the serving ports may be subtracted from the original virtual ports. For that purpose, second adder 704 may be configured to perform an adding operation. Therefore, a new virtual port composed only of the interference ports, denoted as vl^, can be obtained as: vli,i = v_t - vS_{i 0} (5), where V[ denotes the original virtual ports, and vS_{i 0} denotes the reconstructed virtual port for the serving ports only.

[0068] The new virtual port composed of only the interference ports (vl^) according to Equation (5) can have more accuracy as opposed to that of Equation (3) because the new virtual port in Equation (5) may have less interference from the serving ports. Accordingly, instead of using the virtual port for the interference ports

based on Equation (3), the new virtual port for the interference ports vI_{L 1} based on Equation (5) can be used for the demodulation at demodulation unit 4024.

[0069] It can be understood that although FIG. 7 illustrates only one iteration, in other embodiments, more iterations may be implemented to WB channel estimation unit 4022. At a second iteration, another new virtual port for the serving ports can be obtained by: vS_{t l} = v_t - vl_til (6), denotes the original virtual port, and vl^ denotes the channel estimation for the serving ports obtained at the first iteration. Demodulation may be performed based on the new virtual port for the serving ports according to Equation (6) and the new virtual port for the interference ports according to Equation (5) to reduce channel estimation error.

[0070] Generally speaking, virtual ports for the serving ports and the interference ports at multiple levels can be expressed, respectively, as: vl_iik = Vi ~ vS_i>k-1 (7), and vSi,k = v_t - vl_iik (8), is the original virtual port, and vl_{i k} is the channel estimation for the interference ports obtained at 2k- 1 iterations, and vS_{i k} is the channel estimation for the serving ports obtained at 2k iterations. Based on the iterations, the virtual port for the serving ports and the interference ports as obtained may approach their real values.

[0071] As described above, when the MU-MIMO is enabled, the interference ports are mixed with the serving ports due to the use of the OCC. Under that circumstance, the channel estimation for the serving UE cannot be obtained directly from the channel matrix

in Equation (2). Accordingly, the present disclosure exploits the WB channel estimation scheme where the interference ports may be removed from the virtual port. Consequently, various WB channel estimation methods, such as direct Fourier Transform -based channel estimation, can be directly applied. Therefore, the performance of the system can be substantially enhanced.

[0072] According to one aspect of the present disclosure, a baseband is provided. The baseband chip includes a processor and memory coupled to the processor and storing instructions. The processor is configured to identify one or more interference ports using a de-orthogonal cover code (de-OCC) operation on an original virtual port. The original virtual port is obtained based on a demodulation reference signal (DMRS). The de-OCC operation is an inverse of an orthogonal cover code (OCC) operation. A virtual port for the one or more interference ports is reconstructed based on the OCC operation and the one or more interference ports. Channel estimation for one or more serving ports is obtained based on the virtual port for the one or more interference ports.

[0073] In some embodiments, the processor is further configured to obtain the OCC operation performed on the DMRS.

[0074] In some embodiments, the processor is further configured to identify one or more enabled ports using the de-OCC operation on each of DMRS resource elements (REs); and identify the one or more interference ports based on the one or more enabled ports. The DMRS includes the DMRS REs

[0075] In some embodiments, the processor is further configured to obtain at least one of power or signal -to-noise ratio (SNR) associated with each of the one or more enabled ports; and identify the one or more interference ports based on the at least one of power or SNR.

[0076] In some embodiments, the processor is further configured to obtain the channel estimation for the one or more serving ports by removing the virtual port for the one or more interference ports from the original virtual port.

[0077] In some embodiments, the processor is further configured to perform demodulation based on the channel estimation for the one or more serving ports.

[0078] In some embodiments, the processor is further configured to perform channel estimation for each of the one or more interference ports; and reconstruct the virtual port for the one or more interference ports based on the channel estimation for each of the one or more interference ports.

[0079] In some embodiments, the processor is further configured to perform a multiplication operation on each of the one or more interference ports and a corresponding OCC of the interference port to reconstruct the virtual port for the one or more interference ports.

[0080] In some embodiments, the channel estimation for the one or more interference ports is first channel estimation. The processor is further configured to reconstruct a virtual port for the one or more serving ports based on the channel estimation for the one or more serving ports; and obtain second channel estimation for the one or more interference ports based on the virtual port for the one or more serving ports.

[0081] In some embodiments, the processor is further configured to perform a multiplication operation on the channel estimation for each of the one or more serving ports and a corresponding OCC of the serving port to reconstruct the virtual port for the one or more serving ports.

[0082] In some embodiments, the processor is further configured perform demodulation based on the channel estimation for the one or more serving ports and the second channel estimation for the one or more interference ports.

[0083] According to one aspect of the present disclosure, another baseband chip is provided. The baseband chip includes a processor and memory coupled to the processor and storing instructions. The processor is configured to identify one or more interference ports using a de- orthogonal cover code (de-OCC) operation on an original virtual port. The original virtual port is obtained based on a demodulation reference signal (DMRS). The de-OCC operation is an inverse of an orthogonal cover code (OCC) operation. A first virtual port for the one or more interference ports is reconstructed based on the one or more interference ports and the OCC operation. A second virtual port for one or more serving ports is reconstructed based on the first virtual port. Channel estimation for the one or more interference ports is obtained based on the second virtual port.

[0084] In some embodiments, the channel estimation is first channel estimation. The processor is configured to perform second channel estimation for each of the one or more interference ports; and reconstruct the first virtual port for the one or more interference ports based on the second channel estimation for each of the one or more interference ports.

[0085] In some embodiments, the processor is further configured to: obtain channel estimation for the one or more serving ports based on the first virtual port; and reconstruct the second virtual port for the one or more serving ports based on the channel estimation for the one or more serving ports.

[0086] In some embodiments, the first virtual port is a multiplied combination of the second channel estimation for each of the one or more interference ports and a corresponding OCC of the interference port. The second virtual port is a multiplied combination of the channel estimation for each of the one or more serving ports and a corresponding OCC of the serving port. [0087] In some embodiments, the processor is further configured to perform demodulation based on the first channel estimation for the one or more interference ports and the channel estimation for the one or more serving ports.

[0088] According to one aspect of the present disclosure, a method of wideband channel estimation is provided. One or more interference ports are identified using a de-orthogonal cover code (de-OCC) operation on an original virtual port. The original virtual port is obtained based on a demodulation reference signal (DMRS). The de-OCC operation is an inverse of an OCC operation. A virtual port for the one or more interference ports is reconstructed based on the one or more interference ports and the OCC operation. Channel estimation for one or more serving ports is obtained based on the virtual port for the one or more interference ports.

[0089] In some embodiments, obtaining the channel estimation for the one or more serving ports based on the virtual port for the one or more interference ports includes removing the virtual port for the one or more interference ports from the original virtual port to obtain the channel estimation for the one or more serving ports.

[0090] In some embodiments, the method further includes performing channel estimation for each of the one or more interference ports. Reconstructing the virtual port for the one or more interference ports includes performing a multiplication operation on each of the one or more interference ports and a corresponding OCC of the interference port to reconstruct the virtual port for the one or more interference ports.

[0091] In some embodiments, the channel estimation for the one or more interference ports is first channel estimation. The method further includes reconstructing a virtual port for the one or more serving ports based on the channel estimation for the one or more serving ports; and obtaining second channel estimation for the one or more interference ports based on the virtual port for the one or more serving ports.

[0092] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0093] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0094] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. [0095] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. [0096] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A baseband chip, comprising: a processor; and memory coupled to the processor and storing instructions that, when executed by the processor, cause the processor to: identify one or more interference ports using a de-orthogonal cover code (de-OCC) operation on an original virtual port, the original virtual port being obtained based on a demodulation reference signal (DMRS), and the de-OCC operation being an inverse of an orthogonal cover code (OCC) operation; reconstruct a virtual port for the one or more interference ports based on the OCC operation and the one or more interference ports; and obtain channel estimation for one or more serving ports based on the virtual port for the one or more interference ports.

2. The baseband chip of claim 1, wherein the processor is further configured to: obtain the OCC operation performed on the DMRS.

3. The baseband chip of claim 1, wherein the processor is further configured to: identify one or more enabled ports using the de-OCC operation on each of DMRS resource elements (REs), the DMRS comprising the DMRS REs; and identify the one or more interference ports based on the one or more enabled ports.

4. The baseband chip of claim 3, wherein the processor is further configured to: obtain at least one of power or signal -to-noise ratio (SNR) associated with each of the one or more enabled ports; and identify the one or more interference ports based on the at least one of power or SNR.

5. The baseband chip of claim 1, where the processor is further configured to: obtain the channel estimation for the one or more serving ports by removing the virtual port for the one or more interference ports from the original virtual port.

6. The baseband chip of claim 5, wherein the processor is further configured to: perform demodulation based on the channel estimation for the one or more serving ports.

7. The baseband chip of claim 1, wherein the processor is further configured to: perform channel estimation for each of the one or more interference ports; and reconstruct the virtual port for the one or more interference ports based on the channel estimation for each of the one or more interference ports.

8. The baseband chip of claim 7, wherein the processor is further configured to: perform a multiplication operation on each of the one or more interference ports and a corresponding OCC of the interference port to reconstruct the virtual port for the one or more interference ports.

9. The baseband chip of claim 7, wherein: the channel estimation for the one or more interference ports is first channel estimation; and the processor is further configured to: reconstruct a virtual port for the one or more serving ports based on the channel estimation for the one or more serving ports; and obtain second channel estimation for the one or more interference ports based on the virtual port for the one or more serving ports.

10. The baseband chip of claim 9, wherein the processor is further configured to: perform a multiplication operation on the channel estimation for each of the one or more serving ports and a corresponding OCC of the serving port to reconstruct the virtual port for the one or more serving ports.

11. The baseband chip of claim 9, wherein the processor is further configured: perform demodulation based on the channel estimation for the one or more serving ports and the second channel estimation for the one or more interference ports.

12. A baseband chip, comprising: a processor; and memory coupled to the processor and storing instructions that, when executed by the processor, cause the processor to: identify one or more interference ports using a de-orthogonal cover code (de-OCC) operation on an original virtual port, the original virtual port being obtained based on a demodulation reference signal (DMRS), and the de-OCC operation being an inverse of an orthogonal cover code (OCC) operation; reconstruct a first virtual port for the one or more interference ports based on the one or more interference ports and the OCC operation; reconstruct a second virtual port for one or more serving ports based on the first virtual port; and obtain channel estimation for the one or more interference ports based on the second virtual port.

13. The baseband chip of claim 12, wherein: the channel estimation is first channel estimation; and the processor is configured to: perform second channel estimation for each of the one or more interference ports; and reconstruct the first virtual port for the one or more interference ports based on the second channel estimation for each of the one or more interference ports.

14. The baseband chip of claim 13, wherein the processor is further configured to: obtain channel estimation for the one or more serving ports based on the first virtual port; and reconstruct the second virtual port for the one or more serving ports based on the channel estimation for the one or more serving ports.

15. The baseband chip of claim 14, wherein: the first virtual port is a multiplied combination of the second channel estimation for each of the one or more interference ports and a corresponding OCC of the interference port; and the second virtual port is a multiplied combination of the channel estimation for each of the one or more serving ports and a corresponding OCC of the serving port.

16. The baseband chip of claim 15, wherein the processor is further configured to: perform demodulation based on the first channel estimation for the one or more interference ports and the channel estimation for the one or more serving ports.

17. A method of wideband channel estimation, comprising: identifying one or more interference ports using a de-orthogonal cover code (de-OCC) operation on an original virtual port, the original virtual port being obtained based on a demodulation reference signal (DMRS), and the de-OCC operation being an inverse of an orthogonal cover code (OCC) operation; reconstructing a virtual port for the one or more interference ports based on the one or more interference ports and the OCC operation; and obtaining channel estimation for one or more serving ports based on the virtual port for the one or more interference ports.

18. The method of claim 17, wherein: obtaining the channel estimation for the one or more serving ports based on the virtual port for the one or more interference ports comprises removing the virtual port for the one or more interference ports from the original virtual port to obtain the channel estimation for the one or more serving ports.

19. The method of claim 17, further comprising: performing channel estimation for each of the one or more interference ports, wherein reconstructing the virtual port for the one or more interference ports comprises performing a multiplication operation on each of the one or more interference ports and a corresponding OCC of the interference port to reconstruct the virtual port for the one or more interference ports.

20. The method of claim 19, wherein: the channel estimation for the one or more interference ports is first channel estimation; and the method further comprises: reconstructing a virtual port for the one or more serving ports based on the channel estimation for the one or more serving ports; and obtaining second channel estimation for the one or more interference ports based on the virtual port for the one or more serving ports.