WO2023287415A1

WO2023287415A1 - Apparatus and method for low power channel estimation

Info

Publication number: WO2023287415A1
Application number: PCT/US2021/041691
Authority: WO
Inventors: Jian Gu
Original assignee: Zeku, Inc.
Priority date: 2021-07-14
Filing date: 2021-07-14
Publication date: 2023-01-19

Abstract

According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include an interface unit configured to receive a first signal and a second signal. The first signal and the second signal may have the same bit-width. The baseband chip may also include a demodulation circuit configured to demodulate the first signal and the second signal. The baseband chip may also include a first path configured to perform a first channel estimation of the first signal. The baseband chip may also include a second path. The second path may be configured to generate a reduced bit-width difference signal of the first signal and the second signal. The second path may also be configured to perform a second channel estimation of the reduced bit-width difference signal.

Description

APPARATUS AND METHOD FOR LOW POWER CHANNEL ESTIMATION BACKGROUND [0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication. [0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various for channel estimation using reference signals. SUMMARY [0003] Embodiments of apparatus and method for channel estimation are disclosed herein. [0004] According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include an interface unit configured to receive a first signal and a second signa. The first signal and the second signal may have the same bit-width. The baseband chip may also include a demodulation circuit configured to demodulate the first signal and the second signal. The baseband chip may also include a first path configured to perform a first channel estimation of the first signal. The baseband chip may also include a second path. The second path may be configured to reduce the bit-width of a difference signal of the first signal and the second signal. The second path may also be configured to perform a second channel estimation of the reduced bit-width difference signal. [0005] According to one aspect of the present disclosure, an apparatus for wireless communication is disclosed. The apparatus may include a memory and at least one processor. The at least one processor may be configured to receive a first signal and a second signal. The first signal and the second signal may have the same bit-width. The at least one processor may be further configured to demodulate the first signal and the second signal. The at least one processor may be further configured to perform a first channel estimation of the first signal. The at least one processor may be further configured to reduce the bit-width of a difference signal of the first signal and the second signal. The at least one processor may be further configured to perform a second channel estimation of the reduced bit-width second signal. [0006] According to one aspect of the present disclosure, a method of wireless communication is disclosed. The method may include receiving, by an interface unit, a first signal and a second signal. The first signal and the second signal may have a same bit-width. The method may further include demodulating, by a demodulation circuit, the first signal and the second signal. The method may further include performing, by a first path, a first channel estimation of the first signal. The method may further include reducing, by a second path, the bit-width of a difference signal of the first signal and the second signal. The method may further include performing, by the second path, a second channel estimation of the reduced bit-width difference signal. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0008] FIG.1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure. [0009] FIG.2 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure. [0010] FIG.3A illustrates a detailed view of a reduced bit-width channel estimation circuit of the baseband chip of FIG.2, according to some embodiments of the present disclosure. [0011] FIG. 3B illustrates a constellation diagram of reference signals and data REs, according to some embodiments of the present disclosure. [0012] FIG.4 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure. [0013] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure. [0014] FIG.6 illustrates an example channel estimation circuit. [0015] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION [0016] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. [0017] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. [0018] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0019] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system. [0020] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. [0021] Important considerations in the field of wireless communication relate to channel estimation using reference signals. Conventional channel estimation may include the following operations: 1) reference signal (RS) demodulation, 2) RS filtering, and 3) interpolation to obtain a channel estimation for data REs. [0022] FIG.6 illustrates a block diagram of a conventional channel estimation circuit 600. Conventional channel estimation circuit 600 of FIG. 6 may include, e.g., an RS demodulation circuit 602, an RS filtering circuit 604, and an interpolation circuit 606. An RS received by a baseband chip may be inputted into RS demodulation circuit 602. Once the RS is demodulated, it may be input into RS filtering circuit 604. [0023] RS filtering circuit 604 may apply one or more filters to filter the RS in the frequency domain and/or the time domain. One function of RS filtering circuit 604 is to obtain a filtered RS, which may increase the accuracy of channel estimation for data REs. The filtered RS may be input into interpolation circuit 606. Interpolation circuit 606 is used to obtain an estimated channel of data REs or a subcarrier. Based on this estimated channel, a baseband chip may decode/demodulate data REs. [0024] RS filtering circuit 604 may use one 2D filter or two 1D filters. A 2D filter may include a 2D Wiener filter or a 2D singular value decomposition (SVD) filter, by way of example. [0025] The 2D Wiener filter may estimate the RS channel as follows, where 2D Wiener

filter outputs a channel estimation for an RS in symbol k:

where is an autocorrelation function of received signal

is a vector, is a

vector and denotes received signal at symbol k.

is a cross correlation function between received signal y and reference signal

_, in symbol k .

[0026] The 2D SVD filter may estimate the RS channel as follows, by first applying

SVD for autocorrelation function :

where is a unitary matrix containing the singular vectors and

is a diagonal matrix containing the singular values

_. The output of the SVD filter may be given by:

where is a diagonal matrix with entries:

[0027] On the other hand, two ID channel estimation filtering includes first performing frequency domain filtering and then time domain filtering. In other words, the frequency domain filter and the time domain filtering are separated, which lowers computational complexity as compared with 2D filtering described above. There are multiple known algorithms that perform frequency domain filtering. These frequency domain filters include, e.g., Wiener filter, Fast Fourier Transform (FFT) filter, and SVD based filter, etc.

[0028] A ID frequency domain Wiener filter for an RS channel estimation can be given

by:

where is frequency direction autocorrelation function of received signal

,

is a vector and denotes received signal at symbol k. is cross

correlation function between received signal

and reference signal in symbol

.

[0029] FFT based frequency domain filter for RS channel estimation

may be given by:

where is an FFT function, is an inverse FFT (iFFT) function, is a filter weight

applied at symbol k . [0030] When SVD based filter is used, a 1D SVD for autocorrelation function

is first used:

where is a unitary matrix containing the singular vectors and is a diagonal matrix

containing the singular values

_. [0031] The output of the 1D SVD filter is given by:

where is a diagonal matrix with entries

[0032] After 1D frequency domain filtering is performed using any of the above-described 1D frequency domain filters, time domain filtering (e.g., Infinite Impulse Response (IIR) filter or Finite Impulse Response (FIR) filter) may be performed using a linear filter

Here, then the estimated channel

can be given by:

where

[0033] After RS filtering circuit 604 performs RS channel estimation by 1D or 2D filtering, interpolation circuit 606 may interpolate the estimated RS channel to obtain an estimated data resource element (RE) channel. There are different interpolation techniques that may be used, e.g., such as non-linear interpolation and linear interpolation. Non-linear interpolation for an estimated data RE channel may be denoted as:

where is interpolation function for RE (kl).

[0034] On the other hand, interpolation for an estimated data RE channel using linear

interpolation may be denoted as:

where is filter coefficient for resource element (kl).

[0035] As seen above, for both the 2D and 1D scenarios, filtering and interpolation are complex computations, and RS filtering circuit 604 and interpolation circuit 606 must perform an undesirable number of multiplications to obtain an estimated data RE channel. This level of computational complexity uses an undesirable amount of power. [0036] Thus, there is an unmet need for a technique to estimate a data RE channel that is less complex and uses fewer multiplications in order to reduce power consumption. [0037] To overcome these challenges, the present disclosure exploits high correlation fading channel scenarios to reduce the complexity of channel estimation and lower power consumption. For example, when a user equipment (UE) is stationary, the correlation between fading channels is high, which means the correlation between adjacent symbols and/or REs is also high, especially when Doppler is low or delay spread is low. That is, in high correlation scenarios, the difference between a first signal and a second signal may have a small dynamic range. Due to the small dynamic range, the present disclosure determines a difference between the first and second signals and then reduces the bit-width of the difference signal prior to performing channel estimation. Digital signal processing of a reduced bit-width signal may consume significantly less power than digital signal processing of the second signal, which has a larger bit-width. Additional details of the channel estimation technique of the present disclosure is provided below in connection with FIGs.1-5. [0038] FIG.1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation. [0039] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation. [0040] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., S1 interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless. [0041] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides quality-of-service (QoS) flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides UE IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a Streaming Service, and/or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation. [0042] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node. [0043] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack. [0044] Each element in FIG.1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG.5. Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG.1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible. [0045] Transceiver 506 may include any suitable device for sending and/or receiving data. Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well. [0046] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0047] As shown in FIG.5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro- electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. [0048] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0049] Referring back to FIG. 1, in some embodiments, any suitable node of wireless network 100 (e.g., user equipment 102) may exploit high correlation fading channel scenarios to reduce the complexity of computations used for channel estimation, thereby limiting power consumption. For example, when user equipment 102 is stationary, the correlation between fading channels is high, which means the correlation between adjacent symbols and/or REs is also high, especially when Doppler is low or delay spread is low. More specifically, in high correlation scenarios, the difference between a first signal and a second signal may have a small dynamic range. Due to the small dynamic range, the present disclosure determines a difference between the first and second signal and then reduces the bit-width of the difference signal prior to performing channel estimation. Digital signal processing of a reduced bit-width signal may consume significantly less power than if user equipment 102 were to perform digital signal processing of the second signal, which has a larger bit-width. [0050] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip 202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be implemented as user equipment 102 of wireless network 100 in FIG.1. As shown in FIG.2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG.5. Besides the on-chip memory 218 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG.2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above. [0051] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Interface unit 214 of baseband chip 202 may receive the data from host chip 206. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204 via interface unit 214. RF chip 204, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204. [0052] In the downlink, antenna 210 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202. [0053] As seen in FIG. 2, baseband chip 202 may include a reduced bit-width channel estimation circuit 216 (hereinafter “channel estimation circuit 216”). Channel estimation circuit 216 may exploit high correlation fading channel scenarios to reduce the complexity of computations used to perform channel estimation and lower power consumption. For example, when apparatus 200 is stationary, the correlation between fading channels is high, which means the correlation between adjacent symbols and/or REs is also high, especially when Doppler is low or delay spread is low. More specifically, in high correlation scenarios, the difference between a first signal and a second signal may have a small dynamic range. In such instances, the bit-width of the difference between the first signal and the second signal (difference signal) may be reduced at channel estimation circuit 216 before it performs channel estimation is performed. Digital signal processing of a reduced bit-width signal may use significantly less power than using a full bit- width second signal. Additional details of the operations performed by channel estimation circuit 216 are provided below in connection with FIGs.3A, 3B, and 4. [0054] FIG. 3A illustrates a detailed view of the reduced bit-width channel estimation circuit 216 of FIG.2, according to some embodiments of the present disclosure. FIG.3B illustrates a constellation diagram 300 of reference signals and data REs, according to some embodiments of the present disclosure. FIGs.3A and 3B will be described together. [0055] Referring to FIG.3A, channel estimation circuit 216 may include a first circuit path (hereinafter “first path”) in which a first signal (full bit-width signal) is filtered and interpolated to obtain a first estimated channel for data REs, and a second circuit path (hereinafter “second path”) in which a difference signal (difference between first and second signal) with a reduced bit-width is filtered and interpolated to obtain a second estimated channel for data REs. The first path may include, e.g., RS demodulation circuit 302, a first difference calculation circuit 304, a first filtering circuit 306, a first combination circuit 308, a second difference calculation circuit 310, a first interpolation circuit 312, and a second combination circuit 314. The second path may include, e.g., a first bit-width reduction circuit 316, a second filtering circuit 318, a second bit-width reduction circuit 320, and a second interpolation circuit 322. Once the processing along the first path and the second path is complete, the first estimated channel and the second estimated channel may be combined to obtain a final channel estimation for data REs. Different techniques may be used by first difference calculation circuit 304 and second filtering circuit 318 depending on the scenario, as described below. However, in any scenario, to begin, RS demodulation circuit 302 may receive the first signal and the second signal from interface unit 214. [0056] In an embodiment for low delay spread, correlation in the frequency direction is high. Here, first difference calculation circuit 304 may convert the received second signal in symbol n (denoted as

into:

where is a

all-one vector,

is fixed for symbol can have different

implementations, e.g., such as when

is the mean of received symbol n, i.e.,

or a signal of a fixed

, where K0 is the index of used RE. Difference signal has

much smaller dynamic range than . Thus, when is sent to first bit-width reduction circuit

316, its bit-width may be reduced when the delay spread is low. [0057] Once the bit-width of the difference signal _{is reduced, second filtering circuit}

318 may perform filtering. [0058] In some embodiments, second filtering circuit 318 may apply a 2D filter to _{. The}

2D filter may be described by:

where for a 2D Wiener filter and for a 2D SVD filter;

may include a vector with reduced bit width; and

may be a vector with the same width as

. Thus, using this 2D filter, the

computational complexity is reduced from

multiplications with full bit width to

multiplications with full bit width plus multiplications with

reduced bit width. [0059] In some embodiments, when the Doppler effect is low, first difference calculation circuit 304 may adjust symbol n of the received signal . First difference

calculation circuit 304 may change samples to one symbol of the first signal and K symbols of the difference between the first signal and the second signal per (K+1) symbols. K is Doppler dependent; for example, K is larger at smaller Doppler. Then the samples may become:

where means x mod y. Because of the high correlation between adjacent symbols,

has a very small dynamic range. Thus, a smaller bit-width can be used for

than . Thus, the

second RS channel can be estimated with lower power consumption. [0060] In some embodiments, second filtering circuit 318 may apply 2D wiener filter, which may be rewritten as follows:

where

where is a identity matrix and for

2-D Wiener filter; and for 2-D SVD filter.

[0061] Here

may be separated into two parts with different bit-widths. One part is the first signal with large bit width, and the other part is the difference between the first signal and the second signal and has smaller bit width. Different multipliers and adders with different bit widths can be used to calculate these two parts. [0062] In some embodiments, for low Doppler and low delay spread, some adjustments to the received symbol in symbol n may be made by either first

difference calculation circuit 304, first bit-width reduction circuit 316, or second filtering circuit 318. Here, the samples may be changed to one symbol of the first signal and K symbols of the difference between the first signal and the second signal per (K+1) symbols. Then the samples may become:

where mean x mod y. [0063] Because of the high correlation between adjacent symbols, has a very small

dynamic range, and a reduced bit-width can be used. Thus, using , channel estimation can be

performed with lower power consumption. [0064] In some embodiments, 2D Wiener filter or a 2D SVD filter may be applied. 2D filter may be rewritten as follows:

where for 2-D Wiener

filter; and for -D SVD filter.

[0065] Here,

may be separated into two parts. One part is the first signal with a large bit width, and the other part is the difference between the first signal and the second signal and has a smaller bit width. Different multipliers and adders with bit width to may be used by second filtering circuit 318 to calculate these two parts. [0066] In some embodiments, for low delay spread, second filter circuit 318 may apply

given by (Equation 1) to a 1D filter , where . The output of 1D

SVD filter may be rewritten as:

where is a

all-one vector, for 1D Wiener filter and

for 1-D SVD filter. has lower bit width than and . Therefore, this

embodiment lowers the complexity from M ² multiplications with full bit width to ^M multiplications with full bit width plus M ² multiplications with reduced bit width. [0067] In some embodiments, second filtering circuit 318 may use an FFT filter to estimate a second channel associated with the second signal. The FFT filter may be given by:

where has smaller bit-width than and . Here, operators with smaller bit-width may be

used, e.g., such as adders, multipliers and Radix in FFT and iFFT. [0068] After frequency direction filtering, a time direction filter may be applied by second filtering circuit 318. In some embodiments, a linear filter may be applied, then

the second estimated channel can be given by:

[0069] In some embodiments, for low Doppler, second filtering circuit 318 may apply

given by to a 1D filter. The

output of the 1D filter may be rewritten as:

where for 1-D wiener filter and for ID SVD filter.

[0070] Second filtering circuit 318 may estimate the second channel by applying an

FFT filter given by:

where has smaller bit-width in

symbols. Second filtering circuit 318 may use smaller bit-width, including adders, multipliers, and Radix in FFT and iFFT.

[0071] In some embodiments, after frequency direction filtering, a time direction filter may be applied. One embodiment is a linear filter . Here, the estimated second

channel may be given by:

where has smaller bit width in K of (K+l) symbols.

[0072] In some embodiments, for low delay spread and low Doppler, second filtering circuit 318 may apply to ID filter, where . The output of

the ID filter may be rewritten as:

Where is a all -one vector; for ID

Wiener filter; for 1-D SVD filter; and has lower bit width than and .

Therefore, this embodiment lowers the complexity of symbols from

multiplications with full bit width to multiplications with full bit width plus

multiplications with reduced bit width. [0073] Then, second filtering circuit 318 may apply an FFT filter given by:

where

[0074] Here,

has smaller bit-width than

and

. Second filtering circuit 318 may use operators with smaller bit-width, including adders, multipliers, and Radix in FFT and iFFT. [0075] After frequency direction filtering, a time direction filter may be applied. One embodiment may employ a linear filter . Here, may be given by:

where has smaller bit width in

symbols. [0076] Thus, using any one of the embodiments described above, second filtering circuit 318 may estimate a second channel associated with the second signal, but using a reduced bit-width difference signal, and hence, less power as compared to known approaches. [0077] First filtering circuit 306 may estimate a first channel of the first signal using the techniques described above in connection with second filtering circuit 318 and/or those techniques described above in connection with FIG. 6. Once estimated, first combination circuit 308 may combine the estimated first and second RS channels. Then, second difference calculation circuit 310 calculate a difference channel based on a comparison of the estimated first and second RS channels. The difference channel may be input into the second bit-width reduction circuit 320. Second bit-width reduction circuit 320 may reduce the bit-width of the difference channel to lower the complexity of computations performed by second interpolation circuit 322. [0078] Second interpolation circuit 322 may interpolate the difference channel to obtain an estimated channel for data REs. Second interpolation circuit 322 may use non-linear or linear interpretation. Using non-linear interpolation, the estimated channel for data may be

denoted as:

where is an interpolation function.

[0079] Referring to FIG. 3B, with linear interpolation, second interpolation circuit 322 may select a central data RE 305 denoted as in the middle of all surrounding data REs 303 and

reference signals 301. First interpolation circuit 312 may calculate the estimated channel for central data RE 305, and then calculate the estimated channel for the remaining data REs 303. For example, using linear interpolation, the estimated channel for central data REs 305 may

be given by:

where is filter coefficient for resource element . Once has been calculated, the

estimated channel for the remaining data REs 303 may be calculated by:

where has smaller dynamic range for which a smaller bit-width can be used

as compared with when Doppler or delay spread is small.

[0080] Because there are much more data REs 303 than central data RE 305, power consumption used to calculate may be higher than for calculating Using

may save power proportional to a ratio of bit-width difference between

and to bit-width of

[0081] First interpolation circuit 312 may perform interpolation of the estimated first RS channel to estimate the channel for data REs of the first signal. The interpolation performed by first interpolation circuit 312 may include those techniques described in connection with second interpolation circuit 322 or those described above in connection with FIG. 6. Once estimated channels for data REs have been obtained, second combination circuit 314 may combine the outputs of the first interpolation circuit 312 and second interpolation circuit 322 to obtain an estimated final data RE channel. [0082] By enabling the reduction of the bit-width, the power consumption associated with estimating a data RE channel may be significantly reduced as compared to using two full bit-width signals for data RE channel estimation. [0083] FIG. 4 illustrates a flowchart of an exemplary method 400 of wireless communication, according to embodiments of the disclosure. Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as user equipment 102, apparatus 200, baseband chip 202, channel estimation circuit 216, and/or node 500. Method 400 may include steps 402-410 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4A. [0084] At 402, the apparatus may receive a first signal and a second signal. For example, referring to FIG.2, channel estimation circuit 216 may receive the first signal and the second signal from interface unit 214. At 404, the apparatus may demodulate the first signal and the second signal. For example, referring to FIGs. 2 and 3A, RS demodulation circuit 302 may receive the first signal and the second signal from interface unit 214. At 406, the apparatus may perform first channel estimation of the first signal. For example, referring to FIG.3, one or more circuits 302, 304, 306, 308, 310, 312, in the first path may estimate a first data RE channel using the filtering and interpolation techniques described above. At 408, the apparatus may reduce the bit-width of a difference signal. The difference signal may be generated based on a difference between the first signal and the second signal. For example, referring to FIG.3, first bit-width reduction circuit 316 may reduce the bit-width of the difference signal using one of the techniques described above. At 410, the apparatus may perform second channel estimation of the second signal based on the reduced bit-width difference signal. For example, referring to FIG. 3, one or more circuits 316, 318, 320, 322, in the second path may estimate a second data RE channel using the filtering and interpolation techniques described above. [0085] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0086] According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include an interface unit configured to receive a first signal and a second signal. The first signal and the second signal may have the same bit-width. The baseband chip may also include a demodulation circuit configured to demodulate the first signal and the second signal. The baseband chip may also include a first path configured to perform a first channel estimation of the first signal. The baseband chip may also include a second path. The second path may be configured to generate a bit-width of a difference signal of the first signal and the second signal. The second path may also be configured to perform a second channel estimation of the reduced bit-width difference signal. [0087] In some embodiments, the first path may include a first difference calculation circuit configured to generate the difference signal by determining a first difference of the first signal and the second signal. In some embodiments, the second path may include a first bit-width reduction circuit configured to reduce the bit-width of the difference signal based at least in part on the first difference between the first signal and the second signal. [0088] In some embodiments, the first path may further include a first filtering circuit configured to filter the first signal to estimate a first RS channel. In some embodiments, the second path may further include a second filtering circuit configured to filter the reduced bit-width difference signal to estimate a second RS channel. [0089] In some embodiments, the first path may further include a first combination circuit configured to combine the first RS channel and the second RS channel. [0090] In some embodiments, the first path may further include a second difference calculation circuit configured to generate a difference channel by determining a second difference between the first RS channel and the second RS channel. In some embodiments, the second path may further include a second bit-width reduction circuit configured to reduce the bit-width of the difference channel. [0091] In some embodiments, the first path may further include a first interpolation circuit configured to interpolate the first RS channel to generate a first data RE channel. In some embodiments, the second path may further include a second interpolation circuit configured to interpolate the second RS channel to generate a second data RE channel. [0092] In some embodiments, the first path may further include a second combination circuit configured to combine the first data RE channel and the second data RE channel to obtain a final data RE channel. [0093] According to one aspect of the present disclosure, an apparatus for wireless communication is disclosed. The apparatus may include a memory and at least one processor. The at least one processor may be configured to receive a first signal and a second signal. The first signal and the second signal may have the same bit-width. The at least one processor may be further configured to demodulate the first signal and the second signal. The at least one processor may be further configured to perform a first channel estimation of the first signal. The at least one processor may be further configured to generate a reduced bit-width difference signal of the first signal and the second signal. The at least one processor may be further configured to perform a second channel estimation of the reduced bit-width second signal. [0094] In some embodiments, the at least one processor may be further configured to determine a first difference of the first signal and the second signal to generate the difference signal. In some embodiments, the at least one processor may be further configured to reduce the bit-width of the difference signal based at least in part on the first difference between the first signal and the second signal. [0095] In some embodiments, the at least one processor may be further configured to filter the first signal to estimate a first RS channel. In some embodiments, the at least one processor may be further configured to filter the reduced bit-width difference signal to estimate a second RS channel. [0096] In some embodiments, the at least one processor may be further configured to combine the first RS channel and the second RS channel. [0097] In some embodiments, the at least one processor may be further configured to generate a difference channel by determining a second difference between the first RS channel and the second RS channel. In some embodiments, the at least one processor may be further configured to reduce the bit-width of the difference channel based at least in part on the second difference. [0098] In some embodiments, the at least one processor may be further configured to interpolate the first RS channel to estimate a first data RE channel. In some embodiments, the at least one processor may be further configured to interpolate the reduced bit-width difference channel to estimate a second data RE channel. [0099] In some embodiments, the at least one processor may be further configured to combine the first data RE channel and the second data RE channel to generate a final data RE channel. [0100] According to one aspect of the present disclosure, a method of wireless communication is disclosed. The method may include receiving, by an interface unit, a first signal and a second signal. The first signal and the second signal may have a same bit-width. The method may further include demodulating, by a demodulation circuit, the first signal and the second signal. The method may further include performing, by a first path, a first channel estimation of the first signal. The method may further include generating, by a second path, a reduced bit-width difference signal of the first signal and the second signal. The method may further include performing, by the second path, a second channel estimation of the reduced bit-width difference signal. [0101] In some embodiments, the method may include generating, by a first difference calculation circuit of the first path, the difference signal by determining a first difference of the first signal and the second signal. In some embodiments, the method may include reducing, by a first bit-width reduction circuit of the second path, the bit-width of the difference signal. [0102] In some embodiments, the method may include filtering, by a first filtering circuit of the first path, the first signal to estimate a first RS channel. In some embodiments, the method may include filtering, by a second filtering circuit of the second path, the reduced bit-width difference signal to estimate a second RS channel. [0103] In some embodiments, the method may include combining, by a first combination circuit of the first path, the first RS channel, and the second RS channel. [0104] In some embodiments, the method may include generating, by a second difference calculation circuit of the first path, a difference channel by determining a second difference between the first RS channel and the second RS channel. In some embodiments, the method may include reducing, by a second bit-width reduction circuit of the second path, the bit-width of the difference RS channel based at least in part on the second difference. [0105] In some embodiments, the method may include interpolating, by a first interpolation circuit of the first path, the first RS channel to estimate a first data RE channel. In some embodiments, the method may include interpolating, by a second interpolation circuit of the second path, the second RS channel to estimate a second data RE channel. In some embodiments, the method may include combining, by a second combination circuit of the first path, the first data RE channel, and the second data RE channel to generate a final data RE channel. [0106] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. [0107] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0108] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. [0109] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. [0110] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS: 1. A baseband chip, comprising: an interface unit configured to receive a first signal and a second signal of a same bit- width; a demodulation circuit configured to demodulate the first signal and the second signal; a first path configured to perform a first channel estimation of the first signal; and a second path configured to: generate a reduced bit-width difference signal of the first signal and the second signal; and perform a second channel estimation of the reduced bit-width difference signal. 2. The baseband chip of claim 1, wherein the first path comprises: a first difference calculation circuit configured to generate the difference signal by determining a first difference of the first signal and the second signal, wherein the second path comprises: a first bit-width reduction circuit configured to reduce the bit-width of the difference signal based at least in part on the first difference between the first signal and the second signal. 3. The baseband chip of claim 2, wherein the first path further comprises: a first filtering circuit configured to filter the first signal to estimate a first RS channel, wherein the second path further comprises: a second filtering circuit configured to filter the reduced bit-width difference signal to estimate a second RS channel. 4. The baseband chip of claim 3, wherein the first path further comprises: a first combination circuit configured to combine the first RS channel and the second RS channel. 5. The baseband chip of claim 4, wherein the first path further comprises: a second difference calculation circuit configured to generate a difference channel by determining a second difference between the first RS channel and the second RS channel, wherein the second path further comprises: a second bit-width reduction circuit configured to reduce the bit-width of the difference channel. 6. The baseband chip of claim 5, wherein the first path further comprises: a first interpolation circuit configured to interpolate the first RS channel to generate a first data RE channel, wherein the second path further comprises: a second interpolation circuit configured to interpolate the difference channel to generate a second data RE channel. 7. The baseband chip of claim 6, wherein the first path further comprises: a second combination circuit configured to combine the first data RE channel and the second data RE channel to obtain a final data RE channel. 8. An apparatus for wireless communication, comprising: a memory; and at least one processor coupled to the memory and configured to: receive a first signal and a second signal of a same bit-width; demodulate the first signal and the second signal; perform a first channel estimation of the first signal; generate a reduced bit-width difference signal of the first signal and the second signal; and perform a second channel estimation of the reduced bit-width second signal. 9. The apparatus of claim 8, wherein the at least one processor is further configured to: determine a first difference of the first signal and the second signal to generate the difference signal; and reduce the bit-width of the difference signal based at least in part on the first difference between the first signal and the second signal. 10. The apparatus of claim 9, wherein the at least one processor is further configured to: filter the first signal to estimate a first RS channel; and filter the reduced bit-width difference signal to estimate a second RS channel. 11. The apparatus of claim 10, wherein the at least one processor is further configured to: combine the first RS channel and the second RS channel. 12. The apparatus of claim 11, wherein the at least one processor is further configured to: generate a difference channel by determine a second difference between the first RS channel and the second RS channel; and generate a reduced bit-width difference channel based at least in part on the second difference. 13. The apparatus of claim 12, wherein the at least one processor is further configured to: interpolate the first RS channel to estimate a first data RE channel; and interpolate the reduced bit-width difference channel to estimate a second data RE channel. 14. The apparatus of claim 13, wherein the at least one processor is further configured to: combine the first data RE channel and the second data RE channel to generate a final data RE channel. 15. A method of wireless communication, comprising: receiving, by an interface unit, a first signal and a second signal of a same bit-width; demodulating, by a demodulation circuit, the first signal and the second signal; performing, by a first path, a first channel estimation of the first signal; generating, by a second path, a reduced bit-width difference signal of the first signal and the second signal; and performing, by the second path, a second channel estimation of the reduced bit-width difference signal. 16. The method of claim 15, further comprising: generating, by a first difference calculation circuit of the first path, a difference signal by determining a first difference of the first signal and the second signal; and reducing, by a first bit-width reduction circuit of the second path, the bit-width of the difference signal to generate the reduced bit-width difference signal. 17. The method of claim 16, further comprising: filtering, by a first filtering circuit of the first path, the first signal to estimate a first RS channel; and filtering, by a second filtering circuit of the second path, the reduced bit-width difference signal to estimate a second RS channel. 18. The method of claim 17, further comprising: combining, by a first combination circuit of the first path, the first RS channel and the second RS channel. 19. The method of claim 18, further comprising: generating, by a second difference calculation circuit of the first path, a difference channel by determining a second difference between the first RS channel and the second RS channel and reducing, by a second bit-width reduction circuit of the second path, the bit-width of the difference channel based at least in part on the second difference. 20. The method of claim 19, further comprising: interpolating, by a first interpolation circuit of the first path, the first RS channel to estimate a first data RE channel; interpolating, by a second interpolation circuit of the second path, the second RS channel to estimate a second data RE channel; and combining, by a second combination circuit of the first path, the first data RE channel, and the second data RE channel to generate a final data RE channel.