WO2024031769A1 - Structure semi-conductrice et procédé de fabrication de structure semi-conductrice - Google Patents

Structure semi-conductrice et procédé de fabrication de structure semi-conductrice Download PDF

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Publication number
WO2024031769A1
WO2024031769A1 PCT/CN2022/117386 CN2022117386W WO2024031769A1 WO 2024031769 A1 WO2024031769 A1 WO 2024031769A1 CN 2022117386 W CN2022117386 W CN 2022117386W WO 2024031769 A1 WO2024031769 A1 WO 2024031769A1
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Prior art keywords
power supply
memory
semiconductor structure
chip
supply wiring
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PCT/CN2022/117386
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English (en)
Chinese (zh)
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WO2024031769A9 (fr
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庄凌艺
吕开敏
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长鑫存储技术有限公司
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Publication of WO2024031769A1 publication Critical patent/WO2024031769A1/fr
Publication of WO2024031769A9 publication Critical patent/WO2024031769A9/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure belongs to the field of semiconductors, and specifically relates to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • HBM High Bandwidth Memory
  • Memory chip stacking technology represented by HBM extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thus greatly increasing the density of memory chips and achieving large capacity and high performance. bandwidth.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least beneficial to reducing the power consumption of the semiconductor structure and improving the integration level of the semiconductor structure.
  • embodiments of the present disclosure provide a semiconductor structure, wherein the semiconductor structure includes: a substrate; an interposer welded on the upper surface of the substrate; and a power management chip welded on the interposer. upper surface; a memory module located on the upper surface of the interposer; the memory module includes a plurality of memory chips stacked along a first direction, the first direction being parallel to the upper surface of the interposer; each of the There is a power supply signal line in the memory chip, and one of the plurality of memory chips has at least a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; the power management chip is also connected to the power supply wiring layer. Electrical connection.
  • another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure.
  • the manufacturing method includes: providing a memory module, the memory module including a plurality of memory chips stacked along a first direction, each There is a power supply signal line in the memory chip, and one of the plurality of memory chips has at least a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; an intermediary layer and a power management chip are provided; and all The memory module and the power management chip are welded on the interposer layer, and the first direction is parallel to the upper surface of the interposer layer; the power supply wiring layer is electrically connected to the power management chip; providing The substrate is soldered to the interposer layer.
  • the power management chip and the memory module are packaged at the system level, thereby increasing the degree of integration, facilitating power management, and reducing system power consumption.
  • Figure 1 shows a schematic diagram of a semiconductor structure
  • FIGS 2-3, 5, and 7 respectively show cross-sectional views of different semiconductor structures provided by an embodiment of the present disclosure
  • FIGS 4, 6, and 8 respectively show partial top views of different semiconductor structures provided by an embodiment of the present disclosure
  • Figure 9 shows a schematic diagram of the active surface of a memory chip provided by an embodiment of the present disclosure.
  • the arrangement direction of the plurality of memory chips 200 in the HBM is perpendicular to the upper surface of the substrate 300 , that is, the front or back of the memory chips 200 faces the logic chip 400 .
  • a power supply signal line (not shown in the figure) is led out from the front or back of the memory chip 200.
  • the power supply signal line establishes an electrical connection with the logic chip 400 through conductive vias, bonding portions and other conductive structures; the logic chip 400 is electrically connected to the substrate 300.
  • the substrate 300 is electrically connected to the power management chip (not shown in the figure), thereby realizing the electrical connection between the memory chip 200 and the power management chip.
  • the memory chip 200 and the power management chip are located in different packaging structures and are far apart. Therefore, the system power consumption is large and the integration level of the semiconductor structure is low.
  • Embodiments of the present disclosure provide a semiconductor structure in which a power management chip and a memory module are welded to an interposer at the same time, and the interposer is welded to a substrate. That is, the power management chip and the memory module are located in the same packaging structure, with a high degree of integration. In addition, the power supply wiring layer of the memory chip does not need to be electrically connected to the power management chip through the substrate, which is beneficial to shortening the wired power supply path and reducing power consumption.
  • an embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes: a substrate 92; an interposer 91 welded on the upper surface of the substrate 92; and a power management chip 6 welded on the interposer 91.
  • Upper surface; the memory module 100 is located on the upper surface of the interposer 91; the memory module 100 includes a plurality of memory chips 1 stacked along a first direction X, the first direction X is parallel to the upper surface of the interposer 91; each memory chip 1
  • the power supply wiring layer 2 is electrically connected to the power supply signal line 12; the power management chip 6 is also electrically connected to the power supply wiring layer 2.
  • the power management chip 6 and the memory module 100 can be integrated inside the same packaging structure to achieve system-level packaging, thereby increasing the integration level.
  • the distance between the power management chip 6 and the memory module 100 is closer, it is beneficial to power management and reduces system power consumption.
  • the plurality of memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the plurality of memory chips 1 is parallel to the substrate 92 . Therefore, the side surface of the memory chip 1 faces the substrate 92. Since the area of the side surface of the memory chip 1 is smaller, it occupies a smaller area on the upper surface of the substrate 92. Therefore, the power management chip 6 and the power management chip 6 can be connected to the memory chip 1.
  • the connection structure between chips 1 provides more sufficient space, thereby facilitating the implementation of system-level packaging.
  • the semiconductor structure has a first direction X, a second direction Y, and a third direction Z.
  • the first direction X is the stacking direction of the memory chip 1; the second direction Y is perpendicular to the first direction
  • the surface of the memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together through molecular force or other forces.
  • the surface of the memory chip 1 may also have bonding portions 42. Under temperature rising conditions, adjacent bonding portions 42 are bonded and connected together. That is to say, the dielectric layer 43 is made of insulating material and can play an isolation role; the bonding portion 42 is made of conductive material and can play an electrical connection role.
  • the dielectric layer 43 also exposes the end surface 14 of the power supply wiring layer 2 facing away from the substrate 92 and covers the surface of the power supply wiring layer 2 except the end surface 14 .
  • the memory chip 1 may be a chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory).
  • adjacent memory chips 1 can be stacked front to back, which facilitates the unification of the bonding steps of the memory chips 1 and makes the production process simpler.
  • the stacking manner of adjacent memory chips 1 may also include front-to-front, or back-to-back.
  • the front side of the memory chip 1 can also be understood as the active surface 13
  • the back side of the memory chip 1 can be understood as the non-active surface opposite to the active surface 13 .
  • the two memory modules 100 are respectively located on opposite sides of the power management chip 6, and the memory modules 100 and the power management chip 6 are arranged in the first direction X. That is, the opposite sides of the power management chip 6 can provide sufficient connection positions for the memory module 100, making the connection process simpler. In other embodiments, there may be only one storage module 100 .
  • the semiconductor structure further includes: a lead frame 7 electrically connected between the power supply wiring layer 2 and the power management chip 6 .
  • the power management chip 6 performs power management on the memory module 100 through the lead frame 7 .
  • the lead frame 7 has high strength and is not easily deformed, thereby regulating the direction of the wired power supply path.
  • the lead frame 7 will be described in detail below.
  • the lead frame 7 includes: a first frame 71, a second frame 72, and a third frame 73 connected in sequence; both the first frame 71 and the third frame 73 are in the first direction. Extending on X, the first frame 71 extends toward the memory module 100 relative to the second frame 72 ; the third frame 73 extends toward the power management chip 6 relative to the second frame 72 . That is, the cross-sectional areas of the first frame 71 and the third frame 73 are larger than the cross-sectional area of the second frame 72 , and the aforementioned cross-sections are parallel to the upper surface of the interposer 91 .
  • the first frame 71 can reduce the distance between the memory module 100 and the lead frame 7
  • the third frame 73 can reduce the distance between the power management chip 6 and the lead frame 7
  • the first frame 71 can be the power supply wiring layer 2
  • the third frame 73 can provide more sufficient connection positions for the power management chip 6, thereby reducing the difficulty of connection and improving the flexibility of connection.
  • Figures 4, 6 and 8 are partial top views of different semiconductor structures respectively, and Figure 4 corresponds to the semiconductor structure shown in Figures 2 and 3, Figure 6 corresponds to the semiconductor structure shown in Figure 5, and Figure 8 corresponds to the semiconductor structure shown in Figure 7 semiconductor structure.
  • FIGs 4, 6 and 8 there are multiple lead frames 7, and the multiple lead frames 7 are arranged in the second direction Y; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the interposer 91 surface; each power supply wiring layer 2 includes a plurality of power supply wirings 20 with different voltages; different lead frames 7 are electrically connected to the power supply wirings 20 with different voltages. That is, the power management chip 6 can provide different voltage signals to the memory module 100 through different lead frames 7 .
  • the lead frame 7 includes a ground lead frame 7G and a power lead frame 7P; the ground lead frame 7G and the power lead frame 7P are alternately arranged in the second direction Y. In this way, it is beneficial to reduce electromagnetic interference between adjacent lead frames 7 .
  • multiple lead frames 7 are arranged at equal intervals in the second direction Y, which is beneficial to improving structural uniformity and avoiding incorrect electrical connections caused by adjacent lead frames 7 being too close.
  • FIG 9 is a schematic diagram of the active surface 13 of the memory chip 1.
  • Each power supply wiring layer 2 includes a plurality of power supply wirings 20 arranged at intervals, and different power supply signal lines 12 have different voltage signals.
  • the power supply wiring 20 is a ground wiring 20G or a power wiring 20P, that is, each power supply wiring layer 2 may include a plurality of ground wirings 20G and a plurality of power wiring 20P.
  • each memory chip 1 has a plurality of power supply signal lines 12 .
  • the power supply signal lines 12 extend from the memory chip 1 to the active surface 13 for connecting the power supply wiring layer 2 .
  • Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to components in the memory chip 1 .
  • the power supply signal line 12 may be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.
  • ground wiring 20G is electrically connected to the ground signal line 12G and the ground lead frame 7G
  • the power wiring 20P is electrically connected to the power signal line 12P and the power lead frame 7P.
  • multiple wired power supply paths can be formed to provide storage space.
  • Chip 1 provides different voltages.
  • ground wiring 20G and the power wiring 20P can also be alternately arranged in the second direction Y, thereby reducing electromagnetic interference between adjacent power supply wirings 20 .
  • the following will illustrate the arrangement of the power supply wiring layer 2 and the connection method between the lead frame 7 and the power supply wiring layer 2 .
  • each memory chip 1 has a power supply wiring layer 2 , and the power supply wiring layer 2 in each memory chip 1 is connected correspondingly to the power supply signal line 12 . That is, the power supply signal lines 12 of different memory chips 1 are independent of each other and do not need to be electrically connected through the conductive vias 41 and the bonding portion 42; the power supply signal lines 12 in each memory chip 1 can be connected through the power supply wiring of the memory chip 1 itself.
  • the power supply wiring layer 2 is led out without borrowing the power supply wiring layer 2 of other memory chips 1. Since the power supply signal line 12 of each memory chip 1 can be drawn out individually, it is beneficial to improve the stability of the power supply. In addition, the preparation step of the conductive via 41 (refer to FIG. 7 ) can also be omitted, thereby reducing production costs. In addition, since the plurality of memory chips 1 are independent of each other, the bonding portion 42 does not need to be provided between adjacent memory chips 1, resulting in lower production costs.
  • the memory chip 1 also has a plurality of welding bumps 81.
  • the welding bumps 81 are connected to the end face 14 of the power supply wiring 20 away from the interposer 91; the lead frame 7 is connected to the welding bumps 81 of the plurality of memory chips 1. Electrical connection. That is, the welding bumps 81 not only serve to electrically connect the lead frame 7 to the power supply wiring layer 2 , but also serve to fix the lead frame 7 , so that the memory module 100 can support the lead frame 7 to improve the stability of the structure. sex.
  • the welding bump 81 includes a first bump and a second bump arranged in a stack; the cross-sectional area of the first bump is larger than the cross-sectional area of the second bump. That is, the larger cross-sectional area of the first bump is conducive to increasing the contact area between the soldering bump 81 and the power supply wiring layer 2 to reduce the contact resistance.
  • the smaller cross-sectional area of the second bump is conducive to increasing the distance between adjacent soldering bumps 81 to avoid erroneous electrical connections between adjacent soldering bumps 81 .
  • the power supply wirings 20 with the same voltage in the plurality of power supply wiring layers 2 are aligned in the first direction X and are electrically connected to the same lead frame 7 . Therefore, the orthographic projection of the lead frame 7 on the substrate 92 can be linear, which facilitates the alignment of the lead frame 7 with the soldering bumps 81 , simplifies the welding process, and saves the material of the lead frame 7 .
  • the lead frame 7 may also have a groove 7 a , and the welding bumps 81 face the groove 7 a and are welded. That is, the groove 7a is located in the first frame 71. It should be noted that the top surface of the soldering bump 81 also has a solder layer 82 to connect the soldering bump 81 and the lead frame 7.
  • the groove 7 a can accommodate more solder to improve the soldering strength and reduce the contact resistance between the soldering bump 81 and the lead frame 7 .
  • the width of the first frame 71 in the second direction Y may be greater than the width of the soldering bump 81 in the second direction Y, and the opening area of the groove 7a is larger than the top surface area of the soldering bump 81 . In this way, the capacity of the solder is larger and the soldering firmness is higher; in addition, the larger opening facilitates the alignment of the soldering bump 81 and the groove 7a. In other embodiments, the width of the first frame 71 in the second direction Y may also be less than or equal to the width of the soldering bump 81 .
  • each lead frame 7 has a plurality of grooves 7 a , and the plurality of grooves 7 a correspond to the plurality of soldering bumps 81 one-to-one. Therefore, the groove 7a can guide the flow direction of the solder during the welding process, that is, guide the solder to flow into the groove 7a to avoid electrical connection between adjacent welding bumps 81.
  • each lead frame 7 has a groove 7a, and one groove 7a is soldered to the soldering bumps 81 of the plurality of memory chips 1, that is, the groove 7a extends in the first direction X. In this way, the production process is simpler.
  • the number of power supply wiring layers 2 may also be less than the number of memory chips 1. Specifically, there is a conductive through hole 41 in the memory chip 1, and the conductive through hole 41 is connected to the power supply signal line 12; there is a bonding portion 42 between adjacent memory chips 1, and the bonding portion 42 is connected to the conductive hole in the adjacent memory chip 1. Via 41 connection. That is to say, the power supply signal lines 12 with the same voltage signal in different memory chips 1 can be connected together through the conductive vias 41 and the bonding portions 42 . For example, the power supply signal lines 12 with the same voltage signal in two adjacent memory chips 1 are electrically connected. In this way, one of the two memory chips 1 only needs to have the power supply wiring layer 2 .
  • multiple memory chips 1 can share one power supply wiring layer 2 . If a memory chip 1 has its own power supply wiring layer 2, the power supply signal line 12 of the memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, it can be led out through its own power supply wiring layer 2. If a memory chip 1 does not have a power supply wiring layer 2, the memory chip 1 can establish an electrical connection with other memory chips 1 through conductive vias 41 and bonding portions 42, thereby passing through the power supply wiring layer 2 of other memory chips 1 Lead out the power supply signal line 12.
  • the number of power supply wiring layers 2 is smaller, and accordingly, the number of soldering bumps 8 is smaller, thereby increasing the spacing between adjacent soldering bumps 8 to avoid An incorrect electrical connection occurs between adjacent solder bumps 8 .
  • Example 3 referring to Figures 7-8, one memory chip 1 in the memory module 100 has a power supply wiring layer 2; the memory chip 1 has a conductive via 41, and the conductive via 41 is connected to the power supply signal line 12; adjacent memory chips There is a bonding portion 42 between 1, and the bonding portion 42 is connected to the conductive via holes in the adjacent memory chips 1, so that the power supply signal lines 12 of all memory chips 1 are electrically connected to the power supply wiring layer 2. That is to say, the power supply signal lines 12 with the same voltage signal in different memory chips 1 can be connected together through the conductive vias 41 and the bonding portions 42 .
  • the semiconductor structure further includes: a first lead 75 connected between the power supply wiring layer 2 and the lead frame 7 . Since the number of power supply wiring layers 2 is small, the lead connection method can be directly used, thereby making the process simpler and saving costs.
  • the bottom of the lead frame 7 can also be welded to the interposer 91 through the welding pad 86 , thereby improving the stability of the lead frame 7 . That is, the cooperation between the first lead 75 and the bonding pad 86 can improve the connection flexibility and increase the structural strength at the same time.
  • the memory chip 1 closest to the power management chip 6 in the memory module 100 has a power supply wiring layer 2 .
  • the length of the first lead 75 can be shortened and power consumption can be reduced.
  • the power supply wiring layer 2 may include a first wiring layer 21 and a second wiring layer 22.
  • the first wiring layer 21 extends in the third direction Z, and the second wiring layer 22 is located on the memory chip 1 away from the interposer layer 91. surface.
  • the second wiring layer 22 can increase the exposed area of the power supply wiring layer 2 to reduce the difficulty of connecting the first lead 75 to the power supply wiring layer 2 .
  • Example 1 Comparing the above three examples, it is easy to find that in Example 1 and Example 2, the number of power supply wiring layers 2 is relatively large, and welding bumps 81 can be used to connect the power supply wiring layers 2 to the lead frame 7 .
  • the main reason is that compared with the leads, the position of the soldering bumps 81 is fixed, thereby avoiding erroneous electrical connections; in addition, the second frame can extend on the top surface of the memory module 100 to provide multiple soldering bumps. 81 provides sufficient connection positions; in addition, the large number of welding bumps 81 can strengthen the support and fixation of the lead frame 7 .
  • each memory module 100 has only one power supply wiring layer 2 , and the first lead 75 can be used to connect to the lead frame 7 .
  • the leads are easy to bend, and the connection method is more flexible and simple; in addition, because the number of power supply wiring layers 2 is small, the number of first leads 75 is also small, and the distance between adjacent first leads 75 Larger, it can avoid erroneous electrical connection of adjacent first leads 75 .
  • the semiconductor structure further includes: a second lead 74, and the second lead 74 is connected between the lead frame 7 and the power management chip 6.
  • the second lead 74 can improve the flexibility of connecting the lead frame 7 and the power management chip 6 .
  • the semiconductor structure further includes: a first sealing layer 51 surrounding the memory module 100 and exposing the surface of the memory module 100 away from the substrate 9 .
  • the first sealing layer 51 can protect the memory module 100 from the influence of the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration when the semiconductor structure is installed.
  • the semiconductor structure further includes: a second sealing layer 52 , which can cover the memory module 100 , the lead frame 7 , the interposer 91 , the first sealing layer 51 and other structures.
  • the second sealing layer 52 can improve the protection and isolation effect to ensure the performance of the semiconductor structure.
  • first sealing layer 51 and the second sealing layer 52 may be made of the same material.
  • first sealing layer 51 and the second sealing layer 52 may be epoxy resin.
  • the materials of the first sealing layer 51 and the second sealing layer 52 may be different.
  • the second sealing layer 52 has a higher thermal conductivity than the first sealing layer 51 .
  • the lead frame 7 The heat introduced into the second sealing layer 52 can be transferred to the external environment faster, thereby reducing the adverse effects of the high temperature environment on the memory module 100 .
  • the semiconductor structure also includes: a logic chip 3, located between the interposer 91 and the memory module 100.
  • the logic chip 3 has a first wireless communication part 31; the memory chip 1 has a second
  • the wireless communication unit 11 , the second wireless communication unit 11 and the first wireless communication unit 31 perform wireless communication.
  • the second wireless communication part 11 is located on a side of the memory chip 1 facing the logic chip 3 . As a result, the distance between the first wireless communication unit 31 and the second wireless communication unit 11 can be reduced, thereby improving the quality of wireless communication.
  • the arrangement direction of multiple memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delays of the memory chips 1 and the logic chip 3 of different layers will be greatly different; in addition, as the number of layers increases, the The number of through-silicon vias (TSV, Through-Silicon Vias) used for communication will increase proportionally, thus sacrificing wafer area.
  • TSV through-silicon vias
  • the stacking direction and communication method of the memory chip 1 are changed, which is beneficial to improving communication quality and saving wafer area.
  • the side of the memory chip 1 is facing the logic chip 3, and the area on the side is smaller; and using wireless communication, there is no need to set a wire between the memory chip 1 and the logic chip 3.
  • the communication part can thereby reduce the process difficulty and provide sufficient space for the connection structure between the memory chip 1 and the logic chip 3 to improve the structural strength of the two.
  • the lower side of the storage module 100 is used for wireless communication, and the upper side of the storage module 100 is used to lay out the wired power supply path, thereby reducing the electromagnetic interference caused by the current in the wired power supply path to the coil in the wireless communication unit and avoiding signals. loss.
  • the adhesive layer 32 there is an adhesive layer 32 between the memory module 100 and the logic chip 3 . That is, the memory module 100 and the logic chip 3 are connected together through adhesive means to form a memory core.
  • the adhesive layer 32 may be a die attach film (DAF).
  • DAF die attach film
  • the adhesive layer 32 may also be doped with metal ions to improve the heat dissipation effect of the memory module 100 and the logic chip 3 .
  • drawing the power supply signal line 12 from the top of the memory module 100 can leave sufficient space below the memory module 100 to connect the logic chip 3, thereby improving the structural strength.
  • soldering pad 84 and a solder paste layer 85 between the logic chip 3 and the interposer 91 that is, the logic chip 3 is soldered to the interposer 91 through flip-chip welding.
  • the logic chip 3 can be powered and signal exchanged through a wired method, and the wired method has high reliability.
  • the bottom of the interposer 91 also has solder balls 93 to connect the interposer 91 and the substrate 92 .
  • the interposer layer 91 has traces, and its function is to expand the connection surface, thereby making it easier to realize the electrical connection between the substrate 92 and the power management chip 6 and the memory core.
  • the substrate 92 can provide functions such as electrical connection, protection, support, heat dissipation, and assembly for the power management chip 6 and the memory core.
  • the arrangement direction of the multi-layer memory chip 1 is parallel to the upper surface of the logic chip 3, and the two form a memory core.
  • the memory core and the power management chip 6 are packaged in a high-density system level on the interposer layer 91 .
  • the signal communication between the memory chip 1 and the logic chip 3 is realized wirelessly, which can reduce the communication difficulties caused by the increase in the number of stacked layers of the memory chip 1.
  • the power management chip 6 and the memory chip 1 are wired to realize wired power supply, thereby ensuring reliability.
  • system-level packaging is conducive to power management of the memory chip 1 by the power management chip 6, which can increase the degree of integration and reduce system power consumption.
  • FIG. 10-12 and 2 another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • This manufacturing method can manufacture the semiconductor structure provided in the previous embodiment.
  • this semiconductor structure please refer to the foregoing embodiments.
  • the memory module 100 includes a plurality of memory chips 1 stacked along a first direction
  • the wiring layer 2 and the power supply wiring layer 2 are electrically connected to the power supply signal line 12 .
  • a plurality of memory chips 1 are provided; a power supply wiring layer 2 is formed on at least one of the plurality of memory chips 1. After the power supply wiring layer 2 is formed, the plurality of memory chips 1 are stacked. For example, the power supply signal lines 12 of each layer of memory chips 1 are led out to the edge of the memory chip 1 through the power supply wiring layer 2, and the multi-layer memory chips 1 are stacked using hybrid bonding. It should be noted that during the bonding process, the memory chip 1 is placed horizontally.
  • the memory module 100 is rotated 90° so that each memory chip 1 is perpendicular to the logic chip 3, and the memory chip 1 and the logic chip 3 are fixed through the DAF film; the multiple memory modules 100 are reassembled through the first molding process. structure to form a reconstructed wafer; solder bumps 81 are processed on the top surface of the reconstructed wafer through a rewiring process, and balls are planted on the solder bumps 81 to form a solder layer 82. Thereafter, the reconstructed wafer is diced to form memory chips, each of which includes a memory module 100 and a logic chip 3 .
  • an interposer layer 91 and a power management chip 6 are provided; the memory module 100 and the power management chip 6 are welded to the interposer layer 91 , and the first direction X is parallel to the upper surface of the interposer layer 91 .
  • the memory core and the power management chip 6 are soldered on the interposer 91 through flip-chip soldering.
  • the power supply wiring layer 2 is electrically connected to the power management chip 6 .
  • the electrical connection between the memory chip 1 and the power management chip 6 is achieved through the welding bump 81 , the lead frame 7 and the second lead 74 , so that the power management chip 6 supplies power to the memory chip 1 .
  • a substrate 92 is provided, and the interposer 91 is soldered to the substrate 92 .
  • a second molding process may be performed to form a second molding layer 52 covering structures such as the interposer 91 , the memory core die, the power management chip 6 , and the lead frame 7 .
  • the system-level packaging of the memory core and the power management chip 6 can be completed, thereby improving integration and reducing power consumption.
  • a second molding process is used to form the second sealing layer 82 .
  • the reason why two molding processes are used in succession is that the first molding process can connect multiple memory modules 100 together. Therefore, the second wiring layer can be formed on multiple memory modules 100 at the same time subsequently. 22, thus helping to reduce process steps.
  • the volume of a single storage module 100 is small. When multiple storage modules 100 are connected together, the total volume becomes larger, the stability is higher, and it is less likely to tip over.
  • the first sealing layer 51 formed by the first molding process can protect and fix the memory module 100 in the subsequent steps of forming the welding bumps 81 and flip-chip welding to prevent the memory module 100 from collapsing or being damaged. , thereby helping to ensure the performance of the storage module 100.
  • two molding processes in succession can improve the sealing effect.

Abstract

Des modes de réalisation de la présente divulgation relèvent du domaine des semi-conducteurs, et concernent une structure semi-conductrice et un procédé de fabrication de la structure semi-conductrice. La structure semi-conductrice comprend : un substrat ; un interposeur soudé sur la surface supérieure du substrat ; une puce de gestion d'énergie soudée sur la surface supérieure de l'interposeur ; et un module de stockage situé sur la surface supérieure de l'interposeur, le module de stockage comprenant une pluralité de puces de stockage empilées dans une première direction, et la première direction étant parallèle à la surface supérieure de l'interposeur ; chaque puce de stockage est pourvue intérieurement d'une ligne de signal d'alimentation électrique, l'une de la pluralité de puces de stockage est pourvue d'au moins une couche de câblage d'alimentation électrique, et la couche de câblage d'alimentation électrique est électriquement connectée à la ligne de signal d'alimentation électrique ; et la puce de gestion d'énergie est en outre connectée électriquement à la couche de câblage d'alimentation électrique. Selon les modes de réalisation de la présente divulgation, au moins la consommation d'énergie de la structure semi-conductrice peut être réduite, et le niveau d'intégration de la structure semi-conductrice peut être amélioré.
PCT/CN2022/117386 2022-08-10 2022-09-06 Structure semi-conductrice et procédé de fabrication de structure semi-conductrice WO2024031769A1 (fr)

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