WO2024027710A1 - DigRF帧处理方法、装置、计算机设备及可读介质 - Google Patents

DigRF帧处理方法、装置、计算机设备及可读介质 Download PDF

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Publication number
WO2024027710A1
WO2024027710A1 PCT/CN2023/110557 CN2023110557W WO2024027710A1 WO 2024027710 A1 WO2024027710 A1 WO 2024027710A1 CN 2023110557 W CN2023110557 W CN 2023110557W WO 2024027710 A1 WO2024027710 A1 WO 2024027710A1
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data
frame
channels
channel
digrf
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PCT/CN2023/110557
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English (en)
French (fr)
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王海涛
王鹏
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深圳市中兴微电子技术有限公司
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Publication of WO2024027710A1 publication Critical patent/WO2024027710A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/02—Standardisation; Integration
    • H04L41/0226—Mapping or translating multiple network management protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/60—Software-defined switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
    • H04L65/60—Network streaming of media packets
    • H04L65/65—Network streaming protocols, e.g. real-time transport protocol [RTP] or real-time control protocol [RTCP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present disclosure relates to the field of communication technology, and specifically to a DigRF (Digital Radio Frequency, digital radio frequency) frame processing method, device, computer equipment and readable media.
  • DigRF Digital Radio Frequency, digital radio frequency
  • Some of the existing baseband chip interface protocols use streaming transmission methods, such as CPRI (Common Public Radio Interface, public wireless interface) protocol, Aurora protocol and j204B protocol. Since such interface solutions do not support energy-saving shutdown in sleep or idle state, , so the chip energy consumption is higher.
  • CPRI Common Public Radio Interface, public wireless interface
  • Some of the existing terminal chips also use packet transmission methods, such as the DigRF V1.12 protocol.
  • this interface protocol is only for GSM (Global System for Mobile communications, Global System for Mobile Communications). It is not versatile and has the fastest interface. The rate is only 52Mbit/s, which cannot meet existing transmission needs.
  • the present disclosure provides a DigRF frame processing method, device, computer equipment and readable medium.
  • a DigRF frame processing method including: receiving n channels of first data, and mapping each of the n channels of first data to any of m data channels.
  • m and n are integers greater than 2, and n>m; perform clock domain conversion on the first data of each data channel to obtain second data; convert the second data of each data channel The data is bit-width converted to obtain the third data, and the third data is cached; and, when the amount of the third data cached by the data channel reaches the data amount of one frame of data, the third data cached by the data channel is cached according to the data amount of the data channel.
  • Each of the third data is framed to obtain a DigRF data frame, and the data amount of one frame of data is determined according to the number of preset loads and the number of physical channels.
  • a DigRF frame processing device including a channel mapping module, a clock domain conversion module, a bit width conversion module, a cache module and a data processing module, wherein the channel mapping module is configured as Receive n channels of first data, and map each channel of the n channels of first data to any one of m data channels, where m and n are integers greater than 2, and n>m; so
  • the clock domain conversion module is configured to perform clock domain conversion on the first data of each data channel to obtain second data;
  • the bit width conversion module is configured to convert the second data on each data channel Perform bit width conversion to obtain third data;
  • the cache module is configured to cache the third data; and the data processing module is configured to cache the third data in the data channel in a quantity that reaches one frame of data.
  • the DigRF data frame is obtained by framing according to each of the third data cached in the data channel. The data volume of one frame of data is determined based on the number of preset loads and the number of physical channels.
  • a computer device including: one or more processors; a storage device, One or more programs are stored thereon; when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the DigRF frame processing method as described above.
  • a computer-readable medium is provided with a computer program stored thereon, wherein when the program is executed, the DigRF frame processing method as described above is implemented.
  • Figure 1 is a schematic diagram 1 of the DigRF frame processing flow according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the DigRF frame format according to an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of the format of first data according to an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of the format of third data according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram 2 of the DigRF frame processing flow according to an embodiment of the present disclosure.
  • Figure 6 is a module schematic diagram of a DigRF frame processing device according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a DigRF frame processing device according to an embodiment of the present disclosure.
  • Embodiments described herein may be described with reference to plan and/or cross-sectional illustrations, with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified based on manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to those shown in the drawings but include modifications of configurations formed based on the manufacturing process. Accordingly, the regions illustrated in the figures are of a schematic nature and the shapes of the regions shown in the figures are illustrative of the specific shapes of regions of the element and are not intended to be limiting.
  • Embodiments of the present disclosure provide a DigRF frame processing method, which is applied to a DigRF frame processing device. As shown in Figure 1, the following steps S11 to S14 are included.
  • step S11 n channels of first data are received, and each channel of the n channels of first data is mapped to any one of the m data channels.
  • n and n are integers greater than 2, and n>m.
  • Input the DigRF frame processing device, and the channel mapping module (CH_MAP) of the DigRF frame processing device maps each of the 12 channels of first data to any one of the 8 data channels, ensuring that each channel of the first data is evenly distributed. Enter a data channel.
  • Figures 6 and 7 are respectively a module schematic diagram and a structural schematic diagram of a DigRF frame processing device according to an embodiment of the present disclosure.
  • the channel mapping module (CH_MAP) can select a data selector. 12 channels of first data (i_dfe_data0-i_dfe_data11) are input to 8 data selectors (MUX1-MUX8) corresponding to 8 data channels respectively. After 8 By selecting a data selector, the above 12 channels of first data enter 8 data channels respectively.
  • the DigRF frame processing device of the present disclosure can be instantiated as a radio frequency chip, a baseband chip or a terminal chip, or located in these chips.
  • step S12 clock domain conversion is performed on the first data of each data channel to obtain second data.
  • clock domain conversion is performed across the clock fifo (First Input First Output) to obtain the second data.
  • step S13 the second data of each data channel is bit-width converted to obtain third data, and the third data is cached.
  • the accuracy is 12 bits. That is to say, the bit width (precision) of the second data is 12 bits.
  • the second data with a width of 12 bits is converted into a third data with a width of 8 bits through a bit width conversion operation, and the third data is cached in the fifo buffer of the corresponding data channel.
  • the second data of 2 channels has a bit width of 48 bits, and the bus is configured as 1 physical channel.
  • the data is converted into 8-bit wide data.
  • step S14 when the number of third data cached in the data channel reaches the data volume of one frame of data, the DigRF data frame is obtained by framing according to each third data cached in the data channel.
  • the data volume of one frame of data is based on The number of preset loads is determined by the number of physical channels.
  • step S14 may be implemented during the implementation of step S13.
  • the maximum amount of data cached in the fifo buffer is the data amount of one frame of data corresponding to the preset load.
  • the fifo buffer sends a message to the digrfv4_tx_dlc_read module in the DigRF frame processing device.
  • the data volume of one frame of data corresponding to the preset load is determined based on the number of preset loads and the number of physical channels.
  • the preset load quantity is 256 bytes.
  • the digrfv4_tx_dlc_read module reads 256 third data at a time; in the case of 2 physical channels, the digrfv4_tx_dlc_read module reads 126 pieces at a time.
  • Third data, and so on, the embodiment of the present disclosure supports up to 4 physical channels.
  • the DigRF basic frame format is shown in Figure 2, including synchronization symbol (Sync), SOF (Start-of-Frame, Marker0), header signal (Header), load (Payload), CRC (Cyclic Redundancy Check, cyclic redundancy check) Check code and tail signal (EOF/EOT).
  • each data channel has a fixed load, that is, the number of loads in each data channel is the same.
  • the fixed load framing scheme is used, and the radio frequency chip and the baseband chip are related to each other.
  • the framing-related logic is relatively simple, saving chip area and logic resources.
  • the fixed-load framing scheme has high bandwidth utilization, takes less time to transmit the same amount of data, takes longer for the chip to enter idle and sleep states, and consumes less power. It can be used through DigRF The EOT at the end of the v4 frame enters the idle and sleep state to save energy and reduce power consumption.
  • the DigRF frame processing method includes: receiving n channels of first data, mapping the n channels of first data to any one of m data channels, m and n are integers greater than 2, and n>m ; Perform clock domain conversion on the first data of each data channel to obtain the second data; perform bit-width conversion on the second data of each data channel to obtain the third data, and cache the third data; in the third data cache of the data channel When the amount of data reaches the data amount of one frame of data, the DigRF data frame is obtained by framing according to the third data buffered by the data channel.
  • the data amount of one frame of data is the data amount of one frame of data corresponding to the preset load; this
  • the disclosed embodiment uses a fixed load for framing to maximize bandwidth utilization.
  • the framing logic of the radio frequency chip and the baseband chip is simple, saving chip area and logic resources, and the bandwidth utilization rate is improved.
  • the link remains idle or dormant for a longer time, and the chip power consumption is lower.
  • the n channels of first data include multiple formats.
  • the first data of various formats are input into the DigRF frame processing device according to specific application scenarios, and the DigRF frame processing device performs data channel mapping according to software configuration.
  • DLC_IQ_NUM determines the amount of data in a frame
  • DLC_IQ_LEN determines the data bit width, and is dynamically configured according to the transmission requirements of different formats.
  • DigRF protocol involves frame transmission processing, identification of retransmitted frames, or NEST mechanism processing on the receiving side.
  • these solutions involve fewer data formats, relatively simple usage scenarios, and the interface does not involve a frame of data. The question of the number of loads.
  • variable load framing scheme in the standard protocol is not suitable for complex transmission requirements and cannot minimize chip power consumption.
  • Embodiments of the present disclosure provide an interface solution based on DigRF fixed load. According to the transmission requirements of each standard data, fixed load framing is used to maximize the utilization of bandwidth. When the link is idle or dormant, it is turned off to save energy and reduce power consumption. .
  • the format of the first data includes one or any combination of the following: NR (New Radio, New Radio), NR_V2X (New Radio_Vehicle Wireless Communication), LTE (Long Term Evolution, Long Term Evolution Technology), LTE_V2X (Long Term Evolution Technology_Vehicle Wireless Communications), WCDMA (Wideband Code Division Multiple Access, Wideband Code Division Multiple Access).
  • NR New Radio, New Radio
  • NR_V2X New Radio_Vehicle Wireless Communication
  • LTE Long Term Evolution, Long Term Evolution Technology
  • LTE_V2X Long Term Evolution Technology_Vehicle Wireless Communications
  • WCDMA Wideband Code Division Multiple Access
  • the channel mapping module (CH_MAP) in the DigRF frame processing device can receive the first data sent by one or more of the following modems: NR modem, NR_V2X modem, LTE modem, LTE_V2X, WCDMA modem.
  • NR modem NR_V2X modem
  • LTE modem LTE_V2X
  • WCDMA modem WCDMA modem.
  • the three carriers (CC) of LTE can carry data services, and the design can cover the needs.
  • Which data channel the 12 channels of first data are mapped to can be configured through registers.
  • Figure 3 is a schematic diagram of the format of the first data according to an embodiment of the present disclosure.
  • the first data formats of 2 channels and 4 channels are as shown in Figure 3.
  • the amount of data per beat of 2 channels (2T) is smaller than that of 4 channels (4T).
  • Figure 4 is a schematic diagram of the format of the third data according to an embodiment of the present disclosure.
  • the input is the first data of 2 channels, and the format of the third data output by one physical channel is as shown in Figure 4, in which data_vld is valid (high level ), the corresponding header_vld is invalid (low level), and when header_vld is valid (high level), the corresponding data_vld is invalid (low level).
  • the DigRF frame processing method may further include the following step S14'.
  • step S14' in the case of format switching, framing is performed based on the third data currently cached in each data channel.
  • step S13 if the channel is turned off, indicating that an abnormality has occurred, the format will be switched. In this case, there is no need to wait for the amount of data cached in the fifo buffer in the data channel to reach the upper limit of storage (that is, the amount of data for one frame of data). , you can read the third data currently cached in the fifo cache, that is, no matter how much the third data is in the fifo cache at this time, it will be read out, and framed based on the read third data.
  • the payloads of the first data of various formats are the same.
  • the following method is used to determine that the amount of third data cached in the data channel reaches the data amount of one frame of data: in m data channels, it is determined in a polling manner that the amount of third data cached in the data channel reaches the amount of data in one frame.
  • the amount of data in one frame of data That is to say, polling is carried out in m data channels, and it is judged in turn whether the number of third data cached in the fifo buffer in the current data channel has reached the data amount of one frame of data. If so, the current data channel is grouped.
  • the frame to obtain the DigRF data frame of the data channel; if it is not reached, the frame will not be framed for the current data channel, but it will be judged whether the number of third data cached in the fifo buffer in the next data channel has reached one frame of data. amount of data, and so on.
  • the default payload size is 256 bytes.
  • the number of fixed loads is the maximum load number of 256 bytes specified by the protocol. This method has the highest bandwidth utilization, shorter time to transmit the same amount of data, longer time for the chip to enter idle and sleep states, and higher power consumption. Small.
  • Embodiments of the present disclosure can be applied to high-speed serial interfaces with small delays and connected by electrical signals.
  • the radio frequency chip and the terminal chip interact with uplink and downlink data, and this type of interface is usually used.
  • Embodiments of the present disclosure can also be applied to a baseband processing unit or an active antenna processing unit. For example, in a baseband processing unit, two boards perform cell data scheduling processing through a high-speed serial interface.
  • embodiments of the present disclosure also provide a DigRF frame processing device.
  • Figure 6 is a schematic module diagram of the DigRF frame processing device
  • Figure 7 is a schematic structural diagram of the DigRF frame processing device.
  • the DigRF frame processing device includes a channel mapping module 101, a clock domain conversion module 102, a bit width conversion module 103, a cache module 104 and a data processing module 105.
  • the channel mapping module 101 is configured to receive n channels of first data, and map each channel of the n channels of first data to any one of m data channels, where m and n are integers greater than 2. , and n>m.
  • the clock domain conversion module 102 is configured to perform clock domain conversion on the first data of each data channel to obtain second data.
  • the bit width conversion module 103 is configured to perform bit width conversion on the second data of each data channel to obtain third data.
  • the cache module 104 is configured to cache the third data.
  • the data processing module 105 is configured to perform framing according to each of the third data cached in the data channel to obtain a DigRF data frame when the amount of the third data cached in the data channel reaches the data amount of one frame of data.
  • the data amount of one frame of data is determined according to the number of preset loads and the number of physical channels.
  • the channel mapping module 101 is the data selector MUX1-MUX8, the clock domain conversion module 102 is the cross-clock fifo, the bit width conversion module 103 is the digrfv4_tx_dlc_splicing module, and the cache module 104 is The data cache fifo, the data processing module 105 is the digrfv4_tx_dlc_read module.
  • the n channels of first data include multiple formats.
  • the data processing module 105 is further configured to, after the cache module 104 caches the third data, in the case of format switching, perform the processing according to the third data currently cached in each of the data channels. Framing.
  • the format of the first data includes one or any combination of the following: New Radio NR, New Radio_Vehicle Wireless Communication NR_V2X, Long Term Evolution Technology LTE, Long Term Evolution Technology_Vehicle Wireless Communication LTE_V2X, Broadband Code Division Multiple Access WCDMA.
  • the payload of the first data in various formats is the same.
  • the data processing module 105 is configured to determine that the amount of the third data buffered by the data channel reaches the data amount of one frame of data in the following manner: among the m data channels, by polling It is determined that the amount of the third data buffered by the data channel reaches the data amount of one frame of data.
  • the number of preset payloads is 256 bytes.
  • Embodiments of the present disclosure also provide a computer device.
  • the computer device includes: one or more processors and a storage device; wherein one or more programs are stored on the storage device.
  • the above one or more processors implement the DigRF frame processing method as provided in the foregoing embodiments.
  • Embodiments of the present disclosure also provide a computer-readable medium on which a computer program is stored, wherein when the computer program is executed, the DigRF frame processing method as provided in the foregoing embodiments is implemented.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .
  • Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a general illustrative sense only and not for purpose of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be used in conjunction with other embodiments, unless expressly stated otherwise. Features and/or components used in combination. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention as set forth in the appended claims.

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Abstract

本公开提供一种DigRF帧处理方法，包括：接收n路第一数据，将n路第一数据映射到m个数据通道中的任一个，m和n为大于2的整数，且n>m；对每个数据通道的第一数据进行时钟域转换得到第二数据；将每个数据通道的第二数据进行位宽转换得到第三数据，并缓存第三数据；在数据通道缓存的第三数据的数量达到一帧数据的数据量时，根据数据通道缓存的各第三数据进行组帧，得到DigRF数据帧，一帧数据的数据量为预设负载对应的一帧数据的数据量；采用固定负载进行组帧，最大限度提高带宽利用率，射频芯片与基带芯片组帧逻辑简单，节省芯片面积和逻辑资源，带宽利用率提高，芯片功耗更低。本公开还提供一种DigRF帧处理装置、计算机设备和可读介质。

Description

DigRF帧处理方法、装置、计算机设备及可读介质
相关申请的交叉引用
本申请要求于2022年8月3日提交的名称为“DigRF帧处理方法、装置、计算机设备及可读介质”的中国专利申请CN202210927211.4的优先权，其全部内容通过引用并入本文。
技术领域
本公开涉及通信技术领域，具体涉及一种DigRF(Digital Radio Frequency，数字射频)帧处理方法、装置、计算机设备及可读介质。
背景技术
现有的一部分基带芯片接口协议采用的是流传输方式，比如CPRI(Common Public Radio Interface，公共无线接口)协议、Aurora协议和j204B协议,由于此类接口方案不支持休眠或空闲状态进入节能关断，因此芯片能耗较高。
现有终端芯片也有一部分采用包传输方式，比如DigRF V1.12协议，但是该接口协议只针对GSM(Global System for Mobile communications，全球移动通信系统)这一个制式，不具备通用性，且最快接口速率只有52Mbit/s，不能满足现有传输需求。
发明内容
本公开提供一种DigRF帧处理方法、装置、计算机设备和可读介质。
在本公开的一方面中，提供了一种DigRF帧处理方法，包括：接收n路第一数据，将所述n路第一数据中的每一路第一数据映射到m个数据通道中的任一个，其中，m和n为大于2的整数，且n>m；对每个所述数据通道的第一数据进行时钟域转换得到第二数据；将每个所述数据通道的所述第二数据进行位宽转换得到第三数据，并缓存所述第三数据；以及，在数据通道缓存的所述第三数据的数量达到一帧数据的数据量的情况下，根据所述数据通道缓存的各所述第三数据进行组帧得到DigRF数据帧，所述一帧数据的数据量根据预设负载的数量和物理通道的数量确定。
在本公开的另一方面中，提供了一种DigRF帧处理装置，包括通道映射模块、时钟域转换模块、位宽转换模块、缓存模块和数据处理模块，其中，所述通道映射模块被配置为接收n路第一数据，将所述n路第一数据中的每一路第一数据映射到m个数据通道中的任一个，其中，m和n为大于2的整数，且n>m；所述时钟域转换模块被配置为对每个所述数据通道的第一数据进行时钟域转换得到第二数据；所述位宽转换模块被配置为将每个所述数据通道的所述第二数据进行位宽转换得到第三数据；所述缓存模块被配置为缓存所述第三数据；并且，所述数据处理模块被配置为在数据通道缓存的所述第三数据的数量达到一帧数据的数据量的情况下，根据所述数据通道缓存的各所述第三数据进行组帧得到DigRF数据帧，所述一帧数据的数据量根据预设负载的数量和物理通道的数量确定。
在本公开的又一方面中，提供了一种计算机设备，包括：一个或多个处理器；存储装置， 其上存储有一个或多个程序；当所述一个或多个程序被所述一个或多个处理器执行时，使得所述一个或多个处理器实现如前所述的DigRF帧处理方法。
在本公开的再一方面中，提供了一种计算机可读介质，其上存储有计算机程序，其中，所述程序被执行时实现如前所述的DigRF帧处理方法。
关于本申请的以上实施例和其他方面以及其实现方式，在附图说明、具体实施方式和权利要求中提供更多说明。
附图说明
图1为根据本公开实施例的DigRF帧处理流程的示意图一；
图2为根据本公开实施例的DigRF帧格式示意图；
图3为根据本公开实施例的第一数据的格式示意图；
图4为根据本公开实施例的第三数据的格式示意图；
图5为根据本公开实施例的DigRF帧处理流程的示意图二；
图6为根据本公开实施例的DigRF帧处理装置的模块示意图；
图7为根据本公开实施例的DigRF帧处理装置的结构示意图。
具体实施方式
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
本文所述实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。因此，实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不旨在是限制性的。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
本公开实施例提供一种DigRF帧处理方法，应用于DigRF帧处理装置。如图1所示，包括以下步骤S11至S14。
在步骤S11中，接收n路第一数据，将n路第一数据中的每一路第一数据映射到m个数据通道中的任一个。
m和n为大于2的整数，且n>m。在本公开实施例中，n＝12,m＝8，即共有12路第一数据 输入DigRF帧处理装置，由DigRF帧处理装置的通道映射模块(CH_MAP)将12路第一数据中的每一路第一数据分别映射到8个数据通道中的任意一个，保证每路第一数据均进入一个数据通道。
图6和图7分别为根据本公开实施例的DigRF帧处理装置的模块示意图和结构示意图。如图所示，通道映射模块(CH_MAP)可以选用数据选择器，12路第一数据(i_dfe_data0-i_dfe_data11)，分别输入至8个数据通道对应的8个数据选择器(MUX1-MUX8),经过8个数据选择器的选择，上述12路第一数据分别进入8个数据通道。本公开的DigRF帧处理装置可以实例化为射频芯片、基带芯片或终端芯片，或位于这些芯片中。
在步骤S12中，对每个数据通道的第一数据进行时钟域转换得到第二数据。
在本公开实施例中，有两个时钟域，分别为clk_tx_sample*和clk_tx_work，在8个数据通道中的每一个数据通道，通过跨时钟fifo(First Input First Output)进行时钟域转换，得到第二数据。
在步骤S13中，将每个数据通道的第二数据进行位宽转换得到第三数据，并缓存第三数据。
在本公开实施例中，天线信号经过模－数转换以后，精度为12bit，也就是说，第二数据的位宽(精度)为12bit。在本步骤中，针对每个数据通道，通过位宽转换操作将12bit位宽的第二数据转换为8bit位宽的第三数据，并将第三数据缓存在相应数据通道的fifo缓存器内。举例而言，2个通道的第二数据，其位宽48bit，总线配置为1条物理通道，当fifo中缓存6个数据时，将数据转换成8bit位宽数据。
在步骤S14中，在数据通道缓存的第三数据的数量达到一帧数据的数据量的情况下，根据数据通道缓存的各第三数据进行组帧得到DigRF数据帧，一帧数据的数据量根据预设负载的数量和物理通道的数量确定。
需要说明的是，步骤S14可以在实施步骤S13的过程中实施。
每个数据通道中，fifo缓存器缓存的数据量的最大值为预设负载对应的一帧数据的数据量。正常情况下，即通道不关断的情况下，当fifo缓存器中缓存的数据量达到存储的上限(即一帧数据的数据量)时，fifo缓存器向DigRF帧处理装置中的digrfv4_tx_dlc_read模块发送指示信号，以指示digrfv4_tx_dlc_read模块从所述fifo缓存器中读取全部的第三数据，digrfv4_tx_dlc_read模块对读取到的全部第三数据进行组帧，得到一个DigRF数据帧。
预设负载对应的一帧数据的数据量根据预设负载的数量和物理通道的数量确定。比如，预设负载的数量为256byte(字节)，在1条物理通道的情况下，digrfv4_tx_dlc_read模块一次读出256个第三数据；在2条物理通道的情况下，digrfv4_tx_dlc_read模块一次读出126个第三数据，以此类推，本公开实施例最多支持4条物理通道。
DigRF基本帧格式如图2所示，包括同步符号(Sync)、SOF(Start-of-Frame，帧开始)即Marker0、头信号(Header)、负载(Payload)、CRC(Cyclic Redundancy Check，循环冗余校验)校验码和尾信号(EOF/EOT)。
在本公开实施例中，每个数据通道具有固定负载，即每个数据通道的负载数量均相同，与可变负载组帧方式相比，采用固定负载的组帧方案，射频芯片与基带芯片关于组帧相关逻辑比较简单，节省芯片面积和逻辑资源。而且，固定负载的组帧方案带宽利用率高，传输相同的数据量所用时间更短，芯片进入空闲、休眠状态的时间更长，功耗更小，可以通过DigRF  v4帧尾的EOT进入空闲、休眠状态，以达到节能、降功耗的目的。
本公开实施例提供的DigRF帧处理方法，包括：接收n路第一数据，将n路第一数据映射到m个数据通道中的任一个，m和n为大于2的整数，且n>m；对每个数据通道的第一数据进行时钟域转换得到第二数据；将每个数据通道的第二数据进行位宽转换得到第三数据，并缓存第三数据；在数据通道缓存的第三数据的数量达到一帧数据的数据量时，根据数据通道缓存的各第三数据进行组帧，得到DigRF数据帧，一帧数据的数据量为预设负载对应的一帧数据的数据量；本公开实施例采用固定负载进行组帧，最大限度提高带宽利用率，与可变负载组帧方式相比，射频芯片与基带芯片组帧逻辑简单，节省芯片面积和逻辑资源，而且，带宽利用率提高，在传输相同的数据量的情况下，链路处于空闲或休眠状态的时间更长，芯片功耗更低。
在本公开一些实施例中，所述n路第一数据包括多种制式。各种制式的第一数据根据具体应用场景输入DigRF帧处理装置，DigRF帧处理装置根据软件配置进行数据通道映射。
在本公开的相关技术中，DigRF协议中对于负载数量的描述，由DLC_IQ_NUM决定一帧中的数据量，DLC_IQ_LEN决定数据位宽，并且根据不同制式的传输需求进行动态配置。负载数量越大，有效线速率越高。相同数据量的情况下，有效线速率越高，链路处于空闲或者休眠状态时间越长，此时芯片的功耗也越小。因此当系统中集成很多调制解调器(modem)，应用场景比较复杂时，就需要考虑采用协议中描述的可变负载的组帧方案，还是固定负载的组帧方案。目前针对DigRF协议的应用，有关于帧发送处理、重传帧的识别或者接收侧的NEST机制处理，而这些方案涉及的数据制式较少，使用场景比较简单，接口中并未涉及一帧数据中负载的数量的问题。
由此可见，相关技术对DigRF协议虽有应用，但并未讨论负载的组帧方案。标准协议中关于可变负载的组帧方案，并不适用复杂的传输需求，并且不能最大限度降低芯片功耗。本公开实施例提供一种基于DigRF固定负载的接口方案，针对各制式数据的传输需求，采用固定负载组帧，最大限度利用带宽，链路处于空闲或休眠状态时，节能关断，降低功耗。
在一些实施例中，第一数据的制式包括以下之一或任意组合：NR(New Radio,新空口)、NR_V2X(新空口_车用无线通信)、LTE(Long Term Evolution，长期演进技术)、LTE_V2X(长期演进技术_车用无线通信)、WCDMA(Wideband Code Division Multiple Access，宽带码分多址)。
DigRF帧处理装置中的通道映射模块(CH_MAP)可以接收以下调制解调器(modem)中的一个或几个发送的第一数据：NR modem、NR_V2X modem、LTE modem、LTE_V2X、WCDMA modem。在第一数据为多种制式数据的情况下，将各种制式的12路第一数据映射到8个数据通道中，第一数据输入格式如表1所示：
表1

其中，LTE的3个载波(CC)可以承载数据业务，设计可覆盖需求。12路第一数据具体映射到哪一个数据通道，可以通过寄存器进行配置。
图3为根据本公开实施例的第一数据的格式示意图，2通道和4通道的第一数据格式如图3所示，其中，2通道(2T)的1拍数据量小于4通道(4T)的1拍数据量。
图4为根据本公开实施例的第三数据的格式示意图，输入为2通道的第一数据，1条物理通道输出的第三数据的格式如图4所示，其中，data_vld有效(高电平)时对应header_vld无效(低电平)，header_vld有效(高电平)时对应data_vld无效(低电平)。
在一些实施例中，如图5所示，在缓存第三数据(即步骤S13)的过程中或之后，所述DigRF帧处理方法还可包括以下步骤S14’。
在步骤S14’中,在进行制式切换的情况下，根据每个数据通道当前缓存的第三数据进行组帧。
在步骤S13中，若通道关断，说明出现异常，则进行制式切换，在这种情况下，不用等待数据通道中fifo缓存器缓存的数据量达到存储的上限(即一帧数据的数据量)，就可以读取fifo缓存中当前已经缓存的第三数据，即无论此时fifo缓存中的第三数据是多少都将其读出，并根据读取到的第三数据进行组帧。
在一些实施例中，各种制式的第一数据的负载相同。
在一些实施例中，通过以下方式确定数据通道缓存的第三数据的数量达到一帧数据的数据量：在m个数据通道中，通过轮询的方式确定数据通道缓存的第三数据的数量达到一帧数据的数据量。也就是说，在m个数据通道中进行轮询，依次判断当前数据通道中fifo缓存器缓存的第三数据的数量是否已经达到一帧数据的数据量，如果达到，就针对当前数据通道进行组帧，得到该数据通道的DigRF数据帧；如果未达到，则不针对当前数据通道进行组帧，而是判断下一个数据通道中fifo缓存器缓存的第三数据的数量是否已经达到一帧数据的数据量，以此类推。
在一些实施例中，预设负载的数量为256字节。本公开实施例中固定负载的数量为协议规定的最大负载数量256byte，这种方式带宽利用率最高，传输相同的数据量所用时间更短，芯片进入空闲、休眠状态的时间更长，功耗更小。
本公开实施例可以应用于延时小、由电信号连接的高速串行接口中，在移动终端产品中，射频芯片与终端芯片进行上、下行数据交互，通常采用此类接口。本公开实施例也可应用于基带处理单元或有源天线处理单元中，比如基带处理单元中，两个板卡之间通过高速串行接口进行小区数据调度处理。
基于相同的技术构思，本公开实施例还提供一种DigRF帧处理装置。图6为DigRF帧处理装置的模块示意图，图7为DigRF帧处理装置的结构示意图。
如图6所示，所述DigRF帧处理装置包括通道映射模块101、时钟域转换模块102、位宽转换模块103、缓存模块104和数据处理模块105。
通道映射模块101被配置为接收n路第一数据，将所述n路第一数据中的每一路第一数据映射到m个数据通道中的任一个，其中，m和n为大于2的整数，且n>m。
时钟域转换模块102被配置为对每个所述数据通道的第一数据进行时钟域转换得到第二数据。
位宽转换模块103被配置为将每个所述数据通道的所述第二数据进行位宽转换得到第三数据。
缓存模块104被配置为缓存所述第三数据。
数据处理模块105被配置为在数据通道缓存的所述第三数据的数量达到一帧数据的数据量的情况下，根据所述数据通道缓存的各所述第三数据进行组帧得到DigRF数据帧，所述一帧数据的数据量根据预设负载的数量和物理通道的数量确定。
在一些实施例中，结合图6和图7所示，通道映射模块101为数据选择器MUX1-MUX8,时钟域转换模块102为跨时钟fifo，位宽转换模块103为digrfv4_tx_dlc_splicing模块，缓存模块104为数据缓存fifo，数据处理模块105为digrfv4_tx_dlc_read模块。
在一些实施例中，所述n路第一数据包括多种制式。
在一些实施例中，数据处理模块105还被配置为在缓存模块104缓存所述第三数据之后，在进行制式切换的情况下，根据每个所述数据通道当前缓存的所述第三数据进行组帧。
在一些实施例中，所述第一数据的制式包括以下之一或任意组合：新空口NR、新空口_车用无线通信NR_V2X、长期演进技术LTE、长期演进技术_车用无线通信LTE_V2X、宽带码分多址WCDMA。
在一些实施例中，各种制式的所述第一数据的负载相同。
在一些实施例中，数据处理模块105被配置为通过以下方式确定数据通道缓存的所述第三数据的数量达到一帧数据的数据量：在所述m个数据通道中，通过轮询的方式确定数据通道缓存的所述第三数据的数量达到一帧数据的数据量。
在一些实施例中，所述预设负载的数量为256字节。
本公开实施例还提供了一种计算机设备，该计算机设备包括：一个或多个处理器以及存储装置；其中，存储装置上存储有一个或多个程序，当上述一个或多个程序被上述一个或多个处理器执行时，使得上述一个或多个处理器实现如前述各实施例所提供的DigRF帧处理方法。
本公开实施例还提供了一种计算机可读介质，其上存储有计算机程序，其中，该计算机程序被执行时实现如前述各实施例所提供的DigRF帧处理方法。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其他实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本发明的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种DigRF帧处理方法，包括：
    接收n路第一数据，将所述n路第一数据中的每一路第一数据映射到m个数据通道中的任一个，其中，m和n为大于2的整数，且n>m；
    对每个所述数据通道的第一数据进行时钟域转换得到第二数据；
    将每个所述数据通道的所述第二数据进行位宽转换得到第三数据，并缓存所述第三数据；
    在数据通道缓存的所述第三数据的数量达到一帧数据的数据量的情况下，根据所述数据通道缓存的各所述第三数据进行组帧得到DigRF数据帧，所述一帧数据的数据量根据预设负载的数量和物理通道的数量确定。
  2. 如权利要求1所述的方法，其中，所述n路第一数据包括多种制式。
  3. 如权利要求2所述的方法，其中，在缓存所述第三数据之后，所述方法还包括：
    在进行制式切换的情况下，根据每个所述数据通道当前缓存的所述第三数据进行组帧。
  4. 如权利要求2所述的方法，其中，所述第一数据的制式包括以下之一或任意组合：
    新空口NR、新空口_车用无线通信NR_V2X、长期演进技术LTE、长期演进技术_车用无线通信LTE_V2X、宽带码分多址WCDMA。
  5. 如权利要求2所述的方法，其中，各种制式的所述第一数据的负载相同。
  6. 如权利要求1所述的方法，其中，通过以下方式确定数据通道缓存的所述第三数据的数量达到一帧数据的数据量：
    在所述m个数据通道中，通过轮询的方式确定数据通道缓存的所述第三数据的数量达到一帧数据的数据量。
  7. 如权利要求1-6任一项所述的方法，其中，所述预设负载的数量为256字节。
  8. 一种DigRF帧处理装置，包括通道映射模块、时钟域转换模块、位宽转换模块、缓存模块和数据处理模块，所述通道映射模块被配置为接收n路第一数据，将所述n路第一数据中的每一路第一数据映射到m个数据通道中的任一个，其中，m和n为大于2的整数，且n>m；
    所述时钟域转换模块被配置为对每个所述数据通道的第一数据进行时钟域转换得到第二数据；
    所述位宽转换模块被配置为将每个所述数据通道的所述第二数据进行位宽转换得到第三数据；
    所述缓存模块被配置为缓存所述第三数据；
    所述数据处理模块被配置为在数据通道缓存的所述第三数据的数量达到一帧数据的数据 量的情况下，根据所述数据通道缓存的各所述第三数据进行组帧得到DigRF数据帧，所述一帧数据的数据量根据预设负载的数量和物理通道的数量确定。
  9. 一种计算机设备，包括：
    一个或多个处理器；
    存储装置，其上存储有一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行时，使得所述一个或多个处理器实现如权利要求1-7任一项所述的DigRF帧处理方法。
  10. 一种计算机可读介质，其上存储有计算机程序，其中，所述程序被执行时实现如权利要求1-7任一项所述的DigRF帧处理方法。
PCT/CN2023/110557 2022-08-03 2023-08-01 DigRF帧处理方法、装置、计算机设备及可读介质 WO2024027710A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140126615A1 (en) * 2012-11-06 2014-05-08 Motorola Mobility Llc Synchronizing receive data over a digital radio frequency (rf) interface
CN106294234A (zh) * 2016-08-01 2017-01-04 深圳云天励飞技术有限公司 一种数据传输方法及装置
CN113986792A (zh) * 2021-10-26 2022-01-28 新华三信息安全技术有限公司 一种数据位宽转换方法及通信设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140126615A1 (en) * 2012-11-06 2014-05-08 Motorola Mobility Llc Synchronizing receive data over a digital radio frequency (rf) interface
CN106294234A (zh) * 2016-08-01 2017-01-04 深圳云天励飞技术有限公司 一种数据传输方法及装置
CN113986792A (zh) * 2021-10-26 2022-01-28 新华三信息安全技术有限公司 一种数据位宽转换方法及通信设备

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