WO2024027468A1 - 一种rc振荡器电路 - Google Patents

一种rc振荡器电路 Download PDF

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Publication number
WO2024027468A1
WO2024027468A1 PCT/CN2023/106596 CN2023106596W WO2024027468A1 WO 2024027468 A1 WO2024027468 A1 WO 2024027468A1 CN 2023106596 W CN2023106596 W CN 2023106596W WO 2024027468 A1 WO2024027468 A1 WO 2024027468A1
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Prior art keywords
controllable switch
capacitor array
comparator
control signal
output
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PCT/CN2023/106596
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English (en)
French (fr)
Inventor
马凯
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深圳市中兴微电子技术有限公司
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Publication of WO2024027468A1 publication Critical patent/WO2024027468A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature

Definitions

  • This application relates to the field of wireless sensor technology, specifically to RC oscillator circuits.
  • RC oscillators In order to realize the low-temperature drift characteristics of the RC oscillator, various temperature drift compensation schemes exist. RC oscillators generally use series-parallel networks of resistors and capacitors to achieve frequency selection functions, and resistors and capacitors have temperature coefficients. Under some processes, resistors and capacitors have different temperature characteristics. Through combination, a zero temperature drift coefficient can be achieved, and this coefficient Adjustable to compensate for temperature drift in other parts of the circuit and achieve low temperature drift characteristics. However, in some processes, resistors and capacitors do not have different temperature characteristics, or resistors and capacitors with different temperature coefficients cannot be used, and zero temperature drift coefficient cannot be achieved. The circuit output clock is greatly affected by temperature.
  • An embodiment of the present application provides an RC oscillator circuit, including: a delay loop, a voltage generation circuit and a current generation circuit; wherein the delay loop includes: a first capacitor array, a second capacitor array, a comparator, Inverter module and controllable switch module; the current generation circuit, the voltage generation circuit, the first capacitor array, the second capacitor array, and the first input terminal and the second input terminal of the comparator are respectively connected to the controllable switch module; the output end of the comparator is electrically connected to the inverter module, and the inverter module outputs a first control signal, a second control signal and a clock signal; the first control The signal is inverted with the level of the second control signal; the controllable switch module receives the first level state In the case of the first control signal, the voltage generating circuit is controlled to be conductive with the first input terminal of the comparator, the first capacitor array is controlled to be conductive with the second input terminal of the comparator, and the The current generating circuit is connected to the first capacitor array and charges the first
  • the controllable switch module controls the voltage generation circuit to conduct with the second input end of the comparator, and controls the The second capacitor array is connected to the first input terminal of the comparator, and the current generating circuit is controlled to be connected to the second capacitor array and charged to the second capacitor array, and the second capacitor array is connected to the first input terminal of the comparator.
  • the comparator switches the output state, so that the first control signal, the second control signal and the clock signal output by the inverter module switch states. level state; wherein the first control signal switches from the second level state to the first level state.
  • Figure 1 is a schematic diagram of a capacitor array structure
  • Figure 2 is a structural block diagram of an RC oscillator circuit provided by an embodiment of the present application.
  • Figure 3 is a structural block diagram of an RC oscillator current controlled by a first control signal in a first level state provided by an embodiment of the present application;
  • Figure 4 is a structural block diagram of an RC oscillator current controlled by a second control signal in a first level state provided by an embodiment of the present application;
  • Figure 5 is a structural block diagram of another RC oscillator circuit provided by an embodiment of the present application.
  • Figure 6 is a structural block diagram of yet another RC oscillator circuit provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram between an inverter and a Schmitt trigger provided by an embodiment of the present application
  • Figure 8 is a structural block diagram of yet another RC oscillator circuit provided by an embodiment of the present application.
  • Figure 9 is a structural block diagram of a capacitor array provided by an embodiment of the present application.
  • FIG. 10 is a structural block diagram of a capacitor array subunit provided by an embodiment of the present application.
  • the RC oscillator is used in wireless sensors.
  • the application scenarios of the RC oscillator are explained.
  • Wireless sensors have the advantages of ultra-high computing power, small size and low cost, and are widely used in environmental monitoring, biomedicine and other fields.
  • the miniaturization of the system results in limited system energy storage capacity.
  • the battery capacity is several orders of magnitude smaller than the battery capacity of mobile phones.
  • the low duty cycle wireless sensor network node chip is a typical ultra-low power consumption (Ulra-Low Pover, ULP) system. Its working principle is: first wake up and start the central processor, and then open the analog circuit module to execute the sensing application.
  • the radio frequency module (Radio Freqpency, RF) is used for communication. Each time a module is turned on, the system's power consumption will gradually increase. After completing the RF communication, the system returns to the sleep state area again. During the entire operation, the system uses the Real Time Clock (RTC) module to maintain time.
  • the RTC provides an accurate clock for the chip's wake-up and synchronization.
  • the total power consumption of the system varies depending on the application. If the chip works in active mode, its power consumption is mainly affected by the central processing unit (CPU), analog circuit module and RF module; if the chip works in idle mode , the power consumption of its RTC accounts for the main part, and the idle mode time usually accounts for more than half. In order to reduce power consumption and increase the standby time of the system, the power consumption of the RTC needs to be reduced.
  • Figure 1 is a schematic diagram of a capacitor array structure. As shown in Figure 1, in the adjustable capacitor array technology, when en is 0, the capacitor does not charge; when en is 1, the capacitor C1 is charged, that is, the capacitor size is controlled to C1, so the minimum capacitance Cmin does not This structure cannot be used when the oscillator accuracy requirements are met.
  • quartz crystal oscillators have extremely high frequency stability and are widely used. However, due to the required off-chip components, they are expensive and unavailable. It is conducive to integration, and its power consumption level is generally at uA level; under the requirements of low-power and low-cost design, it cannot meet the demand. However, the RC oscillator has a small area and low cost, is easy to integrate, and the power consumption level can reach nA level, which is especially suitable for this type of Scenes.
  • this application proposes an RC oscillator circuit, which is suitable for wireless sensors and is based on a delay loop, using voltage and current sources and capacitor array calibration to solve the problem of on-chip integration of the oscillator and achieve low power consumption under High-precision, low-temperature drift clock.
  • Embodiments of the present application are applied to wireless sensors.
  • the system In order to reduce the power consumption of wireless sensor network nodes, the system is set to a low duty cycle, that is, with short-term activity, followed by a long-term idle mode to save power.
  • the RC oscillator in the embodiment of this application provides a high-precision, low-temperature drift clock for waking up and synchronizing the system in the idle mode of the wireless sensor.
  • FIG. 2 is a structural block diagram of an RC oscillator circuit provided by an embodiment of the present application. This embodiment is applied to provide high-precision and low-temperature drift clocks in wireless sensors.
  • the RC oscillation circuit in this embodiment includes: a delay loop 10, a voltage generation circuit 20 and a current generation circuit 30; in some embodiments, the delay loop 10 includes: a first capacitor Array 110, second capacitor array 120, comparator 130, inverter module 140 and controllable switch module 150; in some embodiments, the current generation circuit 30, the voltage generation circuit 20, the first capacitor The first input terminal and the second input terminal of the array 110, the second capacitor array 120 and the comparator 130 are respectively connected to the controllable switch module 150; the output terminal of the comparator 130 is connected to the inverting
  • the inverter module 140 is electrically connected, and the inverter module 140 outputs a first control signal, a second control signal and a clock signal; the levels of the first control signal and the second control signal are inverted.
  • FIG. 3 is a structural block diagram of an RC oscillator current controlled by a first control signal in a first level state provided by an embodiment of the present application.
  • the controllable switch module 150 when receiving the first control signal in the first level state, controls the voltage generation circuit 20 and the first input terminal of the comparator 130 to be conductive. to control the first capacitor array 110 and the second input terminal of the comparator 130 to be conductive, and to control the current generating circuit 30 to be conductive to the first capacitor array 110 and to control the first capacitor array 110 to be conductive.
  • the comparator 130 switches the output state, so that the inverter module 140 outputs The first control signal, the second control signal and the clock
  • the signal switches level states; in some embodiments, the second control signal switches from the second level state to the first level state.
  • FIG. 4 is a structural block diagram of an RC oscillator current controlled by a second control signal in a first level state provided by an embodiment of the present application.
  • the controllable switch module 150 controls the voltage generation circuit 20 to conduct with the second input terminal of the comparator 130 . to control the second capacitor array 120 and the first input terminal of the comparator 130 to be conductive, and to control the current generating circuit 30 to be conductive to the second capacitor array 120 and to control the second capacitor array 120 to be conductive.
  • the comparator 130 switches the output state, so that the inverter module 140 outputs The first control signal, the second control signal and the clock signal switch level states; in some embodiments, the first control signal switches from the second level state to the first level state.
  • controllable switch module when the controllable switch module receives the first control signal in the first level state, the controllable switch module also receives the second control signal in the second level state, and controls all the control signals.
  • the voltage generating circuit is disconnected from the second input terminal of the comparator, the second capacitor array is controlled to be disconnected from the first input terminal of the comparator, and the current generating circuit is controlled to be disconnected from the second capacitor.
  • the array is disconnected; when the controllable switch module receives the second control signal in the first level state, the controllable switch module also receives the first control signal in the second level state to control all
  • the voltage generating circuit is disconnected from the first input terminal of the comparator, the first capacitor array is controlled to be disconnected from the second input terminal of the comparator, and the current generating circuit is controlled to be disconnected from the first capacitor.
  • Array disconnected when the controllable switch module receives the second control signal in the first level state, the controllable switch module also receives the first control signal in the second level state to control all
  • the voltage generating circuit is disconnected from the first input terminal of the comparator, the first capacitor array is controlled to be disconnected from the second input terminal of the comparator, and the current generating circuit is controlled to be disconnected from the first capacitor.
  • the first level state refers to a state in which the first control signal or the second control signal is at a high level; the second level state refers to a state in which the first control signal or the second control signal is at a low level. flat state.
  • the first capacitor array 110 and the second capacitor array 120 provide controllable capacitance for the oscillator to achieve frequency control, and the smallest controllable capacitance unit achieves high-precision characteristics.
  • the comparator 130 compares the voltage when the capacitor is charging with the voltage of the voltage generating circuit 20 in real time, and outputs a high level or a low level.
  • the inverter module 140 is used to generate a pair of complementary first control signals enb and second control signals en.
  • the controllable switch module 150 is used to control the comparison according to the first control signal or the second control signal.
  • the two inputs of converter 130 are switched to produce an oscillating signal.
  • the current generating circuit 30 is an adjustable reference current generating circuit ibias, which is used to provide the charging current I for the first capacitor array 110 or the second capacitor array 120, and the temperature drift characteristics of the current can compensate the influence of the capacitor temperature drift on the frequency.
  • the voltage generating circuit 20 is used to provide a stable voltage.
  • FIG. 5 is a structural block diagram of another RC oscillator circuit provided by an embodiment of the present application.
  • the delay loop 10 in this embodiment also includes: a Schmitt trigger 160; the input terminal of the Schmitt trigger 160 is connected to the output terminal of the comparator 130, so The output terminal of the Schmitt trigger 160 is connected to the input terminal of the inverter module 140; the Schmitt trigger 160 is configured to pulse-shape the clock signal output by the comparator 130, and The shaped clock signal is input to the inverter module 140 .
  • glitches may occur when the comparator 130 switches the output state, that is, outputs a transition signal.
  • the Schmitt trigger 160 has a high threshold vh and a low threshold vl. When the input voltage is greater than vh, Output the power supply voltage; when the input voltage is less than vl, output the ground voltage to avoid the influence of burrs.
  • FIG. 6 is a structural block diagram of yet another RC oscillator circuit provided by an embodiment of the present application.
  • the RC oscillator circuit in this embodiment also includes: a digital calibration module 40; in some embodiments, the output end of the inverter module 140 is connected to the input end of the digital calibration module 40 , the digital calibration module 40 is connected to the control end of the first capacitor array 110 and the second capacitor array 120 respectively; the digital calibration module is configured to adjust the oscillation frequency output by the inverter module according to the preset value.
  • the oscillation frequency of the clock signal output by the inverter module 140 is compared with the preset reference frequency to determine the difference between the first capacitor array 110 and the second capacitor array 120 .
  • the capacitance adjustment situation that is, if the oscillation frequency of the clock signal output by the inverter module 140 is greater than the preset reference frequency, then the capacitance values in the first capacitor array 110 and the second capacitor array 120 are increased; on the contrary, if the inverter module 140 If the oscillation frequency of the clock signal output by the module 140 is less than the preset reference frequency, then the The capacitance values in the first capacitor array 110 and the second capacitor array 120 are small.
  • FIG. 7 is a schematic structural diagram between an inverter and a Schmitt trigger provided by an embodiment of the present application.
  • the inverter module in this embodiment at least includes: a first inverter unit, a second inverter unit and a third inverter unit; The input terminal is connected to the output terminal of the Schmitt trigger, the output terminal of the first inverter unit is connected to the input terminal of the second inverter unit, and the output terminal of the second inverter unit The terminal is connected to the input terminal of the third inverter; the first inverter unit is configured to output a first control signal in a first level state, and the second inverter unit is configured to output a second The third inverter unit is configured to output a clock signal of the first control signal and the second control signal in different level states.
  • FIG. 8 is a structural block diagram of yet another RC oscillator circuit provided by an embodiment of the present application.
  • the controllable switch module in this embodiment at least includes: a first controllable switch A, a second controllable switch B, a third controllable switch C, a fourth controllable switch D, a fifth controllable switch Switch E, the sixth controllable switch F, the seventh controllable switch G and the eighth controllable switch H; in some embodiments, the input terminal of the first controllable switch A and the input terminal of the second controllable switch B terminals are all connected to the current generating circuit, and the output terminal of the first controllable switch A, the input terminal of the third controllable switch C and the input terminal of the fourth controllable switch D are all connected to the second terminal of the comparator.
  • the input terminal is connected, and the output terminal of the second controllable switch B, the input terminal of the fifth controllable switch E, and the input terminal of the sixth controllable switch F are all connected to the first input terminal of the comparator, and the The output terminal of the third controllable switch C is connected to the first terminal of the first capacitor array and the input terminal of the seventh controllable switch G; the output terminal of the fourth controllable switch D is connected to the first terminal of the first capacitor array and the input terminal of the seventh controllable switch G.
  • the output terminals of the fifth controllable switch E are connected to the first terminal of the voltage generating circuit; the output terminals of the sixth controllable switch F are respectively connected to the first terminal of the second capacitor array and the eighth terminal.
  • the input terminal of the controllable switch H is connected; the output terminal of the eighth controllable switch H, the second terminal of the second capacitor array, the second terminal of the voltage generating circuit, and the seventh controllable switch G
  • the output terminal and the second terminal of the capacitor array are both grounded;
  • the control terminal of the first controllable switch A, the control terminal of the third controllable switch C, and the control terminal of the fifth controllable switch E and the control terminals of the eighth controllable switch H are used to receive the second control signal;
  • the control terminal of the sixth controllable switch F and the control terminal of the seventh controllable switch G are both used to receive the first control signal.
  • the RC oscillator circuit includes a delay loop, a voltage generating circuit vbias, and an adjustable reference current generating circuit ibias.
  • the delay loop includes a first capacitor array C1, a second capacitor array C2, a comparator, a Schmitt trigger, an inverter, and a switch.
  • the comparator includes two input terminals, respectively a first input terminal (denoted as Vn) and a second input terminal (denoted as Vp).
  • Vn When Vp is connected to the voltage source vbias (that is, the second control signal in the first level state is received), Vn is connected to the second capacitor array C2, the current source ibias charges the second capacitor array C2, and the voltage of Vn changes from 0 When it is larger than vbias, the comparator switches the output state, and a control signal is generated through the Schmitt trigger and inverter to act on the switch. At this time, the Vp voltage of the comparator is reset to 0. Moreover, Vp is connected to the first capacitor array C1, the current source starts to charge the first capacitor array C1, and Vn is connected to the voltage source (that is, the first control signal in the first level state is received), thus repeatedly generating a clock signal with an oscillation frequency. .
  • U is the voltage of vbias
  • I is the current of ibias
  • C is the capacitance of the first capacitor array and the second capacitor array
  • Tdelay is the comparator , delays generated by Schmitt triggers and inverters.
  • the oscillation frequency is adjusted by controlling the capacitance values of the first capacitor array and the second capacitor array, and the minimum controllable capacitance of the capacitor array is reduced to achieve high-precision characteristics. Since the capacitance value changes with temperature, the current source ibis is designed to add control to achieve temperature drift controllable to compensate for the temperature drift of the capacitor and achieve low-temperature drift characteristics of the oscillation frequency.
  • the oscillation period corresponding to the oscillation frequency of the clock signal is based on the voltage value generated by the voltage generating circuit, the current value generated by the current generating circuit, the capacitance value of the capacitor array and a preset value. Delay determination; in some embodiments, the preset delay is the total delay generated by the comparator, the Schmitt trigger and the inverter module.
  • the current generating circuit is an adjustable reference current generating circuit, and the current generated by the adjustable reference current generating circuit corresponds to a positive temperature coefficient.
  • the RC oscillator circuit includes a delay loop, a voltage generating circuit vbias, and an adjustable reference current generating circuit ibias.
  • the delay The loop includes: a first capacitor array C1, a second capacitor array C2, a comparator, a Schmitt trigger, an inverter and a switch.
  • the voltage generation circuit vbias provides a stable low-temperature drift voltage, with a voltage magnitude of about 150 mv.
  • the adjustable reference current generation circuit ibias provides a charging current I of about 500 nA to the first capacitor array C1 and the second capacitor array C2, and the temperature drift characteristics of this current can compensate for the impact of capacitor temperature drift on frequency.
  • the capacitor is a positive temperature coefficient capacitor, that is, the capacitance increases as the temperature increases.
  • the current also needs a positive temperature coefficient current to compensate for the temperature drift of the capacitor.
  • the current temperature drift range is about 0 to 500 ppm, controlled by 5 bits, and the step is about 20 ppm, so that the output frequency temperature drift is less than 50 ppm.
  • the inputs Vp and Vn of the comparator pass through switches respectively and are connected to two capacitor arrays and a voltage generating circuit.
  • the output of the comparator is connected to a Schmitt trigger.
  • the output of the Schmitt trigger is connected to three series inverters, and then generates Oscillator output.
  • the adjustable reference current generating circuit connects two capacitor arrays through switches to charge the capacitors.
  • both the first capacitor array and the second capacitor array include: at least one capacitor array sub-unit; the capacitor array sub-units are connected in parallel; the structures of the capacitor array sub-units are the same .
  • FIG. 9 is a structural block diagram of a capacitor array provided by an embodiment of the present application.
  • the first capacitor array and the second capacitor array both include two capacitor array sub-units as an example to describe the structure of the capacitor array. As shown in Figure 9, the two capacitor array subunits in this embodiment are connected in parallel.
  • Figure 10 is a capacitor array subassembly provided by an embodiment of the present application. Structural block diagram of the unit. As shown in Figure 10, the capacitor array subunit in this embodiment includes: a first capacitor C1, a second capacitor C2, a ninth controllable switch J and a tenth controllable switch K;
  • the first end of the first capacitor C1 is connected to the current generating circuit, the second end of the first capacitor C1 is connected to the first end of the ninth controllable switch J; the second end of the second capacitor C2 The first terminal is respectively connected to the second terminal of the ninth controllable switch J and the first terminal of the tenth controllable switch K.
  • the second terminal of the second capacitor C2 is connected to the second terminal of the tenth controllable switch K.
  • the second terminals of switch K are both grounded.
  • the capacitance values of the first capacitor and the second capacitor are the same.
  • the first capacitor array and the second capacitor array are based on the structure shown in Figure 10.
  • the first capacitor C1 and the second capacitor C2 are about 1fF, achieving a minimum control capacitance of 0.5fF, and a frequency accuracy of about 1Hz.
  • the values of the first capacitor C1 and the second capacitor C2 may also be different, which is not limited and may be adjusted according to actual conditions.

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Abstract

本申请提出一种RC振荡器电路，包括：延时环路、电压产生电路和电流产生电路；延时环路包括：第一电容阵列、第二电容阵列、比较器、反相器模块和可控开关模块；其中，电流产生电路、电压产生电路、第一电容阵列、第二电容阵列以及比较器的第一输入端和第二输入端分别与可控开关模块连接；比较器的输出端与反相器模块电连接，反相器模块输出第一控制信号、第二控制信号和时钟信号。

Description

一种RC振荡器电路
相关申请的交叉引用
本申请要求于2022年8月1日提交的中国专利申请NO.202210918069.7的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本申请涉及无线传感器技术领域，具体涉及RC振荡器电路。
背景技术
为了实现RC振荡器低温漂的特性，存在各种温漂补偿方案。RC振荡器一般使用电阻和电容串并联网络实现选频功能，而电阻和电容具有温度系数，在一些工艺下，电阻和电容具有不同的温度特性，通过组合可实现零温漂系数，并且该系数可调，以补偿电路其他部分温漂，实现低温漂特性。但是，在一些工艺下，电阻和电容不具有不同的温度特性，或者无法使用不同温度系数的电阻和电容，无法实现零温漂系数，电路输出时钟受温度影响很大。
发明内容
本申请实施例提供一种RC振荡器电路，包括：延时环路、电压产生电路和电流产生电路；其中，所述延时环路包括：第一电容阵列、第二电容阵列、比较器、反相器模块和可控开关模块；所述电流产生电路、所述电压产生电路、所述第一电容阵列、所述第二电容阵列以及所述比较器的第一输入端和第二输入端分别与所述可控开关模块连接；所述比较器的输出端与所述反相器模块电连接，所述反相器模块输出第一控制信号、第二控制信号和时钟信号；第一控制信号与第二控制信号的电平反相；所述可控开关模块在接收到第一电平状态下 的第一控制信号的情况下，控制所述电压产生电路与所述比较器的第一输入端导通，控制所述第一电容阵列与所述比较器的第二输入端导通，以及控制所述电流产生电路与所述第一电容阵列导通并对所述第一电容阵列进行充电，并在所述第一电容阵列的电压值大于所述电压产生电路所产生的电压值时，所述比较器切换输出状态，以使所述反相器模块输出的第一控制信号、第二控制信号和时钟信号切换电平状态；其中，第二控制信号由第二电平状态切换为第一电平状态；所述可控开关模块在接收到第一电平状态下的第二控制信号的情况下，控制所述电压产生电路与所述比较器的第二输入端导通，控制所述第二电容阵列与所述比较器的第一输入端导通，以及控制所述电流产生电路与所述第二电容阵列导通并对所述第二电容阵列进行充电，并在所述第二电容阵列的电压值大于所述电压产生电路所产生的电压值时，所述比较器切换输出状态，以使所述反相器模块输出的第一控制信号、第二控制信号和时钟信号切换电平状态；其中，第一控制信号由第二电平状态切换为第一电平状态。
附图说明
图1是一种电容阵列结构的示意图；
图2是本申请实施例提供的一种RC振荡器电路的结构框图；
图3是本申请实施例提供的一种第一电平状态下第一控制信号所控制得到的RC振荡器电流的结构框图；
图4是本申请实施例提供的一种第一电平状态下第二控制信号所控制得到的RC振荡器电流的结构框图；
图5是本申请实施例提供的另一种RC振荡器电路的结构框图；
图6是本申请实施例提供的又一种RC振荡器电路的结构框图；
图7是本申请实施例提供的一种反相器与施密特触发器之间的结构示意图；
图8是本申请实施例提供的又一种RC振荡器电路的结构框图；
图9是本申请实施例提供的一种电容阵列的结构框图；以及
图10是本申请实施例提供的一种电容阵列子单元的结构框图。
具体实施方式
下文中将结合附图对本申请的实施例进行说明。以下结合实施例附图对本申请进行描述，所举实例仅用于解释本申请，并非用于限定本申请的范围。
在本申请实施例中，RC振荡器应用于无线传感器中。为了便于对方案的理解，对RC振荡器的应用场景进行说明。
无线传感器同时具有超高的计算能力和体积小、成本低的优势，被广泛应用于环境监测、生物医学等领域。然而系统的小型化导致了系统能量的存储容量有限，对于无线传感器网络节点来说，其电池的容量比移动电话的电池容量最要小多个数量级。为了降低无线传感器网络节点的功耗，系统会被设置成低占空比，即具有短暂的活动，随后是长时间的空闲模式以节省电能。低占空比的无线传感器网络节点芯片是个典型的超低功耗(Ulra-Low Pover，ULP)系统，其工作原理是：首先唤醒并启动中央处理器，然后打开模拟电路模块执行传感应用，最后用射频模块(Radio Freqpency,RF)来进行通信。每次打开一个模块，系统的功耗会逐步上升。完成RF通信后，系统再次回到睡眠状态区。在整个操作过程中，系统都是使用实时时钟(Real Time Clock，RTC)模块来保持时间，RTC为芯片的唤醒和同步提供了精准的时钟。系统的总功耗因应用而异，如果芯片在激活模式下工作，则其功耗主要受中央处理器(Central Processing Unit，CPU)、模拟电路模块和RF模块等影响；如果芯片工作在空闲模式下，则其RTC的功耗占主要部分，并且空闲模式时间通常占一半以上。为了降低功耗并增加系统的待机时间，需要降低RTC的功耗。
图1是一种电容阵列结构的示意图。如图1所示，在可调电容阵列技术中，在en为0时，电容不充电；在en为1时，电容C1充电，即控制电容大小为C1，所以当工艺下最小电容Cmin也不满足振荡器精度要求时，该结构无法使用。
在众多被作为时钟源的振荡器中，石英晶体振荡器具有极高的频率稳定性，应用广泛，但是由于需要的片外元件价格昂贵，并且不 利于集成，其功耗水平一般在uA级；在低功耗低成本设计要求下，无法满足需求，而RC振荡器面积小成本低，方便集成，功耗水平可达到nA级，特别适合这类场景。
因此，本申请提出一种RC振荡器电路，适用于无线传感器，并基于一个延时环路，采用电压电流源以及电容阵列校准，解决振荡器片上集成的问题，在低功耗要求下，实现高精度低温漂的时钟。本申请实施例应用于无线传感器中，为降低无线传感器网络节点的功耗，系统被设置成低占空比，即具有短暂的活动，随后是长时间的空闲模式以节省电能。本申请实施例中的RC振荡器在无线传感器空闲模式下，提供高精度、低温漂的时钟，用于唤醒和同步系统。
在一实施例中，图2是本申请实施例提供的一种RC振荡器电路的结构框图。本实施例应用于无线传感器中提供高精度和低温漂的时钟。如图2所示，本实施例中的RC振荡电路包括：延时环路10、电压产生电路20和电流产生电路30；在一些实施例中，所述延时环路10包括：第一电容阵列110、第二电容阵列120、比较器130、反相器模块140和可控开关模块150；在一些实施例中，所述电流产生电路30、所述电压产生电路20、所述第一电容阵列110、所述第二电容阵列120以及所述比较器130的第一输入端和第二输入端分别与所述可控开关模块150连接；所述比较器130的输出端与所述反相器模块140电连接，所述反相器模块140输出第一控制信号、第二控制信号和时钟信号；第一控制信号与第二控制信号的电平反相。
图3是本申请实施例提供的一种第一电平状态下第一控制信号所控制得到的RC振荡器电流的结构框图。如图3所示，所述可控开关模块150在接收到第一电平状态下的第一控制信号的情况下，控制所述电压产生电路20与所述比较器130的第一输入端导通，控制所述第一电容阵列110与所述比较器130的第二输入端导通，以及控制所述电流产生电路30与所述第一电容阵列110导通并对所述第一电容阵列110进行充电，并在所述第一电容阵列110的电压值大于所述电压产生电路20所产生的电压值时，所述比较器130切换输出状态，以使所述反相器模块140输出的第一控制信号、第二控制信号和时钟 信号切换电平状态；在一些实施例中，第二控制信号由第二电平状态切换为第一电平状态。
图4是本申请实施例提供的一种第一电平状态下第二控制信号所控制得到的RC振荡器电流的结构框图。如图4所示，所述可控开关模块150在接收到第一电平状态下的第二控制信号的情况下，控制所述电压产生电路20与所述比较器130的第二输入端导通，控制所述第二电容阵列120与所述比较器130的第一输入端导通，以及控制所述电流产生电路30与所述第二电容阵列120导通并对所述第二电容阵列120进行充电，并在所述第二电容阵列120的电压值大于所述电压产生电路20所产生的电压值时，所述比较器130切换输出状态，以使所述反相器模块140输出的第一控制信号、第二控制信号和时钟信号切换电平状态；在一些实施例中，第一控制信号由第二电平状态切换为第一电平状态。
在一实施例中，可控开关模块在接收到第一电平状态下的第一控制信号的情况下，所述可控开关模块还接收到第二电平状态的第二控制信号，控制所述电压产生电路与所述比较器的第二输入端断开，控制所述第二电容阵列与所述比较器的第一输入端断开，以及控制所述电流产生电路与所述第二电容阵列断开；所述可控开关模块在接收到第一电平状态下的第二控制信号的情况下，所述可控开关模块还接收到第二电平状态的第一控制信号，控制所述电压产生电路与所述比较器的第一输入端断开，控制所述第一电容阵列与所述比较器的第二输入端断开，以及控制所述电流产生电路与所述第一电容阵列断开。
在一些实施例中，第一电平状态指的是第一控制信号或第二控制信号处于高电平的状态；第二电平状态指的是第一控制信号或第二控制信号处于低电平的状态。在实施例中，第一电容阵列110和第二电容阵列120为振荡器提供可控的电容，实现频率可控，最小可控电容单元实现高精度特性。比较器130，将电容充电时的电压与电压产出电路20的电压实时比较，输出高电平或者低电平。反相器模块140，作用在于产生一对互补的第一控制信号enb和第二控制信号en。可控开关模块150，作用在于根据第一控制信号或第二控制信号使比较 器130的两个输入发生转换，产生振荡信号。电流产生电路30为可调基准电流产生电路ibias，作用在于为第一电容阵列110或第二电容阵列120提供充电电流I，并且该电流的温漂特性可以补偿电容温漂对频率的影响。电压产生电路20，作用在于提供一个稳定电压。
在一实施例中，图5是本申请实施例提供的另一种RC振荡器电路的结构框图。如图5所示，本实施例中的延时环路10，还包括：施密特触发器160；所述施密特触发器160的输入端与所述比较器130的输出端连接，所述施密特触发器160的输出端与所述反相器模块140的输入端连接；所述施密特触发器160，配置为对所述比较器130输出的时钟信号进行脉冲整形，并将整形之后的时钟信号输入至所述反相器模块140。在一些实施例中，当比较器130切换输出状态，即输出跳变信号时，可能会出现毛刺，施密特触发器160存在一个高阈值vh和一个低阈值vl，当输入电压大于vh时，输出电源电压；当输入电压小于vl时，输出地电压，避免毛刺的影响。
在一实施例中，图6是本申请实施例提供的又一种RC振荡器电路的结构框图。如图6所示，本实施例中的RC振荡器电路还包括：数字校准模块40；在一些实施例中，所述反相器模块140的输出端与所述数字校准模块40的输入端连接，所述数字校准模块40分别与所述第一电容阵列110和所述第二电容阵列120的控制端连接；所述数字校准模块配置为根据所述反相器模块输出的振荡频率与预设参考频率，确定所述第一电容阵列和所述第二电容阵列的目标电容值，并根据所述目标电容值确定所述第一电容阵列和所述第二电容阵列中电容阵列子单元的目标启动个数，以启动所述第一电容阵列和所述第二电容阵列中目标启动个数的电容阵列子单元，以使电容值调整至所述目标电容值。在一些实施例中，通过预先配置一个预设参考频率，将反相器模块140输出的时钟信号的振荡频率与预设参考频率相比较，以确定第一电容阵列110和第二电容阵列120中的电容调整情况，即若反相器模块140输出的时钟信号的振荡频率大于预设参考频率，则增大第一电容阵列110和第二电容阵列120中的电容值；相反，若反相器模块140输出的时钟信号的振荡频率小于预设参考频率，则减 小第一电容阵列110和第二电容阵列120中的电容值。
在一实施例中，图7是本申请实施例提供的一种反相器与施密特触发器之间的结构示意图。如图7所示，本实施例中的所述反相器模块至少包括：第一反相器单元、第二反相器单元和第三反相器单元；所述第一反相器单元的输入端与所述施密特触发器的输出端连接，所述第一反相器单元的输出端与所述第二反相器单元的输入端连接，所述第二反相器单元的输出端与所述第三反相器的输入端连接；所述第一反相器单元配置为输出第一电平状态下的第一控制信号，所述第二反相器单元配置为输出第二电平状态下的第二控制信号，所述第三反相器单元配置为输出第一控制信号和第二控制信号在不同电平状态下的时钟信号。
在一实施例中，图8是本申请实施例提供的又一种RC振荡器电路的结构框图。如图8所示，本实施例中的可控开关模块至少包括：第一可控开关A、第二可控开关B、第三可控开关C、第四可控开关D、第五可控开关E、第六可控开关F、第七可控开关G和第八可控开关H；在一些实施例中，所述第一可控开关A的输入端和第二可控开关B的输入端均与所述电流产生电路连接，所述第一可控开关A的输出端、第三可控开关C的输入端和第四可控开关D的输入端均与所述比较器的第二输入端连接，所述第二可控开关B的输出端、第五可控开关E的输入端和第六可控开关F的输入端均与所述比较器的第一输入端连接，所述第三可控开关C的输出端分别与所述第一电容阵列的第一端连接以及所述第七可控开关G的输入端连接；所述第四可控开关D的输出端和所述第五可控开关E的输出端均与所述电压产生电路的第一端连接；所述第六可控开关F的输出端分别与所述第二电容阵列的第一端和所述第八可控开关H的输入端连接；所述第八可控开关H的输出端、所述第二电容阵列的第二端、所述电压产生电路的第二端、所述第七可控开关G的输出端和所述的一电容阵列的第二端均接地；所述第一可控开关A的控制端、所述第三可控开关C的控制端、第五可控开关E的控制端和第八可控开关H的控制端均用于接收第二控制信号；所述第二可控开关B的控制端、所述第四可控开D关的控制端、 所述第六可控开关F的控制端和第七可控开关G的控制端均用于接收第一控制信号。
在一些实施例中，RC振荡器电路包括一个延时环路和电压产生电路vbias、可调基准电流产生电路ibias。在一些实施例中，延时环路包括第一电容阵列C1、第二电容阵列C2、比较器、施密特触发器、反相器以及开关。在一些实施例中，比较器包括两个输入端，分别为第一输入端(记为Vn)和第二输入端(记为Vp)。在Vp接电压源vbias(即接收到第一电平状态下的第二控制信号)的情况下，Vn接第二电容阵列C2，电流源ibias对第二电容阵列C2充电，Vn的电压从0增大到比vbias大的情况下，比较器切换输出状态，通过施密特触发器和反相器产生控制信号作用于开关，此时，比较器的Vp电压重置为0。并且，Vp接第一电容阵列C1，电流源开始对第一电容阵列C1充电，Vn接电压源(即接收到第一电平状态下的第一控制信号)，如此反复产生振荡频率的时钟信号。
由工作原理可知，振荡周期为T＝2(UC/I+Tdelay)，U为vbias的电压，I为ibias的电流，C为第一电容阵列和第二电容阵列的容值，Tdelay为比较器、施密特触发器和反相器产生的延时。通过控制第一电容阵列和第二电容阵列的电容值大小实现振荡频率调整，减小电容阵列可控的最小电容实现高精度特性。由于电容值随温度变化，电流源ibias设计时添加控制实现温漂可控，以补偿电容的温漂，实现振荡频率低温漂的特性。
在一些实施例中，所述时钟信号的振荡频率对应的振荡周期根据所述电压产生电路所产生的电压值、所述电流产生电路所产生的电流值、所述电容阵列的电容值和预设延时确定；在一些实施例中，所述预设延时为所述比较器、施密特触发器和所述反相器模块所产生的总延时。
在一些实施例中，所述电流产生电路为可调基准电流产生电路，所述可调基准电流产生电路所产生的电流对应的是正温度系数。
在一些实施例中，RC振荡器电路包括一个延时环路和电压产生电路vbias、可调基准电流产生电路ibias。在一些实施例中，延时 环路包括：第一电容阵列C1、第二电容阵列C2、比较器、施密特触发器、反相器以及开关。
在一些实施例中，电压产生电路vbias提供一个稳定的低温漂的电压，电压大小为150mv左右。
可调基准电流产生电路ibias，向第一电容阵列C1和第二电容阵列C2提供充电电流I，大小为500nA左右，并且该电流的温漂特性可以补偿电容温漂对频率的影响。本实施例中，电容为正温度系数电容，即电容大小随温度升高而变大。
根据公式T＝2(UC/I+Tdelay)可知，电流也需正温度系数电流才可与电容温漂相互补偿。在实施例中，电流温漂范围为0～500ppm左右，由5bit控制，step为20ppm左右，实现输出频率温漂小于50ppm。
比较器的输入Vp、Vn分别经过开关，连接两个电容阵列和电压产生电路，比较器的输出连接施密特触发器，施密特触发器的输出连接三个串联的反相器，之后产生振荡器的输出。
可调基准电流产生电路经过开关连接两个电容阵列对电容进行充电。
当en为1时，enb为0，此时Vp接电压源vbias，Vn接电容阵列，电流源ibias对电容阵列充电，Vn的电压从0增大到比vbias大时，比较器输出状态改变，通过施密特触发器和反相器产生控制信号作用于开关，此时，en信号变为0，enb信号为1，比较器的Vp电压重置为0，接电容阵列，电流源开始对其充电，Vn接电压源，如此反复产生振荡频率。
在一些实施例中，第一电容阵列和第二电容阵列，均包括：至少一个电容阵列子单元；所述电容阵列子单元之间采用并联连接方式；所述电容阵列子单元的结构是相同的。
图9是本申请实施例提供的一种电容阵列的结构框图。本实施例中的第一电容阵列和第二电容阵列均包括两个电容阵列子单元为例，对电容阵列的结构进行说明。如图9所示，本实施例中的两个电容阵列子单元以并联进行连接。
在一些实施例中，图10是本申请实施例提供的一种电容阵列子 单元的结构框图。如图10所示，本实施例中的电容阵列子单元包括：第一电容C1、第二电容C2、第九可控开关J和第十可控开关K；
所述第一电容C1的第一端与所述电流产生电路连接，所述第一电容C1的第二端与所述第九可控开关J的第一端连接；所述第二电容C2的第一端分别与所述第九可控开关J的第二端，以及所述第十可控开关K的第一端连接，所述第二电容C2的第二端与所述第十可控开关K的第二端均接地。在一些实施例中，所述第一电容和所述第二电容的电容值是相同的。
在一些实施例中，第一电容阵列和第二电容阵列基于图10所示的结构，第一电容C1和第二电容C2为1fF左右，实现最小控制电容为0.5fF，频率精度为1Hz左右。在一些实施例中，第一电容C1和第二电容C2的取值也可以是不相同的，对此并不进行限定，可根据实际情况进行调整。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种RC振荡器电路，包括：延时环路、电压产生电路和电流产生电路；所述延时环路包括：第一电容阵列、第二电容阵列、比较器、反相器模块和可控开关模块；所述电流产生电路、所述电压产生电路、所述第一电容阵列、所述第二电容阵列以及所述比较器的第一输入端和第二输入端分别与所述可控开关模块连接；所述比较器的输出端与所述反相器模块电连接，所述反相器模块输出第一控制信号、第二控制信号和时钟信号；第一控制信号与第二控制信号的电平反相；其中，
    响应于所述可控开关模块接收到第一电平状态下的第一控制信号，控制所述电压产生电路与所述比较器的第一输入端导通，控制所述第一电容阵列与所述比较器的第二输入端导通，以及控制所述电流产生电路与所述第一电容阵列导通并对所述第一电容阵列进行充电，并在所述第一电容阵列的电压值大于所述电压产生电路所产生的电压值时，所述比较器切换输出状态，以使所述反相器模块输出的第一控制信号、第二控制信号和时钟信号切换电平状态；其中，第二控制信号由第二电平状态切换为第一电平状态；
    响应于所述可控开关模块接收到第一电平状态下的第二控制信号，控制所述电压产生电路与所述比较器的第二输入端导通，控制所述第二电容阵列与所述比较器的第一输入端导通，以及控制所述电流产生电路与所述第二电容阵列导通并对所述第二电容阵列进行充电，并在所述第二电容阵列的电压值大于所述电压产生电路所产生的电压值时，所述比较器切换输出状态，以使所述反相器模块输出的第一控制信号、第二控制信号和时钟信号切换电平状态；其中，第一控制信号由第二电平状态切换为第一电平状态。
  2. 根据权利要求1所述的电路，其中，响应于所述可控开关模块接收到第一电平状态下的第一控制信号以及第二电平状态的第二控制信号，控制所述电压产生电路与所述比较器的第二输入端断开， 控制所述第二电容阵列与所述比较器的第一输入端断开，以及控制所述电流产生电路与所述第二电容阵列断开；
    响应于所述可控开关模块接收到第一电平状态下的第二控制信号以及第二电平状态的第一控制信号，控制所述电压产生电路与所述比较器的第一输入端断开，控制所述第一电容阵列与所述比较器的第二输入端断开，以及控制所述电流产生电路与所述第一电容阵列断开。
  3. 根据权利要求1所述的电路，其中，所述延时环路，还包括：施密特触发器；所述施密特触发器的输入端与所述比较器的输出端连接，所述施密特触发器的输出端与所述反相器模块的输入端连接；
    所述施密特触发器配置为对所述比较器输出的时钟信号进行脉冲整形，并将整形之后的时钟信号输入至所述反相器模块。
  4. 根据权利要求1所述的电路，其中，所述RC振荡器电路还包括：数字校准模块；其中，所述反相器模块的输出端与所述数字校准模块的输入端连接，所述数字校准模块分别与所述第一电容阵列和所述第二电容阵列的控制端连接；
    所述数字校准模块配置为根据所述反相器模块输出的振荡频率与预设参考频率，确定所述第一电容阵列和所述第二电容阵列的目标电容值，并根据所述目标电容值确定所述第一电容阵列和所述第二电容阵列中电容阵列子单元的目标启动个数，以启动所述第一电容阵列和所述第二电容阵列中目标启动个数的电容阵列子单元，以使电容值调整至所述目标电容值。
  5. 根据权利要求3所述的电路，其中，所述反相器模块至少包括：第一反相器单元、第二反相器单元和第三反相器单元；
    所述第一反相器单元的输入端与所述施密特触发器的输出端连接，所述第一反相器单元的输出端与所述第二反相器单元的输入端连接，所述第二反相器单元的输出端与所述第三反相器的输入端连接；
    所述第一反相器单元配置为输出第一电平状态下的第一控制信 号，所述第二反相器单元配置为输出第二电平状态下的第二控制信号，所述第三反相器配置为输出第一控制信号和第二控制信号在不同电平状态下的时钟信号。
  6. 根据权利要求1所述的电路，其中，所述可控开关模块至少包括：第一可控开关、第二可控开关、第三可控开关、第四可控开关、第五可控开关、第六可控开关、第七可控开关和第八可控开关；
    其中，所述第一可控开关的输入端和第二可控开关的输入端均与所述电流产生电路连接，所述第一可控开关的输出端、第三可控开关的输入端和第四可控开关的输入端均与所述比较器的第二输入端连接，所述第二可控开关的输出端、第五可控开关的输入端和第六可控开关的输入端均与所述比较器的第一输入端连接，所述第三可控开关的输出端分别与所述第一电容阵列的第一端连接以及所述第七可控开关的输入端连接；所述第四可控开关的输出端和所述第五可控开关的输出端均与所述电压产生电路的第一端连接；所述第六可控开关的输出端分别与所述第二电容阵列的第一端和所述第八可控开关的输入端连接；所述第八可控开关的输出端、所述第二电容阵列的第二端、所述电压产生电路的第二端、所述第七可控开关的输出端和所述的一电容阵列的第二端均接地；
    所述第一可控开关的控制端、所述第三可控开关的控制端、第五可控开关的控制端和第八可控开关的控制端均用于接收第二控制信号；所述第二可控开关的控制端、所述第四可控开关的控制端、所述第六可控开关的控制端和第七可控开关的控制端均用于接收第一控制信号。
  7. 根据权利要求1所述的电路，其中，所述第一电容阵列和所述第二电容阵列，均包括：至少一个电容阵列子单元；所述电容阵列子单元之间采用并联连接方式；所述电容阵列子单元的结构是相同的。
  8. 根据权利要求7所述的电路，其中，所述电容阵列子单元包 括：第一电容、第二电容、第九可控开关和第十可控开关；
    所述第一电容的第一端与所述电流产生电路连接，所述第一电容的第二端与所述第九可控开关的第一端连接；所述第二电容的第一端分别与所述第九可控开关的第二端，以及所述第十可控开关的第一端连接，所述第二电容的第二端与所述第十可控开关的第二端均接地。
  9. 根据权利要求1所述的电路，其中，所述时钟信号的振荡频率对应的振荡周期根据所述电压产生电路所产生的电压值、所述电流产生电路所产生的电流值、所述电容阵列的电容值和预设延时确定；
    其中，所述预设延时为所述比较器、施密特触发器和所述反相器模块所产生的总延时。
  10. 根据权利要求1所述的电路，其中，所述电流产生电路为可调基准电流产生电路，所述可调基准电流产生电路所产生的电流对应的是正温度系数。
PCT/CN2023/106596 2022-08-01 2023-07-10 一种rc振荡器电路 WO2024027468A1 (zh)

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CN206790441U (zh) * 2017-05-31 2017-12-22 广东工业大学 一种rc振荡器及dc‑dc电源芯片
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