WO2024021163A1

WO2024021163A1 - Burn-in test apparatus and test device

Info

Publication number: WO2024021163A1
Application number: PCT/CN2022/111303
Authority: WO
Inventors: 赵凯
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-07-27
Filing date: 2022-08-10
Publication date: 2024-02-01
Also published as: CN117517919A

Abstract

A burn-in test apparatus (200) and test device. The burn-in test apparatus (200) comprises: a test board (210), on which a chip is placed; and a test circuit (220), which comprises an analog-to-digital conversion module (221), wherein an input end of the analog-to-digital conversion module (221) is used for connecting to a chip pin of a chip, and an output end thereof is used for connecting to an upper computer (300), such that the burn-in test efficiency can be effectively improved.

Description

Collapse test device and test equipment

Cross-references to related applications

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on July 27, 2022, with the application number 2022108906485 and the invention name "Collapse Test Device and Test Equipment", the entire content of which is incorporated into this disclosure by reference. .

Technical field

The present disclosure relates to the technical field of integrated circuit chip testing, and in particular to a collapse test device and testing equipment.

Background technique

Collapse testing is a step used to test product reliability. Collapse testing accelerates the aging of the chip by subjecting it to a high-temperature and high-pressure environment, allowing it to pass through the early failure period in a short period of time and enter a stable accidental failure period. The collapse test takes a long time, and coupled with the necessary heating and cooling time of the test equipment, the overall test time is usually longer.

At the same time, during the collapse test phase, using traditional measurement units to measure the voltage and current signals on the chip will further reduce test efficiency.

Contents of the invention

According to various embodiments of the present disclosure, a collapse testing device and testing equipment are provided.

According to various embodiments of the present disclosure, a collapse test device is provided, including:

Test board, used to place chips;

The test circuit includes an analog-to-digital conversion module, the input end of the analog-to-digital conversion module is used to connect the chip pins of the chip, and the output end is used to connect to the host computer.

According to some embodiments, the test circuit is located on the test board.

According to some embodiments, the test circuit further includes:

A control module is used to receive commands from the host computer and control the test circuit to perform testing.

According to some embodiments, the chip pins include data channel pins, and the analog-to-digital conversion module includes:

The input terminal of the first analog-to-digital conversion unit is used to connect the data channel pins, and the output terminal is used to connect to the host computer.

According to some embodiments,

The test boards include:

A connection module used to connect the data channel pins and test equipment;

The test circuit also includes:

A first switch module is connected to the data channel pin, the first analog-to-digital conversion unit and the connection module, and is used to make the data channel pin connect between the first analog-to-digital conversion unit and the connection module. Switch between connections.

According to some embodiments, the first switch module includes a single pole double throw switch.

According to some embodiments, the chip pins further include chip power pins, and the test circuit further includes:

A second switch module is connected to the first analog-to-digital conversion unit, the data channel pin and the chip power pin, and is used to enable the first analog-to-digital conversion unit to connect between the data channel pin and the chip power pin. Switch connections between chip power pins.

According to some embodiments,

The chip power supply pins include a chip power supply voltage pin and a word line power supply voltage pin, and the chip power supply voltage pin and the word line power supply voltage pin are both connected to the second switch module,

The second switch module is used to enable the first analog-to-digital conversion unit to switch connections between the data channel pin, the chip supply voltage pin, and the word line supply voltage pin.

According to some embodiments, the second switch module includes a single pole three throw switch.

According to some embodiments, the first analog-to-digital conversion unit includes a single-ended input analog-to-digital converter.

According to some embodiments, the chip pins include chip supply voltage pins,

The test circuit includes:

A first sampling resistor, one end of which is used to connect the power supply voltage pin of the chip, and the other end of which is used to connect to the first test voltage of the test equipment;

The analog-to-digital conversion module includes:

The second analog-to-digital conversion unit includes a first differential input terminal, a second differential input terminal, and a first output terminal. The first differential input terminal is connected to one end of the first sampling resistor, and the second differential input terminal is connected to The other end of the first sampling resistor, the output end is used to connect to the host computer.

According to some embodiments, the chip pins further include word line supply voltage pins,

The test circuit also includes:

a second sampling resistor, one end of which is used to connect the word line power supply voltage pin, and the other end of which is used to connect to the second test voltage of the test device;

The analog-to-digital conversion module includes:

The third analog-to-digital conversion unit includes a third input terminal, a fourth input terminal and a second output terminal. The third input terminal is connected to one end of the second sampling resistor, and the fourth input terminal is connected to the second sampling resistor. The other end of the sampling resistor, the second output end is used to connect to the host computer.

According to some embodiments, the test circuit further includes:

A decoding module, connected to the output end of the analog-to-digital conversion module, used to send digital signals to the host computer;

The input terminal of the voltage stabilizing module is used to access the first test voltage of the test equipment, and the output terminal is used to provide voltage for the analog-to-digital conversion module and the decoding module.

According to various embodiments of the present disclosure, a test device is also provided, including:

test chamber;

The collapse test device according to any one of the above is located in the test cavity.

According to some embodiments, the test equipment further includes:

The host computer is connected to the output end of the analog-to-digital conversion module.

Embodiments of the present disclosure may/at least have the following advantages:

The collapse test device and test equipment in the embodiment of the present disclosure convert the analog signals on the chip pins into digital signals by setting up a test circuit including an analog-to-digital conversion module, so that the voltage and/or current on the chip pins can be measured. Conduct fast and efficient testing. Therefore, the embodiments of the present disclosure can effectively improve testing efficiency.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the description of the embodiments or the traditional technology will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of explaining the embodiments or the technical solutions of the traditional technology. For some disclosed embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a partial structural diagram of the test equipment in one embodiment;

Figure 2 is a partial structural block diagram of a collapse response test device in one embodiment;

FIG. 3 is a schematic structural diagram of the test circuit of the collapse test device in one embodiment.

To better describe and illustrate embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed inventions, the embodiments and/or examples presently described, and the best modes currently understood of these inventions.

Explanation of reference signs: 100-test cavity, 200-collapse test device, 210-test board, 211-connection module, 220-test circuit, 221-analog-to-digital conversion module, 221a-first analog-to-digital conversion unit, 221b -The second analog-to-digital conversion unit, 221c-the third analog-to-digital conversion unit, 222-control module, 223-the first switch module, 224-the second switch module, 225-the first sampling resistor, 226-the second sampling resistor, 227-decoding module, 228-voltage stabilizing module, 300-host computer.

Detailed ways

To facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are illustrated in the accompanying drawings. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure.

It will be understood that the terms "first," "second," etc. used in this disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.

It should be noted that when an element is said to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intervening element. In addition, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

As used herein, the singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "comprising" or "having" and the like specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more Possibility of other features, integers, steps, operations, components, parts or combinations thereof.

As mentioned in the background art, during the collapse test phase, using traditional measurement units to measure the voltage and current signals on the chip will further reduce the test efficiency.

Based on the above reasons, the present disclosure provides a chip testing device and testing equipment that can improve chip testing efficiency.

In one embodiment, please refer to FIG. 1 , a test equipment is provided, including a test chamber 100 and a collapse test device 200 . The collapse test device 200 is located in the test chamber 100 .

Specifically, the same test equipment may include multiple test chambers 100 . Each test chamber 100 may be provided with multiple collapse test devices 200 . Each collapse test device 200 may be provided with multiple chips.

In one embodiment, the test equipment may also include a host computer 300 , and the host computer 300 may be connected to the collapse test device 200 to obtain the test results of the collapse test device 200 .

In one embodiment, please refer to FIG. 1 and FIG. 2 , a collapse test device 200 is provided, which includes a test board 210 and a test circuit 220 . The test board 210 and the test circuit 220 are located in the test cavity 100 at the same time. Test board 210 is used to place chips.

Referring to FIG. 2 , the test circuit 220 includes an analog-to-digital conversion module 221 . The input end of the analog-to-digital conversion module 221 is used to connect the chip pins of the chip, so that the analog signals on the chip pins can be input to the analog-to-digital conversion module 221 . The analog-to-digital conversion module 221 can convert analog signals into digital signals. At the same time, the output end of the analog-to-digital conversion module 221 is used to connect to the host computer 300, so that the host computer 300 can obtain the voltage and/or current information on the chip pins of the chip, and thereby obtain the voltage and/or current information on the chip pins of the chip. /or current test results. The host computer 300 may be a computer on the test equipment, or may be a computer outside the test equipment.

Specifically, the test board may include multiple chip placement areas, each chip placement area is used to place one chip, so that multiple chips can be placed on the same test board 210 .

At this time, as an example, a test circuit 220 may be provided on the same test board 210 . At the same time, one of the chips on the same test board 210 can be selected as the chip under test, and the circuit under test 220 tests. At this time, the test results of each chip on the same test board 210 can be represented by the test results of the voltage and/or current on the chip pins of the chip under test on the test board 210 .

Alternatively, multiple test circuits 220 may be provided on the same test board 210 , so that multiple chips can be selected from among the chips on the test board 210 as the chips under test, and the tested circuits 220 can test them.

Specifically, each chip under test can be connected to a test circuit 220 . Each test circuit 220 can test the voltage and/or current on the chip pins of the chip under test connected thereto. The test result data on each chip under test can represent the test data on its related chip.

More specifically, for example, multiple chip placement areas may be arranged in multiple rows and multiple columns, so that individual chips on the same test board 210 are arranged in multiple rows and multiple columns.

For the same power supply voltage provided by the test equipment (such as shared T_VPP and/or T_VDD), a corresponding input terminal can be set in the chip placement area of the same column. At this time, chips in the same column can share the power supply voltage provided by the test equipment (such as sharing T_VPP and/or T_VDD).

At the same time, a test circuit 220 can be provided on one side of the chip placement area of each column. At this time, among the chips in the same column, the chip at the end can be selected as the chip under test. One side of the chip under test may be provided with a test circuit 220 correspondingly connected thereto.

For any chip in the column, the voltage and/or current on the chip pins of the chip under test in the column can be tested through the test circuit 220 corresponding to the chip in the column. The test results of this voltage and/or current can represent the test data on all chips in this column.

Or, as another example, the test board 210 may also include a switching module (not shown). One end of the switching module can be connected to the test circuit 220. At the same time, the other end of the switching module can be connected to the same type of chip pins of at least two chips, so as to enable the test circuit to switch connections between the chips.

At this time, when multiple chips are selected as the chips under test on the same test board 210, at least two chips under test can be connected to the same test circuit 220. Specifically, for example, each chip under test on the same test board 210 may be connected to the same test circuit 220 through a switching module. The test circuit 220 can connect different chips under test at different times.

Specifically, for example, the chip pins may include data channel pins, chip supply voltage pins, and word line supply voltage pins. At this time, the switching module may include a first switching unit, a second switching unit and a third switching unit. The first switching unit, the second switching unit and the third switching unit may include, for example, single-pole multi-throw switches.

One end of the first switching unit can be connected to the test circuit 220, and the other end can be connected to the data channel (DQ) pins of at least two chips, so that the test circuit 220 connected to it can switch connections between the DQ pins of each chip. .

One end of the second switching unit can be connected to the test circuit 220, and the other end can be connected to the chip supply voltage (C_VPP) pins of at least two chips, so that the test circuit 220 connected to it can switch connections between the C_VPP pins of each chip.

One end of the third switching unit can be connected to the test circuit 220, and the other end can be connected to the word line supply voltage (C_VDD) pins of at least two chips, so that the test circuit 220 connected to it can switch connections between the C_VDD pins of each chip. .

When testing a chip under test, the first switching unit, the second switching unit and the third switching unit can be switched to be connected to corresponding chip pins of the chip at the same time.

Alternatively, each chip on the same test board 210 can also be tested by the test circuit 220, which is not limited here.

In this embodiment, a test circuit 220 including an analog-to-digital conversion module 221 is provided to convert analog signals on the chip pins into digital signals, so that the voltage and/or current on the chip pins can be tested quickly and efficiently. Therefore, this embodiment can effectively improve testing efficiency.

In one embodiment, referring to FIG. 2 , the test circuit 220 further includes a control module 222 . The control module 222 is used to receive commands from the host computer 300 and control the test circuit 220 to perform testing. At this time, the host computer 300 is used to obtain test results on the one hand, and send test commands on the other hand.

Specifically, the control module 222 can control the sampling parameters and sampling timing of the analog-to-digital conversion module 221. Among them, the sampling parameters may include sampling frequency, sampling voltage range setting (which will affect the measured voltage accuracy), etc.

In this embodiment, under the control of the control module 222, the test circuit 220 can automatically test the voltage and/or current on the chip pins of the chip through the analog-to-digital conversion module 221. At this time, no manual intervention is required, which can effectively improve test reliability.

In one embodiment, referring to FIG. 1 , test circuit 220 is located on test board 210 .

Placing the test circuit 220 on the test board 210 can reduce the resistance between the chip and the test circuit 220, and facilitate stable and reliable connection between the chip pins of the chip and the input end of the analog-to-digital conversion module 221 of the test circuit 220, thereby effectively Improve the reliability of test results. At the same time, the space of the test board 210 can be effectively utilized at this time.

Specifically, as an example, the test circuit 220 may be disposed in an edge area of the test board 210 . A plurality of grid-shaped chip placement areas may be provided on the test board 210, and each chip placement area may place a chip. The test circuit 220 may be located at the periphery of the grid-shaped chip placement area.

Of course, the test circuit 220 can also be disposed at other locations on the test board 210, and this is not limited here. Alternatively, in some embodiments, the test circuit 220 does not have to be provided on the test board 210 for placing the chip, and it may also be provided on another circuit board independent of the test board 210 .

In one embodiment, referring to Figure 3, the chip pins include data channel (DQ) pins.

Collapse testing requires the application of high pressure and high temperature to the chip. The voltage environment is divided into external chip voltage environment and internal chip voltage environment. The off-chip voltage refers to the power supply voltage provided by the test equipment for the chip (such as the first test voltage T_VPP and/or the second test voltage T_VDD). The intra-chip voltage refers to the voltage on the internal circuit of the chip.

During the collapse response test, the external chip voltage and the internal chip voltage need to be raised at the same time. The voltage outside the chip is raised through test equipment. To increase the voltage within the chip, the chip needs to be configured with relevant test modes. Before mass production of the crash response test, in order to ensure that the test mode configured for the chip can make the voltage within the chip reach an expected voltage value, the voltage within the chip can be detected through the test circuit 220 . At the same time, the voltage within the chip is output through the DQ pin.

Therefore, in this embodiment, the analog-to-digital conversion module 221 includes the first analog-to-digital conversion unit 221a. The input end of the first analog-to-digital conversion unit 221a is used to connect the data channel (DQ) pin of the chip, thereby inputting the analog voltage signal on the DQ pin to the first analog-to-digital conversion unit 221a. At the same time, the input end of the first analog-to-digital conversion unit 221a is used to connect to the host computer 300. The first analog-to-digital conversion unit 221a converts the analog voltage signal into a digital signal and sends it to the host computer 300, so that the voltage value on the DQ pin can be obtained through the host computer 300.

Multiple items (such as about 160 items) of internal chip voltages can be output through the DQ pin. The crash test device of this embodiment can sequentially detect various internal chip voltages output through the DQ pin through the first analog-to-digital conversion unit 221a. Moreover, the test items and test results can be matched one-to-one in the host computer 300, thereby improving the reliability of the entire test item.

In this embodiment, before mass production of the crash test, it can be determined whether the test mode configured for the chip can make the voltage within the chip reach an expected voltage value. When the expected voltage value cannot be reached, the relevant test mode can be adjusted.

In one embodiment, referring to FIG. 3 , the test board 221 includes a connection module 211 . The connection module 211 is used to connect the data channel (DQ) pin at one end. At the same time, the other end of the connection module 211 is connected to the test equipment. As an example, the other end of the connection module 211 can be connected to the test device through the input and output port (T_IO_0) of the test device.

Specifically, the test board 221 may include a test board body, which is used to place chips and may be provided with a circuit structure. The circuit structure may include a connection module 211 . The connection module 211 may include connection pins and terminal matching resistors.

At the same time, the test circuit 220 also includes a first switch module 223.

Before the crash test is mass-produced, after the first analog-to-digital conversion unit 221a tests the data channel (DQ) pin and determines that the internal voltages of each chip have reached the expected voltage value, other items of the crash test can be performed. test. At this time, the test equipment can connect the DQ pin through the connecting pin to supply/measure the digital AC signal of the chip, and at the same time, the signal integrity can be ensured through the terminal matching resistor.

The first switch module 223 connects the data channel (DQ) pin, the first analog-to-digital conversion unit 221a and the connection module 211, and is used to make the data channel (DQ) pin between the first analog-to-digital conversion unit 221a and the connection module 211 Switch connections.

When it is necessary to measure various internal chip voltages through the DQ pin, the first switch module 223 can be controlled to connect the DQ pin and the first analog-to-digital conversion unit 221a. When it is necessary to supply/measure the digital AC signal of the chip through the DQ pin and perform other items of the collapse response test, the first switch module 223 can be controlled to connect the DQ pin and the connection module 211 . Specifically, the connection mode of the first switch module 223 can be controlled through the control module 222 (not shown in Figure 3).

In this embodiment, through the switching function of the first switch module 223, the measurement of various internal chip voltages does not affect the measurement of other items of the collapse response test, thereby not affecting the normal function of the test board 210.

In one embodiment, the first switch module 221a may include a single pole double throw switch. Specifically, the first switch module 221a may also include a relay, for example. At this time, the connection mode of the first switch module 223 can be controlled by controlling the opening and closing of the relay.

Of course, the first switch module 221a can also be in other forms. For example, it may include an NMOS transistor and a PMOS transistor. The control terminals of the NMOS tube and the PMOS tube can be connected to each other. The source terminals of the NMOS tube and PMOS tube are connected to the DQ pin. At the same time, the drain terminal of the NMOS tube can be connected to the first switch module 221a, and the drain terminal of the PMOS tube can be connected to the module 211.

At this time, when a high level signal is applied to the control terminals of the NMOS transistor and the PMOS transistor, the NMOS transistor can be turned on, thereby causing the DQ pin to be electrically connected to the first switch module 221a. When a low-level signal is applied to the control terminals of the NMOS tube and the PMOS tube, the PMOS tube can be turned on, thereby causing the DQ pin to be connected to the connection module 211 .

In one embodiment, referring to FIG. 3, the chip pins also include chip power pins. Test circuit 220 also includes a second switch module 224 . The second switch module 224 is connected to the first analog-to-digital conversion unit 221a, the data channel (DQ) pin and the chip power pin, and is used to enable the first analog-to-digital conversion unit 221a to switch between the data channel (DQ) pin and the chip power pin. Switch between connections.

At this time, when it is necessary to measure the analog voltage signal on the DQ pin through the first analog-to-digital conversion unit 221a, the second switch module 224 can connect the first analog-to-digital conversion unit 221a and the DQ pin. When it is necessary to measure the analog voltage signal on the chip power pin through the first analog-to-digital conversion unit 221a, the second switch module 224 can connect the first analog-to-digital conversion unit 221a and the chip power pin.

The chip power pin is a pin used to receive the power voltage provided by the test device. There can be one pin or multiple pins.

During the crash response test, the test equipment provides power supply voltage to the chip, so that the corresponding chip power pin of the chip obtains the external chip voltage. However, since the power supply voltage provided by the test equipment reaches the chip through a long wire diameter, the power supply voltage provided by the test equipment is not equal to the off-chip voltage actually received by the chip.

Therefore, this embodiment uses the second switch module 224 to enable the first analog-to-digital conversion unit 221a to switch the connection between the data channel (DQ) pin and the chip power pin. On the one hand, various internal chip voltages can be effectively measured. , on the other hand, it can also sample and measure the voltage value on the chip's power pin, thereby effectively measuring whether it meets the power supply demand.

In one embodiment, please refer to FIG. 3 . The chip power supply pins include a chip supply voltage (C_VPP) pin and a word line supply voltage (C_VDD) pin. Of course, the chip power pins may also include other types of power supply voltage pins, which are not limited here.

The test equipment provides the first test voltage T_VPP to the chip, so that the C_VPP pin obtains the chip supply voltage C_VPP. The test equipment provides the second test voltage T_VDD to the chip, so that the C_VDD pin obtains the word line supply voltage C_VDD.

However, the first test voltage T_VPP and the second test voltage T_VDD provided by the test equipment will reach the chip end through a very long wire diameter. Therefore, the voltage value of the first test voltage T_VPP supplied by the test equipment is not equal to the external chip voltage C_VPP actually received by the chip. Similarly, the voltage value of the second test voltage T_VDD supplied by the test equipment is not equal to the external chip voltage C_VDD actually received by the chip.

In this embodiment, both the C_VPP pin and the C_VDD pin are connected to the second switch module 224 . At this time, the second switch module 224 is used to cause the first analog-to-digital conversion unit 221a to switch connections between the DQ pin, the C_VPP pin, and the C_VDD pin. Specifically, the connection mode of the second switch module 224 can be controlled through the control module 222 (not shown in FIG. 3 ).

As an example, the second switch module 224 may include a single pole three throw switch. Of course, it can also be in other forms, and there is no restriction on this here.

In this embodiment, the voltage values on the C_VPP pin and the C_VDD pin can be effectively sampled and measured to determine whether they meet the power supply requirements.

In one embodiment, the first analog-to-digital conversion unit 221a includes a single-ended input analog-to-digital converter.

At this time, the first analog-to-digital conversion unit 221a only needs one input terminal to input an analog voltage signal on a chip pin (such as the DQ pin or the C_VPP pin or the C_VDD pin), that is, its relationship to ground can be measured. voltage value.

Of course, in other embodiments, the first analog-to-digital conversion unit 221a may also be configured as a differential input analog-to-digital converter. At this time, in addition to the input terminal connected to the chip pin, the first analog-to-digital conversion unit 221a may also have another input terminal to input the first known voltage. At this time, the first analog-to-digital conversion unit 221a measures the voltage difference between the chip pin voltage and the known voltage, so that the chip pin voltage can be obtained.

In one embodiment, referring to FIG. 3, the chip pins include a chip supply voltage (C_VPP) pin.

Furthermore, the test circuit 220 includes a first sampling resistor 225 . One end of the first sampling resistor 225 is used to connect the chip supply voltage (C_VPP) pin, and the other end is used to connect the first test voltage T_VPP of the test equipment.

Specifically, the test equipment provides the first test voltage T_VPP to the chip, so that the C_VPP pin obtains the chip supply voltage C_VPP. The first sampling resistor 225 is connected in series between the test device and the C_VPP pin, and has the same current as the C_VPP pin.

Meanwhile, the analog-to-digital conversion module 221 includes a second analog-to-digital conversion unit 221b. The second analog-to-digital conversion unit 221b includes a first differential input terminal, a second differential input terminal, and a first output terminal. The first differential input terminal of the second analog-to-digital conversion unit 221b is connected to one end of the first sampling resistor 225, and the second differential input terminal is connected to the other end of the first sampling resistor 225, so that the voltage difference across the first sampling resistor 225 can be obtained.

At the same time, the first output end of the second analog-to-digital conversion unit 221b is used to connect to the host computer 300.

The second analog-to-digital conversion unit 221b converts the voltage difference across the first sampling resistor 225 into a digital signal and sends it to the host computer 300 . The host computer 300 can calculate and obtain the current on the first sampling resistor 225 through the voltage difference across the first sampling resistor 225 and the resistance of the first sampling resistor 225, thereby obtaining the current value on the C_VPP pin.

In this embodiment, by measuring the voltage difference across the first sampling resistor 225, the current on the C_VPP pin can be calculated and obtained simply and effectively.

At the same time, it is understandable that the first test voltage T_VPP provided by the test equipment will reach the C_VPP pin through a long wire diameter. Therefore, the voltage difference between the two ends of the first sampling resistor 225 is usually larger than the difference between the voltages on the first test voltage T_VPP and C_VPP pins provided by the test equipment.

In this embodiment, the voltage difference across the first sampling resistor 225 can be accurately obtained through the second analog-to-digital conversion unit 221b, thereby accurately obtaining the current value on the C_VPP pin.

In one embodiment, referring to FIG. 3 , the chip pins further include a word line supply voltage (C_VDD) pin.

Furthermore, the test circuit 220 includes a second sampling resistor 226 . One end of the second sampling resistor 226 is used to connect to the word line supply voltage (C_VDD) pin, and the other end is used to connect to the second test voltage T_VDD of the test device.

Specifically, the test equipment provides the second test voltage T_VDD to the chip, so that the C_VDD pin obtains the word line supply voltage C_VDD. The second sampling resistor 226 is connected in series between the test device and the C_VDD pin, and has the same current as the C_VDD pin.

Meanwhile, the analog-to-digital conversion module 221 includes a third analog-to-digital conversion unit 221c. The third analog-to-digital conversion unit 221c includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal of the third analog-to-digital conversion unit 221c is connected to one end of the second sampling resistor 226, and the fourth input terminal is connected to the other end of the first sampling resistor 225, so that the voltage difference across the second sampling resistor 226 can be obtained.

At the same time, the second output end of the third analog-to-digital conversion unit 221c is used to connect to the host computer 300.

The third analog-to-digital conversion unit 221c converts the voltage difference across the second sampling resistor 226 into a digital signal and sends it to the host computer 300 . The host computer 300 can calculate and obtain the current on the second sampling resistor 226 through the voltage difference across the second sampling resistor 226 and the resistance of the second sampling resistor 226, thereby obtaining the current value on the C_VDD pin.

In this embodiment, by measuring the voltage difference across the second sampling resistor 226, the current on the C_VDD pin can be calculated and obtained simply and effectively.

At the same time, it is understandable that the second test voltage T_VDD provided by the test equipment will reach the C_VDD pin through a long wire diameter. Therefore, the voltage difference between the two ends of the second sampling resistor 226 is usually larger than the voltage difference between the second test voltage T_VDD and the C_VDD pin provided by the test equipment.

In this embodiment, the voltage difference across the second sampling resistor 226 can be accurately obtained through the third analog-to-digital conversion unit 221c, thereby accurately obtaining the current value on the C_VDD pin.

It can be understood that in some embodiments, the first sampling resistor, the second analog-to-digital conversion unit 221b, the second sampling resistor, and the third analog-to-digital conversion unit 221c may be provided at the same time.

In one embodiment, please refer to FIG. 3 , the test circuit 220 also includes a decoding module 227 and a voltage stabilizing module 228 .

The decoding module 227 is connected to the output end of the analog-to-digital conversion module 221 for sending digital signals to the host computer 300 .

The decoding module 227 can decode and convert the digital signal output by the analog-to-digital conversion module 221, so that the host computer 300 can obtain the test results.

The input terminal of the decoding module 227 can be connected to the output terminal of the analog-to-digital conversion module 221 . At the same time, the output end of the decoding module 227 can be connected to the host computer 300 .

Specifically, the output ends of the first analog-to-digital conversion unit 221a, the second analog-to-digital conversion unit 221b, and the third analog-to-digital conversion unit 221c may all be connected to the decoding module 227. The host computer 300 can be located on the test equipment. The output end of the decoding module 227 can input digital signals to the host computer 300 through multiple input and output ports of the test equipment (such as T_IO_1, T_IO_2, T_IO_3, and T_IO_4).

The input terminal of the voltage stabilizing module 228 is used to access the first test voltage T_VPP of the test equipment, and the output terminal is used to provide voltage for the analog-to-digital conversion module 221 and the decoding module 227 .

Specifically, the voltage stabilizing module 228 may include a low dropout linear voltage regulator, which provides an operating voltage to the analog-to-digital conversion module 221 and the decoding module 227 after being stabilized by an internal circuit.

In this embodiment, through the setting of the decoding module 227, the host computer 300 can effectively obtain the measurement results of the analog-to-digital conversion module 221. At the same time, the voltage stabilizing module 228 receives the first test voltage T_VPP provided by the test equipment for the C_VPP pin, so that the analog-to-digital conversion module 221 can be effectively powered.

Of course, in other embodiments, the test circuit 220 may not be provided with the voltage stabilizing module 228, but may obtain the voltage through other methods, which is not limited here.

In other embodiments, the test circuit 220 may not be provided with the decoding module 227 , but the analog-to-digital conversion module 221 may be directly connected to the host computer 300 . At this time, for example, a module with a decoding function may be provided on the host computer 300 .

In one embodiment, please refer to FIG. 3 , a collapse test device 200 is provided, including: a test board 210 and a test circuit 220 .

The test board 210 may include a test board body, which is used to place chips and may be provided with a circuit structure. The circuit structure may include a connection module 211 . The connection module 211 may include connection pins and terminal matching resistors. The pins of the chip include: data channel (DQ) pin, chip supply voltage (C_VPP) pin and word line supply voltage (C_VDD) pin.

The test circuit 220 is located on the test board 210 and includes: a first analog-to-digital conversion unit 221a, a second analog-to-digital conversion unit 221b, and a third analog-to-digital conversion unit 221c, a control module 222, a first switch module 223, and a second switch module. 224. The first sampling resistor 225, the second sampling resistor 226, the decoding module 227 and the voltage stabilizing module 228.

The control module 222 is connected to the host computer 300 and is used to control the connection mode of the first switch module 223 and the second switch module 224 according to the command of the host computer 300 . At the same time, the control module 222 can control the sampling parameters and sampling timing of the first analog-to-digital conversion unit 221a, the second analog-to-digital conversion unit 221b, and the third analog-to-digital conversion unit 221c.

The first switch module 223 is connected to the DQ pin, the first analog-to-digital conversion unit 221a and the connection module 211, and is used to switch the DQ pin between the input end of the first analog-to-digital conversion unit 221a and the connection module 211. At the same time, the output end of the first analog-to-digital conversion unit 221a is connected to the host computer 300.

The second switch module 223 is connected to the first analog-to-digital conversion unit 221a, the DQ pin, the C_VPP pin and the C_VDD pin, so that the first analog-to-digital conversion unit 221a is between the DQ pin, the C_VPP pin and the C_VDD pin. Switch connections.

Both ends of the first sampling resistor 225 are respectively connected to the two differential input terminals of the second analog-to-digital conversion unit 221b. At the same time, the output end of the second analog-to-digital conversion unit 221b is connected to the host computer 300 .

Both ends of the second sampling resistor 226 are respectively connected to the two differential input terminals of the third analog-to-digital conversion unit 221c. At the same time, the output end of the third analog-to-digital conversion unit 221c is connected to the host computer 300.

The decoding module 227 can decode and convert the digital signals output from the output terminals of the first analog-to-digital conversion unit 221a, the second analog-to-digital conversion unit 221b, and the third analog-to-digital conversion unit 221c, so that the host computer 300 obtains the test results.

The input terminal of the voltage stabilizing module 228 is used to access the first test voltage T_VPP of the test equipment, and the output terminal is used to provide the first analog-to-digital conversion unit 221a, the second analog-to-digital conversion unit 221b, the third analog-to-digital conversion unit 221c and decoding. Module 227 provides voltage.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage. In the medium, when the computer program is executed, it may include the processes of the embodiments of the above methods. Any reference to memory, storage, database or other media used in the various embodiments provided by the present disclosure may include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RandomAccess Memory, RAM) or external cache memory. By way of illustration and not limitation, RAM can be in many forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM).

In the description of this specification, reference to the terms "some embodiments," "other embodiments," "ideal embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included herein. In at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed should be determined by the appended claims.

Claims

A collapse response testing device, including:

Test board, used to place chips;

The test circuit includes an analog-to-digital conversion module, the input end of the analog-to-digital conversion module is used to connect the chip pins of the chip, and the output end is used to connect to the host computer.
The collapse test device according to claim 1, wherein the test circuit is located on the test board.
The collapse test device according to claim 1, wherein the test circuit further includes:

A control module is used to receive commands from the host computer and control the test circuit to perform testing.
The collapse test device according to claim 1, wherein the chip pins include data channel pins, and the analog-to-digital conversion module includes:

The input terminal of the first analog-to-digital conversion unit is used to connect the data channel pins, and the output terminal is used to connect to the host computer.
The collapse test device according to claim 4, wherein,

The test boards include:

A connection module used to connect the data channel pins and test equipment;

The test circuit also includes:

A first switch module is connected to the data channel pin, the first analog-to-digital conversion unit and the connection module, and is used to make the data channel pin connect between the first analog-to-digital conversion unit and the connection module. Switch between connections.
The collapse test device according to claim 5, wherein the first switch module includes a single-pole double-throw switch.
The collapse test device according to claim 4, wherein the chip pins further include chip power pins, and the test circuit further includes:

A second switch module is connected to the first analog-to-digital conversion unit, the data channel pin and the chip power pin, and is used to enable the first analog-to-digital conversion unit to connect between the data channel pin and the chip power pin. Switch connections between chip power pins.
The collapse test device according to claim 7, wherein,

The chip power supply pins include a chip power supply voltage pin and a word line power supply voltage pin, and the chip power supply voltage pin and the word line power supply voltage pin are both connected to the second switch module,

The second switch module is used to enable the first analog-to-digital conversion unit to switch connections between the data channel pin, the chip supply voltage pin, and the word line supply voltage pin.
The collapse test device according to claim 8, wherein the second switch module includes a single-pole three-throw switch.
The collapse test device according to claim 4, wherein the first analog-to-digital conversion unit includes a single-ended input analog-to-digital converter.
The collapse test device according to any one of claims 1 to 10, wherein the chip pins include chip supply voltage pins,

The test circuit includes:

A first sampling resistor, one end of which is used to connect the power supply voltage pin of the chip, and the other end of which is used to connect to the first test voltage of the test equipment;

The analog-to-digital conversion module includes:

The second analog-to-digital conversion unit includes a first differential input terminal, a second differential input terminal, and a first output terminal. The first differential input terminal is connected to one end of the first sampling resistor, and the second differential input terminal is connected to The other end of the first sampling resistor, the output end is used to connect to the host computer.
The collapse test device according to any one of claims 1 to 10, wherein the chip pins further include word line supply voltage pins,

The test circuit also includes:

a second sampling resistor, one end of which is used to connect the word line power supply voltage pin, and the other end of which is used to connect to the second test voltage of the test device;

The analog-to-digital conversion module includes:

The third analog-to-digital conversion unit includes a third input terminal, a fourth input terminal and a second output terminal. The third input terminal is connected to one end of the second sampling resistor, and the fourth input terminal is connected to the second sampling resistor. The other end of the sampling resistor, the second output end is used to connect to the host computer.
The collapse test device according to claim 11, wherein the test circuit further includes:

A decoding module, connected to the output end of the analog-to-digital conversion module, used to send digital signals to the host computer;

Voltage stabilizing module, the input end is used to access the first test voltage of the test equipment, and the output end is used to provide voltage for the analog-to-digital conversion module and the decoding module.
The collapse test device according to claim 1, wherein,

The test board includes multiple chip placement areas, each chip placement area is used to place one chip; one or more test circuits are provided on the same test board.
The collapse test device according to claim 14, wherein,

A plurality of the chip placement areas are arranged in multiple rows and columns,

For the same power supply voltage, an input terminal is set in the chip placement area of the same column so that the chips in the same column share the power supply voltage;

One side of the chip placement area of each column is provided with one test circuit.
The collapse test device according to claim 1, wherein,

The test board includes multiple chip placement areas, each chip placement area is used to place one chip;

The test board also includes a switching module. One end of the switching module is connected to the test circuit, and the other end is connected to the same chip pins of at least two of the chips, so that the test circuit can be switched between the chips. Switch connections.
The collapse test device according to claim 16, wherein the chip pins include data channel pins, chip supply voltage pins and word line supply voltage pins,

The switching module includes:

A first switching unit, with one end connected to the test circuit and the other end connected to the data channel pins of at least two chips, used to enable the test circuit to switch connections between the data channel pins of each chip;

One end of the second switching unit is connected to the test circuit, and the other end is connected to the chip supply voltage pins of at least two chips, and is used to enable the test circuit to switch connections between the chip supply voltage pins of each chip;

One end of the third switching unit is connected to the test circuit, and the other end is connected to the word line supply voltage pins of at least two chips, and is used to enable the test circuit to switch connections between the word line supply voltage pins of each chip.
A test device including:

test chamber;

The collapse test device according to any one of claims 1 to 17, is located in the test cavity.
The test equipment according to claim 18, further comprising:

The host computer is connected to the output end of the analog-to-digital conversion module.