WO2024018815A1 - Linear power supply circuit and vehicle - Google Patents

Linear power supply circuit and vehicle Download PDF

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Publication number
WO2024018815A1
WO2024018815A1 PCT/JP2023/023128 JP2023023128W WO2024018815A1 WO 2024018815 A1 WO2024018815 A1 WO 2024018815A1 JP 2023023128 W JP2023023128 W JP 2023023128W WO 2024018815 A1 WO2024018815 A1 WO 2024018815A1
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Prior art keywords
power supply
voltage
switch
output
field effect
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PCT/JP2023/023128
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French (fr)
Japanese (ja)
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拓生 ▲高▼橋
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ローム株式会社
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Publication of WO2024018815A1 publication Critical patent/WO2024018815A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • the invention disclosed herein relates to a linear power supply circuit and a vehicle using the same.
  • Linear power supply circuits such as LDO [low drop out] are used as power supply means for various devices.
  • Patent Document 1 discloses a linear power supply circuit capable of high-speed response.
  • the output stage of the linear power supply circuit disclosed in Patent Document 1 is a current mirror circuit including an output transistor. Therefore, in the linear power supply circuit disclosed in Patent Document 1, the gate-source voltage of the output transistor is clamped at the threshold voltage of the field effect transistor paired with the output transistor, and the output transistor cannot be fully turned on. Therefore, the output transistor of the linear power supply circuit disclosed in Patent Document 1 cannot be used as a load switch.
  • the linear power supply circuit disclosed herein includes an output transistor provided between an input terminal configured to receive an input voltage and an output terminal configured to apply an output voltage.
  • a field effect transistor that forms a pair with the output transistor to form a current mirror circuit; a first switch provided between the source of the field effect transistor and the input terminal; and a gate and ground of the field effect transistor. and a second switch provided between the ground terminal and the ground terminal configured to apply a voltage.
  • the vehicle disclosed herein has the linear power supply circuit configured as described above.
  • the output transistor of a linear power supply circuit whose output stage is a current mirror circuit can be used as a load switch.
  • FIG. 1 is a diagram showing a first embodiment of a linear power supply circuit.
  • FIG. 2 is a diagram showing operation modes of the linear power supply circuit shown in FIG. 1.
  • FIG. 3 is a diagram showing a second embodiment of the linear power supply circuit.
  • FIG. 4 is a diagram showing a third embodiment of the linear power supply circuit.
  • FIG. 5 is an external view of the vehicle.
  • a MOS field effect transistor is defined as having a gate structure that is a "layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," “an insulating layer,” and "P-type, A field effect transistor consisting of at least three layers of "N-type or intrinsic semiconductor layers”. That is, the structure of the gate of the MOS field effect transistor is not limited to the three-layer structure of metal, oxide, and semiconductor.
  • the reference voltage refers to a voltage that is constant in an ideal state, and is actually a voltage that may vary slightly due to temperature changes or the like.
  • constant current means a current that is constant in an ideal state, and is actually a current that may vary slightly due to temperature changes and the like.
  • FIG. 1 is a diagram showing a first embodiment of a linear power supply circuit.
  • the linear power supply circuit 11 of the present embodiment includes an output transistor Q7 provided between an input terminal to which an input voltage VIN is applied and an output terminal to which an output voltage VOUT is applied; and a driver that drives the output transistor Q7 based on the difference.
  • the output transistor Q7 is a P-channel MOS field effect transistor.
  • the source of output transistor Q7 is connected to an input terminal to which input voltage VIN is applied.
  • the drain of the output transistor Q7 is connected to the output terminal to which the output voltage VOUT is applied.
  • the driver includes an error amplifier 1, a converter, a current amplifier, a P-channel MOS field effect transistor Q6, and first to third switches SW1 to SW3.
  • the first to third switches SW1 to SW3 are controlled by a control circuit 3 provided in the linear power supply circuit 11.
  • the error amplifier 1 outputs an error voltage according to the difference between the output voltage VOUT and the reference voltage VREF.
  • the output voltage VOUT is supplied to the inverting input terminal of the error amplifier 1, and the reference voltage VREF is supplied to the non-inverting input terminal of the error amplifier 1.
  • a power supply terminal of the error amplifier 1 is connected to an application terminal of the power supply voltage VCC.
  • the converter has a P-channel MOS field effect transistor Q1, and converts a voltage based on the output of the error amplifier 1 into a current.
  • the gate of the P-channel MOS field effect transistor Q1 is connected to the output terminal of the error amplifier 1.
  • the source of P-channel type MOS field effect transistor Q1 is connected to the application terminal of power supply voltage VCC.
  • the current amplifier current amplifies the output of the P-channel MOS field effect transistor Q1.
  • the current amplifier includes a constant current source 2, P-channel MOS field effect transistors Q2 and Q3, and N-channel MOS field effect transistors Q4 and Q5.
  • a first end of the constant current source 2 is connected to the drain of a P-channel MOS field effect transistor Q1.
  • a second end of the constant current source 2 is connected to a ground terminal to which a ground voltage is applied.
  • P-channel type MOS field effect transistors Q2 and Q3 constitute a current source type current mirror circuit.
  • Each source of P-channel type MOS field effect transistors Q2 and Q3 is connected to an application terminal of power supply voltage VCC.
  • Each gate of P-channel type MOS field effect transistors Q2 and Q3 and the drain of P-channel type MOS field effect transistor Q2 are connected to a first end of constant current source 2.
  • the mirror ratio (the size of the output side transistor to the size of the input side transistor) of the current mirror circuit constituted by the P-channel type MOS field effect transistors Q2 and Q3 is M. In order to prevent the pole of the current mirror circuit constituted by the P-channel MOS field effect transistors Q2 and Q3 from approaching the low band as much as possible, M is preferably 5 or less, more preferably 3 or less.
  • the N-channel MOS field effect transistors Q4 and Q5 constitute a current sink type current mirror circuit.
  • the drain of the N-channel MOS field effect transistor Q4 and the gates of the N-channel MOS field effect transistors Q4 and Q5 are connected to the drain of the P-channel MOS field effect transistor Q3.
  • Each source of the N-channel MOS field effect transistors Q4 and Q5 is connected to a ground terminal to which a ground voltage is applied.
  • the mirror ratio (the size of the output side transistor to the size of the input side transistor) of the current mirror circuit constituted by the N-channel type MOS field effect transistors Q4 and Q5 is N. In order to prevent the pole of the current mirror circuit constituted by N-channel MOS field effect transistors Q4 and Q5 from approaching the low band as much as possible, N is preferably 5 or less, more preferably 3 or less.
  • a P-channel MOS field effect transistor Q6 is provided between the current amplifier and the output transistor Q7.
  • P-channel type MOS field effect transistor Q6 forms a pair with output transistor Q7 to form a current source type current mirror circuit.
  • the mirror ratio (the size of the output side transistor to the size of the input side transistor) of the current mirror circuit constituted by the P-channel type MOS field effect transistor Q6 and the output transistor Q7 is 1.
  • the gates of the P-channel MOS field-effect transistor Q6 and the output transistor Q7 and the drain of the P-channel MOS field-effect transistor Q6 are connected to the drain of the N-channel MOS field-effect transistor Q5.
  • the source of the P-channel MOS field effect transistor Q6 is connected to the input terminal to which the input voltage VIN is applied via the first switch SW1.
  • the first switch SW1 is a P-channel MOS field effect transistor.
  • the second switch SW2 is provided between the gate of the P-channel MOS field effect transistor Q6 and a ground terminal configured to apply a ground voltage.
  • a third switch SW3 is connected in parallel to the converter.
  • the third switch SW3 is a P-channel MOS field effect transistor.
  • the gate of the output transistor Q7 is prevented from being clamped at the threshold voltage of the P-channel MOS field effect transistor Q6. Furthermore, in the second operation mode shown in FIG. 2, since the second switch SW2 is on, the ground voltage is supplied to the gate of the output transistor Q7. As a result, the output transistor Q7 is fully turned on. Therefore, when the linear power supply circuit 11 is in the second operation mode shown in FIG. 2, the output transistor Q7 of the linear power supply circuit 11 can be used as a load switch.
  • the current amplifier does not amplify current. That is, in the second operation mode shown in FIG. 2, the current consumption of the linear power supply circuit 11 can be suppressed.
  • the power supply voltage of the current amplifier is the power supply voltage VCC
  • the power supply voltage of the current source type current mirror circuit constituted by the P-channel MOS field effect transistor Q6 and the output transistor Q7 is the input voltage VIN. be. That is, in the linear power supply circuit 11, the power supply voltage of the current amplifier and the power supply voltage of the current source type current mirror circuit constituted by the P-channel MOS field effect transistor Q6 and the output transistor Q7 are different from each other.
  • the linear power supply circuit 11 can suppress the power consumption of the current amplifier.
  • FIG. 3 is a diagram showing a second embodiment of the linear power supply circuit.
  • the power supply terminal of the error amplifier 1, the sources of the P-channel MOS field effect transistors Q1 to Q3, and the third switch SW3 are not applied with the power supply voltage VCC, but are applied with the input voltage VIN.
  • the linear power supply circuit 11 differs from the linear power supply circuit 11 of the first embodiment in that it is connected to the input terminal of the first embodiment, and is the same as the linear power supply circuit 11 of the first embodiment in other respects.
  • the linear power supply circuit 12 the power supply voltage of the current amplifier and the power supply voltage of the current source type current mirror circuit constituted by the P-channel type MOS field effect transistor Q6 and the output transistor Q7 are common. Therefore, the linear power supply circuit 12 does not require a power supply voltage different from the input voltage VIN.
  • FIG. 4 is a diagram showing a third embodiment of the linear power supply circuit.
  • the linear power supply circuit 13 of this embodiment has a configuration in which P-channel type MOS field effect transistors Q8 to Q10, resistors R1 and R2, and a diode D1 are added to the linear power supply circuit 11 of the first embodiment.
  • the breakdown voltages of the N-channel MOS field effect transistors Q4, Q5, and Q10, the breakdown voltages of the P-channel MOS field effect transistors Q6 and Q7, and the breakdown voltage of the second switch SW are different from each other in the error amplifier 1. higher than the withstand voltage of its components.
  • the linear power supply circuit 13 can tolerate an increase in the input voltage VIN.
  • the withstand voltage of N-channel MOS field effect transistors Q4, Q5, and Q10 may be set to 20 [V] or more, and the withstand voltage of P-channel MOS field effect transistors Q6 and Q7 may be set to 20 [V] or more.
  • a current sink type current mirror circuit constituted by N-channel MOS field effect transistors Q8 and Q9 is provided between N-channel MOS field effect transistors Q4 and Q5 and a ground terminal to which a ground voltage is applied.
  • the linear power supply circuit 13 combines N-channel MOS field effect transistors Q4 and Q5, which have a high breakdown voltage, with N-channel MOS field effect transistors Q8 and Q9, which do not have a high breakdown voltage. Thereby, the linear power supply circuit 13 can suppress deterioration in precision of the mirror ratio.
  • a first end of the resistor R1, a first end of the diode D1, and a first end of the resistor R2 are connected to the gate of the first switch SW1.
  • Each second end of the resistor R1 and the diode D1 is connected to an input end to which an input voltage VIN is applied.
  • the second end of resistor R2 is connected to the drain of N-channel MOS field effect transistor Q10.
  • the source of the N-channel MOS field effect transistor Q10 is connected to a ground terminal to which a ground voltage is applied.
  • control circuit 3 indirectly controls the third switch SW3 by controlling the N-channel MOS field effect transistor Q10.
  • FIG. 5 is an external view of vehicle X.
  • the vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving voltage output from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.
  • the electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.).
  • the electronic device X12 is a lamp control unit that performs lighting/extinguishing control for HID [high intensity discharged lamp], DRL [daytime running lamp], and the like.
  • the electronic device X13 is a transmission control unit that performs control related to the transmission.
  • the electronic device X14 is a braking unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).
  • ABS anti-lock brake system
  • EPS electric power steering
  • electronic suspension control etc.
  • the electronic device X15 is a security control unit that controls the drive of door locks, security alarms, etc.
  • Electronic equipment X16 refers to electronic equipment that is installed in vehicle It is.
  • the electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].
  • the electronic device X18 is an electronic device equipped with a high-voltage motor, such as an on-vehicle blower, an oil pump, a water pump, and a battery cooling fan.
  • a high-voltage motor such as an on-vehicle blower, an oil pump, a water pump, and a battery cooling fan.
  • linear power supply circuit described above can be incorporated into any of the electronic devices X11 to X18. Further, the installation location of the linear power supply circuit described above is not limited to vehicles, but may be industrial equipment, consumer equipment, etc.
  • the output voltage VOUT is fed back to the error amplifier 1, but a divided voltage of the output voltage VOUT may be fed back to the error amplifier 1.
  • the current amplifier has two current mirror circuits, but the current amplifier may have three or more current mirror circuits.
  • the linear power supply circuits (11 to 13) described above have output transistors ( Q7), a field effect transistor (Q6) forming a current mirror circuit in pair with the output transistor, and a first switch (SW1) provided between the source of the field effect transistor and the input terminal;
  • This is a configuration (first configuration) including a second switch (SW2) provided between the gate of the field effect transistor and a ground terminal configured to apply a ground voltage.
  • the linear power supply circuit with the first configuration has an output stage that is a current mirror circuit, the output transistor can be used as a load switch.
  • a configuration (second configuration) having two operation modes may also be used.
  • the linear power supply circuit having the second configuration can switch between the original operation of the power supply to stabilize the output voltage and the operation when used as a load switch by switching between the first operation mode and the second operation mode. can.
  • the linear power supply circuit having the first configuration includes a driver configured to drive the output transistor based on a difference between a voltage based on the output voltage and a reference voltage, and the driver is configured to drive the output transistor based on the difference between the voltage based on the output voltage and a reference voltage.
  • an error amplifier (1) configured to output an error voltage according to the difference between the reference voltage and the reference voltage; and an error amplifier (1) configured to convert the voltage based on the output of the error amplifier into a current and output the current.
  • a converter, a current amplifier (2, Q2 to Q5, Q8, Q9) configured to current amplify the output of the converter, and the field effect transistor provided between the current amplifier and the output transistor.
  • the converter may have a configuration (third configuration) including the first switch, the second switch, and a third switch (SW3) connected in parallel to the converter.
  • the linear power supply circuit with the third configuration can suppress current consumption when the output transistor is used as a load switch.
  • the linear power supply circuit having the fourth configuration can switch between the original operation of the power supply to stabilize the output voltage and the operation when used as a load switch by switching between the first operation mode and the second operation mode. can.
  • the power supply voltage of the current amplifier and the power supply voltage of the current mirror circuit may be different from each other (fifth configuration).
  • the linear power supply circuit with the fifth configuration can suppress the power consumption of the current amplifier.
  • the withstand voltage of the field effect transistor, the output transistor, and the second switch is higher than the withstand voltage of the components of the error amplifier (sixth configuration); Good too.
  • the linear power supply circuit with the sixth configuration can tolerate an increase in input voltage.
  • the linear power supply circuit of the third or fourth configuration may have a configuration (seventh configuration) in which the power supply voltage of the current amplifier and the power supply voltage of the current mirror circuit are common.
  • the linear power supply circuit of the seventh configuration does not require a power supply voltage different from the input voltage.
  • the vehicle (X) described above has a configuration (eighth configuration) having a linear power supply circuit having any one of the first to seventh configurations.
  • the output transistor of the linear power supply circuit whose output stage is a current mirror circuit can be used as a load switch.

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  • Physics & Mathematics (AREA)
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Abstract

This linear power supply circuit includes: an output transistor that is provided between an input end configured such that input voltage is applied thereto, and an output end configured such that output voltage is applied thereto; a field effect transistor that forms a pair with the output transistor to constitute a current mirror circuit; a first switch provided between a source of the field effect transistor and the input end; and a second switch provided between a gate of the field effect transistor and a ground end configured such that ground voltage is applied thereto.

Description

リニア電源回路及び車両Linear power supply circuit and vehicle
　本明細書中に開示されている発明は、リニア電源回路及びこれを用いた車両に関する。 The invention disclosed herein relates to a linear power supply circuit and a vehicle using the same.
　ＬＤＯ［low　drop　out］などのリニア電源回路は様々なデバイスの電源手段として用いられている。そして、特許文献１は、高速応答が可能なリニア電源回路を開示している。 Linear power supply circuits such as LDO [low drop out] are used as power supply means for various devices. Patent Document 1 discloses a linear power supply circuit capable of high-speed response.
特開２０２０－７２３９９号公報（図５及び図８Ａ）JP 2020-72399 (Figure 5 and Figure 8A)
　特許文献１で開示されているリニア電源回路の出力段は、出力トランジスタを含むカレントミラー回路である。そのため、特許文献１で開示されているリニア電源回路では、出力トランジスタのゲート－ソース間電圧が出力トランジスタと対となる電界効果トランジスタの閾値電圧でクランプされ、出力トランジスタをフルオンさせることができない。したがって、特許文献１で開示されているリニア電源回路の出力トランジスタは、ロードスイッチとして用いることができない。 The output stage of the linear power supply circuit disclosed in Patent Document 1 is a current mirror circuit including an output transistor. Therefore, in the linear power supply circuit disclosed in Patent Document 1, the gate-source voltage of the output transistor is clamped at the threshold voltage of the field effect transistor paired with the output transistor, and the output transistor cannot be fully turned on. Therefore, the output transistor of the linear power supply circuit disclosed in Patent Document 1 cannot be used as a load switch.
　本明細書中に開示されているリニア電源回路は、入力電圧が印加されるように構成される入力端と出力電圧が印加されるように構成される出力端との間に設けられた出力トランジスタと、前記出力トランジスタと対となってカレントミラー回路を構成する電界効果トランジスタと、前記電界効果トランジスタのソースと前記入力端との間に設けられる第１スイッチと、前記電界効果トランジスタのゲートとグラウンド電圧が印加されるように構成される接地端との間に設けられる第２スイッチと、を有する。 The linear power supply circuit disclosed herein includes an output transistor provided between an input terminal configured to receive an input voltage and an output terminal configured to apply an output voltage. a field effect transistor that forms a pair with the output transistor to form a current mirror circuit; a first switch provided between the source of the field effect transistor and the input terminal; and a gate and ground of the field effect transistor. and a second switch provided between the ground terminal and the ground terminal configured to apply a voltage.
　本明細書中に開示されている車両は、上記構成のリニア電源回路を有する。 The vehicle disclosed herein has the linear power supply circuit configured as described above.
　本明細書中に開示されている発明によれば、出力段がカレントミラー回路であるリニア電源回路の出力トランジスタをロードスイッチとして用いることができる。 According to the invention disclosed in this specification, the output transistor of a linear power supply circuit whose output stage is a current mirror circuit can be used as a load switch.
図１は、リニア電源回路の第１実施形態を示す図である。FIG. 1 is a diagram showing a first embodiment of a linear power supply circuit. 図２は、図１に示すリニア電源回路の動作モードを示す図である。FIG. 2 is a diagram showing operation modes of the linear power supply circuit shown in FIG. 1. 図３は、リニア電源回路の第２実施形態を示す図である。FIG. 3 is a diagram showing a second embodiment of the linear power supply circuit. 図４は、リニア電源回路の第３実施形態を示す図である。FIG. 4 is a diagram showing a third embodiment of the linear power supply circuit. 図５は、車両の外観図である。FIG. 5 is an external view of the vehicle.
　本明細書において、ＭＯＳ（Metal　Oxide　Semiconductor）電界効果トランジスタとは、ゲートの構造が、「導電体または抵抗値が小さいポリシリコン等の半導体からなる層」、「絶縁層」、及び「Ｐ型、Ｎ型、又は真性の半導体層」の少なくとも３層からなる電界効果トランジスタをいう。つまり、ＭＯＳ電界効果トランジスタのゲートの構造は、金属、酸化物、及び半導体の３層構造に限定されない。 In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor is defined as having a gate structure that is a "layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "P-type, A field effect transistor consisting of at least three layers of "N-type or intrinsic semiconductor layers". That is, the structure of the gate of the MOS field effect transistor is not limited to the three-layer structure of metal, oxide, and semiconductor.
　本明細書において基準電圧とは、理想的な状態において一定である電圧を意味しており、実際には温度変化等により僅かに変動し得る電圧である。 In this specification, the reference voltage refers to a voltage that is constant in an ideal state, and is actually a voltage that may vary slightly due to temperature changes or the like.
　本明細書において、定電流とは、理想的な状態において一定である電流を意味しており、実際には温度変化等により僅かに変動し得る電流である。 In this specification, constant current means a current that is constant in an ideal state, and is actually a current that may vary slightly due to temperature changes and the like.
＜第１実施形態＞
　図１は、リニア電源回路の第１実施形態を示す図である。本実施形態のリニア電源回路１１は、入力電圧ＶＩＮが印加される入力端と出力電圧ＶＯＵＴが印加される出力端との間に設けられた出力トランジスタＱ７と、出力電圧ＶＯＵＴと基準電圧ＶＲＥＦとの差に基づいて出力トランジスタＱ７を駆動するドライバと、を有する。 <First embodiment>
FIG. 1 is a diagram showing a first embodiment of a linear power supply circuit. The linear power supply circuit 11 of the present embodiment includes an output transistor Q7 provided between an input terminal to which an input voltage VIN is applied and an output terminal to which an output voltage VOUT is applied; and a driver that drives the output transistor Q7 based on the difference.
　出力トランジスタＱ７は、Ｐチャネル型ＭＯＳ電界効果トランジスタである。出力トランジスタＱ７のソースは、入力電圧ＶＩＮが印加される入力端に接続される。出力トランジスタＱ７のドレインは、出力電圧ＶＯＵＴが印加される出力端に接続される。 The output transistor Q7 is a P-channel MOS field effect transistor. The source of output transistor Q7 is connected to an input terminal to which input voltage VIN is applied. The drain of the output transistor Q7 is connected to the output terminal to which the output voltage VOUT is applied.
　上記ドライバは、誤差増幅器１と、変換器と、電流増幅器と、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６と、第１～第３スイッチＳＷ１～ＳＷ３と、を有する。第１～第３スイッチＳＷ１～ＳＷ３は、リニア電源回路１１に設けられる制御回路３によって制御される。 The driver includes an error amplifier 1, a converter, a current amplifier, a P-channel MOS field effect transistor Q6, and first to third switches SW1 to SW3. The first to third switches SW1 to SW3 are controlled by a control circuit 3 provided in the linear power supply circuit 11.
　誤差増幅器１は、出力電圧ＶＯＵＴと基準電圧ＶＲＥＦとの差に応じた誤差電圧を出力する。出力電圧ＶＯＵＴは誤差増幅器１の反転入力端子に供給され、基準電圧ＶＲＥＦは誤差増幅器１の非反転入力端子に供給される。誤差増幅器１の電源端子は、電源電圧ＶＣＣの印加端に接続される。 The error amplifier 1 outputs an error voltage according to the difference between the output voltage VOUT and the reference voltage VREF. The output voltage VOUT is supplied to the inverting input terminal of the error amplifier 1, and the reference voltage VREF is supplied to the non-inverting input terminal of the error amplifier 1. A power supply terminal of the error amplifier 1 is connected to an application terminal of the power supply voltage VCC.
　上記変換器は、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１を有し、誤差増幅器１の出力に基づく電圧を電流に変換する。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１のゲートは、誤差増幅器１の出力端子に接続される。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１のソースは、電源電圧ＶＣＣの印加端に接続される。 The converter has a P-channel MOS field effect transistor Q1, and converts a voltage based on the output of the error amplifier 1 into a current. The gate of the P-channel MOS field effect transistor Q1 is connected to the output terminal of the error amplifier 1. The source of P-channel type MOS field effect transistor Q1 is connected to the application terminal of power supply voltage VCC.
　上記電流増幅器は、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１の出力を電流増幅する。上記電流増幅器は、定電流源２と、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ２及びＱ３と、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５と、を有する。 The current amplifier current amplifies the output of the P-channel MOS field effect transistor Q1. The current amplifier includes a constant current source 2, P-channel MOS field effect transistors Q2 and Q3, and N-channel MOS field effect transistors Q4 and Q5.
　定電流源２の第１端は、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１のドレインに接続される。定電流源２の第２端は、グラウンド電圧が印加される接地端に接続される。 A first end of the constant current source 2 is connected to the drain of a P-channel MOS field effect transistor Q1. A second end of the constant current source 2 is connected to a ground terminal to which a ground voltage is applied.
　Ｐチャネル型ＭＯＳ電界効果トランジスタＱ２及びＱ３は、電流ソース型のカレントミラー回路を構成する。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ２及びＱ３の各ソースは、電源電圧ＶＣＣの印加端に接続される。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ２及びＱ３の各ゲート並びにＰチャネル型ＭＯＳ電界効果トランジスタＱ２のドレインは、定電流源２の第１端に接続される。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ２及びＱ３によって構成されるカレントミラー回路のミラー比（入力側トランジスタのサイズに対する出力側トランジスタのサイズ）はＭである。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ２及びＱ３によって構成されるカレントミラー回路のポールができるだけ低帯域に寄らないようにするために、Ｍは５以下であることが好ましく、より好ましくは３以下である。 P-channel type MOS field effect transistors Q2 and Q3 constitute a current source type current mirror circuit. Each source of P-channel type MOS field effect transistors Q2 and Q3 is connected to an application terminal of power supply voltage VCC. Each gate of P-channel type MOS field effect transistors Q2 and Q3 and the drain of P-channel type MOS field effect transistor Q2 are connected to a first end of constant current source 2. The mirror ratio (the size of the output side transistor to the size of the input side transistor) of the current mirror circuit constituted by the P-channel type MOS field effect transistors Q2 and Q3 is M. In order to prevent the pole of the current mirror circuit constituted by the P-channel MOS field effect transistors Q2 and Q3 from approaching the low band as much as possible, M is preferably 5 or less, more preferably 3 or less.
　Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５は、電流シンク型のカレントミラー回路を構成する。Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４のドレイン及びＮチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５の各ゲートは、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ３のドレインに接続される。Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５の各ソースは、グラウンド電圧が印加される接地端に接続される。Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５によって構成されるカレントミラー回路のミラー比（入力側トランジスタのサイズに対する出力側トランジスタのサイズ）はＮである。Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５によって構成されるカレントミラー回路のポールができるだけ低帯域に寄らないようにするために、Ｎは５以下であることが好ましく、より好ましくは３以下である。 The N-channel MOS field effect transistors Q4 and Q5 constitute a current sink type current mirror circuit. The drain of the N-channel MOS field effect transistor Q4 and the gates of the N-channel MOS field effect transistors Q4 and Q5 are connected to the drain of the P-channel MOS field effect transistor Q3. Each source of the N-channel MOS field effect transistors Q4 and Q5 is connected to a ground terminal to which a ground voltage is applied. The mirror ratio (the size of the output side transistor to the size of the input side transistor) of the current mirror circuit constituted by the N-channel type MOS field effect transistors Q4 and Q5 is N. In order to prevent the pole of the current mirror circuit constituted by N-channel MOS field effect transistors Q4 and Q5 from approaching the low band as much as possible, N is preferably 5 or less, more preferably 3 or less.
　リニア電源回路１１が図２に示す第１動作モードであるとき、すなわち第１スイッチＳＷ１がオンであり、第２スイッチＳＷ２及び第３スイッチＳＷ３がオフであるとき、上記電流増幅器の出力電流（Ｎチャネル型ＭＯＳ電界効果トランジスタＱ５のドレイン電流）Ｉ５は、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１のドレイン電流Ｉ１と、定電流源から出力される定電流Ｉｃと、ミラー比Ｍ及びＮと、を用いた下記の式で表される。
　Ｉ５＝Ｍ×Ｎ×（Ｉｃ－Ｉ１） When the linear power supply circuit 11 is in the first operation mode shown in FIG. 2, that is, when the first switch SW1 is on and the second switch SW2 and third switch SW3 are off, the output current (N The drain current I5 of the channel type MOS field effect transistor Q5 is calculated using the drain current I1 of the P channel type MOS field effect transistor Q1, the constant current Ic output from the constant current source, and the mirror ratios M and N. It is expressed by the following formula.
I5=M×N×(Ic-I1)
　Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６は、上記電流増幅器と出力トランジスタＱ７との間に設けられる。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６は、出力トランジスタＱ７と対となって電流ソース型のカレントミラー回路を構成する。Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及び出力トランジスタＱ７によって構成されるカレントミラー回路のミラー比（入力側トランジスタのサイズに対する出力側トランジスタのサイズ）は１である。 A P-channel MOS field effect transistor Q6 is provided between the current amplifier and the output transistor Q7. P-channel type MOS field effect transistor Q6 forms a pair with output transistor Q7 to form a current source type current mirror circuit. The mirror ratio (the size of the output side transistor to the size of the input side transistor) of the current mirror circuit constituted by the P-channel type MOS field effect transistor Q6 and the output transistor Q7 is 1.
　Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及び出力トランジスタＱ７の各ゲート並びにＰチャネル型ＭＯＳ電界効果トランジスタＱ６のドレインは、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ５のドレインに接続される。 The gates of the P-channel MOS field-effect transistor Q6 and the output transistor Q7 and the drain of the P-channel MOS field-effect transistor Q6 are connected to the drain of the N-channel MOS field-effect transistor Q5.
　Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６のソースは、第１スイッチＳＷ１を介して、入力電圧ＶＩＮが印加される入力端に接続される。第１スイッチＳＷ１は、Ｐチャネル型ＭＯＳ電界効果トランジスタである。 The source of the P-channel MOS field effect transistor Q6 is connected to the input terminal to which the input voltage VIN is applied via the first switch SW1. The first switch SW1 is a P-channel MOS field effect transistor.
　第２スイッチＳＷ２は、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６のゲートとグラウンド電圧が印加されるように構成される接地端との間に設けられる。第３スイッチＳＷ３は、前記変換器に並列接続される。第３スイッチＳＷ３は、Ｐチャネル型ＭＯＳ電界効果トランジスタである。 The second switch SW2 is provided between the gate of the P-channel MOS field effect transistor Q6 and a ground terminal configured to apply a ground voltage. A third switch SW3 is connected in parallel to the converter. The third switch SW3 is a P-channel MOS field effect transistor.
　図２に示す第２動作モードでは、第１スイッチＳＷ１がオフであるため、出力トランジスタＱ７のゲートがＰチャネル型ＭＯＳ電界効果トランジスタＱ６のしきい値電圧でクランプされることが防止される。また、図２に示す第２動作モードでは、第２スイッチＳＷ２がオンであるため、出力トランジスタＱ７のゲートにグラウンド電圧が供給される。その結果、出力トランジスタＱ７はフルオンする。したがって、リニア電源回路１１が図２に示す第２動作モードであるとき、リニア電源回路１１の出力トランジスタＱ７をロードスイッチとして用いることができる。 In the second operation mode shown in FIG. 2, since the first switch SW1 is off, the gate of the output transistor Q7 is prevented from being clamped at the threshold voltage of the P-channel MOS field effect transistor Q6. Furthermore, in the second operation mode shown in FIG. 2, since the second switch SW2 is on, the ground voltage is supplied to the gate of the output transistor Q7. As a result, the output transistor Q7 is fully turned on. Therefore, when the linear power supply circuit 11 is in the second operation mode shown in FIG. 2, the output transistor Q7 of the linear power supply circuit 11 can be used as a load switch.
　さらに、図２に示す第２動作モードでは、第３スイッチＳＷ３がオンであるため、第３スイッチＳＷ３に電流が流れてＰチャネル型ＭＯＳ電界効果トランジスタＱ１及びＱ２に電流が流れなくなる。したがって、図２に示す第２動作モードでは、上記電流増幅器は電流を増幅しない。つまり、図２に示す第２動作モードでは、リニア電源回路１１の消費電流を抑制することができる。 Furthermore, in the second operation mode shown in FIG. 2, since the third switch SW3 is on, current flows through the third switch SW3 and no current flows through the P-channel MOS field effect transistors Q1 and Q2. Therefore, in the second mode of operation shown in FIG. 2, the current amplifier does not amplify current. That is, in the second operation mode shown in FIG. 2, the current consumption of the linear power supply circuit 11 can be suppressed.
　リニア電源回路１１では、上記電流増幅器の電源電圧は電源電圧ＶＣＣであり、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及び出力トランジスタＱ７によって構成される電流ソース型のカレントミラー回路の電源電圧は入力電圧ＶＩＮである。つまり、リニア電源回路１１では、上記電流増幅器の電源電圧と、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及び出力トランジスタＱ７によって構成される電流ソース型のカレントミラー回路の電源電圧とは、互いに異なる。 In the linear power supply circuit 11, the power supply voltage of the current amplifier is the power supply voltage VCC, and the power supply voltage of the current source type current mirror circuit constituted by the P-channel MOS field effect transistor Q6 and the output transistor Q7 is the input voltage VIN. be. That is, in the linear power supply circuit 11, the power supply voltage of the current amplifier and the power supply voltage of the current source type current mirror circuit constituted by the P-channel MOS field effect transistor Q6 and the output transistor Q7 are different from each other.
　したがって、電源電圧ＶＣＣが入力電圧ＶＩＮよりも低い電圧に設定されることで、リニア電源回路１１は、上記電流増幅器の消費電力を抑制することができる。 Therefore, by setting the power supply voltage VCC to a voltage lower than the input voltage VIN, the linear power supply circuit 11 can suppress the power consumption of the current amplifier.
＜第２実施形態＞
　図３は、リニア電源回路の第２実施形態を示す図である。本実施形態のリニア電源回路１２は、誤差増幅器１の電源端子、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ１～Ｑ３及び第３スイッチＳＷ３の各ソースは、電源電圧ＶＣＣの印加端でなく入力電圧ＶＩＮが印加される入力端に接続される点で、第１実施形態のリニア電源回路１１と異なり、それ以外の点で第１実施形態のリニア電源回路１１と同様である。 <Second embodiment>
FIG. 3 is a diagram showing a second embodiment of the linear power supply circuit. In the linear power supply circuit 12 of this embodiment, the power supply terminal of the error amplifier 1, the sources of the P-channel MOS field effect transistors Q1 to Q3, and the third switch SW3 are not applied with the power supply voltage VCC, but are applied with the input voltage VIN. The linear power supply circuit 11 differs from the linear power supply circuit 11 of the first embodiment in that it is connected to the input terminal of the first embodiment, and is the same as the linear power supply circuit 11 of the first embodiment in other respects.
　リニア電源回路１２では、上記電流増幅器の電源電圧と、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及び出力トランジスタＱ７によって構成される電流ソース型のカレントミラー回路の電源電圧とは、共通である。したがって、リニア電源回路１２では、入力電圧ＶＩＮと異なる電源電圧が不要となる。 In the linear power supply circuit 12, the power supply voltage of the current amplifier and the power supply voltage of the current source type current mirror circuit constituted by the P-channel type MOS field effect transistor Q6 and the output transistor Q7 are common. Therefore, the linear power supply circuit 12 does not require a power supply voltage different from the input voltage VIN.
＜第３実施形態＞
　図４は、リニア電源回路の第３実施形態を示す図である。本実施形態のリニア電源回路１３は、第１実施形態のリニア電源回路１１にＰチャネル型ＭＯＳ電界効果トランジスタＱ８～Ｑ１０と、抵抗Ｒ１及びＲ２と、ダイオードＤ１と、を追加した構成である。 <Third embodiment>
FIG. 4 is a diagram showing a third embodiment of the linear power supply circuit. The linear power supply circuit 13 of this embodiment has a configuration in which P-channel type MOS field effect transistors Q8 to Q10, resistors R1 and R2, and a diode D1 are added to the linear power supply circuit 11 of the first embodiment.
　また、リニア電源回路１３では、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４、Ｑ５、及びＱ１０の耐圧と、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及びＱ７の耐圧と、第２スイッチＳＷの耐圧とが誤差増幅器１の構成部品の耐圧よりも高い。これにより、リニア電源回路１３は、入力電圧ＶＩＮが高くなることを許容することができる。例えば、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４、Ｑ５、及びＱ１０の耐圧を２０［Ｖ］以上とし、Ｐチャネル型ＭＯＳ電界効果トランジスタＱ６及びＱ７の耐圧を２０［Ｖ］以上とすればよい。 Furthermore, in the linear power supply circuit 13, the breakdown voltages of the N-channel MOS field effect transistors Q4, Q5, and Q10, the breakdown voltages of the P-channel MOS field effect transistors Q6 and Q7, and the breakdown voltage of the second switch SW are different from each other in the error amplifier 1. higher than the withstand voltage of its components. Thereby, the linear power supply circuit 13 can tolerate an increase in the input voltage VIN. For example, the withstand voltage of N-channel MOS field effect transistors Q4, Q5, and Q10 may be set to 20 [V] or more, and the withstand voltage of P-channel MOS field effect transistors Q6 and Q7 may be set to 20 [V] or more.
　Ｎチャネル型ＭＯＳ電界効果トランジスタＱ８及びＱ９によって構成される電流シンク型のカレントミラー回路は、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５と、グラウンド電圧が印加される接地端との間に設けられる。 A current sink type current mirror circuit constituted by N-channel MOS field effect transistors Q8 and Q9 is provided between N-channel MOS field effect transistors Q4 and Q5 and a ground terminal to which a ground voltage is applied.
　耐圧が高いＮチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５のみではミラー比の精度が悪化する。そこで、リニア電源回路１３は、耐圧が高いＮチャネル型ＭＯＳ電界効果トランジスタＱ４及びＱ５に、耐圧が高くないＮチャネル型ＭＯＳ電界効果トランジスタＱ８及びＱ９を組み合わせている。これにより、リニア電源回路１３は、ミラー比の精度悪化を抑制することができる。 If only N-channel type MOS field effect transistors Q4 and Q5 with high breakdown voltage are used, the precision of the mirror ratio will deteriorate. Therefore, the linear power supply circuit 13 combines N-channel MOS field effect transistors Q4 and Q5, which have a high breakdown voltage, with N-channel MOS field effect transistors Q8 and Q9, which do not have a high breakdown voltage. Thereby, the linear power supply circuit 13 can suppress deterioration in precision of the mirror ratio.
　抵抗Ｒ１の第１端、ダイオードＤ１の第１端、及び抵抗Ｒ２の第１端は、第１スイッチＳＷ１のゲートに接続される。抵抗Ｒ１及びダイオードＤ１の各第２端は、入力電圧ＶＩＮが印加される入力端に接続される。抵抗Ｒ２の第２端は、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ１０のドレインに接続される。Ｎチャネル型ＭＯＳ電界効果トランジスタＱ１０のソースは、グラウンド電圧が印加される接地端に接続される。 A first end of the resistor R1, a first end of the diode D1, and a first end of the resistor R2 are connected to the gate of the first switch SW1. Each second end of the resistor R1 and the diode D1 is connected to an input end to which an input voltage VIN is applied. The second end of resistor R2 is connected to the drain of N-channel MOS field effect transistor Q10. The source of the N-channel MOS field effect transistor Q10 is connected to a ground terminal to which a ground voltage is applied.
　リニア電源回路１３では、制御回路３は、Ｎチャネル型ＭＯＳ電界効果トランジスタＱ１０を制御することで間接的に第３スイッチＳＷ３を制御する。 In the linear power supply circuit 13, the control circuit 3 indirectly controls the third switch SW3 by controlling the N-channel MOS field effect transistor Q10.
＜用途＞
　図５は、車両Ｘの外観図である。本構成例の車両Ｘは、不図示のバッテリから出力される電圧の供給を受けて動作する種々の電子機器Ｘ１１～Ｘ１８を搭載している。なお、本図における電子機器Ｘ１１～Ｘ１８の搭載位置は、図示の便宜上、実際とは異なる場合がある。 <Application>
FIG. 5 is an external view of vehicle X. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving voltage output from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.
　電子機器Ｘ１１は、エンジンに関連する制御（インジェクション制御、電子スロットル制御、アイドリング制御、酸素センサヒータ制御、及び、オートクルーズ制御など）を行うエンジンコントロールユニットである。 The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.).
　電子機器Ｘ１２は、ＨＩＤ［high　intensity　discharged　lamp］やＤＲＬ［daytime　running　lamp］などの点消灯制御を行うランプコントロールユニットである。 The electronic device X12 is a lamp control unit that performs lighting/extinguishing control for HID [high intensity discharged lamp], DRL [daytime running lamp], and the like.
　電子機器Ｘ１３は、トランスミッションに関連する制御を行うトランスミッションコントロールユニットである。 The electronic device X13 is a transmission control unit that performs control related to the transmission.
　電子機器Ｘ１４は、車両Ｘの運動に関連する制御（ＡＢＳ［anti-lock　brake　system］制御、ＥＰＳ［electric　power　steering］制御、電子サスペンション制御など）を行う制動ユニットである。 The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).
　電子機器Ｘ１５は、ドアロックや防犯アラームなどの駆動制御を行うセキュリティコントロールユニットである。 The electronic device X15 is a security control unit that controls the drive of door locks, security alarms, etc.
　電子機器Ｘ１６は、ワイパー、電動ドアミラー、パワーウィンドウ、ダンパー（ショックアブソーバー）、電動サンルーフ、及び、電動シートなど、標準装備品やメーカーオプション品として、工場出荷段階で車両Ｘに組み込まれている電子機器である。 Electronic equipment X16 refers to electronic equipment that is installed in vehicle It is.
　電子機器Ｘ１７は、車載Ａ／Ｖ［audio/visual］機器、カーナビゲーションシステム、及び、ＥＴＣ［electronic　toll　collection　system］など、ユーザオプション品として任意で車両Ｘに装着される電子機器である。 The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].
　電子機器Ｘ１８は、車載ブロア、オイルポンプ、ウォーターポンプ、バッテリ冷却ファンなど、高耐圧系モータを備えた電子機器である。 The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an on-vehicle blower, an oil pump, a water pump, and a battery cooling fan.
　なお、先に説明したリニア電源回路は、電子機器Ｘ１１～Ｘ１８のいずれにも組み込むことが可能である。また、先に説明したリニア電源回路の搭載先は、車両に限定されず、産業機器、民生機器等であってもよい。 Note that the linear power supply circuit described above can be incorporated into any of the electronic devices X11 to X18. Further, the installation location of the linear power supply circuit described above is not limited to vehicles, but may be industrial equipment, consumer equipment, etc.
＜その他＞
　上記実施形態は、全ての点で例示であって、制限的なものではないと考えられるべきであり、本発明の技術的範囲は、上記実施形態の説明ではなく、特許請求の範囲によって示されるものであり、特許請求の範囲と均等の意味及び範囲内に属する全ての変更が含まれると理解されるべきである。 <Others>
The above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims rather than the description of the above embodiments. It should be understood that all changes that come within the meaning and range of equivalence of the claims are included.
　例えば上記実施形態では、出力電圧ＶＯＵＴが誤差増幅器１に帰還されているが、出力電圧ＶＯＵＴの分圧が誤差増幅器１に帰還されてもよい。 For example, in the above embodiment, the output voltage VOUT is fed back to the error amplifier 1, but a divided voltage of the output voltage VOUT may be fed back to the error amplifier 1.
　また例えば上記実施形態では、上記電流増幅器は２つのカレントミラー回路を有するが、上記電流増幅器は３つ以上のカレントミラー回路を有してもよい。 Also, for example, in the above embodiment, the current amplifier has two current mirror circuits, but the current amplifier may have three or more current mirror circuits.
　以上説明したリニア電源回路（１１～１３）は、入力電圧が印加されるように構成される入力端と出力電圧が印加されるように構成される出力端との間に設けられた出力トランジスタ（Ｑ７）と、前記出力トランジスタと対となってカレントミラー回路を構成する電界効果トランジスタ（Ｑ６）と、前記電界効果トランジスタのソースと前記入力端との間に設けられる第１スイッチ（ＳＷ１）と、前記電界効果トランジスタのゲートとグラウンド電圧が印加されるように構成される接地端との間に設けられる第２スイッチ（ＳＷ２）と、を有する構成（第１の構成）である。 The linear power supply circuits (11 to 13) described above have output transistors ( Q7), a field effect transistor (Q6) forming a current mirror circuit in pair with the output transistor, and a first switch (SW1) provided between the source of the field effect transistor and the input terminal; This is a configuration (first configuration) including a second switch (SW2) provided between the gate of the field effect transistor and a ground terminal configured to apply a ground voltage.
　上記第１の構成のリニア電源回路は、出力段がカレントミラー回路であるにもかかわらず、出力トランジスタをロードスイッチとして用いることができる。 Although the linear power supply circuit with the first configuration has an output stage that is a current mirror circuit, the output transistor can be used as a load switch.
　上記第１の構成のリニア電源回路において、前記第１スイッチをオンし、前記第２スイッチをオフにする第１動作モードと、前記第１スイッチをオフし、前記第２スイッチをオンにする第２動作モードと、を有する構成（第２の構成）であってもよい。 In the linear power supply circuit having the first configuration, a first operation mode in which the first switch is turned on and the second switch turned off; and a first operation mode in which the first switch is turned off and the second switch is turned on. A configuration (second configuration) having two operation modes may also be used.
　上記第２の構成のリニア電源回路は、第１動作モードと第２動作モードとの切替によって、出力電圧を安定化させる電源本来の動作と、ロードスイッチとして用いられる場合の動作とを切り替えることができる。 The linear power supply circuit having the second configuration can switch between the original operation of the power supply to stabilize the output voltage and the operation when used as a load switch by switching between the first operation mode and the second operation mode. can.
　上記第１の構成のリニア電源回路において、前記出力電圧に基づく電圧と基準電圧との差に基づいて前記出力トランジスタを駆動するように構成されるドライバを有し、前記ドライバは、前記出力電圧に基づく電圧と前記基準電圧との差に応じた誤差電圧を出力するように構成される誤差増幅器（１）と、前記誤差増幅器の出力に基づく電圧を電流に変換して出力するように構成される変換器と、前記変換器の出力を電流増幅するように構成される電流増幅器（２、Ｑ２～Ｑ５、Ｑ８、Ｑ９）と、前記電流増幅器と前記出力トランジスタとの間に設けられる前記電界効果トランジスタと、前記第１スイッチと、前記第２スイッチと、前記変換器に並列接続される第３スイッチ（ＳＷ３）と、を有する構成（第３の構成）であってもよい。 The linear power supply circuit having the first configuration includes a driver configured to drive the output transistor based on a difference between a voltage based on the output voltage and a reference voltage, and the driver is configured to drive the output transistor based on the difference between the voltage based on the output voltage and a reference voltage. an error amplifier (1) configured to output an error voltage according to the difference between the reference voltage and the reference voltage; and an error amplifier (1) configured to convert the voltage based on the output of the error amplifier into a current and output the current. a converter, a current amplifier (2, Q2 to Q5, Q8, Q9) configured to current amplify the output of the converter, and the field effect transistor provided between the current amplifier and the output transistor. The converter may have a configuration (third configuration) including the first switch, the second switch, and a third switch (SW3) connected in parallel to the converter.
　上記第３の構成のリニア電源回路は、出力トランジスタがロードスイッチとして用いられているときの消費電流を抑制することができる。 The linear power supply circuit with the third configuration can suppress current consumption when the output transistor is used as a load switch.
　上記第３の構成のリニア電源回路において、前記第１スイッチをオンし、前記第２スイッチ及び前記第３スイッチをオフにする第１動作モードと、前記第１スイッチをオフし、前記第２スイッチ及び前記第３スイッチをオンにする第２動作モードと、を有する構成（第４の構成）であってもよい。 In the linear power supply circuit having the third configuration, a first operation mode in which the first switch is turned on and the second switch and the third switch are turned off; and a second operation mode in which the third switch is turned on (fourth configuration).
　上記第４の構成のリニア電源回路は、第１動作モードと第２動作モードとの切替によって、出力電圧を安定化させる電源本来の動作と、ロードスイッチとして用いられる場合の動作とを切り替えることができる。 The linear power supply circuit having the fourth configuration can switch between the original operation of the power supply to stabilize the output voltage and the operation when used as a load switch by switching between the first operation mode and the second operation mode. can.
　上記第３又は第４の構成のリニア電源回路において、前記電流増幅器の電源電圧と前記カレントミラー回路の電源電圧とが互いに異なる構成（第５の構成）であってもよい。 In the linear power supply circuit of the third or fourth configuration, the power supply voltage of the current amplifier and the power supply voltage of the current mirror circuit may be different from each other (fifth configuration).
　上記第５の構成のリニア電源回路は、電流増幅器の消費電力を抑制することができる。 The linear power supply circuit with the fifth configuration can suppress the power consumption of the current amplifier.
　上記第５の構成のリニア電源回路において、前記電界効果トランジスタ、前記出力トランジスタ、及び前記第２スイッチの耐圧は、前記誤差増幅器の構成部品の耐圧よりも高い構成（第６の構成）であってもよい。 In the linear power supply circuit having the fifth configuration, the withstand voltage of the field effect transistor, the output transistor, and the second switch is higher than the withstand voltage of the components of the error amplifier (sixth configuration); Good too.
　上記第６の構成のリニア電源回路は、入力電圧が高くなることを許容することができる。 The linear power supply circuit with the sixth configuration can tolerate an increase in input voltage.
　上記第３又は第４の構成のリニア電源回路において、前記電流増幅器の電源電圧と前記カレントミラー回路の電源電圧とが共通である構成（第７の構成）であってもよい。 The linear power supply circuit of the third or fourth configuration may have a configuration (seventh configuration) in which the power supply voltage of the current amplifier and the power supply voltage of the current mirror circuit are common.
　上記第７の構成のリニア電源回路は、入力電圧と異なる電源電圧が不要となる。 The linear power supply circuit of the seventh configuration does not require a power supply voltage different from the input voltage.
　以上説明した車両（Ｘ）は、上記第１～第７いずれかの構成のリニア電源回路を有する構成（第８の構成）である。 The vehicle (X) described above has a configuration (eighth configuration) having a linear power supply circuit having any one of the first to seventh configurations.
　上記第８の構成の車両は、出力段がカレントミラー回路であるリニア電源回路の出力トランジスタをロードスイッチとして用いることができる。 In the vehicle having the eighth configuration, the output transistor of the linear power supply circuit whose output stage is a current mirror circuit can be used as a load switch.
　　１　誤差増幅器
　　２　定電流源
　　３　制御回路
　　１１～１３　リニア電源回路
　　Ｄ１　ダイオード
　　Ｑ１～Ｑ３、Ｑ６　Ｐチャネル型電界効果トランジスタ
　　Ｑ４、Ｑ５、Ｑ８～Ｑ１０　Ｎチャネル型電界効果トランジスタ
　　Ｑ７　出力トランジスタ
　　Ｒ１、Ｒ２　抵抗
　　ＳＷ１～ＳＷ３　第１～第３スイッチ
　　Ｘ　車両
　　Ｘ１１～Ｘ１８　電子機器 1 Error amplifier 2 Constant current source 3 Control circuit 11-13 Linear power supply circuit D1 Diode Q1-Q3, Q6 P-channel field effect transistor Q4, Q5, Q8-Q10 N-channel field effect transistor Q7 Output transistor R1, R2 Resistor SW1 ~SW3 1st~3rd switch X Vehicle X11~X18 Electronic equipment

Claims (8)

  1. 　入力電圧が印加されるように構成される入力端と出力電圧が印加されるように構成される出力端との間に設けられた出力トランジスタと、
    　前記出力トランジスタと対となってカレントミラー回路を構成する電界効果トランジスタと、
    　前記電界効果トランジスタのソースと前記入力端との間に設けられる第１スイッチと、
    　前記電界効果トランジスタのゲートとグラウンド電圧が印加されるように構成される接地端との間に設けられる第２スイッチと、を有する、リニア電源回路。     an output transistor provided between an input terminal configured to apply an input voltage and an output terminal configured to apply an output voltage;
    a field effect transistor that forms a pair with the output transistor to form a current mirror circuit;
    a first switch provided between the source of the field effect transistor and the input terminal;
    A linear power supply circuit comprising: a second switch provided between the gate of the field effect transistor and a ground terminal configured to apply a ground voltage.
  2. 　前記第１スイッチをオンし、前記第２スイッチをオフにする第１動作モードと、
    　前記第１スイッチをオフし、前記第２スイッチをオンにする第２動作モードと、を有する、請求項１に記載のリニア電源回路。     a first operating mode in which the first switch is turned on and the second switch is turned off;
    The linear power supply circuit according to claim 1, having a second operation mode in which the first switch is turned off and the second switch is turned on.
  3. 　前記出力電圧に基づく電圧と基準電圧との差に基づいて前記出力トランジスタを駆動するように構成されるドライバを有し、
    　前記ドライバは、
    　　前記出力電圧に基づく電圧と前記基準電圧との差に応じた誤差電圧を出力するように構成される誤差増幅器と、
    　前記誤差増幅器の出力に基づく電圧を電流に変換して出力するように構成される変換器と、
    　前記変換器の出力を電流増幅するように構成される電流増幅器と、
    　前記電流増幅器と前記出力トランジスタとの間に設けられる前記電界効果トランジスタと、
    　前記第１スイッチと、
    　前記第２スイッチと、
    　前記変換器に並列接続される第３スイッチと、
    　を有する、請求項１に記載のリニア電源回路。     a driver configured to drive the output transistor based on a difference between a voltage based on the output voltage and a reference voltage;
    The driver is
    an error amplifier configured to output an error voltage according to a difference between a voltage based on the output voltage and the reference voltage;
    a converter configured to convert a voltage based on the output of the error amplifier into a current and output the current;
    a current amplifier configured to current amplify the output of the converter;
    the field effect transistor provided between the current amplifier and the output transistor;
    the first switch;
    the second switch;
    a third switch connected in parallel to the converter;
    The linear power supply circuit according to claim 1, comprising:
  4. 　前記第１スイッチをオンし、前記第２スイッチ及び前記第３スイッチをオフにする第１動作モードと、
    　前記第１スイッチをオフし、前記第２スイッチ及び前記第３スイッチをオンにする第２動作モードと、を有する、請求項３に記載のリニア電源回路。     a first operation mode in which the first switch is turned on and the second switch and the third switch are turned off;
    The linear power supply circuit according to claim 3, having a second operation mode in which the first switch is turned off and the second switch and the third switch are turned on.
  5. 　前記電流増幅器の電源電圧と前記カレントミラー回路の電源電圧とが互いに異なる、請求項３又は請求項４に記載のリニア電源回路。 The linear power supply circuit according to claim 3 or 4, wherein the power supply voltage of the current amplifier and the power supply voltage of the current mirror circuit are different from each other.
  6. 　前記電界効果トランジスタ、前記出力トランジスタ、及び前記第２スイッチの耐圧は、前記誤差増幅器の構成部品の耐圧よりも高い、請求項５に記載のリニア電源回路。 The linear power supply circuit according to claim 5, wherein the field effect transistor, the output transistor, and the second switch have a higher breakdown voltage than the components of the error amplifier.
  7. 　前記電流増幅器の電源電圧と前記カレントミラー回路の電源電圧とが共通である、請求項３又は請求項４に記載のリニア電源回路。 The linear power supply circuit according to claim 3 or 4, wherein the power supply voltage of the current amplifier and the power supply voltage of the current mirror circuit are common.
  8. 　請求項１～４のいずれか一項に記載のリニア電源回路を有する、車両。 A vehicle comprising the linear power supply circuit according to any one of claims 1 to 4.
PCT/JP2023/023128 2022-07-22 2023-06-22 Linear power supply circuit and vehicle WO2024018815A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003099135A (en) * 2001-07-26 2003-04-04 Alcatel Low drop voltage regulator
JP2012134828A (en) * 2010-12-22 2012-07-12 Renesas Electronics Corp Output circuit
JP2016086537A (en) * 2014-10-27 2016-05-19 三菱電機株式会社 Drive circuit
WO2020090616A1 (en) * 2018-10-31 2020-05-07 ローム株式会社 Linear power supply circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003099135A (en) * 2001-07-26 2003-04-04 Alcatel Low drop voltage regulator
JP2012134828A (en) * 2010-12-22 2012-07-12 Renesas Electronics Corp Output circuit
JP2016086537A (en) * 2014-10-27 2016-05-19 三菱電機株式会社 Drive circuit
WO2020090616A1 (en) * 2018-10-31 2020-05-07 ローム株式会社 Linear power supply circuit

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