WO2024018522A1 - Secondary battery protection circuit, secondary battery protection device, and battery pack - Google Patents

Secondary battery protection circuit, secondary battery protection device, and battery pack Download PDF

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Publication number
WO2024018522A1
WO2024018522A1 PCT/JP2022/028048 JP2022028048W WO2024018522A1 WO 2024018522 A1 WO2024018522 A1 WO 2024018522A1 JP 2022028048 W JP2022028048 W JP 2022028048W WO 2024018522 A1 WO2024018522 A1 WO 2024018522A1
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Prior art keywords
voltage
circuit
secondary battery
battery protection
charger
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PCT/JP2022/028048
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French (fr)
Japanese (ja)
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勇人 飯
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日清紡マイクロデバイス株式会社
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Priority to PCT/JP2022/028048 priority Critical patent/WO2024018522A1/en
Publication of WO2024018522A1 publication Critical patent/WO2024018522A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/44—Methods for charging or discharging
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • the present invention relates to a secondary battery protection circuit, a secondary battery protection device, and a battery pack.
  • a pair of N-channel charge/discharge control MOS field effect transistors (hereinafter referred to as “ “Field effect transistor” is called “FET”, and “charge/discharge control MOSFET” is called “charge/discharge control FET”.
  • FET Field effect transistor
  • charge/discharge control MOSFET charge/discharge control FET
  • charge control FET charge control FET
  • discharge control FET discharge control FET
  • discharge control FET discharge control FET
  • the secondary battery according to Conventional Example 1 controls the on/off of a pair of charge/discharge control FETs by boosting the voltage supplied from the secondary battery with a charge pump and supplying it to the gate of the Battery protection circuits are known.
  • the boost operation cannot be performed at a secondary battery voltage of around zero volts, which is lower than the minimum operating voltage of the charge pump, and the voltage for turning on the charge control FET is supplied to the gate. There was a problem that charging was not possible because of the inability to do so.
  • a secondary battery protection circuit uses a switch to switch the gate voltage Vg of the charge control FET to supply the high potential voltage (positive voltage) VP + of the charger.
  • a secondary battery protection circuit according to Conventional Example 2 using a method that can turn on the charge control FET even when the secondary battery is near zero volts by preparing for this is already known (for example, Patent Document 1 reference).
  • Vg charger voltage ( ⁇ positive electrode voltage VP + )
  • Vs Battery voltage VB+ ( ⁇ Power supply voltage VDD)
  • the positive electrode voltage VP + becomes the charger voltage VP + and is expressed by the following equation.
  • An object of the present invention is to provide a secondary battery protection circuit and a secondary battery protection circuit that can reduce heat loss compared to conventional technology by charging a secondary battery near zero volts with a charger voltage lower than that of the conventional technology.
  • An object of the present invention is to provide a battery pack equipped with a secondary battery protection device and a secondary battery protection circuit.
  • the secondary battery protection circuit includes: A secondary battery that protects the secondary battery using a charge control switch element and a discharge control switch element that are inserted between the positive terminal of the secondary battery and the high potential terminal of the load and charger and connected in series with each other.
  • a second battery protection circuit a first voltage detection circuit that detects whether the battery voltage of the secondary battery is less than a predetermined first threshold; An output voltage that is a high potential voltage of the charger is output when a voltage below the first threshold is detected, and an output voltage that is the battery voltage is output when a voltage below the first threshold is not detected.
  • FIG. 2 is a circuit diagram showing a configuration example of a battery pack BP1 and its peripheral circuits according to Embodiment 1 of the present invention.
  • 2 is a block diagram showing a configuration example of a switch circuit 3 and a booster circuit 6 in FIG. 1.
  • FIG. 7 is a timing chart showing each voltage after connection of a charger in a secondary battery protection circuit according to Conventional Example 2.
  • 2 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit 16 of FIG. 1.
  • FIG. FIG. 2 is a circuit diagram showing a configuration example of a battery pack BP2 and its peripheral circuits according to Embodiment 2 of the present invention.
  • 5A is a block diagram showing a configuration example of the switch circuit 3 and the booster circuit 6 in FIG. 5A.
  • FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP3 and its peripheral circuits according to Embodiment 3 of the present invention.
  • FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP4 and its peripheral circuits according to Embodiment 4 of the present invention.
  • FIG. 3 is a circuit diagram showing a configuration example of a battery pack BP5 and its peripheral circuits according to Embodiment 5 of the present invention.
  • FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP6 and its peripheral circuits according to Embodiment 6 of the present invention.
  • FIG. 1 is a circuit diagram showing a configuration example of a battery pack BP1 and its peripheral circuits according to Embodiment 1 of the present invention.
  • the battery pack BP1 includes a secondary battery B1 having a positive terminal 21 and a negative terminal 22, a secondary battery protection device 20, a positive terminal 13, and a negative terminal 12.
  • a parallel circuit of the system load RL and the charger CH1 is connected between the positive terminal 13 and the negative terminal 12. That is, the high potential terminal of the charger CH1 is connected to the positive terminal 13, and the low potential terminal of the charger CH1 is connected to the negative terminal 12.
  • the negative terminal 22 of the secondary battery B1 has a ground voltage VSS and is connected to the negative terminal 12.
  • the secondary battery B1 has a battery voltage (power supply voltage) VDD, which is a potential difference between its positive electrode and negative electrode.
  • the secondary battery protection device 20 includes a secondary battery protection circuit 16 , a charge control FET (CFET) 14 that is, for example, an N-channel MOSFET and has a body diode 10 , and a discharge control FET (CFET) 14 that is, for example, an N-channel MOSFET and has a body diode 11 . (DFET) 15.
  • CFET charge control FET
  • DFET discharge control FET
  • the charge control FET 14 and the discharge control FET 15 are connected in series with each other, and the series circuit is connected between the positive terminal 21 and the positive terminal 13.
  • the secondary battery protection circuit 16 includes an overdischarge detection circuit 2, a switch circuit 3 including a control circuit 3A, a booster circuit 6 including a control circuit 6A, and a drive circuit 7.
  • the overdischarge detection circuit 2 generates a detection signal S2 as a comparison result signal by comparing the battery voltage VDD with a predetermined overdischarge detection threshold Vthe.
  • the overdischarge detection circuit 2 outputs an L level detection signal S2 indicating "overdischarge detection” to the drive circuit 7 and the control circuit 3A when the battery voltage VDD is lower than the overdischarge detection threshold Vthe.
  • the overdischarge detection circuit 2 outputs an H level detection signal S2 indicating "overdischarge not detected” to the drive circuit 7 and the control circuit 3A.
  • the overdischarge detection threshold Vthe is set, for example, to a discharge end voltage or a voltage slightly lower than the discharge end voltage.
  • the switch circuit 3 includes a control circuit 3A and switches 4 and 5.
  • the control circuit 3A of the switch circuit 3 outputs the battery voltage VDD to the booster circuit 6 as an output voltage VSW by turning off the switch 4 and turning on the switch 5 in response to the H level detection signal S2.
  • the control circuit 3A of the switch circuit 3 turns on the switch 4 and turns off the switch 5 in response to the L-level detection signal S2, thereby outputting a positive voltage VP + which is the charger voltage of the positive terminal 13. It is output to the booster circuit 6 as voltage VSW.
  • the drive circuit 7 uses the boosted voltage VCP to control ON or OFF of the charge control FET 14 and the discharge control FET 15.
  • the charge control FET 14 is turned on and the discharge control FET 15 is turned off.
  • FIG. 2 is a block diagram showing a configuration example of the switch circuit 3 and booster circuit 6 in FIG. 1.
  • the switch circuit 3 includes a control circuit 3A and switches 4 and 5, and operates as described above.
  • the booster circuit 6 is a general charge pump circuit, and includes a control circuit 6A, four switches 6a to 6d, and a booster capacitor C1.
  • the output voltage VSW from the switch circuit 3 is supplied as a power supply voltage to the control circuit 6A, and is also output to the drive circuit 7 as a boosted voltage VCP via the switches 6a and 6b.
  • Battery voltage VDD is grounded via switches 6c and 6d.
  • the connection point between the switch 6a and the switch 6b is connected to the connection point between the switch 6c and the switch 6d via a boosting capacitor C1.
  • the switch 5 is turned off and the switch 4 is turned on in response to the L level detection signal S2 from the overdischarge detection circuit 2, and the positive terminal
  • the positive voltage VP + of 13 is supplied to the booster circuit 6 via the switch 4 as the output voltage VSW.
  • the boost circuit 6 uses the output voltage VSW as the power supply voltage, it does not perform a boost operation in this case, and the charge control FET 14 does not supply the drive circuit 7 with the boost voltage VCP that turns it on, so it charges Control FET 14 is driven off.
  • the charger output voltage VP + VSW.
  • VCP voltage control signal
  • the gate-source voltage of the charge control FET 14 is Vgs
  • the gate-source voltage of the charge control FET 14 required to drive the supply current of the charger CH1 is Vth
  • the gate voltage of the charge control FET 14 is Vg.
  • the difference voltage (Vg-Vs) between the source voltage Vs and the source voltage Vs is expressed by the following equation.
  • the condition for enabling charging is Vgs ⁇ Vth, that is, P + ⁇ Vth.
  • FIG. 3 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit according to Conventional Example 2. Further, FIG. 4 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit 16 of FIG. 1. Timing charts during charging of zero-volt batteries in Conventional Example 2 and Embodiment 1 will be described below with reference to FIGS. 3 and 4.
  • Vgs COUT-VDD
  • Vgs VP + -VDD
  • the gate-source voltage of charge control FET 14 required to drive the supply current of charger CH1 is Vth, then the condition for enabling charging is Vgs ⁇ Vth, so VP + -VDD ⁇ Vth. , that is, VP + ⁇ VDD+Vth (FIG. 3).
  • the gate-source voltage of the charge control FET 14 is Vgs
  • the gate-source voltage of the charge control FET 14 required to drive the supply current of the charger CH1 is Vth. Then, it is expressed by the following formula.
  • the condition that enables charging is Vgs>Vth, that is, P+ ⁇ Vth (FIG. 4).
  • Vgs>Vth that is, P+ ⁇ Vth
  • FIG. 4 unlike the second conventional example, it does not depend on the battery voltage VDD, and as a result, it is charged with a lower charger voltage than the second conventional example.
  • the conditions for starting charging are as follows, assuming that the forward voltage of the body diode 11 of the discharge control FET 15 is Vf, and the drain-source voltage of the charge control FET is Vds. It is expressed by the following formula.
  • the charger CH1 performs CC charging by increasing the positive electrode voltage VP + .
  • the positive electrode voltage VP + increases as the battery voltage VDD increases immediately after the start of charging.
  • Embodiment 1 of FIG. 4 since there is a time period in which the positive electrode voltage VP + does not rise during a predetermined time period after the start of charging, charging can be maintained at a lower charger voltage than in Conventional Example 2. Can be done.
  • the heat generation loss is lower than that of the conventional technique. can be reduced.
  • FIG. 5A is a circuit diagram showing a configuration example of a battery pack BP2 and its peripheral circuits according to Embodiment 2 of the present invention
  • FIG. 5B is a block diagram showing a configuration example of the switch circuit 3 and booster circuit 6 in FIG. 5A.
  • Battery pack BP2 in FIG. 5A differs from battery pack BP1 in FIG. 1 in the following points. (1) In place of the secondary battery protection circuit 16, a secondary battery protection circuit 16A further including the voltage detection circuit 1 was provided. (2) In place of the secondary battery protection device 20, a secondary battery protection device 20A including a secondary battery protection circuit 16A was provided. (3) The booster circuit 6 includes a control circuit 6B instead of the control circuit 6A. The differences will be explained below.
  • the voltage detection circuit 1 compares the positive voltage VP + with a predetermined voltage threshold Vthd and generates a detection signal S1 that is a comparison result signal.
  • a predetermined voltage threshold Vthd is set higher than the lowest operating voltage of the booster circuit 6.
  • the control circuit 6B of the booster circuit 6 operates the booster circuit 6 in response to the H level detection signal S1 from the voltage detection circuit 1, but the control circuit 6B operates the booster circuit 6 in response to the H level detection signal S1 from the voltage detection circuit 2.
  • the boosting operation of the booster circuit 6 is stopped in response to the level detection signal S2 (over-discharge detection signal) and the L level detection signal S1. Note that the detection signal S1 from the voltage detection circuit 1 is also output to the drive circuit 7 to notify that the boosting operation of the boosting circuit 6 has stopped.
  • the overdischarge detection circuit 2 detects the "overdischarge" state of the secondary battery B1 and the discharge control FET 15 is driven off to stop discharging from the secondary battery B1
  • the positive electrode voltage VP + and the negative electrode voltage VP - are The voltage between is pulled down to 0V by the system load RL.
  • the positive electrode voltage VP + gradually increases from 0V.
  • the switch 5 of the switch circuit 3 was turned off and the switch 4 was turned on to supply the output voltage VSW, which is the positive voltage VP + , as the power supply voltage of the booster circuit 6.
  • the booster circuit 6 starts up while the positive voltage VP + reaches the lowest operating voltage of the booster circuit 6 from 0V (a period in which the booster circuit 6 is not in a normal operating state), depending on the configuration of the booster circuit 6, It is assumed that malfunction or through current may occur.
  • the booster circuit 6 when the positive voltage VP + is less than the minimum operating voltage of the booster circuit 6 (during a period in which the booster circuit 6 is not in a normal operable state), the booster circuit 6 is controlled to be stopped. This prevents the booster circuit 6 from starting when the positive voltage VP + is less than the minimum operating voltage of the booster circuit 6, and prevents malfunction of the booster circuit 6 or occurrence of a through current.
  • the voltage detection The circuit 1 is in a "non-detection" state, and by outputting the L-level detection signal S1 and stopping the booster circuit 6, it is possible to prevent the booster circuit 6 from malfunctioning or from generating a through current.
  • the secondary battery protection circuit 16A according to the second embodiment has the same effects as the secondary battery protection circuit 16 according to the first embodiment.
  • FIG. 6 is a circuit diagram showing a configuration example of a battery pack BP3 and its peripheral circuits according to the third embodiment of the present invention.
  • Battery pack BP3 in FIG. 6 differs from battery pack BP2 in FIG. 2 in the following points.
  • a secondary battery protection circuit 16B further including a clamp circuit 8 was provided in place of the secondary battery protection circuit 16A.
  • a secondary battery protection device 20B including a secondary battery protection circuit 16B was provided in place of the secondary battery protection device 20A. The differences will be explained below.
  • VCP H level
  • the secondary battery B1 is normally used at 4.2V or less, when the secondary battery protection circuit 16B is configured with a semiconductor integrated circuit (IC), the protection circuit IC that is connected only to the battery voltage is generally A 5V process element is used. Therefore, by setting the clamp voltage VCL from the clamp circuit 8 to 5V or less, the secondary battery protection circuit 16B including the switches 4 and 5 and the booster circuit 6 can be operated at 5V, which is generally used in protection circuit ICs. It becomes possible to construct the device using low-voltage elements processed using a system process. Therefore, it is possible to obtain the advantages of saving area, reducing the number of masks, and shortening lead time.
  • IC semiconductor integrated circuit
  • the secondary battery protection circuit 16B according to the third embodiment has the same effects as the secondary battery protection circuits 16 and 16A according to the first and second embodiments.
  • the voltage detection circuit 1 may be deleted (a modification of the third embodiment).
  • FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP4 and its peripheral circuits according to Embodiment 4 of the present invention.
  • Battery pack BP4 in FIG. 7 differs from battery pack BP3 in FIG. 6 in the following points.
  • a secondary battery protection circuit 16C is provided in which the insertion position of the clamp circuit 8 is changed.
  • the clamp circuit 8 was inserted between the positive terminal 13 and one end of the switch 4 of the voltage detection circuit 1 and the switch circuit 3.
  • a secondary battery protection device 20C including a secondary battery protection circuit 16C was provided. The differences will be explained below.
  • the voltage detection circuit 1 generates an H-level detection signal S1 and outputs it to the drive circuit 7 when the clamp voltage VCL is equal to or higher than the voltage threshold Vthd, and when the clamp voltage VCL is less than the voltage threshold Vthd. In this case, an L level detection signal S1 is generated and output to the drive circuit 7.
  • the voltage detection circuit 1 As shown in FIG. It becomes possible to configure the voltage detection circuit 1 with a low withstand voltage of 5V system, and it is possible to obtain the advantages of saving area, reducing the number of masks, and shortening lead time.
  • the secondary battery protection circuit 16C according to the fourth embodiment has the same effects as the secondary battery protection circuits 16, 16A to 16B according to the first to third embodiments.
  • FIG. 8A is a circuit diagram showing a configuration example of a battery pack BP5 and its peripheral circuits according to Embodiment 5 of the present invention.
  • the battery pack BP5 of FIG. 8A differs from the battery pack BP4 of FIG. 7 in the following points.
  • a secondary battery protection circuit 16D further including a voltage detection circuit 17 was provided in place of the secondary battery protection circuit 16C. Voltage detection circuit 17 was inserted between positive terminal 13 and clamp circuit 8, and voltage detection circuit 1.
  • a secondary battery protection device 20D including a secondary battery protection circuit 16D was provided in place of the secondary battery protection device 20C. The differences will be explained below.
  • the voltage detection circuit 17 is a charger voltage monitoring circuit that monitors the positive electrode voltage VP + , which is the charger voltage, and has a voltage threshold Vthf set higher than the voltage threshold Vthd of the voltage detection circuit 1. has.
  • the voltage detection circuit 17 detects a so-called "high voltage” by comparing the positive voltage VP + with a voltage threshold Vthf, and generates a detection signal S17 as a comparison result signal as described below.
  • a detection signal S1 is generated and outputted to the drive circuit 7 and the control circuit 6B of the booster circuit 6.
  • the boost circuit 6 does not perform a boost operation, and the drive circuit 7 outputs the L-level control signal COUT to the gate of the charge control FET 14, thereby turning off the charge control FET 14 and cutting off the charging path.
  • the boost circuit 6 does not perform a boost operation, and the drive circuit 7 outputs the L-level control signal COUT to the gate of the charge control FET 14, thereby turning off the charge control FET 14 and cutting off the charging path.
  • the secondary battery protection circuit 16D according to the fifth embodiment has the same effects as the secondary battery protection circuits 16, 16A to 16C according to the first to fourth embodiments.
  • FIG. 8B is a circuit diagram showing a configuration example of a battery pack BP6 and its peripheral circuits according to Embodiment 6 of the present invention.
  • the battery pack BP6 of FIG. 8B differs from the battery pack BP5 of FIG. 8A in the following points.
  • the voltage detection circuit 17 detects the clamp voltage VCL from the clamp circuit 8 instead of the positive voltage VP + .
  • a secondary battery protection device 20E including the secondary battery protection circuit 16E was provided. The differences will be explained below.
  • the voltage detection circuit 17 is a charger voltage monitoring circuit that monitors the positive voltage VP + from the clamp circuit 8 via the clamp voltage VCL, and is set higher than the voltage threshold Vthd of the voltage detection circuit 1. It has a voltage threshold Vthf. At this time, in order to enable the voltage detection circuit 17 to detect, based on the clamp voltage VCL from the clamp circuit 8, that the positive voltage VP + has become equal to or higher than the voltage threshold Vthf, the clamp voltage from the clamp circuit 8 is is set higher than Vthf.
  • the voltage detection circuit 17 detects a so-called "high voltage” by comparing the clamp voltage VCL with a voltage threshold Vthf, and generates a detection signal S17 as a comparison result signal as described below.
  • VCL H level
  • Vthf L level
  • the secondary battery protection circuit 16E according to the sixth embodiment configured as described above has the same effects as the secondary battery protection circuit 16D according to the fifth embodiment except for the detection voltage of the voltage detection circuit 17.
  • the overdischarge detection circuit 2 detects overdischarge of the secondary battery B1, but the present invention is not limited to this. It may also be detected that the battery voltage of the positive terminal 21 of the next battery B1 decreases. That is, the overdischarge detection threshold Vthe may be a threshold for detecting another voltage drop.
  • the charging control FET 14 and the discharging control FET 15 may be arranged with their positions interchanged.
  • the charge control FET 14 and the discharge control FET 15 are used, but the present invention is not limited to this, and each uses a different type of switch element such as a bipolar transistor (having a control terminal that is a base). You can.

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Abstract

This secondary battery protection circuit protects a secondary battery by using charging control and discharging control switch elements inserted between a positive terminal of the secondary battery and a high-potential terminal of a charger. The secondary battery protection circuit comprises: a first voltage detection circuit that detects whether the battery voltage is less than a first threshold; a switch circuit that outputs a high-potential voltage of the charger at the time of detection and outputs a battery voltage at the time of non-detection; a booster circuit that boosts and outputs the battery voltage by using the output voltage of the switch circuit; and a drive circuit that performs control to turn on only the charging control switch element by outputting the output volage of the booster circuit at the time of detection only to the control terminal of this switch element, and to turn on both the charging control switch element and the discharging control switch element by outputting the output volage of the booster circuit at the time of non-detection to the control terminals of these switch elements.

Description

二次電池保護回路、二次電池保護装置、及び電池パックSecondary battery protection circuit, secondary battery protection device, and battery pack
　本発明は、二次電池保護回路、二次電池保護装置、及び電池パックに関する。 The present invention relates to a secondary battery protection circuit, a secondary battery protection device, and a battery pack.
　二次電池の正極と、負荷及び充電器の高電位側電源端子に接続されるプラス端子との間の電流経路に直列に挿入される一対のＮチャンネル充放電制御ＭＯＳ電界効果トランジスタ（以下、「電界効果トランジスタ」を「ＦＥＴ」といい、「充放電制御ＭＯＳＦＥＴ」を「充放電制御ＦＥＴ」という。ここで、「充放電制御ＦＥＴ」は、「充電制御ＦＥＴ」と、「放電制御ＦＥＴ」とを含む。）のゲートに対して、二次電池から供給される電圧をチャージポンプで昇圧し供給することで、一対の充放電制御ＦＥＴのオン／オフを制御する、従来例１に係る二次電池保護回路が知られている。 A pair of N-channel charge/discharge control MOS field effect transistors (hereinafter referred to as " "Field effect transistor" is called "FET", and "charge/discharge control MOSFET" is called "charge/discharge control FET". Here, "charge/discharge control FET" is referred to as "charge control FET" and "discharge control FET". The secondary battery according to Conventional Example 1 controls the on/off of a pair of charge/discharge control FETs by boosting the voltage supplied from the secondary battery with a charge pump and supplying it to the gate of the Battery protection circuits are known.
　しかし、従来例１に係る二次電池保護回路においては、チャージポンプの最低動作電圧を下回るゼロボルト付近の二次電池電圧では昇圧動作ができず、充電制御ＦＥＴをオンするための電圧をゲートに供給することができないことから、充電ができないという課題があった。 However, in the secondary battery protection circuit according to Conventional Example 1, the boost operation cannot be performed at a secondary battery voltage of around zero volts, which is lower than the minimum operating voltage of the charge pump, and the voltage for turning on the charge control FET is supplied to the gate. There was a problem that charging was not possible because of the inability to do so.
　この課題を解決するために従来、電池電圧がゼロボルト付近の場合、充電制御ＦＥＴのゲート電圧Ｖｇに充電器の高電位電圧（正極電圧）ＶＰ＋を供給するように切り替えるスイッチを二次電池保護回路に備えることで、二次電池がゼロボルト付近であっても充電制御ＦＥＴをオンさせることができる手法を用いた従来例２に係る二次電池保護回路が既に知られている（例えば、特許文献１参照）。 To solve this problem, conventionally, when the battery voltage is around zero volts, a secondary battery protection circuit uses a switch to switch the gate voltage Vg of the charge control FET to supply the high potential voltage (positive voltage) VP + of the charger. A secondary battery protection circuit according to Conventional Example 2 using a method that can turn on the charge control FET even when the secondary battery is near zero volts by preparing for this is already known (for example, Patent Document 1 reference).
特許第６６１４３８８号公報Patent No. 6614388
　従来例２に係る二次電池保護回路において、ゼロボルト付近の二次電池に対して充電をする際、充電器は、いわゆる「ＣＣ充電」と呼ばれる一定電流により充電を開始することが想定されている。ここで、ゼロボルト付近の二次電池に対して充電をするためには、充電器が供給する電流を流せるゲートソース間電圧Ｖｇｓが充電制御ＦＥＴに発生する必要がある。この場合において、充電器の供給電流を駆動するために必要な充電制御ＦＥＴのゲート－ソース間電圧をしきい値電圧Ｖｔｈとし充電器の供給電流を駆動するための条件は、充電制御ＦＥＴのソース電圧をＶｓとすると、次式で表される。 In the secondary battery protection circuit according to Conventional Example 2, when charging a secondary battery near zero volts, the charger is assumed to start charging with a constant current called "CC charging". . Here, in order to charge a secondary battery near zero volts, it is necessary to generate a gate-source voltage Vgs in the charge control FET that allows the current supplied by the charger to flow. In this case, the condition for driving the supply current of the charger is to set the gate-source voltage of the charge control FET to the threshold voltage Vth, which is necessary to drive the supply current of the charger. When the voltage is Vs, it is expressed by the following equation.
Ｖｇ＝充電器電圧（≒正極電圧ＶＰ＋）
Ｖｓ＝電池電圧ＶＢ＋（≒電源電圧ＶＤＤ） Vg=charger voltage (≒positive electrode voltage VP + )
Vs=Battery voltage VB+ (≒Power supply voltage VDD)
　従って、正極電圧ＶＰ＋は充電器電圧ＶＰ＋となり、次式で表される。 Therefore, the positive electrode voltage VP + becomes the charger voltage VP + and is expressed by the following equation.
Ｖｇｓ＞Ｖｔｈ Vgs>Vth
　すなわち、次式を得る。 In other words, the following equation is obtained.
ＶＰ＋＞ＶＤＤ＋Ｖｔｈ VP + >VDD+Vth
　充電器電圧ＶＰ＋が大きいほど、正極端子（電圧ＶＰ＋）と、電池正極端子との間で降下する電圧が大きくなり充電に伴う発熱損失が大きくなるという問題があった。特に、充電時間短縮化のために電池電圧が低い状態の時から、大電流で充電する際のボトルネックになりうる。従って、より低い充電器電圧で充電が行われる方が望ましい。 There has been a problem in that the larger the charger voltage VP + is, the greater the voltage that drops between the positive terminal (voltage VP + ) and the battery positive terminal, and the greater the heat loss associated with charging. In particular, this can become a bottleneck when charging with a large current when the battery voltage is low to shorten charging time. Therefore, it is desirable to perform charging at a lower charger voltage.
　本発明の目的は、従来よりも低い充電器電圧でゼロボルト付近の二次電池に対して充電することで、従来技術よりも発熱損失を低減できる二次電池保護回路、二次電池保護回路を備えた二次電池保護装置、及び二次電池保護回路を備えた電池パックを提供することにある。 An object of the present invention is to provide a secondary battery protection circuit and a secondary battery protection circuit that can reduce heat loss compared to conventional technology by charging a secondary battery near zero volts with a charger voltage lower than that of the conventional technology. An object of the present invention is to provide a battery pack equipped with a secondary battery protection device and a secondary battery protection circuit.
　本発明に係る二次電池保護回路は、
　二次電池の正極端子と、負荷及び充電器の高電位端子との間に挿入されかつ互いに直列に接続された充電制御スイッチ素子及び放電制御スイッチ素子を用いて、前記二次電池を保護する二次電池保護回路であって、
　前記二次電池の電池電圧が所定の第１のしきい値未満であるか否かを検出する第１の電圧検出回路と、
　前記第１のしきい値未満を検出したときに前記充電器の高電位電圧である出力電圧を出力する一方、前記第１のしきい値未満を検出しないときに前記電池電圧である出力電圧を出力するスイッチ回路と、
　前記電池電圧を前記スイッチ回路の出力電圧を用いて昇圧させて出力する昇圧回路と、
　前記第１のしきい値未満を検出したときに前記昇圧回路の出力電圧を前記充電制御スイッチ素子の制御端子のみに出力することで前記充電制御スイッチ素子のみをオンする一方、前記第１のしきい値未満を検出しないときに前記昇圧回路の出力電圧を前記充電制御スイッチ素子及び前記放電制御スイッチ素子の各制御端子に出力することで前記充電制御スイッチ素子及び前記放電制御スイッチ素子をともにオンするように制御する駆動回路と、
を備える。 The secondary battery protection circuit according to the present invention includes:
A secondary battery that protects the secondary battery using a charge control switch element and a discharge control switch element that are inserted between the positive terminal of the secondary battery and the high potential terminal of the load and charger and connected in series with each other. A second battery protection circuit,
a first voltage detection circuit that detects whether the battery voltage of the secondary battery is less than a predetermined first threshold;
An output voltage that is a high potential voltage of the charger is output when a voltage below the first threshold is detected, and an output voltage that is the battery voltage is output when a voltage below the first threshold is not detected. A switch circuit to output,
a booster circuit that boosts and outputs the battery voltage using the output voltage of the switch circuit;
By outputting the output voltage of the booster circuit only to the control terminal of the charge control switch element when a voltage lower than the first threshold is detected, only the charge control switch element is turned on; Both the charge control switch element and the discharge control switch element are turned on by outputting the output voltage of the booster circuit to each control terminal of the charge control switch element and the discharge control switch element when a voltage lower than a threshold is not detected. A drive circuit that controls the
Equipped with.
　従って、本発明に係る二次電池保護回路等によれば、従来よりも低い充電器電圧でゼロボルト付近の二次電池に対して充電することで、従来技術よりも発熱損失を低減できる。 Therefore, according to the secondary battery protection circuit and the like according to the present invention, by charging a secondary battery near zero volts with a charger voltage lower than that of the conventional technology, heat loss can be reduced more than that of the conventional technology.
本発明の実施形態１に係る電池パックＢＰ１とその周辺回路の構成例を示す回路図である。FIG. 2 is a circuit diagram showing a configuration example of a battery pack BP1 and its peripheral circuits according to Embodiment 1 of the present invention. 図１のスイッチ回路３及び昇圧回路６の構成例を示すブロック図である。2 is a block diagram showing a configuration example of a switch circuit 3 and a booster circuit 6 in FIG. 1. FIG. 従来例２に係る二次電池保護回路において、充電器接続以降の各電圧を示すタイミングチャートである。7 is a timing chart showing each voltage after connection of a charger in a secondary battery protection circuit according to Conventional Example 2. 図１の二次電池保護回路１６において、充電器接続以降の各電圧を示すタイミングチャートである。2 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit 16 of FIG. 1. FIG. 本発明の実施形態２に係る電池パックＢＰ２とその周辺回路の構成例を示す回路図である。FIG. 2 is a circuit diagram showing a configuration example of a battery pack BP2 and its peripheral circuits according to Embodiment 2 of the present invention. 図５Ａのスイッチ回路３及び昇圧回路６の構成例を示すブロック図である。5A is a block diagram showing a configuration example of the switch circuit 3 and the booster circuit 6 in FIG. 5A. FIG. 本発明の実施形態３に係る電池パックＢＰ３とその周辺回路の構成例を示す回路図である。FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP3 and its peripheral circuits according to Embodiment 3 of the present invention. 本発明の実施形態４に係る電池パックＢＰ４とその周辺回路の構成例を示す回路図である。FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP4 and its peripheral circuits according to Embodiment 4 of the present invention. 本発明の実施形態５に係る電池パックＢＰ５とその周辺回路の構成例を示す回路図である。FIG. 3 is a circuit diagram showing a configuration example of a battery pack BP5 and its peripheral circuits according to Embodiment 5 of the present invention. 本発明の実施形態６に係る電池パックＢＰ６とその周辺回路の構成例を示す回路図である。FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP6 and its peripheral circuits according to Embodiment 6 of the present invention.
　以下、本発明に係る実施形態及び変形例について図面を参照して説明する。なお、同一又は同様の構成要素については同一の符号を付している。 Hereinafter, embodiments and modifications according to the present invention will be described with reference to the drawings. Note that the same or similar components are given the same reference numerals.
（実施形態１）
　図１は、本発明の実施形態１に係る電池パックＢＰ１とその周辺回路の構成例を示す回路図である。 (Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration example of a battery pack BP1 and its peripheral circuits according to Embodiment 1 of the present invention.
　図１において、電池パックＢＰ１は、正極端子２１と負極端子２２とを有する二次電池Ｂ１と、二次電池保護装置２０と、正極端子１３と、負極端子１２とを備えて構成される。ここで、正極端子１３と負極端子１２との間には、システム負荷ＲＬと充電器ＣＨ１との並列回路が接続される。すなわち、充電器ＣＨ１の高電位端子は正極端子１３に接続され、充電器ＣＨ１の低電位端子は負極端子１２に接続される。また、二次電池Ｂ１の負極端子２２は接地電圧ＶＳＳを有し、負極端子１２に接続される。二次電池Ｂ１はその正極－負極間の電位差である電池電圧（電源電圧）ＶＤＤを有する。 In FIG. 1, the battery pack BP1 includes a secondary battery B1 having a positive terminal 21 and a negative terminal 22, a secondary battery protection device 20, a positive terminal 13, and a negative terminal 12. Here, a parallel circuit of the system load RL and the charger CH1 is connected between the positive terminal 13 and the negative terminal 12. That is, the high potential terminal of the charger CH1 is connected to the positive terminal 13, and the low potential terminal of the charger CH1 is connected to the negative terminal 12. Further, the negative terminal 22 of the secondary battery B1 has a ground voltage VSS and is connected to the negative terminal 12. The secondary battery B1 has a battery voltage (power supply voltage) VDD, which is a potential difference between its positive electrode and negative electrode.
　二次電池保護装置２０は、二次電池保護回路１６と、例えばＮチャネルＭＯＳＦＥＴでありボディダイオード１０を有する充電制御ＦＥＴ（ＣＦＥＴ）１４と、例えばＮチャネルＭＯＳＦＥＴでありボディダイオード１１を有する放電制御ＦＥＴ（ＤＦＥＴ）１５とを備えて構成される。ここで、充電制御ＦＥＴ１４と、放電制御ＦＥＴ１５とは互いに直列に接続されて、その直列回路が正極端子２１と、正極端子１３との間に接続される。二次電池保護回路１６は、過放電検出回路２と、制御回路３Ａを含むスイッチ回路３と、制御回路６Ａを含む昇圧回路６と、駆動回路７とを備えて構成される。 The secondary battery protection device 20 includes a secondary battery protection circuit 16 , a charge control FET (CFET) 14 that is, for example, an N-channel MOSFET and has a body diode 10 , and a discharge control FET (CFET) 14 that is, for example, an N-channel MOSFET and has a body diode 11 . (DFET) 15. Here, the charge control FET 14 and the discharge control FET 15 are connected in series with each other, and the series circuit is connected between the positive terminal 21 and the positive terminal 13. The secondary battery protection circuit 16 includes an overdischarge detection circuit 2, a switch circuit 3 including a control circuit 3A, a booster circuit 6 including a control circuit 6A, and a drive circuit 7.
　過放電検出回路２は、電池電圧ＶＤＤを所定の過放電検出しきい値Ｖｔｈｅと比較することで、比較結果信号である検出信号Ｓ２を発生する。ここで、過放電検出回路２は、電池電圧ＶＤＤが前記過放電検出しきい値Ｖｔｈｅを下回る場合は「過放電検出」を示すＬレベルの検出信号Ｓ２を駆動回路７及び制御回路３Ａに出力する。一方、過放電検出回路２は、電池電圧ＶＤＤが前記過放電検出しきい値Ｖｔｈｅ以上の場合は「過放電非検出」を示すＨレベルの検出信号Ｓ２を駆動回路７及び制御回路３Ａに出力する。ここで、過放電検出しきい値Ｖｔｈｅは、例えば放電終止電圧又は前記放電終止電圧よりも若干低い電圧に設定される。
The overdischarge detection circuit 2 generates a detection signal S2 as a comparison result signal by comparing the battery voltage VDD with a predetermined overdischarge detection threshold Vthe. Here, the overdischarge detection circuit 2 outputs an L level detection signal S2 indicating "overdischarge detection" to the drive circuit 7 and the control circuit 3A when the battery voltage VDD is lower than the overdischarge detection threshold Vthe. . On the other hand, when the battery voltage VDD is equal to or higher than the overdischarge detection threshold Vthe, the overdischarge detection circuit 2 outputs an H level detection signal S2 indicating "overdischarge not detected" to the drive circuit 7 and the control circuit 3A. . Here, the overdischarge detection threshold Vthe is set, for example, to a discharge end voltage or a voltage slightly lower than the discharge end voltage.
　スイッチ回路３は、制御回路３Ａと、スイッチ４，５とを備えて構成される。スイッチ回路３の制御回路３Ａは、Ｈレベルの検出信号Ｓ２に応答して、スイッチ４をオフしかつスイッチ５をオンさせることで、電池電圧ＶＤＤを出力電圧ＶＳＷとして昇圧回路６に出力する。一方、スイッチ回路３の制御回路３Ａは、Ｌレベルの検出信号Ｓ２に応答して、スイッチ４をオンしかつスイッチ５をオフさせることで正極端子１３の充電器電圧である正極電圧ＶＰ＋を出力電圧ＶＳＷとして昇圧回路６に出力する。 The switch circuit 3 includes a control circuit 3A and switches 4 and 5. The control circuit 3A of the switch circuit 3 outputs the battery voltage VDD to the booster circuit 6 as an output voltage VSW by turning off the switch 4 and turning on the switch 5 in response to the H level detection signal S2. On the other hand, the control circuit 3A of the switch circuit 3 turns on the switch 4 and turns off the switch 5 in response to the L-level detection signal S2, thereby outputting a positive voltage VP + which is the charger voltage of the positive terminal 13. It is output to the booster circuit 6 as voltage VSW.
　昇圧回路６はスイッチ回路３からの出力電圧ＶＳＷを電源電圧として動作し、電池電圧ＶＤＤ及び出力端子ＶＳＷに基づいて、昇圧電圧ＶＣＰ（＝ＶＤＤ＋ＶＳＷ）を生成する。 The booster circuit 6 operates using the output voltage VSW from the switch circuit 3 as a power supply voltage, and generates a boosted voltage VCP (=VDD+VSW) based on the battery voltage VDD and the output terminal VSW.
　駆動回路７は検出信号Ｓ２に基づいて、昇圧電圧ＶＣＰを用いて、充電制御ＦＥＴ１４及び放電制御ＦＥＴ１５のオン又はオフを制御する。ここで、駆動回路７は、Ｈレベルの検出信号Ｓ２に基づいて、Ｈレベル（＝ＶＣＰ）の制御信号ＣＯＵＴ，ＤＯＵＴをそれぞれ充電制御ＦＥＴ１４，放電制御ＦＥＴ１５の各ゲート（制御端子）に出力することで、充電制御ＦＥＴ１４，放電制御ＦＥＴ１５をともにオンさせる。一方、駆動回路７は、Ｌレベルの検出信号Ｓ２に基づいて、Ｈレベル（＝ＶＣＰ）の制御信号ＣＯＵＴを充電制御ＦＥＴ１４のゲートに出力しかつＬレベル（＝ＶＳＳ）の制御信号ＤＯＵＴを放電制御ＦＥＴ１５のゲートに出力することで、充電制御ＦＥＴ１４をオンさせ、かつ放電制御ＦＥＴ１５をオフさせる。 Based on the detection signal S2, the drive circuit 7 uses the boosted voltage VCP to control ON or OFF of the charge control FET 14 and the discharge control FET 15. Here, the drive circuit 7 outputs H level (=VCP) control signals COUT and DOUT to each gate (control terminal) of the charging control FET 14 and the discharging control FET 15, respectively, based on the H level detection signal S2. Then, both the charge control FET 14 and the discharge control FET 15 are turned on. On the other hand, the drive circuit 7 outputs an H level (=VCP) control signal COUT to the gate of the charging control FET 14 based on the L level detection signal S2, and controls discharging of the L level (=VSS) control signal DOUT. By outputting to the gate of the FET 15, the charge control FET 14 is turned on and the discharge control FET 15 is turned off.
　図２は図１のスイッチ回路３及び昇圧回路６の構成例を示すブロック図である。 FIG. 2 is a block diagram showing a configuration example of the switch circuit 3 and booster circuit 6 in FIG. 1.
　図２において、スイッチ回路３は、制御回路３Ａと、スイッチ４，５とを備えて構成され、上述のように動作する。昇圧回路６は一般的なチャージポンプ回路であって、制御回路６Ａと、４個のスイッチ６ａ～６ｄと、昇圧用コンデンサＣ１とを備えて構成される。昇圧回路６において、スイッチ回路３からの出力電圧ＶＳＷは制御回路６Ａの電源電圧として供給されるとともに、スイッチ６ａ，６ｂを介して昇圧電圧ＶＣＰとして駆動回路７に出力される。電池電圧ＶＤＤは、スイッチ６ｃ，６ｄを介して接地される。ここで、スイッチ６ａとスイッチ６ｂの接続点は、昇圧用コンデンサＣ１を介してスイッチ６ｃとスイッチ６ｄの接続点に接続される。 In FIG. 2, the switch circuit 3 includes a control circuit 3A and switches 4 and 5, and operates as described above. The booster circuit 6 is a general charge pump circuit, and includes a control circuit 6A, four switches 6a to 6d, and a booster capacitor C1. In the booster circuit 6, the output voltage VSW from the switch circuit 3 is supplied as a power supply voltage to the control circuit 6A, and is also output to the drive circuit 7 as a boosted voltage VCP via the switches 6a and 6b. Battery voltage VDD is grounded via switches 6c and 6d. Here, the connection point between the switch 6a and the switch 6b is connected to the connection point between the switch 6c and the switch 6d via a boosting capacitor C1.
　以上のように構成された昇圧回路６において、制御回路６Ａは所定のクロックに従って、
（１）スイッチ６ａをオンし、スイッチ６ｂをオフし、スイッチ６ｃをオフしかつスイッチ６ｄをオンすることで、コンデンサＣ１に対して出力電圧ＶＳＷ－接地電圧ＶＳＳ間の電圧差分の電荷を充電する動作と、
（２）スイッチ６ａをオフし、スイッチ６ｂをオンし、スイッチ６ｃをオンしかつスイッチ６ｄをオフすることで、昇圧電圧ＶＣＰ（＝ＶＤＤ＋ＶＳＷ）を発生して駆動回路７に出力する動作と、
を繰り返すように昇圧回路６の動作を制御する。スイッチ回路３において、電池電圧ＶＤＤが過放電検出しきい値Ｖｔｈｅ以上である場合、過放電検出回路２からのＨレベルの検出信号Ｓ２に応答して、スイッチ５をオンしかつスイッチ４をオフとし、正極端子２１の正極電圧ＶＤＤはスイッチ５を介して出力電圧ＶＳＷとして昇圧回路６に供給される。出力電圧ＶＳＷは、前述の通り電池電圧ＶＤＤと導通しているためＶＣＰ＝ＶＤＤ＋ＶＤＤとなる。 In the booster circuit 6 configured as described above, the control circuit 6A operates according to a predetermined clock.
(1) By turning on the switch 6a, turning off the switch 6b, turning off the switch 6c, and turning on the switch 6d, the capacitor C1 is charged with the voltage difference between the output voltage VSW and the ground voltage VSS. movement and
(2) generating a boosted voltage VCP (=VDD+VSW) and outputting it to the drive circuit 7 by turning off the switch 6a, turning on the switch 6b, turning on the switch 6c, and turning off the switch 6d;
The operation of the booster circuit 6 is controlled so that the following steps are repeated. In the switch circuit 3, when the battery voltage VDD is equal to or higher than the overdischarge detection threshold Vthe, the switch 5 is turned on and the switch 4 is turned off in response to the H level detection signal S2 from the overdischarge detection circuit 2. , the positive voltage VDD of the positive terminal 21 is supplied to the booster circuit 6 via the switch 5 as the output voltage VSW. Since the output voltage VSW is electrically connected to the battery voltage VDD as described above, VCP=VDD+VDD.
　一方、電池電圧ＶＤＤが前記過放電検出しきい値Ｖｔｈｅを下回る場合、過放電検出回路２からのＬレベルの検出信号Ｓ２に応答して、スイッチ５をオフしかつスイッチ４をオンとし、正極端子１３の正極電圧ＶＰ＋はスイッチ４を介して出力電圧ＶＳＷとして昇圧回路６に供給される。この際、出力電圧ＶＳＷは前述の通り正極端子１３と導通しているため、昇圧電圧ＶＣＰ＝ＶＤＤ＋ＶＰ＋となる。 On the other hand, when the battery voltage VDD is lower than the overdischarge detection threshold Vthe, the switch 5 is turned off and the switch 4 is turned on in response to the L level detection signal S2 from the overdischarge detection circuit 2, and the positive terminal The positive voltage VP + of 13 is supplied to the booster circuit 6 via the switch 4 as the output voltage VSW. At this time, since the output voltage VSW is electrically connected to the positive terminal 13 as described above, the boosted voltage VCP=VDD+VP + .
　次いで、本実施形態に係るゼロボルト電池に対して充電を行う手法と、充電を可能とする充電器ＣＨ１の出力電圧条件について説明する。 Next, a method of charging the zero-volt battery according to the present embodiment and an output voltage condition of the charger CH1 that enables charging will be explained.
（Ａ）電池電圧ＶＤＤが所定の過放電検出しきい値Ｖｔｈｅ以上の場合、過放電検出回路２は「過放電非検出」状態であり、Ｈレベルの検出信号Ｓ２を出力するので、スイッチ回路３のスイッチ５をオンし、スイッチ４をオフすることで、電池電圧ＶＤＤを出力電圧ＶＳＷとして昇圧回路６に出力させる。すなわち、ＶＳＷ＝ＶＤＤとなる。従って、充電器ＣＨ１の接続の有無にかかわらず、昇圧回路６によって生成される昇圧電圧ＶＣＰは次式で表される。 (A) When the battery voltage VDD is equal to or higher than the predetermined overdischarge detection threshold Vthe, the overdischarge detection circuit 2 is in the "overdischarge non-detection" state and outputs the H level detection signal S2, so the switch circuit 3 By turning on switch 5 and turning off switch 4, battery voltage VDD is outputted to booster circuit 6 as output voltage VSW. That is, VSW=VDD. Therefore, regardless of whether charger CH1 is connected or not, boosted voltage VCP generated by booster circuit 6 is expressed by the following equation.
ＶＣＰ＝ＶＤＤ＋ＶＳＷ＝ＶＤＤ＋ＶＤＤ＝２×ＶＤＤ VCP=VDD+VSW=VDD+VDD=2×VDD
　このとき、駆動回路７はＨレベル（＝ＶＣＰ）の制御信号ＣＯＵＴ，ＤＯＵＴをそれぞれ充電制御ＦＥＴ１４，放電制御ＦＥＴ１５の各ゲートに出力して、充電制御ＦＥＴ１４，放電制御ＦＥＴ１５をともにオンにする。 At this time, the drive circuit 7 outputs H level (=VCP) control signals COUT and DOUT to the respective gates of the charge control FET 14 and the discharge control FET 15, thereby turning on both the charge control FET 14 and the discharge control FET 15.
（Ｂ）一方、ゼロボルト電池に対して充電を行う場合、すなわち電池電圧ＶＤＤが前記過放電検出しきい値Ｖｔｈｅを下回っている場合、過放電検出回路２は「過放電検出」状態であり、Ｌレベルの検出信号Ｓ２を出力するので、駆動回路７はＬレベル（＝ＶＳＳ）の制御信号ＤＯＵＴを放電制御ＦＥＴ１５のゲートに出力することで放電制御ＦＥＴ１５をオフにする。スイッチ回路３はスイッチ５をオフしかつスイッチ４をオンして、充電器電圧ＶＰ＋を出力電圧ＶＳＷとして出力する。すなわち、ＶＳＷ＝ＶＰ＋となる。 (B) On the other hand, when charging a zero-volt battery, that is, when the battery voltage VDD is lower than the overdischarge detection threshold Vthe, the overdischarge detection circuit 2 is in the "overdischarge detection" state, and the Since the level detection signal S2 is output, the drive circuit 7 turns off the discharge control FET 15 by outputting the L level (=VSS) control signal DOUT to the gate of the discharge control FET 15. The switch circuit 3 turns off the switch 5 and turns on the switch 4 to output the charger voltage VP + as the output voltage VSW. That is, VSW=VP + .
　充電器ＣＨ１が接続されていない場合、放電制御ＦＥＴ１５がオフしており、二次電池Ｂ１からの放電パスが遮断されているため、正極端子１３の正極電圧ＶＰ＋はシステム負荷ＲＬによって接地電圧ＶＳＳへプルダウンされる。すなわち、ＶＳＷ＝ＶＳＳ（＝０Ｖ）となる。ここで、昇圧回路６は出力電圧ＶＳＷを電源電圧として用いているため、この場合は昇圧動作をせず、充電制御ＦＥＴ１４はオンに駆動するような昇圧電圧ＶＣＰを駆動回路７に供給しないため充電制御ＦＥＴ１４はオフに駆動される。 When the charger CH1 is not connected, the discharge control FET 15 is off and the discharge path from the secondary battery B1 is cut off, so the positive voltage VP + of the positive terminal 13 is lowered to the ground voltage VSS by the system load RL. pulled down to That is, VSW=VSS (=0V). Here, since the boost circuit 6 uses the output voltage VSW as the power supply voltage, it does not perform a boost operation in this case, and the charge control FET 14 does not supply the drive circuit 7 with the boost voltage VCP that turns it on, so it charges Control FET 14 is driven off.
　一方、充電器ＣＨ１が接続された場合、正極電圧ＶＰ＋は充電器ＣＨ１の出力電圧と等しい。従って、充電器出力電圧ＶＰ＋＝ＶＳＷとなる。昇圧回路６は出力電圧ＶＳＷを電源電圧として昇圧動作を行い、駆動回路７はＨレベル（＝ＶＣＰ）の制御信号ＣＯＵＴを充電制御ＦＥＴ１４のゲートに出力することで充電制御ＦＥＴ１４をオンさせ、充電パスを導通させることでゼロボルト電池に対する充電を可能とする。ここで、昇圧回路６の昇圧動作によって生成される昇圧電圧ＶＣＰは次式で表される。 On the other hand, when the charger CH1 is connected, the positive electrode voltage VP + is equal to the output voltage of the charger CH1. Therefore, the charger output voltage VP + =VSW. The boost circuit 6 performs a boost operation using the output voltage VSW as the power supply voltage, and the drive circuit 7 turns on the charge control FET 14 by outputting an H level (=VCP) control signal COUT to the gate of the charge control FET 14, thereby setting the charge path. By making it conductive, it is possible to charge a zero-volt battery. Here, the boosted voltage VCP generated by the boosting operation of the booster circuit 6 is expressed by the following equation.
ＶＣＰ＝ＶＤＤ＋ＶＳＷ＝ＶＤＤ＋ＶＰ＋ VCP=VDD+VSW=VDD+VP +
　ここで、充電制御ＦＥＴ１４のゲート－ソース間電圧をＶｇｓとし、充電器ＣＨ１の供給電流を駆動するために必要な充電制御ＦＥＴ１４のゲート－ソース間電圧をＶｔｈとすると、充電制御ＦＥＴ１４のゲート電圧Ｖｇとソース電圧Ｖｓの差電圧（Ｖｇ－Ｖｓ）は次式で表される。 Here, if the gate-source voltage of the charge control FET 14 is Vgs, and the gate-source voltage of the charge control FET 14 required to drive the supply current of the charger CH1 is Vth, then the gate voltage of the charge control FET 14 is Vg. The difference voltage (Vg-Vs) between the source voltage Vs and the source voltage Vs is expressed by the following equation.
Ｖｇ－Ｖｓ
＝ＣＯＵＴ－ＶＤＤ
＝（ＶＤＤ＋ＶＰ＋）－ＶＤＤ
＝ＶＰ＋ Vg-Vs
=COUT-VDD
=(VDD+VP + )-VDD
=VP +
　ここで、充電を可能とする条件は、Ｖｇｓ≧Ｖｔｈ、すなわち、Ｐ＋≧Ｖｔｈとなる。 Here, the condition for enabling charging is Vgs≧Vth, that is, P + ≧Vth.
　図３は従来例２に係る二次電池保護回路において、充電器接続以降の各電圧を示すタイミングチャートである。また、図４は図１の二次電池保護回路１６において、充電器接続以降の各電圧を示すタイミングチャートである。以下、図３及び図４を参照して、従来例２と実施形態１におけるゼロボルト電池に対する充電時におけるタイミングチャートについて説明する。 FIG. 3 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit according to Conventional Example 2. Further, FIG. 4 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit 16 of FIG. 1. Timing charts during charging of zero-volt batteries in Conventional Example 2 and Embodiment 1 will be described below with reference to FIGS. 3 and 4.
　従来例２に係る二次電池保護回路において、ゼロボルト付近の二次電池に充電器が接続されると、充電を可能とする充電器の出力電圧条件を満たす電圧まで正極端子１３と負極端子１２との間に電位差を発生させる。具体的には、充電制御ＦＥＴ１４のゲートソース間電圧Ｖｇｓは次式で表される。 In the secondary battery protection circuit according to Conventional Example 2, when a charger is connected to a secondary battery near zero volts, the positive terminal 13 and the negative terminal 12 are connected to a voltage that satisfies the output voltage condition of the charger to enable charging. Generates a potential difference between Specifically, the gate-source voltage Vgs of the charge control FET 14 is expressed by the following equation.
Ｖｇｓ＝ＣＯＵＴ－ＶＤＤ Vgs=COUT-VDD
　ここで、制御信号の電圧ＣＯＵＴは次式で表される（図３）。
ＣＯＵＴ＝ＶＰ＋ Here, the voltage COUT of the control signal is expressed by the following equation (FIG. 3).
COUT=VP +
　従って、次式となる。 Therefore, the following formula is obtained.
Ｖｇｓ＝ＶＰ＋－ＶＤＤ Vgs=VP + -VDD
　充電器ＣＨ１の供給電流を駆動するために必要な充電制御ＦＥＴ１４のゲート－ソース間電圧をＶｔｈとすると、充電を可能とする条件は、Ｖｇｓ≧Ｖｔｈであることから、ＶＰ＋－ＶＤＤ≧Ｖｔｈとなり、すなわち、ＶＰ＋≧ＶＤＤ＋Ｖｔｈとなる（図３）。 If the gate-source voltage of charge control FET 14 required to drive the supply current of charger CH1 is Vth, then the condition for enabling charging is Vgs≧Vth, so VP + -VDD≧Vth. , that is, VP + ≧VDD+Vth (FIG. 3).
　実施形態１に係る二次電池保護回路１６において、充電制御ＦＥＴ１４のゲート－ソース間電圧をＶｇｓとし、充電器ＣＨ１の供給電流を駆動するために必要な充電制御ＦＥＴ１４のゲート－ソース間電圧をＶｔｈとすると、次式で表される。 In the secondary battery protection circuit 16 according to the first embodiment, the gate-source voltage of the charge control FET 14 is Vgs, and the gate-source voltage of the charge control FET 14 required to drive the supply current of the charger CH1 is Vth. Then, it is expressed by the following formula.
ＣＯＵＴ＝ＶＣＰ＝ＶＤＤ＋ＶＳＷ＝ＶＤＤ＋ＶＰ＋ COUT=VCP=VDD+VSW=VDD+VP +
　従って、次式で表される。 Therefore, it is expressed by the following formula.
Ｖｇｓ＝ＣＯＵＴ－ＶＤＤ＝（ＶＤＤ＋Ｐ＋）－ＶＤＤ＝Ｐ＋ Vgs=COUT-VDD=(VDD+P + )-VDD=P +
　ここで、充電を可能とする条件は、Ｖｇｓ＞Ｖｔｈ、すなわち、Ｐ＋≧Ｖｔｈとなる（図４）。図４から明らかなように、従来例２とは異なり、電池電圧ＶＤＤに依存しないため、結果として従来例２よりも低い充電器電圧で充電される。一方、充電がさらに進行することでＶＤＤ電圧が上昇した場合の充電開始条件は、放電制御ＦＥＴ１５のボディダイオード１１の順方向電圧をＶｆとし、充電制御ＦＥＴのドレイン－ソース間電圧をＶｄｓとすると、次式で表される。 Here, the condition that enables charging is Vgs>Vth, that is, P+≧Vth (FIG. 4). As is clear from FIG. 4, unlike the second conventional example, it does not depend on the battery voltage VDD, and as a result, it is charged with a lower charger voltage than the second conventional example. On the other hand, when the VDD voltage increases as charging progresses further, the conditions for starting charging are as follows, assuming that the forward voltage of the body diode 11 of the discharge control FET 15 is Vf, and the drain-source voltage of the charge control FET is Vds. It is expressed by the following formula.
ＶＰ＋≧ＶＤＤ＋Ｖｄｓ＋Ｖｆ VP + ≧VDD+Vds+Vf
　この条件を満たすために充電器ＣＨ１は正極電圧ＶＰ＋を上昇させることでＣＣ充電を行う。図３の従来例２では、充電開始直後から電池電圧ＶＤＤの上昇に伴って正極電圧ＶＰ＋が上昇する。これに対して、図４の実施形態１では、充電開始後、所定時間期間において、正極電圧ＶＰ＋が上昇しない時間期間があるため、従来例２よりも低い充電器電圧で充電を維持することができる。 In order to satisfy this condition, the charger CH1 performs CC charging by increasing the positive electrode voltage VP + . In the conventional example 2 shown in FIG. 3, the positive electrode voltage VP + increases as the battery voltage VDD increases immediately after the start of charging. On the other hand, in Embodiment 1 of FIG. 4, since there is a time period in which the positive electrode voltage VP + does not rise during a predetermined time period after the start of charging, charging can be maintained at a lower charger voltage than in Conventional Example 2. Can be done.
　以上説明したように、実施形態１によれば、図４から明らかなように、従来よりも低い充電器電圧でゼロボルト付近の二次電池Ｂ１に対して充電することで、従来技術よりも発熱損失を低減できる。 As explained above, according to the first embodiment, as is clear from FIG. 4, by charging the secondary battery B1 near zero volts with a charger voltage lower than that of the conventional technique, the heat generation loss is lower than that of the conventional technique. can be reduced.
（実施形態２）
　図５Ａは本発明の実施形態２に係る電池パックＢＰ２とその周辺回路の構成例を示す回路図であり、図５Ｂは図５Ａのスイッチ回路３及び昇圧回路６の構成例を示すブロック図である。図５Ａの電池パックＢＰ２は、図１の電池パックＢＰ１に比較して以下の点が異なる。
（１）二次電池保護回路１６に代えて、電圧検出回路１をさらに備えた二次電池保護回路１６Ａを備えた。
（２）二次電池保護装置２０に代えて、二次電池保護回路１６Ａを備えた二次電池保護装置２０Ａを備えた。
（３）昇圧回路６は、制御回路６Ａに代えて、制御回路６Ｂを備える。
　以下、相違点について説明する。 (Embodiment 2)
FIG. 5A is a circuit diagram showing a configuration example of a battery pack BP2 and its peripheral circuits according to Embodiment 2 of the present invention, and FIG. 5B is a block diagram showing a configuration example of the switch circuit 3 and booster circuit 6 in FIG. 5A. . Battery pack BP2 in FIG. 5A differs from battery pack BP1 in FIG. 1 in the following points.
(1) In place of the secondary battery protection circuit 16, a secondary battery protection circuit 16A further including the voltage detection circuit 1 was provided.
(2) In place of the secondary battery protection device 20, a secondary battery protection device 20A including a secondary battery protection circuit 16A was provided.
(3) The booster circuit 6 includes a control circuit 6B instead of the control circuit 6A.
The differences will be explained below.
　図５Ａにおいて、電圧検出回路１は正極電圧ＶＰ＋を所定の電圧しきい値Ｖｔｈｄと比較して、比較結果信号である検出信号Ｓ１を発生する。ここで、電圧検出回路１は、正極電圧ＶＰ＋が前記電圧しきい値Ｖｔｈｄ以上の場合は、昇圧回路６の正常動作可能状態である期間として判断し、Ｈレベルの検出信号Ｓ１を駆動回路７に出力する。一方、電圧検出回路１は、正極電圧ＶＰ＋が所定の電圧しきい値Ｖｔｈｄ未満の場合は、昇圧回路６の正常動作可能状態ではない期間として判断し、Ｌレベルの検出信号Ｓ１を駆動回路７に出力する。ここで、電圧しきい値Ｖｔｈｄは昇圧回路６の最低動作電圧よりも高く設定される。 In FIG. 5A, the voltage detection circuit 1 compares the positive voltage VP + with a predetermined voltage threshold Vthd and generates a detection signal S1 that is a comparison result signal. Here, when the positive electrode voltage VP Output to. On the other hand, if the positive voltage VP Output to. Here, the voltage threshold Vthd is set higher than the lowest operating voltage of the booster circuit 6.
　また、図５Ａ及び図５Ｂにおいて、昇圧回路６の制御回路６Ｂは、電圧検出回路１からのＨレベルの検出信号Ｓ１に応答して昇圧回路６を動作させるが、過放電検出回路２からのＨレベルの検出信号Ｓ２（過放電検出信号）及びＬレベルの検出信号Ｓ１に応答して昇圧回路６の昇圧動作を停止させる。なお、電圧検出回路１からの検出信号Ｓ１は駆動回路７にも出力され、昇圧回路６の昇圧動作の停止を通知する。 5A and 5B, the control circuit 6B of the booster circuit 6 operates the booster circuit 6 in response to the H level detection signal S1 from the voltage detection circuit 1, but the control circuit 6B operates the booster circuit 6 in response to the H level detection signal S1 from the voltage detection circuit 2. The boosting operation of the booster circuit 6 is stopped in response to the level detection signal S2 (over-discharge detection signal) and the L level detection signal S1. Note that the detection signal S1 from the voltage detection circuit 1 is also output to the drive circuit 7 to notify that the boosting operation of the boosting circuit 6 has stopped.
　以上のように構成された実施形態２において「電圧検出回路１」をさらに備えた作用効果について以下に説明する。 The effects of further including the "voltage detection circuit 1" in the second embodiment configured as above will be described below.
　過放電検出回路２が二次電池Ｂ１の「過放電」状態を検出し、放電制御ＦＥＴ１５がオフに駆動され二次電池Ｂ１からの放電が停止すると、正極電圧ＶＰ＋と負極電圧ＶＰ－との間の電圧はシステム負荷ＲＬによって０Ｖにプルダウンされる。その際に、充電器ＣＨ１を接続すると、正極電圧ＶＰ＋が０Ｖから徐々に大きくなる動作をする。このとき、ゼロボルト電池に対して充電を行うために、スイッチ回路３のスイッチ５をオフしかつスイッチ４をオンして正極電圧ＶＰ＋である出力電圧ＶＳＷを、昇圧回路６の電源電圧として供給した場合において、正極電圧ＶＰ＋が０Ｖから昇圧回路６の最低動作電圧に至るまでの間（昇圧回路６の正常動作可能状態ではない期間）に昇圧回路６が起動すると、昇圧回路６の構成次第では誤動作又は貫通電流を生じることが想定される。 When the overdischarge detection circuit 2 detects the "overdischarge" state of the secondary battery B1 and the discharge control FET 15 is driven off to stop discharging from the secondary battery B1, the positive electrode voltage VP + and the negative electrode voltage VP - are The voltage between is pulled down to 0V by the system load RL. At this time, when the charger CH1 is connected, the positive electrode voltage VP + gradually increases from 0V. At this time, in order to charge the zero-volt battery, the switch 5 of the switch circuit 3 was turned off and the switch 4 was turned on to supply the output voltage VSW, which is the positive voltage VP + , as the power supply voltage of the booster circuit 6. In this case, if the booster circuit 6 starts up while the positive voltage VP + reaches the lowest operating voltage of the booster circuit 6 from 0V (a period in which the booster circuit 6 is not in a normal operating state), depending on the configuration of the booster circuit 6, It is assumed that malfunction or through current may occur.
　従って、実施形態２では、正極電圧ＶＰ＋が昇圧回路６の最低動作電圧未満の時（昇圧回路６の正常動作可能状態ではない期間）は昇圧回路６を停止するように制御している。これにより、正極電圧ＶＰ＋が昇圧回路６の最低動作電圧未満の時に昇圧回路６が起動することを回避し、昇圧回路６の誤動作又は貫通電流が発生することを防止できる。また、故障に起因して異常な低い電圧を出力する充電器ＣＨ１が接続され、正極端子１３に昇圧回路６の最低動作電圧未満の電圧が定常的に印加されるケースにおいても同様に、電圧検出回路１は「非検出」状態であり、Ｌレベルの検出信号Ｓ１を出力し、昇圧回路６を停止することで、昇圧回路６の誤動作又は貫通電流が発生することを防止できる。 Therefore, in the second embodiment, when the positive voltage VP + is less than the minimum operating voltage of the booster circuit 6 (during a period in which the booster circuit 6 is not in a normal operable state), the booster circuit 6 is controlled to be stopped. This prevents the booster circuit 6 from starting when the positive voltage VP + is less than the minimum operating voltage of the booster circuit 6, and prevents malfunction of the booster circuit 6 or occurrence of a through current. Similarly, in the case where the charger CH1 that outputs an abnormally low voltage due to a failure is connected and a voltage lower than the minimum operating voltage of the booster circuit 6 is constantly applied to the positive terminal 13, the voltage detection The circuit 1 is in a "non-detection" state, and by outputting the L-level detection signal S1 and stopping the booster circuit 6, it is possible to prevent the booster circuit 6 from malfunctioning or from generating a through current.
　また、実施形態２に係る二次電池保護回路１６Ａは、実施形態１に係る二次電池保護回路１６と同様の作用効果を有する。 Further, the secondary battery protection circuit 16A according to the second embodiment has the same effects as the secondary battery protection circuit 16 according to the first embodiment.
（実施形態３）
　図６は本発明の実施形態３に係る電池パックＢＰ３とその周辺回路の構成例を示す回路図である。図６の電池パックＢＰ３は、図２の電池パックＢＰ２に比較して以下の点が異なる。
（１）二次電池保護回路１６Ａに代えて、クランプ回路８をさらに備えた二次電池保護回路１６Ｂを備えた。
（２）二次電池保護装置２０Ａに代えて、二次電池保護回路１６Ｂを備えた二次電池保護装置２０Ｂを備えた。
　以下、相違点について説明する。 (Embodiment 3)
FIG. 6 is a circuit diagram showing a configuration example of a battery pack BP3 and its peripheral circuits according to the third embodiment of the present invention. Battery pack BP3 in FIG. 6 differs from battery pack BP2 in FIG. 2 in the following points.
(1) A secondary battery protection circuit 16B further including a clamp circuit 8 was provided in place of the secondary battery protection circuit 16A.
(2) A secondary battery protection device 20B including a secondary battery protection circuit 16B was provided in place of the secondary battery protection device 20A.
The differences will be explained below.
　図６において、クランプ回路８は、正極電圧ＶＰ＋と負極電圧ＶＰ－（＝ＶＳＳ）との間の電圧を、スイッチ４，５及び昇圧回路６の耐圧を下回る一定のクランプ電圧ＶＣＬにクランプして、スイッチ回路３のスイッチ４の一端に出力する。 In FIG. 6, the clamp circuit 8 clamps the voltage between the positive voltage VP + and the negative voltage VP - (=VSS) to a constant clamp voltage VCL that is lower than the withstand voltage of the switches 4 and 5 and the booster circuit 6. , is output to one end of the switch 4 of the switch circuit 3.
　以上のように構成された実施形態３において「クランプ回路８」をさらに備えた作用効果について以下に説明する。 The effects of further including the "clamp circuit 8" in the third embodiment configured as above will be described below.
　図１又は図５Ａにおいて、
（１）電池電圧ＶＤＤが前記過放電しきい値Ｖｔｈｅを下回ったことを過放電検出回路２が検出してＬレベルの検出信号Ｓ２を出力することで、
（２）スイッチ回路３のスイッチ５をオフしかつスイッチ４をオンし、出力電圧ＶＳＷとして正極電圧ＶＰ＋が出力された状態で、
（３）正極端子１３に電圧しきい値Ｖｔｈｄ以上の電圧を出力する充電器ＣＨ１が接続され、
（４）電圧検出回路１が当該充電器ＣＨ１の接続を検知し、
（５）昇圧回路６が昇圧動作を行い駆動回路７がＨレベル（＝ＶＣＰ）の制御信号ＣＯＵＴを充電制御ＦＥＴ１４のゲートに出力して充電制御ＦＥＴ１４をオンさせてゼロボルト付近の二次電池Ｂ１に対して充電をしている最中に、
（６）充電器ＣＨ１が何らかの原因によって故障し、
（７）出力電圧が急峻に変化して高電圧をＰ＋に出力すると、出力電圧ＶＳＷは、より高い電圧となる。
（８）すなわち、出力電圧ＶＳＷに接続されたスイッチ４，５及び昇圧回路６に対して耐圧を上回る高い電圧が印加され、スイッチ４，５及び昇圧回路６が破壊されることが想定される。 In FIG. 1 or FIG. 5A,
(1) The overdischarge detection circuit 2 detects that the battery voltage VDD has fallen below the overdischarge threshold Vthe and outputs an L level detection signal S2,
(2) With the switch 5 of the switch circuit 3 turned off and the switch 4 turned on, and the positive voltage VP + being output as the output voltage VSW,
(3) A charger CH1 that outputs a voltage equal to or higher than the voltage threshold Vthd is connected to the positive terminal 13,
(4) The voltage detection circuit 1 detects the connection of the charger CH1,
(5) The boost circuit 6 performs a boost operation, and the drive circuit 7 outputs an H level (=VCP) control signal COUT to the gate of the charge control FET 14, turns on the charge control FET 14, and charges the secondary battery B1 near zero volts. While charging,
(6) Charger CH1 breaks down for some reason,
(7) When the output voltage changes abruptly and a high voltage is output to P + , the output voltage VSW becomes a higher voltage.
(8) That is, it is assumed that a voltage higher than the withstand voltage is applied to the switches 4 and 5 and the booster circuit 6 connected to the output voltage VSW, and the switches 4 and 5 and the booster circuit 6 are destroyed.
　この課題を解決するために、スイッチ４，５及び昇圧回路６を高耐圧素子で構成することが考えられるが、面積の増大、半導体製造装置の製造工程に用いるマスク枚数の増加及びリードタイムの増大というデメリットが発生する。 In order to solve this problem, it is possible to configure the switches 4, 5 and the booster circuit 6 with high voltage elements, but this would increase the area, increase the number of masks used in the manufacturing process of semiconductor manufacturing equipment, and increase lead time. A disadvantage arises.
　以上説明したように、実施形態３によれば、クランプ回路８をさらに備えることで、スイッチ４，５及び昇圧回路６の破壊を回避することができる。 As explained above, according to the third embodiment, by further providing the clamp circuit 8, it is possible to avoid destruction of the switches 4 and 5 and the booster circuit 6.
　また、二次電池Ｂ１は通常４．２Ｖ以下で利用されるため、二次電池保護回路１６Ｂを半導体集積回路（ＩＣ）で構成する場合、電池電圧のみに接続される保護回路ＩＣは一般的に５Ｖ系プロセスの素子が利用される。従って、クランプ回路８からのクランプ電圧ＶＣＬの設定を５Ｖ以下にすることで、スイッチ４，５及び昇圧回路６を含む二次電池保護回路１６Ｂを、保護回路ＩＣにおいて一般的に利用されている５Ｖ系プロセスの低耐圧素子で構成することが可能となる。それゆえ、省面積、マスク枚数の低減及びリードタイム短縮のメリットを得ることができる。 In addition, since the secondary battery B1 is normally used at 4.2V or less, when the secondary battery protection circuit 16B is configured with a semiconductor integrated circuit (IC), the protection circuit IC that is connected only to the battery voltage is generally A 5V process element is used. Therefore, by setting the clamp voltage VCL from the clamp circuit 8 to 5V or less, the secondary battery protection circuit 16B including the switches 4 and 5 and the booster circuit 6 can be operated at 5V, which is generally used in protection circuit ICs. It becomes possible to construct the device using low-voltage elements processed using a system process. Therefore, it is possible to obtain the advantages of saving area, reducing the number of masks, and shortening lead time.
　また、実施形態３に係る二次電池保護回路１６Ｂは、実施形態１，２に係る二次電池保護回路１６，１６Ａと同様の作用効果を有する。 Further, the secondary battery protection circuit 16B according to the third embodiment has the same effects as the secondary battery protection circuits 16 and 16A according to the first and second embodiments.
　以上の図６の実施形態３において、電圧検出回路１を削除してもよい（実施形態３の変形例）。 In the third embodiment shown in FIG. 6 above, the voltage detection circuit 1 may be deleted (a modification of the third embodiment).
（実施形態４）
　図７は本発明の実施形態４に係る電池パックＢＰ４とその周辺回路の構成例を示す回路図である。図７の電池パックＢＰ４は、図６の電池パックＢＰ３に比較して以下の点が異なる。
（１）二次電池保護回路１６Ｂに代えて、クランプ回路８の挿入位置を変更した二次電池保護回路１６Ｃを備えた。クランプ回路８は、正極端子１３と、電圧検出回路１及びスイッチ回路３のスイッチ４の一端との間に挿入された。
（２）二次電池保護装置２０Ｂに代えて、二次電池保護回路１６Ｃを備えた二次電池保護装置２０Ｃを備えた。
　以下、相違点について説明する。 (Embodiment 4)
FIG. 7 is a circuit diagram showing a configuration example of a battery pack BP4 and its peripheral circuits according to Embodiment 4 of the present invention. Battery pack BP4 in FIG. 7 differs from battery pack BP3 in FIG. 6 in the following points.
(1) In place of the secondary battery protection circuit 16B, a secondary battery protection circuit 16C is provided in which the insertion position of the clamp circuit 8 is changed. The clamp circuit 8 was inserted between the positive terminal 13 and one end of the switch 4 of the voltage detection circuit 1 and the switch circuit 3.
(2) In place of the secondary battery protection device 20B, a secondary battery protection device 20C including a secondary battery protection circuit 16C was provided.
The differences will be explained below.
　図７において、クランプ回路８は、正極電圧ＶＰ＋と負極電圧ＶＰ－（＝ＶＳＳ）との間の電圧をクランプして、スイッチ４，５及び昇圧回路６の耐圧を下回る一定のクランプ電圧ＶＣＬをスイッチ回路３のスイッチ４の一端及び電圧検出回路１に出力する。電圧検出回路１は、クランプ電圧ＶＣＬが前記電圧しきい値Ｖｔｈｄ以上の場合はＨレベルの検出信号Ｓ１を発生して駆動回路７に出力する一方、クランプ電圧ＶＣＬが前記電圧しきい値Ｖｔｈｄ未満の場合はＬレベルの検出信号Ｓ１を発生して駆動回路７に出力する。 In FIG. 7, a clamp circuit 8 clamps a voltage between a positive voltage VP + and a negative voltage VP - (=VSS) to maintain a constant clamp voltage VCL that is lower than the withstand voltage of the switches 4 and 5 and the booster circuit 6. It is output to one end of the switch 4 of the switch circuit 3 and the voltage detection circuit 1. The voltage detection circuit 1 generates an H-level detection signal S1 and outputs it to the drive circuit 7 when the clamp voltage VCL is equal to or higher than the voltage threshold Vthd, and when the clamp voltage VCL is less than the voltage threshold Vthd. In this case, an L level detection signal S1 is generated and output to the drive circuit 7.
　以上のように構成された実施形態４によれば、図７のように、電圧検出回路１をクランプ回路８の後段に配置し、クランプ回路８からのクランプ電圧ＶＣＬをモニタする構成にすることで、電圧検出回路１を５Ｖ系の低耐圧で構成することが可能となり、省面積、マスク枚数の低減及びリードタイム短縮のメリットを得ることができる。 According to the fourth embodiment configured as described above, as shown in FIG. It becomes possible to configure the voltage detection circuit 1 with a low withstand voltage of 5V system, and it is possible to obtain the advantages of saving area, reducing the number of masks, and shortening lead time.
　また、実施形態４に係る二次電池保護回路１６Ｃは、実施形態１～３に係る二次電池保護回路１６，１６Ａ～１６Ｂと同様の作用効果を有する。 Further, the secondary battery protection circuit 16C according to the fourth embodiment has the same effects as the secondary battery protection circuits 16, 16A to 16B according to the first to third embodiments.
（実施形態５）
　図８Ａは本発明の実施形態５に係る電池パックＢＰ５とその周辺回路の構成例を示す回路図である。図８Ａの電池パックＢＰ５は、図７の電池パックＢＰ４に比較して以下の点が異なる。
（１）二次電池保護回路１６Ｃに代えて、電圧検出回路１７をさらに備えた二次電池保護回路１６Ｄを備えた。電圧検出回路１７は、正極端子１３及びクランプ回路８と、電圧検出回路１との間に挿入された。
（２）二次電池保護装置２０Ｃに代えて、二次電池保護回路１６Ｄを備えた二次電池保護装置２０Ｄを備えた。
　以下、相違点について説明する。 (Embodiment 5)
FIG. 8A is a circuit diagram showing a configuration example of a battery pack BP5 and its peripheral circuits according to Embodiment 5 of the present invention. The battery pack BP5 of FIG. 8A differs from the battery pack BP4 of FIG. 7 in the following points.
(1) A secondary battery protection circuit 16D further including a voltage detection circuit 17 was provided in place of the secondary battery protection circuit 16C. Voltage detection circuit 17 was inserted between positive terminal 13 and clamp circuit 8, and voltage detection circuit 1.
(2) A secondary battery protection device 20D including a secondary battery protection circuit 16D was provided in place of the secondary battery protection device 20C.
The differences will be explained below.
　図８Ａにおいて、電圧検出回路１７は充電器電圧である正極電圧ＶＰ＋をモニタする充電器電圧監視回路であり、電圧検出回路１の電圧しきい値Ｖｔｈｄよりも高く設定された電圧しきい値Ｖｔｈｆを有する。電圧検出回路１７は正極電圧ＶＰ＋を電圧しきい値Ｖｔｈｆと比較することで、いわゆる「高電圧」を検出して、以下のように、比較結果信号である検出信号Ｓ１７を発生する。
（Ａ）電圧検出回路１７は、正極電圧ＶＰ＋が電圧しきい値Ｖｔｈｆ以上となった場合、Ｈレベル（＝ＶＣＬ）の検出信号Ｓ１７を発生して電圧検出回路１に出力する。
（Ｂ）一方、電圧検出回路１７は、正極電圧ＶＰ＋が電圧しきい値Ｖｔｈｆ未満の場合、Ｌレベル（＝ＶＳＳ）の検出信号Ｓ１７を発生して電圧検出回路１に出力する。 In FIG. 8A, the voltage detection circuit 17 is a charger voltage monitoring circuit that monitors the positive electrode voltage VP + , which is the charger voltage, and has a voltage threshold Vthf set higher than the voltage threshold Vthd of the voltage detection circuit 1. has. The voltage detection circuit 17 detects a so-called "high voltage" by comparing the positive voltage VP + with a voltage threshold Vthf, and generates a detection signal S17 as a comparison result signal as described below.
(A) The voltage detection circuit 17 generates an H level (=VCL) detection signal S17 and outputs it to the voltage detection circuit 1 when the positive voltage VP + becomes equal to or higher than the voltage threshold Vthf.
(B) On the other hand, when the positive voltage VP + is less than the voltage threshold Vthf, the voltage detection circuit 17 generates an L level (=VSS) detection signal S17 and outputs it to the voltage detection circuit 1 .
　電圧検出回路１は、Ｈレベルの検出信号Ｓ１７に応答してＬレベル（＝ＶＳＳ）の検出信号Ｓ１を発生して駆動回路７及び昇圧回路６の制御回路６Ｂに出力する。一方、電圧検出回路１は、Ｌレベルの検出信号Ｓ１７に応答して、正極電圧ＶＰ＋が電圧しきい値Ｖｔｈｄ以上の場合はＨレベル（＝ＶＣＬ）の検出信号Ｓ１を発生して駆動回路７及び昇圧回路６の制御回路６Ｂに出力し、正極電圧ＶＰ＋が電圧しきい値Ｖｔｈｄ未満である場合はＬレベル（＝ＶＳＳ）の検出信号Ｓ１を発生して駆動回路７及び昇圧回路６の制御回路６Ｂに出力する。 The voltage detection circuit 1 generates an L level (=VSS) detection signal S1 in response to the H level detection signal S17, and outputs it to the drive circuit 7 and the control circuit 6B of the booster circuit 6. On the other hand, in response to the L-level detection signal S17, the voltage detection circuit 1 generates an H-level (=VCL) detection signal S1 when the positive voltage VP+ is equal to or higher than the voltage threshold Vthd. It is output to the control circuit 6B of the booster circuit 6, and when the positive voltage VP + is less than the voltage threshold Vthd, it generates an L level (=VSS) detection signal S1 and outputs it to the control circuit 6B of the drive circuit 7 and the booster circuit 6. Output to 6B.
　次いで、実施形態５に係る電圧検出回路１７の作用効果について以下に説明する。 Next, the effects of the voltage detection circuit 17 according to the fifth embodiment will be described below.
　従来例２及び実施形態１～４において、ゼロボルト付近の二次電池Ｂ１に、比較的高い電圧を出力する充電器ＣＨ１が正極端子１３と負極端子１２との間に接続された場合、正極端子ＶＰ＋（充電器電圧）と電池電圧ＶＤＤとの間の電位差が大きいため、二次電池Ｂ１に対して突入電流が流れこみ、二次電池Ｂ１の損傷や発火を引き起こすという課題がある。この課題を解決するために、電圧検出回路１７をさらに備えたものである。 In Conventional Example 2 and Embodiments 1 to 4, when the charger CH1 that outputs a relatively high voltage is connected between the positive terminal 13 and the negative terminal 12 to the secondary battery B1 near zero volt, the positive terminal VP Since the potential difference between + (charger voltage) and the battery voltage VDD is large, there is a problem in that an inrush current flows into the secondary battery B1, causing damage to the secondary battery B1 or ignition. In order to solve this problem, a voltage detection circuit 17 is further provided.
　図８Ａにおいて、電圧検出回路１７をさらに備えることにより、電圧しきい値Ｖｔｈｆ以上の比較的高い電圧を出力する充電器ＣＨ１が正極端子１３と負極端子１２との間に接続された場合、電圧検出回路１７は、Ｈレベル（＝ＶＣＬ）の検出信号Ｓ１７を発生して電圧検出回路１に出力することで、電圧検出回路１は、Ｈレベルの検出信号Ｓ１７に応答してＬレベル（＝ＶＳＳ）の検出信号Ｓ１を発生して駆動回路７及び昇圧回路６の制御回路６Ｂに出力する。従って、昇圧回路６は昇圧動作を行わず、駆動回路７はＬレベルの制御信号ＣＯＵＴを充電制御ＦＥＴ１４のゲートに出力するので、充電制御ＦＥＴ１４をオフにして充電パスを遮断する。結果として、ゼロボルト付近の二次電池Ｂ１に対する充電は開始されないため、二次電池Ｂ１に対する突入電流の流れ込みは発生せず、二次電池Ｂ１の損傷や発火を回避することができる。 In FIG. 8A, by further including the voltage detection circuit 17, when the charger CH1 that outputs a relatively high voltage equal to or higher than the voltage threshold Vthf is connected between the positive terminal 13 and the negative terminal 12, the voltage detection circuit 17 is The circuit 17 generates an H level (=VCL) detection signal S17 and outputs it to the voltage detection circuit 1, so that the voltage detection circuit 1 generates an L level (=VSS) in response to the H level detection signal S17. A detection signal S1 is generated and outputted to the drive circuit 7 and the control circuit 6B of the booster circuit 6. Therefore, the boost circuit 6 does not perform a boost operation, and the drive circuit 7 outputs the L-level control signal COUT to the gate of the charge control FET 14, thereby turning off the charge control FET 14 and cutting off the charging path. As a result, charging of the secondary battery B1 near zero volts is not started, so no inrush current flows into the secondary battery B1, and damage or ignition of the secondary battery B1 can be avoided.
　また、実施形態５に係る二次電池保護回路１６Ｄは、実施形態１～４に係る二次電池保護回路１６，１６Ａ～１６Ｃと同様の作用効果を有する。 Further, the secondary battery protection circuit 16D according to the fifth embodiment has the same effects as the secondary battery protection circuits 16, 16A to 16C according to the first to fourth embodiments.
（実施形態６）
　図８Ｂは本発明の実施形態６に係る電池パックＢＰ６とその周辺回路の構成例を示す回路図である。図８Ｂの電池パックＢＰ６は、図８Ａの電池パックＢＰ５に比較して以下の点が異なる。
（１）電圧検出回路１７は、正極電圧ＶＰ＋に代えて、クランプ回路８からのクランプ電圧ＶＣＬを検出する。
（２）二次電池保護回路１６Ｄを有する二次電池保護装置２０Ｄに代えて、二次電池保護回路１６Ｅを備えた二次電池保護装置２０Ｅを備えた。
　以下、相違点について説明する。 (Embodiment 6)
FIG. 8B is a circuit diagram showing a configuration example of a battery pack BP6 and its peripheral circuits according to Embodiment 6 of the present invention. The battery pack BP6 of FIG. 8B differs from the battery pack BP5 of FIG. 8A in the following points.
(1) The voltage detection circuit 17 detects the clamp voltage VCL from the clamp circuit 8 instead of the positive voltage VP + .
(2) In place of the secondary battery protection device 20D having the secondary battery protection circuit 16D, a secondary battery protection device 20E including the secondary battery protection circuit 16E was provided.
The differences will be explained below.
　図８Ｂにおいて、電圧検出回路１７はクランプ回路８からクランプ電圧ＶＣＬを介して正極電圧ＶＰ＋をモニタする充電器電圧監視回路であり、電圧検出回路１の電圧しきい値Ｖｔｈｄよりも高く設定された電圧しきい値Ｖｔｈｆを有する。このとき、電圧検出回路１７がクランプ回路８からのクランプ電圧ＶＣＬに基づいて、正極電圧ＶＰ＋が電圧しきい値Ｖｔｈｆ以上となったことを検出可能とするために、クランプ回路８からのクランプ電圧はＶｔｈｆより高く設定する。電圧検出回路１７はクランプ電圧ＶＣＬを電圧しきい値Ｖｔｈｆと比較することで、いわゆる「高電圧」を検出して、以下のように、比較結果信号である検出信号Ｓ１７を発生する。
（Ａ）電圧検出回路１７は、クランプ電圧ＶＣＬが電圧しきい値Ｖｔｈｆ以上となった場合、Ｈレベル（＝ＶＣＬ）の検出信号Ｓ１７を発生して電圧検出回路１に出力する。
（Ｂ）一方、電圧検出回路１７は、クランプ電圧ＶＣＬが電圧しきい値Ｖｔｈｆ未満の場合、Ｌレベル（＝ＶＳＳ）の検出信号Ｓ１７を発生して電圧検出回路１に出力する。 In FIG. 8B, the voltage detection circuit 17 is a charger voltage monitoring circuit that monitors the positive voltage VP + from the clamp circuit 8 via the clamp voltage VCL, and is set higher than the voltage threshold Vthd of the voltage detection circuit 1. It has a voltage threshold Vthf. At this time, in order to enable the voltage detection circuit 17 to detect, based on the clamp voltage VCL from the clamp circuit 8, that the positive voltage VP + has become equal to or higher than the voltage threshold Vthf, the clamp voltage from the clamp circuit 8 is is set higher than Vthf. The voltage detection circuit 17 detects a so-called "high voltage" by comparing the clamp voltage VCL with a voltage threshold Vthf, and generates a detection signal S17 as a comparison result signal as described below.
(A) The voltage detection circuit 17 generates an H level (=VCL) detection signal S17 and outputs it to the voltage detection circuit 1 when the clamp voltage VCL becomes equal to or higher than the voltage threshold Vthf.
(B) On the other hand, when the clamp voltage VCL is less than the voltage threshold Vthf, the voltage detection circuit 17 generates a detection signal S17 of L level (=VSS) and outputs it to the voltage detection circuit 1.
　以上のように構成された実施形態６に係る二次電池保護回路１６Ｅは、電圧検出回路１７の検出電圧を除き、実施形態５に係る二次電池保護回路１６Ｄと同様の作用効果を有する。 The secondary battery protection circuit 16E according to the sixth embodiment configured as described above has the same effects as the secondary battery protection circuit 16D according to the fifth embodiment except for the detection voltage of the voltage detection circuit 17.
（変形例）
　以上の実施形態において、過放電検出回路２は、二次電池Ｂ１の過放電を検出しているが、本発明はこれに限らず、例えば二次電池Ｂ１の消費電流が増大することなどで二次電池Ｂ１の正極端子２１の電池電圧が低下することを検出してもよい。すなわち、過放電検出しきい値Ｖｔｈｅは他の電圧低下を検出するためのしきい値であってもよい。 (Modified example)
In the embodiments described above, the overdischarge detection circuit 2 detects overdischarge of the secondary battery B1, but the present invention is not limited to this. It may also be detected that the battery voltage of the positive terminal 21 of the next battery B1 decreases. That is, the overdischarge detection threshold Vthe may be a threshold for detecting another voltage drop.
　以上の実施形態において、二次電池保護回路、二次電池保護装置及び電池パックについて説明したが、本発明はこれに限らず、二次電池保護回路の制御回路又は制御方法を構成してもいいし、ある実施形態において別の実施形態の一部又は全部を組み合わせるなど種々の変形を行ってもよい。 In the above embodiments, a secondary battery protection circuit, a secondary battery protection device, and a battery pack have been described, but the present invention is not limited to this, and a control circuit or control method of a secondary battery protection circuit may be configured. However, various modifications may be made, such as combining some or all of other embodiments in one embodiment.
　例えば、充電制御ＦＥＴ１４と、放電制御ＦＥＴ１５とは、それらの配置位置を互いに入れ替えて配置してもよい。 For example, the charging control FET 14 and the discharging control FET 15 may be arranged with their positions interchanged.
　以上の実施形態において、充電制御ＦＥＴ１４及び放電制御ＦＥＴ１５を用いているが、本発明はこれに限らず、それぞれ例えばバイポーラトランジスタ（ベースである制御端子を有する）などの別の種類のスイッチ素子を用いてもよい。 In the above embodiment, the charge control FET 14 and the discharge control FET 15 are used, but the present invention is not limited to this, and each uses a different type of switch element such as a bipolar transistor (having a control terminal that is a base). You can.
１　電圧検出回路
２　過放電検出回路
３　スイッチ回路
３Ａ　制御回路
４，５　スイッチ
６　昇圧回路
６Ａ，６Ｂ　制御回路
６ａ～６ｄ　スイッチ
７　駆動回路
８　クランプ回路
９　制御回路
１０，１１　ボディダイオード
１２　負極端子
１３　正極端子
１４　充電制御ＦＥＴ
１５　放電制御ＦＥＴ
１６，１６Ａ～１６Ｅ　二次電池保護回路
１７　電圧検出回路
２０，２０Ａ～２０Ｅ　二次電池保護装置
２１　正極端子
２２　負極端子
Ｂ１　二次電池
ＢＰ１～ＢＰ６　電池パック
Ｃ１　コンデンサ
ＣＨ１　充電器
ＲＬ　システム負荷 1 Voltage detection circuit 2 Over-discharge detection circuit 3 Switch circuit 3A Control circuit 4, 5 Switch 6 Boost circuit 6A, 6B Control circuit 6a to 6d Switch 7 Drive circuit 8 Clamp circuit 9 Control circuit 10, 11 Body diode 12 Negative terminal 13 Positive electrode Terminal 14 Charge control FET
15 Discharge control FET
16, 16A to 16E Secondary battery protection circuit 17 Voltage detection circuit 20, 20A to 20E Secondary battery protection device 21 Positive terminal 22 Negative terminal B1 Secondary battery BP1 to BP6 Battery pack C1 Capacitor CH1 Charger RL System load

Claims (8)

  1. 　二次電池の正極端子と、負荷及び充電器の高電位端子との間に挿入されかつ互いに直列に接続された充電制御スイッチ素子及び放電制御スイッチ素子を用いて、前記二次電池を保護する二次電池保護回路であって、
    　前記二次電池の電池電圧が所定の第１のしきい値未満であるか否かを検出する第１の電圧検出回路と、
    　前記第１のしきい値未満を検出したときに前記充電器の高電位電圧である出力電圧を出力する一方、前記第１のしきい値未満を検出しないときに前記電池電圧である出力電圧を出力するスイッチ回路と、
    　前記電池電圧を前記スイッチ回路の出力電圧を用いて昇圧させて出力する昇圧回路と、
    　前記第１のしきい値未満を検出したときに前記昇圧回路の出力電圧を前記充電制御スイッチ素子の制御端子のみに出力することで前記充電制御スイッチ素子のみをオンする一方、前記第１のしきい値未満を検出しないときに前記昇圧回路の出力電圧を前記充電制御スイッチ素子及び前記放電制御スイッチ素子の各制御端子に出力することで前記充電制御スイッチ素子及び前記放電制御スイッチ素子をともにオンするように制御する駆動回路と、
    を備える二次電池保護回路。     A secondary battery that protects the secondary battery using a charge control switch element and a discharge control switch element that are inserted between the positive terminal of the secondary battery and the high potential terminal of the load and charger and connected in series with each other. A second battery protection circuit,
    a first voltage detection circuit that detects whether the battery voltage of the secondary battery is less than a predetermined first threshold;
    An output voltage that is a high potential voltage of the charger is output when a voltage below the first threshold is detected, and an output voltage that is the battery voltage is output when a voltage below the first threshold is not detected. A switch circuit to output,
    a booster circuit that boosts and outputs the battery voltage using the output voltage of the switch circuit;
    By outputting the output voltage of the booster circuit only to the control terminal of the charge control switch element when a voltage lower than the first threshold is detected, only the charge control switch element is turned on; Both the charge control switch element and the discharge control switch element are turned on by outputting the output voltage of the booster circuit to each control terminal of the charge control switch element and the discharge control switch element when a voltage lower than a threshold is not detected. A drive circuit that controls the
    A secondary battery protection circuit with
  2. 　前記二次電池保護回路はさらに、
    　前記充電器の高電位端子の電圧が、前記昇圧回路の最低動作電圧よりも高い所定の第２のしきい値以上である前記昇圧回路の正常動作可能状態を検出する第２の電圧検出回路を備え、
    　前記第２の電圧検出回路は、前記昇圧回路の正常動作可能状態を検出したときは、前記昇圧回路を動作させる一方、前記第１のしきい値未満を検出しかつ前記昇圧回路の正常動作可能状態ではないことを検出したときは、前記昇圧回路の動作を停止させる、
    請求項１に記載の二次電池保護回路。     The secondary battery protection circuit further includes:
    a second voltage detection circuit that detects a normal operable state of the booster circuit in which the voltage at the high potential terminal of the charger is equal to or higher than a predetermined second threshold higher than the lowest operating voltage of the booster circuit; Prepare,
    The second voltage detection circuit operates the booster circuit when detecting that the booster circuit is capable of normal operation, and detects a voltage lower than the first threshold and enables the booster circuit to operate normally. When it is detected that the booster circuit is not in the above state, the operation of the booster circuit is stopped;
    The secondary battery protection circuit according to claim 1.
  3. 　前記二次電池保護回路はさらに、
    　前記充電器の高電位電圧を所定のクランプ電圧にクランプして、当該クランプ電圧を前記充電器の高電位電圧の代わりに前記スイッチ回路に出力するクランプ回路を備える、
    請求項１又は２に記載の二次電池保護回路。     The secondary battery protection circuit further includes:
    comprising a clamp circuit that clamps the high potential voltage of the charger to a predetermined clamp voltage and outputs the clamp voltage to the switch circuit instead of the high potential voltage of the charger;
    The secondary battery protection circuit according to claim 1 or 2.
  4. 　前記二次電池保護回路はさらに、
    　前記充電器の高電位電圧を所定のクランプ電圧にクランプして、当該クランプ電圧を前記充電器の高電位電圧の代わりに前記スイッチ回路及び前記第２の電圧検出回路に出力するクランプ回路を備える、
    請求項２に記載の二次電池保護回路。     The secondary battery protection circuit further includes:
    comprising a clamp circuit that clamps the high potential voltage of the charger to a predetermined clamp voltage and outputs the clamp voltage to the switch circuit and the second voltage detection circuit instead of the high potential voltage of the charger;
    The secondary battery protection circuit according to claim 2.
  5. 　前記二次電池保護回路はさらに、
    　前記充電器の高電位端子の電圧が、前記第２のしきい値よりも高い所定の第３のしきい値以上である高電圧を検出する第３の電圧検出回路を備え、
    　前記第３の電圧検出回路は、前記高電圧を検出したときは、前記昇圧回路の動作を停止させる、
    請求項２又は４に記載の二次電池保護回路。     The secondary battery protection circuit further includes:
    a third voltage detection circuit that detects a high voltage at which the voltage at the high potential terminal of the charger is equal to or higher than a predetermined third threshold higher than the second threshold;
    The third voltage detection circuit stops the operation of the booster circuit when detecting the high voltage.
    The secondary battery protection circuit according to claim 2 or 4.
  6. 　前記二次電池保護回路はさらに、
    　前記クランプ電圧が、前記第２のしきい値よりも高い所定の第３のしきい値以上である高電圧を検出する第３の電圧検出回路を備え、
    　前記第３の電圧検出回路は、前記高電圧を検出したときは、前記昇圧回路の動作を停止させる、
    請求項４に記載の二次電池保護回路。     The secondary battery protection circuit further includes:
    The clamp voltage includes a third voltage detection circuit that detects a high voltage that is equal to or higher than a predetermined third threshold that is higher than the second threshold;
    The third voltage detection circuit stops the operation of the booster circuit when detecting the high voltage.
    The secondary battery protection circuit according to claim 4.
  7. 　請求項１又は２に記載の二次電池保護回路と、
    　前記充電制御スイッチ素子と、
    　前記放電制御スイッチ素子と、
    を備える、
    二次電池保護装置。     A secondary battery protection circuit according to claim 1 or 2,
    the charging control switch element;
    the discharge control switch element;
    Equipped with
    Secondary battery protection device.
  8. 　請求項１又は２に記載の二次電池保護回路と、
    　前記二次電池と、
    　前記充電制御スイッチ素子と、
    　前記放電制御スイッチ素子と、
    を備える、
    電池パック。     A secondary battery protection circuit according to claim 1 or 2,
    The secondary battery;
    the charging control switch element;
    the discharge control switch element;
    Equipped with
    battery pack.
PCT/JP2022/028048 2022-07-19 2022-07-19 Secondary battery protection circuit, secondary battery protection device, and battery pack WO2024018522A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003143751A (en) * 2001-10-31 2003-05-16 Sanyo Electric Co Ltd Battery pack having protective circuit
JP6614388B1 (en) * 2019-05-31 2019-12-04 ミツミ電機株式会社 Secondary battery protection circuit, secondary battery protection device, battery pack, and control method of secondary battery protection circuit
JP2021158752A (en) * 2020-03-26 2021-10-07 エイブリック株式会社 Charge and discharge control device and battery device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003143751A (en) * 2001-10-31 2003-05-16 Sanyo Electric Co Ltd Battery pack having protective circuit
JP6614388B1 (en) * 2019-05-31 2019-12-04 ミツミ電機株式会社 Secondary battery protection circuit, secondary battery protection device, battery pack, and control method of secondary battery protection circuit
JP2021158752A (en) * 2020-03-26 2021-10-07 エイブリック株式会社 Charge and discharge control device and battery device

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