JPH0918308A - Power supply circuit - Google Patents

Abstract

PURPOSE: To provide a power supply circuit capable of preventing second power supply higher than first power supply from being continuously supplied to a part to be controlled by turning off a transistor even when the clock signals of a control part are stopped and held at a prescribed level. CONSTITUTION: When the clock signals (a) of a microcomputer 1 are held at a high level due to program runaway or the like and the other terminal of a capacitor 9 is kept grounded, the capacitor 9 is charged from the power supply VDD2 higher than the power supply VDD1 through a resistor 5. Then, by boosting the voltage of one terminal of the capacitor 9, a P channel type MOS transistor 4 connected between the power supply VDD2 and the power supply input of a peripheral circuit 3 such as a charging device or the like is turned off and the power supply to the peripheral circuit 3 is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit suitable for being provided in a circuit for supplying a predetermined circuit in a switched state of a power supply.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a conventional power supply circuit. In FIG. 3, (1) is a microcomputer, which is connected between a power supply VDD1 (5 volts) and ground to operate, and has a built-in clock generator (not shown).
To generate a clock signal of a predetermined frequency. Reference numeral (2) in the microcomputer (1) is a buffer, and a P-channel type MOS is provided between the power supply VDD1 and the ground.
It is configured by connecting a transistor and an N-channel type MOS transistor in a predetermined manner. That is, a clock signal having an amplitude of 5 volts is obtained from the buffer (2). The clock signal is a microcomputer (1)
Output to the outside.

(3) is a power supply V that is larger than the power supply VDD1
It is a peripheral circuit which operates when DD2 (20 V) is intermittently switched and supplied. The peripheral circuit (3) is, for example, a switching regulator type charging circuit, and has a configuration for fully charging the secondary battery in a short time. The intermittent supply of the power supply VDD2 to the peripheral circuit (3) means that a large current can be supplied to the peripheral circuit (3) during the intermittent supply time of the power supply VDD2, that is, the charging circuit is It has the advantage that it can be fully charged in a short time. It is the P-channel type MOS transistor (4) that realizes this intermittent switching, and the source and drain paths are the power supply VDD2.
And the input of the peripheral circuit (3). The resistor (5) is connected between the gate and the source of the P-channel MOS transistor (4).

Reference numeral (6) is an NPN bipolar transistor, the base of which is connected to the output of the buffer (2) inside the microcomputer (1) through the resistor (7) and the emitter of which is grounded. Reference numeral (8) is a Zener diode, the cathode of which is connected to the gate of the P-channel MOS transistor (4) and the anode of which is connected to the collector of the NPN bipolar transistor (6). When the Zener diode (8) is conducting, for example, 1
It shall have a terminal voltage of 2.5 volts. here,
The reason why the transistor (6) is bipolar is that it has a sufficient breakdown voltage when a current flows from the high power supply VDD2 through the resistor (5) and the Zener diode (8).

In FIG. 3, when the clock signal is at a high level (5 volts), the NPN bipolar transistor (6) is turned on and the cathode of the zener diode (8) receives 12.5 volts. Then, between the gate and the source of the P-channel type MOS transistor (4), 7.
The voltage becomes 5 volts, the P-channel MOS transistor (4) is turned on, and the current determined by the voltage across the Zener diode (8) is supplied to the peripheral circuit (3). On the other hand, when the clock signal is low level (0 volt), the NPN bipolar transistor (6) is turned off, and at this time, the power source V
DD2 is applied to the gate of the P-channel type MOS transistor (4) through the resistor (5) to turn off the P-channel type MOS transistor (4), and supply of the power supply VDD2 to the peripheral circuit (3), that is, the above current. Supply is prohibited. In this way, by supplying a large current to the peripheral circuit (3) intermittently, if the peripheral circuit (3) is a charging circuit, efficient charging with less energy loss can be realized.

[0006]

However, in the state in which the P-channel type MOS transistor (4) is switched in synchronization with the clock signal to intermittently supply the current to the peripheral circuit (3), the NPN is used. When the clock signal is stopped for some reason such as program runaway of the microcomputer (1) while the type bipolar transistor (6) is on, that is, the clock signal is held at the high level, the P channel Type M
The OS transistor (4) will continue to turn on. This means that a large current constantly flows into the peripheral circuit (3), and the peripheral circuit (3) is overheated and heated, which causes a problem such as destruction of the peripheral circuit (3). It was

Therefore, according to the present invention, even when the clock signal of the control unit is stopped and held at a predetermined level, the transistor is turned off and the second power supply higher than the first power supply is continuously supplied to the controlled unit. It is an object of the present invention to provide a power supply circuit that can prevent such a situation.

[0008]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it is synchronized with a clock signal of a control unit operated by a first power supply. A power supply circuit for switching a second power supply higher than the first power supply and supplying the second power supply to the controlled unit,
A transistor having an input / output electrode connected between a power supply and a power input of the controlled unit, a resistor connected between the input electrode and the control electrode of the transistor, and one end connected to the input electrode of the transistor And a constant voltage generator connected to the second power source to generate a predetermined constant voltage and having a constant voltage output connected to the other end of the capacitor.
Means for setting the other end of the capacitor to the grounded or released state according to two different levels of high or low of the clock signal.

[0009]

According to the present invention, when the clock signal of the control unit is stopped and the other end of the capacitor continues to be grounded, the capacitor is charged from the second power supply higher than the first power supply through the resistor and one end of the capacitor is charged. By increasing the voltage of
The transistor connected between the second power source and the input of the controlled unit is turned off to stop the power supply to the controlled unit.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. In FIG. 1, the same elements and configurations as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 1, the microcomputer (1) corresponds to the control unit according to the present invention, and the peripheral circuit (3) such as a charging circuit corresponds to the controlled unit according to the present invention. Now, (9) is a capacitor, which is connected between the gate of the P-channel type MOS transistor (4) and the collector of the NPN type bipolar transistor (6). (10) and (11) are power supply VDD
A resistor and a Zener diode connected in series between 2 and ground. The cathode of the Zener diode (11) is also connected to the collector of the NPN bipolar transistor (6). Here, in this embodiment, the power source VDD2 is supplied via the P-channel type MOS transistor (4).
When the current is supplied to the peripheral circuit (3) by connecting it to the input of the peripheral circuit (3), the Zener diode (11) is provided so that the current having the same magnitude as that of the conventional circuit of FIG. 3 can be supplied.
Shall have a voltage of 7.5 V at both ends when conducting. Further, the transistor (6) for switching according to the clock signal is provided outside the microcomputer (1).
If a transistor capable of withstanding the withstand voltage of the power supply VDD2 can be integrated, the transistor (6) need not be externally attached.

The operation of FIG. 1 will be described below with reference to the time chart of FIG. First, when the clock signal a is at low level (0 volt), the NPN bipolar transistor (6) is turned off, and the voltage b at one end of the capacitor (9) connected to the collector of the NPN bipolar transistor (6) is Zener diode conducting (11)
The voltage at both ends of the voltage is 7.5 volts. At this time, a current flows from the power supply VDD2 to the other end of the capacitor (9) through the resistor (5), and the voltage c at the other end of the capacitor (9) becomes 20 volts. Therefore, the P-channel type MOS transistor (4) is turned off, the power supply VDD2 is disconnected from the peripheral circuit (3), and no current is supplied to the peripheral circuit (3). After that, when the clock signal a becomes high level (5 volts), the NPN bipolar transistor (6) is turned on. Then, the Zener diode (11) is turned off because its cathode is grounded,
Further, at one end of the capacitor (9), the impedance when the NPN bipolar transistor (6) is turned on is the resistance (1
Since it is smaller than the resistance value of 0), it is grounded. That is, since the voltage b at one end of the capacitor (9) shifts from 7.5 V to 0 V, the voltage c at the other end of the capacitor (9) also shifts from 20 V to 7.5 V, which is 12.5 V. . As a result, the potential difference between the gate and the source of the P-channel type MOS transistor (4) is opened, and the P-channel type MOS transistor (4) is turned on.
As a result, the power supply VDD2 is connected to the peripheral circuit (3) and current is supplied to the peripheral circuit (3). As described above, the P channel type MO is synchronized with the clock signal a.
By switching the S-transistor (4),
The power supply VDD2 is intermittently connected to the peripheral circuit (3), and a relatively large current can be intermittently supplied to the peripheral circuit (3). If the peripheral circuit (3) is, for example, a secondary battery charging circuit, efficient charging with less energy loss can be realized.

By the way, from the state where the clock signal a is normally generated by alternately repeating the high level and the low level as described above, at time T, when the clock signal a is in the high level state, the microcomputer (1 ), An abnormal situation such as a program runaway occurs, and the clock signal a
Is held at a high level, at time T, the voltage c at the other end of the capacitor (9) is 1
Although it remains at 2.5 V, a current then flows from the power supply VDD2 to the capacitor (9) through the resistor (5) according to the time constant determined by the resistance value of the resistor (5) and the capacitance of the capacitor (9). Then, the voltage c at the other end of the capacitor (9) gradually rises, and finally rises from 12.5 volts to 20 volts. In the process of increasing the voltage c, the gate voltage of the P-channel type MOS transistor (4) is the P-channel type M transistor.
The power supply VDD2 and the peripheral circuit (3) are cut off at the time (time T ') when the voltage has risen to a voltage at which the OS transistor (4) can be turned off.

From the above, even if the clock signal a of the microcomputer (1) is held at a high level for some reason, the P-channel type MOS which has been kept on by the charging action of the capacitor (9) is kept on.
The transistor (4) can be turned off and the power supply VDD
2 and the peripheral circuit (3) can be prevented from being continuously connected. For example, when the peripheral circuit (3) is intermittently connected to the power supply VDD2 for the purpose of efficiently fully charging the secondary battery with less energy loss, the peripheral circuit (3) and the power supply VDD2 are connected to each other. Since it is possible to prevent the continuous connection of the peripheral circuit (3), it is possible to prevent a large current from continuously flowing into the peripheral circuit (3). The destruction of (3) can be prevented.

[0014]

According to the present invention, even if the clock signal of the control unit is stopped due to some cause, it is kept on due to the charging action of the capacitor.
The transistor between the power supply and the controlled unit can be turned off, and the second power supply and the controlled unit can be prevented from being continuously connected. For example, in the case where the controlled unit is a charger that is intermittently connected to the second power source and can intermittently supply a large current, and that is a charger that fully charges the secondary battery efficiently with less energy loss, Since it is possible to prevent continuous connection between the controlled unit and the second power source, it is possible to prevent a large current from continuously flowing into the controlled unit, that is, it is possible to protect the controlled unit from heating due to overcurrent. As a result, it is possible to prevent the controlled portion from being destroyed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a power supply circuit of the present invention.

FIG. 2 is a waveform chart showing the operation of FIG.

FIG. 3 is a diagram showing a conventional power supply circuit.

[Explanation of symbols]

 (1) Microcomputer (3) Peripheral circuit (4) P-channel MOS transistor (5) Resistor (6) NPN bipolar transistor (9) Capacitor (11) Zener diode

Claims (2)

[Claims] 1. A power supply circuit for switching a second power supply, which is higher than the first power supply, and supplying the power to a controlled unit in synchronization with a clock signal of a control unit that operates on a first power supply, A transistor having an input / output electrode connected between a power source and a power input of the controlled part, a resistor connected between the input electrode and the control electrode of the transistor, and one end of which is connected to the input electrode of the transistor. A capacitor, a constant voltage generator connected to the second power source to generate a predetermined constant voltage, and a constant voltage output connected to the other end of the capacitor, and two different high or low clock signals. Means for setting the other end of the capacitor to a grounded or released state according to the level, the second power supply when the clock signal of the control unit stops and the other end of the capacitor continues to be grounded. The power supply circuit is characterized in that the transistor is turned off and the power supply to the controlled unit is stopped by charging the capacitor through the resistor and increasing the voltage at one end of the capacitor. 2. The means according to claim 1, wherein the means is a switching transistor to which the clock signal is applied to a control electrode and an input / output electrode is connected between the other end of the capacitor and the ground. Power supply circuit.