JP2021158752A - Charge and discharge control device and battery device - Google Patents

Charge and discharge control device and battery device Download PDF

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JP2021158752A
JP2021158752A JP2020055620A JP2020055620A JP2021158752A JP 2021158752 A JP2021158752 A JP 2021158752A JP 2020055620 A JP2020055620 A JP 2020055620A JP 2020055620 A JP2020055620 A JP 2020055620A JP 2021158752 A JP2021158752 A JP 2021158752A
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JP7345416B2 (en
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貴士 小野
Takashi Ono
貴士 小野
亮一 安斎
Ryoichi Anzai
亮一 安斎
康博 上島
Yasuhiro Ueshima
康博 上島
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Ablic Inc
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02E60/10—Energy storage using batteries

Abstract

To provide a charge and discharge control device and a battery device with less consumption current while comprising functions capable of charging a secondary battery 3 at low voltage.SOLUTION: A charge and discharge control device comprises: a control circuit which controls charge and discharge of a secondary battery by receiving an over discharge detection signal; a charge pump; a voltage detection circuit which has a first resistor between a power supply terminal and a ground terminal, detects that voltage of an input terminal becomes higher than voltage of the power supply terminal when the over discharge detection signal is input, and applies current to the first resistor only during detection; a first switch which is provided between the charge pump and a charge control terminal, and is controlled by the control circuit and the voltage detection circuit; a second switch which is provided between the power supply terminal and the charge control terminal, and is controlled by the control circuit and the voltage detection circuit; and a third switch which is provided between the input terminal and the charge control terminal, and is controlled by the control circuit and the voltage detection circuit.SELECTED DRAWING: Figure 1

Description

本発明は、充放電制御装置及びバッテリ装置に関する。 The present invention relates to a charge / discharge control device and a battery device.

図５は、従来のバッテリ装置を示す回路図である。
従来のバッテリ装置は、充電制御ＦＥＴ１と、放電制御ＦＥＴ２と、二次電池３と、充放電制御装置５０を備え、充電器４からの充電や負荷５への放電を制御している。充放電制御装置５０は、電圧検出回路５１と、チャージポンプ５２と、低電圧検出回路５３と、制御回路５４と、駆動回路５５と、スイッチ５８と、ＮＭＯＳトランジスタ５９と、電源端子ＶＤＤ、接地端子ＶＳＳ、出力端子ＣＯ及びＤＯ、入力端子ＶＭを備えている。 FIG. 5 is a circuit diagram showing a conventional battery device.
The conventional battery device includes a charge control FET 1, a discharge control FET 2, a secondary battery 3, and a charge / discharge control device 50, and controls charging from the charger 4 and discharging to the load 5. The charge / discharge control device 50 includes a voltage detection circuit 51, a charge pump 52, a low voltage detection circuit 53, a control circuit 54, a drive circuit 55, a switch 58, an NMOS transistor 59, a power supply terminal VDD, and a ground terminal. It is equipped with a VSS, output terminals CO and DO, and an input terminal VM.

以上のように構成されたバッテリ装置は、二次電池３の電圧が低電圧検出回路５３の検出電圧よりも低い場合、駆動回路５５の遮断回路５６がオフ、ＮＭＯＳトランジスタ５９がオンしてスイッチ５８がオンするため、充電制御ＦＥＴ１のゲート電圧は充電器４の電圧が印加されている入力端子ＶＭの電圧となる。従って、二次電池３の電圧が低い場合であっても、充電制御ＦＥＴ１がオンすることが出来るので、二次電池３に充電することができる（例えば、特許文献１参照）。 In the battery device configured as described above, when the voltage of the secondary battery 3 is lower than the detection voltage of the low voltage detection circuit 53, the cutoff circuit 56 of the drive circuit 55 is turned off, the NMOS transistor 59 is turned on, and the switch 58 is turned on. Is turned on, so that the gate voltage of the charge control FET 1 becomes the voltage of the input terminal VM to which the voltage of the charger 4 is applied. Therefore, even when the voltage of the secondary battery 3 is low, the charge control FET 1 can be turned on, so that the secondary battery 3 can be charged (see, for example, Patent Document 1).

特許第６６１４３８８号公報Japanese Patent No. 6614388

しかしながら、従来のバッテリ装置の低電圧検出回路５３は、図６に示すように、ゲートが電源端子ＶＤＤに接続されたＮＭＯＳトランジスタ５３１と抵抗５３２を入力端子ＶＭと接地端子ＶＳＳの間に直列接続した回路構成（特許文献１図５）のため、電源電圧ＶＤＤが高い通常状態において、入力端子ＶＭと接地端子ＶＳＳの間に常時電流が流れることになる。 However, in the low voltage detection circuit 53 of the conventional battery device, as shown in FIG. 6, the NMOS transistor 531 whose gate is connected to the power supply terminal VDD and the resistor 532 are connected in series between the input terminal VM and the ground terminal VSS. Due to the circuit configuration (Patent Document 1, FIG. 5), a current always flows between the input terminal VM and the ground terminal VSS in a normal state where the power supply voltage VDD is high.

本発明は上記課題に顧みてなされたもので、電圧が低い二次電池３に充電可能な機能を備えながら、消費電流が少ない充放電制御装置及びバッテリ装置を提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a charge / discharge control device and a battery device that consume a small amount of current while having a function of charging a secondary battery 3 having a low voltage.

上記課題を解決するために、本発明の充放電制御装置は、二次電池の正極端子が接続される電源端子と、前記二次電池の負極端子が接続される接地端子と、充電制御ＦＥＴのゲートと接続される充電制御端子と、正極外部端子と接続される入力端子と、前記二次電池の過放電を検出する過放電検出回路と、前記過放電検出回路の過放電検出信号を受けて前記二次電池の充放電を制御する制御回路と、前記制御回路によって制御されるチャージポンプと、前記過放電検出回路の過放電検出信号が入力されているときに、前記入力端子の電圧が前記電源端子の電圧より高くなったことを検出する電圧検出回路と、前記チャージポンプと充電制御端子の間に設けられ、前記制御回路及び前記電圧検出回路によって制御される第一のスイッチと、前記電源端子と前記充電制御端子の間に設けられ、前記制御回路及び前記電圧検出回路によって制御される第二のスイッチと、前記入力端子と前記充電制御端子の間に設けられ、前記制御回路及び前記電圧検出回路によって制御される第三のスイッチと、を備え、電圧検出回路は、電源端子と接地端子の間の第一の抵抗を有し、入力端子の電圧が電源端子の電圧より高くなったことを検出している間のみ第一の抵抗に電流を流すことを特徴とする。
また、本発明のバッテリ装置は、上記充放電制御装置を備えることを特徴とする。 In order to solve the above problems, the charge / discharge control device of the present invention includes a power supply terminal to which the positive terminal of the secondary battery is connected, a ground terminal to which the negative terminal of the secondary battery is connected, and a charge control FET. The charge control terminal connected to the gate, the input terminal connected to the positive electrode external terminal, the overdischarge detection circuit for detecting the overdischarge of the secondary battery, and the overdischarge detection signal of the overdischarge detection circuit are received. When the over-discharge detection signal of the control circuit that controls the charge / discharge of the secondary battery, the charge pump controlled by the control circuit, and the over-discharge detection circuit is input, the voltage of the input terminal is the voltage of the input terminal. A voltage detection circuit that detects that the voltage is higher than the voltage of the power supply terminal, a first switch provided between the charge pump and the charge control terminal and controlled by the control circuit and the voltage detection circuit, and the power supply. A second switch provided between the terminal and the charge control terminal and controlled by the control circuit and the voltage detection circuit, and provided between the input terminal and the charge control terminal, the control circuit and the voltage With a third switch controlled by the detection circuit, the voltage detection circuit had the first resistance between the power supply terminal and the ground terminal, and the voltage of the input terminal became higher than the voltage of the power supply terminal. It is characterized in that a current is passed through the first resistor only while the voltage is detected.
Further, the battery device of the present invention is characterized by including the charge / discharge control device.

本発明の充放電制御装置及びバッテリ装置によれば、電圧が低い二次電池３に充電可能な機能を備えながら、消費電流が少ない充放電制御装置及びバッテリ装置を提供することが出来る。 According to the charge / discharge control device and the battery device of the present invention, it is possible to provide the charge / discharge control device and the battery device that consume less current while having a function of charging the secondary battery 3 having a low voltage.

本発明のバッテリ装置の一実施形態を示す回路図である。It is a circuit diagram which shows one Embodiment of the battery device of this invention. 本実施形態の電圧検出回路の一例を示す回路図である。It is a circuit diagram which shows an example of the voltage detection circuit of this embodiment. 本実施形態の電圧検出回路の他の例を示す回路図である。It is a circuit diagram which shows another example of the voltage detection circuit of this embodiment. 従来のバッテリ装置を示す回路図である。It is a circuit diagram which shows the conventional battery device. 従来のバッテリ装置の低電圧検出回路を示す回路図である。It is a circuit diagram which shows the low voltage detection circuit of the conventional battery apparatus.

図１は、本発明の実施形態のバッテリ装置を示す回路図である。
本実施形態のバッテリ装置は、充電制御ＦＥＴ１と、放電制御ＦＥＴ２と、二次電池３と、充放電制御装置１０を備え、正極外部端子と負極外部端子の間に接続される充電器４からの充電や負荷５への放電を制御している。 FIG. 1 is a circuit diagram showing a battery device according to an embodiment of the present invention.
The battery device of the present embodiment includes a charge control FET 1, a discharge control FET 2, a secondary battery 3, and a charge / discharge control device 10, and is connected from a charger 4 connected between a positive electrode external terminal and a negative electrode external terminal. It controls charging and discharging to the load 5.

充放電制御装置１０は、過放電検出回路１１と、過充電検出回路１２と、制御回路１３と、チャージポンプ１４及び１５と、ＶＭ−ＶＤＤ間の電圧を検出する電圧検出回路１６と、スイッチ２１、２２、２３、２４、２５と、ＮＭＯＳトランジスタ２６と、電源端子ＶＤＤ、接地端子ＶＳＳ、出力端子ＣＯ（充電制御端子）及びＤＯ（放電制御端子）、入力端子ＶＭを備えている。 The charge / discharge control device 10 includes an over-discharge detection circuit 11, an over-charge detection circuit 12, a control circuit 13, charge pumps 14 and 15, a voltage detection circuit 16 that detects a voltage between VM and VDD, and a switch 21. , 22, 23, 24, 25, an NMOS transistor 26, a power supply terminal VDD, a ground terminal VSS, an output terminal CO (charge control terminal) and a DO (discharge control terminal), and an input terminal VM.

電源端子ＶＤＤは、二次電池３の正極端子と接続されている。接地端子ＶＳＳは、二次電池３の負極端子と接続されている。出力端子ＣＯは、充電制御ＦＥＴ１のゲートと接続されている。出力端子ＤＯは、放電制御ＦＥＴ２のゲートと接続されている。入力端子ＶＭは、正極外部端子と接続されている。 The power supply terminal VDD is connected to the positive electrode terminal of the secondary battery 3. The ground terminal VSS is connected to the negative electrode terminal of the secondary battery 3. The output terminal CO is connected to the gate of the charge control FET 1. The output terminal DO is connected to the gate of the discharge control FET 2. The input terminal VM is connected to the positive electrode external terminal.

過放電検出回路１１は、入力端子が電源端子ＶＤＤと接続され、出力端子が制御回路１３の第一入力端子と接続されている。過充電検出回路１２は、入力端子が電源端子ＶＤＤと接続され、出力端子が制御回路１３の第二入力端子と接続されている。制御回路１３は、第一出力端子がチャージポンプ１４の入力端子と接続され、第二出力端子がチャージポンプ１５の入力端子と接続され、第三〜七出力端子が夫々スイッチ２１、２２、２３、２４、２５の制御端子と接続されている。 In the over-discharge detection circuit 11, the input terminal is connected to the power supply terminal VDD, and the output terminal is connected to the first input terminal of the control circuit 13. In the overcharge detection circuit 12, the input terminal is connected to the power supply terminal VDD, and the output terminal is connected to the second input terminal of the control circuit 13. In the control circuit 13, the first output terminal is connected to the input terminal of the charge pump 14, the second output terminal is connected to the input terminal of the charge pump 15, and the third to seventh output terminals are switches 21, 22, 23, respectively. It is connected to the control terminals 24 and 25.

チャージポンプ１４の出力端子は、スイッチ２３を介して出力端子ＣＯと接続されている。チャージポンプ１５の出力端子は、スイッチ２４を介して出力端子ＤＯと接続されている。スイッチ２１は、入力端子ＶＭと出力端子ＣＯの間に接続されている。スイッチ２２は、電源端子ＶＤＤと出力端子ＣＯの間に接続されている。スイッチ２５は、入力端子ＶＭと出力端子ＤＯの間に接続されている。 The output terminal of the charge pump 14 is connected to the output terminal CO via a switch 23. The output terminal of the charge pump 15 is connected to the output terminal DO via a switch 24. The switch 21 is connected between the input terminal VM and the output terminal CO. The switch 22 is connected between the power supply terminal VDD and the output terminal CO. The switch 25 is connected between the input terminal VM and the output terminal DO.

電圧検出回路１６は、第一入力端子が電源端子ＶＤＤと接続され、第二入力端子が入力端子ＶＭと接続され、第三入力端子が過放電検出回路１１の出力端子と接続され、出力端子がスイッチ２２、２３の制御端子及びＮＭＯＳトランジスタ２６のゲートと接続されている。ＮＭＯＳトランジスタ２６は、ソースが接地端子ＶＳＳと接続され、ドレインがスイッチ２１の制御端子と接続されている。 In the voltage detection circuit 16, the first input terminal is connected to the power supply terminal VDD, the second input terminal is connected to the input terminal VM, the third input terminal is connected to the output terminal of the overdischarge detection circuit 11, and the output terminal is It is connected to the control terminals of switches 22 and 23 and the gate of the NMOS transistor 26. The source of the NMOS transistor 26 is connected to the ground terminal VSS, and the drain is connected to the control terminal of the switch 21.

以下に、上述のように構成した本実施形態のバッテリ装置の動作について説明する。
二次電池３の電圧が過放電検出電圧と過充電検出電圧の間にある通常状態のときは、スイッチ２１、２２、２５がオフし、スイッチ２３、２４がオンしている。そして、ＣＯ端子から充電制御ＦＥＴ１をオンするチャージポンプ１４の出力信号が出力され、ＤＯ端子から放電制御ＦＥＴ２をオンするチャージポンプ１５の出力信号が出力されている。 The operation of the battery device of the present embodiment configured as described above will be described below.
In the normal state where the voltage of the secondary battery 3 is between the over-discharge detection voltage and the over-charge detection voltage, the switches 21, 22 and 25 are off and the switches 23 and 24 are on. Then, the output signal of the charge pump 14 that turns on the charge control FET 1 is output from the CO terminal, and the output signal of the charge pump 15 that turns on the discharge control FET 2 is output from the DO terminal.

過充電検出回路１２は、二次電池３の過充電を検出すると、過充電検出信号ＶＤＨを出力する。制御回路１３は、過充電検出信号ＶＤＨを受けると、スイッチ２３をオフし、スイッチ２２をオンする。即ち、制御回路１３は、出力端子ＣＯから充電制御ＦＥＴ１をオフする電源端子ＶＤＤの電圧を出力し、二次電池３への充電を禁止する。 When the overcharge detection circuit 12 detects the overcharge of the secondary battery 3, it outputs the overcharge detection signal VDH. When the control circuit 13 receives the overcharge detection signal VDH, the control circuit 13 turns off the switch 23 and turns on the switch 22. That is, the control circuit 13 outputs the voltage of the power supply terminal VDD that turns off the charge control FET 1 from the output terminal CO, and prohibits charging of the secondary battery 3.

過放電検出回路１１は、二次電池３の過放電を検出すると、過放電検出信号ＶＤＬを出力する。制御回路１３は、過放電検出信号ＶＤＬを受けると、チャージポンプ１４、１５とスイッチ２３、２４をオフし、スイッチ２１、２５をオンする。即ち、制御回路１３は、出力端子ＣＯから入力端子ＶＭの電圧を出力し、出力端子ＤＯから放電制御ＦＥＴ２をオフする入力端子ＶＭの電圧を出力し、二次電池３からの放電を禁止する。 When the over-discharge detection circuit 11 detects the over-discharge of the secondary battery 3, it outputs an over-discharge detection signal VDC. Upon receiving the over-discharge detection signal VDC, the control circuit 13 turns off the charge pumps 14 and 15 and the switches 23 and 24, and turns on the switches 21 and 25. That is, the control circuit 13 outputs the voltage of the input terminal VM from the output terminal CO, outputs the voltage of the input terminal VM that turns off the discharge control FET 2 from the output terminal DO, and prohibits the discharge from the secondary battery 3.

電圧検出回路１６は、過放電検出信号ＶＤＬが入力されているときに充電器が接続されて入力端子ＶＭの電圧が電源端子ＶＤＤよりも高くなったことを検出すると、検出信号ＶＤを出力する。 When the voltage detection circuit 16 detects that the charger is connected and the voltage of the input terminal VM becomes higher than that of the power supply terminal VDD when the over-discharge detection signal VDL is input, the voltage detection circuit 16 outputs the detection signal VD.

以上のように構成された本実施形態のバッテリ装置は、二次電池３が充電制御ＦＥＴ１をオンすることができない過放電状態において、充電器４が接続されたとき以下のように二次電池３を充電する。 In the battery device of the present embodiment configured as described above, when the charger 4 is connected in an over-discharged state in which the secondary battery 3 cannot turn on the charge control FET 1, the secondary battery 3 is as follows. To charge.

二次電池３が過放電状態のため、過放電検出回路１１は、過放電検出信号ＶＤＬを出力する。電圧検出回路１６は、過放電検出信号ＶＤＬが入力されているため、充電器４が接続されて、入力端子ＶＭの電圧が電源端子ＶＤＤよりも高くなると、検出信号ＶＤを出力する。スイッチ２２、２３は、検出信号ＶＤを受けてオフする。ＮＭＯＳトランジスタ２６はゲートに検出信号ＶＤを受けるとオンするため、スイッチ２１はオンする。従って、充電制御ＦＥＴ１は、ゲートに入力端子ＶＭの電圧が印加されるためオンする。これにより、二次電池３は、充電器４より放電制御ＦＥＴ２のボディダイオードを経由して充電電流が供給される。
このとき、充電制御ＦＥＴ１のソース端子から放電制御ＦＥＴ２のソース端子に発生する電圧は、充電制御ＦＥＴ１の閾値電圧、充電制御ＦＥＴ１のソース―ドレイン飽和電圧と放電制御ＦＥＴ２のボディダイオードの順方向電圧の合計値のいずれか大きい方で決定される。 Since the secondary battery 3 is in the over-discharged state, the over-discharge detection circuit 11 outputs the over-discharge detection signal VDL. Since the over-discharge detection signal VDL is input to the voltage detection circuit 16, the detection signal VD is output when the charger 4 is connected and the voltage of the input terminal VM becomes higher than that of the power supply terminal VDD. The switches 22 and 23 are turned off in response to the detection signal VD. Since the NMOS transistor 26 turns on when the gate receives the detection signal VD, the switch 21 turns on. Therefore, the charge control FET 1 is turned on because the voltage of the input terminal VM is applied to the gate. As a result, the secondary battery 3 is supplied with a charging current from the charger 4 via the body diode of the discharge control FET 2.
At this time, the voltage generated from the source terminal of the charge control FET 1 to the source terminal of the discharge control FET 2 is the threshold voltage of the charge control FET 1, the source-drain saturation voltage of the charge control FET 1, and the forward voltage of the body diode of the discharge control FET 2. It is determined by the larger of the total values.

二次電池３が充電されてその電圧が過放電検出電圧を超えると、過放電検出回路１１は、過放電検出信号ＶＤＬを停止する。制御回路１３は、チャージポンプ１４、１５とスイッチ２３、２４をオンし、スイッチ２１、２２、２５をオフする。また、電圧検出回路１６は、過放電検出信号ＶＤＬが入力されないため、検出信号ＶＤを停止し、ＮＭＯＳトランジスタ２６をオフする。即ち、バッテリ装置は通常状態になる。 When the secondary battery 3 is charged and its voltage exceeds the over-discharge detection voltage, the over-discharge detection circuit 11 stops the over-discharge detection signal VDC. The control circuit 13 turns on the charge pumps 14 and 15 and the switches 23 and 24, and turns off the switches 21, 22 and 25. Further, since the over-discharge detection signal VDL is not input to the voltage detection circuit 16, the detection signal VD is stopped and the NMOS transistor 26 is turned off. That is, the battery device is in the normal state.

図２は、本実施形態のバッテリ装置の電圧検出回路の一例を示す回路図である。
図２の電圧検出回路１６は、ＮＯＴ回路１６０と、ＰＭＯＳトランジスタ１６１と、ＮＭＯＳトランジスタ１６２及び１６３と、抵抗１６４及び１６５と、を備えている。 FIG. 2 is a circuit diagram showing an example of a voltage detection circuit of the battery device of the present embodiment.
The voltage detection circuit 16 of FIG. 2 includes a NOT circuit 160, a NMOS transistor 161, an NMOS transistors 162 and 163, and resistors 164 and 165.

ＮＯＴ回路１６０は、入力が電圧検出回路１６の第三入力端子に接続され、出力がＮＭＯＳトランジスタ１６３のゲートに接続されている。ＮＭＯＳトランジスタ１６３は、ソースが接地端子ＶＳＳに接続され、ドレインが電圧検出回路１６の出力端子に接続されている。ＰＭＯＳトランジスタ１６１は、ソースが電圧検出回路１６の第二入力端子に接続され、ドレインが抵抗１６５を介して出力端子に接続されている。ＮＭＯＳトランジスタ１６２は、ソースが接地端子ＶＳＳに接続され、ドレインが抵抗１６４を介して電圧検出回路１６の第一入力端子に接続されている。 In the NOT circuit 160, the input is connected to the third input terminal of the voltage detection circuit 16, and the output is connected to the gate of the NMOS transistor 163. The source of the NMOS transistor 163 is connected to the ground terminal VSS, and the drain is connected to the output terminal of the voltage detection circuit 16. The source of the epitaxial transistor 161 is connected to the second input terminal of the voltage detection circuit 16, and the drain is connected to the output terminal via the resistor 165. The source of the NMOS transistor 162 is connected to the ground terminal VSS, and the drain is connected to the first input terminal of the voltage detection circuit 16 via the resistor 164.

次に、図２の電圧検出回路１６の動作について説明する。
過放電検出信号ＶＤＬが停止している通常状態では、ＮＯＴ回路１６０にロウレベルが入力されているので、ＮＭＯＳトランジスタ１６３はオンして、出力端子にロウレベルが出力されている。このとき、ＮＭＯＳトランジスタ１６２、ＰＭＯＳトランジスタ１６１がオフしているので、抵抗１６４及び１６５には電流が流れない。 Next, the operation of the voltage detection circuit 16 of FIG. 2 will be described.
Since the low level is input to the NOT circuit 160 in the normal state in which the over-discharge detection signal VDC is stopped, the NMOS transistor 163 is turned on and the low level is output to the output terminal. At this time, since the NMOS transistor 162 and the NMOS transistor 161 are turned off, no current flows through the resistors 164 and 165.

過放電状態になり過放電検出信号ＶＤＬが入力されると、ＮＯＴ回路１６０はロウレベルを出力するので、ＮＭＯＳトランジスタ１６３はオフする。このときも同様に、抵抗１６４及び１６５には電流が流れない。ここで、充電器４が接続されると、入力端子ＶＭの電圧が電源端子ＶＤＤの電圧より高くなるので、ＰＭＯＳトランジスタ１６１はオンする。従って、出力端子にハイレベルの検出信号ＶＤが出力される。 When the over-discharge state is entered and the over-discharge detection signal VDC is input, the NOT circuit 160 outputs a low level, so that the NMOS transistor 163 is turned off. Similarly, at this time, no current flows through the resistors 164 and 165. Here, when the charger 4 is connected, the voltage of the input terminal VM becomes higher than the voltage of the power supply terminal VDD, so that the epitaxial transistor 161 is turned on. Therefore, a high-level detection signal VD is output to the output terminal.

図３は、本実施形態のバッテリ装置の電圧検出回路の他の例を示す回路図である。
図３の電圧検出回路１６は、図２のＮＯＴ回路１６０に替えて、抵抗１６６及び１６７とスイッチ１６８とＮＭＯＳトランジスタ１６９を備えている。 FIG. 3 is a circuit diagram showing another example of the voltage detection circuit of the battery device of the present embodiment.
The voltage detection circuit 16 of FIG. 3 includes resistors 166 and 167, a switch 168, and an NMOS transistor 169 in place of the NOT circuit 160 of FIG.

ＮＭＯＳトランジスタ１６９は、ソースが接地端子ＶＳＳに接続され、ドレインが抵抗１６６の一方の端子に接続され、ゲートがＰＭＯＳトランジスタ１６１のドレインに接続されている。抵抗１６６の他方の端子は、スイッチ１６８の一方の端子とＮＭＯＳトランジスタ１６３のゲートに接続されている。スイッチ１６８は、制御端子が電圧検出回路１６の第三入力端子に接続され、他方の端子が抵抗１６７を介して電源端子ＶＤＤに接続されている。 In the NMOS transistor 169, the source is connected to the ground terminal VSS, the drain is connected to one terminal of the resistor 166, and the gate is connected to the drain of the NMOS transistor 161. The other terminal of the resistor 166 is connected to one terminal of the switch 168 and the gate of the NMOS transistor 163. The control terminal of the switch 168 is connected to the third input terminal of the voltage detection circuit 16, and the other terminal is connected to the power supply terminal VDD via the resistor 167.

次に、図３の電圧検出回路１６の動作について説明する。
過放電検出信号ＶＤＬが停止している通常状態では、スイッチ１６８の制御端子にロウレベルが入力されているのでオンして、ＮＭＯＳトランジスタ１６３はオンして、出力端子にロウレベルが出力されている。このとき、ＮＭＯＳトランジスタ１６２、１６９、及びＰＭＯＳトランジスタ１６１がオフしているので、抵抗１６４、１６５、１６７及び１６９には電流が流れない。 Next, the operation of the voltage detection circuit 16 of FIG. 3 will be described.
In the normal state in which the over-discharge detection signal VDC is stopped, the low level is input to the control terminal of the switch 168, so that the low level is turned on, the NMOS transistor 163 is turned on, and the low level is output to the output terminal. At this time, since the NMOS transistors 162 and 169 and the NMOS transistors 161 are turned off, no current flows through the resistors 164, 165, 167 and 169.

過放電状態になり過放電検出信号ＶＤＬが入力されると、スイッチ１６８はオフするが、ＮＭＯＳトランジスタ１６３はオンしている。このときも同様に、抵抗１６４及び１６５には電流が流れない。ここで、充電器４が接続されると、入力端子ＶＭの電圧が電源端子ＶＤＤの電圧より高くなるのでＰＭＯＳトランジスタ１６１はオンする。従って、ＮＭＯＳトランジスタ１６９がオンして、ＮＭＯＳトランジスタ１６３はオフするので、出力端子にハイレベルの検出信号ＶＤが出力される。 When the over-discharge state is entered and the over-discharge detection signal VDC is input, the switch 168 is turned off, but the NMOS transistor 163 is turned on. Similarly, at this time, no current flows through the resistors 164 and 165. Here, when the charger 4 is connected, the voltage of the input terminal VM becomes higher than the voltage of the power supply terminal VDD, so that the epitaxial transistor 161 is turned on. Therefore, the NMOS transistor 169 is turned on and the NMOS transistor 163 is turned off, so that a high-level detection signal VD is output to the output terminal.

以上説明したように、本発明のバッテリ装置によれば、電圧検出回路１６が通常状態、及び充電器４が接続されていない過放電状態において電流を流さないので、消費電流を低減することが出来る。 As described above, according to the battery device of the present invention, the voltage detection circuit 16 does not pass current in the normal state and the over-discharged state in which the charger 4 is not connected, so that the current consumption can be reduced. ..

以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されず、本発明の趣旨を逸脱しない範囲において種々の変更が可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

例えば、本実施形態において、過放電検出信号ＶＤＬがハイレベルであればＮＯＴ回路１６０はなくてよい。また例えば、本実施形態において、充電制御ＦＥＴ１を制御するチャージポンプ１４と、放電制御ＦＥＴ２を制御するチャージポンプ１５を備えているが、チャージポンプは１つであってもよい。 For example, in the present embodiment, if the over-discharge detection signal VDC is at a high level, the NOT circuit 160 may be omitted. Further, for example, in the present embodiment, the charge pump 14 for controlling the charge control FET 1 and the charge pump 15 for controlling the discharge control FET 2 are provided, but the charge pump may be one.

１０ 充放電制御装置
１１ 過放電検出回路
１２ 過充電検出回路
１３ 制御回路
１４、１５ チャージポンプ
１６ 電圧検出回路
１６０ ＮＯＴ回路 10 Charge / discharge control device 11 Over-discharge detection circuit 12 Over-charge detection circuit 13 Control circuits 14, 15 Charge pump 16 Voltage detection circuit 160 NOT circuit

Claims (4)

二次電池の正極端子が接続される電源端子と、
前記二次電池の負極端子が接続される接地端子と、
充電制御ＦＥＴのゲートと接続される充電制御端子と、
正極外部端子と接続される入力端子と、
前記二次電池の過放電を検出する過放電検出回路と、
前記過放電検出回路の過放電検出信号を受けて前記二次電池の充放電を制御する制御回路と、
前記制御回路によって制御されるチャージポンプと、
前記過放電検出回路の過放電検出信号が入力されているときに、前記入力端子の電圧が前記電源端子の電圧より高くなったことを検出する電圧検出回路と、
前記チャージポンプと充電制御端子の間に設けられ、前記制御回路及び前記電圧検出回路によって制御される第一のスイッチと、
前記電源端子と前記充電制御端子の間に設けられ、前記制御回路及び前記電圧検出回路によって制御される第二のスイッチと、
前記入力端子と前記充電制御端子の間に設けられ、前記制御回路及び前記電圧検出回路によって制御される第三のスイッチと、を備え、
前記電圧検出回路は、前記電源端子と前記接地端子の間の第一の抵抗を有し、前記入力端子の電圧が前記電源端子の電圧より高くなったことを検出している間のみ前記第一の抵抗に電流を流す
ことを特徴とする充放電制御装置。 The power supply terminal to which the positive electrode terminal of the secondary battery is connected and
The ground terminal to which the negative electrode terminal of the secondary battery is connected and
Charge control terminal connected to the gate of the charge control FET,
The input terminal connected to the positive electrode external terminal and
An over-discharge detection circuit that detects the over-discharge of the secondary battery, and
A control circuit that controls the charge / discharge of the secondary battery by receiving the over-discharge detection signal of the over-discharge detection circuit, and
The charge pump controlled by the control circuit and
A voltage detection circuit that detects that the voltage at the input terminal is higher than the voltage at the power supply terminal when the overdischarge detection signal of the overdischarge detection circuit is input.
A first switch provided between the charge pump and the charge control terminal and controlled by the control circuit and the voltage detection circuit, and
A second switch provided between the power supply terminal and the charge control terminal and controlled by the control circuit and the voltage detection circuit, and
A third switch provided between the input terminal and the charge control terminal and controlled by the control circuit and the voltage detection circuit is provided.
The voltage detection circuit has a first resistor between the power supply terminal and the ground terminal, and the first is only while detecting that the voltage of the input terminal is higher than the voltage of the power supply terminal. A charge / discharge control device characterized by passing an electric current through a resistor. 前記電圧検出回路は、
前記電源端子と前記接地端子の間に直列に接続された前記第一の抵抗、及び第一のＭＯＳトランジスタと、
前記入力端子と前記接地端子の間に直列に接続された第二のＭＯＳトランジスタ、第二の抵抗、及び第三のＭＯＳトランジスタと、を備え、
前記第三のＭＯＳトランジスタは、前記過放電検出信号によってオフして、
前記第二のＭＯＳトランジスタは、前記入力端子の電圧が前記電源端子の電圧より高くなるとオンして出力端子に検出信号を出力し、
前記第一のＭＯＳトランジスタは、前記出力端子の検出信号によってオンする
ことを特徴とする請求項１に記載の充放電制御装置。 The voltage detection circuit
The first resistor and the first MOS transistor connected in series between the power supply terminal and the ground terminal,
A second MOS transistor, a second resistor, and a third MOS transistor connected in series between the input terminal and the ground terminal are provided.
The third MOS transistor is turned off by the over-discharge detection signal,
The second MOS transistor turns on when the voltage of the input terminal becomes higher than the voltage of the power supply terminal and outputs a detection signal to the output terminal.
The charge / discharge control device according to claim 1, wherein the first MOS transistor is turned on by a detection signal of the output terminal. 前記二次電池の過充電を検出する過充電検出回路と、
前記チャージポンプと放電制御端子の間に設けられ、前記制御回路によって制御される第四のスイッチと、
前記入力端子と前記放電制御端子の間に設けられ、前記制御回路によって制御される第五のスイッチと、
を更に備えることを特徴とする請求項１または２に記載の充放電制御装置。 An overcharge detection circuit that detects overcharge of the secondary battery, and
A fourth switch provided between the charge pump and the discharge control terminal and controlled by the control circuit,
A fifth switch provided between the input terminal and the discharge control terminal and controlled by the control circuit,
The charge / discharge control device according to claim 1 or 2, further comprising. 正極外部端子と負極外部端子の間に直列に接続される二次電池と充電制御ＦＥＴと放電制御ＦＥＴと、
前記二次電池の電圧によって前記充電制御ＦＥＴ及び前記放電制御ＦＥＴを制御する請求項１から３のいずれかに記載の充放電制御装置と
を備えたことを特徴とするバッテリ装置。 A secondary battery, a charge control FET, and a discharge control FET, which are connected in series between the positive electrode external terminal and the negative electrode external terminal,
A battery device including the charge / discharge control device according to any one of claims 1 to 3, which controls the charge control FET and the discharge control FET by the voltage of the secondary battery.
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