WO2024017320A9 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024017320A9
WO2024017320A9 PCT/CN2023/108330 CN2023108330W WO2024017320A9 WO 2024017320 A9 WO2024017320 A9 WO 2024017320A9 CN 2023108330 W CN2023108330 W CN 2023108330W WO 2024017320 A9 WO2024017320 A9 WO 2024017320A9
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WO
WIPO (PCT)
Prior art keywords
light
sub
transmitting
substrate
electrode
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Application number
PCT/CN2023/108330
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English (en)
French (fr)
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WO2024017320A1 (zh
Inventor
李硕
陈友春
尚延阳
闫政龙
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2024017320A1 publication Critical patent/WO2024017320A1/zh
Publication of WO2024017320A9 publication Critical patent/WO2024017320A9/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • OLED organic light emitting diodes
  • a display panel includes a substrate, a first electrode layer and a light-emitting defining layer.
  • the first electrode layer is disposed on one side of the substrate.
  • the first electrode layer includes a plurality of first electrode blocks and a plurality of second electrode blocks, and the area of the first electrode block is greater than the area of the second electrode block.
  • the plurality of first electrode blocks are arranged in an array of multiple rows and columns, each row includes a plurality of first electrode blocks arranged along a first direction, and each column includes a plurality of first electrode blocks arranged along a second direction, and the first direction and the second direction are substantially perpendicular.
  • Each second electrode block is located between four first electrode blocks of two adjacent rows and two columns.
  • the light-emitting defining layer is disposed on a side of the first electrode layer away from the substrate.
  • the light-emitting defining layer has a plurality of first light-transmitting holes, at least a portion of each first electrode block is exposed by a first light-transmitting hole, and at least a portion of each second electrode block is exposed by a first light-transmitting hole. At least a portion of the boundary of at least one of the first light-transmitting holes is a curve.
  • the plurality of first light-transmitting holes include a plurality of first sub-light-transmitting holes, a plurality of second sub-light-transmitting holes, and a plurality of third sub-light-transmitting holes, wherein the first sub-light-transmitting holes and the third sub-light-transmitting holes respectively correspond to exposing at least a portion of a first electrode block, and the second sub-light-transmitting holes correspond to exposing at least a portion of a second electrode block.
  • the plurality of first sub-light-transmitting holes and the plurality of third sub-light-transmitting holes are arranged alternately; along the second direction, the plurality of first sub-light-transmitting holes and the plurality of third sub-light-transmitting holes are arranged alternately.
  • the line connecting the centers of adjacent first sub-light-transmitting holes and third sub-light-transmitting holes is the first line, and the line connecting the centers of two first electrode blocks corresponding to the adjacent first sub-light-transmitting holes and third sub-light-transmitting holes is the second line; there is at least one first line that is not parallel to the corresponding second line.
  • the center lines of the four first light-transmitting holes located at the four corners form a virtual quadrilateral.
  • the virtual quadrilateral has a first center line extending along the first direction and a second center line extending along the second direction; the nine first light-transmitting holes are symmetrical about the first center line and/or the second center line.
  • one of the first sub-light-transmitting hole and the third sub-light-transmitting hole is located at the center and four corners of the virtual quadrilateral; the other is located on the four sides of the virtual quadrilateral.
  • the first light-transmitting hole located at the center and four corners of the virtual quadrilateral is a set light-transmitting hole, and the first light-transmitting holes located on the four sides of the virtual quadrilateral are non-set light-transmitting holes.
  • the light-emitting center of the set light-transmitting hole roughly coincides with the center of the corresponding first electrode block
  • the light-emitting center of the second sub-light-transmitting hole roughly coincides with the center of the corresponding second electrode block.
  • the center of one non-set light-transmitting hole is located on the first side of the center of the corresponding first electrode block, and the center of the other non-set light-transmitting hole is located on the second side of the center of the corresponding first electrode block.
  • the center of one non-set light-transmitting hole is located on the third side of the center of the corresponding first electrode block, and the center of the other non-set light-transmitting hole is located on the fourth side of the center of the corresponding first electrode block.
  • the first side and the second side are two opposite sides of the center of the first electrode block, and the third side and the fourth side are the other two opposite sides of the center of the first electrode block.
  • the plurality of first light-transmitting holes include a plurality of first sub-light-transmitting holes, a plurality of second sub-light-transmitting holes, and a plurality of third sub-light-transmitting holes.
  • the area of the first sub-light-transmitting holes is greater than the area of the third sub-light-transmitting holes; the area of the third sub-light-transmitting holes is greater than the area of the second sub-light-transmitting holes.
  • the first sub-light-transmitting holes and the third sub-light-transmitting holes respectively correspond to exposing at least a portion of a first electrode block
  • the second sub-light-transmitting holes correspond to exposing at least a portion of a second electrode block
  • at least a portion of the boundary of at least one of the first sub-light-transmitting holes, the second sub-light-transmitting holes, and the third sub-light-transmitting holes is a curve.
  • the outer contour of at least one first light-transmitting hole includes a first curved edge and a second curved edge, two ends of the first curved edge and two ends of the second curved edge are connected respectively, and two connection points of the first curved edge and the second curved edge are a first connection point and a second connection point.
  • the line connecting the first connection point and the second connection point is a first line segment, the length of the first line segment is the maximum size of the first light-transmitting hole, and the first light-transmitting hole is divided into a first sub-portion including the first curved edge and a second sub-portion including the second curved edge.
  • the area of the first sub-portion is greater than the area of the second sub-portion.
  • the first curved side and the first line segment form a semicircle, and the second curved side and the first line segment form a semi-ellipse.
  • the plurality of first light-transmitting holes include a plurality of first sub-light-transmitting holes and a plurality of third sub-light-transmitting holes
  • the outer contours of the first sub-light-transmitting holes and/or the third sub-light-transmitting holes include the first sub-light-transmitting holes and/or the third sub-light-transmitting holes.
  • the plurality of first light-transmitting holes include a second sub-light-transmitting hole, and an outer contour of the second sub-light-transmitting hole is substantially circular or elliptical.
  • the outer contour of at least one first light-transmitting hole includes a first straight side, a second straight side, and a third curved side.
  • the first straight side and the second straight side are connected to form a folded edge, and the two ends of the third curved side are respectively connected to the two ends of the folded edge, and the two connection points where the two ends of the third curved side are connected to the folded edge are the third connection point and the fourth connection point.
  • the line connecting the third connection point and the fourth connection point is a second line segment, and the length of the second line segment is the maximum size of the first light-transmitting hole, and the first light-transmitting hole is divided into a third sub-portion including the first straight side and the second straight side and a fourth sub-portion including the third curved side.
  • the area of the third sub-portion is greater than the area of the fourth sub-portion.
  • the third curved edge includes a first sub-straight line segment, a first sub-curved line segment, and a second sub-straight line segment connected in sequence, the first sub-straight line segment is connected to the first straight edge, the second sub-straight line segment is connected to the second straight edge, the first sub-straight line segment is substantially parallel to the second straight edge, and the second sub-straight line segment is substantially parallel to the first straight edge.
  • the plurality of first light-transmitting holes include a plurality of first sub-light-transmitting holes and a plurality of third sub-light-transmitting holes
  • the outer contours of the first sub-light-transmitting holes and/or the third sub-light-transmitting holes include the first straight edge, the second straight edge and the third curved edge.
  • the plurality of first light-transmitting holes include a second sub-light-transmitting hole, and an outer contour of the second sub-light-transmitting hole is substantially in a diamond shape.
  • the outer contours of the first light-transmitting holes are substantially circular or elliptical.
  • the light-emitting defining layer further has a plurality of second light-transmitting holes, and an orthographic projection of each second light-transmitting hole on the substrate is located between orthographic projections of second electrode blocks adjacent to each other along the second direction on the substrate.
  • the outer contours of the first electrode block and the second electrode block are both substantially polygonal in shape.
  • the boundaries of any adjacent first electrode block and second electrode block are opposite and substantially parallel, and the distance between adjacent first electrode blocks and second electrode blocks is substantially equal to a first preset value, which is a process limit value for disconnecting the first electrode block and the second electrode block.
  • the orthographic projections of the first electrode block and the second electrode block on the substrate are both substantially regular octagons.
  • the first electrode layer further includes a plurality of first connecting bars and a plurality of second connecting bars, each first connecting bar being electrically connected to a first electrode block, and each second connecting bar being electrically connected to a second electrode block.
  • the two electrode blocks are electrically connected.
  • one of the first connecting strips and one of the second connecting strips is disposed between each two adjacent first electrode blocks.
  • the display panel further includes a first flat layer, the first flat layer contacts the surface of the first electrode layer close to the substrate.
  • the first flat layer is provided with overlapping holes, each first connecting strip extends into a corresponding overlapping hole, and each second connecting strip extends into a corresponding overlapping hole.
  • the minimum distance between the orthographic projection of the boundary of the overlapping hole on the substrate and the orthographic projection of the boundary of the first light-transmitting hole on the substrate is greater than or equal to a second preset value.
  • the display panel further includes at least one conductive layer, and the at least one conductive layer is disposed between the substrate and the first electrode layer.
  • the at least one conductive layer includes a plurality of first power signal lines extending substantially along the second direction.
  • the orthographic projection of at least one first electrode block on the substrate overlaps with the orthographic projection of at least one first power signal line on the substrate, and the region where the orthographic projections of the first electrode block and the first power signal line on the substrate overlap is symmetrical relative to the midline of the first electrode block along the second direction.
  • the plurality of first power signal lines include a plurality of first power signal line groups, each of which includes two first power signal lines arranged in parallel.
  • a column of first electrode blocks arranged along the second direction overlaps with the orthographic projections of two first power signal lines in one first power signal line group on the substrate, and the two first power signal lines in the first power signal line group are symmetrical with respect to a midline of the column of first electrode blocks along the second direction.
  • the first electrode layer further includes a plurality of first connecting strips and a plurality of second connecting strips.
  • the first power signal line includes a first routing segment and a second routing segment, and the orthographic projection of the first routing segment on the substrate is located within the orthographic projection of the first electrode block on the substrate.
  • the second routing segment is located between two first electrode blocks adjacent to each other in the second direction.
  • the orthographic projections of a first connecting strip and a second connecting strip on the substrate are located between the orthographic projections of the second routing segments of two first power signal lines in a first power signal line group on the substrate.
  • At least one conductive layer further includes a plurality of data lines extending substantially along the second direction.
  • An orthographic projection of at least one second electrode block on the substrate at least partially overlaps with an orthographic projection of at least one data line on the substrate, and an overlapping region of the orthographic projections of the second electrode block and the data line on the substrate is symmetrical with respect to a midline of the second electrode block along the second direction.
  • the plurality of data lines include a plurality of data line groups, each data line group includes two data lines arranged in parallel.
  • the orthographic projection of a column of second electrode blocks arranged along the second direction on the substrate overlaps with the orthographic projection of two data lines in a data line group on the substrate in part, and the two data lines in the data line group are at least partially aligned with each other relative to the column of second electrode blocks. Symmetrical along the midline of the second direction.
  • the light-emitting defining layer further has a plurality of second light-transmitting holes.
  • the data line includes a third routing segment and a fourth routing segment.
  • the orthographic projection of the third routing segment on the substrate is located within the orthographic projection of the second electrode block on the substrate.
  • the fourth routing segment is located between two second electrode blocks adjacent in the second direction.
  • the orthographic projection of each second light-transmitting hole on the substrate is located between the orthographic projections of the fourth routing segments of two data lines in a data line group on the substrate.
  • the at least one conductive layer includes a first gate conductive layer, a second gate conductive layer, a first source-drain conductive layer, and a second source-drain conductive layer arranged in sequence.
  • the first power signal line is located in the second source-drain conductive layer; and/or the plurality of data lines are located in the first source-drain conductive layer.
  • the light-emitting defining layer includes a pixel defining layer, the pixel defining layer is provided with a plurality of first openings, and the first light-transmitting hole includes the first opening.
  • the light-emitting defining layer further has a plurality of second light-transmitting holes.
  • the pixel defining layer is provided with a plurality of second openings, and the second light-transmitting holes include the second openings.
  • the light-emitting defining layer includes a black matrix
  • the black matrix is provided with a plurality of third openings
  • the first light-transmitting hole includes the third openings.
  • the light-emitting defining layer further has a plurality of second light-transmitting holes; the black matrix is provided with a plurality of fourth openings, and the second light-transmitting holes include the fourth openings.
  • the light-emitting defining layer includes a pixel defining layer and a black matrix
  • the first light-transmitting hole includes a first opening of the pixel defining layer and a third opening of the black matrix
  • the shape of the outer contour of the first opening is the same as the shape of the outer contour of the third opening.
  • the second light-transmitting hole includes a second opening of the pixel defining layer and a fourth opening of the black matrix, and a shape of an outer contour of the second opening is the same as a shape of an outer contour of the fourth opening.
  • the display panel further comprises a color film, and the color film is disposed on a side of the light-emitting limiting layer away from the substrate.
  • the color film comprises a plurality of first filter sections and a plurality of second filter sections, and the area of the first filter section is greater than the area of the second filter section.
  • the orthographic projection of the boundary of each first electrode block on the substrate is located within the orthographic projection of the boundary of a first filter section on the substrate.
  • the orthographic projection of the boundary of each second electrode block on the substrate is located within the orthographic projection of the boundary of a second filter section on the substrate.
  • the outer contour of the first filter portion is substantially the same as the outer contour of the first electrode block.
  • the shapes of the outer contours are roughly the same.
  • a display device comprising the display panel as described in any one of the above embodiments.
  • FIG1 is a structural diagram of a display device according to some embodiments.
  • FIG2 is an exploded view of a display device according to some embodiments.
  • FIG3A is a cross-sectional view of a display panel according to some embodiments.
  • FIG3B is a cross-sectional view of another display panel according to some embodiments.
  • FIG4 is a structural diagram of a first electrode according to some embodiments.
  • FIG5 is a structural diagram of another first electrode according to some embodiments.
  • FIG6 is a top view of a first electrode layer according to some embodiments.
  • FIG. 7A is a structural diagram of a first light-transmitting hole of a light-emitting defining layer according to some embodiments.
  • FIG7B is a structural diagram of a light-emitting limiting layer according to some embodiments.
  • FIG. 7C is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG7D is a structural diagram of the first light-transmitting holes and the first electrodes in three rows and three columns in FIG7B ;
  • FIG7E is a structural diagram of the first light-transmitting holes and the first electrodes in three rows and three columns in FIG7C ;
  • FIG8A is a structural diagram of another first light-transmitting hole of a pixel definition layer according to some embodiments.
  • FIG8B is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG8C is a structural diagram of another light-emitting limiting layer according to some embodiments.
  • FIG8D is a structural diagram of the first light-transmitting holes and the first electrodes in three rows and three columns in FIG8B ;
  • FIG8E is a structural diagram of the first light-transmitting holes and the first electrodes in three rows and three columns in FIG8C ;
  • FIG. 9A is a structural diagram of another first light-transmitting hole of a pixel definition layer according to some embodiments.
  • FIG9B is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG9C is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG9D is a structural diagram of the first light-transmitting holes and the first electrodes in three rows and three columns in FIG9B ;
  • FIG9E is a structural diagram of the first light-transmitting holes and the first electrodes in three rows and three columns in FIG9C ;
  • FIG10A is a routing diagram of a first power signal line and a data line according to some embodiments.
  • FIG10B is a routing diagram of a first power signal line and a data line according to some other embodiments.
  • FIG11 is a top view of a first power signal line and a data line and a first electrode layer according to some embodiments
  • FIG12A is a structural diagram of a light-emitting defining layer according to some embodiments.
  • FIG12B is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG12C is a structural diagram of yet another light-emitting defining layer according to some embodiments.
  • FIG12D is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG12E is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG12F is a structural diagram of another light-emitting defining layer according to some embodiments.
  • FIG13 is a top view of a color film according to some embodiments.
  • FIG. 14 is a top view of a first electrode layer, a pixel defining layer, a black matrix, and a color filter stack according to some embodiments.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • the expressions “connected”, “electrically connected” and their derivatives may be used.
  • the term “connected” may be used to indicate that two or more components are in direct physical contact or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the contents of this document.
  • the term “electrically connected” may be used to indicate that two or more components are in direct electrical contact or indirect electrical connection with each other.
  • the embodiments disclosed herein are not necessarily limited to the contents of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, it is conceivable that due to For example, variations in shape relative to the drawings due to manufacturing techniques and/or tolerances. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing.
  • an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the pixel circuit provided in the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, abbreviated as: TFT), field effect transistors (Metal Oxide Semiconductor, abbreviated as: MOS) or other switching devices with the same characteristics.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the embodiments of the present disclosure are described by taking thin film transistors as an example.
  • a display device 1000 which may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images.
  • the display device 1000 may be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, or the like.
  • PDA personal digital assistant
  • VR virtual reality
  • a display device 1000 includes a display panel 100 .
  • the display device 1000 may further include a housing 200 , a circuit board 300 (see FIG2 ) and other electronic components.
  • the display panel 100 and the circuit board 300 (see FIG2 ) may be disposed in the housing 200 .
  • display panel 100 There are various types of display panel 100 , which can be selected according to actual needs.
  • the display panel 100 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, etc., which is not specifically limited in the embodiments of the present disclosure.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display panel 100 includes a display substrate 11 and an encapsulation layer 12 for encapsulating the display substrate 11 .
  • the display substrate 11 has a light-emitting side and a non-light-emitting side that are arranged opposite to each other, and the encapsulation layer 12 is arranged on the light-emitting side of the display substrate 11, that is, the upper side in FIG3A.
  • the encapsulation layer 12 can be an encapsulation film or an encapsulation substrate.
  • the display panel 100 comprises a display area A and a peripheral area B disposed on at least one side of the display area A.
  • FIG2 takes the peripheral area B disposed around the display area A as an example for illustration.
  • the display area A is an area for displaying images and is configured to set a plurality of sub-pixels P.
  • the peripheral area B is an area for not displaying images and is configured to set a display driving circuit, for example, a gate driving circuit and a source driving circuit.
  • the display panel 100 includes a substrate 10 and a plurality of sub-pixels P disposed on one side of the substrate 10 and located in a display area A. As shown in FIG. 2 and FIG. 3A , the display panel 100 includes a substrate 10 and a plurality of sub-pixels P disposed on one side of the substrate 10 and located in a display area A. As shown in FIG. 2 and FIG. 3A , the display panel 100 includes a substrate 10 and a plurality of sub-pixels P disposed on one side of the substrate 10 and located in a display area A. As shown in FIG.
  • the substrate 10 There are many types of the substrate 10 , which can be selected according to actual needs.
  • the substrate 10 may be a rigid substrate.
  • the rigid substrate may be a glass substrate or a polymethyl methacrylate (PMMA) substrate.
  • PMMA polymethyl methacrylate
  • the substrate 10 may be a flexible substrate.
  • the flexible substrate may be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PI polyimide
  • the plurality of sub-pixels P may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color.
  • the first color, the second color and the third color are three primary colors, for example, the first color is red, the second color is blue, and the third color is green.
  • the following takes the first color being blue, the second color being green, and the third color being red as an example to exemplify the present embodiment.
  • the human eye has different sensitivities to red light, green light, and blue light, that is, the human eye is more sensitive to green light than to red light, and is more sensitive to red light than to blue light.
  • the area of the effective light-emitting area of the first sub-pixel is larger than the area of the effective light-emitting area of the third sub-pixel; the area of the effective light-emitting area of the third sub-pixel is larger than the area of the effective light-emitting area of the second sub-pixel.
  • the description of the effective light-emitting area can refer to the following.
  • each sub-pixel P includes a light emitting device 2 and a pixel circuit 3 disposed on a substrate 10.
  • the pixel circuit 3 includes a plurality of thin film transistors 31.
  • the thin film transistor 31 includes an active layer 311 , a source electrode 312 , a drain electrode 313 , and a gate electrode 314 .
  • the source electrode 312 and the drain electrode 313 are in contact with the active layer 311 , respectively.
  • source 312 and the drain 313 can be interchanged, that is, 312 in FIG. 3A represents the drain, and 313 in FIG. 3A represents the source.
  • the light emitting device 2 includes a first electrode 21, a light emitting functional layer 22, and a second electrode 23.
  • the first electrode 21 is electrically connected to a source 312 or a drain 313 of a thin film transistor 31 serving as a driving transistor among a plurality of thin film transistors 31.
  • the first electrode 21 and the thin film transistor 31 are electrically connected.
  • the source 312 is electrically connected for illustration purposes only.
  • first electrode 21 is the anode of the light emitting device 2
  • second electrode 23 is the cathode of the light emitting device 2
  • first electrode 21 is the cathode of the light emitting device 2
  • second electrode 23 is the anode of the light emitting device 2 .
  • the first electrode 21 includes an electrode block 210 and a connecting bar 220 .
  • the electrode block 210 is configured to contact the light-emitting functional layer 22 to form a light-emitting area, that is, the orthographic projection of the light-emitting area on the substrate 10 is located within the orthographic projection of the electrode block 210 on the substrate 10 .
  • connection bar 220 is configured to be electrically connected to the pixel circuit 3 , that is, the connection bar 220 is electrically connected to the source 312 or the drain 313 of the thin film transistor 31 .
  • the first electrode 21 is located in the first electrode layer 20 , that is, the first electrode layer 20 includes a plurality of electrode blocks 210 and a plurality of connecting bars 220 , and the plurality of electrode blocks 210 and the plurality of connecting bars 220 are formed by patterning the first electrode layer 20 .
  • the second electrode 23 is a continuous whole-layer pattern and covers the entire display area A.
  • the light-emitting functional layer 22 only includes a light-emitting layer.
  • the light-emitting functional layer 22 includes, in addition to the light-emitting layer, at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transport layer
  • HIL hole injection layer
  • the display panel 100 further includes a pixel defining layer 70, which is disposed on a side of the first electrode 21 away from the substrate 10.
  • the pixel defining layer 70 has a plurality of first openings 71, and the light emitting device 2 is disposed in one of the first openings 71, that is, the light emitting function layer 22 of the light emitting device 2 is in electrical contact with the electrode block 210 of the first electrode 21 in the first opening 71.
  • the area of the first electrode 21 is larger than the area of the first opening 71 of the pixel defining layer 70, so that the entire first opening 71 of the pixel defining layer 70 is a light-emitting area. That is, the overlapping portion of the first electrode 21, the second electrode 23 and the light-emitting functional layer 22 constitutes a light-emitting area.
  • the effective light emitting area is the area defined by the first opening 71 , that is, the light emitting area is the effective light emitting area.
  • the display panel 100 includes a reflection reduction film 13 , and the reflection reduction film 13 is configured to reduce the reflection intensity of the external ambient light on the display panel 100 .
  • the anti-reflection film 13 includes a polarizer 131 , and the polarizer 131 is disposed on a side of the encapsulation layer 12 away from the substrate 10 .
  • the anti-reflection film 13 includes a black matrix 132 and a color filter 80.
  • the black matrix 132 is used to separate the light emitted from different sub-pixels P, and has the function of reducing the reflected light generated after the external ambient light enters the display panel 100.
  • the color filter 80 can filter out most of the wavelengths of the external ambient light, thereby reducing the reflection intensity of the external ambient light on the display panel 100.
  • the black matrix 132 is disposed on a side of the pixel defining layer 70 away from the substrate 10 .
  • the black matrix 132 has a plurality of third openings 134 , and one third opening 134 exposes at least a portion of the first opening 71 .
  • the effective light emitting area is the area where the first opening 71 and the third opening 134 overlap.
  • the outer contour of the third opening 134 of the black matrix 132 may be the same as the outer contour of the first opening 71 of the pixel defining layer 70 .
  • the size of the third opening 134 of the black matrix 132 may be larger than the size of the first opening 71 of the pixel defining layer 70 , or may be smaller than the size of the first opening 71 of the pixel defining layer 70 .
  • the size of the third opening 134 of the black matrix 132 is larger than the size of the first opening 71 of the pixel defining layer 70 , and the boundary of the orthographic projection of the third opening 134 on the substrate 10 (see FIG3A ) is 2 ⁇ m to 6 ⁇ m away from the boundary of the orthographic projection of the first opening 71 on the substrate 10 (see FIG3A ).
  • the shape and area of the electrode block of the first electrode included in the first electrode layer are adjusted according to the area of the effective light-emitting area, that is, the shape and area of the electrode block of the first electrode are adaptively adjusted according to the first opening of the pixel defining layer or the third opening of the black matrix.
  • the effective light-emitting areas of sub-pixels of different colors are different, the areas of the electrode blocks of the first electrode are different for sub-pixels of different colors, and the production cost is high.
  • the shapes of the first opening of the pixel defining layer and the third opening of the black matrix are not unique. This results in poor versatility of the first electrode layer and high production costs during the production of OLED display devices corresponding to different pixel defining layers or black matrices.
  • the display panel 100 provided in some embodiments of the present disclosure, referring to FIG. 3A and FIG. 7B , includes a light-emitting defining layer 4 having a plurality of first light-transmitting holes 40 , and the orthographic projection of the first light-transmitting holes 40 on the substrate 10 is the effective light-emitting area.
  • the light-emitting defining layer 4 includes a pixel defining layer 70
  • the first light-transmitting hole 40 includes a first opening 71 on the pixel defining layer 70
  • the effective light-emitting area is an area defined by the first opening 71 .
  • the light-emitting defining layer 4 includes a black matrix 132
  • the first light-transmitting hole 40 includes a third opening 134
  • the effective light-emitting area is an area defined by the third opening 134 .
  • the light-emitting defining layer 4 includes a pixel defining layer 70 and a black matrix 132.
  • the first light-transmitting hole 40 includes a first opening 71 and a third opening 134, and the effective light-emitting area is the area where the first opening 71 and the third opening 134 overlap.
  • FIG. 7A to 9E illustrate the example that the light-emitting defining layer 4 includes the pixel defining layer 70 or the black matrix 132.
  • FIG. 12A to 12F illustrate the example that the light-emitting defining layer 4 includes the pixel defining layer 70 and the black matrix 132.
  • the plurality of electrode blocks 210 of the plurality of first electrodes 21 include a plurality of first electrode blocks 211 and a plurality of second electrode blocks 212 .
  • each first electrode block 211 is exposed by a first light-transmitting hole 40
  • at least a portion of each second electrode block 212 is exposed by a first light-transmitting hole 40 , to form an effective light-emitting area.
  • a plurality of first electrode blocks 211 are arranged in a plurality of rows and columns, each row includes a plurality of first electrode blocks 211 arranged along a first direction X, and each column includes a plurality of first electrode blocks 211 arranged along a second direction Y, and the first direction X is substantially perpendicular to the second direction Y.
  • Each second electrode block 212 is located between four first electrode blocks 211 arranged in two adjacent rows and two columns.
  • the area of the first electrode block 211 is larger than the area of the second electrode block 212 , so that the first electrode block 211 matches the sub-pixel P with a larger effective light emitting area.
  • the first electrode block 211 corresponds to the first sub-pixel and the third sub-pixel. That is, among all the first electrode blocks 211, some first electrode blocks 211 form part of the effective light-emitting area as the first electrode 21 (see FIG. 3A ) of the light-emitting device 2 (see FIG. 3A ) of the first sub-pixel, and other first electrode blocks 211 form part of the effective light-emitting area as the first electrode 21 (see FIG. 3A ) of the light-emitting device 2 (see FIG. 3A ) of the third sub-pixel.
  • the second electrode block 212 forms part of the effective light-emitting area as the first electrode 21 (see FIG. 3A ) of the light-emitting device 2 (see FIG. 3A ) of the second sub-pixel.
  • the first electrode layer 20 provided in the embodiment of the present disclosure includes a first electrode block 211 with a larger area and a second electrode block 212 with a smaller area.
  • the first electrode block 211 can be adapted to the sub-pixel with the largest area of the effective light-emitting area, for example, the first sub-pixel; the second electrode block 212 can be adapted to the sub-pixel P with the smallest area of the effective light-emitting area, for example, the second sub-pixel.
  • the effective light-emitting areas of the remaining sub-pixels P can all be formed on the first electrode block 211. That is, the first electrode layer 20 provided in the embodiment of the present disclosure only
  • the two types of electrode blocks 210 can be adapted to at least three types of sub-pixels P, which can reduce the difficulty of patterning the first electrode layer 20 and thus reduce the preparation cost of the multiple first electrodes 21 formed.
  • the shapes of the first opening 71 of the pixel defining layer 70 and the third opening 134 of the black matrix 132 are not unique, the shape of the first light-transmitting hole 40 of the light-emitting defining layer 4 is also not unique.
  • the shapes and areas of the first electrode block 211 and the second electrode block 212 can be adjusted accordingly to adapt to different types of light-emitting defining layers 4, thereby reducing the production cost of the display device 1000 corresponding to different light-emitting defining layers 4.
  • the outer contours of the first electrode block 211 and the second electrode block 212 are both substantially polygonal in shape.
  • the orthographic projections of the first electrode block 211 and the second electrode block 212 on the substrate 10 are both approximately regular octagons.
  • the orthographic projections of the first electrode block 211 and the second electrode block 212 on the substrate 10 can also be regular hexagons, regular decagons, regular dodecagons, etc., which are not specifically limited in the embodiments of the present disclosure.
  • any adjacent first electrode blocks 211 and second electrode blocks 212 are opposite and substantially parallel, and the distance between adjacent first electrode blocks 211 and second electrode blocks 212 is substantially equal to the first preset value.
  • the first preset value is a process limit value for disconnecting the first electrode block 211 and the second electrode block 212, that is, the first preset value can be set according to the process accuracy, with the first electrode block 211 and the second electrode block 212 of the same layer being disconnected as a reference.
  • the first preset value is 3.5 ⁇ m to 6.5 ⁇ m.
  • the first preset value is any one of 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m and 6.5 ⁇ m.
  • the area utilization rate of the first electrode block 211 and the second electrode block 212 is high, so that the area of the first electrode block 211 and the second electrode block 212 can be set larger, so that the first light-transmitting holes 40 with the smallest areas of various light-emitting defining layers 4 can all be formed on the first electrode block 211, and other first light-transmitting holes 40 with larger areas can all be formed on the second electrode block 212, thereby improving the versatility of the first electrode layer 20, so that the display devices 1000 corresponding to different light-emitting defining layers 4 can all adopt the above-mentioned first electrode layer 20, thereby reducing the preparation cost of producing a variety of display devices 1000 corresponding to different light-emitting defining layers 4.
  • At least part of the boundary of at least one first light-transmitting hole 40 of the light-emitting defining layer 4 is a curve.
  • the diffraction generated by the external ambient light can be evenly dispersed at the curved boundary of the first light-transmitting hole 40, thereby improving the color separation caused by the external ambient light.
  • the multiple first light-transmitting holes 40 may include multiple first sub-light-transmitting holes 41, multiple second sub-light-transmitting holes 42 and multiple third sub-light-transmitting holes 43.
  • the first sub-light-transmitting holes 41 and the third sub-light-transmitting holes 43 respectively expose at least a portion of a first electrode block 211
  • the second sub-light-transmitting hole 42 exposes at least a portion of a second electrode block 212.
  • the multiple first sub-light-transmitting holes 41 and the multiple third sub-light-transmitting holes 43 are alternately arranged.
  • the multiple first sub-light-transmitting holes 41 and the multiple third sub-light-transmitting holes 43 are alternately arranged.
  • At least a portion of the boundary of at least one of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 is a curve, so that the light-emitting center C (see Figure 7A) of the same sub-pixel P (see Figure 2) is distributed in the same way, making the brightness distribution of the display panel 100 more uniform and improving the display effect.
  • the area of the first sub-light-transmitting hole 41 is greater than the area of the third sub-light-transmitting hole 43; the area of the third sub-light-transmitting hole 43 is greater than the area of the second sub-light-transmitting hole 42.
  • the first sub-light-transmitting hole 41 corresponds to the first sub-pixel
  • the second sub-light-transmitting hole 42 corresponds to the second sub-pixel
  • the third sub-light-transmitting hole 43 corresponds to the third sub-pixel.
  • the outer contour of at least one first light transmission hole 40 includes a first curved edge B1 and a second curved edge B2.
  • the two ends of the first curved edge B1 and the two ends of the second curved edge B2 are connected respectively, and the two connection points of the first curved edge B1 and the second curved edge B2 are the first connection point and the second connection point.
  • the line connecting the first connection point and the second connection point is a first line segment M1
  • the length of the first line segment M1 is the maximum size of the first light-transmitting hole 40
  • the first light-transmitting hole 40 is divided into a first sub-portion S1 including a first curved edge B1 and a second sub-portion S2 including a second curved edge B2.
  • the area of the first sub-portion S1 is greater than the area of the second sub-portion S2.
  • the light-emitting center C of the first light-transmitting hole 40 is located in the first sub-portion S1.
  • the first curved side B1 and the first line segment M1 form a semicircle
  • the second curved side B2 and the first line segment M1 form a semi-ellipse.
  • the area of the semicircle is larger than the area of the semi-ellipse
  • the luminous center C is located on the side of the semicircle away from the semi-ellipse, that is, inside the semicircle.
  • the outer contour of the first sub-light-transmitting holes 41 and/or the third sub-light-transmitting holes 43 includes a first curved edge B1 and a second curved edge B2.
  • the outer contour of the second sub-light-transmitting hole 42 is substantially circular or elliptical.
  • substantially circular or elliptical means that the shape is circular or elliptical as a whole, but is not limited to a standard circular or elliptical shape. That is, the "circular or elliptical” here includes not only a basic rhombus shape, but also a shape similar to a circular or elliptical shape in consideration of process conditions.
  • the shape of a circle For example, a circle or ellipse where the local segments are straight lines.
  • the outer contour of at least one first light transmission hole 40 includes a first straight side D1, a second straight side D2, and a third curved side B3.
  • the first straight side D1 and the second straight side D2 are connected to form a folded side, and the two ends of the third curved side B3 are respectively connected to the two ends of the folded side, and the two connection points where the two ends of the third curved side B3 are connected to the folded side are the third connection point and the fourth connection point.
  • the line connecting the third connection point and the fourth connection point is the second line segment M2, the length of the second line segment M2 is the maximum size of the first light-transmitting hole 40, and the first light-transmitting hole 40 is divided into a third sub-portion S3 including the first straight side D1 and the second straight side D2 and a fourth sub-portion S4 including the third curved side B3.
  • the area of the third sub-portion S3 is greater than the area of the fourth sub-portion S4.
  • the light-emitting center C of the first light-transmitting hole 40 is located in the third sub-portion S3.
  • the third curved side B3 includes a first sub-straight line segment B31, a first sub-curved line segment B32, and a second sub-straight line segment B33 connected in sequence, the first sub-straight line segment B31 is connected to the first straight side D1, and the second sub-straight line segment B33 is connected to the second straight side D2.
  • the first sub-straight line segment B31 is substantially parallel to the second straight side D2, and the second sub-straight line segment B33 is substantially parallel to the first straight side D1.
  • the area of the third sub-portion S3 is greater than the area of the fourth sub-portion S4, and the light-emitting center C is located in the third sub-portion S3.
  • the outer contour of the first sub-light-transmitting holes 41 and/or the third sub-light-transmitting holes 43 includes a first straight side D1, a second straight side D2 and a third curved side B3, and the shape of the outer contour of the second sub-light-transmitting hole 42 is roughly rhombus-shaped.
  • rhombus-shaped means that the shape is rhombus-shaped as a whole, but is not limited to a standard rhombus. That is, the "rhombus-shaped” here includes not only the basic rhombus shape, but also the shape similar to the rhombus in consideration of the process conditions. For example, the corners of the rhombus are curved, that is, the corners are smooth.
  • the outer contour of at least one first light-transmitting hole 40 is roughly circular or elliptical.
  • the light-emitting center C of the first light-transmitting hole 40 is the center of the circle or the center of the ellipse.
  • FIG9A takes the case where the outer contour of the first light-transmitting hole is roughly circular as an example.
  • the multiple first light-transmitting holes 40 include multiple first sub-light-transmitting holes 41, multiple second sub-light-transmitting holes 42 and multiple third sub-light-transmitting holes 43
  • the shapes of the outer contours of the first sub-light-transmitting holes 41, the second sub-light-transmitting holes 42 and the third sub-light-transmitting holes 43 are all roughly circular or elliptical.
  • the display panel 100 can also flexibly adjust the position of the light-emitting center C of different sub-pixels P (see Figure 2), and then adjust the actual brightness center of the pixel unit composed of multiple sub-pixels P, so that the actual brightness center distribution of each pixel unit in the entire display panel 100 is more uniform.
  • the line connecting the centers of adjacent first sub-light-transmitting holes 41 and third sub-light-transmitting holes 43 is the first line L1
  • the line connecting the centers of two first electrode blocks 211 corresponding to adjacent first sub-light-transmitting holes 41 and third sub-light-transmitting holes 43 is the second line L2
  • the luminous center C of the sub-pixel P (see Figure 2) can be adjusted, and then the actual brightness center of the pixel unit composed of multiple sub-pixels P can be adjusted, so that the actual brightness center distribution of each pixel unit in the entire display panel 100 is more uniform.
  • the center lines of the four first light-transmitting holes 40 located at the four corners form a virtual quadrilateral
  • the virtual quadrilateral has a first center line C1 extending along the first direction X and a second center line C2 extending along the second direction Y.
  • the first center line C1 and the second center line C2 both pass through the light-emitting center C of the first light-transmitting hole 40 located at the center among the nine first light-transmitting holes 40.
  • the nine first light-transmitting holes 40 are symmetrical about the first center line C1 and/or the second center line C2 to avoid the problem of color separation caused by the light emission centers C of multiple sub-pixels P in a pixel unit being offset, thereby improving the display effect.
  • the virtual quadrilateral is substantially a rectangle, and two of the four sides of the rectangle are substantially parallel to the first direction X, and the other two sides are substantially parallel to the second direction Y.
  • the nine first light-transmitting holes 40 are symmetrical about the first center line C1, and the nine first light-transmitting holes 40 are also symmetrical about the second center line C2.
  • the nine first light-transmitting holes 40 are centrally symmetrically distributed about the center of the virtual quadrilateral to avoid the problem of color separation caused by the light emission center C of multiple sub-pixels P in one pixel unit being offset, thereby improving the display effect.
  • the virtual quadrilateral is substantially an isosceles trapezoid, and the top side and the bottom side of the isosceles trapezoid are substantially parallel to the first direction X.
  • the nine first light-transmitting holes 40 are symmetrical about the second center line C2, and the two first light-transmitting holes 40 located between the top and bottom sides of the isosceles trapezoid among the nine first light-transmitting holes 40 are also symmetrical about the first center line C1, so as to avoid the problem of color separation caused by the offset of the light-emitting center C of multiple sub-pixels P in a pixel unit, thereby improving the display effect.
  • the virtual quadrilateral is substantially an isosceles trapezoid, and the top side and the bottom side of the isosceles trapezoid are substantially parallel to the second direction Y.
  • one of the first sub-light-transmitting hole 41 and the third sub-light-transmitting hole 43 is located at the center and four corners of the virtual quadrilateral; the other is located on the four sides of the virtual quadrilateral.
  • the first light-transmitting hole 40 located at the center and four corners of the virtual quadrilateral is a set light-transmitting hole, and the first light-transmitting hole 40 located on the four sides of the virtual quadrilateral is a non-set light-transmitting hole.
  • the set light-transmitting hole is the first sub-light-transmitting hole 41
  • the non-set light-transmitting hole is the third sub-light-transmitting hole 43
  • the set light-transmitting hole is the third sub-light-transmitting hole 43
  • the non-set light-transmitting hole is the first sub-light-transmitting hole 41.
  • the luminous center C of the light-transmitting hole is set to roughly coincide with the center of the corresponding first electrode block 211
  • the luminous center C of the second sub-light-transmitting hole 42 is set to roughly coincide with the center of the corresponding second electrode block 212 .
  • the plurality of set light-transmitting holes and the plurality of second sub-light-transmitting holes 42 are symmetrical about the first center line C1 and/or the second center line C.
  • the center of one non-set light-transmitting hole is located on the first side of the center of the corresponding first electrode block 211, and the center of the other non-set light-transmitting hole is located on the second side of the center of the corresponding first electrode block 211.
  • the two non-set light-transmitting holes that are opposite to each other in the first direction X are symmetrical about the second center line C2.
  • the center of one non-set light-transmitting hole is located on the third side of the center of the corresponding first electrode block 211, and the center of the other non-set light-transmitting hole is located on the fourth side of the center of the corresponding first electrode block 211.
  • the two non-set light-transmitting holes that are opposite to each other in the second direction Y are symmetrical about the first center line C1.
  • first side and the second side are two opposite sides of the center of the first electrode block 211
  • third side and the fourth side are the other two opposite sides of the center of the first electrode block 211.
  • first side, the second side, the third side and the fourth side are four sides of the center of the first electrode block 211 in the first direction X and the second direction Y, respectively.
  • the first sub-light-transmitting hole 41 is a non-set light-transmitting hole
  • the third sub-light-transmitting hole 43 is a set light-transmitting hole.
  • the outer contour of the first sub-light-transmitting hole 41 includes a first curved side B1 and a second curved side B2, the first curved side B1 and the first line segment M1 form a semicircle, and the second curved side B2 and the first line segment M1 form a semi-ellipse; and the center of the semicircle of the first sub-light-transmitting hole 41 is aligned with the corresponding first The centers of the electrode blocks 211 coincide with each other.
  • the outer contour of the second light-transmitting sub-hole 42 is substantially circular, and the center of the circle coincides with the center of the corresponding second electrode block 212.
  • the outer contour of the third light-transmitting sub-hole 43 is substantially circular, and the center of the circle coincides with the center of the corresponding first electrode block 211.
  • the semicircular portion of one first sub-light-transmitting hole 41 is located on one side of the corresponding elliptical portion in the second direction Y; the semicircular portion of the other first sub-light-transmitting hole 41 is located on the other side of the corresponding elliptical portion in the second direction Y.
  • the semicircular portion of one first sub-light-transmitting hole 41 is located on one side of the corresponding elliptical portion in the first direction X; the semicircular portion of the other first sub-light-transmitting hole 41 is located on the other side of the corresponding elliptical portion in the first direction X.
  • the minimum radial dimension of the above-mentioned first light-transmitting hole 40 is 19 ⁇ m ⁇ 21 ⁇ m, and the minimum distance between the first light-transmitting hole 40 and the electrode block 210 is 5.3 ⁇ m ⁇ 7.3 ⁇ m.
  • the distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the corresponding overlapping hole 301 is 18.38 ⁇ m ⁇ 20.38 ⁇ m
  • the distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 13 ⁇ m ⁇ 15 ⁇ m
  • the distance between the boundary of the third sub-light-transmitting hole 43 and the boundary of the corresponding overlapping hole 301 is 21.27 ⁇ m ⁇ 23.27 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 of different PPIs are not the same.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 are greater than or equal to the second preset value, the description of the overlapping hole 301 and the second preset value can be referred to below, and the embodiments of the present disclosure will not be repeated here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 is 20 ⁇ m to 22 ⁇ m
  • the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 is 22.83 ⁇ m to 24.83 ⁇ m.
  • the opening ratio of the first light-transmitting sub-hole 41 is 5.24% to 7.24%
  • the opening ratio of the second light-transmitting sub-hole 42 is 2.79% to 4.79%
  • the opening ratio of the third light-transmitting hole 43 is 3.46% to 5.46%.
  • the display panel 100 with a 400PPI is used as an example here for illustration, and the opening ratios of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 with different PPIs are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the first sub-light-transmitting hole 41 is a set light-transmitting hole
  • the third sub-light-transmitting hole 43 is a non-set light-transmitting hole.
  • the outer contour of the third sub-light-transmitting hole 43 includes a first curved edge B1 and a second curved edge B2, the first curved edge B1 and the first line segment M1 form a semicircle, and the second curved edge B2 and the first line segment M1 form a semi-ellipse; and the center of the semicircle of the third sub-light-transmitting hole 43 coincides with the center of the corresponding first electrode block 211.
  • the outer contour of the second light-transmitting sub-hole 42 is substantially circular, and the center of the circle coincides with the center of the corresponding second electrode block 212.
  • the outer contour of the first light-transmitting sub-hole 41 is substantially circular, and the center of the circle coincides with the center of the corresponding first electrode block 211.
  • the semicircular portion of one third sub-light-transmitting hole 43 is located on one side of the corresponding elliptical portion in the second direction Y; the semicircular portion of the other third sub-light-transmitting hole 43 is located on the other side of the corresponding elliptical portion in the second direction Y.
  • the semicircular portion of one third sub-light-transmitting hole 43 is located on one side of the corresponding elliptical portion in the first direction X; the semicircular portion of the other third sub-light-transmitting hole 43 is located on the other side of the corresponding elliptical portion in the first direction X.
  • the minimum radial dimension of the above-mentioned first light-transmitting hole 40 is 19 ⁇ m ⁇ 21 ⁇ m, and the minimum distance between the first light-transmitting hole 40 and the electrode block 210 is 5.3 ⁇ m ⁇ 7.3 ⁇ m.
  • the distance between the boundary of the first light-transmitting sub-hole 41 and the boundary of the corresponding overlapping hole 301 is The distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 18.69 ⁇ m ⁇ 20.69 ⁇ m, the distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 12.42 ⁇ m ⁇ 14.42 ⁇ m, and the distance between the boundary of the third sub-light-transmitting hole 43 and the boundary of the corresponding overlapping hole 301 is 19.94 ⁇ m ⁇ 21.94 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 of different PPIs are not the same.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 are greater than or equal to the second preset value, the description of the overlapping hole 301 and the second preset value can be referred to below, and the embodiments of the present disclosure will not be repeated here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 is 21.53 ⁇ m to 23.53 ⁇ m
  • the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 is 22.83 ⁇ m to 24.83 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 corresponding to the display panels 100 of different PPIs, and the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the opening ratio of the first sub-light-transmitting hole 41 is 5.88% to 7.88%
  • the opening ratio of the second sub-light-transmitting hole 42 is 3.18% to 5.18%
  • the opening ratio of the third sub-light-transmitting hole 43 is 3.92% to 5.92%.
  • the total opening ratio of the sub-pixel P is 16.16% to 24.16%.
  • the display panel 100 with a 400PPI is used as an example here for illustration, and the opening ratios of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 with different PPIs are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the first sub-light-transmitting hole 41 is a non-set light-transmitting hole
  • the third sub-light-transmitting hole 43 is a set light-transmitting hole.
  • the outer contour of the first light-transmitting sub-hole 41 includes a first straight side D1, a second straight side D2 and a third curved side B3, and the two ends of the third curved side B3 are respectively connected to the first straight side D1 and the second straight side D2 to form a third connection point and a fourth connection point.
  • the midpoint of the line connecting the third connection point and the fourth connection point that is, the midpoint of the second line segment M2 coincides with the center of the corresponding first electrode block 211.
  • the outer contour of the second light-transmitting sub-hole 42 is roughly rhombus-shaped, and the center of the rhombus coincides with the center of the corresponding second electrode block 212.
  • the outer contour of the third light-transmitting sub-hole 43 is roughly rhombus-shaped, and the center of the rhombus coincides with the center of the corresponding first electrode block 211.
  • the third curved side B3 of one first sub-light-transmitting hole 41 is located on one side of the corresponding second line segment M2 in the second direction Y; the third curved side B3 of the other first sub-light-transmitting hole 41 is located on the other side of the corresponding second line segment M2 in the second direction Y.
  • the third curved side B3 of one first sub-light-transmitting hole 41 is located on one side of the corresponding second line segment M2 in the first direction X; the third curved side B3 of the other first sub-light-transmitting hole 41 is located on the other side of the corresponding second line segment M2 in the first direction X.
  • the minimum radial dimension of the above-mentioned first light-transmitting hole 40 is 19.68 ⁇ m ⁇ 21.68 ⁇ m, and the minimum distance between the first light-transmitting hole 40 and the electrode block 210 is 3 ⁇ m ⁇ 3.2 ⁇ m.
  • the distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the corresponding overlapping hole 301 is 14.9 ⁇ m ⁇ 16.9 ⁇ m
  • the distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 10 ⁇ m ⁇ 12 ⁇ m
  • the distance between the boundary of the third sub-light-transmitting hole 43 and the boundary of the corresponding overlapping hole 301 is 18.1 ⁇ m ⁇ 20.1 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 of different PPIs are not the same.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 are greater than or equal to the second preset value, the description of the overlapping hole 301 and the second preset value can be referred to below, and the embodiments of the present disclosure will not be repeated here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 is 20 ⁇ m to 22 ⁇ m
  • the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 is 22 ⁇ m to 24 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 corresponding to the display panels 100 of different PPIs, and the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the opening ratio of the first light-transmitting sub-hole 41 is 7.48% to 9.48%
  • the opening ratio of the second light-transmitting sub-hole 42 is 4.15% to 6.15%
  • the opening ratio of the third light-transmitting sub-hole 43 is 5.06% to 7.06%.
  • the total aperture ratio of the sub-pixel P is 20.84% to 28.84%.
  • the display panel 100 with a 400PPI is used as an example here for illustration, and the opening ratios of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 with different PPIs are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the first sub-light-transmitting hole 41 is a set light-transmitting hole
  • the third sub-light-transmitting hole 43 is a non-set light-transmitting hole.
  • the outer contour of the third light-transmitting sub-hole 43 includes a first straight side D1, a second straight side D2 and a third curved side B3, and the two ends of the third curved side B3 are respectively connected to the first straight side D1 and the second straight side D2 to form a third connection point and a fourth connection point.
  • the midpoint of the line connecting the third connection point and the fourth connection point that is, the midpoint of the second line segment M2 coincides with the center of the corresponding first electrode block 211.
  • the outer contour of the second light-transmitting sub-hole 42 is roughly rhombus-shaped, and the center of the rhombus coincides with the center of the corresponding second electrode block 212.
  • the outer contour of the first light-transmitting sub-hole 41 is roughly rhombus-shaped, and the center of the rhombus coincides with the center of the corresponding first electrode block 211.
  • the third curved side B3 of one third sub-light-transmitting hole 43 is located on one side of the corresponding second line segment M2 in the second direction Y; the third curved side B3 of the other third sub-light-transmitting hole 43 is located on the other side of the corresponding second line segment M2 in the second direction Y.
  • the third curved side B3 of one third sub-light-transmitting hole 43 is located on one side of the corresponding second line segment M2 in the first direction X; the third curved side B3 of the other third sub-light-transmitting hole 43 is located on the other side of the corresponding second line segment M2 in the first direction X.
  • the minimum radial dimension of the above-mentioned first light-transmitting hole 40 is 19.68 ⁇ m ⁇ 21.68 ⁇ m, and the minimum distance between the first light-transmitting hole 40 and the electrode block 210 is 3 ⁇ m ⁇ 3.2 ⁇ m.
  • the distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the corresponding overlapping hole 301 is 15.16 ⁇ m ⁇ 17.16 ⁇ m
  • the distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 9.7 ⁇ m ⁇ 11.7 ⁇ m
  • the distance between the boundary of the third sub-light-transmitting hole 43 and the boundary of the corresponding overlapping hole 301 is 17.6 ⁇ m ⁇ 19.6 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 of different PPIs are not the same.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 are greater than or equal to the second preset value, the description of the overlapping hole 301 and the second preset value can be referred to below, and the embodiments of the present disclosure will not be repeated here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 is 20 ⁇ m to 22 ⁇ m
  • the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 is 24.56 ⁇ m to 26.56 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 corresponding to the display panels 100 of different PPIs, and the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the opening ratio of the first sub-light-transmitting hole 41 is 7.45% to 9.45%
  • the opening ratio of the second sub-light-transmitting hole 42 is 4.13% to 6.13%
  • the opening ratio of the third sub-light-transmitting hole 43 is 5.04% to 7.04%.
  • the total opening ratio of the sub-pixel P is 20.75% to 28.75%.
  • the display panel 100 with a 400PPI is used as an example here for illustration, and the opening ratios of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 with different PPIs are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the first sub-light-transmitting hole 41 is a set light-transmitting hole
  • the third sub-light-transmitting hole 43 is a non-set light-transmitting hole.
  • the outer contours of the third light-transmitting sub-holes 43 are all substantially circular, and the center of the circle does not coincide with the center of the corresponding first electrode block 211 .
  • the outer contour of the second light-transmitting sub-hole 42 is substantially circular, and the center of the circle coincides with the center of the corresponding second electrode block 212.
  • the outer contour of the first light-transmitting sub-hole 41 is substantially circular, and the center of the circle coincides with the center of the corresponding first electrode block 211.
  • the center of one third sub-light-transmitting hole 43 is located on one side of the center of the corresponding first electrode block 211 in the second direction Y; the center of the other third sub-light-transmitting hole 43 is located on the other side of the center of the corresponding first electrode block 211 in the second direction Y.
  • the center of one third sub-light-transmitting hole 43 is located on one side of the center of the corresponding first electrode block 211 in the first direction X; the center of the other third sub-light-transmitting hole 43 is located on the other side of the center of the corresponding first electrode block 211 in the second direction Y.
  • the other side in the first direction X of the center of the first electrode block 211 is located on one side of the center of the corresponding first electrode block 211 in the first direction X;
  • the minimum radial dimension of the above-mentioned first light-transmitting hole 40 is 19 ⁇ m ⁇ 21 ⁇ m, and the minimum distance between the first light-transmitting hole 40 and the electrode block 210 is 5.5 ⁇ m ⁇ 7.5 ⁇ m.
  • the distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the corresponding overlapping hole 301 is 19.12 ⁇ m ⁇ 21.12 ⁇ m
  • the distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 12.34 ⁇ m ⁇ 14.34 ⁇ m
  • the distance between the boundary of the third sub-light-transmitting hole 43 and the boundary of the corresponding overlapping hole 301 is 20.4 ⁇ m ⁇ 22.4 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 of different PPIs are not the same.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 are greater than or equal to the second preset value, the description of the overlapping hole 301 and the second preset value can be referred to below, and the embodiments of the present disclosure will not be repeated here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 is 20 ⁇ m to 22 ⁇ m
  • the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 is 22 ⁇ m to 24 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 corresponding to the display panels 100 of different PPIs, and the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the opening ratio of the first sub-light-transmitting hole 41 is 5.82% to 7.82%
  • the opening ratio of the second sub-light-transmitting hole 42 is 3.12% to 5.12%
  • the opening ratio of the third sub-light-transmitting hole 43 is 3.87% to 5.87%.
  • the display panel 100 with a 400PPI is used as an example here for illustration, and the opening ratios of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 with different PPIs are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the first sub-light-transmitting hole 41 is a non-set light-transmitting hole
  • the third The sub-light-transmitting hole 43 is a set light-transmitting hole.
  • the outer contours of the first light-transmitting sub-holes 41 are all substantially circular, and the center of the circle does not coincide with the center of the corresponding first electrode block 211 .
  • the outer contour of the second light-transmitting sub-hole 42 is substantially circular, and the center of the circle coincides with the center of the corresponding second electrode block 212.
  • the outer contour of the third light-transmitting sub-hole 43 is substantially circular, and the center of the circle coincides with the center of the corresponding first electrode block 211.
  • the center of one first sub-light-transmitting hole 41 is located on one side of the center of the corresponding first electrode block 211 in the second direction Y; the center of the other first sub-light-transmitting hole 41 is located on the other side of the center of the corresponding first electrode block 211 in the second direction Y.
  • the center of one first sub-light-transmitting hole 41 is located on one side of the center of the corresponding first electrode block 211 in the first direction X; the center of the other first sub-light-transmitting hole 41 is located on the other side of the center of the corresponding first electrode block 211 in the first direction X.
  • the minimum radial dimension of the above-mentioned first light-transmitting hole 40 is 19 ⁇ m ⁇ 21 ⁇ m, and the minimum distance between the first light-transmitting hole 40 and the electrode block 210 is 5.5 ⁇ m ⁇ 7.5 ⁇ m.
  • the distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the corresponding overlapping hole 301 is 18.7 ⁇ m ⁇ 20.7 ⁇ m
  • the distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the corresponding overlapping hole 301 is 12.65 ⁇ m ⁇ 14.65 ⁇ m
  • the distance between the boundary of the third sub-light-transmitting hole 43 and the boundary of the corresponding overlapping hole 301 is 20.78 ⁇ m ⁇ 22.78 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 of different PPIs are not the same.
  • the distances between the boundaries of the boundary overlapping holes 301 of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 are greater than or equal to the second preset value, the description of the overlapping hole 301 and the second preset value can be referred to below, and the embodiments of the present disclosure will not be repeated here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 is 20 ⁇ m to 22 ⁇ m
  • the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 is 22 ⁇ m to 24 ⁇ m.
  • the 400PPI display panel 100 is used as an example for illustration here.
  • the minimum distance between the boundary of the first sub-light-transmitting hole 41 and the boundary of the second sub-light-transmitting hole 42 corresponding to the display panels 100 of different PPIs, and the minimum distance between the boundary of the second sub-light-transmitting hole 42 and the boundary of the third sub-light-transmitting hole 43 are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the opening ratio of the first sub-light-transmitting hole 41 is 5.82% to 7.82%
  • the opening ratio of the second sub-light-transmitting hole 42 is 3.12% to 5.12%
  • the opening ratio of the third sub-light-transmitting hole 43 is 3.87% to 5.87%.
  • the display panel 100 with a 400PPI is used as an example here for illustration, and the opening ratios of the first sub-light-transmitting hole 41, the second sub-light-transmitting hole 42 and the third sub-light-transmitting hole 43 corresponding to the display panels 100 with different PPIs are not the same, and are specifically set according to the parameter requirements of the display panel 100.
  • the first electrode layer 20 further includes a plurality of connecting bars 220, and the plurality of connecting bars 220 include a plurality of first connecting bars 221 and a plurality of second connecting bars 222.
  • Each first connecting bar 221 is electrically connected to a first electrode block 211
  • each second connecting bar 222 is electrically connected to a second electrode block 212.
  • a first connecting bar 221 and a second connecting bar 222 are provided between each two adjacent first electrode blocks 211 along the second direction Y.
  • the first connecting bar 221 and the second connecting bar 222 are centrally arranged, which is beneficial to the arrangement of the first electrode blocks 211 and the second electrode blocks 212.
  • the shape of the connecting bar 220 is roughly a long strip.
  • the length of the first connecting bar 221 is greater than or equal to 7.9 ⁇ m
  • the width is greater than or equal to 4.6 ⁇ m.
  • the length of the second connecting bar is any one of 7.9 ⁇ m, 8 ⁇ m, 8.1 ⁇ m, 8.2 ⁇ m and 8.3 ⁇ m
  • the width is any one of 4.6 ⁇ m, 4.7 ⁇ m, 4.8 ⁇ m, 4.9 ⁇ m and 5 ⁇ m.
  • substantially in the shape of an elongated strip means that the shape is rectangular as a whole, but is not limited to a standard rectangle. That is, the "elongated strip” here includes not only a basic rectangular shape, but also a shape similar to a rectangle in consideration of process conditions. For example, the corners of a rectangle are curved, that is, the corners are smooth.
  • the display panel 100 further includes a first planar layer 30 , and the first planar layer 30 is in contact with a surface of the first electrode layer 20 close to the substrate 10 .
  • the first flat layer 30 is provided with overlapping holes 301 , each first connecting strip 221 extends into a corresponding overlapping hole 301 , and each second connecting strip 222 extends into a corresponding overlapping hole 301 .
  • the minimum distance between the orthographic projection of the boundary of the overlapping hole 301 on the substrate 10 and the orthographic projection of the boundary of the first light-transmitting hole 40 on the substrate 10 is greater than or equal to the second preset value, so that the electrode block 210 (See FIG. 4 )
  • the portion exposed by the first light-transmitting hole 40 is at a greater distance from the overlapping hole 301, so that the portion of the electrode block 210 exposed by the first light-transmitting hole 40 has a higher flatness, thereby improving the flatness of the light-emitting device 2 and making the display brightness of the display panel 100 more uniform.
  • the second preset value may be 8.5 ⁇ m to 11.5 ⁇ m.
  • the second preset value is any one of 8.5 ⁇ m, 9 ⁇ m, 9.5 ⁇ m, 10 ⁇ m, 10.5 ⁇ m, 11 ⁇ m and 11.5 ⁇ m.
  • the display panel 100 further includes at least one conductive layer 50 .
  • the at least one conductive layer 50 is disposed between the substrate 10 and the first electrode layer 20 .
  • the at least one conductive layer 50 includes a plurality of first power signal lines VL extending substantially along the second direction Y.
  • the first power signal lines VL are configured to transmit a first power voltage signal Vdd.
  • the orthographic projection of at least one first electrode block 211 on the substrate 10 overlaps with the orthographic projection of at least one first power signal line VL on the substrate 10, and the area where the orthographic projections of the first electrode block 211 and the first power signal line VL on the substrate 10 overlap is symmetrical relative to the midline of the first electrode block 211 along the second direction Y.
  • the portion of the first power signal line VL directly under the first electrode block 211 is symmetrical with respect to the midline of the first electrode block 211 along the second direction Y. This balances the heights on both sides of the midline of the first electrode block 211 along the second direction Y, thereby increasing the flatness of the first electrode block 211 and improving the display effect.
  • the plurality of first power signal lines VL include a plurality of first power signal line groups VL10 , and each first power signal line group VL10 includes two first power signal lines VL disposed in parallel.
  • the orthographic projections of a column of first electrode blocks 211 arranged along the second direction Y on the substrate 10 overlap with the orthographic projections of two first power signal lines VL in a first power signal line group VL10 on the substrate 10 (see Figure 3A), and the two first power signal lines VL in the first power signal line group VL10 are symmetrical with respect to the midline of the column of first electrode blocks 211 along the second direction Y.
  • the orthographic projection of a column of first electrode blocks 211 arranged along the second direction Y on the substrate 10 overlaps with the orthographic projection of a first power signal line VL on the substrate 10 (see FIG. 3A ), and the first power signal line VL is symmetrical relative to the midline of the column of first electrode blocks 211 along the second direction Y.
  • This arrangement is beneficial to improving the regularity of the arrangement of the first power signal line VL and increasing The cross-sectional area of the first power signal line VL is increased to reduce the resistance.
  • the orthographic projection of at least one second electrode block 212 on the substrate 10 overlaps with the orthographic projection of at least one first power signal line VL1 on the substrate 10, and the area where the orthographic projections of the second electrode block 212 and the first power signal line VL1 on the substrate 10 overlap is symmetrical relative to the midline of the second electrode block 212 along the second direction Y.
  • the portion of the first power signal line VL directly below the second electrode block 212 is symmetrical with respect to the midline of the first electrode block 211 along the second direction Y. This can balance the heights on both sides of the midline of the first electrode block 211 along the second direction Y, thereby increasing the flatness of the first electrode block 211 and improving the display effect.
  • the plurality of first power signal lines VL include a plurality of first power signal line groups VL10 , and each first power signal line group VL10 includes two first power signal lines VL disposed in parallel.
  • the orthographic projections of a column of second electrode blocks 212 arranged along the second direction Y on the substrate 10 overlap with the orthographic projections of two adjacent first power signal lines VL in two adjacent first power signal line groups VL10 on the substrate 10 (see Figure 3A), and the two adjacent first power signal lines VL are symmetrical with respect to the midline of the column of second electrode blocks 212 along the second direction Y.
  • the orthographic projections of a column of second electrode blocks 212 arranged along the second direction Y on the substrate 10 overlap with the orthographic projections of two adjacent first power signal lines VL on the substrate 10 (see FIG. 3A ), and the two adjacent first power signal lines VL are symmetrical relative to the midline of the column of second electrode blocks 212 along the second direction Y.
  • Arranging in this way is beneficial to improving the regularity of the arrangement of the first power signal line VL, increasing the cross-sectional area of the first power signal line VL, and reducing the resistance.
  • the electrode block 210 is electrically connected to the pixel circuit 3 via the connecting bar 220 , that is, the connecting bar 220 cannot be short-circuited with other signal lines. Based on this, the first power signal line VL should avoid the connecting bar 220 .
  • the first power signal line VL includes a first routing segment VL1 and a second routing segment VL2 .
  • the orthographic projection of the first wiring segment VL1 on the substrate 10 is located within the orthographic projection of the first electrode block 211 on the substrate 10 .
  • the first electrode blocks 211 are located between two adjacent first electrode blocks 211 in the second direction Y.
  • the distance between the boundary of the first wiring segment VL1 and the boundary of the first electrode block 211 is greater than or equal to 2.5 ⁇ m.
  • the orthographic projection of the second wiring segment VL2 on the substrate 10 partially overlaps with the orthographic projection of the nearest column of second electrode blocks 212 on the substrate 10 .
  • the second line segment VL2 includes a main portion VL21 and a supporting portion VL22.
  • the two ends of the main body VL21 are electrically connected to the first wiring segment VL1, and the support part VL22 is located on the side of the midline of the nearest column of second electrode blocks 212 along the second direction Y close to the main body VL21, so as to increase the orthographic projection of the second wiring segment VL2 on the substrate 10 (see Figure 3A), and the overlapping area with the orthographic projection of the second electrode block 212 on the substrate 10 (see Figure 3A), thereby further improving the flatness of the second electrode block 212.
  • the orthographic projection of the second wiring segment VL2 on the substrate 10 partially overlaps with the orthographic projections of two adjacent columns of second electrode blocks 212 on the substrate 10 .
  • the second line segment VL2 includes a main portion VL21 and a support portion VL22.
  • the two ends of the main body VL21 are electrically connected to the first wiring segment VL1, and the support part VL22 is located on the opposite sides of the main body VL21 to increase the orthographic projection of the second wiring segment VL2 on the substrate 10 (see Figure 3A), and the overlapping area with the orthographic projection of the second electrode block 212 on the substrate 10 (see Figure 3A), thereby further improving the flatness of the second electrode block 212.
  • the at least one conductive layer 50 further includes a conductive layer substantially along the first A plurality of data lines DL extend in a direction Y.
  • the data lines DL are configured to transmit data signals Data.
  • the orthographic projection of at least one second electrode block 212 on the substrate 10 overlaps with the orthographic projection of at least one data line DL on the substrate 10, and the area where the orthographic projections of the second electrode block 212 and the data line DL on the substrate 10 overlap is symmetrical relative to the midline of the second electrode block 212 along the second direction Y.
  • the portion of the data line DL directly under the second electrode block 212 is symmetrical with respect to the midline of the second electrode block 212 along the second direction Y. This can balance the heights on both sides of the midline of the second electrode block 212 along the second direction Y, thereby increasing the flatness of the second electrode block 212 and improving the display effect.
  • the plurality of data lines DL include a plurality of data line groups DL10 , and each data line group DL10 includes two data lines DL arranged in parallel.
  • the display panel 100 further includes a functional device, which needs to collect ambient light and is integrated on the non-light-emitting side of the display panel 100.
  • the functional device may include other functional components such as a fingerprint recognition unit and a photosensitive device.
  • the above-mentioned light-emitting limiting layer 4 also has a plurality of second light-transmitting holes 44 , and the orthographic projection of each second light-transmitting hole 44 on the substrate 10 (see FIG. 3A ) is located between the orthographic projections of the second electrode blocks 212 adjacent along the second direction Y on the substrate 10 (see FIG. 3A ), so that the functional device can collect external ambient light through the second light-transmitting hole 44 .
  • the light-emitting defining layer 4 includes a pixel defining layer 70 , the pixel defining layer 70 is provided with a plurality of second openings 72 , and the second light-transmitting hole 44 includes a first opening 72 on the pixel defining layer 70 , and the first opening 72 defines a light-transmitting area of the second light-transmitting hole 44 .
  • the light-emitting defining layer 4 includes a black matrix 132 , the black matrix 132 is provided with a plurality of fourth openings 135 , the second light-transmitting hole 44 includes the fourth opening 135 , and the fourth opening 135 defines a light-transmitting area of the second light-transmitting hole 44 .
  • the light-emitting defining layer 4 includes a pixel defining layer 70 and a black matrix 132.
  • the pixel defining layer 70 is provided with a plurality of second openings 72
  • the black matrix 132 is provided with a plurality of fourth openings 135
  • the second light-transmitting hole 44 includes the second openings 72 and the fourth openings 135.
  • the first openings 72 and the fourth openings 135 jointly define the light-transmitting area of the second light-transmitting hole 44.
  • the outer contour of the fourth opening 135 of the black matrix 132 is The shape may be the same as the outer contour of the second opening 72 of the pixel defining layer 70 .
  • the size of the fourth opening 135 of the black matrix 132 may be larger than the size of the second opening 72 of the pixel defining layer 70 , or may be smaller than the size of the second opening 72 of the pixel defining layer 70 .
  • the size of the fourth opening 135 of the black matrix 132 is larger than the size of the second opening 72 of the pixel defining layer 70, and the distance between the boundary of the orthographic projection of the fourth opening 135 on the substrate 10 and the boundary of the orthographic projection of the second opening 72 on the substrate 10 is 2 ⁇ m to 6 ⁇ m.
  • the data line DL should be arranged to avoid the second light-transmitting hole 44 .
  • the data line DL includes a third routing segment DL1 and a fourth routing segment DL2 .
  • the orthographic projection of the third line segment DL1 on the substrate 10 is located within the orthographic projection of the second electrode block 212 on the substrate 10.
  • the fourth line segment DL2 is located between two second electrode blocks 212 adjacent in the second direction Y.
  • the orthographic projection of each second light-transmitting hole 44 on the substrate 10 is located between the orthographic projections of the fourth routing segments DL2 of two data lines DL in a data line group DL10 on the substrate 10, so as to avoid the data lines DL blocking the second light-transmitting holes 44, thereby affecting the photosensitivity of the functional device.
  • two parallel fourth line segments DL2 in one data line group DL10 are bent in directions away from each other, so as to increase the area of the second light-transmitting hole 44 .
  • first power signal line VL and the data line DL can be arranged in the same layer or in different layers.
  • the first power signal line VL and the data line DL are arranged in different layers, and the at least one conductive layer, the first power signal line VL and the data line DL mentioned above are exemplarily introduced in combination with the film layer structure of the display panel 100.
  • the display panel 100 sequentially includes a semiconductor layer ACT, a first gate conductive layer GT1 , a second gate conductive layer GT2 , a first source and drain conductive layer SD1 , a second source and drain conductive layer SD2 , a first planarizing layer 30 , and a first electrode layer 20 .
  • an insulating film layer is disposed between every two adjacent layers.
  • the display panel 100 further includes a first gate insulating layer GI1 , a second gate insulating layer GI2 , an interlayer insulating layer ILD, and a second planarization layer 60 .
  • the first gate insulating layer GI1 is disposed between the semiconductor layer ACT and the first gate conductive layer GT1.
  • the second gate insulating layer GI2 is disposed between the first gate conductive layer GT1 and the second gate conductive layer GT2.
  • the interlayer insulating layer ILD is disposed between the second gate conductive layer GT2 and the first source and drain conductive layer SD1.
  • the layer 60 is disposed between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 .
  • the at least one conductive layer 50 includes at least one of a first gate conductive layer GT1 , a second gate conductive layer GT2 , a first source-drain conductive layer SD1 , and a second source-drain conductive layer SD2 .
  • the at least one conductive layer 50 includes a first gate conductive layer GT1, a second gate conductive layer GT2, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2.
  • a plurality of data lines DL may be located in the first source-drain conductive layer SD1; and/or a plurality of first power signal lines VL may be located in the second source-drain conductive layer SD2.
  • the display panel 100 further includes a third source-drain conductive layer, and the third source-drain conductive layer is located between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 .
  • the at least one conductive layer 50 includes at least one of a first gate conductive layer GT1 , a second gate conductive layer GT2 , a first source-drain conductive layer SD1 , a third source-drain conductive layer, and a second source-drain conductive layer SD2 .
  • the at least one conductive layer 50 includes a first gate conductive layer GT1, a second gate conductive layer GT2, a first source-drain conductive layer SD1, a third source-drain conductive layer SD3, and a second source-drain conductive layer SD2.
  • a plurality of data lines DL may be located in the first source-drain conductive layer SD1 and/or the third source-drain conductive layer SD3; and/or a plurality of first power signal lines VL may be located in the second source-drain conductive layer SD2.
  • the display panel 100 further includes a color film 80 , and the color film 80 is disposed on a side of the light-emitting defining layer 4 away from the substrate 10 .
  • the color filter 80 includes a plurality of filter sections 810, each filter section 810 corresponds to a first light-transmitting hole 40 of the light-emitting defining layer 4, and the orthographic projection of each filter section 810 on the substrate 10 covers the orthographic projection of the corresponding first light-transmitting hole 40 on the substrate 10 (see FIG3A ). Furthermore, each filter section 810 is configured to transmit light of one color.
  • each filter portion 810 on the substrate 10 covers the third opening 134 corresponding to the black matrix 132, and the filter portion 81 partially overlaps the black matrix 132.
  • the distance between the boundaries of the third opening 134 corresponding to the boundaries of the filter portion 81 is less than or equal to 5 ⁇ m.
  • the material of the filter unit 810 includes organic materials.
  • the material of the filter unit 810 includes at least one of polymethyl methacrylate, general polymers of polystyrene, polymer derivatives with phenol groups, acryl polymers, imide polymers, aromatic ether polymers, amide polymers, fluorine polymers, paraxylene polymers and vinyl alcohol polymers.
  • the plurality of sub-pixels P include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color.
  • the first color, the second color and the third color are three primary colors.
  • the multiple filter sections 810 may include a first sub-filter section 811 transmitting light of a first color, a second sub-filter section 812 transmitting light of a second color, and a third sub-filter section 813 transmitting light of a third color.
  • the light emitted by the light-emitting device 2 is irradiated on the corresponding first sub-filter portion 811 to emit light of the first color; is irradiated on the corresponding second sub-filter portion 812 to emit light of the second color; and is irradiated on the corresponding third sub-filter portion 813 to emit light of the third color, so as to achieve color display.
  • the above-mentioned light emitting device 2 can be configured to emit white light or can be configured to emit colored light, which is not specifically limited in the embodiments of the present disclosure.
  • the plurality of filter portions 810 of the color filter 80 may include a plurality of first filter portions 814 and a plurality of second filter portions 815 .
  • the area of the first filter portion 814 is greater than that of the second filter portion 815 .
  • the orthographic projection of the boundary of each first electrode block 211 on the substrate 10 is located within the orthographic projection of the boundary of a first filter portion 814 on the substrate 10 (see Fig. 3A).
  • the orthographic projection of the boundary of each second electrode block 212 on the substrate 10 is located within the orthographic projection of the boundary of a second filter portion 815 on the substrate 10 (see Fig. 3A).
  • the color filter 80 provided in the embodiment of the present disclosure may include a first filter portion 814 with a larger area and a second filter portion 815 with a smaller area.
  • the plurality of filter portions 810 are set to have only two different areas, which can adapt to at least three sub-pixels P with different areas of the effective light-emitting area, thereby reducing the process difficulty of patterning the color filter 80, thereby reducing the preparation cost of the plurality of filter portions 810 formed.
  • first filter portion 814 and the second filter portion 815 can be adjusted accordingly to adapt to different types of multiple light-emitting defining layers 4, thereby further reducing the preparation cost of producing the display device 1000 corresponding to different light-emitting defining layers 4.
  • the outer contour of the first filter 814 may be substantially the same as that of the first electrode block 211 .
  • the outer contour of the second filter 815 may be substantially the same as that of the second electrode block 212 .
  • the orthographic projections of the first electrode block 211 and the second electrode block 212 on the substrate 10 are both approximately regular octagons.
  • the orthographic projections of the first filter portion 814 and the second filter portion 815 on the substrate 10 are both approximately regular octagons.
  • the orthographic projections of the first filter section 814 and the second filter section 815 on the substrate 10 are It may also be substantially circular.
  • the distance between any adjacent first filter portions 814 and second filter portions 815 is substantially equal to the third preset value.
  • the third preset value can be set according to the process accuracy.
  • the third preset value is 3.5 ⁇ m to 6.5 ⁇ m.
  • the third preset value is any one of 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m and 6.5 ⁇ m.
  • the area utilization rate of the first filter part 814 and the second filter part 815 is high, so that the area of the first filter part 814 and the second filter part 815 can be set larger, so that the first light-transmitting holes 40 with the smallest area of various light-emitting limiting layers 4 can be completely blocked by the first filter part 814 for filtering, and other first light-transmitting holes 40 with larger areas can be completely blocked by the second filter part 815 for filtering, thereby improving the versatility of the color film 80, so that the display devices 1000 corresponding to different light-emitting limiting layers 4 can adopt the above-mentioned color film 80, thereby reducing the preparation cost of producing a variety of display devices 1000 corresponding to different light-emitting limiting layers 4.

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Abstract

一种显示面板（100），包括衬底（10）、第一电极层（20）和发光限定层（4）。第一电极层（20）设置于衬底（10）的一侧。第一电极层（20）包括多个第一电极块（211）和多个第二电极块（212），第一电极块（211）的面积大于第二电极块（212）的面积。多个第一电极块（211）阵列排布为多行多列，每行包括沿第一方向（X）排列的多个第一电极块（211），每列包括沿第二方向（Y）排列的多个第一电极块（211），第一方向（X）和第二方向（Y）大致垂直。每个第二电极块（212）位于相邻排布的两行两列的四个第一电极块（211）之间。发光限定层（4）设置于第一电极层（20）远离衬底（10）的一侧。发光限定层（4）具有多个第一透光孔（40），每个第一电极块（211）的至少部分区域被一个第一透光孔（40）暴露，且每个第二电极块（212）的至少部分区域被一个第一透光孔（40）暴露。至少一个第一透光孔（40）的至少部分边界为曲线。

Description

显示面板及显示装置
本申请要求于2022年07月22日提交的、申请号为202210870995.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(Organic Light Emitting Diode，简称：OLED)由于具有自发光、低功耗、宽视角、响应速度快、高对比度以及柔性显示等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。
公开内容
一方面，提供一种显示面板。所述显示面板包括衬底、第一电极层和发光限定层。所述第一电极层设置于所述衬底的一侧。所述第一电极层包括多个第一电极块和多个第二电极块，所述第一电极块的面积大于所述第二电极块的面积。所述多个第一电极块阵列排布为多行多列，每行包括沿第一方向排列的多个第一电极块，每列包括沿第二方向排列的多个第一电极块，所述第一方向和所述第二方向大致垂直。每个第二电极块位于相邻排布的两行两列的四个第一电极块之间。
所述发光限定层设置于所述第一电极层远离所述衬底的一侧。所述发光限定层具有多个第一透光孔，每个第一电极块的至少部分区域被一个第一透光孔暴露，且每个第二电极块的至少部分区域被一个第一透光孔暴露。至少一个所述第一透光孔的至少部分边界为曲线。
在一些实施例中，所述多个第一透光孔包括多个第一子透光孔、多个第二子透光孔和多个第三子透光孔，所述第一子透光孔和所述第三子透光孔分别对应暴露一个第一电极块的至少部分区域，所述第二子透光孔对应暴露一个第二电极块的至少部分区域。沿所述第一方向，多个第一子透光孔和多个第三子透光孔交替排列；沿所述第二方向，多个第一子透光孔和多个第三子透光孔交替排列。相邻的第一子透光孔和第三子透光孔的中心的连线为第一连线，所述相邻的第一子透光孔和第三子透光孔对应的两个第一电极块的中心的连线为第二连线；至少存在一条第一连线与对应的第二连线不平行。
在一些实施例中，相邻排布的三行三列的九个第一电极块所对应的九个第一透光孔中，位于四角的四个第一透光孔的中心连线围成虚拟四边形。所述虚拟四边形具有沿所述第一方向延伸的第一中线和沿所述第二方向延伸的第二中线；所述九个第一透光孔关于所述第一中线和/或所述第二中线对称。
在一些实施例中，所述第一子透光孔和所述第三子透光孔中的一者位于所述虚拟四边形的中心和四个角位置处；另一者位于所述虚拟四边形的四条边上。位于所述虚拟四边形的中心和四个角位置处的第一透光孔为设定透光孔，位于所述虚拟四边形的四条边上的第一透光孔为非设定透光孔。设定透光孔的发光中心与对应的第一电极块的中心大致重合，第二子透光孔的发光中心与对应的第二电极块的中心大致重合。
在所述第一方向上相对的两个非设定透光孔中，一个非设定透光孔的中心位于对应的第一电极块的中心的第一侧，另一个非设定透光孔的中心位于对应的第一电极块的中心的第二侧。在所述第二方向上相对的两个非设定透光孔中，一个非设定透光孔的中心位于对应的第一电极块的中心的第三侧，另一个非设定透光孔的中心位于对应的第一电极块的中心的第四侧。所述第一侧和所述第二侧为所述第一电极块的中心的相对的两侧，第三侧和第四侧为所述第一电极块的中心相对的另外两侧。
在一些实施例中，所述多个第一透光孔包括多个第一子透光孔、多个第二子透光孔和多个第三子透光孔。所述第一子透光孔的面积，大于所述第三子透光孔的面积；所述第三子透光孔的面积，大于所述第二子透光孔的面积。所述第一子透光孔和所述第三子透光孔分别对应暴露一个第一电极块的至少部分区域，所述第二子透光孔对应暴露一个第二电极块的至少部分区域，且所述第一子透光孔、所述第二子透光孔和所述第三子透光孔中的至少一者的至少部分边界为曲线。
在一些实施例中，至少一个第一透光孔的外轮廓包括第一曲边和第二曲边，所述第一曲边的两端和所述第二曲边的两端分别相连，所述第一曲边和所述第二曲边的两个连接点为第一连接点和第二连接点。所述第一连接点和所述第二连接点的连线为第一线段，所述第一线段的长度为所述第一透光孔的最大尺寸，且将所述第一透光孔划分为包括所述第一曲边的第一子部分和包括所述第二曲边的第二子部分。所述第一子部分的面积大于所述第二子部分的面积。
在一些实施例中，所述第一曲边与所述第一线段围成半圆，所述第二曲边与所述第一线段围成半椭圆。
在一些实施例中，所述多个第一透光孔包括多个第一子透光孔和多个第三子透光孔，所述第一子透光孔和/或所述第三子透光孔的外轮廓包括所述第一曲边和所述第二曲边。
在一些实施例中，所述多个第一透光孔包括第二子透光孔，所述第二子透光孔的外轮廓的形状大致为圆形或椭圆形。
在一些实施例中，至少一个第一透光孔的外轮廓包括第一直边、第二直边和第三曲边。所述第一直边和所述第二直边相连形成折线边，所述第三曲边的两端与所述折线边的两端分别相连，所述第三曲边的两端与所述折线边相连的两个连接点为第三连接点和第四连接点。所述第三连接点和所述第四连接点的连线为第二线段，所述第二线段的长度为所述第一透光孔的最大尺寸，且将所述第一透光孔划分为包括所述第一直边和所述第二直边的第三子部分和包括所述第三曲边的第四子部分。所述第三子部分的面积大于所述第四子部分的面积。
在一些实施例中，所述第三曲边包括依次连接的第一子直线段、第一子曲线段和第二子直线段，所述第一子直线段与所述第一直边连接，所述第二子直线段与所述第二直边连接。所述第一子直线段与所述第二直边大致平行，所述第二子直线段与所述第一直边大致平行。
在一些实施例中，所述多个第一透光孔包括多个第一子透光孔和多个第三子透光孔，所述第一子透光孔和/或所述第三子透光孔的外轮廓包括所述第一直边、所述第二直边和所述第三曲边。
在一些实施例中，所述多个第一透光孔包括第二子透光孔，所述第二子透光孔的外轮廓的形状大致为菱形。
在一些实施例中，所述第一透光孔的外轮廓的形状均大致为圆形或椭圆形。
在一些实施例中，所述发光限定层还具有多个第二透光孔，每个第二透光孔在所述衬底上的正投影，位于沿所述第二方向相邻的第二电极块在所述衬底上的正投影之间。
在一些实施例中，所述第一电极块和所述第二电极块的外轮廓的形状均大致为多边形。任意相邻的第一电极块和第二电极块的边界相对且大致平行，且相邻的第一电极块和第二电极块之间的距离大致等于第一预设值，所述第一预设值为所述第一电极块和所述第二电极块断开的工艺极限值。
在一些实施例中，所述第一电极块和所述第二电极块在所述衬底上的正投影均大致为正八边形。
在一些实施例中，所述第一电极层还包括多个第一连接条和多个第二连接条，每个第一连接条与一个第一电极块电连接，每个第二连接条与一个第二电极块电连接。沿所述第二方向，每相邻的两个第一电极块之间设有一个所述第一连接条和一个所述第二连接条。
在一些实施例中，所述显示面板还包括第一平坦层，所述第一平坦层与所述第一电极层靠近所述衬底的表面接触。所述第一平坦层上设有搭接孔，每个第一连接条对应延伸至一个搭接孔内，每个第二连接条对应延伸至一个搭接孔内。其中，所述搭接孔的边界在所述衬底上的正投影，与所述第一透光孔的边界在所述衬底上的正投影的最小距离大于或等于第二预设值。
在一些实施例中，所述显示面板还包括至少一层导电层，所述至少一层导电层设置于所述衬底和所述第一电极层之间。所述至少一层导电层包括大致沿所述第二方向延伸的多条第一电源信号线。至少一个第一电极块在所述衬底上的正投影，与至少一条第一电源信号线在所述衬底上的正投影交叠，且所述第一电极块和所述第一电源信号线在所述衬底上的正投影交叠的区域，相对于所述第一电极块沿所述第二方向的中线对称。
在一些实施例中，所述多条第一电源信号线包括多个第一电源信号线组，每个第一电源信号线组包括两条并列设置的第一电源信号线。沿所述第二方向排列的一列第一电极块，与一个第一电源信号线组中的两条第一电源信号线在所述衬底上的正投影均交叠，且所述第一电源信号线组中的两条第一电源信号线，相对于所述一列第一电极块沿所述第二方向的中线对称。
在一些实施例中，所述第一电极层还包括多个第一连接条和多个第二连接条。所述第一电源信号线包括第一走线段和第二走线段，所述第一走线段在所述衬底上的正投影，位于所述第一电极块在所述衬底上的正投影内。所述第二走线段位于在所述第二方向上相邻的两个第一电极块之间。一个第一连接条和一个第二连接条在所述衬底上的正投影，位于一个第一电源信号线组中的两条第一电源信号线的第二走线段在所述衬底上的正投影之间。
在一些实施例中，至少一层导电层还包括大致沿所述第二方向延伸的多条数据线。至少一个第二电极块在所述衬底上的正投影，与至少一条数据线在所述衬底上的正投影至少部分交叠，且所述第二电极块和所述数据线在所述衬底上的正投影交叠的区域，相对于所述第二电极块沿所述第二方向的中线对称。
在一些实施例中，所述多条数据线包括多个数据线组，每个数据线组包括两条并列设置的数据线。沿所述第二方向排列的一列第二电极块在所述衬底上的正投影，与一个数据线组中的两条数据线在所述衬底上的正投影均至少部分交叠，且所述数据线组中的两条数据线，相对于所述一列第二电极块沿所述第二方向的中线对称。
在一些实施例中，所述发光限定层还具有多个第二透光孔。所述数据线包括第三走线段和第四走线段。所述第三走线段在所述衬底上的正投影，位于所述第二电极块在所述衬底上的正投影内。所述第四走线段位于在所述第二方向上相邻的两个第二电极块之间。每个第二透光孔在所述衬底上的正投影，位于一个数据线组中的两条数据线的第四走线段在所述衬底上的正投影之间。
在一些实施例中，沿垂直与所述衬底，且由所述衬底指向所述第一电极层的方向，所述至少一层导电层包括依次设置的第一栅导电层、第二栅导电层、第一源漏导电层和第二源漏导电层。所述第一电源信号线位于所述第二源漏导电层；和/或，所述多条数据线位于所述第一源漏导电层。
在一些实施例中，所述发光限定层包括像素界定层，所述像素界定层设有多个第一开口，所述第一透光孔包括所述第一开口。
在一些实施例中，所述发光限定层还具有多个第二透光孔。所述像素界定层设有多个第二开口，所述第二透光孔包括所述第二开口。
在一些实施例中，所述发光限定层包括黑矩阵，所述黑矩阵设有多个第三开口，所述第一透光孔包括所述第三开口。
在一些实施例中，所述发光限定层还具有多个第二透光孔；所述黑矩阵设有多个第四开口，所述第二透光孔包括所述第四开口。
在一些实施例中，所述发光限定层包括像素界定层和黑矩阵，所述第一透光孔包括所述像素界定层的第一开口和所述黑矩阵的第三开口，所述第一开口的外轮廓的形状与所述第三开口的外轮廓的形状相同。
在一些实施例中，所述第二透光孔包括所述像素界定层的第二开口和所述黑矩阵的第四开口，所述第二开口的外轮廓的形状与所述第四开口的外轮廓的形状相同。
在一些实施例中，所述显示面板还包括彩膜，所述彩膜设置于所述发光限定层远离所述衬底的一侧。所述彩膜包括多个第一滤光部和多个第二滤光部，所述第一滤光部的面积大于所述第二滤光部的面积。每个第一电极块的边界在所述衬底上的正投影，位于一个第一滤光部的边界在所述衬底上的正投影内。每个第二电极块的边界在所述衬底上的正投影，位于一个第二滤光部的边界在所述衬底上的正投影内。
在一些实施例中，所述第一滤光部的外轮廓的形状与所述第一电极块的外轮廓的形状大致相同。所述第二滤光部的外轮廓的形状与所述第二电极块的外轮廓的形状大致相同。
另一方面，提供一种显示装置。所述显示装置包括如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示装置的爆炸图；
图3A为根据一些实施例的一种显示面板的剖视图；
图3B为根据一些实施例的另一种显示面板的剖视图；
图4为根据一些实施例的一种第一电极的结构图；
图5为根据一些实施例的另一种第一电极的结构图；
图6为根据一些实施例的第一电极层的俯视图；
图7A为根据一些实施例的发光限定层的一种第一透光孔的结构图；
图7B为根据一些实施例的一种发光限定层的结构图；
图7C为根据一些实施例的另一种发光限定层的结构图；
图7D为图7B中的三行三列的第一透光孔及第一电极的结构图；
图7E为图7C中的三行三列的第一透光孔及第一电极的结构图；
图8A为根据一些实施例的像素界定层的另一种第一透光孔的结构图；
图8B为根据一些实施例的又一种发光限定层的结构图；
图8C为根据一些实施例的再一种发光限定层的结构图；
图8D为图8B中的三行三列的第一透光孔及第一电极的结构图；
图8E为图8C中的三行三列的第一透光孔及第一电极的结构图；
图9A为根据一些实施例的像素界定层的又一种第一透光孔的结构图；
图9B为根据一些实施例的又一种发光限定层的结构图；
图9C为根据一些实施例的又一种发光限定层的结构图；
图9D为图9B中的三行三列的第一透光孔及第一电极的结构图；
图9E为图9C中的三行三列的第一透光孔及第一电极的结构图；
图10A为根据一些实施例的第一电源信号线和数据线的走线图；
图10B为根据另一些实施例的第一电源信号线和数据线的走线图；
图11为根据一些实施例的第一电源信号线和数据线与第一电极层的俯视图；
图12A为根据一些实施例的一种发光限定层的结构图；
图12B为根据一些实施例的另一种发光限定层的结构图；
图12C为根据一些实施例的再一种发光限定层的结构图；
图12D为根据一些实施例的又一种发光限定层的结构图；
图12E为根据一些实施例的又一种发光限定层的结构图；
图12F为根据一些实施例的又一种发光限定层的结构图；
图13为根据一些实施例的彩膜的俯视图；
图14为根据一些实施例的第一电极层、像素界定层、黑矩阵及彩膜堆叠的俯视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”、“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。又例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件彼此间有直接电接触或间接电连接。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的像素电路中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称：TFT)、场效应晶体管(Metal Oxide Semiconductor，简称：MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
如图1所示，本公开的一些实施例提供一种显示装置1000，该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(Personal Digital Assistant；简称：PDA)、导航仪、可穿戴设备、虚拟现实(Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，参阅图1，显示装置1000包括显示面板100。
示例性地，如图1所示，上述显示装置1000还可以包括壳体200、电路板300(参见图2)以及其他电子配件。其中，显示面板100和电路板300(参见图2)可以设置在该壳体200内。
其中，上述显示面板100的类型包括多种，可以根据实际需要选择设置。
示例性地，上述显示面板100可以为：有机发光二极管(Organic Light Emitting Diode，简称：OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diode，简称：QLED)显示面板等，本公开实施例在此不作具体限定。
下面以上述显示面板100为OLED显示面板为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，参阅图2，显示面板100包括显示基板11和用于封装显示基板11的封装层12。
其中，如图2和图3A所示，显示基板11具有相对设置的出光侧和非出光侧，封装层12设置于显示基板11的出光侧，即图3A中的上侧。此处，封装层12可以为封装薄膜，也可以为封装基板。
参阅图2，显示面板100具有显示区A，以及设置在显示区A的至少一侧的周边区B。图2中以周边区B围绕显示区A设置为例进行示意。
其中，显示区A为显示图像的区域，被配置为设置多个子像素P。周边区B为不显示图像的区域，周边区B被配置为设置显示驱动电路，例如，栅极驱动电路和源极驱动电路。
示例性地，参阅图2和图3A，显示面板100包括衬底10和设置在衬底10的一侧，且位于显示区A的多个子像素P。
上述衬底10的类型包括多种，可以根据实际需要选择设置。
示例性地，衬底10可以为刚性衬底。例如，该刚性衬底可以为玻璃衬底或聚甲基丙烯酸甲酯(Polymethyl Methacrylate，简称：PMMA)衬底等。
示例性地，衬底10可以为柔性衬底。例如，该柔性衬底可以为聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，简称：PET)衬底、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate Two Formic Acid Glycol Ester，简称：PEN)衬底或聚酰亚胺(Polyimide，简称：PI)衬底等。
其中，参阅图3A，多个子像素P可以包括发光颜色为第一颜色的第一子像素、发光颜色为第二颜色的第二子像素、以及发光颜色为第三颜色的第三子像素。
这里，第一颜色、第二颜色和第三颜色为三基色，例如，第一颜色为红色，第二颜色为蓝色，第三颜色为绿色。以下以第一颜色为蓝色，第二颜色为绿色，第三颜色为红色为例，对本公实施例进行示例性说明。
应理解，人眼对红光、绿光和蓝光感光的敏感程度不同，即人眼对绿光的感光程度大于对红光的感光程度，对红光的感光程度大于对蓝光的感光程度。
基于此，第一子像素的有效发光区的面积，大于第三子像素的有效发光区的面积；第三子像素的有效发光区的面积，大于第二子像素的有效发光区的面积。这里，有效发光区的描述可以参考下文。
此外，每个子像素P均包括设置于衬底10上的发光器件2和像素电路3。像素电路3包括多个薄膜晶体管31。
如图3A所示，薄膜晶体管31包括有源层311、源极312、漏极313和栅极314，源极312和漏极313分别与有源层311接触。
需要说明的是，上述源极312和漏极313可以互换，即图3A中的312表示漏极，图3A中的313表示源极。
如图3A所示，发光器件2包括第一电极21、发光功能层22以及第二电极23，第一电极21和多个薄膜晶体管31中作为驱动晶体管的薄膜晶体管31的源极312或漏极313电连接，图3A中以第一电极21和薄膜晶体管31的源极312电连接进行示意。
需要说明的是，上述第一电极21为发光器件2的阳极，第二电极23为发光器件2的阴极；或者，第一电极21为发光器件2的阴极，第二电极23为发光器件2的阳极。
在一些实施例中，参阅图4和图5，上述第一电极21包括电极块210和连接条220。
如图3A和图4所示，电极块210被配置为与发光功能层22接触，以形成发光区，即发光区在衬底10上的正投影，位于电极块210在衬底10上的正投影内。
如图3A和图4所示，连接条220被配置为与像素电路3电连接，即连接条220与薄膜晶体管31的源极312或漏极313电连接。
需要说明的是，第一电极21位于第一电极层20，即第一电极层20包括多个电极块210和多个连接条220，多个电极块210和多个连接条220由第一电极层20图案化形成。
在一些实施例中，参阅图2和图3A，上述第二电极23为连续的整层图案，并覆盖整个显示区A。
在一些实施例中，参阅图3A，上述发光功能层22仅包括发光层。在另一些实施例中，上述发光功能层22除包括发光层外，还包括电子传输层(Election Transporting Layer，简称：ETL)、电子注入层(Election Injection Layer，简称：EIL)、空穴传输层(Hole Transporting Layer，简称：HTL)和空穴注入层(Hole Injection Layer，简称：HIL)中的至少一个。
在一些实施例中，如图3A所示，显示面板100还包括像素界定层70，像素界定层70设置于第一电极21远离衬底10的一侧。其中，像素界定层70具有多个第一开口71，发光器件2设置于一个第一开口71中，即发光器件2的发光功能层22在第一开口71内与第一电极21的电极块210电接触。
需要说明的是，为了降低工艺难度，第一电极21的面积大于像素界定层70的第一开口71的面积，以使得像素界定层70的整个第一开口71均为发光区。即，第一电极21、第二电极23以及发光功能层22重叠的部分构成发光区。
此处，在像素界定层70的第一开口71上方无其他遮光膜层遮挡时，有效发光区为第一开口71所限定的区域，即发光区即为有效发光区。
在一些实施例中，如图3A和图3B所示，显示面板100包括降反射膜13，降反射膜13被配置为，降低外界环境光在显示面板100的反射强度。
在一些示例中，参阅图3B，降反射膜13包括偏光片131，偏光片131设置于封装层12远离衬底10的一侧。
在另一些示例中，参阅图3A，降反射膜13包括黑矩阵132和彩膜80。黑矩阵132用于将从不同子像素P发出的光间隔开，并且具有减少外界环境光进入显示面板100内部后产生反射光线的作用。彩膜80可以滤去外界环境光中的大部分波段的光，从而可以降低外界环境光在显示面板100的反射强度。
其中，参阅图3A和图12A，黑矩阵132设置于像素界定层70远离衬底10的一侧。黑矩阵132具有多个第三开口134，一个第三开口134暴露至少部分第一开口71。
需要说明的是，在显示面板100包括黑矩阵132的情况下，有效发光区为第一开口71和第三开口134重合的区域。
这里，参阅图3A和图12A，上述黑矩阵132的第三开口134的外轮廓的形状与像素界定层70的第一开口71的外轮廓的形状可以相同。
此外，黑矩阵132的第三开口134的尺寸可以大于像素界定层70的第一开口71的尺寸，也可以小于像素界定层70的第一开口71的尺寸。
示例性地，如图12A所示，黑矩阵132的第三开口134的尺寸大于像素界定层70的第一开口71的尺寸，且第三开口134在衬底10(参见图3A)上的正投影的边界，与第一开口71在衬底10(参见图3A)上的正投影的边界的距离为2μm～6μm。
相关技术中，第一电极层所包括的第一电极的电极块的形状和面积均根据有效发光区的面积调整，即第一电极的电极块的形状和面积均根据像素界定层的第一开口或黑矩阵的第三开口适应性调整。这样的话，由于不同颜色的子像素的有效发光区的面积不同，因此，针对不同颜色的子像素，第一电极的电极块的面积各不相同，生产成本较高。
此外，在不同的OLED显示装置中，像素界定层的第一开口和黑矩阵的第三开口的形状并不唯一，这样在生产不同的像素界定层或黑矩阵对应的OLED显示装置的过程中，导致第一电极层的通用性较差，生产成本较高。
基于此，本公开的一些实施例提供的显示面板100，参阅图3A和图7B，包括发光限定层4，发光限定层4具有多个第一透光孔40，第一透光孔40在衬底10上的正投影即为有效发光区。
在一些示例中，上述发光限定层4包括像素界定层70，第一透光孔40包括像素界定层70上的第一开口71，有效发光区为第一开口71所限定的区域。
在另一些示例中，上述发光限定层4包括黑矩阵132，第一透光孔40包括第三开口134，有效发光区为第三开口134所限定的区域。
在又一些示例中，上述发光限定层4包括像素界定层70和黑矩阵132。第一透光孔40包括第一开口71和第三开口134，有效发光区为第一开口71和第三开口134重合的区域。
图7A～图9E以发光限定层4包括像素界定层70或黑矩阵132为例进行示意。图12A～图12F以发光限定层4包括像素界定层70和黑矩阵132为例进行示意。
其中，参阅图4和图5，多个第一电极21的多个电极块210包括多个第一电极块211和多个第二电极块212。
如图7B所示，每个第一电极块211的至少部分区域被一个第一透光孔40暴露，且每个第二电极块212的至少部分区域被一个第一透光孔40暴露，以形成有效发光区。
其中，参阅图6，多个第一电极块211阵列排布为多行多列，每行包括沿第一方向X排列的多个第一电极块211，每列包括沿第二方向Y排列的多个第一电极块211，第一方向X和第二方向Y大致垂直。每个第二电极块212位于相邻排布的两行两列的四个第一电极块211之间。
这里，第一电极块211的面积大于第二电极块212的面积，以便于第一电极块211匹配有效发光区的面积较大的子像素P。
示例性地，参见图7A，第一电极块211对应匹配第一子像素和第三子像素。即，所有的第一电极块211中，一些第一电极块211作为第一子像素的发光器件2(参见图3A)的第一电极21(参见图3A)形成有效发光区的部分，另一些第一电极块211作为第三子像素的发光器件2(参见图3A)的第一电极21(参见图3A)形成有效发光区的部分。第二电极块212作为第二子像素的发光器件2(参见图3A)的第一电极21(参见图3A)形成有效发光区的部分。
由上述可知，本公开实施例所提供的第一电极层20，包括面积较大的第一电极块211和面积较小的第二电极块212。其中，第一电极块211可以与有效发光区的面积最大的子像素适配，例如，第一子像素；第二电极块212可以与有效发光区的面积最小的子像素P适配，例如，第二子像素。
在这种情况下，鉴于第一电极块211的面积大于剩余的子像素P的有效发光区的面积，剩余的子像素P(例如第三子像素)的有效发光区均可以形成于第一电极块211上。也就是说，本公开实施例所提供的第一电极层20，仅包括两种电极块210，可以适配至少三种子像素P，这样可以降低第一电极层20图案化的工艺难度，从而降低形成的多个第一电极21的制备成本。
应理解，由于像素界定层70的第一开口71和黑矩阵132的第三开口134的形状并不唯一，因此，发光限定层4的第一透光孔40的形状也并不唯一。这里，第一电极块211和第二电极块212的形状以及面积可以相应的调整，以适配不同类型的多种发光限定层4，从而降低生产不同的发光限定层4对应的显示装置1000的制备成本。
示例性地，参阅图4和图5，第一电极块211和第二电极块212的外轮廓的形状均大致为多边形。
例如，如图4和图5所示，第一电极块211和第二电极块212在衬底10上的正投影均大致为正八边形。当然，该第一电极块211和第二电极块212在衬底10上的正投影还可以为正六边形、正十边形和正十二边形等，本公开实施例在此不作具体限定。
其中，如图6所示，任意相邻的第一电极块211和第二电极块212的边界相对且大致平行，且相邻的第一电极块211和第二电极块212之间的距离大致等于第一预设值。
这里，第一预设值为第一电极块211和第二电极块212断开的工艺极限值，即第一预设值可以根据工艺精度设定，以能够使得同层的第一电极块211和第二电极块212断开为基准。示例性地，第一预设值为3.5μm～6.5μm。例如，第一预设值为3.5μm、4μm、4.5μm、5μm、5.5μm、6μm和6.5μm中的任一者。
在这种情况下，在衬底10的第一方向X和第二方向Y所确定的平面上，第一电极块211和第二电极块212的面积利用率高，可以使得第一电极块211和第二电极块212的面积设置的更大，使得各种发光限定层4的面积最小的第一透光孔40均可以形成于第一电极块211上，其他面积较大的第一透光孔40均可以形成于第二电极块212上，从而提高第一电极层20的通用性，使得不同的发光限定层4对应的显示装置1000均可以采用上述第一电极层20，降低生产不同的发光限定层4对应的多种显示装置1000的制备成本。
在一些实施例中，参阅图6和图7A，上述发光限定层4的至少一个第一透光孔40的至少部分边界为曲线。以这种方式设置，在外界环境光照射在第一电极块211或第二电极块212，并经过发光限定层4的第一透光孔40反射至外界，产生衍射的过程中，外界环境光所产生的衍射在第一透光孔40的曲线边界，能够被均匀的分散，从而改善外界环境光导致的色分离。
此外，在上述多个子像素P包括第一子像素、第二子像素和第三子像素的情况下，如图7B所示，多个第一透光孔40可以包括多个第一子透光孔41、多个第二子透光孔42和多个第三子透光孔43。第一子透光孔41和第三子透光孔43分别对应暴露一个第一电极块211的至少部分区域，第二子透光孔42对应暴露一个第二电极块212的至少部分区域。沿第一方向X，多个第一子透光孔41和多个第三子透光孔43交替排列。沿第二方向Y，多个第一子透光孔41和多个第三子透光孔43交替排列。
其中，第一子透光孔41、第二子透光孔42和第三子透光孔43中的至少一者的至少部分边界为曲线，以使得相同的子像素P(参见图2)的发光中心C(参见图7A)分布相同，使得显示面板100的亮度分布更加均匀，提高显示效果。
需要说明的是，上述第一子透光孔41的面积，大于第三子透光孔43的面积；第三子透光孔43的面积，大于第二子透光孔42的面积。例如，第一子透光孔41对应上述第一子像素，第二子透光孔42对应上述第二子像素，第三子透光孔43对应上述第三子像素。
在一些实施例中，如图7A所示，至少一个第一透光孔40的外轮廓包括第一曲边B1和第二曲边B2。第一曲边B1的两端和第二曲边B2的两端分别相连，第一曲边B1和第二曲边B2的两个连接点为第一连接点和第二连接点。
其中，第一连接点和第二连接点的连线为第一线段M1，第一线段M1的长度为第一透光孔40的最大尺寸，且将第一透光孔40划分为包括第一曲边B1的第一子部分S1和包括第二曲边B2的第二子部分S2。并且，第一子部分S1的面积大于第二子部分S2的面积。此时，该第一透光孔40的发光中心C位于第一子部分S1。
示例性地，如图7A所示，第一曲边B1与第一线段M1围成半圆，第二曲边B2与第一线段M1围成半椭圆。在这种情况下，半圆的面积大于半椭圆的面积，发光中心C位于半圆的圆心远离半椭圆的一侧，即位于半圆内。
这里，在多个第一透光孔40包括多个第一子透光孔41、多个第二子透光孔42和多个第三子透光孔43的情况下，第一子透光孔41和/或第三子透光孔43的外轮廓包括第一曲边B1和第二曲边B2。第二子透光孔42的外轮廓大致为圆形或椭圆形。
需要说明的是，在本文中，“大致为圆形或椭圆形”是指，形状整体上呈圆形或椭圆形，但是并不局限为标准的圆形或椭圆形。即，这里的“圆形或椭圆形”不但包括基本菱形的形状，而且考虑到工艺条件，还包括类似于圆形或椭圆形的形状。例如，圆形或椭圆形局部线段为直线。
在另一些实施例中，如图8A所示，至少一个第一透光孔40的外轮廓包括第一直边D1、第二直边D2和第三曲边B3。第一直边D1和第二直边D2相连形成折线边，第三曲边B3的两端与折线边的两端分别相连，且第三曲边B3的两端与折线边相连的两个连接点为第三连接点和第四连接点。
其中，第三连接点和第四连接点的连线为第二线段M2，第二线段M2的长度为第一透光孔40的最大尺寸，且将第一透光孔40划分为包括第一直边D1和第二直边D2的第三子部分S3和包括第三曲边B3的第四子部分S4。并且，第三子部分S3的面积大于第四子部分S4的面积。此时，该第一透光孔40的发光中心C位于第三子部分S3。
示例性地，如图8A所示，第三曲边B3包括依次连接的第一子直线段B31、第一子曲线段B32和第二子直线段B33，第一子直线段B31与第一直边D1连接，第二子直线段B33与第二直边D2连接。第一子直线段B31与第二直边D2大致平行，第二子直线段B33与第一直边D1大致平行。在这种情况下，结合第二线段M2的长度为第一透光孔40的最大尺寸，第三子部分S3的面积大于第四子部分S4的面积，发光中心C位于第三子部分S3。
这里，在多个第一透光孔40包括多个第一子透光孔41、多个第二子透光孔42和多个第三子透光孔43的情况下，第一子透光孔41和/或第三子透光孔43的外轮廓包括第一直边D1、第二直边D2和第三曲边B3，第二子透光孔42的外轮廓的形状大致为菱形。
需要说明的是，在本文中，“大致为菱形”是指，形状整体上呈菱形，但是并不局限为标准的菱形。即，这里的“菱形”不但包括基本菱形的形状，而且考虑到工艺条件，还包括类似于菱形的形状。例如，菱形的拐角处为弯曲状，即拐角处平滑。
在又一些实施例中，如图9A所示，至少一个第一透光孔40的外轮廓的形状大致为圆形或椭圆形。此时，该第一透光孔40的发光中心C为圆心或椭圆心。图9A中以第一透光孔的外轮廓的形状大致为圆形为例进行示意。
这里，在多个第一透光孔40包括多个第一子透光孔41、多个第二子透光孔42和多个第三子透光孔43的情况下，第一子透光孔41、第二子透光孔42和第三子透光孔43的外轮廓的形状均大致为圆形或椭圆形。
可以理解的是，该显示面板100还可以灵活的调整不同子像素P(参见图2)的发光中心C的位置，进而调整多个子像素P构成的像素单元的实际亮度中心，使得整个显示面板100中各个像素单元的实际亮度中心分布更加均匀。
在一些实施例中，参阅图7D、图8D和图9D，相邻的第一子透光孔41和第三子透光孔43的中心的连线为第一连线L1，相邻的第一子透光孔41和第三子透光孔43对应的两个第一电极块211的中心的连线为第二连线L2，至少存在一条第一连线L1与对应的第二连线L2不平行。
以这种方式设置，可以调整子像素P(参见图2)的发光中心C，进而调整多个子像素P构成的像素单元的实际亮度中心，使得整个显示面板100中各个像素单元的实际亮度中心分布更加均匀。
在此基础上，参阅7D、图8D和图9D，相邻排布的三行三列的九个第一电极块211所对应的九个第一透光孔40中，位于四角的四个第一透光孔40的中心连线围成虚拟四边形，虚拟四边形具有沿第一方向X延伸的第一中线C1和沿第二方向Y延伸的第二中线C2。这里，第一中线C1和第二中线C2均经过九个第一透光孔40中位于中心的第一透光孔40的发光中心C。
其中，九个第一透光孔40关于第一中线C1和/或第二中线C2对称，以避免一个像素单元中的多个子像素P的发光中心C偏移，而导致显示面板100产生色分离的问题，提高显示效果。
在一些示例中，参阅7D、图8D和图9D，虚拟四边形大致为矩形，且矩形的四条边中，两条边与第一方向X大致平行，另外两条边与第二方向Y大致平行。
此时，九个第一透光孔40关于第一中线C1对称，且九个第一透光孔40还关于第二中线C2对称。并且，九个第一透光孔40关于虚拟四边形的中心呈中心对称分布，以避免一个像素单元中的多个子像素P的发光中心C偏移，而导致显示面板100产生色分离的问题，提高显示效果。
在另一些示例中，虚拟四边形大致为等腰梯形，且等腰梯形的顶边和底边与第一方向X大致平行。
此时，九个第一透光孔40关于第二中线C2对称，且九个第一透光孔40中位于等腰梯形的顶边和底边的中间的两个第一透光孔40还关于第一中线C1对称，以避免一个像素单元中的多个子像素P的发光中心C偏移，而导致显示面板100产生色分离的问题，提高显示效果。
在又一些示例中，虚拟四边形大致为等腰梯形，且等腰梯形的顶边和底边与第二方向Y大致平行。
此时，九个第一透光孔40关于第一中线C1对称，且九个第一透光孔40中位于等腰梯形的顶边和底边的中间的两个第一透光孔40还关于第二中线C2对称，以避免一个像素单元中的多个子像素P的发光中心C偏移，而导致显示面板100产生色分离的问题，提高显示效果。
下面以虚拟四边形大致为矩形为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，参阅图7D和图7E，第一子透光孔41和第三子透光孔43中的一者位于虚拟四边形的中心和四个角位置处；另一者位于虚拟四边形的四条边上。位于虚拟四边形的中心和四个角位置处的第一透光孔40为设定透光孔，位于虚拟四边形的四条边上的第一透光孔40为非设定透光孔。
需要说明的是，在一些实施例中，如图7E所示，上述设定透光孔为第一子透光孔41，非设定透光孔为第三子透光孔43。在另一些实施例中，如图7D所示，上述设定透光孔为第三子透光孔43，非设定透光孔为第一子透光孔41。本公开的下文会结合具体实施例进行分别阐述，在此不做赘述。
其中，如图7D和图7E所示，设定透光孔的发光中心C与对应的第一电极块211的中心大致重合，第二子透光孔42的发光中心C与对应的第二电极块212的中心大致重合。
此时，多个设定透光孔和多个第二子透光孔42关于第一中线C1和/或第二中线C对称。
在此基础上，在第一方向X上相对的两个非设定透光孔中，一个非设定透光孔的中心位于对应的第一电极块211的中心的第一侧，另一个非设定透光孔的中心位于对应的第一电极块211的中心的第二侧。
此时，在第一方向X上相对的两个非设定透光孔关于第二中线C2对称。
此外，在第二方向Y上相对的两个非设定透光孔中，一个非设定透光孔的中心位于对应的第一电极块211的中心的第三侧，另一个非设定透光孔的中心位于对应的第一电极块211的中心的第四侧。
此时，在第二方向Y上相对的两个非设定透光孔关于第一中线C1对称。
需要说明的是，第一侧和第二侧为第一电极块211的中心的相对的两侧，第三侧和第四侧为第一电极块211的中心相对的另外两侧。例如，第一侧、第二侧、第三侧和第四侧分别为第一电极块211的中心在第一方向X和第二方向Y上的四侧。
例如，如图7B和图7D所示，第一子透光孔41为非设定透光孔，第三子透光孔43为设定透光孔。
其中，参阅图7A、图7B和图7D，第一子透光孔41外轮廓包括第一曲边B1和第二曲边B2，第一曲边B1与第一线段M1形成半圆，第二曲边B2与第一线段M1形成半椭圆；且第一子透光孔41的半圆的圆心与对应的第一电极块211的中心重合。
此外，第二子透光孔42的外轮廓大致为圆形，且圆心与对应的第二电极块212的中心重合。第三子透光孔43的外轮廓大致为圆形，且圆心与对应的第一电极块211的中心重合。
在一个虚拟四边形中，第一方向X上相对的两侧的两个第一子透光孔41中，一个第一子透光孔41的半圆部分，位于对应的椭圆部分的第二方向Y上的一侧；另一个第一子透光孔41的半圆部分，位于对应的椭圆部分的第二方向Y上的另一侧。第二方向Y上相对的两侧的两个第一子透光孔41中，一个第一子透光孔41的半圆部分，位于对应的椭圆部分的第一方向X上的一侧；另一个第一子透光孔41的半圆部分，位于对应的椭圆部分的第一方向X上的另一侧。
此时，在400PPI(Pixels Per Inch)的显示面板100中，上述第一透光孔40的最小径向尺寸为19μm～21μm，第一透光孔40与电极块210之间的最小距离为5.3μm～7.3μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一透光孔40的最小径向尺寸以及第一透光孔40与电极块210之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的边界与对应的搭接孔301的边界之间的距离为18.38μm～20.38μm，第二子透光孔42的边界与对应的搭接孔301的边界之间的距离为13μm～15μm，第三子透光孔43的边界与对应的搭接孔301的边界之间的距离为21.27μm～23.27μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离并不相同，只要使得第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离，大于或等于第二预设值即可，搭接孔301及第二预设值的描述可以参考下文，本公开实施例在此不作赘述。
此外，上述第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离为20μm～22μm，第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离为22.83μm～24.83μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离，以及第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的开口率为5.24％～7.24％，第二子透光孔42的开口率为2.79％～4.79％，第三透光孔43的开口率为3.46％～5.46％。在一个像素单元包括一个第一子透光孔41、两个第二子透光孔42和一个第三子透光孔43的情况下，子像素P的总开口率为14.28％～22.28％。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的开口率并不相同，具体根据显示面板100的参数需求进行设定。
又例如，如图7C和图7E所示，第一子透光孔41为设定透光孔，第三子透光孔43为非设定透光孔。
其中，参阅图7A、图7C和图7E，第三子透光孔43外轮廓包括第一曲边B1和第二曲边B2，第一曲边B1与第一线段M1形成半圆，第二曲边B2与第一线段M1形成半椭圆；且第三子透光孔43的半圆的圆心与对应的第一电极块211的中心重合。
此外，第二子透光孔42的外轮廓大致为圆形，且圆心与对应的第二电极块212的中心重合。第一子透光孔41的外轮廓大致为圆形，且圆心与对应的第一电极块211的中心重合。
在一个虚拟四边形中，第一方向X上相对的两侧的两个第三子透光孔43中，一个第三子透光孔43的半圆部分，位于对应的椭圆部分的第二方向Y上的一侧；另一个第三子透光孔43的半圆部分，位于对应的椭圆部分的第二方向Y上的另一侧。第二方向Y上相对的两侧的两个第三子透光孔43中，一个第三子透光孔43的半圆部分，位于对应的椭圆部分的第一方向X上的一侧；另一个第三子透光孔43的半圆部分，位于对应的椭圆部分的第一方向X上的另一侧。
此时，在400PPI(Pixels Per Inch)的显示面板100中，上述第一透光孔40的最小径向尺寸为19μm～21μm，第一透光孔40与电极块210之间的最小距离为5.3μm～7.3μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一透光孔40的最小径向尺寸以及第一透光孔40与电极块210之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的边界与对应的搭接孔301的边界之间的距离为18.69μm～20.69μm，第二子透光孔42的边界与对应的搭接孔301的边界之间的距离为12.42μm～14.42μm，第三子透光孔43的边界与对应的搭接孔301的边界之间的距离为19.94μm～21.94μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离并不相同，只要使得第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离，大于或等于第二预设值即可，搭接孔301及第二预设值的描述可以参考下文，本公开实施例在此不作赘述。
此外，上述第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离为21.53μm～23.53μm，第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离为22.83μm～24.83μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离，以及第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的开口率为5.88％～7.88％，第二子透光孔42的开口率为3.18％～5.18％，第三子透光孔43的开口率为3.92％～5.92％。在一个像素单元包括一个第一子透光孔41、两个第二子透光孔42和一个第三子透光孔43的情况下，子像素P的总开口率为16.16％～24.16％。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的开口率并不相同，具体根据显示面板100的参数需求进行设定。
再例如，如图8B和图8D所示，第一子透光孔41为非设定透光孔，第三子透光孔43为设定透光孔。
其中，参阅图8A、图8B和图8D，第一子透光孔41外轮廓包括第一直边D1、第二直边D2和第三曲边B3，第三曲边B3的两端与第一直边D1和第二直边D2分别相连，并形成第三连接点和第四连接点。且，第三连接点和第四连接点的连线的中点，即第二线段M2的中点与对应的第一电极块211的中心重合。
此外，第二子透光孔42的外轮廓大致为菱形，且菱形的中心与对应的第二电极块212的中心重合。第三子透光孔43的外轮廓大致为菱形，且菱形的中心与对应的第一电极块211的中心重合。
在一个虚拟四边形中，第一方向X上相对的两侧的两个第一透光孔41中，一个第一子透光孔41的第三曲边B3，位于对应的第二线段M2的第二方向Y上的一侧；另一个第一子透光孔41的第三曲边B3，位于对应的第二线段M2的第二方向Y上的另一侧。第二方向Y上相对的两侧的两个第一子透光孔41中，一个第一子透光孔41的第三曲边B3，位于对应的第二线段M2的第一方向X上的一侧；另一个第一子透光孔41的第三曲边B3，位于对应的第二线段M2的第一方向X上的另一侧。
此时，在400PPI(Pixels Per Inch)的显示面板100中，上述第一透光孔40的最小径向尺寸为19.68μm～21.68μm，第一透光孔40与电极块210之间的最小距离为3μm～3.2μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一透光孔40的最小径向尺寸以及第一透光孔40与电极块210之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的边界与对应的搭接孔301的边界之间的距离为14.9μm～16.9μm，第二子透光孔42的边界与对应的搭接孔301的边界之间的距离为10μm～12μm，第三子透光孔43的边界与对应的搭接孔301的边界之间的距离为18.1μm～20.1μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离并不相同，只要使得第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离，大于或等于第二预设值即可，搭接孔301及第二预设值的描述可以参考下文，本公开实施例在此不作赘述。
此外，上述第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离为20μm～22μm，第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离为22μm～24μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离，以及第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的开口率为7.48％～9.48％，第二子透光孔42的开口率为4.15％～6.15％，第三子透光孔43的开口率为5.06％～7.06％。在一个像素单元包括一个第一子透光孔41、两个第二子透光孔42和一个第三子透光孔43的情况下，子像素P的总开口率为20.84％～28.84％。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的开口率并不相同，具体根据显示面板100的参数需求进行设定。
再例如，如图8C和图8E所示，第一子透光孔41为设定透光孔，第三子透光孔43为非设定透光孔。
其中，参阅图8A、图8C和图8E，第三子透光孔43外轮廓包括第一直边D1、第二直边D2和第三曲边B3，第三曲边B3的两端与第一直边D1和第二直边D2分别相连，并形成第三连接点和第四连接点。且，第三连接点和第四连接点的连线的中点，即第二线段M2的中点与对应的第一电极块211的中心重合。
此外，第二子透光孔42的外轮廓大致为菱形，且菱形的中心与对应的第二电极块212的中心重合。第一子透光孔41的外轮廓大致为菱形，且菱形的中心与对应的第一电极块211的中心重合。
在一个虚拟四边形中，第一方向X上相对的两侧的两个第三子透光孔43中，一个第三子透光孔43的第三曲边B3，位于对应的第二线段M2的第二方向Y上的一侧；另一个第三子透光孔43的第三曲边B3，位于对应的第二线段M2的第二方向Y上的另一侧。第二方向Y上相对的两侧的两个第三子透光孔43中，一个第三子透光孔43的第三曲边B3，位于对应的第二线段M2的第一方向X上的一侧；另一个第三子透光孔43的第三曲边B3，位于对应的第二线段M2的第一方向X上的另一侧。
此时，在400PPI(Pixels Per Inch)的显示面板100中，上述第一透光孔40的最小径向尺寸为19.68μm～21.68μm，第一透光孔40与电极块210之间的最小距离为3μm～3.2μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一透光孔40的最小径向尺寸以及第一透光孔40与电极块210之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的边界与对应的搭接孔301的边界之间的距离为15.16μm～17.16μm，第二子透光孔42的边界与对应的搭接孔301的边界之间的距离为9.7μm～11.7μm，第三子透光孔43的边界与对应的搭接孔301的边界之间的距离为17.6μm～19.6μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离并不相同，只要使得第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离，大于或等于第二预设值即可，搭接孔301及第二预设值的描述可以参考下文，本公开实施例在此不作赘述。
此外，上述第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离为20μm～22μm，第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离为24.56μm～26.56μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离，以及第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的开口率为7.45％～9.45％，第二子透光孔42的开口率为4.13％～6.13％，第三子透光孔43的开口率为5.04％～7.04％。在一个像素单元包括一个第一子透光孔41、两个第二子透光孔42和一个第三子透光孔43的情况下，子像素P的总开口率为20.75％～28.75％。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的开口率并不相同，具体根据显示面板100的参数需求进行设定。
又例如，如图9B和图9D所示，第一子透光孔41为设定透光孔，第三子透光孔43为非设定透光孔。
其中，参阅图9A、图9B和图9D，第三子透光孔43外轮廓均大致为圆形，且圆形的中心与对应的第一电极块211的中心不重合。
此外，第二子透光孔42的外轮廓大致为圆形，且圆形的中心与对应的第二电极块212的中心重合。第一子透光孔41的外轮廓大致为圆形，且圆形的中心与对应的第一电极块211的中心重合。
在一个虚拟四边形中，第一方向X上相对的两侧的两个第三子透光孔43中，一个第三子透光孔43的圆心，位于对应的第一电极块211的中心的第二方向Y上的一侧；另一个第三子透光孔43的圆心，位于对应的第一电极块211的中心的第二方向Y上的另一侧。第二方向Y上相对的两侧的两个第三子透光孔43中，一个第三子透光孔43的圆心，位于对应的第一电极块211的中心的第一方向X上的一侧；另一个第三子透光孔43的圆心，位于对应的第一电极块211的中心的第一方向X上的另一侧。
此时，在400PPI(Pixels Per Inch)的显示面板100中，上述第一透光孔40的最小径向尺寸为19μm～21μm，第一透光孔40与电极块210之间的最小距离为5.5μm～7.5μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一透光孔40的最小径向尺寸以及第一透光孔40与电极块210之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的边界与对应的搭接孔301的边界之间的距离为19.12μm～21.12μm，第二子透光孔42的边界与对应的搭接孔301的边界之间的距离为12.34μm～14.34μm，第三子透光孔43的边界与对应的搭接孔301的边界之间的距离为20.4μm～22.4μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离并不相同，只要使得第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离，大于或等于第二预设值即可，搭接孔301及第二预设值的描述可以参考下文，本公开实施例在此不作赘述。
此外，上述第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离为20μm～22μm，第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离为22μm～24μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离，以及第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的开口率为5.82％～7.82％，第二子透光孔42的开口率为3.12％～5.12％，第三子透光孔43的开口率为3.87％～5.87％。在一个像素单元包括一个第一子透光孔41、两个第二子透光孔42和一个第三子透光孔43的情况下，子像素P的总开口率为15.97％～23.97％。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的开口率并不相同，具体根据显示面板100的参数需求进行设定。
又例如，如图9C和图9E所示，第一子透光孔41为非设定透光孔，第三子透光孔43为设定透光孔。
其中，参阅图9A、图9C和图9E，第一子透光孔41外轮廓均大致为圆形，且圆形的中心与对应的第一电极块211的中心不重合。
此外，第二子透光孔42的外轮廓大致为圆形，且圆形的中心与对应的第二电极块212的中心重合。第三子透光孔43的外轮廓大致为圆形，且圆形的中心与对应的第一电极块211的中心重合。
在一个虚拟四边形中，第一方向X上相对的两侧的两个第一子透光孔41中，一个第一子透光孔41的圆心，位于对应的第一电极块211的中心的第二方向Y上的一侧；另一个第一子透光孔41的圆心，位于对应的第一电极块211的中心的第二方向Y上的另一侧。第二方向Y上相对的两侧的两个第一子透光孔41中，一个第一子透光孔41的圆心，位于对应的第一电极块211的中心的第一方向X上的一侧；另一个第一子透光孔41的圆心，位于对应的第一电极块211的中心的第一方向X上的另一侧。
此时，在400PPI(Pixels Per Inch)的显示面板100中，上述第一透光孔40的最小径向尺寸为19μm～21μm，第一透光孔40与电极块210之间的最小距离为5.5μm～7.5μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一透光孔40的最小径向尺寸以及第一透光孔40与电极块210之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的边界与对应的搭接孔301的边界之间的距离为18.7μm～20.7μm，第二子透光孔42的边界与对应的搭接孔301的边界之间的距离为12.65μm～14.65μm，第三子透光孔43的边界与对应的搭接孔301的边界之间的距离为20.78μm～22.78μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离并不相同，只要使得第一子透光孔41、第二子透光孔42和第三子透光孔43的边界搭接孔301的边界之间的距离，大于或等于第二预设值即可，搭接孔301及第二预设值的描述可以参考下文，本公开实施例在此不作赘述。
此外，上述第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离为20μm～22μm，第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离为22μm～24μm。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41的边界和第二子透光孔42的边界之间的最小距离，以及第二子透光孔42的边界与第三子透光孔43的边界之间的最小距离并不相同，具体根据显示面板100的参数需求进行设定。
上述第一子透光孔41的开口率为5.82％～7.82％，第二子透光孔42的开口率为3.12％～5.12％，第三子透光孔43的开口率为3.87％～5.87％。在一个像素单元包括一个第一子透光孔41、两个第二子透光孔42和一个第三子透光孔43的情况下，子像素P的总开口率为15.97％～23.97％。
需要说明的是，这里仅以400PPI的显示面板100为例进行示意，不同PPI的显示面板100对应的第一子透光孔41、第二子透光孔42和第三子透光孔43的开口率并不相同，具体根据显示面板100的参数需求进行设定。
在一些实施例中，参阅图3A、图4和图5，上述第一电极层20还包括多个连接条220，多个连接条220包括多个第一连接条221和多个第二连接条222。每个第一连接条221与一个第一电极块211电连接，每个第二连接条222与一个第二电极块212电连接。
其中，如图6所示，沿第二方向Y，每相邻的两个第一电极块211之间设有一个第一连接条221和一个第二连接条222。在这种情况下，第一连接条221和第二连接条222集中设置，有利于第一电极块211和第二电极块212的布置。
这里，连接条220的形状大致为长条形。在此基础上，第一连接条221的长度大于或等于7.9μm，宽度为大于或等于4.6μm。示例性地，第二连接条的长度为7.9μm、8μm、8.1μm、8.2μm和8.3μm中的任一者，宽度为4.6μm、4.7μm、4.8μm、4.9μm和5μm中的任一者。
需要说明的是，在本文中，“大致为长条形”是指，形状整体上呈长方形，但是并不局限为标准的长方形。即，这里的“长条形”不但包括基本长方形的形状，而且考虑到工艺条件，还包括类似于长方形的形状。例如，长方形的拐角处为弯曲状，即拐角处平滑。
在一些实施例中，参阅图3A和图14，显示面板100还包括第一平坦层30，第一平坦层30与第一电极层20靠近衬底10的表面接触。
其中，第一平坦层30上设有搭接孔301，每个第一连接条221对应延伸至一个搭接孔301内，每个第二连接条222对应延伸至一个搭接孔301内。
这里，搭接孔301的边界在衬底10上的正投影，与第一透光孔40的边界在衬底10上的正投影的最小距离大于或等于第二预设值，使得电极块210(参见图4)被第一透光孔40暴露的部分与搭接孔301的距离较大，使得电极块210的被第一透光孔40暴露的部分平坦度较高，提高发光器件2的平坦性，使得显示面板100的显示亮度更加均匀。
需要说明的是，第二预设值可以为8.5μm～11.5μm。示例性地，第二预设值为8.5μm、9μm、9.5μm、10μm、10.5μm、11μm和11.5μm中的任一者。
在一些实施例中，参阅图3A和图10A，显示面板100还包括至少一层导电层50。至少一层导电层50设置于衬底10和第一电极层20之间。
其中，至少一层导电层50包括大致沿第二方向Y延伸的多条第一电源信号线VL。第一电源信号线VL被配置为传输第一电源电压信号Vdd。
在此基础上，如图3A、图10A和图11所示，至少一个第一电极块211在衬底10上的正投影，与至少一条第一电源信号线VL在衬底10上的正投影交叠，且第一电极块211和第一电源信号线VL在衬底10上的正投影交叠的区域，相对于第一电极块211沿第二方向Y的中线对称。
以这种方式设置，第一电源信号线VL在经过第一电极块211的下方时，第一电极块211正下方的第一电源信号线VL的部分相较于第一电极块211沿第二方向Y的中线对称，这样可以平衡第一电极块211沿第二方向Y的中线的两侧的高度，提高第一电极块211的平坦度，提升显示效果。
在一些示例中，参阅图10A，多条第一电源信号线VL包括多个第一电源信号线组VL10，每个第一电源信号线组VL10包括两条并列设置的第一电源信号线VL。
其中，如图10A和图11所示，沿第二方向Y排列的一列第一电极块211在衬底10(参见图3A)上的正投影，与一个第一电源信号线组VL10中的两条第一电源信号线VL在衬底10(参见图3A)上的正投影均交叠，且第一电源信号线组VL10中的两条第一电源信号线VL，相对于一列第一电极块211沿第二方向Y的中线对称。
以这种方式设置，有利于提高第一电源信号线VL排布的规整性，且每两条第一电源信号线VL集中排布，使得第一电源信号线组VL10之间的间距较大，利于避让其他结构，例如，下文提到的需要感测外界环境光的功能器件。
在另一些示例中，参阅图10B，沿第二方向Y排列的一列第一电极块211在衬底10(参见图3A)上的正投影，与一条第一电源信号线VL在衬底10(参见图3A)上的正投影交叠，且第一电源信号线VL相对于一列第一电极块211沿第二方向Y的中线对称。
以这种方式设置，有利于提高第一电源信号线VL排布的规整性，以及增大第一电源信号线VL的横截面积，降低电阻。
在一些实施例中，参阅图3A、图10A和图11，至少一个第二电极块212在衬底10上的正投影，与至少一条第一电源信号线VL1在衬底10上的正投影交叠，且第二电极块212和第一电源信号线VL1在衬底10上的正投影交叠的区域，相对于第二电极块212沿第二方向Y的中线对称。
以这种方式设置，第二电极块212正下方的第一电源信号线VL的部分相较于第一电极块211沿第二方向Y的中线对称，这样可以平衡第一电极块211沿第二方向Y的中线的两侧的高度，提高第一电极块211的平坦度，提升显示效果。
在一些示例中，参阅图10A，多条第一电源信号线VL包括多个第一电源信号线组VL10，每个第一电源信号线组VL10包括两条并列设置的第一电源信号线VL。
其中，如图10A和图11所示，沿第二方向Y排列的一列第二电极块212在衬底10(参见图3A)上的正投影，与相邻的两个第一电源信号线组VL10中，相靠近的两条第一电源信号线VL在衬底10(参见图3A)上的正投影均交叠，且相靠近的两条第一电源信号线VL，相对于一列第二电极块212沿第二方向Y的中线对称。
以这种方式设置，有利于提高第一电源信号线VL排布的规整性，且每两条第一电源信号线VL集中排布，使得第一电源信号线组VL10之间的间距较大，利于避让其他结构，例如，下文提到的需要感测外界环境光的功能器件。
在另一些示例中，参阅图10B，沿第二方向Y排列的一列第二电极块212在衬底10(参见图3A)上的正投影，与相邻的两条第一电源信号线VL在衬底10(参见图3A)上的正投影均交叠，且相邻的两条第一电源信号线VL，相对于一列第二电极块212沿第二方向Y的中线对称。
以这种方式设置，有利于提高第一电源信号线VL排布的规整性，以及增大第一电源信号线VL的横截面积，降低电阻。
应理解，上述电极块210通过连接条220与像素电路3电连接，即连接条220不能与其他信号线短接。基于此，第一电源信号线VL应避让连接条220。
在一些实施例中，参阅图10A和图10B，第一电源信号线VL包括第一走线段VL1和第二走线段VL2。
如图3A、图10A、图10B和图11所示，第一走线段VL1在衬底10上的正投影，位于第一电极块211在衬底10上的正投影内。第二走线段21位于在第二方向Y上相邻的两个第一电极块211之间。
需要说明的是，在第一方向X上，第一走线段VL1的边界与第一电极块211边界之间的距离大于或等于2.5μm。
如图3A、图10A和图11所示，在沿第二方向Y排列的一列第一电极块211在衬底10上的正投影，与一个第一电源信号线组VL10中的两条第一电源信号线VL在衬底10上的正投影均交叠的情况下，一个第一连接条221和一个第二连接条222在衬底10上的正投影，位于一个第一电源信号线组VL10中的两条第一电源信号线VL的第二走线段VL2在衬底10上的正投影之间。
这里，第二走线段VL2在衬底10上的正投影，与最近的一列第二电极块212在衬底10上的正投影部分交叠。
例如，如图10A所示，第二走线段VL2包括主体部VL21和支撑部VL22。主体部VL21和支撑部VL22在衬底10上的正投影，与第二电极块212在衬底10上的正投影均交叠。
其中，主体部VL21的两端与第一走线段VL1电连接，支撑部VL22位于主体部VL21靠近，最近的一列第二电极块212的沿第二方向Y的中线的一侧，以增大第二走线段VL2在衬底10(参见图3A)上的正投影，与第二电极块212在衬底10(参见图3A)上的正投影交叠的面积，进一步地提高第二电极块212的平坦度。
如图3A、图10B和图11所示，在沿第二方向Y排列的一列第一电极块211在衬底10上的正投影，与一条第一电源信号线VL在衬底10上的正投影交叠的情况下，第一电源信号线VL还设有沿第二方向Y排列的多个镂空区，一个第一连接条221和一个第二连接条222在衬底10上的正投影，位于一个镂空区在衬底10上的正投影内。
这里，第二走线段VL2在衬底10上的正投影，与相邻的两列第二电极块212在衬底10上的正投影部分交叠。
例如，如图10B所示，第二走线段VL2包括主体部VL21和支撑部VL22。主体部VL21和支撑部VL22在衬底10上的正投影，与第二电极块212在衬底10上的正投影均交叠。
其中，主体部VL21的两端与第一走线段VL1电连接，支撑部VL22位于主体部VL21相对的两侧，以增大第二走线段VL2在衬底10(参见图3A)上的正投影，与第二电极块212在衬底10(参见图3A)上的正投影交叠的面积，进一步地提高第二电极块212的平坦度。
在一些实施例中，参阅图10A，上述至少一层导电层50还包括大致沿第二方向Y延伸的多条数据线DL。数据线DL被配置为传输数据信号Data。
在此基础上，如图3A、图10A和图11所示，至少一个第二电极块212在衬底10上的正投影，与至少一条数据线DL在衬底10上的正投影交叠，且第二电极块212和数据线DL在衬底10上的正投影交叠的区域，相对于第二电极块212沿第二方向Y的中线对称。
以这种方式设置，数据线DL在经过第二电极块212的下方时，第二电极块212正下方的数据线DL的部分相较于第二电极块212沿第二方向Y的中线对称，这样可以平衡第二电极块212沿第二方向Y的中线的两侧的高度，提高第二电极块212的平坦度，提升显示效果。
示例性地，参阅图10A，多条数据线DL包括多个数据线组DL10，每个数据线组DL10包括两条并列设置的数据线DL。
其中，如图3A、图10A和图11所示，沿第二方向Y排列的一列第二电极块212在衬底10上的正投影，与一个数据线组DL10中的两条数据线DL在衬底10上的正投影均交叠，且数据线组DL10中的两条数据线DL，相对于一列第二电极块212沿第二方向的中线对称。
在一些实施例中，显示面板100还包括功能器件，该功能器件需要采集外界环境光，且集成在显示面板100的非出光侧。这里，该功能器件可以包括指纹识别单元、感光装置等其他功能部件。
在此基础上，参阅图7B，上述发光限定层4还具有多个第二透光孔44，每个第二透光孔44在衬底10(参见图3A)上的正投影，位于沿第二方向Y相邻的第二电极块212在衬底10(参见图3A)上的正投影之间，以使得功能器件可以通过第二透光孔44，采集外界环境光。
在一些示例中，参阅图3A和图12B，上述发光限定层4包括像素界定层70，像素界定层70设有多个第二开口72，第二透光孔44包括像素界定层70上的第一开口72，第一开口72限定第二透光孔44的透光区域。
在另一些示例中，参阅图3A和图12C，上述发光限定层4包括黑矩阵132，黑矩阵132设有多个第四开口135，第二透光孔44包括第四开口135，第四开口135限定第二透光孔44的透光区域。
在又一些示例中，参阅图3A和图12D，上述发光限定层4包括像素界定层70和黑矩阵132。像素界定层70设有多个第二开口72，黑矩阵132设有多个第四开口135，第二透光孔44包括第二开口72和第四开口135。第一开口72和第四开口135共同限定第二透光孔44的透光区域。
这里，参阅图3A和图12E，上述黑矩阵132的第四开口135的外轮廓的形状与像素界定层70的第二开口72的外轮廓的形状可以相同。
此外，黑矩阵132的第四开口135的尺寸可以大于像素界定层70的第二开口72的尺寸，也可以小于像素界定层70的第二开口72的尺寸。
示例性地，参阅图3A和图12F，黑矩阵132的第四开口135的尺寸大于像素界定层70的第二开口72的尺寸，且第四开口135在衬底10上的正投影的边界，与第二开口72在衬底10上的正投影的边界的距离为2μm～6μm。
应理解，为了避免数据线DL对第二透光孔44造成遮挡，数据线DL的布置应该避让该第二透光孔44。
在一些实施例中，参阅图10A，数据线DL包括第三走线段DL1和第四走线段DL2。
如图3A、图10A和图11所示，第三走线段DL1在衬底10上的正投影，位于第二电极块212在衬底10上的正投影内。第四走线段DL2位于在第二方向Y上相邻的两个第二电极块212之间。
其中，每个第二透光孔44在衬底10上的正投影，位于一个数据线组DL10中的两条数据线DL的第四走线段DL2在衬底10上的正投影之间，以避免数据线DL对第二透光孔44造成遮挡，从而影响功能器件的感光。
此外，为了增大第二透光孔44的面积，一个数据线组DL10中并列的两个第四走线段DL2朝相互远离的方向弯曲，以增大第二透光孔44的面积。
应理解，上述第一电源信号线VL和数据线DL可以同层设置，也可以位于不同层。下面以第一电源信号线VL和数据线DL不同层，且结合显示面板100的膜层结构，对上面提到的至少一层导电层、第一电源信号线VL以及数据线DL进行示例性地介绍。
如图3A所示，沿垂直于衬底10且远离衬底10的方向，显示面板100依次包括半导体层ACT、第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1、第二源漏导电层SD2、第一平坦层30和第一电极层20。
需要说明的是，半导体层ACT、第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1和第二源漏导电层SD2中，每相邻的两层之间均设有绝缘膜层。
示例性地，参阅图3A，显示面板100还包括第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层ILD和第二平坦层60。
其中，第一栅绝缘层GI1设置于半导体层ACT和第一栅导电层GT1之间。第二栅绝缘层GI2设置于第一栅导电层GT1和第二栅导电层GT2之间。层间绝缘层ILD设置于第二栅导电层GT2和第一源漏导电层SD1之间。第二平坦层60设置于第一源漏导电层SD1和第二源漏导电层SD2之间。
在此基础上，参阅图3A和图10A，上述至少一层导电层50包括第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1和第二源漏导电层SD2中的至少一者。
示例性地，如图3A和图10A所示，上述至少一层导电层50包括第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1和第二源漏导电层SD2。此时，多条数据线DL可以位于第一源漏导电层SD1；和/或，多条第一电源信号线VL可以位于第二源漏导电层SD2。
在一些实施例中，显示面板100还包括第三源漏导电层，第三源漏导电层位于第一源漏导电层SD1和第二源漏导电层SD2之间。
此时，上述至少一层导电层50包括第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1、第三源漏导电层和第二源漏导电层SD2中的至少一者。
示例性地，上述至少一层导电层50包括第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1、第三源漏导电层SD3和第二源漏导电层SD2。此时，多条数据线DL可以位于第一源漏导电层SD1和/或第三源漏导电层SD3；和/或，多条第一电源信号线VL可以位于第二源漏导电层SD2。
在一些实施例中，参阅图3A、图13和图14，上述显示面板100还包括彩膜80，彩膜80设置于发光界定层4远离衬底10的一侧。
其中，如图8C和图13所示，彩膜80包括多个滤光部810，每个滤光部810对应发光界定层4的一个第一透光孔40，每个滤光部810在衬底10上的正投影，覆盖对应的第一透光孔40在衬底10(参见图3A)上的正投影。并且，每个滤光部810被配置为透射一种颜色的光。
示例性地，参阅图3A、图13和图14，每个滤光部810在衬底10上的正投影，覆盖黑矩阵132对应的第三开口134，滤光部81与黑矩阵132部分交叠。并且，滤光部81的边界对应的第三开口134的边界之间的距离小于或等于5μm。
需要说明的是，滤光部810的材料包括有机材料，例如，滤光部810的材料包括聚甲基丙烯酸甲酯、聚苯乙烯的通用聚合物、具有苯酚类基团的聚合物衍生物、丙烯酰基类聚合物、酰亚胺类聚合物、芳基醚类聚合物、酰胺类聚合物、氟类聚合物、对二甲苯类聚合物和乙烯醇类聚合物中的至少一种。
例如，参阅图2，多个子像素P包括发光颜色为第一颜色的第一子像素、发光颜色为第二颜色的第二子像素、以及发光颜色为第三颜色的第三子像素。其中，第一颜色、第二颜色和第三颜色为三基色。
在此基础上，参阅图13，根据滤光部810透射的光的颜色划分，多个滤光部810可以包括透射第一颜色的光的第一子滤光部811、透射第二颜色的光的第二子滤光部812、以及透射第三颜色的光的第三子滤光部813。
此时，参阅图3A、图13和图14，发光器件2所发出的光，照射在对应的第一子滤光部811上出射第一颜色的光；照射在对应的第二子滤光部812上出射第二颜色的光；照射在对应的第三子滤光部813上出射第三颜色的光，以实现彩色显示。
需要说明的是，上述发光器件2可以被配置为发射白色光线，也可以被配置为发射彩色光线，本公开实施例在此不作具体限定。
在一些实施例中，参阅图13，根据滤光部810的外轮廓的形状及面积划分，彩膜80的多个滤光部810，可以包括多个第一滤光部814和多个第二滤光部815。第一滤光部814的面积大于第二滤光部815的面积。
其中，如图11、图13和图14所示，每个第一电极块211的边界在衬底10(参见图3A)上的正投影，位于一个第一滤光部814的边界在衬底10(参见图3A)上的正投影内。每个第二电极块212的边界在衬底10(参见图3A)上的正投影，位于一个第二滤光部815的边界在衬底10(参见图3A)上的正投影内。
也就是说，本公开实施例所提供的彩膜80，可以包括面积较大的第一滤光部814和面积较小的第二滤光部815。此时，将多个滤光部810仅设置为两种不同的面积，既可以适配有效发光区的面积不同的至少三种子像素P，这样可以降低彩膜80图案化的工艺难度，从而降低形成的多个滤光部810的制备成本。
此外，第一滤光部814和第二滤光部815的形状以及面积可以相应的调整，以适配不同类型的多种发光限定层4，从而进一步地降低生产不同的发光限定层4对应的显示装置1000的制备成本。
示例性地，参阅图11和图13，第一滤光部814的外轮廓的形状可以与第一电极块211的外轮廓的形状大致相同。第二滤光部815的外轮廓的形状可以与第二电极块212的外轮廓的形状大致相同。
例如，如图3A、图11和图13所示，第一电极块211和第二电极块212在衬底10上的正投影均大致为正八边形。第一滤光部814和第二滤光部815在衬底10上的正投影均大致为正八边形。
需要说明的是，第一滤光部814和第二滤光部815在衬底10上的正投影还可以大致为圆形。
此外，任意相邻的第一滤光部814和第二滤光部815之间的距离大致等于第三预设值。
这里，第三预设值可以根据工艺精度设定。示例性地，第三预设值为3.5μm～6.5μm。例如，第三预设值为3.5μm、4μm、4.5μm、5μm、5.5μm、6μm和6.5μm中的任一者。
在这种情况下，在衬底10的第一方向X和第二方向Y所确定的平面上，第一滤光部814和第二滤光部815的面积利用率高，可以使得第一滤光部814和第二滤光部815的面积设置的更大，使得各种发光限定层4的面积最小的第一透光孔40均可以被第一滤光部814完全遮挡进行滤光，其他面积较大的第一透光孔40均可以被第二滤光部815完全遮挡进行滤光，从而提高彩膜80的通用性，使得不同的发光限定层4对应的显示装置1000均可以采用上述彩膜80，降低生产不同的发光限定层4对应的多种显示装置1000的制备成本。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (35)

  1. 一种显示面板，包括：
    衬底；
    第一电极层，设置于所述衬底的一侧；所述第一电极层包括多个第一电极块和多个第二电极块，所述第一电极块的面积大于所述第二电极块的面积；所述多个第一电极块阵列排布为多行多列，每行包括沿第一方向排列的多个第一电极块，每列包括沿第二方向排列的多个第一电极块，所述第一方向和所述第二方向大致垂直；每个第二电极块位于相邻排布的两行两列的四个第一电极块之间；
    发光限定层，设置于所述第一电极层远离所述衬底的一侧；所述发光限定层具有多个第一透光孔，每个第一电极块的至少部分区域被一个第一透光孔暴露，且每个第二电极块的至少部分区域被一个第一透光孔暴露；至少一个所述第一透光孔的至少部分边界为曲线。
  2. 根据权利要求1所述的显示面板，其中，所述多个第一透光孔包括多个第一子透光孔、多个第二子透光孔和多个第三子透光孔，所述第一子透光孔和所述第三子透光孔分别对应暴露一个第一电极块的至少部分区域，所述第二子透光孔对应暴露一个第二电极块的至少部分区域；
    沿所述第一方向，多个第一子透光孔和多个第三子透光孔交替排列；沿所述第二方向，多个第一子透光孔和多个第三子透光孔交替排列；
    相邻的第一子透光孔和第三子透光孔的中心的连线为第一连线，所述相邻的第一子透光孔和第三子透光孔对应的两个第一电极块的中心的连线为第二连线；至少存在一条第一连线与对应的第二连线不平行。
  3. 根据权利要求2所述的显示面板，其中，相邻排布的三行三列的九个第一电极块所对应的九个第一透光孔中，位于四角的四个第一透光孔的中心连线围成虚拟四边形；
    所述虚拟四边形具有沿所述第一方向延伸的第一中线和沿所述第二方向延伸的第二中线；所述九个第一透光孔关于所述第一中线和/或所述第二中线对称。
  4. 根据权利要求3所述的显示面板，其中，所述第一子透光孔和所述第三子透光孔中的一者位于所述虚拟四边形的中心和四个角位置处；另一者位于所述虚拟四边形的四条边上；
    位于所述虚拟四边形的中心和四个角位置处的第一透光孔为设定透光孔，位于所述虚拟四边形的四条边上的第一透光孔为非设定透光孔；
    设定透光孔的发光中心与对应的第一电极块的中心大致重合，第二子透光孔的发光中心与对应的第二电极块的中心大致重合；
    在所述第一方向上相对的两个非设定透光孔中，一个非设定透光孔的中心位于对应的第一电极块的中心的第一侧，另一个非设定透光孔的中心位于对应的第一电极块的中心的第二侧；
    在所述第二方向上相对的两个非设定透光孔中，一个非设定透光孔的中心位于对应的第一电极块的中心的第三侧，另一个非设定透光孔的中心位于对应的第一电极块的中心的第四侧；
    所述第一侧和所述第二侧为所述第一电极块的中心的相对的两侧，第三侧和第四侧为所述第一电极块的中心相对的另外两侧。
  5. 根据权利要求1～4中任一项所述的显示面板，其中，所述多个第一透光孔包括多个第一子透光孔、多个第二子透光孔和多个第三子透光孔；所述第一子透光孔的面积，大于所述第三子透光孔的面积；所述第三子透光孔的面积，大于所述第二子透光孔的面积；
    所述第一子透光孔和所述第三子透光孔分别对应暴露一个第一电极块的至少部分区域，所述第二子透光孔对应暴露一个第二电极块的至少部分区域，且所述第一子透光孔、所述第二子透光孔和所述第三子透光孔中的至少一者的至少部分边界为曲线。
  6. 根据权利要求1～5中任一项所述的显示面板，其中，至少一个第一透光孔的外轮廓包括第一曲边和第二曲边，所述第一曲边的两端和所述第二曲边的两端分别相连，所述第一曲边和所述第二曲边的两个连接点为第一连接点和第二连接点；
    所述第一连接点和所述第二连接点的连线为第一线段，所述第一线段的长度为所述第一透光孔的最大尺寸，且将所述第一透光孔划分为包括所述第一曲边的第一子部分和包括所述第二曲边的第二子部分；所述第一子部分的面积大于所述第二子部分的面积。
  7. 根据权利要求6所述的显示面板，其中，所述第一曲边与所述第一线段围成半圆，所述第二曲边与所述第一线段围成半椭圆。
  8. 根据权利要求6或7所述的显示面板，其中，所述多个第一透光孔包括多个第一子透光孔和多个第三子透光孔，所述第一子透光孔和/或所述第三子透光孔的外轮廓包括所述第一曲边和所述第二曲边。
  9. 根据权利要求6～8中任一项所述的显示面板，其中，所述多个第一透光孔包括第二子透光孔，所述第二子透光孔的外轮廓的形状大致为圆形或椭圆形。
  10. 根据权利要求1～5中任一项所述的显示面板，其中，至少一个第一透光孔的外轮廓包括第一直边、第二直边和第三曲边；所述第一直边和所述第二直边相连形成折线边，所述第三曲边的两端与所述折线边的两端分别相连，所述第三曲边的两端与所述折线边相连的两个连接点为第三连接点和第四连接点；
    所述第三连接点和所述第四连接点的连线为第二线段，所述第二线段的长度为所述第一透光孔的最大尺寸，且将所述第一透光孔划分为包括所述第一直边和所述第二直边的第三子部分和包括所述第三曲边的第四子部分；所述第三子部分的面积大于所述第四子部分的面积。
  11. 根据权利要求10所述的显示面板，其中，所述第三曲边包括依次连接的第一子直线段、第一子曲线段和第二子直线段，所述第一子直线段与所述第一直边连接，所述第二子直线段与所述第二直边连接；
    所述第一子直线段与所述第二直边大致平行，所述第二子直线段与所述第一直边大致平行。
  12. 根据权利要求10或11所述的显示面板，其中，所述多个第一透光孔包括多个第一子透光孔和多个第三子透光孔，所述第一子透光孔和/或所述第三子透光孔的外轮廓包括所述第一直边、所述第二直边和所述第三曲边。
  13. 根据权利要求10～12中任一项所述的显示面板，其中，所述多个第一透光孔包括第二子透光孔，所述第二子透光孔的外轮廓的形状大致为菱形。
  14. 根据权利要求1～5中任一项所述的显示面板，其中，所述第一透光孔的外轮廓的形状均大致为圆形或椭圆形。
  15. 根据权利要求1～14中任一项所述的显示面板，其中，所述发光限定层还具有多个第二透光孔，每个第二透光孔在所述衬底上的正投影，位于沿所述第二方向相邻的第二电极块在所述衬底上的正投影之间。
  16. 根据权利要求1～15中任一项所述的显示面板，其中，所述第一电极块和所述第二电极块的外轮廓的形状均大致为多边形；
    任意相邻的第一电极块和第二电极块的边界相对且大致平行，且相邻的第一电极块和第二电极块之间的距离大致等于第一预设值，所述第一预设值为所述第一电极块和所述第二电极块断开的工艺极限值。
  17. 根据权利要求16所述的显示面板，其中，所述第一电极块和所述第二电极块在所述衬底上的正投影均大致为正八边形。
  18. 根据权利要求1～17中任一项所述的显示面板，其中，所述第一电极层还包括多个第一连接条和多个第二连接条，每个第一连接条与一个第一电极块电连接，每个第二连接条与一个第二电极块电连接；
    沿所述第二方向，每相邻的两个第一电极块之间设有一个所述第一连接条和一个所述第二连接条。
  19. 根据权利要求18所述的显示面板，还包括：
    第一平坦层，与所述第一电极层靠近所述衬底的表面接触；所述第一平坦层上设有搭接孔，每个第一连接条对应延伸至一个搭接孔内，每个第二连接条对应延伸至一个搭接孔内；
    其中，所述搭接孔的边界在所述衬底上的正投影，与所述第一透光孔的边界在所述衬底上的正投影的最小距离大于或等于第二预设值。
  20. 根据权利要求1～19中任一项所述的显示面板，还包括：
    至少一层导电层，设置于所述衬底和所述第一电极层之间；所述至少一层导电层包括大致沿所述第二方向延伸的多条第一电源信号线；
    至少一个第一电极块在所述衬底上的正投影，与至少一条第一电源信号线在所述衬底上的正投影交叠，且所述第一电极块和所述第一电源信号线在所述衬底上的正投影交叠的区域，相对于所述第一电极块沿所述第二方向的中线对称。
  21. 根据权利要求20所述的显示面板，其中，所述多条第一电源信号线包括多个第一电源信号线组，每个第一电源信号线组包括两条并列设置的第一电源信号线；
    沿所述第二方向排列的一列第一电极块，与一个第一电源信号线组中的两条第一电源信号线在所述衬底上的正投影均交叠，且所述第一电源信号线组中的两条第一电源信号线，相对于所述一列第一电极块沿所述第二方向的中线对称。
  22. 根据权利要求21所述的显示面板，其中，所述第一电极层还包括多个第一连接条和多个第二连接条；
    所述第一电源信号线包括第一走线段和第二走线段，所述第一走线段在所述衬底上的正投影，位于所述第一电极块在所述衬底上的正投影内；所述第二走线段位于在所述第二方向上相邻的两个第一电极块之间；
    一个第一连接条和一个第二连接条在所述衬底上的正投影，位于一个第一电源信号线组中的两条第一电源信号线的第二走线段在所述衬底上的正投影之间。
  23. 根据权利要求20～22中任一项所述的显示面板，其中，至少一层导电层还包括大致沿所述第二方向延伸的多条数据线；
    至少一个第二电极块在所述衬底上的正投影，与至少一条数据线在所述衬底上的正投影至少部分交叠，且所述第二电极块和所述数据线在所述衬底上的正投影交叠的区域，相对于所述第二电极块沿所述第二方向的中线对称。
  24. 根据权利要求23所述的显示面板，其中，所述多条数据线包括多个数据线组，每个数据线组包括两条并列设置的数据线；
    沿所述第二方向排列的一列第二电极块在所述衬底上的正投影，与一个数据线组中的两条数据线在所述衬底上的正投影均至少部分交叠，且所述数据线组中的两条数据线，相对于所述一列第二电极块沿所述第二方向的中线对称。
  25. 根据权利要求24所述的显示面板，其中，所述发光限定层还具有多个第二透光孔；
    所述数据线包括第三走线段和第四走线段；所述第三走线段在所述衬底上的正投影，位于所述第二电极块在所述衬底上的正投影内；所述第四走线段位于在所述第二方向上相邻的两个第二电极块之间；
    每个第二透光孔在所述衬底上的正投影，位于一个数据线组中的两条数据线的第四走线段在所述衬底上的正投影之间。
  26. 根据权利要求23～25中任一项所述的显示面板，其中，沿垂直与所述衬底，且由所述衬底指向所述第一电极层的方向，所述至少一层导电层包括依次设置的第一栅导电层、第二栅导电层、第一源漏导电层和第二源漏导电层；
    所述第一电源信号线位于所述第二源漏导电层；和/或，所述多条数据线位于所述第一源漏导电层。
  27. 根据权利要求1～26中任一项所述的显示面板，其中，所述发光限定层包括像素界定层，所述像素界定层设有多个第一开口，所述第一透光孔包括所述第一开口。
  28. 根据权利要求27所述的显示面板，其中，所述发光限定层还具有多个第二透光孔；所述像素界定层设有多个第二开口，所述第二透光孔包括所述第二开口。
  29. 根据权利要求1～28中任一项所述的显示面板，其中，所述发光限定层包括黑矩阵，所述黑矩阵设有多个第三开口，所述第一透光孔包括所述第三开口。
  30. 根据权利要求29所述的显示面板，其中，所述发光限定层还具有多个第二透光孔；所述黑矩阵设有多个第四开口，所述第二透光孔包括所述第四开口。
  31. 根据权利要求1～30中任一项所述的显示面板，其中，所述发光限定层包括像素界定层和黑矩阵，所述第一透光孔包括所述像素界定层的第一开口和所述黑矩阵的第三开口，所述第一开口的外轮廓的形状与所述第三开口的外轮廓的形状相同。
  32. 根据权利要求31所述的显示面板，其中，所述第二透光孔包括所述像素界定层的第二开口和所述黑矩阵的第四开口，所述第二开口的外轮廓的形状与所述第四开口的外轮廓的形状相同。
  33. 根据权利要求1～32中任一项所述的显示面板，还包括：
    彩膜，设置于所述发光限定层远离所述衬底的一侧；所述彩膜包括多个第一滤光部和多个第二滤光部；所述第一滤光部的面积大于所述第二滤光部的面积；每个第一电极块的边界在所述衬底上的正投影，位于一个第一滤光部的边界在所述衬底上的正投影内；每个第二电极块的边界在所述衬底上的正投影，位于一个第二滤光部的边界在所述衬底上的正投影内。
  34. 根据权利要求33所述的显示面板，其中，所述第一滤光部的外轮廓的形状与所述第一电极块的外轮廓的形状大致相同；所述第二滤光部的外轮廓的形状与所述第二电极块的外轮廓的形状大致相同。
  35. 一种显示装置，包括权利要求1～34中任一项所述的显示面板。
PCT/CN2023/108330 2022-07-22 2023-07-20 显示面板及显示装置 WO2024017320A1 (zh)

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