WO2024014201A1 - Switching power supply and control method for same - Google Patents

Switching power supply and control method for same Download PDF

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Publication number
WO2024014201A1
WO2024014201A1 PCT/JP2023/021404 JP2023021404W WO2024014201A1 WO 2024014201 A1 WO2024014201 A1 WO 2024014201A1 JP 2023021404 W JP2023021404 W JP 2023021404W WO 2024014201 A1 WO2024014201 A1 WO 2024014201A1
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Prior art keywords
soft start
pulse current
output
pulse
power supply
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PCT/JP2023/021404
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French (fr)
Japanese (ja)
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一宏 堀井
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ローム株式会社
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Publication of WO2024014201A1 publication Critical patent/WO2024014201A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present disclosure relates to a switching power supply device.
  • Electronic equipment, industrial equipment, industrial machinery, and automobiles are equipped with switching power supply devices that convert the voltage from the main power source into a power supply voltage suitable for the circuit.
  • a switching power supply device includes an error amplifier that amplifies the error between an output detection signal indicating an output signal and a reference signal, a pulse modulator that converts the error signal that is the output of the error amplifier into a pulse modulation signal, and a pulse modulator that converts the error signal that is the output of the error amplifier into a pulse modulation signal.
  • a driver that drives a switching element of the switching power supply device according to the modulation signal.
  • Soft start control is incorporated to prevent the output voltage from overshooting due to feedback loop response delays when starting up the switching power supply.
  • Soft start control can be achieved by gradually increasing (gradually changing) the reference signal over time.
  • a capacitor For example, by charging a capacitor with a current source, it is possible to generate a reference signal that gradually increases over time.
  • a reference signal that gradually increases over time can be generated.
  • the startup time of the switching power supply device be as short as possible within a range that does not cause overshoot.
  • the rate of rise of the reference signal should be slow just before the reference signal reaches the target level, and in order to shorten the startup time, the rise of the reference signal immediately after startup should be It is necessary to increase the speed.
  • the present disclosure has been made in such a situation, and one exemplary objective of a certain aspect thereof is to provide a switching power supply device that can digitally control the waveform of the output signal of the switching power supply device at startup.
  • a switching power supply device includes a power circuit including a switching element, a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal, and a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal.
  • a converter controller that generates a drive pulse with a duty cycle and drives a switching element according to the drive pulse, a soft start capacitor, and a pulse current generator that generates a pulse current for soft start and supplies it to the soft start capacitor. and a clamp circuit that clamps the error signal at a clamp level corresponding to the voltage generated in the soft start capacitor.
  • Another aspect of the present disclosure is a method of controlling a switching power supply device including a switching element.
  • the control method includes the steps of generating an error signal according to the error between an output detection signal indicating the output signal of the switching power supply and a reference signal, generating a drive pulse having a duty cycle according to the error signal, and generating a drive pulse according to the drive pulse. a step of generating a soft start pulse current and charging or discharging the soft start capacitor with the soft start pulse current; and a step of adjusting the clamp level according to the voltage generated in the soft start capacitor. and clamping the error signal.
  • the waveform of the output signal of the switching power supply device at startup can be digitally controlled.
  • FIG. 1 is a block diagram of a circuit system including a switching power supply device according to an embodiment.
  • FIG. 2 is an operational waveform diagram during startup of the switching power supply device.
  • FIG. 3 is a circuit diagram of the switching power supply device according to the first embodiment.
  • FIG. 4 is a circuit diagram of a switching power supply device according to the second embodiment.
  • FIG. 5 is a circuit diagram of the switching power supply device.
  • FIG. 6 is a circuit diagram showing a first configuration example of the current driver.
  • FIG. 7 is a circuit diagram showing a second configuration example of the current driver.
  • FIG. 8 is a circuit diagram showing a third configuration example of the current driver.
  • FIG. 9 is a circuit diagram of the switching power supply device.
  • a switching power supply device includes a power circuit including a switching element, a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal, and a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal.
  • a converter controller that generates a drive pulse with a duty cycle and drives a switching element according to the drive pulse, a soft start capacitor, and a pulse current generator that generates a soft start pulse current and supplies it to the soft start capacitor. and a clamp circuit that clamps the error signal at a clamp level corresponding to the voltage generated in the soft start capacitor.
  • the voltage of the soft start capacitor changes with a slope according to the duty cycle of the soft start pulse current. Since the error signal is clamped by the clamp circuit at a clamp level that corresponds to the voltage of the soft start capacitor, the error signal immediately after startup also changes with a slope that corresponds to the duty cycle of the soft start pulse current. As a result, the duty cycle of the drive pulse gradually changes over time, making it possible to realize a soft start operation. With this configuration, the waveform of the output voltage at startup can be controlled according to the duty cycle of the soft start pulse current. Further, an expensive D/A converter is not required, and the configuration can be made at low cost.
  • the pulse current generator may change the duty cycle of the soft start pulse current depending on the elapsed time from startup. For example, by increasing the duty cycle of the pulse current for soft start immediately after startup, and decreasing the duty cycle of the pulse current for soft start when the output voltage approaches the target level, it is possible to both suppress overshoot and shorten startup time. can.
  • the drive pulse and the soft start pulse current are pulse width modulated signals, and the frequency of the drive pulse and the soft start pulse current may be equal. This makes it possible to suppress vibrations in the output voltage due to beats.
  • the pulse current generator includes a counter that receives a set value for the frequency of the pulse current for soft start and a set value for the duty cycle, and generates the pulse signal for soft start by counting the clock signal. It may be possible to generate a synchronization signal that is asserted every cycle of the soft start pulse current.
  • the converter controller may include a pulse width modulator that generates the drive pulses in synchronization with the synchronization signal.
  • the drive pulse and the soft start pulse current are pulse width modulated signals, and where m is a natural number, the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current. It may be. This makes it possible to suppress vibrations in the output voltage due to beats.
  • the pulsed current generator receives a frequency setting and a duty cycle setting of the soft-start pulsed current and generates the soft-start pulsed signal by counting the clock signal. 1 counter.
  • the converter controller includes a second counter that receives a set value of the frequency of the drive pulse and generates a synchronization signal by counting a clock signal, and a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal. But that's fine. With this configuration, the frequency of the soft start pulse current and the frequency of the drive pulse can be set independently.
  • the power circuit may be an isolated converter.
  • the converter controller, pulse current generator, and clamp circuit may be provided on the primary side.
  • the feedback circuit may include an error amplifier provided on the secondary side, and an isolation circuit whose input is connected to the output of the error amplifier and whose output is connected to the converter controller.
  • the clamp circuit may clamp the output of the isolation circuit.
  • the pulse current generator includes an output stage having a push-pull configuration in which a high-side transistor (upper arm) and a low-side transistor (lower arm) are connected in series, and between the output of the output stage and a soft-start capacitor. and a rectifying element and a series resistor connected in series to the rectifying element and the series resistor.
  • the pulse current generator includes an open-drain or open-collector output stage consisting of a low-side transistor, a rectifying element connected between the output of the output stage and a soft-start capacitor, and an output of the output stage. and a pull-up resistor connected to the pull-up resistor.
  • the pulsed current generator may include an open-drain or open-collector output stage consisting of a high-side transistor, and a series resistor connected between the output of the output stage and a soft-start capacitor. good.
  • a state in which member A is connected to member B refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.
  • a state in which member C is connected (provided) between member A and member B refers to a state in which member A and member C or member B and member C are directly connected. In addition, it also includes cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.
  • FIG. 1 is a block diagram of a circuit system 1 including a switching power supply device 100 according to an embodiment.
  • the circuit system 1 includes an input power source 2, a load 4, and a switching power supply device 100.
  • the switching power supply device 100 receives an input voltage V IN from the input power supply 2 on an input line (input terminal) 102 .
  • a load 4 is connected to an output line (output terminal) 104 of the switching power supply device 100.
  • Switching power supply device 100 receives power from input power supply 2 and supplies power to load 4 .
  • the switching power supply device 100 may output a constant voltage or a constant current, but in this embodiment, it outputs a constant voltage and is stabilized at a predetermined target level V OUT (REF).
  • the output voltage V OUT is supplied to the load 4.
  • the switching power supply device 100 includes a power circuit 110, a feedback circuit 120, a converter controller 130, a pulse current generator 140, a clamp circuit 150, and a soft start capacitor CSS . Note that each block shown in FIG. 1 represents a function or process implemented in the switching power supply device 100, and does not necessarily represent a hardware unit or configuration.
  • the power circuit 110 is the main circuit of the switching power supply, and includes at least one switching element M1, an inductive element such as a transformer or a coil (not shown), a rectifier circuit (not shown), and a smoothing capacitor (not shown).
  • the configuration and topology of the power circuit 110 are not particularly limited, and may be insulated or non-insulated.
  • the power circuit 110 is exemplified by a forward converter, a flyback converter, a half-bridge converter, a full-bridge converter, and the like.
  • the power circuit 110 may have a topology including an inductor (reactor) instead of a transformer, such as a buck converter, a boost converter, a buck-boost converter, a Cuk converter, or a SEPIC. It may also be a converter.
  • An output detection signal V DET indicating the output voltage V OUT of the power circuit 110 is fed back to the feedback circuit 120 .
  • the output detection signal V DET may be the output voltage V OUT or may be a voltage obtained by dividing the output voltage V OUT using a resistor or a transformer.
  • the feedback circuit 120 generates an error signal V ERR according to the error between the output detection signal V DET and the reference signal V REF .
  • feedback circuit 120 includes an error amplifier 122.
  • the output detection signal V DET is input to a first input of the error amplifier 122, and the reference signal V REF is input to a second input of the error amplifier 122.
  • the error amplifier 122 amplifies the error between the output detection signal V DET and the reference signal V REF and outputs an error signal V ERR .
  • the error amplifier 122 may be an operational amplifier or a combination of a transconductance amplifier and a capacitor. In the case of an isolated converter, a shunt regulator may be used as the error amplifier 122.
  • Converter controller 130 generates a drive pulse V DRV having a duty cycle according to error signal V ERR , and drives switching element M1 in accordance with drive pulse V DRV .
  • One end of the soft start capacitor CSS is grounded.
  • the pulse current generator 140 generates a soft start pulse current I PS whose duty cycle changes over time, and supplies it to the soft start capacitor C SS .
  • "Duty cycle" is the ratio of the on level (for example, high) to the period, and the soft start pulse current I PS may be a pulse width modulation (PWM) signal or a pulse frequency modulation (PFM) signal. There may be.
  • PWM pulse width modulation
  • PFM pulse frequency modulation
  • the pulse current generator 140 outputs current when it is on, and cuts off the current when it is off.
  • the clamp circuit 150 clamps the error signal V ERR at a clamp level V CL that corresponds to a voltage (hereinafter referred to as a soft start voltage) V SS generated in the soft start capacitor C SS . That is, the upper limit of the error signal V ERR becomes the clamp level V CL .
  • the above is the configuration of the switching power supply device 100. Next, its operation will be explained.
  • FIG. 2 is an operational waveform diagram when the switching power supply device 100 is started up.
  • a start signal that triggers the activation of switching power supply device 100 is asserted.
  • the pulse current generator 140 starts generating the soft start pulse current IPS .
  • the soft start pulse current IPS is pulse width modulated and its duty cycle decreases over time.
  • the duty cycle of the soft start pulse current I PS is the first duty cycle d1 in the first period T1 (t 1 to t 2 ) immediately after startup, and the first duty cycle d1 in the second period T2 (t 2 to t 3 ) that follows. 2 duty cycle d2, and a third duty cycle d3 in the subsequent third period T3 (from t 3 ).
  • the slope of increase of the soft start voltage V SS of the soft start capacitor C SS becomes smaller in the order of the first period T1, the second period T2, and the third period T3.
  • the clamp level V CL of the clamp circuit 150 increases following the soft start voltage V SS .
  • Time t4 represents the timing at which the output voltage V OUT reaches its target level V OUT (REF) , in other words, the timing at which the output detection signal V DET reaches the reference signal V REF .
  • the error signal V ERR is clamped at the clamp level V CL .
  • the error signal V ERR is stabilized near the stable point of the feedback loop, while the clamp level V CL continues to rise. Therefore, clamp circuit 150 does not affect the feedback loop.
  • the third period T3 is determined to include timing t4 , and the value of the third duty cycle d3 is determined to be sufficiently small. Thereby, when the output voltage V OUT reaches its target level V OUT (REF) , the rate of increase in the output voltage V OUT is sufficiently suppressed, so that overshoot can be suppressed.
  • V OUT target level
  • the output voltage V OUT can be rapidly increased, and the startup time can be shortened.
  • a second period T2 having an intermediate duty cycle d2 is inserted between the first period T1 and the third period T3. If there is no second period T2 and the duty cycle changes directly from d1 to d3, there is a risk that unnecessary vibrations will occur in the output voltage V OUT . By inserting the second period T2, unnecessary vibrations in the output voltage V OUT can be suppressed.
  • the present disclosure covers various devices and methods that can be understood as the block diagram and circuit diagram of FIG. 1 or derived from the above description, and is not limited to a specific configuration. More specific configuration examples and examples will be described below, not to narrow the scope of the present disclosure, but to help understand and clarify the essence and operation of the present disclosure and the present invention.
  • FIG. 3 is a circuit diagram of the switching power supply device 100A according to the first embodiment.
  • the switching power supply device 100A is a non-insulated converter, and the power circuit 110A has a step-down converter topology.
  • the power circuit 110A includes a high-side transistor (switching transistor) M1H, a low-side transistor (synchronous rectification transistor) M1L, an inductor L1, and an output capacitor C1.
  • Converter controller 130A includes a pulse modulator 132, a high-side driver 134H, and a low-side driver 134L.
  • Pulse modulator 132 generates a pulse modulated signal V MOD having a duty cycle responsive to error signal V ERR .
  • High-side driver 134H and low-side driver 134L complementarily drive high-side transistor M1H and low-side transistor M1L according to pulse modulation signal V MOD .
  • Pulse modulator 132 may be a pulse width modulator or a pulse frequency modulator.
  • Clamp circuit 150A includes a PNP type bipolar transistor Q1.
  • the collector of bipolar transistor Q1 is grounded, and the emitter is connected to the output of error amplifier 122 and the input of converter controller 130A.
  • a soft start voltage VSS is input to the base of the bipolar transistor Q1.
  • a P-channel type MOSFET may be used as the PNP type bipolar transistor Q1.
  • FIG. 4 is a circuit diagram of a switching power supply device 100B according to the second embodiment.
  • the switching power supply device 100B is an isolated converter
  • the power circuit 110B is a forward converter and includes a transformer T1, a switching element M1, rectifying elements D1 and D2, an output choke coil L0, and an output capacitor C0.
  • Switching element M1 is connected to primary winding W1 of transformer T1. Rectifying elements D1 and D2, output choke coil L0, and output capacitor C0 are connected to secondary winding W2.
  • the feedback circuit 120B includes an error amplifier 122 and an isolation circuit 124.
  • Error amplifier 122 is provided on the secondary side.
  • Isolation circuit 124 is arranged at the boundary between the primary side and the secondary side, the input of isolation circuit 124 is connected to the output of error amplifier 122, and the output of isolation circuit 124 is connected to the input of converter controller 130B.
  • the insulation circuit 124 can use a photocoupler 124B.
  • the error amplifier 122 is a shunt regulator, and supplies an error signal I ERR corresponding to the error between the output detection signal V DET and the reference voltage V REF to the light emitting element (photo diode) of the photo coupler 124B.
  • a current IFB corresponding to the error current IERR flows through the light receiving element (phototransistor) of the photocoupler 124B.
  • Converter controller 130B includes a pulse modulator 132, a driver 134, and a resistor R11.
  • the resistor R11 converts the current flowing through the light receiving element of the photocoupler 124B into an error signal V ERR which is a voltage signal.
  • Pulse modulator 132 generates a pulse modulated signal V MOD having a duty cycle responsive to error signal VERR.
  • the driver 134 generates a drive pulse V DRV according to the pulse modulation signal V MOD and supplies it to the gate of the switching element M1.
  • Clamp circuit 150 is provided on the primary side together with converter controller 130B and pulse current generator 140. Clamp circuit 150 is connected to the output of isolation circuit 124 and the input of pulse modulator 132.
  • the above is the configuration of the switching power supply device 100B. According to this switching power supply device 100B, even in an isolated converter, it is possible to achieve both faster startup and suppression of overshoot.
  • the hardware related to soft start can be consolidated on the primary side, there is no need for an insulating element for transmitting signals related to soft start. This makes it possible to suppress an increase in the cost of the switching power supply device 100B.
  • FIG. 5 is a circuit diagram of the switching power supply device 100C.
  • the switching power supply device 100C is an isolated converter like the switching power supply device 100B.
  • the drive pulse V DRV and the soft start pulse current I PS are pulse width modulated (PWM) signals.
  • the frequency of the drive pulse VDRV that is, the switching frequency, and the frequency of the soft start pulse current IPS are equal.
  • the pulse current generator 140C includes a processor 142, a counter 144, and a current driver 146.
  • the processor 142 generates a set value D SET of the duty cycle of the soft start pulse current I PS and a set value F SET of the frequency f SS of the soft start pulse current I PS .
  • the set value D SET takes a first value d1 in the first period T1, a second value d2 in the second period T2, and a third value d3 in the third period T3.
  • Counter 144 is a digital PWM (DPWM) circuit and functions as a pulse width modulator.
  • the counter 144 generates a soft start pulse signal V PS having a predetermined frequency f SS and a duty cycle according to the set value D SET .
  • a set value D SET of the duty cycle and a set value F SET of the frequency f SS of the soft start pulse current I PS are input to the counter 144 .
  • the counter 144 generates a soft start pulse signal VPS by counting the clock signal CLK. Specifically, the counter 144 counts up in accordance with the clock signal CLK, outputs a first level (for example, high) from the start of counting until the count value reaches the set value DSET , and then outputs the first level (for example, high). A second level (for example, low) is output until the value reaches the set value F SET . When the count value reaches the set value F SET , the counter 144 is reset and repeats the same operation.
  • the current driver 146 generates a soft start pulse current I PS in response to the soft start pulse signal V PS .
  • the current driver 146 outputs current when the soft start pulse signal VPS is at a first level (for example, high), and cuts off the current when the soft start pulse signal VPS is at a second level (for example, low). .
  • the pulse current generator 140C generates a synchronization signal V SYNC that is asserted every cycle (1/f SS ) of the soft start pulse current I PS (pulse signal V PS ). Synchronization signal V SYNC is provided to converter controller 130C.
  • Converter controller 130C includes a pulse width modulator 132C and a driver 134.
  • a synchronizing signal V SYNC is supplied to the pulse width modulator 132C from the pulse current generator 140C.
  • Pulse current generator 140C generates pulse width modulation signal V PWM in synchronization with synchronization signal V SYNC .
  • converter controller 130C includes a PWM comparator 170 and an oscillator 172.
  • the oscillator 172 generates a periodic signal V OSC having the same frequency as the soft start pulse signal V PS in synchronization with the synchronization signal V SYNC .
  • the periodic signal V OSC is a triangular wave or a sawtooth wave.
  • PWM comparator 170 compares periodic signal V OSC with error signal V ERR and generates PWM signal V PWM . With this configuration, the frequency of the PWM signal VPWM and the frequency of the soft start pulse current IPS can be made equal.
  • the switching frequency of the power circuit 110C and the frequency of the soft start pulse current IPS are different from each other, the output voltage V OUT will fluctuate due to the beat.
  • the switching frequency with the frequency of the soft start pulse current IPS , it is possible to suppress vibrations in the output voltage due to beats.
  • FIG. 6 is a circuit diagram showing a first configuration example (146a) of the current driver 146.
  • Current driver 146a includes an output stage 148a with a push-pull configuration, a rectifying element D21, and a series resistor R21.
  • the output stage 148a switches in response to an inverted signal V PS ⁇ ( ⁇ represents logical inversion) of the soft start pulse signal V PS .
  • Rectifying element D21 and series resistor R21 are connected in series between the output of output stage 148a and soft start capacitor CSS .
  • FIG. 7 is a circuit diagram showing a second configuration example (146b) of the current driver 146.
  • the current driver 146b includes an open drain type (or open collector type) output stage 148b including a low-side transistor M22, a pull-up resistor R22, and a rectifier D22.
  • the output stage 148b switches in response to the inverted signal V PS ⁇ of the soft start pulse signal V PS .
  • the soft-start pulse current IPS is supplied to the soft-start capacitor CSS via the pull-up resistor R22 and the rectifier D22.
  • FIG. 8 is a circuit diagram showing a third configuration example (146c) of the current driver 146.
  • Current driver 146c includes an open drain type (or open collector type) output stage 148c including a high side transistor M23 and a series resistor R23.
  • the output stage 148c switches in response to the inverted signal V PS ⁇ of the soft start pulse signal V PS .
  • the soft start pulse current I PS is supplied to the soft start capacitor C SS via the series resistor R23.
  • the configuration of the current driver 146 is not limited to those shown in FIGS. 6 to 8.
  • the current driver 146 may be configured with a constant current source that can be turned on and off.
  • FIG. 9 is a circuit diagram of switching power supply device 100D.
  • Switching power supply device 100D is an isolated converter like switching power supply devices 100B and 100C.
  • the drive pulse V DRV and the soft start pulse current I PS are pulse width modulated (PWM) signals.
  • the frequency of the drive pulse VDRV ie, the switching frequency, is m times or 1/m times the frequency of the soft start pulse current IPS .
  • Pulse current generator 140D includes a first counter 144 and a current driver 146.
  • the first counter 144 receives a frequency setting value F SET1 and a duty cycle setting value D SET of the soft start pulse current I PS from the processor 142, and generates a soft start pulse signal V PS .
  • the current driver 146 outputs a soft start pulse current I PS corresponding to the soft start pulse signal V PS .
  • Converter controller 130D includes a synchronization signal generator 136 in addition to pulse width modulator 132C and driver 134.
  • the synchronization signal generator 136 generates a synchronization signal V SYNC having a frequency m times or 1/m times the soft start pulse current I PS generated by the pulse current generator 140 .
  • Synchronization signal generator 136 includes a second counter 138.
  • the second counter 138 is supplied with a frequency setting value F SET2 that defines the frequency of the synchronization signal V SYNC , that is, the switching frequency of the switching element M1, from the digital processor 200.
  • the second counter 138 counts up in accordance with the clock signal CLK, and when the count value reaches the frequency setting value F SET2 , repeats the operation of asserting the synchronization signal V SYNC and resetting it.
  • Synchronization signal V SYNC is provided to converter controller 130C.
  • the duty cycle of the soft start pulse current IPS changes in three values d1, d2, and d3, but this is not the case. If the response speed of the feedback circuit 120 is relatively fast, the second period T2 may be omitted and the duty cycle may be changed between two values, d1 and d3. Alternatively, the duty cycle of the soft start pulse current IPS may be changed by four or more values, or may be changed continuously.
  • the duty cycle of the soft start pulse current IPS may be fixed at one value. For example, in applications that do not require high-speed startup, it is sufficient to generate a soft-start pulse current IPS with a constant duty cycle that does not cause overshoot.In this case, the output voltage VOUT of the switching power supply 100 is It can be raised by tilting.
  • a power circuit including a switching element, a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal; a converter controller that generates a drive pulse having a duty cycle according to the error signal and drives the switching element according to the drive pulse; soft start capacitor, a pulse current generator that generates a pulse current for soft start and supplies it to the soft start capacitor; a clamp circuit that clamps the error signal at a clamp level that corresponds to the voltage generated in the soft start capacitor;
  • a switching power supply device comprising:
  • the driving pulse and the soft start pulse current are pulse width modulated signals, The switching power supply device according to item 1 or 2, wherein the frequency of the drive pulse and the frequency of the soft start pulse current are equal.
  • the pulse current generator includes a counter that receives a frequency setting value and a duty cycle setting value of the soft start pulse current, and generates a soft start pulse signal by counting a clock signal, It is possible to generate a synchronization signal that is asserted every cycle of the soft start pulse current,
  • the switching power supply device includes a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal.
  • the driving pulse and the soft start pulse current are pulse width modulated signals, 3.
  • the switching power supply device according to item 1 or 2, wherein the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current, where m is a natural number.
  • the pulse current generator receives a frequency setting value and a duty cycle setting value of the soft start pulse current, and operates a first counter that generates a soft start pulse signal by counting a clock signal.
  • the converter controller includes: a second counter that receives a set value of the frequency of the drive pulse and generates a synchronization signal by counting the clock signal; a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal;
  • the switching power supply device according to item 3 or 5, comprising:
  • the power circuit is an isolated converter;
  • the converter controller, the pulse current generator, and the clamp circuit are provided on the primary side,
  • the feedback circuit is An error amplifier provided on the secondary side, an isolation circuit whose input is connected to the output of the error amplifier and whose output is connected to the converter controller; including; 7.
  • the switching power supply device according to any one of items 1 to 6, wherein the clamp circuit clamps the output of the insulation circuit.
  • the pulse current generator is An output stage with a push-pull configuration, a rectifying element and a series resistor connected in series between the output of the output stage and the soft start capacitor;
  • the switching power supply device according to any one of items 1 to 7, including:
  • the pulse current generator is An open-drain or open-collector output stage consisting of a low-side transistor, a rectifying element connected between the output of the output stage and the soft start capacitor; a pull-up resistor connected to the output of the output stage;
  • the switching power supply device according to any one of items 1 to 7, including:
  • the pulse current generator is An open-drain or open-collector output stage consisting of a high-side transistor, a series resistor connected between the output of the output stage and the soft start capacitor;
  • the switching power supply device according to any one of items 1 to 7, including:
  • (Item 11) 11 The switching power supply device according to any one of items 1 to 10, wherein the clamp circuit includes a transistor whose base receives the voltage of the soft start capacitor and whose emitter is connected to the input of the converter controller.
  • a method for controlling a switching power supply device including a switching element comprising: generating an error signal according to an error between an output detection signal indicating an output signal of the switching power supply and a reference signal; generating a drive pulse having a duty cycle according to the error signal, and driving the switching element according to the drive pulse; generating a soft-start pulse current and charging or discharging a soft-start capacitor with the soft-start pulse current; clamping the error signal at a clamp level according to the voltage generated in the soft start capacitor;
  • a control method comprising:
  • the driving pulse and the soft start pulse current are pulse width modulated signals, 13.
  • the driving pulse and the soft start pulse current are pulse width modulated signals, The control method according to item 12, wherein the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current, where m is a natural number.
  • the present disclosure relates to a switching power supply device.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A power circuit 110 includes a switching element M1. A feedback circuit 120 generates an error signal VERR according to an error between an output detection signal VDET indicating the output signal VOUT of the power circuit 110 and a reference signal VREF. A converter controller 130 generates a drive pulse VDRV having a duty cycle according to the error signal VERR, and drives the switching element M1 in accordance with the drive pulse VDRV. A pulse current generator 140 generates a soft start pulse current IPS and supplies the soft start pulse current IPS to a soft start capacitor CSS. A clamp circuit 150 clamps the error signal VERR at a clamp level VCL corresponding to the voltage VSS generated in the soft start capacitor CSS.

Description

スイッチング電源装置およびその制御方法Switching power supply and its control method
　本開示は、スイッチング電源装置に関する。 The present disclosure relates to a switching power supply device.
　電子機器、産業機器、産業機械、自動車は、主電源からの電圧を、回路に適した電源電圧に変換するスイッチング電源装置を備える。 Electronic equipment, industrial equipment, industrial machinery, and automobiles are equipped with switching power supply devices that convert the voltage from the main power source into a power supply voltage suitable for the circuit.
　スイッチング電源装置には、出力電圧もしくは出力電流である出力信号が、目標レベルを示す基準信号に近づくようにフィードバックループが組み込まれている。具体的には、スイッチング電源装置は、出力信号を示す出力検出信号と基準信号の誤差を増幅するエラーアンプと、エラーアンプの出力である誤差信号をパルス変調信号に変換するパルス変調器と、パルス変調信号に応じて、スイッチング電源装置のスイッチング素子を駆動するドライバと、を含む。 A feedback loop is built into the switching power supply so that an output signal, which is an output voltage or an output current, approaches a reference signal indicating a target level. Specifically, a switching power supply device includes an error amplifier that amplifies the error between an output detection signal indicating an output signal and a reference signal, a pulse modulator that converts the error signal that is the output of the error amplifier into a pulse modulation signal, and a pulse modulator that converts the error signal that is the output of the error amplifier into a pulse modulation signal. A driver that drives a switching element of the switching power supply device according to the modulation signal.
　スイッチング電源装置の起動時に、フィードバックループの応答遅れによって、出力電圧がオーバーシュートするのを防止するため、ソフトスタート制御が組み込まれる。ソフトスタート制御は、基準信号を時間とともに緩やかに上昇（徐変）させることで実現できる。 Soft start control is incorporated to prevent the output voltage from overshooting due to feedback loop response delays when starting up the switching power supply. Soft start control can be achieved by gradually increasing (gradually changing) the reference signal over time.
　たとえば、キャパシタを電流源によって充電することにより、時間とともに緩やかに上昇する基準信号を生成することができる。あるいはＤ／Ａコンバータに、波形データを入力することにより、時間とともに緩やかに上昇する基準信号を生成することができる。 For example, by charging a capacitor with a current source, it is possible to generate a reference signal that gradually increases over time. Alternatively, by inputting waveform data to a D/A converter, a reference signal that gradually increases over time can be generated.
特開２０２１－０６９２２７号公報JP2021-069227A 特開２０２１－０９０２７２号公報JP 2021-090272 Publication
　スイッチング電源装置の起動時間は、オーバーシュートが生じない範囲において、極力短いことが好ましい。オーバーシュートを抑制するためには、基準信号が、目標レベルに到達する直前において、基準信号の上昇速度が遅くなっていればよく、起動時間を短縮するためには、起動直後の基準信号の上昇速度を高めることが求められる。キャパシタを充電する方式では、基準信号の上昇速度（波形）を可変にすることが難しいため、オーバーシュートの抑制と起動時間の短縮の両立は難しい。 It is preferable that the startup time of the switching power supply device be as short as possible within a range that does not cause overshoot. In order to suppress overshoot, the rate of rise of the reference signal should be slow just before the reference signal reaches the target level, and in order to shorten the startup time, the rise of the reference signal immediately after startup should be It is necessary to increase the speed. In the method of charging a capacitor, it is difficult to make the rising speed (waveform) of the reference signal variable, so it is difficult to suppress overshoot and shorten startup time at the same time.
　Ｄ／Ａコンバータを利用する方式では、オーバーシュートの抑制と起動時間の短縮の両立が可能であるが、出力電圧を滑らかに上昇させるためには、高ビットのＤ／Ａコンバータが必要となり、コストアップの要因となる。 Methods that use a D/A converter can suppress overshoot and shorten startup time, but in order to smoothly increase the output voltage, a high-bit D/A converter is required, which increases cost. It becomes a factor of increase.
　また基準信号を徐変させるソフトスタート制御では、絶縁型スイッチング電源装置への適用が難しい。すなわち絶縁型スイッチング電源では、エラーアンプが二次側に配置されるため、二次側の基準信号を徐変させる必要がある。一方で、絶縁型スイッチング電源装置のメインとなるコントローラは一次側に配置されるため、一次側から二次側へ、絶縁素子を介して制御信号を送り込む必要があり、コストアップの要因となる。 Furthermore, soft start control that gradually changes the reference signal is difficult to apply to isolated switching power supplies. That is, in an isolated switching power supply, since the error amplifier is placed on the secondary side, it is necessary to gradually change the reference signal on the secondary side. On the other hand, since the main controller of an isolated switching power supply is placed on the primary side, it is necessary to send control signals from the primary side to the secondary side via an insulating element, which increases costs.
　本開示はかかる状況においてされたものであり、そのある態様の例示的な目的のひとつは、起動時におけるスイッチング電源装置の出力信号の波形をデジタル制御可能なスイッチング電源装置の提供にある。 The present disclosure has been made in such a situation, and one exemplary objective of a certain aspect thereof is to provide a switching power supply device that can digitally control the waveform of the output signal of the switching power supply device at startup.
　本開示のある態様のスイッチング電源装置は、スイッチング素子を含むパワー回路と、パワー回路の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するフィードバック回路と、誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、駆動パルスに応じてスイッチング素子を駆動するコンバータコントローラと、ソフトスタート用キャパシタと、ソフトスタート用パルス電流を生成し、ソフトスタート用キャパシタに供給するパルス電流発生器と、ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、誤差信号をクランプするクランプ回路と、を備える。 A switching power supply device according to an aspect of the present disclosure includes a power circuit including a switching element, a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal, and a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal. A converter controller that generates a drive pulse with a duty cycle and drives a switching element according to the drive pulse, a soft start capacitor, and a pulse current generator that generates a pulse current for soft start and supplies it to the soft start capacitor. and a clamp circuit that clamps the error signal at a clamp level corresponding to the voltage generated in the soft start capacitor.
　本開示の別の態様は、スイッチング素子を含むスイッチング電源装置の制御方法である。制御方法は、スイッチング電源装置の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するステップと、誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、駆動パルスに応じてスイッチング素子を駆動するステップと、ソフトスタート用パルス電流を生成し、ソフトスタート用パルス電流によってソフトスタート用キャパシタを充電または放電するステップと、ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、誤差信号をクランプするステップと、を備える。 Another aspect of the present disclosure is a method of controlling a switching power supply device including a switching element. The control method includes the steps of generating an error signal according to the error between an output detection signal indicating the output signal of the switching power supply and a reference signal, generating a drive pulse having a duty cycle according to the error signal, and generating a drive pulse according to the drive pulse. a step of generating a soft start pulse current and charging or discharging the soft start capacitor with the soft start pulse current; and a step of adjusting the clamp level according to the voltage generated in the soft start capacitor. and clamping the error signal.
　なお、以上の構成要素を任意に組み合わせたもの、構成要素や表現を、方法、装置、システムなどの間で相互に置換したものもまた、本発明あるいは本開示の態様として有効である。さらに、この項目（課題を解決するための手段）の記載は、本発明の欠くべからざるすべての特徴を説明するものではなく、したがって、記載されるこれらの特徴のサブコンビネーションも、本発明たり得る。 Note that arbitrary combinations of the above components, and mutual substitution of components and expressions among methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not describe all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. .
　本開示のある態様によれば、起動時におけるスイッチング電源装置の出力信号の波形をデジタル制御できる。 According to an aspect of the present disclosure, the waveform of the output signal of the switching power supply device at startup can be digitally controlled.
図１は、実施形態に係るスイッチング電源装置を備える回路システムのブロック図である。FIG. 1 is a block diagram of a circuit system including a switching power supply device according to an embodiment. 図２は、スイッチング電源装置の起動時の動作波形図である。FIG. 2 is an operational waveform diagram during startup of the switching power supply device. 図３は、実施例１に係るスイッチング電源装置の回路図である。FIG. 3 is a circuit diagram of the switching power supply device according to the first embodiment. 図４は、実施例２に係るスイッチング電源装置の回路図である。FIG. 4 is a circuit diagram of a switching power supply device according to the second embodiment. 図５は、スイッチング電源装置の回路図である。FIG. 5 is a circuit diagram of the switching power supply device. 図６は、電流ドライバの第１の構成例を示す回路図である。FIG. 6 is a circuit diagram showing a first configuration example of the current driver. 図７は、電流ドライバの第２の構成例を示す回路図である。FIG. 7 is a circuit diagram showing a second configuration example of the current driver. 図８は、電流ドライバの第３の構成例を示す回路図である。FIG. 8 is a circuit diagram showing a third configuration example of the current driver. 図９は、スイッチング電源装置の回路図である。FIG. 9 is a circuit diagram of the switching power supply device.
（実施形態の概要）
　本開示のいくつかの例示的な実施形態の概要を説明する。この概要は、後述する詳細な説明の前置きとして、実施形態の基本的な理解を目的として、１つまたは複数の実施形態のいくつかの概念を簡略化して説明するものであり、発明あるいは開示の広さを限定するものではない。この概要は、考えられるすべての実施形態の包括的な概要ではなく、すべての実施形態の重要な要素を特定することも、一部またはすべての態様の範囲を線引きすることも意図していない。便宜上、「一実施形態」は、本明細書に開示するひとつの実施形態（実施例や変形例）または複数の実施形態（実施例や変形例）を指すものとして用いる場合がある。 (Summary of embodiment)
1 provides an overview of some exemplary embodiments of the present disclosure. This Summary is intended to provide a simplified description of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments and as a prelude to the more detailed description that is presented later. It does not limit the size. This summary is not an exhaustive overview of all possible embodiments and is not intended to identify key elements of all embodiments or to delineate the scope of any or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or modification) or multiple embodiments (examples or modifications) disclosed in this specification.
　一実施形態に係るスイッチング電源装置は、スイッチング素子を含むパワー回路と、パワー回路の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するフィードバック回路と、誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、駆動パルスに応じてスイッチング素子を駆動するコンバータコントローラと、ソフトスタート用キャパシタと、ソフトスタート用パルス電流を生成し、ソフトスタート用キャパシタに供給するパルス電流発生器と、ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、誤差信号をクランプするクランプ回路と、を備える。 A switching power supply device according to an embodiment includes a power circuit including a switching element, a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal, and a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal. A converter controller that generates a drive pulse with a duty cycle and drives a switching element according to the drive pulse, a soft start capacitor, and a pulse current generator that generates a soft start pulse current and supplies it to the soft start capacitor. and a clamp circuit that clamps the error signal at a clamp level corresponding to the voltage generated in the soft start capacitor.
　ソフトスタート用キャパシタの電圧は、ソフトスタート用パルス電流のデューティサイクルに応じた傾きで変化する。クランプ回路によって、誤差信号は、ソフトスタート用キャパシタの電圧に応じたクランプレベルでクランプされるため、起動直後の誤差信号も、ソフトスタート用パルス電流のデューティサイクルに応じた傾きで変化する。これにより、駆動パルスのデューティサイクルが、時間とともに徐々に変化し、ソフトスタート動作を実現できる。この構成では、ソフトスタート用パルス電流のデューティサイクルに応じて、起動時の出力電圧の波形を制御できる。また高価なＤ／Ａコンバータが不要であり、安価に構成できる。 The voltage of the soft start capacitor changes with a slope according to the duty cycle of the soft start pulse current. Since the error signal is clamped by the clamp circuit at a clamp level that corresponds to the voltage of the soft start capacitor, the error signal immediately after startup also changes with a slope that corresponds to the duty cycle of the soft start pulse current. As a result, the duty cycle of the drive pulse gradually changes over time, making it possible to realize a soft start operation. With this configuration, the waveform of the output voltage at startup can be controlled according to the duty cycle of the soft start pulse current. Further, an expensive D/A converter is not required, and the configuration can be made at low cost.
　一実施形態において、パルス電流発生器は、起動からの経過時間に応じて、ソフトスタート用パルス電流のデューティサイクルを変化させてもよい。たとえば起動直後のソフトスタート用パルス電流のデューティサイクルを大きくし、出力電圧が目標レベルに近づくとソフトスタート用パルス電流のデューティサイクルを小さくすることで、オーバーシュートの抑制と、起動時間の短縮を両立できる。 In one embodiment, the pulse current generator may change the duty cycle of the soft start pulse current depending on the elapsed time from startup. For example, by increasing the duty cycle of the pulse current for soft start immediately after startup, and decreasing the duty cycle of the pulse current for soft start when the output voltage approaches the target level, it is possible to both suppress overshoot and shorten startup time. can.
　一実施形態において、駆動パルスおよびソフトスタート用パルス電流は、パルス幅変調信号であり、駆動パルスの周波数と、ソフトスタート用パルス電流の周波数が等しくてもよい。これにより、ビートによる出力電圧の振動を抑制できる。 In one embodiment, the drive pulse and the soft start pulse current are pulse width modulated signals, and the frequency of the drive pulse and the soft start pulse current may be equal. This makes it possible to suppress vibrations in the output voltage due to beats.
　一実施形態において、パルス電流発生器は、ソフトスタート用パルス電流の周波数の設定値と、デューティサイクルの設定値と、を受け、クロック信号をカウントすることにより、ソフトスタート用パルス信号を生成するカウンタを含み、ソフトスタート用パルス電流の周期ごとにアサートされる同期信号を生成可能であってもよい。コンバータコントローラは、同期信号と同期して駆動パルスを生成するパルス幅変調器を含んでもよい。 In one embodiment, the pulse current generator includes a counter that receives a set value for the frequency of the pulse current for soft start and a set value for the duty cycle, and generates the pulse signal for soft start by counting the clock signal. It may be possible to generate a synchronization signal that is asserted every cycle of the soft start pulse current. The converter controller may include a pulse width modulator that generates the drive pulses in synchronization with the synchronization signal.
　一実施形態において、駆動パルスおよびソフトスタート用パルス電流は、パルス幅変調信号であり、ｍを自然数とするとき、駆動パルスの周波数は、ソフトスタート用パルス電流の周波数のｍ倍または１／ｍ倍であってもよい。これにより、ビートによる出力電圧の振動を抑制できる。 In one embodiment, the drive pulse and the soft start pulse current are pulse width modulated signals, and where m is a natural number, the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current. It may be. This makes it possible to suppress vibrations in the output voltage due to beats.
　一実施形態において、パルス電流発生器は、ソフトスタート用パルス電流の周波数の設定値と、デューティサイクルの設定値と、を受け、クロック信号をカウントすることにより、ソフトスタート用パルス信号を生成する第１カウンタを含んでもよい。コンバータコントローラは、駆動パルスの周波数の設定値を受け、クロック信号をカウントすることにより同期信号を生成する第２カウンタと、同期信号と同期して駆動パルスを生成するパルス幅変調器と、を含んでもよい。この構成では、ソフトスタート用パルス電流の周波数と、駆動パルスの周波数を独立に設定できる。 In one embodiment, the pulsed current generator receives a frequency setting and a duty cycle setting of the soft-start pulsed current and generates the soft-start pulsed signal by counting the clock signal. 1 counter. The converter controller includes a second counter that receives a set value of the frequency of the drive pulse and generates a synchronization signal by counting a clock signal, and a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal. But that's fine. With this configuration, the frequency of the soft start pulse current and the frequency of the drive pulse can be set independently.
　一実施形態において、パワー回路は絶縁コンバータであってもよい。コンバータコントローラ、パルス電流発生器、クランプ回路は、一次側に設けられてもよい。フィードバック回路は、二次側に設けられたエラーアンプと、入力がエラーアンプの出力と接続され、出力がコンバータコントローラと接続された絶縁回路と、を含んでもよい。クランプ回路は、絶縁回路の出力をクランプしてもよい。この構成によれば、ソフトスタートに関するハードウェアを、一次側に集約できるため、ソフトスタートに関する信号を伝送するための絶縁素子が不要である。 In one embodiment, the power circuit may be an isolated converter. The converter controller, pulse current generator, and clamp circuit may be provided on the primary side. The feedback circuit may include an error amplifier provided on the secondary side, and an isolation circuit whose input is connected to the output of the error amplifier and whose output is connected to the converter controller. The clamp circuit may clamp the output of the isolation circuit. According to this configuration, hardware related to soft start can be integrated on the primary side, so an insulating element for transmitting signals related to soft start is not required.
　一実施形態において、パルス電流発生器は、ハイサイドトランジスタ（上アーム）とローサイドトランジスタ（下アーム）を直列接続してなるプッシュプル構成の出力段と、出力段の出力とソフトスタート用キャパシタの間に直列に接続された整流素子およびシリーズ抵抗と、を含んでもよい。 In one embodiment, the pulse current generator includes an output stage having a push-pull configuration in which a high-side transistor (upper arm) and a low-side transistor (lower arm) are connected in series, and between the output of the output stage and a soft-start capacitor. and a rectifying element and a series resistor connected in series to the rectifying element and the series resistor.
　一実施形態において、パルス電流発生器は、ローサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、出力段の出力とソフトスタート用キャパシタの間に接続された整流素子と、出力段の出力と接続されたプルアップ抵抗と、を含んでもよい。 In one embodiment, the pulse current generator includes an open-drain or open-collector output stage consisting of a low-side transistor, a rectifying element connected between the output of the output stage and a soft-start capacitor, and an output of the output stage. and a pull-up resistor connected to the pull-up resistor.
　一実施形態において、パルス電流発生器は、ハイサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、出力段の出力とソフトスタート用キャパシタの間に接続されたシリーズ抵抗と、を含んでもよい。 In one embodiment, the pulsed current generator may include an open-drain or open-collector output stage consisting of a high-side transistor, and a series resistor connected between the output of the output stage and a soft-start capacitor. good.
（実施形態）
　以下、好適な実施形態について、図面を参照しながら説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付するものとし、適宜重複した説明は省略する。また、実施形態は、開示および発明を限定するものではなく例示であって、実施形態に記述されるすべての特徴やその組み合わせは、必ずしも開示および発明の本質的なものであるとは限らない。 (Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. Identical or equivalent components, members, and processes shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are illustrative rather than limiting the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.
　本明細書において、「部材Ａが、部材Ｂと接続された状態」とは、部材Ａと部材Ｂが物理的に直接的に接続される場合のほか、部材Ａと部材Ｂが、それらの電気的な接続状態に実質的な影響を及ぼさない、あるいはそれらの結合により奏される機能や効果を損なわせない、その他の部材を介して間接的に接続される場合も含む。 In this specification, "a state in which member A is connected to member B" refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.
　同様に、「部材Ｃが、部材Ａと部材Ｂの間に接続された（設けられた）状態」とは、部材Ａと部材Ｃ、あるいは部材Ｂと部材Ｃが直接的に接続される場合のほか、それらの電気的な接続状態に実質的な影響を及ぼさない、あるいはそれらの結合により奏される機能や効果を損なわせない、その他の部材を介して間接的に接続される場合も含む。 Similarly, "a state in which member C is connected (provided) between member A and member B" refers to a state in which member A and member C or member B and member C are directly connected. In addition, it also includes cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.
　図１は、実施形態に係るスイッチング電源装置１００を備える回路システム１のブロック図である。回路システム１は、入力電源２、負荷４、スイッチング電源装置１００を備える。 FIG. 1 is a block diagram of a circuit system 1 including a switching power supply device 100 according to an embodiment. The circuit system 1 includes an input power source 2, a load 4, and a switching power supply device 100.
　スイッチング電源装置１００は、入力ライン（入力端子）１０２に入力電源２から入力電圧ＶＩＮを受ける。スイッチング電源装置１００の出力ライン（出力端子）１０４には、負荷４が接続される。スイッチング電源装置１００は、入力電源２からの電力を受け、負荷４に電力を供給する。スイッチング電源装置１００は、定電圧出力であってもよいし、定電流出力であってもよいが、本実施形態では、定電圧出力であり、所定の目標レベルＶＯＵＴ（ＲＥＦ）に安定化された出力電圧ＶＯＵＴを、負荷４に供給する。 The switching power supply device 100 receives an input voltage V IN from the input power supply 2 on an input line (input terminal) 102 . A load 4 is connected to an output line (output terminal) 104 of the switching power supply device 100. Switching power supply device 100 receives power from input power supply 2 and supplies power to load 4 . The switching power supply device 100 may output a constant voltage or a constant current, but in this embodiment, it outputs a constant voltage and is stabilized at a predetermined target level V OUT (REF). The output voltage V OUT is supplied to the load 4.
　スイッチング電源装置１００は、パワー回路１１０、フィードバック回路１２０、コンバータコントローラ１３０、パルス電流発生器１４０、クランプ回路１５０、ソフトスタート用キャパシタＣＳＳを備える。なお、図１に示す各ブロックは、スイッチング電源装置１００に実装される機能や処理を示しており、必ずしもハードウェアの単位や構成を示しているものではない。 The switching power supply device 100 includes a power circuit 110, a feedback circuit 120, a converter controller 130, a pulse current generator 140, a clamp circuit 150, and a soft start capacitor CSS . Note that each block shown in FIG. 1 represents a function or process implemented in the switching power supply device 100, and does not necessarily represent a hardware unit or configuration.
　パワー回路１１０は、スイッチング電源の主回路であり、少なくとも１個のスイッチング素子Ｍ１と、トランスやコイルなどの誘導素子（不図示）、整流回路（不図示）や平滑キャパシタ（不図示）を含む。パワー回路１１０の構成、トポロジーは特に限定されず、絶縁、非絶縁を問わない。たとえばパワー回路１１０は、フォワードコンバータ、フライバックコンバータ、ハーフブリッジコンバータ、フルブリッジコンバータなどが例示される。あるいはパワー回路１１０は、トランスの代わりにインダクタ（リアクトル）を含むトポロジーであってもよく、たとえば、降圧（Ｂｕｃｋ）コンバータ、昇圧（Ｂｏｏｓｔ）コンバータ、昇降圧（Ｂｕｃｋ－Ｂｏｏｓｔ）コンバータ、ＣｕｋコンバータやＳＥＰＩＣコンバータであってもよい。 The power circuit 110 is the main circuit of the switching power supply, and includes at least one switching element M1, an inductive element such as a transformer or a coil (not shown), a rectifier circuit (not shown), and a smoothing capacitor (not shown). The configuration and topology of the power circuit 110 are not particularly limited, and may be insulated or non-insulated. For example, the power circuit 110 is exemplified by a forward converter, a flyback converter, a half-bridge converter, a full-bridge converter, and the like. Alternatively, the power circuit 110 may have a topology including an inductor (reactor) instead of a transformer, such as a buck converter, a boost converter, a buck-boost converter, a Cuk converter, or a SEPIC. It may also be a converter.
　フィードバック回路１２０には、パワー回路１１０の出力電圧ＶＯＵＴを示す出力検出信号ＶＤＥＴがフィードバックされている。出力検出信号ＶＤＥＴは、出力電圧ＶＯＵＴであってもよいし、出力電圧ＶＯＵＴを抵抗やトランスによって分圧した電圧であってもよい。フィードバック回路１２０は、出力検出信号ＶＤＥＴと基準信号ＶＲＥＦの誤差に応じた誤差信号ＶＥＲＲを生成する。 An output detection signal V DET indicating the output voltage V OUT of the power circuit 110 is fed back to the feedback circuit 120 . The output detection signal V DET may be the output voltage V OUT or may be a voltage obtained by dividing the output voltage V OUT using a resistor or a transformer. The feedback circuit 120 generates an error signal V ERR according to the error between the output detection signal V DET and the reference signal V REF .
　たとえばフィードバック回路１２０は、エラーアンプ１２２を含む。エラーアンプ１２２の第１入力には出力検出信号ＶＤＥＴが入力され、エラーアンプ１２２の第２入力には、基準信号ＶＲＥＦが入力される。エラーアンプ１２２は、出力検出信号ＶＤＥＴと基準信号ＶＲＥＦの誤差を増幅し、誤差信号ＶＥＲＲを出力する。 For example, feedback circuit 120 includes an error amplifier 122. The output detection signal V DET is input to a first input of the error amplifier 122, and the reference signal V REF is input to a second input of the error amplifier 122. The error amplifier 122 amplifies the error between the output detection signal V DET and the reference signal V REF and outputs an error signal V ERR .
　エラーアンプ１２２は、オペアンプであってもよいし、トランスコンダクタンスアンプとキャパシタの組み合わせであってもよい。絶縁コンバータの場合、エラーアンプ１２２としてシャントレギュレータを利用してもよい。 The error amplifier 122 may be an operational amplifier or a combination of a transconductance amplifier and a capacitor. In the case of an isolated converter, a shunt regulator may be used as the error amplifier 122.
　コンバータコントローラ１３０は、誤差信号ＶＥＲＲに応じたデューティサイクルを有する駆動パルスＶＤＲＶを生成し、駆動パルスＶＤＲＶに応じてスイッチング素子Ｍ１を駆動する。 Converter controller 130 generates a drive pulse V DRV having a duty cycle according to error signal V ERR , and drives switching element M1 in accordance with drive pulse V DRV .
　ソフトスタート用キャパシタＣＳＳは、一端が接地されている。 One end of the soft start capacitor CSS is grounded.
　パルス電流発生器１４０は、時間とともにデューティサイクルが変化するソフトスタート用パルス電流ＩＰＳを生成し、ソフトスタート用キャパシタＣＳＳに供給する。「デューティサイクル」は、周期に対するオンレベル（たとえばハイ）の割合であり、ソフトスタート用パルス電流ＩＰＳは、パルス幅変調（ＰＷＭ）信号であってもよいし、パルス周波数変調（ＰＦＭ）信号であってもよい。ＰＷＭ信号の場合、周期が一定であり、オン時間が、時間とともに徐変する。ＰＦＭ信号の場合、オン時間が一定、もしくはオフ時間が一定であり、周波数（周期）が時間とともに徐変する。パルス電流発生器１４０はオン時は電流を出力し、オフ時は電流を遮断する。 The pulse current generator 140 generates a soft start pulse current I PS whose duty cycle changes over time, and supplies it to the soft start capacitor C SS . "Duty cycle" is the ratio of the on level (for example, high) to the period, and the soft start pulse current I PS may be a pulse width modulation (PWM) signal or a pulse frequency modulation (PFM) signal. There may be. In the case of a PWM signal, the period is constant, and the on time gradually changes over time. In the case of a PFM signal, the on time or off time is constant, and the frequency (period) gradually changes over time. The pulse current generator 140 outputs current when it is on, and cuts off the current when it is off.
　クランプ回路１５０は、ソフトスタート用キャパシタＣＳＳに発生する電圧（以下、ソフトスタート電圧という）ＶＳＳに応じたクランプレベルＶＣＬにて、誤差信号ＶＥＲＲをクランプする。すなわち、誤差信号ＶＥＲＲの上限が、クランプレベルＶＣＬとなる。 The clamp circuit 150 clamps the error signal V ERR at a clamp level V CL that corresponds to a voltage (hereinafter referred to as a soft start voltage) V SS generated in the soft start capacitor C SS . That is, the upper limit of the error signal V ERR becomes the clamp level V CL .
　以上がスイッチング電源装置１００の構成である。続いてその動作を説明する。 The above is the configuration of the switching power supply device 100. Next, its operation will be explained.
　図２は、スイッチング電源装置１００の起動時の動作波形図である。時刻ｔ１に、スイッチング電源装置１００の起動のトリガとなるスタート信号がアサートされる。スタート信号のアサートに応答して、パルス電流発生器１４０は、ソフトスタート用パルス電流ＩＰＳの生成を開始する。この例では、ソフトスタート用パルス電流ＩＰＳは、パルス幅変調されており、そのデューティサイクルは、時間とともに小さくなっていく。 FIG. 2 is an operational waveform diagram when the switching power supply device 100 is started up. At time t1 , a start signal that triggers the activation of switching power supply device 100 is asserted. In response to the assertion of the start signal, the pulse current generator 140 starts generating the soft start pulse current IPS . In this example, the soft start pulse current IPS is pulse width modulated and its duty cycle decreases over time.
　ソフトスタート用パルス電流ＩＰＳのデューティサイクルは、起動直後の第１期間Ｔ１（ｔ１～ｔ２）において、第１デューティサイクルｄ１、それに続く第２期間Ｔ２（ｔ２～ｔ３）において、第２デューティサイクルｄ２、それ以降の第３期間Ｔ３（ｔ３～）において、第３デューティサイクルｄ３を有する。ただし、ｄ１＞ｄ２＞ｄ３である。 The duty cycle of the soft start pulse current I PS is the first duty cycle d1 in the first period T1 (t 1 to t 2 ) immediately after startup, and the first duty cycle d1 in the second period T2 (t 2 to t 3 ) that follows. 2 duty cycle d2, and a third duty cycle d3 in the subsequent third period T3 (from t 3 ). However, d1>d2>d3.
　したがって、第１期間Ｔ１においては、ソフトスタート用キャパシタＣＳＳのソフトスタート電圧ＶＳＳの増加する傾きは、第１期間Ｔ１，第２期間Ｔ２、第３期間Ｔ３と順に小さくなっていく。クランプ回路１５０のクランプレベルＶＣＬは、ソフトスタート電圧ＶＳＳに追従して上昇していく。 Therefore, in the first period T1, the slope of increase of the soft start voltage V SS of the soft start capacitor C SS becomes smaller in the order of the first period T1, the second period T2, and the third period T3. The clamp level V CL of the clamp circuit 150 increases following the soft start voltage V SS .
　時刻ｔ４は、出力電圧ＶＯＵＴがその目標レベルＶＯＵＴ（ＲＥＦ）に到達するタイミング、言い換えると、出力検出信号ＶＤＥＴが基準信号ＶＲＥＦに到達するタイミングを表す。時刻ｔ４より前の期間ｔ１～ｔ４の間、誤差信号ＶＥＲＲは、クランプレベルＶＣＬでクランプされる。時刻ｔ４以降、誤差信号ＶＥＲＲは、フィードバックループの安定点の近傍に安定化される一方、クランプレベルＶＣＬは、上昇し続ける。そのため、クランプ回路１５０は、フィードバックループに影響を与えない。 Time t4 represents the timing at which the output voltage V OUT reaches its target level V OUT (REF) , in other words, the timing at which the output detection signal V DET reaches the reference signal V REF . During the period t 1 to t 4 before time t 4 , the error signal V ERR is clamped at the clamp level V CL . After time t4 , the error signal V ERR is stabilized near the stable point of the feedback loop, while the clamp level V CL continues to rise. Therefore, clamp circuit 150 does not affect the feedback loop.
　第３期間Ｔ３は、タイミングｔ４を含むように定められ、第３デューティサイクルｄ３の値は十分に小さく定められる。これにより、出力電圧ＶＯＵＴがその目標レベルＶＯＵＴ（ＲＥＦ）に到達したときに、出力電圧ＶＯＵＴの上昇速度が十分に抑制されているため、オーバーシュートを抑制できる。 The third period T3 is determined to include timing t4 , and the value of the third duty cycle d3 is determined to be sufficiently small. Thereby, when the output voltage V OUT reaches its target level V OUT (REF) , the rate of increase in the output voltage V OUT is sufficiently suppressed, so that overshoot can be suppressed.
　また、起動直後の第１期間Ｔ１では、ソフトスタート電圧ＶＳＳひいてはクランプレベルＶＣＬを高速に上昇させることで、出力電圧ＶＯＵＴを高速に上昇させることができ、起動時間を短縮できる。 Further, in the first period T1 immediately after startup, by quickly increasing the soft start voltage V SS and thus the clamp level V CL , the output voltage V OUT can be rapidly increased, and the startup time can be shortened.
　また第１期間Ｔ１と第３期間Ｔ３の間に、中間的なデューティサイクルｄ２を有する第２期間Ｔ２を挿入されている。もし、第２期間Ｔ２がなく、デューティサイクルｄ１からｄ３に直接変化すると、出力電圧ＶＯＵＴに不要な振動が発生するおそれがある。第２期間Ｔ２を挿入することで、出力電圧ＶＯＵＴに不要な振動を抑制できる。 Further, a second period T2 having an intermediate duty cycle d2 is inserted between the first period T1 and the third period T3. If there is no second period T2 and the duty cycle changes directly from d1 to d3, there is a risk that unnecessary vibrations will occur in the output voltage V OUT . By inserting the second period T2, unnecessary vibrations in the output voltage V OUT can be suppressed.
　本開示は、図１のブロック図や回路図として把握され、あるいは上述の説明から導かれるさまざまな装置、方法に及ぶものであり、特定の構成に限定されるものではない。以下、本開示の範囲を狭めるためではなく、本開示や本発明の本質や動作の理解を助け、またそれらを明確化するために、より具体的な構成例や実施例を説明する。 The present disclosure covers various devices and methods that can be understood as the block diagram and circuit diagram of FIG. 1 or derived from the above description, and is not limited to a specific configuration. More specific configuration examples and examples will be described below, not to narrow the scope of the present disclosure, but to help understand and clarify the essence and operation of the present disclosure and the present invention.
（実施例１）
　図３は、実施例１に係るスイッチング電源装置１００Ａの回路図である。スイッチング電源装置１００Ａは、非絶縁型のコンバータであり、パワー回路１１０Ａは、降圧コンバータのトポロジーを有する。パワー回路１１０Ａは、ハイサイドトランジスタ（スイッチングトランジスタ）Ｍ１Ｈ、ローサイドトランジスタ（同期整流トランジスタ）Ｍ１Ｌ、インダクタＬ１、出力キャパシタＣ１を含む。 (Example 1)
FIG. 3 is a circuit diagram of the switching power supply device 100A according to the first embodiment. The switching power supply device 100A is a non-insulated converter, and the power circuit 110A has a step-down converter topology. The power circuit 110A includes a high-side transistor (switching transistor) M1H, a low-side transistor (synchronous rectification transistor) M1L, an inductor L1, and an output capacitor C1.
　コンバータコントローラ１３０Ａは、パルス変調器１３２、ハイサイドドライバ１３４Ｈ、ローサイドドライバ１３４Ｌを含む。パルス変調器１３２は、誤差信号ＶＥＲＲに応じたデューティサイクルを有するパルス変調信号ＶＭＯＤを生成する。ハイサイドドライバ１３４Ｈおよびローサイドドライバ１３４Ｌは、パルス変調信号ＶＭＯＤに応じて、ハイサイドトランジスタＭ１ＨおよびローサイドトランジスタＭ１Ｌを相補的に駆動する。パルス変調器１３２は、パルス幅変調器であってもよいし、パルス周波数変調器であってもよい。 Converter controller 130A includes a pulse modulator 132, a high-side driver 134H, and a low-side driver 134L. Pulse modulator 132 generates a pulse modulated signal V MOD having a duty cycle responsive to error signal V ERR . High-side driver 134H and low-side driver 134L complementarily drive high-side transistor M1H and low-side transistor M1L according to pulse modulation signal V MOD . Pulse modulator 132 may be a pulse width modulator or a pulse frequency modulator.
　クランプ回路１５０Ａは、ＰＮＰ型のバイポーラトランジスタＱ１を含む。バイポーラトランジスタＱ１のコレクタは接地され、エミッタが、エラーアンプ１２２の出力、コンバータコントローラ１３０Ａの入力と接続される。バイポーラトランジスタＱ１のベースには、ソフトスタート電圧ＶＳＳが入力される。バイポーラトランジスタＱ１のベースエミッタ間電圧をＶｂｅとするとき、クランプ回路１５０ＡのクランプレベルＶＣＬは、
　ＶＣＬ＝ＶＳＳ＋Ｖｂｅ
となる。また、ＰＮＰ型のバイポーラトランジスタＱ１は、Ｐチャンネル型ＭＯＳＦＥＴを使用しても構わない。 Clamp circuit 150A includes a PNP type bipolar transistor Q1. The collector of bipolar transistor Q1 is grounded, and the emitter is connected to the output of error amplifier 122 and the input of converter controller 130A. A soft start voltage VSS is input to the base of the bipolar transistor Q1. When the base-emitter voltage of the bipolar transistor Q1 is Vbe, the clamp level VCL of the clamp circuit 150A is:
VCL = VSS +Vbe
becomes. Moreover, a P-channel type MOSFET may be used as the PNP type bipolar transistor Q1.
（実施例２）
　図４は、実施例２に係るスイッチング電源装置１００Ｂの回路図である。スイッチング電源装置１００Ｂは絶縁型のコンバータであり、パワー回路１１０Ｂは、フォワードコンバータであり、トランスＴ１、スイッチング素子Ｍ１、整流素子Ｄ１，Ｄ２、出力チョークコイルＬ０、出力キャパシタＣ０を含む。スイッチング素子Ｍ１は、トランスＴ１の一次巻線Ｗ１と接続される。整流素子Ｄ１，Ｄ２、出力チョークコイルＬ０、出力キャパシタＣ０は、二次巻線Ｗ２と接続される。 (Example 2)
FIG. 4 is a circuit diagram of a switching power supply device 100B according to the second embodiment. The switching power supply device 100B is an isolated converter, and the power circuit 110B is a forward converter and includes a transformer T1, a switching element M1, rectifying elements D1 and D2, an output choke coil L0, and an output capacitor C0. Switching element M1 is connected to primary winding W1 of transformer T1. Rectifying elements D1 and D2, output choke coil L0, and output capacitor C0 are connected to secondary winding W2.
　フィードバック回路１２０Ｂは、エラーアンプ１２２および絶縁回路１２４を含む。エラーアンプ１２２は、二次側に設けられる。絶縁回路１２４は、一次側と二次側の境界に配置され、絶縁回路１２４の入力が、エラーアンプ１２２の出力と接続され、絶縁回路１２４の出力が、コンバータコントローラ１３０Ｂの入力と接続される。 The feedback circuit 120B includes an error amplifier 122 and an isolation circuit 124. Error amplifier 122 is provided on the secondary side. Isolation circuit 124 is arranged at the boundary between the primary side and the secondary side, the input of isolation circuit 124 is connected to the output of error amplifier 122, and the output of isolation circuit 124 is connected to the input of converter controller 130B.
　絶縁回路１２４は、フォトカプラ１２４Ｂを用いることができる。エラーアンプ１２２は、シャントレギュレータであり、出力検出信号ＶＤＥＴと基準電圧ＶＲＥＦの誤差に応じた誤差信号ＩＥＲＲを、フォトカプラ１２４Ｂの発光素子（フォトダイオード）に供給する。フォトカプラ１２４Ｂの受光素子（フォトトランジスタ）には、誤差電流ＩＥＲＲに応じた電流ＩＦＢが流れる。 The insulation circuit 124 can use a photocoupler 124B. The error amplifier 122 is a shunt regulator, and supplies an error signal I ERR corresponding to the error between the output detection signal V DET and the reference voltage V REF to the light emitting element (photo diode) of the photo coupler 124B. A current IFB corresponding to the error current IERR flows through the light receiving element (phototransistor) of the photocoupler 124B.
　コンバータコントローラ１３０Ｂは、パルス変調器１３２およびドライバ１３４、抵抗Ｒ１１を含む。抵抗Ｒ１１により、フォトカプラ１２４Ｂの受光素子に流れる電流が、電圧信号である誤差信号ＶＥＲＲに変換される。パルス変調器１３２は、誤差信号ＶＥＲＲに応じたデューティサイクルを有するパルス変調信号ＶＭＯＤを生成する。ドライバ１３４は、パルス変調信号ＶＭＯＤに応じた駆動パルスＶＤＲＶを生成し、スイッチング素子Ｍ１のゲートに供給する。 Converter controller 130B includes a pulse modulator 132, a driver 134, and a resistor R11. The resistor R11 converts the current flowing through the light receiving element of the photocoupler 124B into an error signal V ERR which is a voltage signal. Pulse modulator 132 generates a pulse modulated signal V MOD having a duty cycle responsive to error signal VERR. The driver 134 generates a drive pulse V DRV according to the pulse modulation signal V MOD and supplies it to the gate of the switching element M1.
　クランプ回路１５０は、コンバータコントローラ１３０Ｂ、パルス電流発生器１４０とともに、一次側に設けられる。クランプ回路１５０は、絶縁回路１２４の出力、パルス変調器１３２の入力と接続される。 Clamp circuit 150 is provided on the primary side together with converter controller 130B and pulse current generator 140. Clamp circuit 150 is connected to the output of isolation circuit 124 and the input of pulse modulator 132.
　以上がスイッチング電源装置１００Ｂの構成である。このスイッチング電源装置１００Ｂによれば、絶縁コンバータにおいても、起動の高速化と、オーバーシュートの抑制を両立できる。 The above is the configuration of the switching power supply device 100B. According to this switching power supply device 100B, even in an isolated converter, it is possible to achieve both faster startup and suppression of overshoot.
　また、ソフトスタートに関するハードウェアを、一次側に集約できるため、ソフトスタートに関する信号を伝送するための絶縁素子が不要である。これによりスイッチング電源装置１００Ｂコストアップを抑えることができる。 Additionally, since the hardware related to soft start can be consolidated on the primary side, there is no need for an insulating element for transmitting signals related to soft start. This makes it possible to suppress an increase in the cost of the switching power supply device 100B.
（実施例３）
　図５は、スイッチング電源装置１００Ｃの回路図である。スイッチング電源装置１００Ｃは、スイッチング電源装置１００Ｂと同様に絶縁コンバータである。 (Example 3)
FIG. 5 is a circuit diagram of the switching power supply device 100C. The switching power supply device 100C is an isolated converter like the switching power supply device 100B.
　本実施例において、駆動パルスＶＤＲＶおよびソフトスタート用パルス電流ＩＰＳは、パルス幅変調（ＰＷＭ）信号である。駆動パルスＶＤＲＶの周波数、すなわちスイッチング周波数と、ソフトスタート用パルス電流ＩＰＳの周波数が等しい。 In this embodiment, the drive pulse V DRV and the soft start pulse current I PS are pulse width modulated (PWM) signals. The frequency of the drive pulse VDRV , that is, the switching frequency, and the frequency of the soft start pulse current IPS are equal.
　パルス電流発生器１４０Ｃは、プロセッサ１４２、カウンタ１４４、電流ドライバ１４６を含む。 The pulse current generator 140C includes a processor 142, a counter 144, and a current driver 146.
　プロセッサ１４２は、ソフトスタート用パルス電流ＩＰＳのデューティサイクルの設定値ＤＳＥＴ、および、ソフトスタート用パルス電流ＩＰＳの周波数ｆＳＳの設定値ＦＳＥＴを生成する。図２のシーケンスに従う場合、設定値ＤＳＥＴは、第１期間Ｔ１において第１値ｄ１をとり、第２期間Ｔ２において第２値ｄ２をとり、第３期間Ｔ３において第３値ｄ３をとる。 The processor 142 generates a set value D SET of the duty cycle of the soft start pulse current I PS and a set value F SET of the frequency f SS of the soft start pulse current I PS . When following the sequence of FIG. 2, the set value D SET takes a first value d1 in the first period T1, a second value d2 in the second period T2, and a third value d3 in the third period T3.
　カウンタ１４４は、デジタルＰＷＭ（ＤＰＷＭ）回路であり、パルス幅変調器として機能する。カウンタ１４４は、所定の周波数ｆＳＳを有し、設定値ＤＳＥＴに応じたデューティサイクルを有するソフトスタート用パルス信号ＶＰＳを生成する。 Counter 144 is a digital PWM (DPWM) circuit and functions as a pulse width modulator. The counter 144 generates a soft start pulse signal V PS having a predetermined frequency f SS and a duty cycle according to the set value D SET .
　カウンタ１４４には、デューティサイクルの設定値ＤＳＥＴと、ソフトスタート用パルス電流ＩＰＳの周波数ｆＳＳの設定値ＦＳＥＴが入力される。カウンタ１４４は、クロック信号ＣＬＫをカウントすることにより、ソフトスタート用パルス信号ＶＰＳを生成する。具体的には、カウンタ１４４は、クロック信号ＣＬＫに応じてカウントアップし、カウント開始から、カウント値が設定値ＤＳＥＴに達するまでの間、第１レベル（たとえばハイ）を出力し、その後、カウント値が設定値ＦＳＥＴに達するまでの間、第２レベル（たとえばロー）を出力する。カウント値が設定値ＦＳＥＴに達すると、カウンタ１４４はリセットされ、同じ動作を繰り返す。 A set value D SET of the duty cycle and a set value F SET of the frequency f SS of the soft start pulse current I PS are input to the counter 144 . The counter 144 generates a soft start pulse signal VPS by counting the clock signal CLK. Specifically, the counter 144 counts up in accordance with the clock signal CLK, outputs a first level (for example, high) from the start of counting until the count value reaches the set value DSET , and then outputs the first level (for example, high). A second level (for example, low) is output until the value reaches the set value F SET . When the count value reaches the set value F SET , the counter 144 is reset and repeats the same operation.
　電流ドライバ１４６は、ソフトスタート用パルス信号ＶＰＳに応じて、ソフトスタート用パルス電流ＩＰＳを生成する。電流ドライバ１４６は、ソフトスタート用パルス信号ＶＰＳが第１レベル（たとえばハイ）のとき、電流を出力し、ソフトスタート用パルス信号ＶＰＳが第２レベル（たとえばロー）のとき、電流を遮断する。 The current driver 146 generates a soft start pulse current I PS in response to the soft start pulse signal V PS . The current driver 146 outputs current when the soft start pulse signal VPS is at a first level (for example, high), and cuts off the current when the soft start pulse signal VPS is at a second level (for example, low). .
　このように、カウンタ（ＤＰＷＭ回路）を利用することで、デューティサイクルが変化するソフトスタート用パルス電流ＩＰＳを生成できる。 In this way, by using the counter (DPWM circuit), it is possible to generate the soft start pulse current IPS whose duty cycle changes.
　パルス電流発生器１４０Ｃは、ソフトスタート用パルス電流ＩＰＳ（パルス信号ＶＰＳ）の周期（１／ｆＳＳ）ごとにアサートされる同期信号ＶＳＹＮＣを生成する。同期信号ＶＳＹＮＣは、コンバータコントローラ１３０Ｃに供給される。 The pulse current generator 140C generates a synchronization signal V SYNC that is asserted every cycle (1/f SS ) of the soft start pulse current I PS (pulse signal V PS ). Synchronization signal V SYNC is provided to converter controller 130C.
　コンバータコントローラ１３０Ｃは、パルス幅変調器１３２Ｃおよびドライバ１３４を含む。パルス幅変調器１３２Ｃには、パルス電流発生器１４０Ｃから同期信号ＶＳＹＮＣが供給される。パルス電流発生器１４０Ｃは、同期信号ＶＳＹＮＣと同期して、パルス幅変調信号ＶＰＷＭを生成する。 Converter controller 130C includes a pulse width modulator 132C and a driver 134. A synchronizing signal V SYNC is supplied to the pulse width modulator 132C from the pulse current generator 140C. Pulse current generator 140C generates pulse width modulation signal V PWM in synchronization with synchronization signal V SYNC .
　たとえばコンバータコントローラ１３０Ｃは、ＰＷＭコンパレータ１７０およびオシレータ１７２を含む。オシレータ１７２は、同期信号ＶＳＹＮＣと同期して、ソフトスタート用パルス信号ＶＰＳの周波数と同じ周波数を有する周期信号ＶＯＳＣを生成する。周期信号ＶＯＳＣは、三角波やのこぎり波である。ＰＷＭコンパレータ１７０は、周期信号ＶＯＳＣを、誤差信号ＶＥＲＲと比較し、ＰＷＭ信号ＶＰＷＭを生成する。この構成により、ＰＷＭ信号ＶＰＷＭの周波数と、ソフトスタート用パルス電流ＩＰＳの周波数を等しくすることができる。 For example, converter controller 130C includes a PWM comparator 170 and an oscillator 172. The oscillator 172 generates a periodic signal V OSC having the same frequency as the soft start pulse signal V PS in synchronization with the synchronization signal V SYNC . The periodic signal V OSC is a triangular wave or a sawtooth wave. PWM comparator 170 compares periodic signal V OSC with error signal V ERR and generates PWM signal V PWM . With this configuration, the frequency of the PWM signal VPWM and the frequency of the soft start pulse current IPS can be made equal.
　パワー回路１１０Ｃのスイッチング周波数と、ソフトスタート用パルス電流ＩＰＳの周波数がずれていると、ビートにより、出力電圧ＶＯＵＴが変動する。これに対して、スイッチング周波数とソフトスタート用パルス電流ＩＰＳの周波数を一致させることにより、ビートによる出力電圧の振動を抑制できる。 If the switching frequency of the power circuit 110C and the frequency of the soft start pulse current IPS are different from each other, the output voltage V OUT will fluctuate due to the beat. On the other hand, by matching the switching frequency with the frequency of the soft start pulse current IPS , it is possible to suppress vibrations in the output voltage due to beats.
　図６は、電流ドライバ１４６の第１の構成例（１４６ａ）を示す回路図である。電流ドライバ１４６ａは、プッシュプル構成の出力段１４８ａ、整流素子Ｄ２１、シリーズ抵抗Ｒ２１を含む。出力段１４８ａは、ソフトスタート用パルス信号ＶＰＳの反転信号ＶＰＳ＼（＼は論理反転を表す）に応じてスイッチングする。整流素子Ｄ２１およびシリーズ抵抗Ｒ２１は、出力段１４８ａの出力と、ソフトスタート用キャパシタＣＳＳの間に直列に接続される。 FIG. 6 is a circuit diagram showing a first configuration example (146a) of the current driver 146. Current driver 146a includes an output stage 148a with a push-pull configuration, a rectifying element D21, and a series resistor R21. The output stage 148a switches in response to an inverted signal V PS \ (\ represents logical inversion) of the soft start pulse signal V PS . Rectifying element D21 and series resistor R21 are connected in series between the output of output stage 148a and soft start capacitor CSS .
　出力段１４８ａのハイサイドのＰチャンネルＭＯＳＦＥＴがオンとなると、整流素子Ｄ２１およびシリーズ抵抗Ｒ２１を介して、ソフトスタート用パルス電流ＩＰＳがソフトスタート用キャパシタＣＳＳに供給される。出力段１４８ａのローサイドのＮチャンネルＭＯＳＦＥＴがオンとなると、出力段１４８ａの出力は０Ｖとなるが、整流素子Ｄ２１が挿入されているため、ソフトスタート用パルス電流ＩＰＳが遮断され、ソフトスタート用キャパシタＣＳＳの電荷は充電も放電されず、ＩＰＳ＝０の状態となる。 When the high-side P-channel MOSFET of output stage 148a is turned on, soft-start pulse current IPS is supplied to soft-start capacitor CSS via rectifier D21 and series resistor R21. When the low-side N-channel MOSFET of the output stage 148a turns on, the output of the output stage 148a becomes 0V, but since the rectifying element D21 is inserted, the soft start pulse current I PS is cut off, and the soft start capacitor The charge on C SS is neither charged nor discharged, and the state becomes I PS =0.
　図７は、電流ドライバ１４６の第２の構成例（１４６ｂ）を示す回路図である。電流ドライバ１４６ｂは、ローサイドトランジスタＭ２２を含むオープンドレイン型（またはオープンコレクタ型）の出力段１４８ｂ、プルアップ抵抗Ｒ２２、整流素子Ｄ２２を含む。 FIG. 7 is a circuit diagram showing a second configuration example (146b) of the current driver 146. The current driver 146b includes an open drain type (or open collector type) output stage 148b including a low-side transistor M22, a pull-up resistor R22, and a rectifier D22.
　出力段１４８ｂは、ソフトスタート用パルス信号ＶＰＳの反転信号ＶＰＳ＼に応じてスイッチングする。出力段１４８ｂのＮチャンネルＭＯＳＦＥＴがオフとなると、プルアップ抵抗Ｒ２２および整流素子Ｄ２２を介して、ソフトスタート用パルス電流ＩＰＳがソフトスタート用キャパシタＣＳＳに供給される。出力段１４８ｂのＮチャンネルＭＯＳＦＥＴがオンとなると、出力段１４８ｂの出力は０Ｖとなるが、整流素子Ｄ２２が挿入されているため、ソフトスタート用パルス電流ＩＰＳが遮断され、ソフトスタート用キャパシタＣＳＳの電荷は充電も放電されず、ＩＰＳ＝０の状態となる。 The output stage 148b switches in response to the inverted signal V PS \ of the soft start pulse signal V PS . When the N-channel MOSFET of the output stage 148b is turned off, the soft-start pulse current IPS is supplied to the soft-start capacitor CSS via the pull-up resistor R22 and the rectifier D22. When the N-channel MOSFET of the output stage 148b is turned on, the output of the output stage 148b becomes 0V, but since the rectifying element D22 is inserted, the soft start pulse current I PS is cut off, and the soft start capacitor C SS The charge is neither charged nor discharged, resulting in a state of I PS =0.
　図８は、電流ドライバ１４６の第３の構成例（１４６ｃ）を示す回路図である。電流ドライバ１４６ｃは、ハイサイドトランジスタＭ２３を含むオープンドレイン型（またはオープンコレクタ型）の出力段１４８ｃおよびシリーズ抵抗Ｒ２３を含む。 FIG. 8 is a circuit diagram showing a third configuration example (146c) of the current driver 146. Current driver 146c includes an open drain type (or open collector type) output stage 148c including a high side transistor M23 and a series resistor R23.
　出力段１４８ｃは、ソフトスタート用パルス信号ＶＰＳの反転信号ＶＰＳ＼に応じてスイッチングする。出力段１４８ｃのＰチャンネルＭＯＳＦＥＴがオンとなると、シリーズ抵抗Ｒ２３を介して、ソフトスタート用パルス電流ＩＰＳがソフトスタート用キャパシタＣＳＳに供給される。出力段１４８ｃのＰチャンネルＭＯＳＦＥＴがオフとなると、出力段１４８ｃの出力はハイインピーダンスとなり、ソフトスタート用パルス電流ＩＰＳが遮断され、ソフトスタート用キャパシタＣＳＳの電荷は充電も放電されず、ＩＰＳ＝０の状態となる。 The output stage 148c switches in response to the inverted signal V PS \ of the soft start pulse signal V PS . When the P-channel MOSFET of the output stage 148c is turned on, the soft start pulse current I PS is supplied to the soft start capacitor C SS via the series resistor R23. When the P-channel MOSFET of the output stage 148c is turned off, the output of the output stage 148c becomes high impedance, the soft start pulse current I PS is cut off, and the charge of the soft start capacitor C SS is neither charged nor discharged, and the I PS =0.
　電流ドライバ１４６の構成は、図６～図８に限定されない。たとえば電流ドライバ１４６は、オン、オフが切り替え可能な定電流源で構成してもよい。 The configuration of the current driver 146 is not limited to those shown in FIGS. 6 to 8. For example, the current driver 146 may be configured with a constant current source that can be turned on and off.
（実施例４）
　図９は、スイッチング電源装置１００Ｄの回路図である。スイッチング電源装置１００Ｄは、スイッチング電源装置１００Ｂや１００Ｃと同様に絶縁コンバータである。 (Example 4)
FIG. 9 is a circuit diagram of switching power supply device 100D. Switching power supply device 100D is an isolated converter like switching power supply devices 100B and 100C.
　本実施例において、駆動パルスＶＤＲＶおよびソフトスタート用パルス電流ＩＰＳは、パルス幅変調（ＰＷＭ）信号である。駆動パルスＶＤＲＶの周波数、すなわちスイッチング周波数は、ソフトスタート用パルス電流ＩＰＳの周波数のｍ倍、または１／ｍ倍である。ｍは自然数である。なお、ｍ＝１とした場合は、実施例３と等価である。 In this embodiment, the drive pulse V DRV and the soft start pulse current I PS are pulse width modulated (PWM) signals. The frequency of the drive pulse VDRV , ie, the switching frequency, is m times or 1/m times the frequency of the soft start pulse current IPS . m is a natural number. Note that when m=1, this is equivalent to the third embodiment.
　パルス電流発生器１４０Ｄは、第１カウンタ１４４および電流ドライバ１４６を含む。第１カウンタ１４４は、プロセッサ１４２から、ソフトスタート用パルス電流ＩＰＳの周波数の設定値ＦＳＥＴ１と、デューティサイクルの設定値ＤＳＥＴを受け、ソフトスタート用パルス信号ＶＰＳを生成する。電流ドライバ１４６は、ソフトスタート用パルス信号ＶＰＳに応じたソフトスタート用パルス電流ＩＰＳを出力する。 Pulse current generator 140D includes a first counter 144 and a current driver 146. The first counter 144 receives a frequency setting value F SET1 and a duty cycle setting value D SET of the soft start pulse current I PS from the processor 142, and generates a soft start pulse signal V PS . The current driver 146 outputs a soft start pulse current I PS corresponding to the soft start pulse signal V PS .
　コンバータコントローラ１３０Ｄは、パルス幅変調器１３２Ｃおよびドライバ１３４に加えて、同期信号発生器１３６を含む。 Converter controller 130D includes a synchronization signal generator 136 in addition to pulse width modulator 132C and driver 134.
　同期信号発生器１３６は、パルス電流発生器１４０が生成するソフトスタート用パルス電流ＩＰＳのｍ倍、または１／ｍ倍の周波数を有する同期信号ＶＳＹＮＣを生成する。同期信号発生器１３６は、第２カウンタ１３８を含む。第２カウンタ１３８には、デジタルプロセッサ２００から、同期信号ＶＳＹＮＣの周波数、すなわちスイッチング素子Ｍ１のスイッチング周波数を規定する周波数設定値ＦＳＥＴ２が供給される。第２カウンタ１３８は、クロック信号ＣＬＫに応じてカウントアップし、カウント値が、周波数設定値ＦＳＥＴ２に達すると、同期信号ＶＳＹＮＣをアサートし、リセットする動作を繰り返す。同期信号ＶＳＹＮＣは、コンバータコントローラ１３０Ｃに供給される。 The synchronization signal generator 136 generates a synchronization signal V SYNC having a frequency m times or 1/m times the soft start pulse current I PS generated by the pulse current generator 140 . Synchronization signal generator 136 includes a second counter 138. The second counter 138 is supplied with a frequency setting value F SET2 that defines the frequency of the synchronization signal V SYNC , that is, the switching frequency of the switching element M1, from the digital processor 200. The second counter 138 counts up in accordance with the clock signal CLK, and when the count value reaches the frequency setting value F SET2 , repeats the operation of asserting the synchronization signal V SYNC and resetting it. Synchronization signal V SYNC is provided to converter controller 130C.
　この構成によれば、実施例３と同様に、ビートによる出力変動を抑制できる。なお、実施例４において、ＦＳＥＴ１とＦＳＥＴ２を同じ値とすれば、スイッチング周波数とソフトスタート用パルス電流ＩＰＳの周波数を同一にできる。 According to this configuration, similarly to the third embodiment, output fluctuations due to beats can be suppressed. In the fourth embodiment, if F SET1 and F SET2 are set to the same value, the switching frequency and the frequency of the soft start pulse current IPS can be made the same.
（変形例）
　上述した実施形態は例示であり、それらの各構成要素や各処理プロセスの組み合わせにいろいろな変形例が可能なことが当業者に理解される。以下、こうした変形例について説明する。 (Modified example)
The embodiments described above are illustrative, and those skilled in the art will understand that various modifications can be made to the combinations of their constituent elements and processing processes. Hereinafter, such modified examples will be explained.
（変形例１）
　図２の例では、ソフトスタート用パルス電流ＩＰＳのデューティサイクルが、ｄ１，ｄ２，ｄ３の３値で変化したがその限りでない。フィードバック回路１２０の応答速度がある程度速い場合は、第２期間Ｔ２を省略し、デューティサイクルをｄ１とｄ３の２値で変化させてもよい。あるいは、ソフトスタート用パルス電流ＩＰＳのデューティサイクルを、４値以上で変化させてもよいし、連続的に変化させてもよい。 (Modification 1)
In the example of FIG. 2, the duty cycle of the soft start pulse current IPS changes in three values d1, d2, and d3, but this is not the case. If the response speed of the feedback circuit 120 is relatively fast, the second period T2 may be omitted and the duty cycle may be changed between two values, d1 and d3. Alternatively, the duty cycle of the soft start pulse current IPS may be changed by four or more values, or may be changed continuously.
　あるいは、ソフトスタート用パルス電流ＩＰＳのデューティサイクルを、１値で固定してもよい。たとえば高速起動が要求されないアプリケーションでは、オーバーシュートが発生しない程度の一定のデューティサイクルを有するソフトスタート用パルス電流ＩＰＳを生成すればよく、この場合、スイッチング電源装置１００の出力電圧ＶＯＵＴを一定の傾きで上昇させることができる。 Alternatively, the duty cycle of the soft start pulse current IPS may be fixed at one value. For example, in applications that do not require high-speed startup, it is sufficient to generate a soft-start pulse current IPS with a constant duty cycle that does not cause overshoot.In this case, the output voltage VOUT of the switching power supply 100 is It can be raised by tilting.
（変形例２）
　絶縁コンバータに関連する実施例２～実施例４で説明した各ブロックの構成や特徴は、非絶縁コンバータに関連する実施例１にも適用可能である。 (Modification 2)
The configurations and features of each block described in Examples 2 to 4 related to isolated converters can also be applied to Example 1 related to non-isolated converters.
（付記）
　本明細書には以下の技術が開示される。 (Additional note)
The following technology is disclosed in this specification.
（項目１）
　スイッチング素子を含むパワー回路と、
　前記パワー回路の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するフィードバック回路と、
　前記誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、前記駆動パルスに応じて前記スイッチング素子を駆動するコンバータコントローラと、
　ソフトスタート用キャパシタと、
　ソフトスタート用パルス電流を生成し、前記ソフトスタート用キャパシタに供給するパルス電流発生器と、
　前記ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、前記誤差信号をクランプするクランプ回路と、
　を備える、スイッチング電源装置。 (Item 1)
A power circuit including a switching element,
a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal;
a converter controller that generates a drive pulse having a duty cycle according to the error signal and drives the switching element according to the drive pulse;
soft start capacitor,
a pulse current generator that generates a pulse current for soft start and supplies it to the soft start capacitor;
a clamp circuit that clamps the error signal at a clamp level that corresponds to the voltage generated in the soft start capacitor;
A switching power supply device comprising:
（項目２）
　前記パルス電流発生器は、起動からの経過時間に応じて、前記ソフトスタート用パルス電流のデューティサイクルを変化させる、項目１に記載のスイッチング電源装置。 (Item 2)
The switching power supply device according to item 1, wherein the pulse current generator changes the duty cycle of the soft start pulse current depending on the elapsed time from startup.
（項目３）
　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
　前記駆動パルスの周波数と、前記ソフトスタート用パルス電流の周波数が等しい、項目１または２に記載のスイッチング電源装置。 (Item 3)
The driving pulse and the soft start pulse current are pulse width modulated signals,
The switching power supply device according to item 1 or 2, wherein the frequency of the drive pulse and the frequency of the soft start pulse current are equal.
（項目４）
　前記パルス電流発生器は、前記ソフトスタート用パルス電流の周波数の設定値と、デューティサイクルの設定値と、を受け、クロック信号をカウントすることにより、ソフトスタート用パルス信号を生成するカウンタを含み、前記ソフトスタート用パルス電流の周期ごとにアサートされる同期信号を生成可能であり、
　前記コンバータコントローラは、前記同期信号と同期して前記駆動パルスを生成するパルス幅変調器を含む、項目３に記載のスイッチング電源装置。 (Item 4)
The pulse current generator includes a counter that receives a frequency setting value and a duty cycle setting value of the soft start pulse current, and generates a soft start pulse signal by counting a clock signal, It is possible to generate a synchronization signal that is asserted every cycle of the soft start pulse current,
The switching power supply device according to item 3, wherein the converter controller includes a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal.
（項目５）
　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
　ｍを自然数とするとき、前記駆動パルスの周波数は、前記ソフトスタート用パルス電流の周波数のｍ倍または１／ｍ倍である、項目１または２に記載のスイッチング電源装置。 (Item 5)
The driving pulse and the soft start pulse current are pulse width modulated signals,
3. The switching power supply device according to item 1 or 2, wherein the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current, where m is a natural number.
（項目６）
　前記パルス電流発生器は、前記ソフトスタート用パルス電流の周波数の設定値と、デューティサイクルの設定値と、を受け、クロック信号をカウントすることにより、ソフトスタート用パルス信号を生成する第１カウンタを含み、
　前記コンバータコントローラは、
　前記駆動パルスの周波数の設定値を受け、前記クロック信号をカウントすることにより同期信号を生成する第２カウンタと、
　前記同期信号と同期して前記駆動パルスを生成するパルス幅変調器と、
　を含む、項目３または５に記載のスイッチング電源装置。 (Item 6)
The pulse current generator receives a frequency setting value and a duty cycle setting value of the soft start pulse current, and operates a first counter that generates a soft start pulse signal by counting a clock signal. including,
The converter controller includes:
a second counter that receives a set value of the frequency of the drive pulse and generates a synchronization signal by counting the clock signal;
a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal;
The switching power supply device according to item 3 or 5, comprising:
（項目７）
　前記パワー回路は絶縁コンバータであり、
　前記コンバータコントローラ、前記パルス電流発生器、前記クランプ回路は、一次側に設けられ、
　前記フィードバック回路は、
　二次側に設けられたエラーアンプと、
　入力が前記エラーアンプの出力と接続され、出力が前記コンバータコントローラと接続された絶縁回路と、
　を含み、
　前記クランプ回路は、前記絶縁回路の前記出力をクランプする、項目１から６のいずれかに記載のスイッチング電源装置。 (Item 7)
the power circuit is an isolated converter;
The converter controller, the pulse current generator, and the clamp circuit are provided on the primary side,
The feedback circuit is
An error amplifier provided on the secondary side,
an isolation circuit whose input is connected to the output of the error amplifier and whose output is connected to the converter controller;
including;
7. The switching power supply device according to any one of items 1 to 6, wherein the clamp circuit clamps the output of the insulation circuit.
（項目８）
　前記パルス電流発生器は、
　プッシュプル構成の出力段と、
　前記出力段の出力と前記ソフトスタート用キャパシタの間に直列に接続された整流素子およびシリーズ抵抗と、
　を含む、項目１から７のいずれかに記載のスイッチング電源装置。 (Item 8)
The pulse current generator is
An output stage with a push-pull configuration,
a rectifying element and a series resistor connected in series between the output of the output stage and the soft start capacitor;
The switching power supply device according to any one of items 1 to 7, including:
（項目９）
　前記パルス電流発生器は、
　ローサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、
　前記出力段の出力と前記ソフトスタート用キャパシタの間に接続された整流素子と、
　前記出力段の出力と接続されたプルアップ抵抗と、
　を含む、項目１から７のいずれかに記載のスイッチング電源装置。 (Item 9)
The pulse current generator is
An open-drain or open-collector output stage consisting of a low-side transistor,
a rectifying element connected between the output of the output stage and the soft start capacitor;
a pull-up resistor connected to the output of the output stage;
The switching power supply device according to any one of items 1 to 7, including:
（項目１０）
　前記パルス電流発生器は、
　ハイサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、
　前記出力段の出力と前記ソフトスタート用キャパシタの間に接続されたシリーズ抵抗と、
　を含む、項目１から７のいずれかに記載のスイッチング電源装置。 (Item 10)
The pulse current generator is
An open-drain or open-collector output stage consisting of a high-side transistor,
a series resistor connected between the output of the output stage and the soft start capacitor;
The switching power supply device according to any one of items 1 to 7, including:
（項目１１）
　前記クランプ回路は、ベースに前記ソフトスタート用キャパシタの電圧を受け、エミッタが前記コンバータコントローラの入力と接続されたトランジスタを含む、項目１から１０のいずれかに記載のスイッチング電源装置。 (Item 11)
11. The switching power supply device according to any one of items 1 to 10, wherein the clamp circuit includes a transistor whose base receives the voltage of the soft start capacitor and whose emitter is connected to the input of the converter controller.
（項目１２）
　スイッチング素子を含むスイッチング電源装置の制御方法であって、
　前記スイッチング電源装置の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するステップと、
　前記誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、前記駆動パルスに応じて前記スイッチング素子を駆動するステップと、
　ソフトスタート用パルス電流を生成し、ソフトスタート用パルス電流によってソフトスタート用キャパシタを充電または放電するステップと、
　前記ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、前記誤差信号をクランプするステップと、
　を備える、制御方法。 (Item 12)
A method for controlling a switching power supply device including a switching element, the method comprising:
generating an error signal according to an error between an output detection signal indicating an output signal of the switching power supply and a reference signal;
generating a drive pulse having a duty cycle according to the error signal, and driving the switching element according to the drive pulse;
generating a soft-start pulse current and charging or discharging a soft-start capacitor with the soft-start pulse current;
clamping the error signal at a clamp level according to the voltage generated in the soft start capacitor;
A control method comprising:
（項目１３）
　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
　前記駆動パルスの周波数と、前記ソフトスタート用パルス電流の周波数が等しい、項目１２に記載の制御方法。 (Item 13)
The driving pulse and the soft start pulse current are pulse width modulated signals,
13. The control method according to item 12, wherein the frequency of the drive pulse and the frequency of the soft start pulse current are equal.
（項目１４）
　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
　ｍを自然数とするとき、前記駆動パルスの周波数は、前記ソフトスタート用パルス電流の周波数のｍ倍または１／ｍ倍である、項目１２に記載の制御方法。 (Item 14)
The driving pulse and the soft start pulse current are pulse width modulated signals,
The control method according to item 12, wherein the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current, where m is a natural number.
　本開示に係る実施形態について、具体的な用語を用いて説明したが、この説明は、理解を助けるための例示に過ぎず、本開示あるいは請求の範囲を限定するものではない。本発明の範囲は、請求の範囲によって規定されるものであり、したがって、ここでは説明しない実施形態、実施例、変形例も、本発明の範囲に含まれる。 Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to aid understanding, and does not limit the scope of the present disclosure or claims. The scope of the present invention is defined by the claims, and therefore embodiments, examples, and modifications not described here are also included within the scope of the present invention.
　本開示は、スイッチング電源装置に関する。 The present disclosure relates to a switching power supply device.
　１　回路システム
　２　入力電源
　４　負荷
　１００，１００Ａ，１００Ｂ，１００Ｃ，１００Ｄ　スイッチング電源装置
　１０２　入力ライン
　１０４　出力ライン
　１１０，１１０Ａ，１１０Ｂ，１１０Ｃ　パワー回路
　Ｍ１　スイッチング素子
　Ｍ１Ｈ　ハイサイドトランジスタ
　Ｍ１Ｌ　ローサイドトランジスタ
　Ｍ２２　ローサイドトランジスタ
　Ｍ２３　ハイサイドトランジスタ
　Ｑ１　バイポーラトランジスタ
　Ｒ１１　抵抗
　Ｒ２１　シリーズ抵抗
　Ｒ２２　プルアップ抵抗
　Ｒ２３　シリーズ抵抗
　Ｔ１　トランス
　Ｗ１　一次巻線
　Ｗ２　二次巻線
　Ｃ０，Ｃ１　出力キャパシタ
　Ｄ１，Ｄ２，Ｄ２１，Ｄ２２　整流素子
　Ｌ０　出力チョークコイル
　Ｌ１　インダクタ
　１２０，１２０Ｂ　フィードバック回路
　１２２　エラーアンプ
　１２４Ｂ　フォトカプラ
　１２４　絶縁回路
　１３０，１３０Ａ，１３０Ｂ，１３０Ｃ，１３０Ｄ　コンバータコントローラ
　１３２　パルス変調器
　１３２Ｃ　パルス幅変調器
　１３４　ドライバ
　１３４Ｈ　ハイサイドドライバ
　１３４Ｌ　ローサイドドライバ
　１３６　同期信号発生器
　１３８　第２カウンタ
　１４０，１４０Ｃ，１４０Ｄ　パルス電流発生器
　１４２　プロセッサ
　１４４　カウンタ、第１カウンタ
　１４６，１４６ａ，１４６ｂ，１４６ｃ　電流ドライバ
　１４８ａ，１４８ｂ、１４８ｃ　出力段
　ＣＳＳ　ソフトスタート用キャパシタ
　１５０，１５０Ａ　クランプ回路
　１７０　ＰＷＭコンパレータ
　１７２　オシレータ
　２００　デジタルプロセッサ
　Ｍ１Ｈ ハイサイドトランジスタ
　Ｍ１Ｌ ローサイドトランジスタ 1 Circuit system 2 Input power supply 4 Load 100, 100A, 100B, 100C, 100D Switching power supply device 102 Input line 104 Output line 110, 110A, 110B, 110C Power circuit M1 Switching element M1H High side transistor M1L Low side transistor M22 Low side transistor M23 High Side transistor Q1 Bipolar transistor R11 Resistor R21 Series resistor R22 Pull-up resistor R23 Series resistor T1 Transformer W1 Primary winding W2 Secondary winding C0, C1 Output capacitor D1, D2, D21, D22 Rectifier L0 Output choke coil L1 Inductor 120, 120B Feedback circuit 122 Error amplifier 124B Photocoupler 124 Isolation circuit 130, 130A, 130B, 130C, 130D Converter controller 132 Pulse modulator 132C Pulse width modulator 134 Driver 134H High side driver 134L Low side driver 136 Synchronous signal generator 138 Second counter 140, 140C, 140D Pulse current generator 142 Processor 144 Counter, first counter 146, 146a, 146b, 146c Current driver 148a, 148b, 148c Output stage C SS soft start capacitor 150, 150A Clamp circuit 170 PWM comparator 172 Oscillator 200 Digital processor M1H High side transistor M1L Low side transistor

Claims (18)

  1. 　スイッチング素子を含むパワー回路と、
    　前記パワー回路の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するフィードバック回路と、
    　前記誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、前記駆動パルスに応じて前記スイッチング素子を駆動するコンバータコントローラと、
    　ソフトスタート用キャパシタと、
    　ソフトスタート用パルス電流を生成し、前記ソフトスタート用キャパシタに供給するパルス電流発生器と、
    　前記ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、前記誤差信号をクランプするクランプ回路と、
    　を備える、スイッチング電源装置。     A power circuit including a switching element,
    a feedback circuit that generates an error signal according to an error between an output detection signal indicating an output signal of the power circuit and a reference signal;
    a converter controller that generates a drive pulse having a duty cycle according to the error signal and drives the switching element according to the drive pulse;
    soft start capacitor,
    a pulse current generator that generates a pulse current for soft start and supplies it to the soft start capacitor;
    a clamp circuit that clamps the error signal at a clamp level according to the voltage generated in the soft start capacitor;
    A switching power supply device comprising:
  2. 　前記パルス電流発生器は、起動からの経過時間に応じて、前記ソフトスタート用パルス電流のデューティサイクルを変化させる、請求項１に記載のスイッチング電源装置。 The switching power supply device according to claim 1, wherein the pulse current generator changes the duty cycle of the soft start pulse current according to the elapsed time from startup.
  3. 　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
    　前記駆動パルスの周波数と、前記ソフトスタート用パルス電流の周波数が等しい、請求項１に記載のスイッチング電源装置。     The driving pulse and the soft start pulse current are pulse width modulated signals,
    The switching power supply device according to claim 1, wherein the frequency of the drive pulse and the frequency of the soft start pulse current are equal.
  4. 　前記パルス電流発生器は、前記ソフトスタート用パルス電流の周波数の設定値と、デューティサイクルの設定値と、を受け、クロック信号をカウントすることにより、ソフトスタート用パルス信号を生成するカウンタを含み、前記ソフトスタート用パルス電流の周期ごとにアサートされる同期信号を生成可能であり、
    　前記コンバータコントローラは、前記同期信号と同期して前記駆動パルスを生成するパルス幅変調器を含む、請求項３に記載のスイッチング電源装置。     The pulse current generator includes a counter that receives a frequency setting value and a duty cycle setting value of the soft start pulse current, and generates a soft start pulse signal by counting a clock signal, It is possible to generate a synchronization signal that is asserted every cycle of the soft start pulse current,
    The switching power supply device according to claim 3, wherein the converter controller includes a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal.
  5. 　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
    　ｍを自然数とするとき、前記駆動パルスの周波数は、前記ソフトスタート用パルス電流の周波数のｍ倍または１／ｍ倍である、請求項１に記載のスイッチング電源装置。     The driving pulse and the soft start pulse current are pulse width modulated signals,
    The switching power supply device according to claim 1, wherein the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current, where m is a natural number.
  6. 　前記パルス電流発生器は、前記ソフトスタート用パルス電流の周波数の設定値と、デューティサイクルの設定値と、を受け、クロック信号をカウントすることにより、ソフトスタート用パルス信号を生成する第１カウンタを含み、
    　前記コンバータコントローラは、
    　前記駆動パルスの周波数の設定値を受け、前記クロック信号をカウントすることにより同期信号を生成する第２カウンタと、
    　前記同期信号と同期して前記駆動パルスを生成するパルス幅変調器と、
    　を含む、請求項３または５に記載のスイッチング電源装置。     The pulse current generator receives a frequency setting value and a duty cycle setting value of the soft start pulse current, and operates a first counter that generates a soft start pulse signal by counting a clock signal. including,
    The converter controller includes:
    a second counter that receives a set value of the frequency of the drive pulse and generates a synchronization signal by counting the clock signal;
    a pulse width modulator that generates the drive pulse in synchronization with the synchronization signal;
    The switching power supply device according to claim 3 or 5, comprising:
  7. 　前記パワー回路は絶縁コンバータであり、
    　前記コンバータコントローラ、前記パルス電流発生器、前記クランプ回路は、一次側に設けられ、
    　前記フィードバック回路は、
    　二次側に設けられたエラーアンプと、
    　入力が前記エラーアンプの出力と接続され、出力が前記コンバータコントローラと接続された絶縁回路と、
    　を含み、
    　前記クランプ回路は、前記絶縁回路の前記出力をクランプする、請求項１から５のいずれかに記載のスイッチング電源装置。     the power circuit is an isolated converter;
    The converter controller, the pulse current generator, and the clamp circuit are provided on the primary side,
    The feedback circuit is
    An error amplifier provided on the secondary side,
    an isolation circuit whose input is connected to the output of the error amplifier and whose output is connected to the converter controller;
    including;
    6. The switching power supply device according to claim 1, wherein the clamp circuit clamps the output of the isolation circuit.
  8. 　前記パワー回路は絶縁コンバータであり、
    　前記コンバータコントローラ、前記パルス電流発生器、前記クランプ回路は、一次側に設けられ、
    　前記フィードバック回路は、
    　二次側に設けられたエラーアンプと、
    　入力が前記エラーアンプの出力と接続され、出力が前記コンバータコントローラと接続された絶縁回路と、
    　を含み、
    　前記クランプ回路は、前記絶縁回路の前記出力をクランプする、請求項６に記載のスイッチング電源装置。     the power circuit is an isolated converter;
    The converter controller, the pulse current generator, and the clamp circuit are provided on the primary side,
    The feedback circuit is
    An error amplifier provided on the secondary side,
    an isolation circuit whose input is connected to the output of the error amplifier and whose output is connected to the converter controller;
    including;
    The switching power supply device according to claim 6, wherein the clamp circuit clamps the output of the isolation circuit.
  9. 　前記パルス電流発生器は、
    　プッシュプル構成の出力段と、
    　前記出力段の出力と前記ソフトスタート用キャパシタの間に直列に接続された整流素子およびシリーズ抵抗と、
    　を含む、請求項１から５のいずれかに記載のスイッチング電源装置。     The pulse current generator is
    An output stage with a push-pull configuration,
    a rectifying element and a series resistor connected in series between the output of the output stage and the soft start capacitor;
    The switching power supply device according to any one of claims 1 to 5, comprising:
  10. 　前記パルス電流発生器は、
    　プッシュプル構成の出力段と、
    　前記出力段の出力と前記ソフトスタート用キャパシタの間に直列に接続された整流素子およびシリーズ抵抗と、
    　を含む、請求項６に記載のスイッチング電源装置。     The pulse current generator is
    An output stage with a push-pull configuration,
    a rectifying element and a series resistor connected in series between the output of the output stage and the soft start capacitor;
    The switching power supply device according to claim 6, comprising:
  11. 　前記パルス電流発生器は、
    　ローサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、
    　前記出力段の出力と前記ソフトスタート用キャパシタの間に接続された整流素子と、
    　前記出力段の出力と接続されたプルアップ抵抗と、
    　を含む、請求項１から５のいずれかに記載のスイッチング電源装置。     The pulse current generator is
    An open-drain or open-collector output stage consisting of a low-side transistor,
    a rectifying element connected between the output of the output stage and the soft start capacitor;
    a pull-up resistor connected to the output of the output stage;
    The switching power supply device according to any one of claims 1 to 5, comprising:
  12. 　前記パルス電流発生器は、
    　ローサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、
    　前記出力段の出力と前記ソフトスタート用キャパシタの間に接続された整流素子と、
    　前記出力段の出力と接続されたプルアップ抵抗と、
    　を含む、請求項６に記載のスイッチング電源装置。     The pulse current generator is
    An open-drain or open-collector output stage consisting of a low-side transistor,
    a rectifying element connected between the output of the output stage and the soft start capacitor;
    a pull-up resistor connected to the output of the output stage;
    The switching power supply device according to claim 6, comprising:
  13. 　前記パルス電流発生器は、
    　ハイサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、
    　前記出力段の出力と前記ソフトスタート用キャパシタの間に接続されたシリーズ抵抗と、
    　を含む、請求項１から５のいずれかに記載のスイッチング電源装置。     The pulse current generator is
    An open-drain or open-collector output stage consisting of a high-side transistor,
    a series resistor connected between the output of the output stage and the soft start capacitor;
    The switching power supply device according to any one of claims 1 to 5, comprising:
  14. 　前記パルス電流発生器は、
    　ハイサイドトランジスタからなるオープンドレイン型またはオープンコレクタ型の出力段と、
    　前記出力段の出力と前記ソフトスタート用キャパシタの間に接続されたシリーズ抵抗と、
    　を含む、請求項６に記載のスイッチング電源装置。     The pulse current generator is
    An open-drain or open-collector output stage consisting of a high-side transistor,
    a series resistor connected between the output of the output stage and the soft start capacitor;
    The switching power supply device according to claim 6, comprising:
  15. 　前記クランプ回路は、ベースに前記ソフトスタート用キャパシタの電圧を受け、エミッタが前記コンバータコントローラの入力と接続されたトランジスタを含む、請求項１から５のいずれかに記載のスイッチング電源装置。 6. The switching power supply device according to claim 1, wherein the clamp circuit includes a transistor whose base receives the voltage of the soft start capacitor and whose emitter is connected to the input of the converter controller.
  16. 　スイッチング素子を含むスイッチング電源装置の制御方法であって、
    　前記スイッチング電源装置の出力信号を示す出力検出信号と基準信号の誤差に応じた誤差信号を生成するステップと、
    　前記誤差信号に応じたデューティサイクルを有する駆動パルスを生成し、前記駆動パルスに応じて前記スイッチング素子を駆動するステップと、
    　ソフトスタート用パルス電流を生成し、ソフトスタート用パルス電流によってソフトスタート用キャパシタを充電または放電するステップと、
    　前記ソフトスタート用キャパシタに発生する電圧に応じたクランプレベルにて、前記誤差信号をクランプするステップと、
    　を備える、制御方法。     A method for controlling a switching power supply device including a switching element, the method comprising:
    generating an error signal according to an error between an output detection signal indicating an output signal of the switching power supply and a reference signal;
    generating a drive pulse having a duty cycle according to the error signal, and driving the switching element according to the drive pulse;
    generating a soft-start pulse current and charging or discharging a soft-start capacitor with the soft-start pulse current;
    clamping the error signal at a clamp level according to the voltage generated in the soft start capacitor;
    A control method comprising:
  17. 　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
    　前記駆動パルスの周波数と、前記ソフトスタート用パルス電流の周波数が等しい、請求項１６に記載の制御方法。     The driving pulse and the soft start pulse current are pulse width modulated signals,
    17. The control method according to claim 16, wherein the frequency of the drive pulse and the frequency of the soft start pulse current are equal.
  18. 　前記駆動パルスおよび前記ソフトスタート用パルス電流は、パルス幅変調信号であり、
    　ｍを自然数とするとき、前記駆動パルスの周波数は、前記ソフトスタート用パルス電流の周波数のｍ倍または１／ｍ倍である、請求項１６に記載の制御方法。     The driving pulse and the soft start pulse current are pulse width modulated signals,
    17. The control method according to claim 16, wherein the frequency of the drive pulse is m times or 1/m times the frequency of the soft start pulse current, where m is a natural number.
PCT/JP2023/021404 2022-07-12 2023-06-08 Switching power supply and control method for same WO2024014201A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005033864A (en) * 2003-07-08 2005-02-03 Fuji Electric Device Technology Co Ltd Semiconductor integrated circuit
JP2009022075A (en) * 2007-07-10 2009-01-29 Fuji Electric Device Technology Co Ltd Soft start circuit and dc-dc converter
JP2013005514A (en) * 2011-06-14 2013-01-07 Honda Motor Co Ltd Switching power supply circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005033864A (en) * 2003-07-08 2005-02-03 Fuji Electric Device Technology Co Ltd Semiconductor integrated circuit
JP2009022075A (en) * 2007-07-10 2009-01-29 Fuji Electric Device Technology Co Ltd Soft start circuit and dc-dc converter
JP2013005514A (en) * 2011-06-14 2013-01-07 Honda Motor Co Ltd Switching power supply circuit

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