WO2024012015A1

WO2024012015A1 - Storage system, main control chip, data storage method and data reading method

Info

Publication number: WO2024012015A1
Application number: PCT/CN2023/091887
Authority: WO
Inventors: 戴瑾; 张云森
Original assignee: 北京超弦存储器研究院
Priority date: 2022-07-13
Filing date: 2023-04-28
Publication date: 2024-01-18
Also published as: CN117435535A

Abstract

A storage system, a main control chip, a data storage method and a data reading method. The storage system may comprise: a main control chip and N storage devices, wherein N is an integer not less than 2; the main control chip is in communication connection with the N storage devices on the basis of a PCIe protocol; and the main control chip is configured to realize data storage and data reading. The data storage comprises: when a write request is received and distributed storage of external storage objects is determined, segmenting data of the storage objects and then respectively storing same in parallel in a plurality of storage devices; and the data reading comprises: when a reading request is received and it is determined that storage objects needing to be read are stored in a distributed manner, reading the data of the storage objects in parallel from the plurality of storage devices, and transmitting same to an external device.

Description

A storage system, main control chip, data storage method and data reading method

Cross-references to related applications

This disclosure requests the priority of the Chinese patent application submitted to CNIPA on July 13, 2022, with application number 202210828397.8 and the invention name "a storage system, main control chip, data storage method and data reading method", which The contents are incorporated herein by reference.

Technical field

The present disclosure relates to but is not limited to storage technology, and in particular, refers to a storage system, a main control chip, a data storage method and a data reading method.

Background technique

PCI-Express (Peripheral Component Interconnect Express, PCIe for short) is a high-speed serial computer expansion bus standard. PCIe is currently a commonly used bus in high-speed computing systems. It can realize a certain starting address of the memory in one device to another device. High-speed data transfer from a certain starting address in memory.

Current storage devices have slow read and write speeds and insufficient bandwidth. Especially in application scenarios that directly support high-speed computing, they cannot reach the transmission capabilities of PCIe channels.

Summary of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

Embodiments of the present disclosure provide a storage system, which is inserted into the PCIe bus of a computer system or connected to the computer system through the CXL protocol, including: a main control chip and N storage devices, where N is an integer not less than 2;

The main control chip communicates with the N storage devices based on the PCIe protocol.

Embodiments of the present disclosure also provide a main control chip that communicates with N storage devices, where N is an integer not less than 2. The main control chip includes a memory and a processor, and the memory is configured as a storage device. Store execution instructions; the processor is configured to call the execution instructions to perform the following processing;

Data storage: When a write request is received and it is determined to perform distributed storage of an external storage object, the data of the storage object is divided and stored in multiple storage devices in parallel;

Data reading includes: when receiving a read request and determining that the storage object to be read is stored in a distributed manner, reading the data of the storage object in multiple storage devices in parallel and transmitting it to an external device.

Embodiments of the present disclosure also provide a data storage method, which is applied to a storage system including a main control chip and N storage devices. The N storage devices are connected to the main control chip through the PCIe protocol, and N is an integer not less than 2. , the method includes:

The main control chip receives the write request and determines whether to perform distributed storage of external storage objects;

When the main control chip determines to perform distributed storage of the storage object, it divides the data of the storage object and stores it in multiple storage devices in parallel.

The embodiment of the present disclosure also provides a data reading method, which is applied to a storage system including a main control chip and N storage devices. The N storage devices are connected to the main control chip through the PCIe protocol, and N is not less than 2. Integer, the methods include:

The main control chip receives the read request and determines whether the storage object to be read is distributedly stored;

When the main control chip determines that the storage object to be read is stored in a distributed manner, it reads the data of the storage object in multiple storage devices in parallel and transmits it to the outside.

Compared with the existing technology, the storage system, main control chip, data storage method and data reading method provided by at least one embodiment of the present disclosure have the following beneficial effects: multiple storage devices can be connected through PCIe interfaces respectively, and multiple Storage devices form parallel connections, which can expand bandwidth and provide the largest data transmission bandwidth and the shortest delay.

Other aspects will be apparent after reading and understanding the drawings and detailed description.

Figure overview

The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. They are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute an explanation of the technical solutions of the present disclosure. case restrictions.

Figure 1 is a structural diagram of a storage system provided by an example embodiment of the present disclosure;

Figure 2 is a structural diagram of a storage system provided by another example embodiment of the present disclosure;

Figure 3 is a flow chart of a data storage method provided by an example embodiment of the present disclosure;

Figure 4 is a flow chart of a data storage method provided by another example embodiment of the present disclosure;

Figure 5 is a structural block diagram of a storage system provided by an example embodiment of the present disclosure;

FIG. 6 is a structural block diagram of a main control chip provided by an exemplary embodiment of the present disclosure.

Elaborate

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments and features in the embodiments of the present disclosure may be arbitrarily combined with each other unless there is any conflict.

The present disclosure describes multiple embodiments, but the description is illustrative rather than restrictive, and for those of ordinary skill in the art, there may be more within the scope of the embodiments described in the present disclosure. Embodiments and implementation solutions. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless expressly limited, any feature or element of any embodiment may be used in combination with, or may be substituted for, any other feature or element of any other embodiment.

The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features and elements that have been disclosed in this disclosure may also be combined with any conventional features or elements to form solutions defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other disclosed solutions to form another unique solution as defined by the claims. Accordingly, it should be understood that any features shown and discussed in this disclosure may be implemented individually or in any suitable combination. Accordingly, the embodiments are not to be limited except by those appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented methods and processes as a specific sequence of steps. However, this method or process does not rely on the specific steps described in this disclosure. To the extent that a sequence is specified, the method or process should not be limited to the specific sequence of steps described. As one of ordinary skill in the art will appreciate, other sequences of steps are possible. Therefore, the specific order of steps set forth in the specification should not be construed as limiting the claims. Furthermore, claims directed to the methods and processes should not be limited to steps performing them in the order written, as those skilled in the art will readily appreciate that such order may be varied and still remain within the spirit and scope of the disclosed embodiments.

Figure 1 is a structural diagram of a storage system provided by an example embodiment of the present disclosure. The storage system can be inserted into the PCIe bus of the computer system (i.e., inserted into the system), or the storage system can be connected to the computer system (i.e., connected to the system) through the CXL protocol. into the system), as shown in Figure 1, the storage system may include: a main control chip 11 and N storage devices 12, where N is an integer not less than 2 (that is, not less than 2); the main control chip and N storage devices Communication connection is based on PCIe protocol.

In this embodiment, multiple storage devices can be connected through PCIe interfaces respectively, and multiple storage devices form a parallel connection. Through the parallel connection, the bandwidth can be expanded, providing the maximum data transmission bandwidth and the shortest delay.

In one example, the storage device may include a solid state drive (SSD), and multiple SSDs are connected to the main control chip through the PCIe protocol.

Parallel connections can effectively expand data bandwidth. For example, N SSDs each establish a P-channel (Lane) PCIe connection with the main control chip. The main control chip is connected to the external PCIe using N times P lanes, and P is a non-negative integer. When performing object storage operations, the main control chip can read and write N storage devices in parallel, and convert the data blocks read out by each storage device in turn to the PCIe interface of N times P channels and send them out; or input them from the outside. Data, the main control chip can divide the external input data in sequence and write it to N storage devices in parallel on the PCIe interface of the P channel. P and N may be determined based on the lanes of the PCIe bus of the system into which the storage device is plugged, where N multiplied by P is less than or equal to the number of lanes of the PCIe bus.

For each SSD, a P-channel PCIe connection can be established with the main control chip, and a data packet can be transmitted to the SSD through one of the P-channels. If there are multiple flash memory chips in the SSD, one channel can correspondingly transmit the read or write data in one flash memory chip.

In an example embodiment of the present disclosure, N=4 and P=4. Currently, in some embodiments, the SSD only supports 4 PCIe lanes, while the PCIe bus commonly has 16 lanes.

In this embodiment, four SSDs can be provided, and each SSD can be composed of an SSD control chip and a set of flash memory chips. The entire system can be deployed on a motherboard to form a high-bandwidth SSD. The formed high-bandwidth SSD can be plugged into the PCIe bus of the host, or the formed high-bandwidth SSD can be connected to the host through the CXL protocol.

In an example embodiment of the present disclosure, the main control chip may be configured to implement data storage (i.e., data writing) and data reading (i.e., data reading). Data storage may include: receiving a write request and determining whether to When the storage object is stored in a distributed manner, the data of the storage object is divided and stored in multiple storage devices in parallel, that is, the data of the storage object is divided and stored in N storage devices in parallel, or the data of the storage object is stored in parallel. After splitting, store the data in N partial storage devices in parallel; data storage may include: when a read request is received and the storage object to be read is determined to be distributed, reading the data of the objects stored in multiple storage devices in parallel And transmit it to the external device, that is, read the data of the objects stored in N storage devices in parallel and transmit it to the external device, or read the data of the objects stored in some of the N storage devices in parallel and transmit it to the external device.

In this embodiment, the main control chip can realize parallel connection with multiple storage devices on different channels through multi-channel PCIe. The main control chip and the storage device are tightly coupled, and the resources of the storage device (such as SSD) can be fully utilized.

The main control chip can be used to cooperate with multiple storage devices connected in parallel. The main control chip is responsible for data transfer and distributed management of the storage system. It divides large storage objects and stores them in different storage devices to facilitate parallel processing. Data reading and writing.

In one example, when the data size of the storage object is greater than a preset size threshold, the main control chip determines to perform distributed storage of the external storage object when the data size of the storage object is greater than the size threshold. The main control chip implements distributed storage for storage objects whose data size exceeds the set threshold.

The storage system provided by the embodiment of the present disclosure can connect multiple storage devices through PCIe interfaces with multiple channels, and multiple storage devices form parallel connections. Through parallel connections, bandwidth can be expanded and latency can be reduced.

In an example embodiment of the present disclosure, each storage device may include: an SSD control chip and K flash memory chips, where K is greater than or equal to 1; each SSD control chip is connected to K lanes of the PCIe, and each lane Corresponding to the transmission of read or written data of a flash memory chip, 1≤K≤ P.

In this embodiment, the storage device may include a solid state drive (SSD for short). The SSD may include an SSD control chip and a flash memory chip. Each SSD control chip can be connected to the main control chip through the PCIe protocol. One of the P channels established by the SSD and the main control chip corresponds to transmitting the read or write data in a flash memory chip.

Figure 2 is a structural diagram of a storage system provided by another example embodiment of the present disclosure. As shown in Figure 2, the main control chip can include a CPU core 111, an internal memory 112 and a programmable logic device 113. The programmable logic device can be configured as Realize data transfer between storage devices and external devices; the internal memory can store a distributed storage management program, and the CPU core can run the distributed storage management program to realize data storage and data reading.

In this embodiment, one implementation of the main control chip can be implemented by using an FPGA. The distributed storage system can be implemented by the software of the built-in CPU core of the FPGA and programmable hardware. PCIe data transfer can be implemented by programmable logic devices.

In an example embodiment of the present disclosure, the external device may include a processor of a local host or a processor of a remote host (such as a CPU), and the main control chip may include an external communication interface; the main control chip may communicate with the computer system ( such as the host) for external communication.

In an example, the external communication interface may include: a PCIe bus interface, and the PCIe bus interface may be configured to communicate with the processor of the local host through the PCIe bus.

As shown in Figure 2, multiple storage devices (such as SSD) can be connected to the main control chip through the PCIe protocol. The entire system composed of multiple storage devices and the main control chip can be deployed on one motherboard to form a high-bandwidth SSD. The high-bandwidth SSD can be inserted into the PCIe bus through the PCIe bus interface of the main control chip and connected to the local host.

In an example, the external communication interface may include: a CXL bus interface, and the CXL bus interface may be configured to communicate with the processor of the local host through the CXL bus.

As shown in Figure 2, multiple storage devices (such as SSD) are connected to the main control chip through the PCIe protocol. The entire system composed of multiple storage devices and the main control chip can be deployed on one motherboard to form a high-bandwidth SSD. The high-bandwidth SSD can be inserted into the CXL bus through the CXL bus interface of the main control chip and connected to the local host.

In an example, the external communication interface may include: a network interface configured to communicate with a processor of a remote host through a network.

Multiple storage devices (such as SSD) are connected to the main control chip through the PCIe protocol. The entire system composed of multiple storage devices and the main control chip can be deployed on a motherboard to form a high-bandwidth SSD. The high-bandwidth SSD formed can access the network through the network interface of the main control chip and connect to the remote host.

In an example embodiment of the present disclosure, the PCIe Gen5 protocol can be used between the main control chip and multiple storage devices, and the read and write bandwidth can exceed the dynamic random access connected to the Double Data Rate (DDR) bus. Memory (Dynamic Random Access Memory, DRAM for short).

Figure 3 is a flow chart of a data storage method provided by an example embodiment of the present disclosure. The execution subject of the data storage method can be the storage system shown in any embodiment. The data storage method can be applied to a system including a main control chip and N storage devices. The storage system of the device. N storage devices are connected to the main control chip through the PCIe protocol. N is an integer not less than 2. As shown in Figure 3, data storage methods can include:

S301: The main control chip receives the write request and determines whether to perform distributed storage of external storage objects.

In this embodiment, the main control chip can cooperate with multiple storage devices, and external storage objects can be written into the storage devices in parallel through the main control chip.

In an example, the write request may carry the data size of the storage object; determining whether to perform distributed storage on the external storage object may include: when the data size of the storage object is greater than the size threshold, determining to perform distributed storage on the storage object .

The requester (such as the host of the computer system) sends a write request to the storage system. The write request information can carry the object name, data size, starting address of the existing data, etc. The main control chip implements distributed storage for storage objects whose size exceeds the set threshold.

S302: When the main control chip determines to perform distributed storage of the storage object, it divides the data of the storage object and stores it in multiple storage devices in parallel, that is, stores it in N storage devices or some of the N storage devices.

When the main control chip determines that the storage object needs to be stored in a distributed manner, the data of the storage object is divided and stored in different storage devices to facilitate parallel data reading and writing.

In an example embodiment of the present disclosure, dividing the data of the storage object and storing it in parallel in N storage devices or some of the N storage devices may include:

Divide the storage object into M data packets, M>N, M can be much larger than N; store the M data packets in N data packets in units of N data packets in turn to N storage devices in a preset order, where M data Every N data packets in the package are stored in N storage devices in parallel, and one data packet is stored in one storage device at a time.

When the number M of data packets is not an integer multiple of N, divide M by N and the remaining data packets are stored in parallel in some of the N storage devices. One data packet is stored in one storage device at a time.

When the number of data packets M < N, each data packet is stored in parallel to some of the N storage devices, and one data packet is stored in one storage device at a time.

When arranging distributed storage, for multiple storage devices (such as SSD) connected to the PCIe interface of the main control chip, the main control chip can assign multiple consecutive data packets to multiple storage devices, and each data packet is assigned to a storage device. equipment.

In an example, when the storage object is divided into M data packets and M>N, M data packets are written to N storage devices through multiple storages. Each storage may include:

When the number of remaining data packets is greater than or equal to N, N data packets are stored in parallel in N storage devices in a preset order, and one data packet is stored in one storage device at a time;

When the number of remaining data packets is less than N, the remaining data packets are stored in parallel in the storage device, and one data packet is stored in one storage device at a time.

If M≤N, M data packets can be stored in parallel in M different storage devices through one storage.

In an example, the preset order may be determined based on empirical values, and the preset order may be the size order of storage addresses of data packets, or the preset order may be the number size order of storage devices.

In an example embodiment of the present disclosure, the write request may also carry the name of the storage object and the current storage address of the data of the storage object, and the storage device may include a control chip and a flash memory chip connected to the control chip. Store M data packets in N data packet units in turn to N storage devices in a preset order, which can include:

The main control chip determines the size of the M data packets divided into according to the current storage address of the storage object, and determines the starting address for fetching data from the M storage devices; the main control chip takes turns to the control chips of the N storage devices in a preset order. Send a write request, carrying the starting address of the data to be retrieved from the storage device sent to and the size of the data packet to be retrieved; the control chip of each storage device retrieves data from the corresponding starting address of data retrieval through the PCIe protocol and Write to the connected flash memory chip.

After the main control chip divides the data of the storage object into multiple data packets and allocates a corresponding storage device to each data packet, the main control chip can send write requests to multiple storage devices. The write request can carry Each storage device takes the starting address of data. Each storage device will fetch data at the corresponding address through the PCIe protocol and write it to the flash memory. Repeat the above steps until all data is written.

In an example, the write request may also carry the name of the storage object and the current storage address information of the data of the storage object, and the storage device may include a control chip and a flash memory chip connected to the control chip;

When the main control chip divides the storage object into M data packets, it determines the size and starting address of the divided M data packets based on the current storage address information of the storage object;

The main control chip takes turns sending write requests to the control chips of N storage devices in a preset order, carrying the starting address and size of the data packet to be taken out by the storage device;

After receiving the write request, the control chip of each storage device fetches data from the corresponding starting address of data acquisition through the PCIe protocol and writes it to the connected flash memory chip.

The current storage address information may include: the current start and end addresses and the size of the data packet, or the current storage address information may include: the current start address and the current end address.

Figure 4 is a flow chart of a data reading method provided by another example embodiment of the present disclosure. The execution subject of the data reading method can be the storage system shown in any embodiment. The data reading method can be applied to a system including a main control chip. A storage system with N storage devices. The N storage devices are connected to the main control chip through the PCIe protocol, and N is an integer not less than 2. As shown in Figure 4, data reading methods can include:

S401: The main control chip receives the read request and determines whether the storage object to be read is distributedly stored.

In this embodiment, the main control chip can be used to cooperate with multiple storage devices, and the main control chip can be used to realize Read storage object data in parallel from multiple storage devices.

S402: When the main control chip determines that the storage object to be read is distributedly stored, it reads the data of the storage object in multiple storage devices in parallel and transmits it to the external device, that is, it reads N storage devices or N storage objects in parallel. The object's data is stored in some storage devices and transferred to the outside. When the main control chip determines that the storage object needs to be read from the storage device, it first determines whether the storage object to be read is distributed. If the storage object is distributed, the main control chip sends a read message to all storage devices that store the storage object. Fetch requests and read corresponding data in parallel from all storage devices that store the storage object to facilitate parallel data reading.

In an example embodiment of the present disclosure, the read request may carry the name of the storage object and a receiving address for receiving the read data of the storage object, and the storage device may include a control chip and a flash memory chip connected to the control chip. Reading the data of objects stored in N storage devices or some of the N storage devices in parallel and transmitting it to the outside may include:

The main control chip determines all storage devices for distributed storage of the storage object based on the name of the storage object, and determines the starting address of each storage device for writing data to the outside based on the receiving address and the size of the data packet in each storage device; The main control chip sends read requests to all storage devices that distribute the storage objects, carrying the starting address of the sent storage device to write data to the outside; the control chip of each storage device reads from the connected flash memory chip Read data from it and write data to the corresponding starting address of writing data through PCIe protocol.

The requester (such as an external host) sends a read request (or read request) to the storage system. The read request can carry the object name, the starting memory address for receiving data, etc.

If the storage object is stored in a distributed manner, the main control chip sends a read request to all storage devices (such as SSD) that store the object, calculates the starting address of the received data corresponding to each storage device, and sends the corresponding received data to each storage device. The starting address of the data is included in the read request. Each storage device will read data from the flash memory and send the read data to the corresponding address. Repeat the above steps until all data is read out.

In one example, the read request carries the name of the storage object and receiving address information for receiving the data of the read storage object. The storage device may include a control chip and a flash memory chip connected to the control chip;

The main control chip reads the data of objects stored in multiple storage devices in parallel and transmits it to external devices, which can include:

The main control chip determines all storage devices that distribute the data of the storage object based on the name of the storage object, and determines the start of each storage device writing data to the external device based on the receiving address and the size of the data in each storage device. address;

The main control chip sends read requests to all storage devices that distribute the data of the storage object, carrying the current storage address of the data to be read, and the starting address of the storage device writing data to the external device;

After receiving the read request, the control chip of each storage device reads data from the connected flash memory chip according to the current storage address of the data to be read, and writes data to the corresponding starting address of writing data through the PCIe protocol. .

The data of the storage object saved by each storage device may be the data packet stored when the data was previously written.

Figure 5 is a structural block diagram of a computer system provided by an example embodiment of the present disclosure. As shown in Figure 5, the computer system may include: a host 51, a bus 52 and a storage system 53. The storage system adopts the storage system shown in any embodiment. , the bus can be PCIe bus or CXL bus.

Multiple storage devices (such as SSD control chips) can be connected to the main control chip through the PCIe protocol. The entire system composed of multiple storage devices and main control chips can be deployed on one motherboard to form a high-bandwidth SSD. The high-bandwidth SSD can be inserted into the PCIe bus of the host or connected to the host through the CXL protocol.

Figure 6 is a structural block diagram of a main control chip provided by an example embodiment of the present disclosure. The main control chip can communicate with N storage devices, where N is an integer not less than 2. As shown in Figure 6, the main control chip can include Memory 61 and processor 62.

The memory is set to store execution instructions. When the main control chip is running, the processor communicates with the memory, and the processor is set to call execution instructions for executing the data storage method and the data reading method.

The processor in this article may be a Central Processing Unit (CPU for short), or an Application Specific Integrated Circuit (ASIC for short), or one or more integrated circuits that implement the embodiments of the present disclosure. or other having A device that handles functions.

The processor is configured to invoke execution instructions to perform the following operations:

Data storage, that is, the data storage method may include: when receiving a write request and determining to perform distributed storage of an external storage object, dividing the data of the storage object and storing them in parallel in multiple storage devices. , that is, stored in N storage devices or part of N storage devices, where N is an integer not less than 2;

Data reading, that is, the data reading method may include: when a read request is received and it is determined that the storage object to be read is stored in a distributed manner, reading the data of the storage object in multiple storage devices in parallel and Transmitting to an external device means reading the data of the storage object in N storage devices or part of the N storage devices in parallel and transmitting it to the external device.

In an example embodiment of the present disclosure, the write request may carry the data size of the storage object;

Determining whether to perform distributed storage of external storage objects may include: the data size of the storage object by the main control chip is greater than a preset size threshold, that is, the data size of the main control chip in the storage object When the size is greater than the size threshold, it is determined to perform distributed storage of the storage object.

In an exemplary embodiment of the present disclosure, the main control chip divides the data of the storage object and stores it in N storage devices or some of the N storage devices in parallel, which may include:

Divide the storage object into M data packets, M≥N; store the M data packets in N data packets in units of N data packets in turn to N storage devices in a preset order, where each N of M data packets Data packets are stored in N storage devices in parallel, and one data packet is stored in one storage device at a time;

In an example embodiment of the present disclosure, the main control chip divides the data of the storage object and stores it in multiple storage devices in parallel, which may include:

Divide the storage object into M data packets. When M>N, store the M data packets multiple times. The data packet is written to N storage devices, and each storage includes:

When the number of remaining data packets is less than N, the remaining data packets are stored in the storage device in parallel, and one data packet is stored in one storage device at a time.

In an example embodiment of the present disclosure, the write request may also carry the name of the storage object and the current storage address of the data of the storage object. The storage device includes a control chip and a device connected to the control chip. flash memory chips;

The method of storing M data packets in N data packets as a unit to N storage devices in turn in a preset order may include:

The main control chip determines the size of the M data packets divided into according to the current storage address of the storage object, and determines the starting addresses of the M storage devices for fetching data;

The main control chip sends write requests to the control chips of the N storage devices in turn in a preset order, carrying the starting address of the data sent to the storage device and the size of the data packet to be taken out;

The control chip of each storage device fetches data from the corresponding starting address for fetching data through the PCIe protocol and writes it to the connected flash memory chip.

In an example embodiment of the present disclosure, the write request also carries the name of the storage object and the current storage address information of the data of the storage object. The storage device includes a control chip and a device connected to the control chip. flash memory chips;

When the main control chip divides the storage object into M data packets, it determines the size and starting address of the divided M data packets according to the current storage address information of the storage object;

The main control chip sends write requests to the control chips of the N storage devices in turn in a preset order, carrying the starting address and size of the data packet to be taken out by the storage device;

After receiving the write request, the control chip of each storage device fetches data from the corresponding starting address through the PCIe protocol and writes it into the connected flash memory chip.

In an example embodiment of the present disclosure, the read request may carry the name of the storage object and a receiving address for receiving the read data of the storage object, and the storage device includes a control A chip and a flash memory chip connected to the control chip;

The parallel reading of the data of the storage object in N storage devices or part of the N storage devices and transmitting it to the outside may include:

The main control chip determines all storage devices that distribute the storage object according to the name of the storage object, and determines each storage device to write to the outside based on the receiving address and the size of the data packet in each storage device. The starting address of the data;

The main control chip sends read requests to all storage devices that distribute the storage objects, carrying the starting address of the sent storage device to write data to the outside;

The control chip of each storage device reads data from the connected flash memory chip and writes data to the corresponding starting address of writing data through the PCIe protocol.

In an example embodiment of the present disclosure, the read request may carry the name of the storage object, and receiving address information for receiving the data of the read storage object, and the storage device may include a control chip and a device connected to the storage object. The flash memory chip connected to the control chip;

The main control chip reads the data of the storage objects in multiple storage devices in parallel and transmits it to external devices, which may include:

The main control chip determines all storage devices that distribute the data of the storage object according to the name of the storage object, and determines the external data of each storage device according to the receiving address and the size of the data in each storage device. The starting address of the device writing data;

After receiving the read request, the control chip of each storage device reads the data from the connected flash memory chip according to the current storage address of the data to be read, and writes the data to the corresponding starting address through the PCIe protocol. Write data.

Those of ordinary skill in the art can understand that all or some steps, systems, and functional modules/units in the devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one A function or step can be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer. Additionally, it is known to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

Claims

A storage system, inserted into the PCIe bus of a computer system, or connected to the computer system through the CXL protocol, including a main control chip and N storage devices, where N is an integer not less than 2;

The main control chip communicates with the N storage devices based on the PCIe protocol.
The storage system according to claim 1, wherein the main control chip is configured to implement data storage and data reading;

The data storage includes: when receiving a write request and determining to perform distributed storage of an external storage object, dividing the data of the storage object and storing them in parallel in multiple storage devices;

The data reading includes: when receiving a read request and determining that the storage object to be read is stored in a distributed manner, reading the data of the storage object in multiple storage devices in parallel and transmitting it to an external device.
The storage system of claim 2, wherein:

The external device includes a processor of a local host or a processor of a remote host; the main control chip includes an external communication interface:

The external communication interface includes: a PCIe bus interface, the PCIe bus interface is configured to communicate with the processor of the local host through the PCIe bus;

or,

The external communication interface includes: a CXL bus interface, the CXL bus interface is configured to communicate with the processor of the local host through the CXL bus;

or,

The external communication interface includes: a network interface configured to communicate with a processor of a remote host through a network.
The storage system according to claim 2, wherein the main control chip determines to perform distributed storage of external storage objects when the data size of the storage object is greater than a preset size threshold.
The storage system of claim 4, wherein each of the storage devices includes: SSD Control chip and K flash memory chips, K is greater than or equal to 1;

Each SSD control chip is connected to K lanes of the PCIe, and each lane corresponds to transmitting data read or written from a flash memory chip.
The storage system according to any one of claims 1 to 5, wherein the main control chip includes a CPU core, an internal memory and a programmable logic device, and the programmable logic device is configured to implement the storage device and the external device Data transfer between; the internal memory stores a distributed storage management program, and the CPU core runs the distributed storage management program to implement the data storage and data reading.
The storage system according to claim 2, wherein the main control chip divides the data of the storage object and stores it in multiple storage devices in parallel, including:

Divide the storage object into M data packets. When M>N, write the M data packets into N storage devices through multiple storages. Each storage includes:

When the number of remaining data packets is greater than or equal to N, N data packets are stored in parallel in N storage devices in a preset order, and one data packet is stored in one storage device at a time;

When the number of remaining data packets is less than N, the remaining data packets are stored in the storage device in parallel, and one data packet is stored in one storage device at a time.
A main control chip that communicates with N storage devices, where N is an integer not less than 2. The main control chip includes a memory and a processor. The memory is configured to store execution instructions; the processor is configured to call the execution instructions. , to perform the following processing;

Data storage: When a write request is received and it is determined to perform distributed storage of an external storage object, the data of the storage object is divided and stored in multiple storage devices in parallel;

Data reading: When a read request is received and it is determined that the storage object to be read is stored in a distributed manner, the data of the storage object in multiple storage devices is read in parallel and transmitted to an external device.
The main control chip according to claim 8, wherein the write request carries the data size of the storage object;

The determining whether to perform distributed storage on the external storage object includes: the main control chip determines to perform distributed storage on the storage object when the data size of the storage object is greater than a preset size threshold.
The main control chip according to claim 8, wherein the main control chip divides the data of the storage object and stores it in multiple storage devices in parallel, including:

Divide the storage object into M data packets. When M>N, write the M data packets into N storage devices through multiple storages. Each storage includes:

When the number of remaining data packets is greater than or equal to N, N data packets are stored in parallel in N storage devices in a preset order, and one data packet is stored in one storage device at a time;

When the number of remaining data packets is less than N, the remaining data packets are stored in the storage device in parallel, and one data packet is stored in one storage device at a time.
The main control chip according to claim 10, wherein the write request also carries the name of the storage object and the current storage address information of the data of the storage object, and the storage device includes a control chip and the A flash memory chip that controls the chip connection;

When the main control chip divides the storage object into M data packets, it determines the size and starting address of the divided M data packets according to the current storage address information of the storage object;

The main control chip sends write requests to the control chips of the N storage devices in turn in a preset order, carrying the starting address and size of the data packet to be taken out by the storage device;

After receiving the write request, the control chip of each storage device fetches data from the corresponding starting address through the PCIe protocol and writes it into the connected flash memory chip.
The main control chip according to claim 8, wherein the read request carries the name of the storage object and receiving address information for receiving the read data of the storage object, and the storage device includes a control chip and A flash memory chip connected to the control chip;

The main control chip reads the data of the storage objects in multiple storage devices in parallel and transmits it to external devices, including:

The main control chip determines all storage devices that distribute the data of the storage object according to the name of the storage object, and determines the external data of each storage device according to the receiving address and the size of the data in each storage device. The starting address of the device writing data;

The main control chip sends read requests to all storage devices that distribute the data of the storage object, carrying the current storage address of the data to be read, and the starting address of the storage device writing data to the external device;

After receiving the read request, the control chip of each storage device reads the data from the connected flash memory chip according to the current storage address of the data to be read, and writes the data to the corresponding starting address through the PCIe protocol. Write data.
A data storage method, applied to a storage system including a main control chip and N storage devices. The N storage devices are connected to the main control chip through the PCIe protocol, and N is an integer not less than 2. The method includes:

The main control chip receives the write request and determines whether to perform distributed storage of external storage objects;

When the main control chip determines to perform distributed storage of the storage object, it divides the data of the storage object and stores it in multiple storage devices in parallel.
The method of claim 13, wherein the write request carries the data size of the storage object;

The determining whether to perform distributed storage on the external storage object includes: the main control chip determines to perform distributed storage on the storage object when the data size of the storage object is greater than a preset size threshold.
The method according to claim 13, wherein the main control chip divides the data of the storage object and stores it in multiple storage devices in parallel, including:

Divide the storage object into M data packets. When M>N, write the M data packets into N storage devices through multiple storages. Each storage includes:

When the number of remaining data packets is greater than or equal to N, N data packets are stored in parallel in N storage devices in a preset order, and one data packet is stored in one storage device at a time;

When the number of remaining data packets is less than N, the remaining data packets are stored in the storage device in parallel, and one data packet is stored in one storage device at a time.
The method according to claim 15, wherein the write request also carries the name of the storage object and the current storage address information of the data of the storage object, and the storage device includes a control chip and a control chip. Connected flash memory chips;

When the main control chip divides the storage object into M data packets, it determines the size and starting address of the divided M data packets according to the current storage address information of the storage object;

The main control chip sends write requests to the control chips of the N storage devices in turn in a preset order, carrying the starting address and size of the data packet to be taken out by the storage device;

After receiving the write request, the control chip of each storage device fetches data from the corresponding starting address through the PCIe protocol and writes it into the connected flash memory chip.
A data reading method, applied to a storage system including a main control chip and N storage devices. The N storage devices are connected to the main control chip through the PCIe protocol, and N is an integer not less than 2. The method includes:

The main control chip receives the read request and determines whether the storage object to be read is distributedly stored;

When the main control chip determines that the storage object to be read is stored in a distributed manner, it reads the data of the storage object in multiple storage devices in parallel and transmits it to an external device.
The method according to claim 17, wherein the read request carries the name of the storage object and receiving address information for receiving the read data of the storage object, and the storage device includes a control chip and the storage object. The flash memory chip connected to the control chip;

The main control chip reads the data of the storage objects in multiple storage devices in parallel and transmits it to external devices, including:

The main control chip determines all storage devices that distribute the data of the storage object according to the name of the storage object, and determines the external data of each storage device according to the receiving address and the size of the data in each storage device. The starting address of the device writing data;

The main control chip sends read requests to all storage devices that distribute the data of the storage object, carrying the current storage address of the data to be read, and the starting address of the storage device writing data to the external device;

After receiving the read request, the control chip of each storage device reads the data from the connected flash memory chip according to the current storage address of the data to be read, and writes the data to the corresponding starting address through the PCIe protocol. Write data.