CN117435535A - Storage system, main control chip, data storage method and data reading method - Google Patents
Storage system, main control chip, data storage method and data reading method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Abstract
The embodiment of the invention discloses a storage system, a main control chip, a data storage method and a data reading method, wherein the storage system can comprise: the device comprises a main control chip and N storage devices, wherein N is an integer not lower than 2; the main control chip is in communication connection with the N storage devices based on PCIe protocol; the main control chip is arranged to realize data writing and reading, and the data writing comprises: when a write-in request is received and distributed storage is carried out on an external storage object, dividing the data of the storage object and respectively storing the divided data into N storage devices or partial storage devices in N storage devices in parallel; the data read-out includes: and when a reading request is received and the storage objects to be read are determined to be stored in a distributed mode, the data of the storage objects in the plurality of storage devices are read in parallel and transmitted to the outside. The memory system, the main control chip, the data storage method and the data reading method disclosed by the embodiment of the invention can provide the maximum data transmission bandwidth and the shortest time delay.
Description
Technical Field
The present invention relates to, but not limited to, memory technologies, and in particular, to a memory system, a main control chip, a data storage method, and a data reading method.
Background
PCI-Express (Peripheral Component Interconnect Express, PCIe) is a high-speed serial computer expansion bus standard, which is a bus commonly used by high-speed computing systems today to enable high-speed data transfer from a starting address of memory in one device to a starting address of memory in another device.
The current storage device has slower read-write speed and insufficient bandwidth, and especially in an application scene directly supporting high-speed calculation, the transmission capability of a PCIe channel cannot be achieved.
Disclosure of Invention
The embodiment of the application provides a storage system which is inserted into a PCIe bus of the system or is accessed into the system through CXL protocol, comprising: the device comprises a main control chip and N storage devices, wherein N is an integer not lower than 2;
and the main control chip is in communication connection with the N storage devices based on PCIe protocol.
The embodiment of the application also provides a main control chip, which comprises a memory and a controller, wherein the memory is used for storing the execution instruction; the processor calls the execution instruction to execute a data storage method and a data reading and writing method;
the data storage method comprises the following steps: when a write-in request is received and distributed storage is carried out on an external storage object, dividing the data of the storage object, and respectively and parallelly storing the data into N storage devices or partial storage devices in N storage devices, wherein N is an integer not lower than 2;
the data reading and writing method comprises the following steps: and when a reading request is received and the storage objects to be read are determined to be stored in a distributed mode, the data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to an external device.
The embodiment of the application also provides a data storage method, which is applied to a storage system comprising a main control chip and N storage devices, wherein the N storage devices are connected with the main control chip through a PCIe protocol, and N is an integer not lower than 2, and the method comprises the following steps:
the main control chip receives the writing request and determines whether to perform distributed storage on an external storage object;
when the main control chip determines to perform distributed storage on the storage object, the data of the storage object are divided and then stored in N storage devices or part of the N storage devices in parallel.
The embodiment of the application also provides a data storage method, which is applied to a storage system comprising a main control chip and N storage devices, wherein the N storage devices are connected with the main control chip through a PCIe protocol, and N is an integer not lower than 2, and the method comprises the following steps:
the main control chip receives a reading request and determines whether a storage object to be read is stored in a distributed mode;
and when the main control chip determines that the storage objects to be read are stored in a distributed mode, the data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to the outside.
Compared with the prior art, the storage system, the main control chip, the data storage method and the data reading method provided by at least one embodiment of the application have the following beneficial effects: the storage devices can be connected through PCIe interfaces respectively, the storage devices form parallel connection, the bandwidth can be enlarged through parallel connection, and the maximum data transmission bandwidth and the shortest time delay are provided.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a block diagram of a memory system according to an exemplary embodiment of the present invention;
FIG. 2 is a block diagram of a storage system provided in accordance with another exemplary embodiment of the present invention;
FIG. 3 is a flow chart of a data storage method according to an exemplary embodiment of the present invention;
FIG. 4 is a flow chart of a data storage method provided by another exemplary embodiment of the present invention;
FIG. 5 is a block diagram of a memory system according to an exemplary embodiment of the present invention;
fig. 6 is a block diagram of a main control chip according to an exemplary embodiment of the present invention.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
FIG. 1 is a block diagram of a storage system according to an exemplary embodiment of the present invention, where the storage system may be plugged into a PCIe bus of the system or accessed to the system through CXL protocol, and as shown in FIG. 1, the storage system may include: the main control chip 11 and N storage devices 12, N is an integer not lower than 2; the main control chip and the N storage devices are in communication connection based on PCIe protocol.
In this embodiment, the multiple storage devices may be connected through PCIe interfaces, where the multiple storage devices form parallel connections, and bandwidth may be enlarged through the parallel connections, so as to provide the maximum data transmission bandwidth and the shortest latency.
In an example, the storage device may include a solid state disk (Solid State Drives, abbreviated as SSD), where the SSDs are respectively connected to the master control chip through PCIe protocol.
The parallel connection can effectively enlarge the data bandwidth. For example, N SSDs respectively establish PCIe connection of a P channel (Lane) with a main control chip, where the main control chip is connected with the outside by PCIe of N times the P channel, and P is a non-negative integer. When the object storage operation is carried out, the main control chip can read and write N storage devices in parallel, and sequentially convert the data blocks read out by each storage device to a PCIe interface of N times P channels to be sent out; or data is input from the outside, and N storage devices are written in parallel on the PCIe interface of the P channel after being divided in sequence. P and N may be determined from the lanes of the PCIe bus of the system into which the storage device is inserted, where N times P is less than or equal to the number of lanes of the PCIe bus.
For each SSD and the main control chip establish PCIe connection of the P channel, one data packet can be transmitted to the SSD through one of the P channels. If there are multiple flash memory chips in the SSD, one channel can correspondingly transmit read or write data in one flash memory chip.
In an example embodiment of the invention, n=4, p=4. Currently, in some embodiments, SSDs support only 4 PCIe lanes, whereas PCIe buses are common for 16 lanes.
In this embodiment, 4 SSDs may be provided, and each SSD may be composed of one SSD control chip and a set of flash memory chips. The whole system can be deployed on a main board to form a high-bandwidth SSD. The composed high bandwidth SSD may be plugged onto the host's PCIe bus or accessed to the host through the CXL protocol.
In an exemplary embodiment of the present invention, the main control chip is configured to implement data writing and data reading, where the data writing includes: when a write-in request is received and distributed storage is carried out on an external storage object, dividing the data of the storage object and respectively storing the divided data into N storage devices or partial storage devices in N storage devices in parallel; the data read-out includes: and when the reading request is received and the storage objects to be read are determined to be stored in a distributed mode, the data of the storage objects in the N storage devices or part of the storage devices in the N storage devices are read in parallel and transmitted to the outside.
In this embodiment, the master control chip is connected to multiple storage devices in parallel on different channels through the multi-channel PCIe, and the master control chip is tightly coupled to the storage devices, so that resources of the storage devices (such as SSDs) can be fully utilized.
The main control chip is responsible for data transfer and distributed management of the storage system, large storage objects are divided and stored in different storage devices respectively, and parallel data reading and writing are facilitated.
In an example, the master control chip determines to store the external storage object in a distributed manner when the data size of the storage object is greater than the size threshold. And the main control chip performs distributed storage on the storage objects with the data sizes exceeding the set threshold.
According to the storage system provided by the embodiment of the invention, a plurality of storage devices can be connected through PCIe interfaces with multiple channels respectively, the storage devices form parallel connection, and the bandwidth can be enlarged and the time delay can be reduced through the parallel connection.
In an example embodiment of the invention, each storage device may include: SSD control chip and K flash memory chips, K is greater than or equal to 1; each SSD control chip is connected to K channels of PCIe, and each channel correspondingly transmits read-out or write-in data in one flash memory chip, wherein K is more than or equal to 1 and less than or equal to P.
In this embodiment, the storage device may include a solid state disk (Solid State Drives, abbreviated as SSD), and the SSD may include: each SSD control chip can be connected with the main control chip through a PCIe protocol, and read or write data in one flash memory chip can be correspondingly transmitted through one channel in the P channels established by each SSD and the main control chip.
Fig. 2 is a block diagram of a memory system according to another exemplary embodiment of the present invention, and as shown in fig. 2, a main control chip may include a CPU core 111, an internal memory 112, and a programmable logic device 113 configured to implement data transfer between a memory device and an external device; the internal memory stores a distributed storage management program, and the CPU core runs the distributed storage management program to realize data writing and reading.
In this embodiment, an implementation manner of the main control chip may be implemented by using FGPA, the distributed storage system may be implemented by software of a CPU core built in the FPGA together with programmable hardware, and PCIe data transfer may be implemented by using a programmable logic device.
In an example embodiment of the present invention, the external device may include a CPU of a local host or a CPU of a remote host, and the main control chip may include an external communication interface; the main control chip can perform external communication with a computer system (such as a host) through an external communication interface.
In an example, the external communication interface may include: and the PCIe bus interface is configured to communicate with the CPU of the local host through the PCIe bus.
As shown in fig. 2, a plurality of storage devices (such as SSDs) are connected with a main control chip through PCIe protocol, and the whole system can be deployed on a motherboard to form a high bandwidth SSD. The composed high-bandwidth SSD can be inserted into a PCIe bus through a PCIe bus interface of the main control chip and connected to a local host.
In an example, the external communication interface may include: a CXL bus interface configured to communicate with the CPU of the local host via the CXL bus.
As shown in fig. 2, a plurality of storage devices (such as SSDs) are connected with a main control chip through PCIe protocol, and the whole system can be deployed on a motherboard to form a high bandwidth SSD. The composed high-bandwidth SSD can be inserted into a CXL bus through a CXL bus interface of a main control chip and connected to a local host.
In an example, the external communication interface may include: a network interface configured to communicate with the CPU of the remote host over a network.
Multiple storage devices (such as SSDs) are connected with a main control chip through a PCIe protocol, and the whole system can be deployed on a main board to form a high-bandwidth SSD. The composed high-bandwidth SSD can be connected to a remote host through a network interface access network of the main control chip.
In an exemplary embodiment of the present invention, PCIe Gen5 protocol may be used between the host chip and the plurality of memory devices, and the read/write bandwidth may exceed the dynamic random access memory (Dynamic Random Access Memory, DRAM) connected to the Double Data Rate (DDR) bus.
Fig. 3 is a flowchart of a data storage method according to an exemplary embodiment of the present invention, where an execution body of the data storage method is a storage system shown in any embodiment, and the data storage method may be applied to a storage system including a main control chip and N storage devices, where the N storage devices are connected to the main control chip through a PCIe protocol, and N is an integer not lower than 2. As shown in fig. 3, the data storage method may include:
s301: the main control chip receives the writing request and determines whether to perform distributed storage on the external storage object.
In this embodiment, the main control chip may cooperate with a plurality of storage devices, and external storage objects may be written into the storage devices in parallel through the main control chip.
In an example, the write request may carry the data size of the storage object; determining whether to store the external storage object in a distributed manner includes: and determining to store the storage object in a distributed mode when the data size of the storage object is larger than the size threshold.
A requestor (such as a host of a computer system) sends a write request to a storage system, the write request information may carry an object name, a data size, a starting address of existing data, and so on. The main control chip performs distributed storage on the storage objects with the sizes exceeding a set threshold.
S302: when the main control chip determines to perform distributed storage on the storage object, the data of the storage object are divided and then stored in N storage devices or part of storage devices in N storage devices in parallel.
When the main control chip determines that the storage objects are required to be stored in a distributed mode, the data of the storage objects are divided and stored in different storage devices respectively, and parallel data reading and writing are facilitated.
In an exemplary embodiment of the present invention, the data of the storage object is divided and then stored in parallel in N storage devices or part of N storage devices, respectively, may include:
dividing a storage object into M data packets, wherein M is greater than or equal to N, and M is far greater than N; and storing the M data packets into N storage devices in turn according to a preset sequence by taking the N data packets as units, wherein each N data packets in the M data packets are stored in the N storage devices in parallel, and one data packet is correspondingly stored into one storage device at a time.
When the number M of the data packets is not an integer multiple of N, the remaining data packets divided by N are respectively stored in the N partial storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time.
When the number M of the data packets is smaller than N, the data packets are respectively stored in partial storage devices in N in parallel, and one data packet is correspondingly stored in one storage device at a time.
When distributed storage is arranged, for a plurality of storage devices (such as SSDs) connected to a PCIe interface of a master control chip, the master control chip allocates a plurality of consecutive data packets to the plurality of storage devices, each data packet being allocated to one storage device.
In an example, the preset order may be based on an empirical value, the preset order may be a size order of the memory addresses of the data packets, or the preset order may be a number size order of the memory devices.
In an example embodiment of the present invention, the write request may further carry a name of the memory object and a current memory address of the data of the memory object, and the memory device may include a control chip and a flash memory chip connected to the control chip. The alternately storing the M data packets in the N storage devices in a preset order in units of N data packets may include:
the main control chip determines the sizes of M divided data packets according to the current storage address of the storage object, and determines the initial address of the M storage devices for taking data; the main control chip respectively sends write-in requests to the control chips of the N storage devices according to a preset sequence wheel, and the write-in requests carry the initial address of the data access of the storage devices and the size of the data packet to be fetched; the control chip of each memory device fetches data from the corresponding data fetch starting address through PCIe protocol and writes the data into the connected flash memory chip.
The main control chip divides the data of the storage object into a plurality of data packets, and after distributing a corresponding storage device for each data packet, the main control chip sends a writing request to the plurality of storage devices, wherein the writing request can carry the initial address of each storage device for taking the data. Each memory device will fetch data on the corresponding address via PCIe protocol, writing to flash memory. Repeating the steps until all the data are written.
Fig. 4 is a flowchart of a data storage method according to another exemplary embodiment of the present invention, where an execution body of the data storage method is a storage system shown in any embodiment, and the data storage method may be applied to a storage system including a main control chip and N storage devices, where the N storage devices are connected to the main control chip through a PCIe protocol, and N is an integer not lower than 2. As shown in fig. 4, the data storage method may include:
s401: and the main control chip receives the reading request and determines whether the storage object to be read is stored in a distributed mode.
In this embodiment, the main control chip may cooperate with a plurality of storage devices, and the data of the storage object may be read in parallel from the plurality of storage devices through the main control chip.
S402: when the main control chip determines that the storage objects to be read are stored in a distributed mode, data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to the outside.
When the main control chip determines that the storage object is required to be read from the storage device, whether the storage object to be read is stored in a distributed mode or not is determined, if the storage object is stored in the distributed mode, the main control chip sends a reading request to all the storage devices storing the storage object, corresponding data are read in parallel from all the storage devices storing the storage object, and parallel data reading is facilitated.
In an example embodiment of the present invention, the read request may carry a name of the memory object, and a receiving address for receiving data of the read memory object, and the memory device may include a control chip and a flash memory chip connected to the control chip. Reading data of the storage object in the N storage devices or in part of the N storage devices in parallel and transmitting the data to the outside may include:
the main control chip determines all storage devices of the distributed storage object according to the names of the storage objects, and determines the initial address of each storage device for writing data to the outside according to the receiving address and the size of a data packet in each storage device; the main control chip respectively sends a read request to all storage devices of the distributed storage object and carries a start address of the sent storage device for writing data to the outside; the control chip of each memory device reads data from the connected flash memory chip and writes data to the corresponding start address of the write data through the PCIe protocol.
The requestor (e.g., an external host) sends a read request (or read request) to the storage system, which may carry the object name, the starting memory address for receiving the data, etc.
If the storage object is stored in a distributed manner, the main control chip sends a read request to all storage devices (such as SSDs) storing the object, calculates the start address of the received data corresponding to each storage device, and includes the start address of the received data corresponding to each storage device in the read request. Each memory device will read data from the flash memory and send the read data to the corresponding address, repeating the above steps until all data reads are completed.
FIG. 5 is a block diagram of a computer system according to an exemplary embodiment of the present invention, where, as shown in FIG. 5, the computer system may include: host 51, bus 52, and storage system 53, which may be a PCIe bus or a CXL bus, using the storage system of any of the embodiments shown.
Multiple storage devices (such as SSD control chips) are connected with the main control chip through PCIe protocol, and the whole system can be deployed on a main board to form a high-bandwidth SSD. The composed high bandwidth SSD may be plugged onto the host's PCIe bus or accessed to the host through the CXL protocol.
Fig. 6 is a block diagram of a main control chip according to an exemplary embodiment of the present invention, and as shown in fig. 6, the main control chip includes a memory 61 and a controller 62.
The memory is used to store instructions for execution and the processor may be a central processing unit (Central Processing Unit, CPU for short), or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), or one or more integrated circuits that implement embodiments of the present invention. When the main control chip runs, the processor communicates with the memory, and the processor calls an execution instruction for executing a data storage method and a data reading and writing method;
the data storage method comprises the following steps: when a write-in request is received and distributed storage is carried out on an external storage object, dividing the data of the storage object, and respectively and parallelly storing the data into N storage devices or partial storage devices in N storage devices, wherein N is an integer not lower than 2;
the data reading and writing method comprises the following steps: and when a reading request is received and the storage objects to be read are determined to be stored in a distributed mode, the data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to an external device.
In an example embodiment of the invention, the write request carries a data size of the storage object;
the determining whether to perform distributed storage on the external storage object includes: and when the data size of the storage object is larger than a size threshold value, the main control chip determines to store the storage object in a distributed mode.
In an example embodiment of the present invention, the main control chip divides the data of the storage object and then stores the divided data in parallel into N storage devices or a part of N storage devices, including:
dividing the storage object into M data packets, wherein M is more than or equal to N; the method comprises the steps of alternately storing M data packets into N storage devices according to a preset sequence by taking N data packets as units, wherein each N data packets in the M data packets are stored in the N storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time;
when the number M of the data packets is not an integer multiple of N, the remaining data packets divided by N are respectively stored in the N partial storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time.
In an example embodiment of the present invention, the write request further carries a name of the storage object and a current storage address of data of the storage object, and the storage device includes a control chip and a flash memory chip connected to the control chip;
the alternately storing the M data packets to N storage devices in a preset sequence with N data packets as a unit includes:
the main control chip determines the sizes of the M divided data packets according to the current storage address of the storage object, and determines the initial address of the M storage devices for taking data;
the main control chip respectively sends write-in requests to the control chips of the N storage devices according to a preset sequence, and the write-in requests carry the initial address of the data access of the storage device and the size of the data packet to be fetched;
the control chip of each memory device fetches data from the corresponding data fetch starting address through PCIe protocol and writes the data into the connected flash memory chip.
In an exemplary embodiment of the present invention, the read request carries a name of the storage object, and a receiving address for receiving data of the read storage object, and the storage device includes a control chip and a flash memory chip connected to the control chip;
the parallel reading of the data of the storage object in the N storage devices or in the partial storage devices in the N storage devices and transmitting to the outside includes:
the main control chip determines all storage devices for storing the storage objects in a distributed mode according to the names of the storage objects, and determines a starting address of each storage device for writing data to the outside according to the receiving address and the size of a data packet in each storage device;
the main control chip respectively sends a read request to all storage devices for storing the storage objects in a distributed mode, and carries a start address of the sent storage devices for writing data to the outside;
the control chip of each memory device reads data from the connected flash memory chip and writes data to the corresponding start address of the write data through the PCIe protocol.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (17)
1. The storage system is inserted into a PCIe bus of the system or accessed into the system through CXL protocol, and is characterized by comprising a main control chip and N storage devices, wherein N is an integer not lower than 2;
and the main control chip is in communication connection with the N storage devices based on PCIe protocol.
2. The memory system of claim 1, wherein the master control chip is configured to implement data writing and data reading;
the data writing includes: when a write-in request is received and distributed storage is carried out on an external storage object, dividing the data of the storage object and respectively and parallelly storing the data into N storage devices or part of the N storage devices; the data readout includes: and when a reading request is received and the storage objects to be read are determined to be stored in a distributed mode, the data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to an external device.
3. The storage system of claim 2, wherein the memory is configured to store the data,
the external equipment comprises a CPU of a local host or a CPU of a remote host;
the main control chip comprises an external communication interface;
the external communication interface includes: the PCIe bus interface is configured to communicate with the CPU of the local host through the PCIe bus;
or,
the external communication interface includes: a CXL bus interface configured to communicate with a CPU of a local host via a CXL bus;
or,
the external communication interface includes: a network interface configured to communicate with a CPU of a remote host over a network.
4. The memory system of claim 2, wherein the master control chip determines to distributively store the external memory object when the data size of the memory object is greater than a size threshold.
5. The storage system of claim 4, wherein each of the storage devices comprises: SSD control chip and K flash memory chips, K is greater than or equal to 1;
each SSD control chip is connected to the K channels of PCIe, and each channel correspondingly transmits read or write data in one flash memory chip.
6. The memory system of any one of claims 1-5, wherein the master control chip comprises a CPU core, an internal memory, and a programmable logic device configured to enable data transfer between the memory device and an external device; the internal memory stores a distributed storage management program, and the CPU kernel runs the distributed storage management program to realize the data writing and reading.
7. The main control chip is characterized by comprising a memory and a controller, wherein the memory is used for storing an execution instruction; the processor calls the execution instruction to execute a data storage method and a data reading and writing method;
the data storage method comprises the following steps: when a write-in request is received and distributed storage is carried out on an external storage object, dividing the data of the storage object, and respectively and parallelly storing the data into N storage devices or partial storage devices in N storage devices, wherein N is an integer not lower than 2;
the data reading and writing method comprises the following steps: and when a reading request is received and the storage objects to be read are determined to be stored in a distributed mode, the data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to an external device.
8. The master control chip of claim 7, wherein the write request carries a data size of the memory object;
the determining whether to perform distributed storage on the external storage object includes: and when the data size of the storage object is larger than a size threshold value, the main control chip determines to store the storage object in a distributed mode.
9. The main control chip according to claim 7, wherein the main control chip divides the data of the storage object and then stores the divided data in N storage devices or a part of N storage devices in parallel, and the main control chip comprises:
dividing the storage object into M data packets, wherein M is more than or equal to N; the method comprises the steps of alternately storing M data packets into N storage devices according to a preset sequence by taking N data packets as units, wherein each N data packets in the M data packets are stored in the N storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time;
when the number M of the data packets is not an integer multiple of N, the remaining data packets divided by N are respectively stored in the N partial storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time.
10. The master control chip of claim 9, wherein the write request further carries a name of the memory object and a current memory address of data of the memory object, the memory device comprising a control chip and a flash memory chip connected to the control chip;
the alternately storing the M data packets to N storage devices in a preset sequence with N data packets as a unit includes:
the main control chip determines the sizes of the M divided data packets according to the current storage address of the storage object, and determines the initial address of the M storage devices for taking data;
the main control chip respectively sends write-in requests to the control chips of the N storage devices according to a preset sequence, and the write-in requests carry the initial address of the data access of the storage device and the size of the data packet to be fetched;
the control chip of each memory device fetches data from the corresponding data fetch starting address through PCIe protocol and writes the data into the connected flash memory chip.
11. The main control chip according to claim 7, wherein the read request carries a name of the memory object and a receiving address for receiving data of the read memory object, the memory device including a control chip and a flash memory chip connected to the control chip;
the parallel reading of the data of the storage object in the N storage devices or in the partial storage devices in the N storage devices and transmitting to the outside includes:
the main control chip determines all storage devices for storing the storage objects in a distributed mode according to the names of the storage objects, and determines a starting address of each storage device for writing data to the outside according to the receiving address and the size of a data packet in each storage device;
the main control chip respectively sends a read request to all storage devices for storing the storage objects in a distributed mode, and carries a start address of the sent storage devices for writing data to the outside;
the control chip of each memory device reads data from the connected flash memory chip and writes data to the corresponding start address of the write data through the PCIe protocol.
12. The data storage method is characterized by being applied to a storage system comprising a main control chip and N storage devices, wherein the N storage devices are connected with the main control chip through a PCIe protocol, and N is an integer not lower than 2, and the method comprises the following steps:
the main control chip receives the writing request and determines whether to perform distributed storage on an external storage object;
when the main control chip determines to perform distributed storage on the storage object, the data of the storage object are divided and then stored in N storage devices or part of the N storage devices in parallel.
13. The method of claim 12, wherein the write request carries a data size of the storage object;
the determining whether to perform distributed storage on the external storage object includes: and when the data size of the storage object is larger than a size threshold value, the main control chip determines to store the storage object in a distributed mode.
14. The method of claim 12, wherein the master control chip divides the data of the storage object and then stores the divided data in parallel in N storage devices or a part of N storage devices, including:
dividing the storage object into M data packets, wherein M is more than or equal to N; the method comprises the steps of alternately storing M data packets into N storage devices according to a preset sequence by taking N data packets as units, wherein each N data packets in the M data packets are stored in the N storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time;
when the number M of the data packets is not an integer multiple of N, the remaining data packets divided by N are respectively stored in the N partial storage devices in parallel, and one data packet is correspondingly stored in one storage device at a time.
15. The method of claim 14, wherein the write request further carries a name of the memory object and a current memory address of the data of the memory object, the memory device comprising a control chip and a flash memory chip connected to the control chip;
the alternately storing the M data packets to N storage devices in a preset sequence with N data packets as a unit includes:
the main control chip determines the sizes of the M divided data packets according to the current storage address of the storage object, and determines the initial address of the M storage devices for taking data;
the main control chip respectively sends write-in requests to the control chips of the N storage devices according to a preset sequence, and the write-in requests carry the initial address of the data access of the storage device and the size of the data packet to be fetched;
the control chip of each memory device fetches data from the corresponding data fetch starting address through PCIe protocol and writes the data into the connected flash memory chip.
16. The data reading method is characterized by being applied to a storage system comprising a main control chip and N storage devices, wherein the N storage devices are connected with the main control chip through a PCIe protocol, and N is an integer not lower than 2, and the method comprises the following steps:
the main control chip receives a reading request and determines whether a storage object to be read is stored in a distributed mode;
and when the main control chip determines that the storage objects to be read are stored in a distributed mode, the data of the storage objects in N storage devices or part of storage devices in N storage devices are read in parallel and transmitted to the outside.
17. The method of claim 16, wherein the read request carries a name of the memory object and a receiving address for receiving data of the read memory object, the memory device comprising a control chip and a flash memory chip connected to the control chip;
the parallel reading of the data of the storage object in the N storage devices or in the partial storage devices in the N storage devices and transmitting to the outside includes:
the main control chip determines all storage devices for storing the storage objects in a distributed mode according to the names of the storage objects, and determines a starting address of each storage device for writing data to the outside according to the receiving address and the size of a data packet in each storage device;
the main control chip respectively sends a read request to all storage devices for storing the storage objects in a distributed mode, and carries a start address of the sent storage devices for writing data to the outside;
the control chip of each memory device reads data from the connected flash memory chip and writes data to the corresponding start address of the write data through the PCIe protocol.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210828397.8A CN117435535A (en) | 2022-07-13 | 2022-07-13 | Storage system, main control chip, data storage method and data reading method |
| PCT/CN2023/091887 WO2024012015A1 (en) | 2022-07-13 | 2023-04-28 | Storage system, main control chip, data storage method and data reading method |
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| CN202210828397.8A CN117435535A (en) | 2022-07-13 | 2022-07-13 | Storage system, main control chip, data storage method and data reading method |
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|---|---|---|---|---|
| US7822912B2 (en) * | 2005-03-14 | 2010-10-26 | Phision Electronics Corp. | Flash storage chip and flash array storage system |
| US20100125695A1 (en) * | 2008-11-15 | 2010-05-20 | Nanostar Corporation | Non-volatile memory storage system |
| US20100017650A1 (en) * | 2008-07-19 | 2010-01-21 | Nanostar Corporation, U.S.A | Non-volatile memory data storage system with reliability management |
| KR20180130140A (en) * | 2017-05-29 | 2018-12-07 | 에스케이하이닉스 주식회사 | Data processing system and data processing method |
| US11442646B2 (en) * | 2020-09-09 | 2022-09-13 | Western Digital Technologies Inc. | Identified zones for optimal parity sharing zones |
| CN113778333A (en) * | 2021-08-25 | 2021-12-10 | 戴瑾 | Combined chip, storage device and operation method for storage object |
| CN115982078A (en) * | 2023-01-19 | 2023-04-18 | 北京超弦存储器研究院 | CXL memory module and memory storage system |
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