WO2024011807A1 - 数据驱动电路、显示模组以及输出驱动信号的方法 - Google Patents

数据驱动电路、显示模组以及输出驱动信号的方法 Download PDF

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Publication number
WO2024011807A1
WO2024011807A1 PCT/CN2022/132868 CN2022132868W WO2024011807A1 WO 2024011807 A1 WO2024011807 A1 WO 2024011807A1 CN 2022132868 W CN2022132868 W CN 2022132868W WO 2024011807 A1 WO2024011807 A1 WO 2024011807A1
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Prior art keywords
grayscale
gray
pulses
duration
data
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PCT/CN2022/132868
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English (en)
French (fr)
Inventor
周满城
郭东胜
康报虹
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惠科股份有限公司
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Publication of WO2024011807A1 publication Critical patent/WO2024011807A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present application relates to the field of display technology, and in particular to data driving circuits, display modules and methods of outputting driving signals.
  • Mini-LED refers to an LED chip with a size of 100um. Compared with ordinary LEDs, it has a higher density per unit area and a smaller light source unit size. Compared with Liquid Crystal Display (LCD), Mini-LED display has better display effect, response speed has been improved by orders of magnitude, the screen can be thinner and lighter, and consumes less power.
  • LCD Liquid Crystal Display
  • Mini-LED when displaying low brightness, due to the existence of parasitic capacitance, the proportion of current flowing through Mini-LED is small, resulting in color cast during display.
  • the present application provides a data driving circuit that effectively improves display color shift.
  • a data drive circuit includes a data processing unit, a grayscale clock generation unit and an output unit.
  • the data processing unit outputs a data clock signal to the grayscale clock generation unit and outputs a data signal for displaying an image to the output unit.
  • the data clock signal has The first pulse width duration.
  • the first pulse width duration in a frame of image display duration is the longest time for the pixel unit performing image display to receive the data signal.
  • the grayscale clock generation unit outputs a grayscale clock signal based on the data clock signal.
  • the grayscale clock signal is
  • the gray-scale clock signal includes N consecutive gray-scale pulses.
  • the N consecutive gray-scale pulses include a plurality of first gray-scale pulses with a first duration and a plurality of second gray-scale pulses with a second duration.
  • the first The duration is longer than the second duration, and the output unit is used to receive the data signal.
  • the gray-scale brightness corresponding to the data signal is less than or equal to the first threshold, count the first gray-scale pulses according to the magnitude of the gray-scale brightness corresponding to the data signal. And obtain a count pulse, output the driving signal according to the duration of a count pulse, when the gray scale brightness corresponding to the data signal is greater than the first threshold, count the second gray scale pulse according to the size of the gray scale brightness corresponding to the data signal and b count pulses are obtained, and the drive signal is output according to the duration of the b count pulses.
  • the drive signal is used to drive the pixel unit to display the image, 1 ⁇ a ⁇ N, 1 ⁇ b ⁇ N.
  • the grayscale clock signal includes a first grayscale area and a second grayscale area
  • the first grayscale area includes the 1st to x grayscale pulses
  • the first grayscale pulse is any of the 1st to x grayscale pulses.
  • One grayscale pulse; the second grayscale area includes the x+1 ⁇ Nth grayscale pulse, and the second grayscale pulse is any grayscale pulse among the x+1 ⁇ Nth grayscale pulse; the 1st ⁇ x grayscale pulse
  • the duration of any gray-scale pulse in is less than or equal to the first threshold
  • the gray-scale pulses in the first gray-scale area are counted according to the magnitude of the gray-scale brightness corresponding to the data signal and a count pulses are obtained, 1 ⁇ a ⁇ x
  • a driving signal is output according to a counting pulse duration; when the gray-scale brightness corresponding to the data signal is greater than the first threshold, the gray-scale pulses in the second gray-scale area are counted according to the gray-scale brightness corresponding to the data
  • the duration of each grayscale pulse in the first grayscale area is the same, and the duration of each grayscale pulse in the second grayscale area is the same.
  • the first grayscale area includes at least two grayscale pulses with different durations, and each grayscale pulse in the second grayscale area has the same duration.
  • the number of gray pulses in the first gray region is less than or equal to the number of gray pulses in the second gray region.
  • the grayscale clock generation module is used to divide and/or multiply the frequency of the data clock signal to control the first pulse width duration in the data clock signal to correspond to N grayscale pulses.
  • the application also discloses a method for the aforementioned data driving circuit to output a driving signal, which outputs a data clock signal to a grayscale clock generation unit and a data signal for displaying an image to an output unit, where the data clock signal has a first pulse width duration, and The first pulse width duration in one frame of image display is the longest time for the pixel unit performing image display to receive the data signal; a grayscale clock signal is output according to the data clock signal, and the grayscale clock signal includes N consecutive grayscale pulses.
  • the N consecutive gray pulses include a plurality of first gray pulses with a first duration and a plurality of second gray pulses with a second duration, where the first duration is greater than the second duration; when the data signal corresponds to When the gray-scale brightness is less than or equal to the first threshold, the first gray-scale pulses are counted according to the gray-scale brightness corresponding to the data signal and a counting pulses are obtained, and the driving signal is output according to the duration of a counting pulses.
  • the second gray-scale pulses are counted according to the size of the gray-scale brightness corresponding to the data signal and b count pulses are obtained, and the driving signal is output according to the duration of the b count pulses, and the driving signal is used
  • Driving the pixel unit to display the image 1 ⁇ a ⁇ N, 1 ⁇ b ⁇ N.
  • "outputting a grayscale clock signal based on the data clock signal” includes: applying a voltage corresponding to standard white to the pixel unit, determining the color coordinates corresponding to the current display color of the pixel unit according to the color gamut map, and comparing the current color of the pixel unit.
  • the color coordinate corresponding to the standard white Adjust the duration of the 1st to x grayscale pulses in the first grayscale area to control the pixel unit to display standard white.
  • the current color coordinate of the pixel unit is the color coordinate of standard white, obtain The adjusted 1st to x grayscale pulses.
  • applying a voltage corresponding to standard white to the pixel unit in the display area includes applying a voltage corresponding to standard red, standard green, or standard blue to the pixel unit in the display area.
  • outputting a grayscale clock signal based on the data clock signal includes: controlling the pixel unit to display standard white, determining the standard amount of charge flowing through the pixel unit, and adjusting the second grayscale in the first grayscale area.
  • the duration of the 1-x grayscale pulses is such that the amount of charge flowing through the pixel unit is controlled to be the standard charge amount, and the adjusted 1st-x grayscale pulses are obtained.
  • the application also discloses a display module including a display control circuit, a scan drive circuit, a display panel, a light emitting controller and the aforementioned data drive circuit.
  • the display control circuit receives the original data signal based on an external signal source and outputs the source respectively. control signal and gate control signal.
  • the data driving circuit cooperates with the light-emitting controller to control the display panel to display images based on the source control signal and the scan driving circuit based on the gate control signal.
  • the display panel is provided with a plurality of scan lines extending along the first direction and a plurality of data lines extending along the second direction F2, and pixels are respectively provided at intersections of the plurality of scan lines and the plurality of data lines.
  • the pixel unit is a light-emitting diode
  • the anode of the light-emitting diode is connected to the scan line to receive the scan signal
  • the cathode is connected to the data line to receive the data signal.
  • the data driving circuit disclosed in this application adjusts the duration of the gray pulse in the first gray area to increase the duration of the first gray pulse to eliminate the problem of the display panel displaying low gray levels.
  • the color cast that occurs effectively improves the color cast problem when the display panel displays low grayscale and improves the display effect.
  • Figure 1 is a schematic structural diagram of a display device provided by the first embodiment of the present application.
  • Figure 2 is a schematic diagram of the plan layout structure of the display module shown in Figure 1 according to the second embodiment of the present application;
  • Figure 3 is a schematic diagram of the connection of the pixel units in Figure 2;
  • Figure 4 is a circuit block diagram of the data driving circuit shown in Figure 2 in a third embodiment of the present application.
  • FIG. 5 is a schematic diagram of the frequency multiplication/frequency division principle of the grayscale clock generation unit in Figure 4;
  • Figure 6 is a schematic diagram of the gray pulses in the gray clock signal in Figure 4.
  • Figure 7 is a schematic diagram of the standard color gamut
  • Figure 8 is a schematic diagram of gray pulses in the gray clock signal provided by the fourth embodiment of the present application.
  • Figure 9 is a method of outputting a driving signal provided by the fifth embodiment of the present application.
  • connection and “connection” mentioned in this application include direct and indirect connections (connections) unless otherwise specified.
  • the directional terms mentioned in this application such as “up”, “down”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only Reference is made to the direction of the attached drawings.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be a mechanical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be a mechanical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • the specific meanings of the above terms in this application can be understood on a case-by-case basis.
  • the terms “first”, “second”, etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than describing a specific sequence.
  • the terms “include”, “can include”, “include”, or “can include” used in this application indicate the existence of the corresponding disclosed functions, operations, elements, etc., and do not limit other one or more more Functions, operations, components, etc.
  • the term “comprises” or “comprises” indicates the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but does not exclude the presence or addition of one or more other features, numbers, steps, Operations, elements, parts, or combinations thereof, are intended to cover non-exclusive inclusion.
  • a display device may generally include a display panel and a backlight assembly, wherein the display panel is mounted to the light exit side of the backlight assembly, and the backlight assembly is used to provide backlight to the display panel to adjust the display.
  • the panel displays different images.
  • FIG. 1 is a schematic structural diagram of a display device 100 provided in the first embodiment of the present application.
  • the display device 100 includes the display device 100 .
  • the display module 10 and the power module 20 are fixed on the support frame 30 .
  • the power module 20 is disposed on the back of the display module 10 for providing power voltage to the display module 10 .
  • FIG. 2 is a schematic diagram of the plan layout structure of the display module 10 shown in FIG. 1 according to the second embodiment of the present application.
  • the display module 10 also includes a data driving circuit 11 , a scanning driving circuit 12 and a display panel 13 , a display control circuit 14 and a light emitting controller 16 .
  • the data driving circuit 11 , the scanning driving circuit 12 , the display control circuit 14 and the light emitting controller 16 are provided in the non-display area of the display panel 13 .
  • the display area 13a of the display panel 13 is provided with a plurality of scanning lines (Gate lines) G1-Gn extending along the first direction F1 and a plurality of data lines (Source lines) extending along the second direction F2 in a grid shape. )S1 ⁇ Sm.
  • the first direction F1 and the second direction F2 are perpendicular to each other, and the plurality of scanning lines G1 to Gn, the plurality of data lines S1 to Sm, and the scanning lines G1 to Gn and the data lines S1 to Sm are insulated from each other. .
  • the pixel units 15 are respectively provided at the intersections of the plurality of scanning lines G1 to Gn and the data lines S1 to Sm.
  • the pixel units 15 can be respectively represented as P11 ⁇ P1m, P21 ⁇ P2m, ..., Pn1 ⁇ Pnm.
  • the scan lines G1 to Gn are connected to the scan drive circuit 12 and receive scan signals from the scan drive circuit 12.
  • the data lines S1 to Sm are connected to the data drive circuit 11 and are used to receive data stored and transmitted in the form of grayscale values provided by the data drive circuit 11. SignalData.
  • the display control circuit 14 receives the original image signal representing image information, the clock signal CLK for synchronization, the horizontal synchronization signal Hsyn, and the vertical synchronization signal Vsyn from an external signal source, and outputs a gate control signal used to control the scan drive circuit 12 Cg, the source control signal Cs used to control the data driving circuit 11 and the data signal Data representing image information.
  • the display control circuit 14 performs data adjustment processing on the original data signal to obtain the data signal Data, and transmits the data signal Data to the data driving circuit 11 .
  • the scan driver circuit 12 receives the gate control signal Cg output from the display control circuit 14 and outputs scan signals to the respective scan lines G1 to Gn.
  • the data driving circuit 11 receives the source control signal Cs, the clock signal CLK and the data signal Data output from the display control circuit 14, and outputs to each data line S1 to Sm a signal for driving the elements in each pixel unit 15 of the display panel 13 to perform image display. drive signal.
  • the light-emitting controller 16 is used to apply light-emitting signals to a plurality of pixels to control the pixel unit 15 to emit light, so as to control the pixel unit 15 to display a corresponding image.
  • FIG. 3 is a schematic connection diagram of the pixel unit 15 in FIG. 2 .
  • the pixel unit 15 includes a light-emitting diode.
  • the anode of the light-emitting diode is connected to the scanning lines G1 ⁇ Gn, and the cathode is connected to the data lines S1 ⁇ Sm.
  • Each scanning line is provided with a P-type MOS tube.
  • the P-type MOS tube When the gate is at a low voltage potential, the source and drain of the P-type MOS tube are turned on, allowing the light-emitting diodes connected to the scan lines to receive corresponding scan signals, causing the anode voltage to rise.
  • the data drive circuit 11 can control the brightness of the light-emitting diode through pulse width modulation (Pulse WidT Modulation, PWM). The wider the pulse width of the light-emitting diode, the higher the brightness.
  • PWM pulse width modulation
  • the data driving circuit includes a data processing unit 111 , a grayscale clock generation unit 112 and an output unit 113 .
  • the data processing unit 111 is used to receive and store the data clock signal DCLK and the data signal Data. After processing, the data clock signal DCLK is transmitted to the grayscale clock generation unit 112 and the data signal Data is transmitted to the output unit 113 respectively.
  • the data clock signal DCLK is used to control the output timing of the data signal Data.
  • the data clock signal has a first pulse width duration H. In a frame of image display duration, the first pulse width duration H is for the pixel unit that performs image display to receive the data signal Data. the longest time.
  • the gray clock generation unit 112 is used to receive the data clock signal DCLK and perform frequency multiplication/division processing on the data clock signal to generate the gray clock signal GCLK.
  • the gray clock signal GCLK is used to control the gray level.
  • the grayscale clock signal GCLK includes N consecutive grayscale pulses, wherein the N consecutive grayscale pulses include a plurality of first grayscale pulses with a first duration and a plurality of second grayscales with a second duration. Pulse, the first duration is longer than the second duration, the i-th grayscale corresponds to i grayscale pulse, 1 ⁇ i ⁇ N, N can be determined according to specific needs, and can be 128, 256, etc., this application does not limit it.
  • the output unit 113 is used to receive the data signal Data and the grayscale clock signal GCLK, count the grayscale pulses in the grayscale clock signal GCLK, and generate an output waveform of the PWM signal corresponding to the data signal Data based on the data result, as well. That is, the grayscale pulse duration corresponding to the data signal Data is used to control the pixel unit 15 to display images.
  • the first gray-scale pulses are counted according to the magnitude of the gray-scale brightness corresponding to the data signal and a count pulses are obtained.
  • a count pulses The duration of the driving signal is output.
  • the second gray-scale pulses are counted according to the gray-scale brightness corresponding to the data signal and b count pulses are obtained.
  • the b count pulse duration Output the driving signal, which is used to drive the pixel unit to display the image, 1 ⁇ a ⁇ N, 1 ⁇ b ⁇ N.
  • Figure 5 is a schematic diagram of the frequency multiplication/frequency division principle of the grayscale clock generation unit in Figure 4.
  • the first pulse width H in the data clock signal DCLK is the time to scan one row of pixel units, and is converted into the gray clock signal GCLK by the gray clock generation unit 112.
  • the gray clock signal GCLK converts the first pulse width H into the gray clock signal GCLK.
  • the H data clock signal DCLK is converted into N gray-scale pulses, where the i-th gray level corresponds to the i gray-scale pulses, 1 ⁇ i ⁇ N.
  • a pulse width T includes one pulse, that is, one pulse width T represents grayscale 1, two pulse widths T represent grayscale 2, three pulse widths T represent grayscale 3, and so on, by controlling the pulse width T
  • the length thereby controls the grayscale displayed by the pixel unit 15.
  • the gray level is determined by the number of the same pulse width T and has nothing to do with the starting time of the pulse width T.
  • gray level 3 can start from the first pulse width T and end at the third pulse width T, or it can start from the third pulse width T.
  • the four pulse widths T start and end with the seventh pulse width T. That is to say, the pixel unit 15 displays the preset grayscale and can select the grayscale from any time point within the data clock signal DCLK of the first pulse width H.
  • Clock GCLK turns on for a preset number of pulse widths T.
  • the grayscale clock signal GCLK includes N consecutive grayscale pulses, and the N consecutive grayscale pulses include a plurality of first grayscale pulses with a first duration and a plurality of second grayscale pulses.
  • the first duration is longer than the second duration.
  • the grayscale clock signal GCLK includes a first grayscale area GL and a second grayscale area GH.
  • the first grayscale area GL includes the 1st to x grayscale pulses, that is, a plurality of first grayscale pulses.
  • the area GH includes the x+1 ⁇ Nth grayscale pulse, that is, a plurality of second grayscale pulses, and the duration of any one of the 1st ⁇ xth grayscale pulses is longer than the x+1 ⁇ Nth grayscale pulse.
  • the number of gray pulses in the first gray region GL is less than or equal to the number of gray pulses in the second gray region GH.
  • the gray-scale pulses in the first gray-scale area GL are counted according to the magnitude of the gray-scale brightness corresponding to the data signal Data and a count pulse is obtained, 1 ⁇ a ⁇ x, the driving signal is output according to the duration of a count pulse.
  • the gray-scale pulses in the second gray-scale area GH are counted according to the magnitude of the gray-scale brightness corresponding to the data signal Data and b count pulses are obtained, x ⁇ b ⁇ N, the driving signal is output according to the duration of b count pulses.
  • the first threshold is 32, and when the first grayscale area GL includes 64 grayscales, the first threshold is 64, that is, the first threshold is the first grayscale.
  • the original grayscale clock signal GCLK_0 is an unadjusted grayscale clock signal, in which the duration of the grayscale pulses in the first grayscale area GL is the same, the duration of the grayscale pulses in the second grayscale area GH is the same, and the duration of the grayscale pulses in the first grayscale area GL is the same.
  • the grayscale pulses in the grayscale area GL and the second grayscale area GH have the same duration.
  • the first pulse width H in the data clock signal DCLK corresponds to 256 gray pulses in the gray clock signal GCLK.
  • 256 gray pulses correspond to 256 grays.
  • One pulse width T includes A grayscale pulse.
  • the first threshold is 64, that is, grayscales 0 to 63 are set as the first grayscale area GL, and grayscales 64 to 255 are set as the second grayscale area GH.
  • the 64 gray pulses in the first gray area GL are the same, that is, the pulse width Ta is the same.
  • the 192 gray pulses in the second gray area GH are the same, that is, the pulse width Tb is the same.
  • One pulse width in the first gray area GL The duration of Ta is longer than the duration of one pulse width Tb in the second grayscale area GH, that is, the duration of one grayscale pulse in the first grayscale area GL is longer than the duration of one grayscale pulse in the second grayscale area GH.
  • a pulse width Ta in the first grayscale area GL can be set to 0.5ms
  • a pulse width Tb in the second grayscale area GH can be set to 0.3ms.
  • it can also be other values, which are not limited by this application.
  • the pulse width setting of the first gray scale area GL and the second gray scale area GH is mainly adjusted based on the parasitic capacitance in the display panel 13. Due to the existence of the parasitic capacitance, the pulse width actually flows through the pixel unit 15, that is, the light emitting diode. The current becomes smaller, resulting in the grayscale displayed by the pixel unit 15 not reaching the preset grayscale, and a color cast occurs. This is because when the pixel unit 15 performs low grayscale display, the current flowing through the pixel unit 15 is small, so the color cast occurs. It mainly occurs when the pixel unit 15 performs low-grayscale display. Therefore, by setting the duration of each pulse width Ta in the first grayscale area GL to be longer, the color cast caused by the parasitic capacitance is offset.
  • the amount of charge flowing through the pixel unit 15 can be controlled to ensure the grayscale displayed by the pixel unit 15.
  • the pixel unit 15 is not only controlled by the current, but also by the PWM signal, that is, the number of pulse widths T in the grayscale clock signal GCLK. Determined, and the effect of time on brightness is linear.
  • the constant k can be obtained by testing the parasitic capacitance in the display panel 13 , that is, by debugging the corresponding relationship between the brightness Lv and the charge Q when no color cast occurs, and the constant k can be obtained.
  • the color gamut map can also be used to determine whether the pixel unit 15 has a color cast, so as to set the pulse width T in the grayscale clock signal GCLK.
  • Figure 7 is a schematic diagram of the standard color gamut. Among them, the standard red color coordinates are (0.67,0.33), the standard green color coordinates are (0.21,0.71), the standard blue color coordinates are (0.14,0.08), and the standard white color coordinates are (0.33,0.33).
  • the real display color of the pixel unit 15 corresponds to the color coordinates in the standard color gamut diagram, and then by debugging the first grayscale area GL in the grayscale clock signal GCLK.
  • the duration of a pulse width Ta, when the color displayed by the pixel unit 15 after debugging is the standard color, the pulse width at this time is the optimal pulse width.
  • the pixel unit 15 is controlled to display standard red, that is, the color coordinates in the corresponding color gamut diagram are (0.67, 0.33). At this time, the color displayed by the pixel unit 15 corresponds to the color coordinates in the color gamut diagram (0.67, 0.25) and There are certain differences in the standard red color coordinates. Then adjust the pulse width Ta of the first grayscale area GL in the grayscale clock signal GCLK. If the pulse width Ta is 0.5ms, the pixel unit 15 displays standard red, that is, the color coordinates are (0.67, 0.33), and the pulse width at this time is A width of 0.5ms is the required pulse width, thus eliminating the color shift caused by parasitic capacitance.
  • the pulse width in the second grayscale area GH can also be modulated as described above to eliminate the color cast phenomenon in the second grayscale area GH.
  • the grayscale clock signal GCLK includes N consecutive grayscale pulses.
  • the N consecutive grayscale pulses include a plurality of first grayscale pulses with a first duration and a plurality of second grayscale pulses.
  • the first duration is longer than the second duration.
  • the grayscale clock signal GCLK includes a first grayscale area GL and a second grayscale area GH.
  • the first grayscale area GL includes the 1st to x grayscale pulses, that is, a plurality of first grayscale pulses.
  • the second grayscale area GH includes the x+1 ⁇ Nth grayscale pulse, that is, a plurality of second grayscale pulses, and the duration of any one of the 1st ⁇ xth grayscale pulses is longer than the x+1 ⁇ Nth grayscale pulse.
  • the first grayscale area GL includes at least two first grayscale pulses with different durations, and each grayscale pulse in the second grayscale area GH has the same duration.
  • the number of gray pulses in the first gray region GL is less than or equal to the number of gray pulses in the second gray region GH.
  • the original grayscale clock signal GCLK_0 is an unadjusted grayscale clock signal, in which the duration of the grayscale pulses in the first grayscale area GL is the same, the duration of the grayscale pulses in the second grayscale area GH is the same, and the duration of the grayscale pulses in the first grayscale area GL is the same.
  • the grayscale pulses in the grayscale area GL and the second grayscale area GH have the same duration.
  • the first pulse width H in the data clock signal DCLK corresponds to 256 gray pulses in the gray clock signal GCLK.
  • 256 gray pulses correspond to 256 grays.
  • One pulse width T includes A grayscale pulse.
  • the first threshold is 64, that is, grayscales 0 to 63 are set as the first grayscale area GL, and grayscales 64 to 255 are set as the second grayscale area GH.
  • the 64 pulse widths Ta in the first grayscale area GL are not exactly the same, and can be set to multiple pulse widths of different durations. For example, among the 64 pulse widths Ta, a first pulse width Ta1 of 5ms duration can be set, and multiple pulse widths can be set to 5ms.
  • the number of pulse width types can also be set as needed, which is not limited in this application.
  • the pulse width setting of the first gray scale area GL and the second gray scale area GH is mainly adjusted based on the parasitic capacitance in the display panel 13 .
  • the amount of charge flowing through the pixel unit 15 can be controlled to ensure the grayscale displayed by the pixel unit 15.
  • the pixel unit 15 is not only controlled by the current, but also by the PWM signal, that is, the number of pulse widths T in the grayscale clock signal GCLK. Determined, and the effect of time on brightness is linear.
  • the constant k can be obtained by testing the parasitic capacitance in the display panel 13 , that is, by debugging the corresponding relationship between the brightness Lv and the charge Q when no color cast occurs, and the constant k can be obtained.
  • the color gamut map can also be used to determine whether a color cast occurs in the pixel unit 15, so as to set the pulse width T in the grayscale clock signal GCLK.
  • Figure 7 is a schematic diagram of the standard color gamut. Among them, the standard red color coordinates are (0.67,0.33), the standard green color coordinates are (0.21,0.71), the standard blue color coordinates are (0.14,0.08), and the standard white color coordinates are (0.33,0.33).
  • the real display color of the pixel unit 15 corresponds to the color coordinates in the standard color gamut diagram, and then by debugging the grayscale The duration of a pulse width Ta of the first gray scale area GL in the clock signal GCLK.
  • the pulse width T at this time is the optimal pulse width.
  • the pixel unit 15 is controlled to display standard red, that is, the color coordinates in the corresponding color gamut diagram are (0.67, 0.33). At this time, the color displayed by the pixel unit 15 corresponds to the color coordinates in the color gamut diagram (0.67, 0.25) and There are certain differences in the standard red color coordinates. Then adjust the pulse width Ta of the first grayscale area GL in the grayscale clock signal GCLK. If the pulse width T is 0.5ms, the pixel unit 15 displays standard red, that is, the color coordinates are (0.67, 0.33). At this time, the pulse width A width T of 0.5ms is the required pulse width, thus eliminating the color shift caused by parasitic capacitance.
  • FIG. 9 illustrates a method for outputting a driving signal according to a fifth embodiment of the present application. As shown in Figure 9, the specific steps are as follows:
  • Step S101 output the data clock signal to the grayscale clock generation unit and output the data signal for displaying the image to the output unit.
  • the data clock signal has a first pulse width duration, and the first pulse width duration in one frame of image display duration is The maximum time that a pixel unit of an image display receives a data signal.
  • Step S102 Output a grayscale clock signal according to the data clock signal.
  • the grayscale clock signal includes N consecutive grayscale pulses, and the N consecutive grayscale pulses include a plurality of first grayscale pulses with a first duration and A plurality of second grayscale pulses of second duration, the first duration being greater than the second duration.
  • the duration of the 1st to x grayscale pulses in the first grayscale area is adjusted according to the parasitic capacitance of the display panel 13, specifically: applying a voltage corresponding to standard white to any number of pixel units 15, or applying standard red or The voltage corresponding to standard green or standard blue controls the pixel unit 15 to display.
  • the pulse width of the first grayscale area GL is mainly adjusted. According to the color gamut diagram, when the color coordinate of the pixel unit 15 is the standard white color coordinate (0.33, 0.33), it indicates that the influence of the parasitic capacitance has been eliminated, and the pulse width T at this time is the optimal pulse width.
  • control the pixel unit to display standard white, determine the standard charge amount flowing through the pixel unit, and adjust the duration of the 1st to x grayscale pulses in the first grayscale area to control the charge amount flowing through the pixel unit to be the standard charge. amount to obtain the adjusted 1st to x grayscale pulses.
  • Step S103 When the gray-scale brightness corresponding to the data signal is less than or equal to the first threshold, count the first gray-scale pulses according to the magnitude of the gray-scale brightness corresponding to the data signal and obtain a count pulses, and obtain a count pulses according to the duration of a count pulses. Output the driving signal.
  • the gray-scale brightness corresponding to the data signal is greater than the first threshold, the second gray-scale pulses are counted according to the gray-scale brightness corresponding to the data signal and b count pulses are obtained, and the b count pulses are output according to the duration.
  • Driving signal the driving signal is used to drive the pixel unit to display the image, 1 ⁇ a ⁇ N, 1 ⁇ b ⁇ N.

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Abstract

一种数据驱动电路(11)、显示模组(10)及输出驱动信号的方法，数据处理单元(111)输出数据时钟信号(DCLK)和数据信号(Data)，灰度时钟生成单元(112)依据数据时钟信号(DCLK)输出包括第一灰度区(GL)和第二灰度区(GH)的灰度时钟信号(GCLK)，第一灰度区(GL)中灰度脉冲时长大于第二灰度区(GH)中灰度脉冲时长。通过控制灰度脉冲的持续时长改善显示面板(13)的色偏以提升显示效果。

Description

数据驱动电路、显示模组以及输出驱动信号的方法
本申请要求于2022年07月15日提交中国专利局，申请号CN202210832800.4，申请名称为“数据驱动电路、显示模组以及输出驱动信号的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及数据驱动电路、显示模组以及输出驱动信号的方法。
背景技术
Mini-LED是指尺寸在100um量级的LED芯片，与普通LED相比，单位面积密度更高、光源单元尺寸更小。Mini-LED显示屏与液晶显示屏(Liquid Crystal Display，LCD)相比，Mini-LED具备更优良的显示效果，响应速度有着数量级的提升，屏幕可以更轻薄，并且功耗更低。
目前，使用Mini-LED进行显示过程中，在显示低亮度时，由于寄生电容的存在，导致流过Mini-LED的电流占比小，从而显示时出现偏色现象。
发明内容
鉴于上述现有技术的不足，本申请提供一种有效改善显示色偏的数据驱动电路。
一种数据驱动电路，包括数据处理单元、灰度时钟生成单元和输出单元，数据处理单元输出数据时钟信号至灰度时钟生成单元和输出用于显示图像的数据信号至输出单元，数据时钟信号具有第一脉宽时长，在一帧图像显示时长中第一脉宽时长为执行图像显示的像素单元接收数据信号的最长时间，灰度时钟生成单元依据数据时钟信号输出一灰度时钟信号，灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，第一持续时长大于第二持续时长，输出单元用于接收数据信号，当数据信号对应的灰阶亮度小于或等于第一阈值时，依据数据信号对应的灰阶亮度的大小对第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当数据信号对应的灰阶亮度大于 第一阈值时，依据数据信号对应的灰阶亮度的大小对第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，驱动信号用于驱动像素单元显示图像，1＜a≤N，1＜b≤N。
可选地，灰度时钟信号包括第一灰度区和第二灰度区，第一灰度区包括第1～x灰度脉冲，第一灰度脉冲为第1～x灰度脉冲中任意一个灰度脉冲；第二灰度区包括第x+1～N灰度脉冲，第二灰度脉冲为第x+1～N灰度脉冲中任意一个灰度脉冲；第1～x灰度脉冲中任意一个灰度脉冲的持续时长大于第x+1～N灰度脉冲中任意一个灰度脉冲的持续时长，其中，第i灰度对应i个灰度脉冲，1≤i≤N；当数据信号对应的灰阶亮度小于或等于第一阈值时，依据数据信号对应的灰阶亮度的大小对第一灰度区中的灰度脉冲进行计数并获得a个计数脉冲，1≤a≤x，依据a个计数脉冲时长输出驱动信号；当数据信号对应的灰阶亮度大于第一阈值时，依据数据信号对应的灰阶亮度的大小对第二灰度区中的灰度脉冲进行计数并获得b个计数脉冲，x＜b≤N，依据b个计数脉冲时长输出驱动信号。
可选地，在第一灰度区中每一个灰度脉冲的持续时长相同，在第二灰度区中每一个灰度脉冲持续时间相同。
可选地，在第一灰度区中至少包括两个持续时长不同的灰度脉冲，第二灰度区中每一个灰度脉冲持续时长相同。
可选地，第一灰度区中的灰度脉冲数量小于或等于第二灰度区中的灰度脉冲数量。
可选地，灰度时钟生成模块用于对数据时钟信号进行分频和/或倍频处理，以控制数据时钟信号中的第一脉宽时长对应N个灰度脉冲。
本申请还公开一种前述数据驱动电路输出驱动信号的方法，输出数据时钟信号至灰度时钟生成单元和输出用于显示图像的数据信号至输出单元，数据时钟信号具有第一脉宽时长，在一帧图像显示时长中第一脉宽时长为执行图像显示的像素单元接收数据信号的最长时间；依据数据时钟信号输出一灰度时钟信号，灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，第一持续时长大于第二持续时长；当数据信号对应的灰阶亮度小于或等于第一阈值时，依据数据信号对应的灰阶亮度的大小对第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当数据信号对应的灰阶亮度大于第一阈值时，依据数据信号对应的灰阶亮度的大小对第二灰度脉冲进行计 数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，驱动信号用于驱动像素单元显示图像，1＜a≤N，1＜b≤N。
可选地，“依据数据时钟信号输出一灰度时钟信号”包括：对像素单元施加标准白色对应的电压，依据色域图确定像素单元当前显示颜色对应的色坐标，比对像素单元当前的色坐标与标准白色对应的色坐标，调整第一灰度区中第1～x灰度脉冲的持续时长以控制像素单元显示标准白色，当像素单元当前的色坐标为标准白色的色坐标时，获取调整后的第1～x灰度脉冲。
可选地，“对显示区域中的像素单元施加标准白色对应的电压”包括对显示区域中的像素单元施加标准红色或标准绿色或标准蓝色对应的电压。
可选地，“依据所述数据时钟信号输出一灰度时钟信号”包括：控制像素单元显示标准白色，并确定流过所述像素单元的标准电荷量，调整所述第一灰度区中第1～x灰度脉冲的持续时长以控制流过所述像素单元的电荷量为所述标准电荷量，获取调整后的第1～x灰度脉冲。
本申请还公开一种显示模组包括显示控制电路、扫描驱动电路、显示面板、发光控制器和前述的数据驱动电路，所述显示控制电路依据外部信号源接收原数据信号，并分别输出源极控制信号和栅极控制信号，所述数据驱动电路依据所述源极控制信号与所述扫描驱动电路依据所述栅极控制信号配合所述发光控制器控制所述显示面板进行图像显示。
可选地，所述显示面板设置有沿着第一方向延伸多条扫描线，沿着第二方向F2延伸的多条数据线，多条扫描线和多条数据线的交叉部均对应设置像素单元，所述像素单元为发光二极管，所述发光二极管阳极连接所述扫描线以接收扫描信号，阴极连接所述数据线以接收数据信号。
相较于现有技术，本申请公开的数据驱动电路，通过调整第一灰度区中的灰度脉冲的持续时长，使第一灰度脉冲的持续时长增加以消除显示低灰度时显示面板发生的偏色，有效的改善了由于显示面板显示低灰度时的偏色问题，提升了显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例提供的一种显示装置的结构示意图；
图2本申请第二实施例如图1所示显示模组的平面布局结构示意图；
图3为图2中像素单元的连接示意图；
图4为本申请第三实施例如图2所示数据驱动电路的电路方框示意图；
图5为图4中灰度时钟生成单元的倍频/分频原理示意图；
图6为图4中灰度时钟信号中灰度脉冲示意图；
图7为标准色域示意图；
图8为本申请第四实施例提供的灰度时钟信号中灰度脉冲示意图；
图9为本申请第五实施例提供的一种输出驱动信号的方法。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接(联接)。本申请中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本申请，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。需要说明的是，本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，本申请中使用的术语“包括”、“可以包括”、“包含”、或“可以包含”表示公开的相应功能、操作、元件等的存在，并不 限制其他的一个或多个更多功能、操作、元件等。此外，术语“包括”或“包含”表示存在说明书中公开的相应特征、数目、步骤、操作、元素、部件或其组合，而并不排除存在或添加一个或多个其他特征、数目、步骤、操作、元素、部件或其组合，意图在于覆盖不排他的包含。还需要理解的是，本文中描述的“至少一个”的含义是一个及其以上，例如一个、两个或三个等，而“多个”的含义是至少两个，例如两个或三个等，除非另有明确具体的限定。本申请的说明书和权利要求书及所述附图中的术语“步骤1”、“步骤2”等是用于区别不同对象，而不是用于描述特定顺序。
在显示技术领域中，显示装置通常可以包括显示面板和背光组件，其中，所述显示面板安装至所述背光组件的出光侧，所述背光组件用于给所述显示面板提供背光，以调节显示面板显示不同画面。
请参阅图1，图1为本申请第一实施例提供的一种显示装置100的结构示意图。显示装置100包括显示装置100，显示模组10与电源模组20固定于支撑框架30，电源模组20设置于显示模组10的背面用于为显示模组10提供电源电压。
请参阅图2，图2本申请第二实施例如图1所示显示模组10的平面布局结构示意图。
如图2所示，显示模组10还包括数据驱动电路11、扫描驱动电路12和显示面板13、显示控制电路14和发光控制器16。数据驱动电路11、扫描驱动电路12和显示控制电路14和发光控制器16设置于显示面板13的非显示区域。
在显示面板13的显示区域13a设置有互相呈网格状设置沿着第一方向F1延伸多条扫描线(Gate line)G1～Gn和沿着第二方向F2延伸的多条数据线(Source line)S1～Sm。其中，第一方向F1与第二方向F2相互垂直，并且多条扫描线G1～Gn之间、多条数据线S1～Sm之间以及扫描线G1～Gn与数据线S1～Sm之间相互绝缘。
多条扫描线G1～Gn和数据线S1～Sm的交叉部均对应设置像素单元15。本实施例中，像素单元15可分别表示为P11～P1m，P21～P2m，……，Pn1～Pnm。
扫描线G1～Gn连接扫描驱动电路12，自扫描驱动电路12接收扫描信号，数据线S1～Sm连接数据驱动电路11，用于接收数据驱动电路11提供的以灰阶值形式保存并传输的数据信号Data。
显示控制电路14从的外部信号源接收表示图像信息的原图像信号、取得同 步用的时钟信号CLK、水平同步信号Hsyn及垂直同步信号Vsyn，并输出供控制扫描驱动电路12使用的栅极控制信号Cg、供控制数据驱动电路11使用的源极控制信号Cs及表示图像信息的数据信号Data。本实施例中，显示控制电路14对原数据信号进行数据调整处理后获得数据信号Data，并且将数据信号Data传输至数据驱动电路11。
扫描驱动电路12接收显示控制电路14输出的栅极控制信号Cg，向各扫描线G1～Gn输出扫描信号。数据驱动电路11接收显示控制电路14输出的源极控制信号Cs、时钟信号CLK和数据信号Data，并向各数据线S1～Sm输出在显示面板13中各个像素单元15中驱动元件执行图像显示用的驱动信号。发光控制器16用于向多个像素施加发光信号以控制像素单元15发光，以控制像素单元15显示对应图像。
请参阅图3，图3为图2中像素单元15的连接示意图。如图3所示，像素单元15包括一个发光二极管，发光二极管的阳极连接扫描线G1～Gn，阴极连接数据线S1～Sm，每一条扫描线设置有一个P型MOS管，当P型MOS管栅极为低压电位时，P型MOS管的源极与漏极导通，使连接于扫描线的发光二极管接收对应的扫描信号，使得阳极电压上升。数据驱动电路11可通过脉宽调制(Pulse WidT Modulation，PWM)控制发光二极管的发光亮度，发光二极管的脉冲宽度越宽，亮度越高。
请参阅图4，图4本申请第三实施例如图2所示数据驱动电路的电路方框示意图。如图4所示，数据驱动电路包括数据处理单元111、灰度时钟生成单元112和输出单元113。其中，数据处理单元111用于接收并存储数据时钟信号DCLK和数据信号Data，经过处理后分别将数据时钟信号DCLK传输至灰度时钟生成单元112，将数据信号Data传输至输出单元113。数据时钟信号DCLK用于控制数据信号Data的输出时序，数据时钟信号具有第一脉宽时长H，在一帧图像显示时长中，第一脉宽时长H为执行图像显示的像素单元接收数据信号Data的最长时间。
灰度时钟生成单元112用于接收数据时钟信号DCLK，并对数据时钟信号进行倍频/分频处理，以生成灰度时钟信号GCLK，灰度时钟信号GCLK用于控制灰度等级。灰度时钟信号GCLK包括N个连续的灰度脉冲，其中，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长 的第二灰度脉冲，第一持续时长大于第二持续时长，第i灰度对应i个灰度脉冲，1≤i≤N，N可以根据具体需要而定，可以为128、256等，本申请不做限制。
输出单元113用于接收数据信号Data和灰度时钟信号GCLK，并依据对灰度时钟信号GCLK中的灰度脉冲进行计数，并依据数据结果生成数据信号Data所对应的PWM信号的输出波形，也即是数据信号Data对应的灰度脉冲持续时长，用于控制像素单元15进行图像显示。
具体地，当数据信号Data对应的灰阶亮度小于或等于第一阈值时，依据数据信号对应的灰阶亮度的大小对第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当数据信号对应的灰阶亮度大于第一阈值时，依据数据信号对应的灰阶亮度的大小对第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，驱动信号用于驱动像素单元显示图像，1＜a≤N，1＜b≤N。
请参阅图5，图5为图4中灰度时钟生成单元的倍频/分频原理示意图。如图5所示，数据时钟信号DCLK中第一脉宽H为扫描一行像素单元的时间，并由灰度时钟生成单元112转化成灰度时钟信号GCLK，灰度时钟信号GCLK将第一脉宽H的数据时钟信号DCLK转化为N个灰度脉冲，其中，第i灰度对应i个所述灰度脉冲，1≤i≤N。一个脉宽T包括一个脉冲，也即是一个脉宽T表征灰度1，两个脉宽T表征灰度2，三个脉宽T则表征灰度3，以此类推，通过控制脉宽T的长度从而控制像素单元15显示的灰度。灰度高低是由相同脉宽T的数量决定，与脉宽T的起始时间无关，例如，灰度3可以从第一个脉宽T起至第三个脉宽T结束，也可以从第四个脉宽T起至第七个脉宽T结束，也就是说，像素单元15显示预设灰度可以在第一脉宽H时长的数据时钟信号DCLK内，选取任意时间点起的灰度时钟GCLK打开预设的数量的脉宽T。
请参阅图6，图6为图4中灰度时钟信号中灰度脉冲示意图。如图6所示，灰度时钟信号GCLK包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，所述第一持续时长大于所述第二持续时长。具体地，灰度时钟信号GCLK包括第一灰度区GL和第二灰度区GH，第一灰度区GL包括第1～x灰度脉冲即多个第一灰度脉冲，第二灰度区GH包括第x+1～N灰度脉冲即多个第二灰度脉冲，第1～x灰度脉冲中任意一个所述灰度脉冲的持续时长大于所述第x+1～N灰度脉冲 中任意一个所述灰度脉冲的持续时长，其中，第i灰度对应i个所述灰度脉冲，1≤i≤N。第一灰度区GL中的灰度脉冲数量小于或等于第二灰度区GH中的灰度脉冲数量。
当数据信号Data对应的灰阶亮度小于或等于第一阈值时，依据数据信号Data对应的灰阶亮度的大小对第一灰度区GL中的灰度脉冲进行计数并获得a个计数脉冲，1≤a≤x，依据a个计数脉冲时长输出驱动信号。
当数据信号Data对应的灰阶亮度大于第一阈值时，依据数据信号Data对应的灰阶亮度的大小对第二灰度区GH中的灰度脉冲进行计数并获得b个计数脉冲，x＜b≤N，依据b个计数脉冲时长输出驱动信号。
其中，当第一灰度区GL包括32灰度时，第一阈值为32，当第一灰度区GL包括64灰度时，第一阈值为64，也即是第一阈值为第一灰度区GL与第二灰度区GH的分界值。
原始灰度时钟信号GCLK_0为未调整的灰度时钟信号，其中，第一灰度区GL中灰度脉冲的持续时长相同，第二灰度区GH中灰度脉冲的持续时长相同，且第一灰度区GL与第二灰度区GH中的灰度脉冲的持续时长相同。
以8bit为例，在数据时钟信号DCLK中，数据时钟信号DCLK中第一脉宽H对应灰度时钟信号GCLK中256个灰度脉冲，256个灰度脉冲对应256灰度，一个脉宽T包括一个灰度脉冲。第一阈值为64，即设置0灰度～63灰度为第一灰度区GL，64灰度～255灰度为第二灰度区GH。第一灰度区GL中的64个灰度脉冲相同即脉宽Ta相同，第二灰度区GH的192个灰度脉冲相同即脉宽Tb相同，第一灰度区GL中的一个脉宽Ta的时长大于第二灰度区GH中一个脉宽Tb的时长也即是第一灰度区GL中一个灰度脉冲的持续时长大于第二灰度区GH中一个灰度脉冲的持续时长。例如，第一灰度区GL中一个脉宽Ta可以设置为0.5ms，第二灰度区GH中一个脉宽Tb可以设置为0.3ms，当然也可以为其他值，本申请不做限制。
其中，第一灰度区GL和第二灰度区GH的脉宽设置主要依据显示面板13中寄生电容进行调整的，由于寄生电容的存在，导致实际流过像素单元15也即是发光二极管的电流变小，从而导致像素单元15显示的灰度未达到预设灰度，出现偏色现象，因为像素单元15进行低灰度显示时，流过像素单元15的电流较小，故偏色现象主要出现在像素单元15进行低灰度显示时。因此，通过将第 一灰度区GL中每一个脉宽Ta的时长设置更长，从而抵消寄生电容造成的偏色现象。
具体地，可以通过控制流过像素单元15的电荷量从而保证像素单元15显示的灰度，像素单元15不仅受电流控制，还受PWM信号也即是灰度时钟信号GCLK中的脉宽T数量决定，且时间对亮度的影响为线性。而电荷量Q＝It，即流过像素单元15的电荷量等于电流乘以时间，因此电荷量与时间的关系也是线性的。像素单元15显示的亮度可以设置为Lv＝kQ，其中，k为一个常数，Q表示流过像素单元15的电荷总量。常数k可以通过对显示面板13中寄生电容的测试得出，即通过调试得到不发生偏色现象时，亮度Lv与电荷量Q之间的对应关系，得到常数k。
在一种实施例中，还可以通过色域图来判断像素单元15是否发生偏色，从而对灰度时钟信号GCLK中的脉宽T进行设置。如图7所示，图7为标准色域示意图。其中，标准红色色坐标为(0.67,0.33)，标准绿色色坐标为(0.21,0.71)，标准蓝色色坐标为(0.14,0.08)，标准白色色坐标为(0.33,0.33)。通过控制像素单元15也即是发光二极管显示对应的标准颜色，将像素单元15真实的显示颜色对应标准色域示意图中的色坐标，然后通过调试灰度时钟信号GCLK中第一灰度区GL的一个脉宽Ta的时长，当像素单元15经调试后显示的颜色为标准颜色时，此时的脉宽为最佳脉宽。
例如，控制像素单元15显示标准红色，即对应色域图中的色坐标为(0.67,0.33)，而此时像素单元15显示的颜色对应色域图中的色坐标为(0.67,0.25)与标准红色色坐标具有一定的差异。然后调试灰度时钟信号GCLK中第一灰度区GL的脉宽Ta，若当脉宽Ta为0.5ms时，像素单元15显示为标准红色即色坐标为(0.67,0.33)，此时的脉宽0.5ms就为所需脉宽，从而消除了寄生电容导致的色偏现象。当然还可以对第二灰度区GH中的脉宽进行上述调制，消除第二灰度区GH中的偏色现象。
请参阅图8，图8为本申请第四实施例提供的灰度时钟信号脉冲示意图。如图8所示，灰度时钟信号GCLK包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，所述第一持续时长大于所述第二持续时长。其中，灰度时钟信号GCLK包括第一灰度区GL和第二灰度区GH，第一灰度区GL包括第1～x灰度脉冲即 多个第一灰度脉冲，第二灰度区GH包括第x+1～N灰度脉冲即多个第二灰度脉冲，第1～x灰度脉冲中任意一个所述灰度脉冲的持续时长大于所述第x+1～N灰度脉冲中任意一个所述灰度脉冲的持续时长，其中，第i灰度对应i个所述灰度脉冲，1≤i≤N。
在第一灰度区GL中至少包括两个持续时长不同的第一灰度脉冲，第二灰度区GH中每一个灰度脉冲持续时长相同。第一灰度区GL中的灰度脉冲数量小于或等于第二灰度区GH中的灰度脉冲数量。
原始灰度时钟信号GCLK_0为未调整的灰度时钟信号，其中，第一灰度区GL中灰度脉冲的持续时长相同，第二灰度区GH中灰度脉冲的持续时长相同，且第一灰度区GL与第二灰度区GH中的灰度脉冲的持续时长相同。
以8bit为例，在数据时钟信号DCLK中，数据时钟信号DCLK中第一脉宽H对应灰度时钟信号GCLK中256个灰度脉冲，256个灰度脉冲对应256灰度，一个脉宽T包括一个灰度脉冲。第一阈值为64，即设置0灰度～63灰度为第一灰度区GL，64灰度～255灰度为第二灰度区GH。第一灰度区GL中的64个脉宽Ta不完全相同，可以设置为多个不同时长的脉宽，例如，在64个脉宽Ta中可以设置时长为5ms的第一脉宽Ta1，多个时长为6ms的第二脉宽Ta2和多个时长为7ms的第三脉宽Ta3。
在示例性实施例中，脉宽种类还可以根据需要设置其他数量，本申请不做限制。
其中，第一灰度区GL和第二灰度区GH的脉宽设置主要依据显示面板13中寄生电容进行调整。
具体地，可以通过控制流过像素单元15的电荷量从而保证像素单元15显示的灰度，像素单元15不仅受电流控制，还受PWM信号也即是灰度时钟信号GCLK中的脉宽T数量决定，且时间对亮度的影响为线性。而电荷量Q＝It，即流过像素单元15的电荷量等于电流乘以时间，因此电荷量与时间的关系也是线性的。像素单元15显示的亮度可以设置为Lv＝kQ，其中，k为一个常数，Q表示流过像素单元15的电荷总量。常数k可以通过对显示面板13中寄生电容的测试得出，即通过调试得到不发生偏色现象时，亮度Lv与电荷量Q之间的对应关系，得到常数k。
在一种实施例中，还可以通过色域图来判断像素单元15是否发生偏色，从 而对灰度时钟信号GCLK中的脉宽T进行设置。如图7所示，图7为标准色域示意图。其中，标准红色色坐标为(0.67,0.33)，标准绿色色坐标为(0.21,0.71)，标准蓝色色坐标为(0.14,0.08)，标准白色色坐标为(0.33,0.33)。通过对像素单元15也即是发光二极管施加标准颜色即标准红色、标准绿色或标准蓝色对应的电压，将像素单元15真实的显示颜色对应标准色域示意图中的色坐标，然后通过调试灰度时钟信号GCLK中第一灰度区GL的一个脉宽Ta的时长，当像素单元15经调试后显示的颜色为标准颜色时，此时的脉宽T为最佳脉宽。
例如，控制像素单元15显示标准红色，即对应色域图中的色坐标为(0.67,0.33)，而此时像素单元15显示的颜色对应色域图中的色坐标为(0.67,0.25)与标准红色色坐标具有一定的差异。然后调试灰度时钟信号GCLK中第一灰度区GL的脉宽Ta，若当脉宽T为0.5ms时，像素单元15显示为标准红色即色坐标为(0.67,0.33)，此时的脉宽T为0.5ms就为所需脉宽，从而消除了寄生电容导致的色偏现象。
请参阅图9，图9为本申请第五实施例提供的一种输出驱动信号的方法。如图9所示，具体步骤如下：
步骤S101，输出数据时钟信号至灰度时钟生成单元和输出用于显示图像的数据信号至输出单元，数据时钟信号具有第一脉宽时长，在一帧图像显示时长中第一脉宽时长为执行图像显示的像素单元接收数据信号的最长时间。
步骤S102，依据数据时钟信号输出一灰度时钟信号，灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，第一持续时长大于第二持续时长。
依据显示面板13的寄生电容对第一灰度区中第1～x灰度脉冲的持续时长进行调整，具体为：给任意数量的像素单元15施加标准白色对应的电压，也可以施加标准红色或标准绿色或标准蓝色对应的电压，控制像素单元15进行显示。
依据色域图确定像素单元当前显示颜色对应的色坐标。像素单元15被施加电压后，由于寄生电容的存在，导致显示的颜色与标准白色存在一定的差异，此时通过色域图确定当前显示的颜色对应的色坐标。
比对像素单元当前的色坐标与标准白色色坐标。依据色域图确定当前显示颜色的色坐标与标准白色色坐标之间是否存在差异，若存在差异则表明存在寄 生电容，若不存在差异则表示没有寄生电容影响。
调整第一灰度区GL中第1～x灰度脉冲的持续时长以控制像素单元显示标准白色。由于寄生电容对于像素单元显示低灰度影响较大，故主要针对第一灰度区GL的脉宽进行调整。依据色域图，当像素单元15的色坐标为标准白色色坐标(0.33,0.33)时，表明已消除了寄生电容的影响，此时的脉宽T则为最佳脉宽。
还可以为控制像素单元显示标准白色，并确定流过像素单元的标准电荷量，调整第一灰度区中第1～x灰度脉冲的持续时长以控制流过像素单元的电荷量为标准电荷量，获取调整后的第1～x灰度脉冲。
步骤S103，当数据信号对应的灰阶亮度小于或等于第一阈值时，依据数据信号对应的灰阶亮度的大小对第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当数据信号对应的灰阶亮度大于第一阈值时，依据数据信号对应的灰阶亮度的大小对第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，驱动信号用于驱动像素单元显示图像，1＜a≤N，1＜b≤N。
应当理解的是，本申请的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本申请所附权利要求的保护范围。

Claims (17)

  1. 一种数据驱动电路，其中，包括数据处理单元、灰度时钟生成单元和输出单元，
    所述数据处理单元输出数据时钟信号至所述灰度时钟生成单元，同时输出用于图像显示的数据信号至所述输出单元，所述数据时钟信号具有第一脉宽时长，在一帧图像显示时长中所述第一脉宽时长为执行图像显示的像素单元接收所述数据信号的最长时间；
    所述灰度时钟生成单元依据所述数据时钟信号输出一灰度时钟信号，所述灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，所述第一持续时长大于所述第二持续时长；
    所述输出单元用于接收所述数据信号，当所述数据信号对应的灰阶亮度小于或等于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当所述数据信号对应的灰阶亮度大于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，所述驱动信号用于驱动所述像素单元显示图像，1＜a≤N，1＜b≤N。
  2. 如权利要求1所述的数据驱动电路，其中，
    所述灰度时钟信号包括第一灰度区和第二灰度区，所述第一灰度区包括第1～x灰度脉冲，所述第一灰度脉冲为所述第1～x灰度脉冲中任意一个灰度脉冲；
    所述第二灰度区包括第x+1～N灰度脉冲，所述第二灰度脉冲为所述第x+1～N灰度脉冲中任意一个灰度脉冲；
    第1～x灰度脉冲中任意一个所述灰度脉冲的持续时长大于所述第x+1～N灰度脉冲中任意一个所述灰度脉冲的持续时长，其中，第i灰度对应i个所述灰度脉冲，1≤i≤N；
    当所述数据信号对应的灰阶亮度小于或等于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第一灰度区中的所述灰度脉冲进行计数并获得a个计数脉冲，1≤a≤x，依据a个计数脉冲时长输出驱动信号；
    当所述数据信号对应的灰阶亮度大于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第二灰度区中的所述灰度脉冲进行计数并获得b个计 数脉冲，x＜b≤N，依据b个计数脉冲时长输出驱动信号。
  3. 如权利要求1所述的数据驱动电路，其中，在所述第一灰度区中每一个所述灰度脉冲的持续时长相同，在所述第二灰度区中每一个灰度脉冲持续时间相同。
  4. 如权利要求2所述的数据驱动电路，其中，在所述第一灰度区中每一个所述灰度脉冲的持续时长相同，在所述第二灰度区中每一个灰度脉冲持续时间相同。
  5. 如权利要求1所述的数据驱动电路，其中，在所述第一灰度区中至少包括两个持续时长不同的灰度脉冲，所述第二灰度区中每一个灰度脉冲持续时长相同。
  6. 如权利要求2所述的数据驱动电路，其中，在所述第一灰度区中至少包括两个持续时长不同的灰度脉冲，所述第二灰度区中每一个灰度脉冲持续时长相同。
  7. 如权利要求1所述的数据驱动电路，其中，所述第一灰度区中的灰度脉冲数量小于或等于所述第二灰度区中的灰度脉冲数量。
  8. 如权利要求2所述的数据驱动电路，其中，所述第一灰度区中的灰度脉冲数量小于或等于所述第二灰度区中的灰度脉冲数量。
  9. 一种输出驱动信号的方法，其中，应用于数据驱动电路，所述数据驱动电路包括数据处理单元、灰度时钟生成单元和输出单元，所述数据处理单元输出数据时钟信号至所述灰度时钟生成单元，同时输出用于图像显示的数据信号至所述输出单元，所述数据时钟信号具有第一脉宽时长，在一帧图像显示时长中所述第一脉宽时长为执行图像显示的像素单元接收所述数据信号的最长时间；所述灰度时钟生成单元依据所述数据时钟信号输出一灰度时钟信号，所述灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，所述第一持续时长大于所述第二持续时长；所述输出单元用于接收所述数据信号，当所述数据信号对应的灰阶亮度小于或等于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当所述数据信号对应的灰阶亮度大于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，所述驱动信号用于驱动所述像素单元显示图像，1＜a≤N，1＜b≤N；
    所述输出驱动信号的方法包括：输出数据时钟信号至所述灰度时钟生成单元和输出用于显示图像的数据信号至所述输出单元，所述数据时钟信号具有第一脉宽时长，在一帧图像显示时长中所述第一脉宽时长为执行图像显示的像素单元接收所述数据信号的最长时间；
    依据所述数据时钟信号输出一灰度时钟信号，所述灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，所述第一持续时长大于所述第二持续时长；
    当所述数据信号对应的灰阶亮度小于或等于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当所述数据信号对应的灰阶亮度大于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，所述驱动信号用于驱动所述像素单元显示图像，1＜a≤N，1＜b≤N。
  10. 如权利要求9所述的方法，其中，“依据所述数据时钟信号输出一灰度时钟信号”包括：
    对像素单元施加标准白色对应的电压，依据色域图确定所述像素单元当前显示颜色对应的色坐标，比对所述像素单元当前的色坐标与所述标准白色对应的色坐标，调整所述第一灰度区中第1～x灰度脉冲的持续时长以控制所述像素单元显示所述标准白色，当所述像素单元当前的色坐标为所述标准白色的色坐标时，获取调整后的第1～x灰度脉冲。
  11. 如权利要求9所述的方法，其中，“依据所述数据时钟信号输出一灰度时钟信号”包括：
    控制像素单元显示标准白色，并确定流过所述像素单元的标准电荷量，调整所述第一灰度区中第1～x灰度脉冲的持续时长以控制流过所述像素单元的电荷量为所述标准电荷量，获取调整后的第1～x灰度脉冲。
  12. 一种显示模组，其中，包括显示控制电路、扫描驱动电路、显示面板、发光控制器和数据驱动电路，所述显示控制电路依据外部信号源接收原数据信号，并分别输出源极控制信号和栅极控制信号，所述数据驱动电路依据所述源极控制信号与所述扫描驱动电路依据所述栅极控制信号配合所述发光控制器控制所述显示面板进行图像显示；
    所述数据驱动电路包括数据处理单元、灰度时钟生成单元和输出单元；所述数据处理单元输出数据时钟信号至所述灰度时钟生成单元，同时输出用于图像显示的数据信号至所述输出单元，所述数据时钟信号具有第一脉宽时长，在一帧图像显示时长中所述第一脉宽时长为执行图像显示的像素单元接收所述数据信号的最长时间；所述灰度时钟生成单元依据所述数据时钟信号输出一灰度时钟信号，所述灰度时钟信号包括N个连续的灰度脉冲，N个连续的灰度脉冲中包括多个具有第一持续时长的第一灰度脉冲和多个第二持续时长的第二灰度脉冲，所述第一持续时长大于所述第二持续时长；所述输出单元用于接收所述数据信号，当所述数据信号对应的灰阶亮度小于或等于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第一灰度脉冲进行计数并获得a个计数脉冲，依据a个计数脉冲时长输出驱动信号，当所述数据信号对应的灰阶亮度大于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第二灰度脉冲进行计数并获得b个计数脉冲，依据b个计数脉冲时长输出驱动信号，所述驱动信号用于驱动所述像素单元显示图像，1＜a≤N，1＜b≤N。
  13. 如权利要求12所述的显示模组，其中，所述灰度时钟信号包括第一灰度区和第二灰度区，所述第一灰度区包括第1～x灰度脉冲，所述第一灰度脉冲为所述第1～x灰度脉冲中任意一个灰度脉冲；
    所述第二灰度区包括第x+1～N灰度脉冲，所述第二灰度脉冲为所述第x+1～N灰度脉冲中任意一个灰度脉冲；
    第1～x灰度脉冲中任意一个所述灰度脉冲的持续时长大于所述第x+1～N灰度脉冲中任意一个所述灰度脉冲的持续时长，其中，第i灰度对应i个所述灰度脉冲，1≤i≤N；
    当所述数据信号对应的灰阶亮度小于或等于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第一灰度区中的所述灰度脉冲进行计数并获得a个计数脉冲，1≤a≤x，依据a个计数脉冲时长输出驱动信号；
    当所述数据信号对应的灰阶亮度大于第一阈值时，依据所述数据信号对应的灰阶亮度的大小对所述第二灰度区中的所述灰度脉冲进行计数并获得b个计数脉冲，x＜b≤N，依据b个计数脉冲时长输出驱动信号。
  14. 如权利要求13所述的显示模组，其中，在所述第一灰度区中每一个所述灰度脉冲的持续时长相同，在所述第二灰度区中每一个灰度脉冲持续时间相同。
  15. 如权利要求13所述的显示模组，其中，在所述第一灰度区中至少包括两 个持续时长不同的灰度脉冲，所述第二灰度区中每一个灰度脉冲持续时长相同。
  16. 如权利要求13所述的显示模组，其中，所述第一灰度区中的灰度脉冲数量小于或等于所述第二灰度区中的灰度脉冲数量。
  17. 如权利要求9所述的显示模组，其中，所述显示面板设置有沿着第一方向延伸多条扫描线，沿着第二方向F2延伸的多条数据线，多条扫描线和多条数据线的交叉部均对应设置像素单元，所述像素单元为发光二极管，所述发光二极管的阳极连接所述扫描线以接收扫描信号、阴极连接所述数据线以接收数据信号。
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