WO2024007835A1 - 复位开关电源通断控制电路及系统 - Google Patents
复位开关电源通断控制电路及系统 Download PDFInfo
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- WO2024007835A1 WO2024007835A1 PCT/CN2023/100324 CN2023100324W WO2024007835A1 WO 2024007835 A1 WO2024007835 A1 WO 2024007835A1 CN 2023100324 W CN2023100324 W CN 2023100324W WO 2024007835 A1 WO2024007835 A1 WO 2024007835A1
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- resistor
- electrically connected
- control circuit
- signal
- reset switch
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- 239000003990 capacitor Substances 0.000 claims description 62
- WTJKGGKOPKCXLL-RRHRGVEJSA-N phosphatidylcholine Chemical compound CCCCCCCCCCCCCCCC(=O)OC[C@H](COP([O-])(=O)OCC[N+](C)(C)C)OC(=O)CCCCCCCC=CCCCCCCCC WTJKGGKOPKCXLL-RRHRGVEJSA-N 0.000 claims description 4
- 238000000034 method Methods 0.000 description 14
- 238000001514 detection method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
- H03K17/785—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling field-effect transistor switches
Definitions
- the present application relates to the technical field of reset switches, and specifically to a reset switch power supply on-off control circuit and system.
- Reset switching power supply is widely used in almost all electronic equipment such as various terminal equipment and communication equipment led by electronic computers due to its small size, light weight and high efficiency. It is an indispensable power supply for the rapid development of today's electronic information industry. Way. Battery products are particularly sensitive to the self-consumption of power of the machine, especially when the system is not turned on but requires continuous power supply.
- the reset switching power supply is designed according to the existing traditional methods. The circuit is complex, the workload is large, the cost is high, and the efficiency is low. Moreover, because there are many variables in the design of the reset switching power supply, it is difficult to accurately determine the system status, making the main control and various detection systems It cannot cooperate well and cannot accurately turn off the reset switch power supply.
- this application provides a reset switch power supply on-off control circuit and system, which solves the problem of the reset switch locking the power on with low cost and low power consumption, and notifies the main control according to the current, voltage and other detection circuits. Make a judgment on the system status and turn off the switch circuit through the main control.
- a reset switching power supply on-off control circuit using For reset switches, include:
- a reset switch control circuit connected to the reset switch, is used to collect the status of the reset switch and output a status signal and a first control signal;
- a MOS switch circuit is connected to the reset switch control circuit and receives the first control signal from the reset switch control circuit;
- a main control chip is connected to the reset switch control circuit and is used to obtain the status signal of the reset switch control circuit and output a second control signal to the reset switch control circuit.
- the reset switching power supply on-off control circuit further includes a power module for supplying power to the main control chip, the reset switch control circuit and the MOS switch circuit.
- the reset switch control circuit includes a signal input unit, a first signal unit and a second signal unit, wherein:
- the signal input unit is configured to output a first output signal and the status signal according to the state of the reset switch;
- the first signal unit is connected to the signal input unit, used to receive the first output signal and output a second output signal;
- the second signal unit is connected to the first signal unit and is used to receive the second output signal and output the first control signal.
- the reset switch control circuit further includes a buffer unit connected to the signal input unit for preventing accidental key presses.
- the signal input unit includes a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first diode, wherein:
- One end of the first resistor is electrically connected to the power module, the other end is electrically connected to one end of the first capacitor and the cathode of the first diode, and the other end of the first capacitor is grounded;
- One end of the second resistor is electrically connected to the cathode of the first diode, and the other end is grounded;
- the anode of the first diode is electrically connected to one end of the third resistor, the other end of the third resistor is electrically connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
- the cathode of the first diode receives the status signal and outputs the first output signal
- the other end of the third resistor is electrically connected to the output signal IO_POKEY.
- the buffer unit includes a first chip, a third capacitor, a fourth capacitor and a fifth capacitor, wherein:
- the third capacitor, the fourth capacitor, and the fifth capacitor are connected in parallel;
- One end of the third capacitor is electrically connected to the power module, and the other end is grounded;
- the input terminal of the first chip receives the first output signal, the power terminal is electrically connected to the power module, the ground terminal is grounded, and the output terminal is electrically connected to the first signal unit.
- the first signal unit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a sixth capacitor, a first transistor and a first MOS transistor, wherein:
- One end of the sixth resistor receives the first output signal, and the other end is electrically connected to the base of the first transistor;
- One end of the sixth capacitor is electrically connected to the base of the first transistor, and the other end is grounded;
- One end of the fourth resistor is electrically connected to the power module, and the other end is electrically connected to the collector of the first transistor;
- One end of the fifth resistor is electrically connected to the collector of the first transistor, and the other end is electrically connected to the drain of the first MOS transistor;
- the emitter of the first transistor is grounded
- the seventh resistor is connected in parallel with the gate and source of the first MOS transistor
- One end of the eighth resistor is electrically connected to the gate of the first MOS transistor, and the other end is electrically connected to the output signal IO_POPC;
- the source of the first MOS tube is grounded
- the drain of the first MOS transistor is electrically connected to the second signal unit and outputs the second output signal.
- the second signal unit includes a ninth resistor, a tenth resistor, a seventh capacitor, an eighth capacitor, a second transistor and a second MOS transistor, wherein:
- the base of the second transistor is electrically connected to the first signal unit for receiving the second output signal
- the seventh capacitor is connected in parallel with the base and emitter of the second transistor
- One end of the ninth resistor is electrically connected to the base of the second transistor, and the other end is electrically connected to the drain of the second MOS transistor;
- One end of the eighth capacitor is electrically connected to the drain of the second MOS transistor, and the other end is grounded;
- the tenth resistor is connected in parallel with the gate and source of the second MOS transistor
- the emitter of the second triode is grounded, and the collector is electrically connected to the gate of the second MOS tube;
- the drain of the second MOS transistor outputs the first control signal, and the source is electrically connected to the power module.
- the first output signal When the reset switch is not pressed, the first output signal outputs a high level, the second output signal outputs a low level, and the first control signal outputs a low level;
- the first output signal When the reset switch is pressed and then released, the first output signal outputs a high level, the second output signal outputs a low level, and the first control signal maintains a high level. .
- the main control chip When the pressing time of the reset switch exceeds the shutdown time threshold, the main control chip outputs the second control signal to the reset switch control circuit, and the first control signal outputs a low level.
- the MOS switch circuit includes a photocoupler, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor,
- the ninth capacitor, the third MOS tube, the fourth MOS tube, the fifth MOS tube, and the sixth MOS tube among which:
- One end of the thirteenth resistor receives the first control signal, and the other end is electrically connected to the first terminal of the optocoupler;
- the second terminal and the third terminal of the optocoupler are grounded;
- One end of the fourteenth resistor is electrically connected to the gate of the third MOS transistor, and the other end is electrically connected to the fourth terminal of the photocoupler;
- the fifteenth resistor is connected in parallel with the gate and source of the third MOS transistor
- the source of the third MOS tube is electrically connected to the power module
- One end of the twelfth resistor is electrically connected to the drain of the third MOS transistor, and the other end is electrically connected to the gate of the fourth MOS transistor;
- One end of the ninth capacitor is electrically connected to the gate of the fourth MOS transistor, and the other end is grounded;
- the gates of the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are electrically connected, their sources are electrically connected, and their drains are grounded;
- the eleventh resistor is connected in parallel with the gate and source of the fourth MOS transistor
- One end of the sixteenth resistor is electrically connected to the source of the fourth MOS transistor, and the other end is grounded;
- the seventeenth resistor is connected in parallel with the sixteenth resistor.
- the third MOS tube When the first control signal is low level, the third MOS tube is turned off, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are turned off, and the reset The switching power supply on-off control circuit is open.
- a reset switching power supply on-off control system which is characterized in that it includes the reset switching power supply on-off control circuit as described in any one of the first aspects.
- This application provides a reset switching power supply on-off control circuit and system, which has one or more of the following advantages:
- the reset switching power supply on-off control system is composed of basic components such as MOS tubes and transistors.
- the cost is low, the power consumption of the basic components is low, and the static power consumption can be adjusted by adjusting the circuit impedance. Therefore, it can be low-cost and low-cost. Power consumption solves the problem of the reset switch locking the power on.
- the reset switching power supply on-off control system sets the main control to read the button status according to detection circuits such as current and voltage, sets an interface to shut down the system power supply, and determines the equipment status through the main control and various detection systems. Turn off the system reset switch.
- Figure 1 shows a schematic diagram of a reset switching power supply on-off control system according to an exemplary embodiment
- Figure 2 shows a schematic diagram of a power module circuit of an exemplary embodiment
- Figure 3 shows a schematic diagram of a reset switch control circuit of an exemplary embodiment
- FIG. 4 shows a schematic diagram of a MOS switch circuit according to an exemplary embodiment.
- Example embodiments will now be described more fully with reference to the accompanying drawings.
- Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art.
- the same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted.
- Figure 1 shows a schematic diagram of a reset switching power supply on-off control system according to an exemplary embodiment.
- the reset switching power supply on-off control system includes DC-DC power supply modules 1 and 2, which are connected to the main power supply respectively and are used to convert the voltage from 12V to 3.3V.
- DC-DC power supply module 1 and reset The switch control circuit is connected to provide conversion power, and the reset switch is connected to the reset switch control circuit to control the reset switch control circuit to start up; the DC-DC power module 1 is connected to the MOS switch circuit to provide conversion power; the DC-DC power module 2.
- Shut down the main control chip is connected to the reset switch control circuit, the reset switch control circuit feeds back the button status, and the main control chip controls the reset switch control circuit to shut down through the button and device status.
- the reset switching power supply on-off control system includes a switch circuit power supply return path. This circuit is in a continuous path state when the power supply is powered. As shown in Figure 1, the power supply return path is represented by a dotted line.
- the reset switching power supply on-off control system also includes a system power supply return flow path.
- the GND return flow of this path will pass through the MOS switch circuit for switching control. It is a path only when the MOS tube is turned on, as shown in Figure 1. This supply return path is shown as a solid line.
- FIG. 2 shows a schematic diagram of a power module circuit of an exemplary embodiment.
- the 12.6V power supply is converted into a 3.3V working power supply.
- the power input end of chip U21 is connected to resistor R114, capacitor C47, and capacitor C48; the other end of resistor R114 is connected to the 12.6V main power supply; the other end of capacitor C47 and capacitor C48 is connected to ground; the voltage output end of chip U21 is connected to the capacitor C49, C50, output 3.3V working power supply; the other end of capacitor C49, C50 is connected to ground.
- FIG. 3 shows a schematic diagram of a reset switch control circuit of an exemplary embodiment.
- the reset switch control circuit includes a signal input unit 301 , a buffer unit 302 , a first signal unit 303 and a second signal unit 304 .
- the signal input unit 301 includes resistors R98, R100, R104, capacitors C107, C134, and a diode D12, wherein: one end of the resistor R98 is electrically connected to the working power supply, and the other end is electrically connected to one end of the capacitor C107, and the other end of the capacitor C107 Grounding; one end of resistor R100 is grounded, the other end is electrically connected to the cathode of diode D12, the anode of diode D12 is electrically connected to one end of resistor R104, the other end of resistor R104 is electrically connected to the output signal IO_POKEY; one end of capacitor C134 is grounded, and the other end is electrically connected to the output The signal IO_POKEY; the second signal Power_Key is electrically connected to the resistor R98 and the cathode of the diode D12.
- the buffer unit 302 includes a chip U12, capacitors C104, C105, and C106, wherein: the capacitors C104, C105, and C106 are connected in parallel, one end of the capacitor C104 is grounded, and the other end is electrically connected to the working power supply, the power supply VCC end of the chip U12,
- the second signal Power_Key is electrically connected to the input terminal of the chip U12, and the output terminal of the chip U12 is electrically connected to the first signal unit 303.
- the buffer unit 302 may prevent false touches.
- the first signal unit 303 includes resistors R101, R102, R103, R105, R106, a capacitor C109, a triode Q3, and a MOS tube Q4; wherein: one end of the resistor R103 is electrically connected to the buffer unit 302, and the other end is electrically connected to the triode.
- the second signal unit 304 includes resistors R96 and R97, capacitors C108 and C128, a transistor Q2, and a MOS transistor Q1; wherein the base of the transistor Q2 is electrically connected to the first signal unit 303; the capacitor C108 and the base of the transistor Q2 The emitter and the emitter are connected in parallel; the emitter of transistor Q2 is grounded; the collector of transistor Q2 is electrically connected to the gate of MOS transistor Q4; the resistor R97 is connected in parallel with the gate and source of MOS transistor Q4; one end of resistor R96 is electrically connected to the gate of transistor Q2 The base is the drain of MOS tube Q1 at the other end; one end of capacitor C128 is electrically connected to the drain of MOS tube Q1, and the other end is grounded; the output signal LM_OFF is electrically connected to the drain of MOS tube Q1; The source of MOS tube Q1 is electrically connected to the working power supply.
- the second signal IO_POKEY is to send the switching signal of the reset switch to the main control chip for determining the key status.
- the device is not powered on, that is, the reset switch is not pressed: the second signal Power_Key is open circuited and GND, and the second signal Power_Key inputs a high level, which requires the main control chip to do a built-in pull-up, and it works at this time
- the power supply SWITCH_3V3 will pull up the second signal Power_Key, then the base of the transistor Q3 is at a high level, the transistor Q3 is turned on, the left side of the resistor R102 is at a low level, the transistor Q2 is turned off, and the gate of the MOS tube Q1 is at a high level. , the MOS tube Q1 is turned off, and the output signal LM_OFF is low level at this time; the diode D12 blocks the high level, and the output signal IO_POKEY has no output.
- the second signal Power_Key when the reset switch is pressed and the device is powered on, the second signal Power_Key is connected to GND, and GND will pull down the second signal Power_Key.
- the base of transistor Q3 is at low level, and the output signal IO_POKEY is at low level.
- the control chip receives the output signal IO_POKEY and determines that the reset switch is pressed; the base of transistor Q3 is low level, transistor Q3 is turned off, the left side of resistor R102 is high level, transistor Q2 is turned on, and the gate of MOS tube Q1 is low level , MOS tube Q1 is turned on, and the output signal LM_OFF is high level at this time.
- the reset switch state is: the second signal Power_Key is disconnected from GND, and the working power supply SWITCH_3V3 will pull up the second signal Power_Key.
- the base of the transistor Q3 is at a high voltage. flat, the output signal IO_POKEY is high level, the main control chip receives the output signal IO_POKEY and determines that the reset switch is released; the transistor Q3 is turned on, at this time the output signal LM_OFF is high level, the output signal LM_OFF will affect the base of the transistor Q2 Pull up, the output signal LM_OFF will maintain the high level state of the base of transistor Q2.
- transistor Q2 is turned on, the gate of MOS tube Q1 is at low level, and the output signal LM_OFF remains at high level.
- the second signal Power_Key is connected to GND, GND pulls down the second signal Power_Key, the base of the transistor Q3 is at a low level, and the output signal IO_POKEY is Low level, at this time the main control can judge that the button has been pressed, and the base of the transistor Q2 has been maintained at a high level by the output signal LM_OFF. No matter whether the reset switch button is pressed or released, the transistor will not change.
- the device when the button of the reset switch is pressed again and exceeds the preset shutdown seconds, the device is shut down.
- the output signal IO_POKEY is responsible for reading the button status.
- the main control will pull up the IO_POPC voltage.
- the MOS The gate of tube Q4 is at high level, MOS tube Q4 is turned on, pulling down the base of transistor Q2, and transistor Q2 is turned off.
- the gate of MOS tube Q1 is at high level, MOS tube Q1 is turned off, and the output signal LM_OFF is low level. flat.
- the reset switching power supply on-off control system is composed of basic components such as MOS tubes and transistors. It has low cost and low power consumption of the basic components.
- the static power consumption can be adjusted by adjusting the circuit impedance. Therefore, it can be low Low cost and low power consumption solve the problem of reset switch locking the power on.
- the reset switching power supply on-off control system sets the main control to read the button status according to the current, voltage and other signal detection circuits, sets an interface to shut down the system power supply, and determines the equipment status through the main control and various detection systems, and shuts down the power supply. Turn off the system reset switch.
- FIG. 4 shows a schematic diagram of a MOS switch circuit according to an exemplary embodiment.
- the MOS switch circuit includes photocoupler U14, resistors R69, R70, R71, R72, R73, R74, R75; capacitor C24, MOS tubes Q22, Q23, Q24, Q26.
- one end of the resistor R71 is electrically connected to the first signal LM_OFF, the other end is electrically connected to the 1 end of the optocoupler U14, and the 2 and 3 ends of the optocoupler U14 are grounded; one end of the resistor R72 is electrically connected to the optocoupler U14 4 terminals, the other end is electrically connected to the gate of MOS tube Q26; one end of resistor R73 is electrically connected to the gate of MOS tube Q26, and the other end is connected to the main power supply; the source of MOS tube Q26 is electrically connected to the main power supply, and the drain is electrically connected to resistor R70 One end of the resistor R70 is electrically connected to the gate of the MOS transistor Q22; one end of the capacitor C24 is electrically connected to the gate of the MOS transistor Q22, and the other end is grounded; one end of the resistor R69 is electrically connected to the gate of the MOS transistor Q22, and the other end is electrically connected to the gate of
- terminals 3 and 4 of the photocoupler U14 are turned on, the gate of the MOS tube Q26 is pulled low, the MOS tube Q26 is turned on, and the MOS tubes Q22, Q23, and Q24 conduction, system path.
- terminals 3 and 4 of the photocoupler U14 are turned off, the gate of the MOS tube Q26 is pulled high, the MOS tube Q26 is turned off, and the MOS tubes Q22, Q23, and Q24 Shut down, the system is disconnected.
Abstract
本申请提供一种复位开关电源通断控制电路及系统，用于复位开关，复位开关电源通断控制电路包括：复位开关控制电路，与所述复位开关连接，用于采集所述复位开关的状态并输出状态信号和第一控制信号；MOS开关电路，与所述复位开关控制电路连接，接收所述复位开关控制电路的所述第一控制信号；主控芯片，与所述复位开关控制电路连接，用于获取所述复位开关控制电路的所述状态信号，输出第二控制信号至所述复位开关控制电路。
Description
本申请涉及复位开关技术领域，具体而言，涉及一种复位开关电源通断控制电路及系统。
复位开关电源以小型、轻量和高效率的特点被广泛应用于以电子计算机为主导的各种终端设备、通信设备等几乎所有的电子设备，是当今电子信息产业飞速发展不可缺少的一种电源方式。电池产品对于本机的自耗电特别敏感，特别是在系统未开机，却需要持续供电的情况下开关电路。目前，按照现有传统方法设计复位开关电源，电路复杂、工作量大、成本高、效率低；而且因复位开关电源设计时的变量多，难以准确确定系统状态，使得主控与各种检测系统不能较好配合，不能准确关断复位开关电源。
因此，有必要提供一种低成本、低功耗的复位开关电源通断控制电路及系统，来解决复位开关锁定的问题，并改善主控与各检测设备的配合逻辑，准确关断复位开关电源。
在所述背景技术部分公开的上述信息仅用于加强对本申请的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
针对现有技术存在的不足，本申请提供一种复位开关电源通断控制电路及系统，以低成本、低功耗解决复位开关锁定开机的问题，并且根据电流、电压等检测电路告知主控，对系统状态做出判断，通过主控实现开关电路的关断。
根据本申请的第一方面，提出一种复位开关电源通断控制电路，用
于复位开关，包括：
复位开关控制电路，与所述复位开关连接，用于采集所述复位开关的状态并输出状态信号和第一控制信号；
MOS开关电路，与所述复位开关控制电路连接，接收所述复位开关控制电路的所述第一控制信号；
主控芯片，与所述复位开关控制电路连接，用于获取所述复位开关控制电路的所述状态信号，输出第二控制信号至所述复位开关控制电路。
根据一些实施例，所述复位开关电源通断控制电路还包括电源模块，用于给所述主控芯片、所述复位开关控制电路以及所述MOS开关电路供电。
根据一些实施例，所述复位开关控制电路包括信号输入单元、第一信号单元和第二信号单元，其中：
所述信号输入单元，用于根据所述复位开关的状态输出第一输出信号和所述状态信号；
所述第一信号单元，与所述信号输入单元连接，用于接收所述第一输出信号，输出第二输出信号；
所述第二信号单元，与所述第一信号单元连接，用于接收所述第二输出信号，输出所述第一控制信号。
根据一些实施例，所述复位开关控制电路还包括缓冲器单元，与所述信号输入单元连接，用于防止按键误触。
根据一些实施例，所述信号输入单元包括第一电阻、第二电阻、第三电阻、第一电容、第二电容和第一二极管，其中：
所述第一电阻的一端电连接所述电源模块，另一端电连接所述第一电容的一端和所述第一二极管的负极，所述第一电容的另一端接地；
所述第二电阻的一端电连接所述第一二极管的负极，另一端接地；
所述第一二极管的正极电连接所述第三电阻的一端，所述第三电阻的另一端电连接所述第二电容的一端，所述第二电容的另一端接地；
所述第一二极管的负极接收所述状态信号，并输出所述第一输出信号；
所述第三电阻的另一端电连接输出信号IO_POKEY。
根据一些实施例，所述缓冲器单元包括第一芯片，第三电容、第四电容和第五电容，其中：
所述第三电容、所述第四电容、所述第五电容并联；
所述第三电容的一端电连接所述电源模块，另一端接地；
所述第一芯片的输入端接收所述第一输出信号，电源端电连接所述电源模块，接地端接地，输出端电连接所述第一信号单元。
根据一些实施例，所述第一信号单元包括第四电阻、第五电阻、第六电阻、第七电阻、第八电阻，第六电容、第一三极管和第一MOS管，其中：
所述第六电阻的一端接收所述第一输出信号，另一端电连接所述第一三极管的基极；
所述第六电容的一端电连接所述第一三极管的基极，另一端接地；
所述第四电阻的一端电连接所述电源模块，另一端电连接所述第一三极管的集电极；
所述第五电阻的一端电连接所述第一三极管的集电极，另一端电连接所述第一MOS管的漏极；
所述第一三极管的发射极接地；
所述第七电阻与所述第一MOS管的栅极和源极并联；
所述第八电阻的一端电连接所述第一MOS管的栅极，另一端电连接输出信号IO_POPC；
所述第一MOS管的源极接地；
所述第一MOS管的漏极电连接所述第二信号单元，输出所述第二输出信号。
根据一些实施例，所述第二信号单元包括第九电阻、第十电阻、第七电容、第八电容、第二三极管和第二MOS管，其中：
所述第二三极管的基极电连接所述第一信号单元，用于接收所述第二输出信号；
所述第七电容与所述第二三极管的基极和发射极并联；
所述第九电阻的一端电连接所述第二三极管的基极，另一端电连接所述第二MOS管的漏极；
所述第八电容的一端电连接所述第二MOS管的漏极，另一端接地；
所述第十电阻与所述第二MOS管的栅极和源极并联；
所述第二三极管的发射极接地，集电极电连接所述第二MOS管的栅极；
所述第二MOS管的漏极输出所述第一控制信号，源极电连接所述电源模块。
根据一些实施例，包括：
在所述复位开关的状态为未按下的情况下，所述第一输出信号输出高电平，所述第二输出信号输出低电平，所述第一控制信号输出低电平；
在所述复位开关的状态为按下的情况下，所述第一输出信号输出低电平，所述第二输出信号输出高电平，所述第一控制信号输出高电平。
根据一些实施例，包括：
在所述复位开关的状态为按下后又松开的情况下，所述第一输出信号输出高电平，所述第二输出信号输出低电平，所述第一控制信号维持高电平。
根据一些实施例，包括：
在所述复位开关的按下时间超过关机时间阈值，则所述主控芯片输出所述第二控制信号至所述复位开关控制电路，所述第一控制信号输出低电平。
根据一些实施例，所述MOS开关电路包括光电耦合器、第十一电阻、第十二电阻、第十三电阻、第十四电阻、第十五电阻、第十六电阻、第十七电阻、第九电容、第三MOS管、第四MOS管、第五MOS管、第六MOS管，其中：
所述第十三电阻的一端接收所述第一控制信号，另一端电连接所述光电耦合器的第一端子；
所述光电耦合器的第二端子、第三端子接地；
所述第十四电阻的一端电连接所述第三MOS管的栅极，另一端电连接所述光电耦合器的第四端子；
所述第十五电阻与所述第三MOS管的栅极和源极并联；
所述第三MOS管的源极电连接所述电源模块；
所述第十二电阻的一端电连接所述第三MOS管的漏极，另一端电连接所述第四MOS管的栅极；
所述第九电容的一端电连接所述第四MOS管的栅极，另一端接地；
所述第四MOS管，所述第五MOS管和所述第六MOS管的栅极电连接，源极电连接，漏极接地；
所述第十一电阻与所述第四MOS管的栅极和源极并联；
所述第十六电阻的一端电连接所述第四MOS管的源极，另一端接地；
所述第十七电阻与所述第十六电阻并联。
根据一些实施例，在所述第一控制信号为高电平的情况下，所述第三MOS管导通，所述第四MOS管，所述第五MOS管和所述第六MOS管导通，所述复位开关电源通断控制电路通路；
在所述第一控制信号为低电平的情况下，所述第三MOS管关断，所述第四MOS管，所述第五MOS管和所述第六MOS管关断，所述复位开关电源通断控制电路断路。
根据本申请的第二方面，提出一种复位开关电源通断控制系统，其特征在于，包括如第一方面中任一项所述的复位开关电源通断控制电路。
本申请提供一种复位开关电源通断控制电路及系统，具备以下优点中的一个或多个：
1、复位开关电源通断控制系统由MOS管、三极管等基础元器件组成，成本较低，基础元件功耗较低，且可以通过调节电路阻抗来调节静态功耗，因此，可以低成本、低功耗解决复位开关锁定开机的问题。
2、根据示例实施例，复位开关电源通断控制系统设置主控根据电流、电压等检测电路读取按键状态，设置关断系统供电的接口，通过主控与各种检测系统搭配判断设备状态，关断系统复位开关。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本申请。
通过参照附图详细描述其示例实施例，本申请的上述和其它目标、
特征及优点将变得更加显而易见。下面描述的附图仅仅是本申请的一些实施例，而不是对本申请的限制。
图1示出一示例性实施例的复位开关电源通断控制系统示意图；
图2示出一示例性实施例的电源模块电路的示意图；
图3示出一示例性实施例的复位开关控制电路的示意图；
图4示出一示例性实施例的MOS开关电路的示意图。
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本申请将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有这些特定细节中的一个或更多，或者可以采用其它的方式、组元、材料、装置等。在这些情况下，将不详细示出或描述公知结构、方法、装置、实现、材料或者操作。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解，而有的操作/步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
本领域技术人员可以理解，附图只是示例实施例的示意图，附图中
的模块或流程并不一定是实施本申请所必须的，因此不能用于限制本申请的保护范围。
图1示出一示例性实施例的复位开关电源通断控制系统示意图。
如图1所示，复位开关电源通断控制系统包括DC-DC电源模块1、2，分别与总电源连接，用于将电压从12V转换成3.3V，其中：DC-DC电源模块1与复位开关控制电路连接，提供转换电源，复位开关与复位开关控制电路连接，用于控制复位开关控制电路开机；DC-DC电源模块1与MOS开关电路连接，用于提供转换电源；DC-DC电源模块2与主控芯片、电流检测模块和漏水传感器分别连接，用于提供供电电源；主控芯片与电流检测模块、漏水传感器连接，用于收集系统状态，由主控芯片判断，在系统异常时及时关机；主控芯片与复位开关控制电路连接，复位开关控制电路反馈按键状态，主控芯片通过按键和设备状态控制复位开关控制电路关机。
根据示例实施例，复位开关电源通断控制系统包括开关电路供电回流路径，此电路在电源有电的情况下，为持续通路的状态，如图1所示，此供电回流路径以虚线表示。
根据示例实施例，复位开关电源通断控制系统还包括系统供电回流路径，此路径GND回流会经过MOS开关电路进行开关控制，只有当MOS管打开的时候，才为通路，如图1所示，此供电回流路径以实线表示。
图2示出一示例性实施例的电源模块电路的示意图。
如图2所示，总电源经过芯片处理后，将12.6V电源转换为3.3V工作电源。
根据示例实施例，芯片U21的电源输入端连接电阻R114，电容C47，电容C48；电阻R114的另一端接12.6V总电源；电容C47，电容C48的另一端接地；芯片U21的电压输出端连接电容C49、C50，输出3.3V工作电源；电容C49、C50的另一端接地。
图3示出一示例性实施例的复位开关控制电路的示意图。
如图3所示，复位开关控制电路包括信号输入单元301、缓冲器单元302、第一信号单元303和第二信号单元304。
根据示例实施例，信号输入单元301包括电阻R98、R100、R104，电容C107、C134，二极管D12，其中：电阻R98的一端电连接工作电源，另一端电连接电容C107的一端，电容C107的另一端接地；电阻R100的一端接地，另一端电连接二极管D12的负极，二极管D12的正极电连接电阻R104的一端，电阻R104的另一端电连接输出信号IO_POKEY；电容C134的一端接地，另一端电连接输出信号IO_POKEY；第二信号Power_Key电连接电阻R98，二极管D12的负极。
根据示例实施例，缓冲器单元302包括芯片U12，电容C104、C105、C106，其中：电容C104、C105、C106并联，电容C104的一端接地，另一端电连接工作电源，芯片U12的供电VCC端，第二信号Power_Key电连接芯片U12的输入端，芯片U12的输出端电连接第一信号单元303。
根据一些实施例，缓冲器单元302可以防止误触。
根据示例实施例，第一信号单元303包括电阻R101、R102、R103、R105、R106，电容C109，三极管Q3、MOS管Q4；其中：电阻R103的一端电连接缓冲器单元302，另一端电连接三极管Q3的基极；电阻R101的一端电连接工作电源，另一端电连接三极管Q3的集电极；电阻R102的一端电连接三极管Q3的集电极，另一端电连接MOS管Q4的漏极；电容C109的一端电连接三极管Q3的基极，另一端接地；三极管Q3的发射极接地；电阻R106的一端电连接输出信号IO_POPC，另一端电连接MOS管Q4的栅极；电阻R105与MOS管Q4的栅极和源极并联；MOS管Q4的源极接地；MOS管Q4的漏极电连接第二信号单元304。
根据示例实施例，第二信号单元304包括电阻R96、R97，电容C108、C128，三极管Q2，MOS管Q1；其中，三极管Q2的基极电连接第一信号单元303；电容C108与三极管Q2的基极和发射极并联；三极管Q2的发射极接地；三极管Q2的集电极电连接MOS管Q4的栅极；电阻R97与MOS管Q4的栅极和源极并联；电阻R96的一端电连接三极管Q2的基极，另一端MOS管Q1的漏极；电容C128的一端电连接MOS管Q1的漏极，另一端接地；输出信号LM_OFF与MOS管Q1的漏极电连接；
MOS管Q1的源极电连接工作电源。
根据示例实施例，第二信号IO_POKEY是把复位开关的开关信号发送到主控芯片，用于判断按键状态。
根据示例实施例，设备未开机操作状态，即复位开关未按下：第二信号Power_Key与GND之间属于断路，第二信号Power_Key输入高电平，需要主控芯片做内置上拉，此时工作电源SWITCH_3V3会对第二信号Power_Key进行上拉，则三极管Q3的基极为高电平，三极管Q3导通，电阻R102左侧为低电平，三极管Q2关断，MOS管Q1的栅极为高电平，MOS管Q1关断，此时输出信号LM_OFF为低电平；二极管D12隔断高电平，则输出信号IO_POKEY无输出。
根据示例实施例，复位开关按下，设备开机操作状态，第二信号Power_Key与GND连接，GND会对第二信号Power_Key进行下拉，三极管Q3基极为低电平，输出信号IO_POKEY为低电平，主控芯片接收到输出信号IO_POKEY并判断复位开关按下；三极管Q3的基极为低电平，三极管Q3关断，电阻R102左侧为高电平，三极管Q2打开，MOS管Q1的栅极为低电平，MOS管Q1打开，此时输出信号LM_OFF为高电平。
根据示例实施例，当复位开关松开时，设备开机，松复位开关状态：第二信号Power_Key与GND断路，工作电源SWITCH_3V3会对第二信号Power_Key进行上拉，此时三极管Q3的基极为高电平，输出信号IO_POKEY为高电平，主控芯片接收到输出信号IO_POKEY并判断复位开关松开；三极管Q3导通，此时输出信号LM_OFF为高电平，输出信号LM_OFF会对三极管Q2的基极上拉，输出信号LM_OFF会维持三极管Q2的基极高电平状态，当三极管Q2的基极为高电平时三极管Q2导通，MOS管Q1的栅极为低电平，输出信号LM_OFF维持高电平。
根据示例实施例，当复位开关再次按下，设备开机，按复位开关状态：第二信号Power_Key与GND连接，GND对第二信号Power_Key进行下拉，三极管Q3的基极为低电平，输出信号IO_POKEY为低电平，此时主控可判断按键已经按下，三极管Q2的基极已经被输出信号LM_OFF维持高电平，不管复位开关按键按下、松开都不会改变三极管
Q2的电平状态。
根据示例实施例，当复位开关的按键再次按下，超过预设关机秒数时，设备关机。
根据示例实施例，当复位开关的按键再次按下，输出信号IO_POKEY负责读取按键状态，复位开关的按键按下的时间超过预设关机秒数时，主控会拉高IO_POPC电压，此时MOS管Q4的栅极为高电平，MOS管Q4导通，拉低三极管Q2的基极，三极管Q2关断，MOS管Q1的栅极为高电平，MOS管Q1关断，输出信号LM_OFF为低电平。
根据示例实施例，复位开关电源通断控制系统由MOS管、三极管等基础元器件组成，成本较低，基础元件功耗较低，且可以通过调节电路阻抗来调节静态功耗，因此，可以低成本、低功耗解决复位开关锁定开机的问题。
根据示例实施例，复位开关电源通断控制系统设置主控根据电流、电压等信号检测电路读取按键状态，设置关断系统供电的接口，通过主控与各种检测系统搭配判断设备状态，关断系统复位开关。
图4示出一示例性实施例的MOS开关电路的示意图。
如图4所示，MOS开关电路包括光电耦合器U14，电阻R69，R70，R71，R72，R73，R74，R75；电容C24，MOS管Q22，Q23，Q24，Q26。
根据示例实施例，电阻R71的一端电连接第一信号LM_OFF，另一端电连接光电耦合器U14的1端，光电耦合器U14的2、3端接地；电阻R72的一端电连接光电耦合器U14的4端，另一端电连接MOS管Q26的栅极；电阻R73的一端电连接MOS管Q26的栅极，另一端接总电源；MOS管Q26的源极电连接总电源，漏极电连接电阻R70的一端，电阻R70的另一端电连接MOS管Q22的栅极；电容C24的一端电连接MOS管Q22的栅极，另一端接地；电阻R69的一端电连接MOS管Q22的栅极，另一端电连接MOS管Q22的源极；MOS管Q22、Q23、Q24的栅极电连接，源极电连接，漏极接地；电阻R75的一端电连接MOS管Q24的源极，另一端接地；电阻R74与电阻R75并联。
根据示例实施例，当第一信号LM_OFF为高电平时，光电耦合器U14的3、4端导通，MOS管Q26的栅极被拉低，MOS管Q26导通，MOS管Q22、Q23、Q24导通，系统通路。
根据示例实施例，当第一信号LM_OFF为低电平时，光电耦合器U14的3、4端关断，MOS管Q26的栅极被拉高，MOS管Q26关断，MOS管Q22、Q23、Q24关断，系统断路。
应清楚地理解，本申请描述了如何形成和使用特定示例，但本申请不限于这些示例的任何细节。相反，基于本申请公开的内容的教导，这些原理能够应用于许多其它实施例。
此外，需要注意的是，上述附图仅是根据本申请示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
以上具体地示出和描述了本申请的示例性实施例。应可理解的是，本申请不限于这里描述的详细结构、设置方式或实现方法；相反，本申请意图涵盖包含在所附权利要求的精神和范围内的各种修改和等效设置。
Claims (14)
- 一种复位开关电源通断控制电路，用于复位开关，其特征在于，包括：复位开关控制电路，与所述复位开关连接，用于采集所述复位开关的状态并输出状态信号和第一控制信号；MOS开关电路，与所述复位开关控制电路连接，接收所述复位开关控制电路的所述第一控制信号；主控芯片，与所述复位开关控制电路连接，用于获取所述复位开关控制电路的所述状态信号，输出第二控制信号至所述复位开关控制电路。
- 如权利要求1所述的控制电路，其特征在于，所述复位开关电源通断控制电路还包括电源模块，用于给所述主控芯片、所述复位开关控制电路以及所述MOS开关电路供电。
- 如权利要求2所述的控制电路，其特征在于，所述复位开关控制电路包括信号输入单元、第一信号单元和第二信号单元，其中：所述信号输入单元，用于根据所述复位开关的状态输出第一输出信号和所述状态信号；所述第一信号单元，与所述信号输入单元连接，用于接收所述第一输出信号，输出第二输出信号；所述第二信号单元，与所述第一信号单元连接，用于接收所述第二输出信号，输出所述第一控制信号。
- 如权利要求3所述的控制电路，其特征在于，所述复位开关控制电路还包括缓冲器单元，与所述信号输入单元连接，用于防止按键误触。
- 如权利要求3所述的控制电路，其特征在于，所述信号输入单元包括第一电阻、第二电阻、第三电阻、第一电容、第二电容和第一二 极管，其中：所述第一电阻的一端电连接所述电源模块，另一端电连接所述第一电容的一端和所述第一二极管的负极，所述第一电容的另一端接地；所述第二电阻的一端电连接所述第一二极管的负极，另一端接地；所述第一二极管的正极电连接所述第三电阻的一端，所述第三电阻的另一端电连接所述第二电容的一端，所述第二电容的另一端接地；所述第一二极管的负极接收所述状态信号，并输出所述第一输出信号；所述第三电阻的另一端电连接输出信号IO_POKEY。
- 如权利要求4所述的控制电路，其特征在于，所述缓冲器单元包括第一芯片，第三电容、第四电容和第五电容，其中：所述第三电容、所述第四电容、所述第五电容并联；所述第三电容的一端电连接所述电源模块，另一端接地；所述第一芯片的输入端接收所述第一输出信号，电源端电连接所述电源模块，接地端接地，输出端电连接所述第一信号单元。
- 如权利要求3所述的控制电路，其特征在于，所述第一信号单元包括第四电阻、第五电阻、第六电阻、第七电阻、第八电阻，第六电容、第一三极管和第一MOS管，其中：所述第六电阻的一端接收所述第一输出信号，另一端电连接所述第一三极管的基极；所述第六电容的一端电连接所述第一三极管的基极，另一端接地；所述第四电阻的一端电连接所述电源模块，另一端电连接所述第一三极管的集电极；所述第五电阻的一端电连接所述第一三极管的集电极，另一端电连接所述第一MOS管的漏极；所述第一三极管的发射极接地；所述第七电阻与所述第一MOS管的栅极和源极并联；所述第八电阻的一端电连接所述第一MOS管的栅极，另一端电连 接输出信号IO_POPC；所述第一MOS管的源极接地；所述第一MOS管的漏极电连接所述第二信号单元，输出所述第二输出信号。
- 如权利要求3所述的控制电路，其特征在于，所述第二信号单元包括第九电阻、第十电阻、第七电容、第八电容、第二三极管和第二MOS管，其中：所述第二三极管的基极电连接所述第一信号单元，用于接收所述第二输出信号；所述第七电容与所述第二三极管的基极和发射极并联；所述第九电阻的一端电连接所述第二三极管的基极，另一端电连接所述第二MOS管的漏极；所述第八电容的一端电连接所述第二MOS管的漏极，另一端接地；所述第十电阻与所述第二MOS管的栅极和源极并联；所述第二三极管的发射极接地，集电极电连接所述第二MOS管的栅极；所述第二MOS管的漏极输出所述第一控制信号，源极电连接所述电源模块。
- 如权利要求3所述的控制电路，其特征在于，包括：在所述复位开关的状态为未按下的情况下，所述第一输出信号输出高电平，所述第二输出信号输出低电平，所述第一控制信号输出低电平；在所述复位开关的状态为按下的情况下，所述第一输出信号输出低电平，所述第二输出信号输出高电平，所述第一控制信号输出高电平。
- 如权利要求9所述的控制电路，其特征在于，包括：在所述复位开关的状态为按下后又松开的情况下，所述第一输出信号输出高电平，所述第二输出信号输出低电平，所述第一控制信号维持高电平。
- 如权利要求9所述的控制电路，其特征在于，包括：在所述复位开关的按下时间超过关机时间阈值，则所述主控芯片输出所述第二控制信号至所述复位开关控制电路，所述第一控制信号输出低电平。
- 如权利要求5所述的控制电路，其特征在于，所述MOS开关电路包括光电耦合器、第十一电阻、第十二电阻、第十三电阻、第十四电阻、第十五电阻、第十六电阻、第十七电阻、第九电容、第三MOS管、第四MOS管、第五MOS管、第六MOS管，其中：所述第十三电阻的一端接收所述第一控制信号，另一端电连接所述光电耦合器的第一端子；所述光电耦合器的第二端子、第三端子接地；所述第十四电阻的一端电连接所述第三MOS管的栅极，另一端电连接所述光电耦合器的第四端子；所述第十五电阻与所述第三MOS管的栅极和源极并联；所述第三MOS管的源极电连接所述电源模块；所述第十二电阻的一端电连接所述第三MOS管的漏极，另一端电连接所述第四MOS管的栅极；所述第九电容的一端电连接所述第四MOS管的栅极，另一端接地；所述第四MOS管，所述第五MOS管和所述第六MOS管的栅极电连接，源极电连接，漏极接地；所述第十一电阻与所述第四MOS管的栅极和源极并联；所述第十六电阻的一端电连接所述第四MOS管的源极，另一端接地；所述第十七电阻与所述第十六电阻并联。
- 如权利要求12所述的控制电路，其特征在于，在所述第一控制信号为高电平的情况下，所述第三MOS管导通，所述第四MOS管，所述第五MOS管和所述第六MOS管导通，所述复位开关电源通断控 制电路通路；在所述第一控制信号为低电平的情况下，所述第三MOS管关断，所述第四MOS管，所述第五MOS管和所述第六MOS管关断，所述复位开关电源通断控制电路断路。
- 一种复位开关电源通断控制系统，其特征在于，包括如权利要求1-13中任一项所述的复位开关电源通断控制电路。
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