WO2024002231A1 - 控制器供电系统、电子设备及存储介质 - Google Patents

控制器供电系统、电子设备及存储介质 Download PDF

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Publication number
WO2024002231A1
WO2024002231A1 PCT/CN2023/103798 CN2023103798W WO2024002231A1 WO 2024002231 A1 WO2024002231 A1 WO 2024002231A1 CN 2023103798 W CN2023103798 W CN 2023103798W WO 2024002231 A1 WO2024002231 A1 WO 2024002231A1
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WIPO (PCT)
Prior art keywords
circuit
power
domain
chip
control processing
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Application number
PCT/CN2023/103798
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English (en)
French (fr)
Inventor
杨莉
赵楠楠
王强
赵目龙
王泽尉
尹光雨
Original Assignee
中国第一汽车股份有限公司
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Publication of WO2024002231A1 publication Critical patent/WO2024002231A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads

Definitions

  • Embodiments of the present application relate to the field of automotive power supply technology, for example, to a controller power supply system, electronic equipment and storage media.
  • the new centralized domain controller is replacing the previous multiple distributed electronic controllers (electronic Control Unit, ECU).
  • ECU electronic Control Unit
  • the vehicle control domain controller is the central processing unit in the new electronic and electrical architecture.
  • Vehicle control domain controllers in the related art usually include a high-performance processing unit and a microprocessor unit, which are used to implement vehicle control, vehicle functions, management and other functions.
  • the power supply of the high-performance processing unit usually uses a power management chip. and multiple discrete power supply chips to provide multi-channel power supply and power supply sequence management.
  • the microprocessor unit usually uses a power management chip or multiple discrete power supply chips to provide multi-channel power supply and power supply sequence management.
  • This application provides a controller power supply system, electronic equipment and storage media that can support redundant power supply of two power supplies, realize the isolation of the two power supplies, and have overvoltage, undervoltage, overcurrent, and
  • the over-temperature diagnosis and protection function can improve the functional safety level of the controller power supply system when the Microcontroller Unit (MCU) domain serves as the safety monitoring of the controller power supply system.
  • MCU Microcontroller Unit
  • the embodiment of the present application provides a controller power supply system, which includes: a power input circuit 10, a microprocessor circuit 20, a main control processing circuit 30, a driving processing circuit 40, a wake-up circuit 60 and a parking processing circuit 50;
  • the power input circuit 10 includes: a first power input circuit 11 and a second power input circuit 12; the first power input circuit 11 and the second power input circuit 12 are mutual backups and are jointly configured as a microprocessor circuit 20,
  • the main control processing circuit 30, the driving processing circuit 40 and the parking processing circuit 50 provide power supply a;
  • the wake-up circuit 60 is configured to provide the control signal e1 for the microprocessor circuit 20 and to control the main processing circuit.
  • Road 30 provides the wake-up signal;
  • the microprocessor circuit 20 is configured to provide the control signal a1 to the parking processing circuit 50 based on the control signal e1, provide the control signal a2 to the driving processing circuit 40 and provide the control signal a3 to the main control processing circuit 30;
  • the main control processing circuit 30 is configured to provide the control signal b1 to the driving processing circuit 40 based on the wake-up signal, provide the control signal b2 to the parking processing circuit 50 and provide the control signal b3 to the microprocessor circuit 20, so that the driving processing circuit 40 is in control
  • the parking processing circuit 50 operates normally under the control of the control signal b1 and the control signal a2, and the parking processing circuit 50 operates normally under the control of the control signal a1 and the control signal b2.
  • An embodiment of the present application provides an electronic device, including:
  • processors one or more processors
  • memory configured to store one or more programs
  • the one or more processors are caused to implement the controller power supply system described in any embodiment of this application.
  • Embodiments of the present application provide a storage medium on which a computer program is stored.
  • the program is executed by a processor, the controller power supply system described in any embodiment of the present application is implemented.
  • Figure 1 is a first structural schematic diagram of a controller power supply system provided by an embodiment of the present application
  • FIG. 2 is a second structural schematic diagram of the controller power supply system provided by the embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a power input circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of the main control processing module provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of the driving control processing module provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of the parking control processing module provided by the embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a wake-up circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG 1 is a first structural schematic diagram of a controller power supply system provided by an embodiment of the present application.
  • the system can be executed by an electronic device.
  • the electronic device can be implemented in the form of software and/or hardware.
  • the electronic device can be integrated into any smart device with network communication capabilities.
  • the controller power supply system may include: power input circuit 10, microprocessor circuit 20, main control processing circuit 30, driving processing circuit 40, wake-up circuit 60 and parking processing circuit 50.
  • the power input circuit 10 includes: a first power input circuit 11 and a second power input circuit 12; the first power input circuit 10 and the second power input circuit 12 are mutual backups and are configured as a microprocessor circuit 20 and a main control processing
  • the circuit 30, the driving processing circuit 40 and the parking processing circuit 50 provide power supply a;
  • the wake-up circuit 60 is configured to provide the control signal e1 for the microprocessor circuit 20 and the wake-up signal for the main control processing circuit 30;
  • the microprocessor circuit 20 is configured to The control signal a1 is provided to the parking processing circuit 50 based on the control signal e1, the control signal a2 is provided to the driving processing circuit 40, and the control signal a3 is provided to the main control processing circuit 30;
  • the main control processing circuit 30 is configured to provide the driving signal based on the wake-up signal.
  • the processing circuit 40 provides a control signal b1, a control signal b2 for the parking processing circuit 50 and a control signal b3 for the microprocessor circuit 20, so that the driving processing circuit 40 operates normally under the control of the control signal b1 and the control signal a2, and
  • the parking processing circuit 50 is allowed to operate normally under the control of the control signal a1 and the control signal b2.
  • Embodiments of the present application can support redundant power supply of dual-channel power supplies, realize isolation of the two-channel power supplies, and have functions of diagnosis and protection of overvoltage, undervoltage, overcurrent, and overtemperature of the two-channel power supplies; Embodiments of the present application It can ensure the independence of power supply between different processing domains within the high-performance processor chip, and can flexibly enable low-power consumption mode, which can significantly reduce system power consumption when central processing unit (Central Processing Unit, CPU) domain operation is not required. It can improve the robustness of the system and avoid interference from single point failures in the MCU domain and CPU domain subsystems. When the MCU domain is used as the safety monitoring of the system, it can improve the functional safety level of the system.
  • CPU Central Processing Unit
  • the embodiments of the present application can power multiple high-performance processor chips, and the solution is scalable. Several high-performance processing modules can be added based on this power supply topology; the embodiments of the present application can support wake-up scene recognition and purposeful It controls the power supply of each processor unit and can flexibly control the power consumption of the entire converged vehicle control domain controller.
  • the controller power supply system proposed in the embodiment of the present application includes a power input circuit, a microprocessor circuit, a main control processing circuit, a driving processing circuit, a wake-up circuit and a parking processing circuit; wherein the power input circuit includes: a first power input circuit and a third Two power input circuits; the first power input circuit and the second power input circuit back up each other and jointly provide power for the microprocessor circuit, the main control processing circuit, the driving processing circuit and the parking processing circuit.
  • the other power input circuit can continue to provide power to the system, thus ensuring the independence of power supply between different processing domains within the high-performance processor chip and enabling flexible activation of low-power modes.
  • the controller power supply system proposed in the embodiment of this application can support the redundant power supply of dual power supplies, realize the isolation of the two power supplies, and has the ability to diagnose and diagnose overvoltage, undervoltage, overcurrent, and overtemperature of the two power supplies. Protection function, when the MCU domain is used as the security monitoring of the system, it can improve the functional safety level of the system.
  • the technical solution of the embodiment of the present application is simple, convenient and easy to implement. It is easy to popularize and has a wider scope of application.
  • FIG. 2 is a second structural schematic diagram of a controller power supply system provided by an embodiment of the present application.
  • the controller power supply system may include: power input circuit 10, power management module 21, microprocessor module 22, DC voltage conversion circuit 31, main control processing module 32, DC voltage conversion circuit 41, driving control processing Module 42, DC voltage conversion circuit 51, parking control processing module 52, wake-up circuit 60.
  • the power input circuit 10 includes a first power input circuit 11 and a second power input circuit 12, which jointly provide power supply a for the system, and provide the first monitoring signal A and the second monitoring signal B to the main control processing module 32.
  • the power management module 21 converts the power supply a from the power input circuit 10 into the power supply b required by the microprocessor module 22, and monitors each other with the microprocessor module 22 through different monitoring signals.
  • the control signal of the power management module 21 e1 comes from the first wake-up circuit 61 in the wake-up circuit 60 .
  • the microprocessor module 22 is powered by the output power supply b of the power management module 21, and monitors each other with the power management module 21 through different monitoring signals.
  • the microprocessor module 22 provides the control signal a1, and communicates with the main control processing module 32
  • the provided control signal b2 jointly controls the DC voltage conversion circuit 51 .
  • the microprocessor module 22 provides a control signal a2, which together with the control signal b1 provided by the main control processing module 32, controls the DC voltage conversion circuit 41.
  • the microprocessor module 22 also provides a control signal a3 to control the main control processing module 32.
  • the DC voltage conversion circuit 31 converts the power supply a from the power input circuit 10 into the power supply c required by the main control processing module 32, and provides a control signal e2 to control the main control processing module 32.
  • the main control processing module 32 is powered by the output power supply c of the DC voltage conversion circuit 31.
  • the control signal e2 of the main control processing module 32 comes from the DC voltage conversion circuit 31.
  • the main control processing module 32 provides the control signal b2, which communicates with the microprocessor module
  • the control signal a1 provided by 22 jointly controls the DC voltage conversion circuit 51.
  • the control signal b1 provided by the main control processing module 32 and the control signal a2 provided by the microprocessor module 22 jointly control the DC voltage conversion circuit 41.
  • the main control processing module 32 passes The first monitoring signal A and the second monitoring signal B monitor the power input circuit 10 , and the wake-up signal of the main control processing module 32 comes from the second wake-up circuit 62 in the wake-up circuit 60 .
  • the DC voltage conversion circuit 41 converts the power supply a from the power input circuit 10 into the power supply d required by the driving control processing module 42, and provides the control signal c to the driving control processing module 42.
  • the control signal f1 of the DC voltage conversion circuit 41 comes from the microcomputer.
  • the control signal a2 of the processor module 22 and the control signal b1 of the main control processing module 32 are output after passing through the OR gate processing circuit 1 .
  • the driving control processing module 42 is powered by the output power supply d of the DC voltage conversion circuit 41.
  • the control signal c of the vehicle control processing module 42 comes from the DC voltage conversion circuit 41 .
  • the DC voltage conversion circuit 51 converts the power supply a from the power input circuit 10 into the power supply e required by the parking control processing module 52, and provides the control signal d to the parking control processing module 52.
  • the control signal f2 of the DC voltage conversion circuit 51 The control signal a1 from the microprocessor module 22 and the control signal b2 from the main control processing module 32 are output after passing through the OR gate processing circuit 2 .
  • the parking control processing module 52 is powered by the output power supply e from the DC voltage conversion circuit 51 , and the control signal d of the parking control processing module 52 is from the DC voltage conversion circuit 51 .
  • the wake-up circuit 60 includes a first wake-up circuit 61 and a second wake-up circuit 62 , where the first wake-up circuit 61 provides the control signal e1 for the power management module 21 , and the second wake-up circuit 62 provides a wake-up signal for the main control processing module 32 .
  • the controller power supply system proposed in the embodiment of the present application includes a power input circuit, a microprocessor circuit, a main control processing circuit, a driving processing circuit, a wake-up circuit and a parking processing circuit; wherein the power input circuit includes: a first power input circuit and the second power input circuit; the first power input circuit and the second power input circuit back up each other, and jointly provide power for the microprocessor circuit, the main control processing circuit, the driving processing circuit and the parking processing circuit.
  • the other power input circuit can continue to provide power to the system, thus ensuring the independence of power supply between different processing domains within the high-performance processor chip and enabling flexible activation of low-power modes.
  • the controller power supply system proposed in the embodiment of this application can support the redundant power supply of dual power supplies, realize the isolation of the two power supplies, and has the ability to diagnose and diagnose overvoltage, undervoltage, overcurrent, and overtemperature of the two power supplies.
  • the protection function when the MCU domain is used as the security monitoring of the system, can improve the functional safety level of the system; moreover, the technical solution of the embodiment of the present application is simple and convenient to implement, easy to popularize, and has a wider scope of application.
  • FIG. 3 is a schematic structural diagram of a power input circuit provided by an embodiment of the present application.
  • two power inputs (the first battery and the second battery), after being processed by the first power input circuit 11 and the second power input circuit 12 respectively, are combined into one power supply a to power the system.
  • the embodiment of the present application provides redundant power supply and isolation of the two power supplies, and diagnoses and protects the undervoltage, overvoltage, overcurrent, and overtemperature of the two power supplies.
  • the first power input circuit AA may include: a first power isolation chip 111, a first N-channel metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) tube group and a first current sampling resistor R.
  • the first N-channel MOSFET tube group includes: N-channel MOSFET tube (Qa1) and N-channel MOSFET tube (Qa2).
  • the second power input circuit AB may include: a second power isolation chip 211, a second N-channel MOSFET tube group, and a second current sampling resistor R2.
  • the second N-channel MOSFET tube group includes: N-channel MOSFET tube (Qb1) and N-channel MOSFET tube (Qb2).
  • the gate drive control MOSFET transistors Qa1 and Qa2 of the first power isolation chip 111 are in the conductive state.
  • the gate drive control MOSFET transistors Qb1 and Qb2 of the second power isolation chip 211 are in the conduction state.
  • the voltages of the first battery and the second battery are normally transmitted to Vout_A and Vout_B respectively, ensuring the normal operation of the back-end power chip, and the two power supplies are mutual backups.
  • the first power isolation chip 111 of the first battery channel monitors that the voltage of the first battery is lower than the set undervoltage shutdown threshold, the first power isolation chip 111 is automatically turned off within 1 us.
  • the gate is driven, and fault feedback is performed by setting the potential of the pin FAULT of the first power isolation chip 111 low, that is, the main control processing circuit 30 is notified of the undervoltage fault through the pin FAULT.
  • the normal voltage of the second battery can maintain the normal output power supply a of Vout_B.
  • the first power isolation chip 111 of the first battery monitors that the voltage of the first battery is higher than the set overvoltage shutdown threshold, the first power isolation chip 111 will be automatically turned off within 1 us.
  • the gate is driven, and fault feedback is performed by setting the potential of the pin FAULT of the first power isolation chip 111 low, that is, notifying the main control processing circuit 30 of the overvoltage fault through the pin FAULT.
  • the normal voltage of the second battery can maintain the normal output power supply a of Vout_B.
  • the power isolation chip 111 of the overcurrent channel monitors that the current on the current sampling resistor R1 is greater than the set threshold, it will automatically turn off the gate drive of the first power isolation chip 111 within 1us, and pass Set the potential of the pin FAULT of the first power isolation chip 111 low for fault feedback, that is, notify the main control processing circuit 30 of the overcurrent fault through the pin FAULT; when the power isolation chip of one channel, such as the first power isolation chip 111, monitors When its own temperature is higher than the temperature threshold, the gate driver of the first power isolation chip 111 is automatically turned off, and fault feedback is performed by setting the potential of the pin FAULT of the first power isolation chip 111 low, that is, the main control process is notified through the pin FAULT. Circuit 30 should have an over-temperature fault.
  • both the first power input circuit 11 and the second power input circuit 12 can independently monitor their own under-voltage, over-voltage, over-current, and over-temperature faults, and can turn off the drive in time, thereby realizing the protection of the power supply.
  • the two power supplies not only work independently, but also when one power supply is shut down due to a fault, it does not affect the normal operation of the back-end power chip, achieving dual power supply isolation and redundant power supply.
  • the first power input circuit 11 is also configured to provide the first monitoring signal to the main control processing circuit 30 through the first power isolation chip 111; the second power input circuit 12 is also configured to provide the main control processing through the second power isolation chip 211. Circuit 30 provides a second monitoring signal.
  • FIG 4 is a schematic structural diagram of a main control processing module provided by an embodiment of the present application.
  • the main The control processing module 32 may include: a power management unit 321 and a main control processing unit 322; wherein the power management unit 321 includes: a first power management chip r1, a second power management chip r2, a first DC voltage conversion chip r3, and a second power management chip r3. DC voltage conversion chip r4.
  • the first power management chip r1 provides multi-channel power supply f1-fn and timing management of multiple power supplies to the MCU domain microprocessing unit domain 3221 in the main control processing unit 322; the second power management chip r2
  • the CPU domain computing processing unit domain 3222 provides multi-channel power supply g1-gn and timing management of multiple power supplies; the first DC voltage conversion chip r3 and the second DC voltage conversion chip r4 are respectively the WKUP domain in the main control processing unit 322
  • the wake-up processing unit domain 3223C223 provides power supplies h1 and h2.
  • the first power management chip r1 provides control signals b6, b4, and b5 to the second power management chip r2, the first DC voltage conversion chip r3, and the second DC voltage conversion chip r4 respectively.
  • the embodiment of the present application can realize independent power supply and timing management of different processing unit domains in the main control processing unit 322.
  • the power management unit 321 When powered on, the power management unit 321 provides the required multiple power supplies f1-fn, g1-gn, h1, h2 to the main control processing unit 322.
  • the first power management chip r1 uses its own settings and control signals b6, b4, b5 manages the timing sequence of power supply f1-fn, g1-gn, h1, h2 to ensure that the main control processing unit 322 can be powered on and off correctly and work normally.
  • the power supply output of the second power management chip r2 can be turned off through the control signal b6.
  • the CPU domain computing processing unit domain 3222 in the main control processing unit 322 does not work, which greatly reduces the power of the main control processing unit 322. power consumption without affecting the normal operation of the MCU domain.
  • the MCU domain and the CPU domain are completely independent, which can also improve the functional safety level of the system.
  • the embodiments of the present application can ensure the independence of power supply between different processing domains within the high-performance processor chip, and can flexibly enable low-power consumption mode (that is, power consumption can be significantly reduced by turning off the CPU domain when the CPU domain operation is not required), and can Improving system robustness can avoid interference from single-point failures in the MCU domain and CPU domain subsystems.
  • the MCU domain is used as a safety monitor for the system, the functional safety level of the system can be improved.
  • FIG. 5 is a schematic structural diagram of a driving control processing module provided by an embodiment of the present application.
  • the driving control processing module 42 includes: a power management unit 421 and a driving control processing unit 422, where the power management unit 421 includes: a third power management chip t1, a fourth power management chip t2, a third DC voltage
  • the conversion chip t3 and the third power management chip t1 provide multi-channel power supply i1-in and timing management of multiple power supplies for the MCU domain microprocessing unit domain 42211 in the driving control processing unit 422;
  • the fourth power management chip t2 provides driving control
  • the CPU domain computing processing unit domain 42221 in the processing unit 422 provides multiple power supplies j1-jn and timing management of the multiple power supplies;
  • the third DC voltage conversion chip t3 provides power supply k for the video encoding and decoding circuit 4222.
  • the third power management chip t1 provides the control signal c1 to the fourth power management chip t2, and the driving control processing unit 422 provides the control signal c2 to the third DC voltage conversion chip b3 to respectively control the fourth power management chip t2 and the third DC voltage.
  • the embodiment of the present application can realize independent power supply and timing management of different processing unit domains in the driving control processing chip 4221.
  • the power management unit 421 When powered on, the power management unit 421 provides the required multiple power supplies i1-in, j1-jn, k to the driving control processing unit 422.
  • the third power management chip t1 uses its own settings and control signals to c1, manages the timing of power supply i1-in, j1-jn, and the driving control processing unit 422 controls the timing of power supply k through the control signal c2, jointly ensuring that the driving control processing unit 422 can be powered on and off correctly and work normally.
  • FIG. 6 is a schematic structural diagram of a parking control processing module provided by an embodiment of the present application.
  • the parking control processing module 52 includes: a power management unit 521 and a parking control processing unit 522, wherein the power management unit 521 includes: a fifth power management chip y1, a sixth power management chip y2 and a fourth DC Voltage conversion chip y3.
  • the fifth power management chip y1 provides multi-channel power supply l1-ln and timing management of multiple power supplies for the MCU domain microprocessing unit domain 52211 in the parking control processing unit 522
  • the sixth power management chip y2 is the parking control processing unit.
  • the CPU domain computing processing unit domain 52212 in 522 provides multiple power supplies m1-mn and timing management of multiple power supplies.
  • the fourth DC voltage conversion chip y3 provides power supply n for the video encoding and decoding circuit 5222.
  • the fifth power management chip y1 provides the control signal d1 to the sixth power management chip y2, and the parking control processing unit 522 provides the control signal d2 to the fourth DC voltage conversion chip y3 to control the sixth power management chip y2 and the fourth DC respectively.
  • the embodiment of the present application can realize independent power supply and timing management of different processing unit domains in the parking control processing chip 5221. When powered on, the power management unit 521 provides the required multiple power supplies l1-ln, m1-mn, n to the parking control processing unit 522.
  • the fifth power management chip y1 manages the power supply l1 through its own settings and control signal d1. -ln, m1-mn timing, the parking control processing unit 522 controls the timing of power supply n through the control signal d2, jointly ensuring that the parking control processing unit 522 can be powered on and off correctly and work normally.
  • FIG. 7 is a schematic structural diagram of a wake-up circuit provided by an embodiment of the present application.
  • the wake-up circuit 60 includes a first wake-up circuit 61 and a second wake-up circuit 62.
  • the first wake-up circuit 61 includes: key door KL15 wake-up signal, brake signal, Controller Area Network (Controller Area Network, CAN) Wake-up signal 1, the above signals are connected to the anodes of three diodes respectively, and the cathodes of the three diodes are connected together and then connected to the enable terminal EN1 of the power management module 21.
  • the above three types of wake-up signals jointly control the opening and closing of the power management module 21. break.
  • the second wake-up circuit 62 includes: CAN wake-up signals 2 to n, Ethernet wake-up signals 1 to n, real-time clock (Real-Time Clock, RTC) scheduled wake-up signal, and online diagnosis (On-Board Diagnostic, OBD) wake-up signal.
  • the four types of wake-up signals are respectively connected to WKUP IO[1 ⁇ n] of the main control processing unit 322 to realize the wake-up of the main control processing unit 322.
  • the power management module 21 receives the wake-up signal (KL15, braking signal, CAN wake-up signal 1), and the microprocessor module 22 starts normally.
  • the microprocessor module 22 identifies the wake-up source and the wake-up scenario.
  • the microprocessor module 22 determines whether it needs to wake up the main control processing module 32. If it needs to wake up, it wakes up the main control processing module 32 through the control signal a3.
  • the main control processing module 32 starts normally; similarly, the microprocessor module 22 determines whether it needs to wake up the driving control processing module 42.
  • the microprocessor module 22 determines whether the parking control processing module 52 needs to be awakened. If it needs to be awakened, the The control signal a1 wakes up the parking control processing module 52, and the parking control processing module 52 starts normally.
  • the main control processing module 32 when the entire vehicle control domain controller is in a sleep state, the main control processing module 32 receives the wake-up signal (OBD Activeline, CAN wake-up signal 2 ⁇ n, Ethernet wake-up signal 1 ⁇ n, RTC Timing wake-up signal), the main control processing module 32 wakes up the power management unit 321 through the control signal b3.
  • the main control processing module 32 identifies the wake-up source and the wake-up scenario.
  • the main control processing module 32 determines whether the microprocessor module 22 needs to be woken up.
  • the microprocessor module 22 is awakened through the control signal b3, and the microprocessor module 22 starts normally; similarly, the main control processing module 32 determines whether it needs to wake up the driving control processing module 42, and if it needs to be woken up, it wakes up the driving through the control signal b1
  • the control processing module 42 and the driving control processing module 42 start normally; similarly, the main control processing module 32 determines whether the parking control processing module 52 needs to be awakened. If it needs to be awakened, the parking control processing module 52 is awakened through the control signal b2.
  • the vehicle control processing module 52 starts normally.
  • the solution supports different wake-up scene recognition. If a simple wake-up scene only requires a single processor module to process, only the relevant processing module will be powered on normally, for example, the microprocessor module 22 will be powered on alone. Or when the main control processing module 32 is powered on and works alone, the controller power supply system works in a low power consumption mode; this solution also supports complex wake-up scenarios and multiple processor modules working together to achieve more complex work scenario processing Function. This solution purposefully controls the power supply of each processor unit, realizes the functions required by multiple wake-up scenarios, and can flexibly control the power consumption of the entire integrated vehicle control domain controller.
  • the controller power supply system proposed in the embodiment of the present application includes a power input circuit, a microprocessor circuit, a main control processing circuit, a driving processing circuit, a wake-up circuit and a parking processing circuit; wherein the power input circuit includes: a first power input circuit and a third Two power input circuits; the first power input circuit and the second power input circuit back up each other and jointly provide power for the microprocessor circuit, the main control processing circuit, the driving processing circuit and the parking processing circuit.
  • the other power input circuit can continue to provide power to the system, thus ensuring the independence of power supply between different processing domains within the high-performance processor chip and enabling flexible activation of low-power modes.
  • the controller power supply system proposed in the embodiment of this application can support the redundant power supply of dual power supplies, realize the isolation of the two power supplies, and has the ability to diagnose and diagnose overvoltage, undervoltage, overcurrent, and overtemperature of the two power supplies.
  • the protection function when the MCU domain is used as the security monitoring of the system, can improve the functional safety level of the system; moreover, the technical solution of the embodiment of the present application is simple and convenient to implement, easy to popularize, and has a wider scope of application.
  • FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 8 shows a diagram suitable for A block diagram of an exemplary electronic device implementing embodiments of the present application.
  • the electronic device 12 shown in FIG. 8 is only an example and should not bring any limitations to the functions and scope of use of the embodiments of the present application.
  • electronic device 12 is embodied in the form of a general computing device.
  • Components of electronic device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 connecting various system components (including system memory 28 and processing unit 16).
  • Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics accelerated port, a processor, or a local bus using any of a variety of bus structures.
  • these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA bus, Video Electronics Standards Association (Video Electronics Standards) Association, VESA) local bus and Peripheral Component Interconnect (PCI) bus.
  • Electronic device 12 includes a variety of computer system readable media. These media can be any available media that can be accessed by electronic device 12, including volatile and nonvolatile media, removable and non-removable media.
  • System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32.
  • Electronic device 12 may include other removable/non-removable, volatile/non-volatile computer system storage media.
  • storage system 34 may be configured to read and write to non-removable, non-volatile magnetic media (not shown in Figure 8, commonly referred to as a "hard drive”).
  • a disk drive for reading and writing to a removable non-volatile disk (such as a "floppy disk") and a removable non-volatile optical disk (such as a Portable Compact Disk Read-Only Memory) may be provided.
  • each drive may be connected to bus 18 through one or more data media interfaces.
  • the memory 28 may include at least one program product having a set (eg, at least one) of program modules configured to perform the functions of embodiments of the present application.
  • a program/utility 40 having a set of (at least one) program modules 42 may be stored, for example, in memory 28 , each or a combination of these examples may include the implementation of a network environment.
  • Program modules 42 generally perform functions and/or methods in the embodiments described herein.
  • Electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.) and with one or more devices that enable a user to interact with electronic device 12 communicate, and/or communicate with any device (eg, network card, modem, etc.) that enables the electronic device 12 to communicate with one or more other computing devices. This communication may occur through an input/output (I/O) interface 22 .
  • the electronic device 12 may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN) and/or a public network such as the Internet) through the network adapter 20 . As shown, network adapter 20 communicates with other modules of electronic device 12 via bus 18 . It should be understood that, although not shown in FIG.
  • the processing unit 16 executes programs stored in the system memory 28 to perform various functional applications and data processing, for example, implementing the controller power supply system provided by the embodiment of the present application.
  • An embodiment of the present application provides a computer storage medium.
  • the computer-readable storage medium in the embodiment of the present application may be any combination of one or more computer-readable media.
  • the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.
  • the computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination thereof.
  • Computer-readable storage media may include (a non-exhaustive list): an electrical connection having one or more wires, a portable computer disk, a hard drive, RAM, read-only memory (ROM), erasable programmable Read-only memory (Electrically Erasable Programmable Read-Only Memory, EPROM) or flash memory, optical fiber, CD-ROM, optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying computer-readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can be sent, propagated, or transmitted for use by or in connection with an instruction execution system, apparatus, or device. A program for use with a device or device.
  • Program code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wire, optical cable, radio frequency (Radio Frequency, RF), etc., or the above Any suitable combination.
  • any appropriate medium including but not limited to wireless, wire, optical cable, radio frequency (Radio Frequency, RF), etc., or the above Any suitable combination.
  • Computer program code for performing the operations of the present application may be written in one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programs. Design language—such as "C” or a similar programming language.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer may be connected to the user computer through any kind of network, including a LAN or WAN, or may be connected to an external computer (eg, through the Internet using an Internet service provider).

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Abstract

一种控制器供电系统、电子设备及存储介质；该系统包括：电源输入电路(10)、微处理器电路(20)、主控处理电路(30)、行车处理电路(40)、唤醒电路(60)和泊车处理电路(50)；其中，电源输入电路(10)包括第一电源输入电路(11)和第二电源输入电路(12)；第一电源输入电路(11)和第二电源输入电路(12)共同设置为为上述其他电路提供供电a；唤醒电路(60)设置为为微处理器电路(20)提供控制信号e1和为主控处理电路(30)提供唤醒信号；微处理器电路(20)设置为基于控制信号e1为泊车处理电路(50)提供控制信号a1，为行车处理电路(40)提供控制信号a2和为主控处理电路(30)提供控制信号a3；主控处理电路(30)设置为基于唤醒信号为行车处理电路(40)提供控制信号b1，为泊车处理电路(50)提供控制信号b2和为微处理器电路(20)提供控制信号b3，使得行车处理电路(40)在b1和a2的控制下正常工作，以及使得泊车处理电路50在a1和b2的控制下正常工作。

Description

控制器供电系统、电子设备及存储介质
本申请要求在2022年06月29日提交中国专利局、申请号为202210763736.9的中国专利申请的优先权，以上申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及汽车供电技术领域，例如涉及一种控制器供电系统、电子设备及存储介质。
背景技术
随着汽车向智能方向的不断发展，智能驾驶、智能升级、智能交互、智能诊断等对数据的处理速度及处理量要求越来越高，传统的分布式电子电气架构已经无法满足需求。新的集中式的域控制器正在代替以前的多个分布式的电子控制器(electronic Control Unit，ECU)，其中，车控域控制器就是新电子电气架构中的中心处理单元。
相关技术中的车控域控制器中通常包含一个高性能处理单元和一个微处理器单元，用来实现车辆控制、整车功能以及管理等功能，高性能处理单元的供电通常使用一片电源管理芯片和多个分立电源芯片来提供多路供电和供电时序管理，微处理器单元通常使用一片电源管理芯片或者多个分立电源芯片来提供多路供电和供电时序管理。
发明内容
本申请提供一种控制器供电系统、电子设备及存储介质，可以支持两路电源的冗余供电，且实现两路电源的隔离，并具备对两路电源的过压、欠压、过流、过温的诊断与保护功能，当微控制器单元(Microcontroller Unit，MCU)域作为控制器供电系统的安全监控时，能够提高控制器供电系统的功能安全等级。
本申请实施例提供了一种控制器供电系统，所述系统包括：电源输入电路10、微处理器电路20、主控处理电路30、行车处理电路40、唤醒电路60和泊车处理电路50；
其中，电源输入电路10，包括：第一电源输入电路11和第二电源输入电路12；第一电源输入电路11和第二电源输入电路12互为备份，共同设置为为微处理器电路20、主控处理电路30、行车处理电路40和泊车处理电路50提供供电a；
唤醒电路60，设置为为微处理器电路20提供控制信号e1和为主控处理电 路30提供唤醒信号；
微处理器电路20，设置为基于控制信号e1为泊车处理电路50提供控制信号a1，为行车处理电路40提供控制信号a2和为主控处理电路30提供控制信号a3；
主控处理电路30，设置为基于唤醒信号为行车处理电路40提供控制信号b1，为泊车处理电路50提供控制信号b2和为微处理器电路20提供控制信号b3，使得行车处理电路40在控制信号b1和控制信号a2的控制下正常工作，以及使得泊车处理电路50在控制信号a1和控制信号b2的控制下正常工作。
本申请实施例提供了一种电子设备，包括：
一个或多个处理器；
存储器，设置为存储一个或多个程序；
当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现本申请任意实施例所述的控制器供电系统。
本申请实施例提供了一种存储介质，其上存储有计算机程序，该程序被处理器执行时实现本申请任意实施例所述的控制器供电系统。
附图说明
图1为本申请实施例提供的控制器供电系统的第一结构示意图；
图2为本申请实施例提供的控制器供电系统的第二结构示意图；
图3为本申请实施例提供的电源输入电路的结构示意图；
图4为本申请实施例提供的主控处理模块的结构示意图；
图5为本申请实施例提供的行车控制处理模块的结构示意图；
图6为本申请实施例提供的泊车控制处理模块的结构示意图；
图7为本申请实施例提供的唤醒电路的结构示意图；
图8为本申请实施例提供的电子设备的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作说明。
实施例一
图1为本申请实施例提供的控制器供电系统的第一结构示意图，该系统可以由电子设备来执行，该电子设备可以由软件和/或硬件的方式实现，该电子设 备可以集成在任何具有网络通信功能的智能设备中。如图1所示，控制器供电系统可以包括：电源输入电路10、微处理器电路20、主控处理电路30、行车处理电路40、唤醒电路60和泊车处理电路50。
电源输入电路10，包括：第一电源输入电路11和第二电源输入电路12；第一电源输入电路10和第二电源输入电路12互为备份，设置为为微处理器电路20、主控处理电路30、行车处理电路40和泊车处理电路50提供供电a；唤醒电路60，设置为为微处理器电路20提供控制信号e1和为主控处理电路30提供唤醒信号；微处理器电路20，设置为基于控制信号e1为泊车处理电路50提供控制信号a1，为行车处理电路40提供控制信号a2和为主控处理电路30提供控制信号a3；主控处理电路30，设置为基于唤醒信号为行车处理电路40提供控制信号b1，为泊车处理电路50提供控制信号b2和为微处理器电路20提供控制信号b3，使得行车处理电路40在控制信号b1和控制信号a2的控制下正常工作，以及使得泊车处理电路50在控制信号a1和控制信号b2的控制下正常工作。
本申请实施例可以支持双路电源的冗余供电，且实现两路电源的隔离，并具备对两路电源的过压、欠压、过流、过温的诊断与保护功能；本申请实施例可以保证高性能处理器芯片内部的不同处理域之间供电的独立性，可灵活启用低功耗模式，在不需要中央处理器(Central Processing Unit，CPU)域操作时可显著降低系统功耗，可提高系统鲁棒性，可避免受MCU域和CPU域子系统的单点故障的干扰，当MCU域作为系统的安全监控时可以提高系统的功能安全等级。本申请实施例可以为多个高性能处理器芯片供电，且方案具有可扩展性，可在此供电拓扑基础上增加数个高性能处理模块；本申请实施例可以支持唤醒场景识别，有目的性的控制每个处理器单元的供电，能够灵活地控制整个融合车控域控制器的功耗。
本申请实施例提出的控制器供电系统包括电源输入电路、微处理器电路、主控处理电路、行车处理电路、唤醒电路和泊车处理电路；其中，电源输入电路包括：第一电源输入电路和第二电源输入电路；第一电源输入电路和第二电源输入电路互为备份，共同为微处理器电路、主控处理电路、行车处理电路和泊车处理电路提供供电。当一个电源输入电路发生故障时，另外一个电源输入电路可以继续为该系统提供供电，从而可以保证高性能处理器芯片内部的不同处理域之间供电的独立性，可灵活启用低功耗模式，可提高系统的鲁棒性，可避免受MCU域和CPU域子系统的单点故障的干扰，当MCU域作为系统的安全监控时可以提高系统的功能安全等级。本申请实施例提出的控制器供电系统，可以支持双路电源的冗余供电，且实现两路电源的隔离，并具备对两路电源的过压、欠压、过流、过温的诊断与保护功能，当MCU域作为系统的安全监控时，能够提高系统的功能安全等级，并且，本申请实施例的技术方案实现简单方便、 便于普及，适用范围更广。
实施例二
图2为本申请实施例提供的控制器供电系统的第二结构示意图。如图2所示，控制器供电系统可以包括：电源输入电路10、电源管理模块21、微处理器模块22、直流电压转换电路31、主控处理模块32、直流电压转换电路41、行车控制处理模块42、直流电压转换电路51、泊车控制处理模块52、唤醒电路60。
电源输入电路10包括第一电源输入电路11和第二电源输入电路12，共同为系统提供供电a，并提供第一监控信号A和第二监控信号B给主控处理模块32。电源管理模块21，将来自电源输入电路10的供电a转换成微处理器模块22需要的供电b，并与微处理器模块22之间通过不同的监控信号互相监控，电源管理模块21的控制信号e1来自唤醒电路60中的第一唤醒电路61。
微处理器模块22，供电来自于电源管理模块21的输出供电b，并与电源管理模块21之间通过不同的监控信号互相监控，微处理器模块22提供控制信号a1，与主控处理模块32提供的控制信号b2共同控制直流电压转换电路51。微处理器模块22提供控制信号a2，与主控处理模块32提供的控制信号b1共同控制直流电压转换电路41，微处理器模块22还提供控制信号a3控制主控处理模块32。
直流电压转换电路31，将来自电源输入电路10的供电a转换成主控处理模块32需要的供电c，并提供控制信号e2以控制主控处理模块32。
主控处理模块32，供电来自于直流电压转换电路31的输出供电c，主控处理模块32的控制信号e2来自直流电压转换电路31，主控处理模块32提供控制信号b2，与微处理器模块22提供的控制信号a1共同控制直流电压转换电路51，主控处理模块32提供的控制信号b1，与微处理器模块22提供的控制信号a2共同控制直流电压转换电路41，主控处理模块32通过第一监控信号A和第二监控信号B监控电源输入电路10，主控处理模块32的唤醒信号来自唤醒电路60中的第二唤醒电路62。
直流电压转换电路41，将来自电源输入电路10的供电a转换成行车控制处理模块42需要的供电d，并为行车控制处理模块42提供控制信号c，直流电压转换电路41的控制信号f1来自微处理器模块22的控制信号a2和主控处理模块32的控制信号b1经过或门处理电路1后的输出。
行车控制处理模块42，供电来自于直流电压转换电路41的输出供电d，行 车控制处理模块42的控制信号c来自直流电压转换电路41。
直流电压转换电路51，将来自电源输入电路10的供电a转换成泊车控制处理模块52需要的供电e，并为泊车控制处理模块52提供控制信号d，直流电压转换电路51的控制信号f2来自微处理器模块22的控制信号a1和主控处理模块32的控制信号b2经过或门处理电路2后的输出。
泊车控制处理模块52，供电来自于直流电压转换电路51的输出供电e，泊车控制处理模块52的控制信号d来自直流电压转换电路51。
唤醒电路60包括第一唤醒电路61和第二唤醒电路62，其中第一唤醒电路61为电源管理模块21提供控制信号e1，第二唤醒电路62为主控处理模块32提供唤醒信号。
本申请实施例提出的控制器供电系统，该系统包括电源输入电路、微处理器电路、主控处理电路、行车处理电路、唤醒电路和泊车处理电路；其中，电源输入电路包括：第一电源输入电路和第二电源输入电路；第一电源输入电路和第二电源输入电路互为备份，共同为微处理器电路、主控处理电路、行车处理电路和泊车处理电路提供供电。当一个电源输入电路发生故障时，另外一个电源输入电路可以继续为该系统提供供电，从而可以保证高性能处理器芯片内部的不同处理域之间供电的独立性，可灵活启用低功耗模式，可提高系统的鲁棒性，可避免受MCU域和CPU域子系统的单点故障的干扰，当MCU域作为系统的安全监控时可以提高系统的功能安全等级。本申请实施例提出的控制器供电系统，可以支持双路电源的冗余供电，且实现两路电源的隔离，并具备对两路电源的过压、欠压、过流、过温的诊断与保护功能，当MCU域作为系统的安全监控时，能够提高系统的功能安全等级；并且，本申请实施例的技术方案实现简单方便、便于普及，适用范围更广。
实施例三
图3为本申请实施例提供的电源输入电路的结构示意图。如图3所示，两路电源输入(第一蓄电池和第二蓄电池)，分别经过第一电源输入电路11和第二电源输入电路12的处理之后，合成一路供电a，为系统供电。本申请实施例为双路电源冗余供电且实现两路电源隔离，并对两路电源的欠压、过压、过流、过温进行诊断与保护。第一电源输入电路AA可以包括：第一电源隔离芯片111、第一N沟道金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)管组和第一电流采样电阻R。第一N沟道MOSFET管组包括：N沟道MOSFET管(Qa1)和N沟道MOSFET管(Qa2)。 第二电源输入电路AB可以包括：第二电源隔离芯片211、第二N沟道MOSFET管组和第二电流采样电阻R2。第二N沟道MOSFET管组包括：N沟道MOSFET管(Qb1)和N沟道MOSFET管(Qb2)。
在正常工作状态下，第一电源隔离芯片111的门极驱动控制MOSFET管Qa1、Qa2处于导通状态，同样地，第二电源隔离芯片211的门极驱动控制MOSFET管Qb1、Qb2处于导通状态，第一蓄电池和第二蓄电池的电压分别正常传输到Vout_A和Vout_B，保证后端电源芯片正常工作，且两路电源互为备份。当其中一路蓄电池欠压时，例如第一蓄电池一路的第一电源隔离芯片111监控到第一蓄电池的电压低于设置好的欠压关断阈值，则在1us内自动关闭第一电源隔离芯片111的门极驱动，并通过置低第一电源隔离芯片111的引脚FAULT的电位进行故障反馈，即通过引脚FAULT通知主控处理电路30该欠压故障。此时因第二蓄电池的正常电压能够维持Vout_B正常输出供电a。
当一路蓄电池过压时，例如第一蓄电池一路的第一电源隔离芯片111监控到第一蓄电池的电压高于设置好的过压关断阈值，则在1us内自动关闭第一电源隔离芯片111的门极驱动，并通过置低第一电源隔离芯片111的引脚FAULT的电位进行故障反馈，即通过引脚FAULT通知主控处理电路30该过压故障。此时因第二蓄电池的正常电压能够维持Vout_B正常输出供电a。
当一路蓄电池过流时，例如过流一路的电源隔离芯片111监控到电流采样电阻R1上的电流大于设置好的阈值，则在1us内自动关闭第一电源隔离芯片111的门极驱动，并通过置低第一电源隔离芯片111的引脚FAULT的电位进行故障反馈，即通过引脚FAULT通知主控处理电路30该过流故障；当一路的电源隔离芯片，例如第一电源隔离芯片111监控到本身温度高于温度阈值时，自动关闭第一电源隔离芯片111的门极驱动，并通过置低第一电源隔离芯片111的引脚FAULT的电位进行故障反馈，即通过引脚FAULT通知主控处理电路30该过温故障。
在上述实施例中，第一电源输入电路11和第二电源输入电路12均能独立监控本身的欠压、过压、过流、过温故障，且能及时关断驱动，从而实现保护电源的功能，两路电源不仅独立工作，且当一路电源因故障关断时，并不影响后端电源芯片的正常工作，实现了双路电源隔离的同时也能冗余供电。
第一电源输入电路11，还设置为通过第一电源隔离芯片111为主控处理电路30提供第一监控信号；第二电源输入电路12，还设置为通过第二电源隔离芯片211为主控处理电路30提供第二监控信号。
图4为本申请实施例提供的主控处理模块的结构示意图。如图4所示，主 控处理模块32可以包括：电源管理单元321和主控处理单元322；其中，电源管理单元321包括：第一电源管理芯片r1、第二电源管理芯片r2、第一直流电压转换芯片r3和第二直流电压转换芯片r4。第一电源管理芯片r1为主控处理单元322中的MCU域微处理单元域3221提供多路电源供电f1-fn及多路电源的时序管理；第二电源管理芯片r2为主控处理单元322中的CPU域计算处理单元域3222提供多路电源供电g1-gn及多路电源的时序管理；第一直流电压转换芯片r3和第二直流电压转换芯片r4分别为主控处理单元322中的WKUP域唤醒处理单元域3223C223提供电源供电h1和h2.第一电源管理芯片r1为第二电源管理芯片r2、第一直流电压转换芯片r3、第二直流电压转换芯片r4分别提供控制信号b6、b4、b5，控制上述三个芯片的打开和关断。本申请实施例可实现主控处理单元322中不同处理单元域的独立供电和时序管理。上电时，电源管理单元321为主控处理单元322提供所需的多路供电f1-fn、g1-gn、h1、h2，第一电源管理芯片r1通过自身的设置以及控制信号b6、b4、b5管理供电f1-fn、g1-gn、h1、h2的时序，保证主控处理单元322能够正确地上下电并正常工作。若需要低功耗模式，可以通过控制信号b6关断第二电源管理芯片r2的供电输出，此时主控处理单元322中的CPU域计算处理单元域3222不工作，大大降低主控处理单元322的功耗，同时不影响MCU域的正常工作。MCU域和CPU域完全独立，也可提高系统的功能安全等级。
本申请实施例可以保证高性能处理器芯片内部不同处理域之间供电的独立性，可灵活启用低功耗模式(即不需要CPU域操作时通过关断CPU域可显著降低功耗)，可提高系统鲁棒性，可避免受MCU域和CPU域子系统的单点故障的干扰，当MCU域作为系统的安全监控时可以提高系统的功能安全等级。
图5为本申请实施例提供的行车控制处理模块的结构示意图。如图5所示，行车控制处理模块42包括：电源管理单元421和行车控制处理单元422，其中，电源管理单元421包括：第三电源管理芯片t1、第四电源管理芯片t2、第三直流电压转换芯片t3，第三电源管理芯片t1为行车控制处理单元422中的MCU域微处理单元域42211提供多路电源供电i1-in及多路电源的时序管理；第四电源管理芯片t2为行车控制处理单元422中的CPU域计算处理单元域42221提供多路电源供电j1-jn及多路电源的时序管理；第三直流电压转换芯片t3为视频编解码电路4222提供电源供电k。第三电源管理芯片t1为第四电源管理芯片t2提供控制信号c1，行车控制处理单元422为第三直流电压转换芯片b3提供控制信号c2，以分别控制第四电源管理芯片t2和第三直流电压转换芯片t3的打开和关断。本申请实施例可实现行车控制处理芯片4221中不同处理单元域的独立供电和时序管理。上电时，电源管理单元421为行车控制处理单元422提供所需的多路供电i1-in、j1-jn、k，第三电源管理芯片t1通过自身的设置以及控制信号 c1，管理供电i1-in、j1-jn的时序，行车控制处理单元422通过控制信号c2控制供电k的时序，共同保证行车控制处理单元422能够正确地上下电并正常工作。
图6为本申请实施例提供的泊车控制处理模块的结构示意图。如图6所示，泊车控制处理模块52包括：电源管理单元521和泊车控制处理单元522，其中，电源管理单元521包括：第五电源管理芯片y1、第六电源管理芯片y2和第四直流电压转换芯片y3。第五电源管理芯片y1为泊车控制处理单元522中的MCU域微处理单元域52211提供多路电源供电l1-ln及多路电源的时序管理，第六电源管理芯片y2为泊车控制处理单元522中的CPU域计算处理单元域52212提供多路电源供电m1-mn及多路电源的时序管理，第四直流电压转换芯片y3为视频编解码电路5222提供电源供电n。第五电源管理芯片y1为第六电源管理芯片y2提供控制信号d1、泊车控制处理单元522为第四直流电压转换芯片y3提供控制信号d2，以分别控制第六电源管理芯片y2和第四直流电压转换芯片y3的打开和关断。本申请实施例可实现泊车控制处理芯片5221中不同处理单元域的独立供电和时序管理。上电时，电源管理单元521为泊车控制处理单元522提供所需的多路供电l1-ln、m1-mn、n，第五电源管理芯片y1通过自身的设置以及控制信号d1，管理供电l1-ln、m1-mn的时序，泊车控制处理单元522通过控制信号d2控制供电n的时序，共同保证泊车控制处理单元522能够正确地上下电并正常工作。
图7为本申请实施例提供的唤醒电路的结构示意图。如图7所示，唤醒电路60包括第一唤醒电路61和第二唤醒电路62，第一唤醒电路61包括：钥匙门KL15唤醒信号、制动信号、控制器局域网络(Controller Area Network，CAN)唤醒信号1，以上信号分别连接三个二极管的阳极，三个二极管的阴极连接在一起后连接到电源管理模块21的使能端EN1，以上三类唤醒信号共同控制电源管理模块21的开启和关断。第二唤醒电路62包括：CAN唤醒信号2～n、以太网唤醒信号1～n、实时时钟(Real-Time Clock，RTC)定时唤醒信号、在线诊断(On-Board Diagnostic，OBD)唤醒信号，这四类唤醒信号分别连接到主控处理单元322的WKUP IO[1～n]上，以实现对主控处理单元322的唤醒。
在本申请的具体实施例中，当整个车控域控制器处于休眠状态时，电源管理模块21接收到唤醒信号(KL15、制动信号、CAN唤醒信号1)，微处理器模块22正常启动，完成初始化，微处理器模块22识别唤醒源和唤醒场景，微处理器模块22判断是否需要唤醒主控处理模块32，如果需要唤醒，则通过控制信号a3唤醒主控处理模块32，主控处理模块32正常启动；同样地，微处理器模块22判断是否需要唤醒行车控制处理模块42，如果需要唤醒，则通过控制信号a2唤醒行车控制处理模块42，行车控制处理模块42正常启动；同样的，微处理器模块22判断是否需要唤醒泊车控制处理模块52，如果需要唤醒，则通过 控制信号a1唤醒泊车控制处理模块52，泊车控制处理模块52正常启动。
在本申请的具体实施例中，当整个车控域控制器处于休眠状态时，主控处理模块32接收到唤醒信号(OBD Activeline、CAN唤醒信号2～n、以太网唤醒信号1～n、RTC定时唤醒信号)，主控处理模块32通过控制信号b3唤醒电源管理单元321，主控处理模块32识别唤醒源和唤醒场景，主控处理模块32判断是否需要唤醒微处理器模块22，如果需要唤醒，则通过控制信号b3唤醒微处理器模块22，微处理器模块22正常启动；同样地，主控处理模块32判断是否需要唤醒行车控制处理模块42，如果需要唤醒，则通过控制信号b1唤醒行车控制处理模块42，行车控制处理模块42正常启动；同样的，主控处理模块32判断是否需要唤醒泊车控制处理模块52，如果需要唤醒，则通过控制信号b2唤醒泊车控制处理模块52，泊车控制处理模块52正常启动。
上述实施例中，该方案支持不同的唤醒场景识别，若个别简单的唤醒场景只需要单个处理器模块进行处理，则只有相关的处理模块正常上电工作，例如微处理器模块22单独上电工作或主控处理模块32单独上电工作时，控制器供电系统工作于低功耗模式；该方案也支持复杂的唤醒场景，多个处理器模块协同工作的情况，以实现更复杂的工作场景处理功能。该方案有目的性的控制每个处理器单元的供电，实现了多个唤醒场景要求的功能，能灵活控制整个融合车控域控制器的功耗。
本申请实施例提出的控制器供电系统包括电源输入电路、微处理器电路、主控处理电路、行车处理电路、唤醒电路和泊车处理电路；其中，电源输入电路包括：第一电源输入电路和第二电源输入电路；第一电源输入电路和第二电源输入电路互为备份，共同为微处理器电路、主控处理电路、行车处理电路和泊车处理电路提供供电。当一个电源输入电路发生故障时，另外一个电源输入电路可以继续为该系统提供供电，从而可以保证高性能处理器芯片内部的不同处理域之间供电的独立性，可灵活启用低功耗模式，可提高系统鲁棒性，可避免受MCU域和CPU域子系统的单点故障的干扰，当MCU域作为系统的安全监控时可以提高系统的功能安全等级。本申请实施例提出的控制器供电系统，可以支持双路电源的冗余供电，且实现两路电源的隔离，并具备对两路电源的过压、欠压、过流、过温的诊断与保护功能，当MCU域作为系统的安全监控时，能够提高系统的功能安全等级；并且，本申请实施例的技术方案实现简单方便、便于普及，适用范围更广。
实施例四
图8为本申请实施例提供的电子设备的结构示意图。图8示出了适于用来 实现本申请实施方式的示例性电子设备的框图。图8显示的电子设备12仅仅是一个示例，不应对本申请实施例的功能和使用范围带来任何限制。
如图8所示，电子设备12以通用计算设备的形式表现。电子设备12的组件可以包括但不限于：一个或者多个处理器或者处理单元16，系统存储器28，连接不同系统组件(包括系统存储器28和处理单元16)的总线18。
总线18表示几类总线结构中的一种或多种，包括存储器总线或者存储器控制器，外围总线，图形加速端口，处理器或者使用多种总线结构中的任意总线结构的局域总线。举例来说，这些体系结构包括但不限于工业标准体系结构(Industry Standard Architecture，ISA)总线，微通道体系结构(Micro Channel Architecture，MCA)总线，增强型ISA总线、视频电子标准协会(Video Electronics Standards Association,VESA)局域总线以及外围组件互连(Peripheral Component Interconnect，PCI)总线。
电子设备12包括多种计算机系统可读介质。这些介质可以是任何能够被电子设备12访问的可用介质，包括易失性和非易失性介质，可移动的和不可移动的介质。
系统存储器28可以包括易失性存储器形式的计算机系统可读介质，例如随机存取存储器(Random Access Memory，RAM)30和/或高速缓存存储器32。电子设备12可以包括其它可移动/不可移动的、易失性/非易失性计算机系统存储介质。仅作为举例，存储系统34可以设置为读写不可移动的、非易失性磁介质(图8未显示，通常称为“硬盘驱动器”)。尽管图8中未示出，可以提供用于对可移动非易失性磁盘(例如“软盘”)读写的磁盘驱动器，以及对可移动非易失性光盘(例如便携式紧凑磁盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)，高密度数字视频光盘只读存储器(Digital Video Disc Read-Only Memory，DVD-ROM)或者其它光介质)读写的光盘驱动器。在这些情况下，每个驱动器可以通过一个或者多个数据介质接口与总线18相连。存储器28可以包括至少一个程序产品，该程序产品具有一组(例如至少一个)程序模块，这些程序模块被配置以执行本申请实施例的功能。
具有一组(至少一个)程序模块42的程序/实用工具40，可以存储在例如存储器28中，这样的程序模块42包括但不限于操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或一种组合中可能包括网络环境的实现。程序模块42通常执行本申请所描述的实施例中的功能和/或方法。
电子设备12也可以与一个或多个外部设备14(例如键盘、指向设备、显示器24等)通信，还可与一个或者多个使得用户能与该电子设备12交互的设备 通信，和/或与使得该电子设备12能与一个或多个其它计算设备进行通信的任何设备(例如网卡，调制解调器等等)通信。这种通信可以通过输入/输出(Input/Output，I/O)接口22进行。并且，电子设备12还可以通过网络适配器20与一个或者多个网络(例如局域网(Local Area Network，LAN)，广域网(Wide Area Network，WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器20通过总线18与电子设备12的其它模块通信。应当明白，尽管图8中未示出，可以结合电子设备12使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、磁盘阵列(Redundant Arrays of Independent Disks，RAID)系统、磁带驱动器以及数据备份存储系统等。
处理单元16通过运行存储在系统存储器28中的程序，从而执行多种功能应用以及数据处理，例如实现本申请实施例所提供的控制器供电系统。
实施例五
本申请实施例提供了一种计算机存储介质。
本申请实施例的计算机可读存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质可以(非穷举的列表)包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、RAM、只读存储器(Read-Only Memory，ROM)、可擦式可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EPROM)或闪存、光纤、CD-ROM、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与指令执行系统、装置或者器件结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括——但不限于无线、电线、光缆、射频(Radio Frequency，RF)等等，或者上述的 任意合适的组合。
可以以一种或多种程序设计语言来编写用于执行本申请操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络——包括LAN或WAN—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。

Claims (10)

  1. 一种控制器供电系统，包括：电源输入电路(10)、微处理器电路(20)、主控处理电路(30)、行车处理电路(40)、唤醒电路(60)和泊车处理电路(50)；
    其中，电源输入电路(10)，包括：第一电源输入电路(11)和第二电源输入电路(12)；第一电源输入电路(11)和第二电源输入电路(12)互为备份，共同设置为为微处理器电路(20)、主控处理电路(30)、行车处理电路(40)和泊车处理电路(50)提供供电a；
    唤醒电路(60)，设置为为微处理器电路(20)提供控制信号e1和为主控处理电路(30)提供唤醒信号；
    微处理器电路(20)，设置为基于控制信号e1为泊车处理电路(50)提供控制信号a1，为行车处理电路(40)提供控制信号a2和为主控处理电路(30)提供控制信号a3；
    主控处理电路(30)，设置为基于唤醒信号为行车处理电路(40)提供控制信号b1，为泊车处理电路(50)提供控制信号b2和为微处理器电路(20)提供控制信号b3，使得行车处理电路(40)在控制信号b1和控制信号a2的控制下正常工作，以及使得泊车处理电路(50)在控制信号a1和控制信号b2的控制下正常工作。
  2. 根据权利要求1所述的系统，其中，第一电源输入电路(11)包括：第一电源隔离芯片(111)、第一N沟道金属-氧化物半导体场效应晶体管MOSFET管组和第一电流采样电阻R1；其中，第一N沟道MOSFET管组包括：N沟道MOSFET管(Qa1)和N沟道MOSFET管(Qa2)；
    第二电源输入电路(12)包括：第二电源隔离芯片(211)、第二N沟道MOSFET管组和第二电流采样电阻R2；其中，第二N沟道MOSFET管组包括：N沟道MOSFET管(Qb1)和N沟道MOSFET管(Qb2)。
  3. 根据权利要求1所述的系统，其中，第一电源输入电路(11)，还设置为通过第一电源隔离芯片(111)为主控处理电路(30)提供第一监控信号；
    第二电源输入电路(12)，还设置为通过第二电源隔离芯片(211)为主控处理电路(30)提供第二监控信号。
  4. 根据权利要求1所述的系统，其中，微处理器电路(20)包括：电源管理模块(21)和微处理器模块(22)；
    其中，电源管理模块(21)，设置为接收唤醒电路(60)发送的控制信号e1和主控处理电路(30)发送的控制信号b3，基于控制信号e1和控制信号b3 为微处理器模块(22)提供监控信号和供电b。
  5. 根据权利要求1所述的系统，其中，主控处理电路(30)包括：直流电压转换电路(31)和主控处理模块(32)；其中，主控处理模块(32)包括：电源管理单元(321)和主控处理单元(322)；电源管理单元(321)包括：第一电源管理芯片(r1)、第二电源管理芯片(r2)、第一直流电压转换芯片(r3)和第二直流电压转换芯片(r4)；主控处理单元(322)包括：微控制器单元MCU域微处理单元域(3221)、中央处理器CPU域计算处理单元域(3222)、WKUP域唤醒处理单元域(3223)；
    其中，第一电源管理芯片(r1)，设置为为MCU域微处理单元域(3221)提供N路供电，N为大于1的自然数；
    第二电源管理芯片(r2)，设置为为CPU域计算处理单元域(3222)提供N路供电，N为大于1的自然数；
    第一直流电压转换芯片(r3)和第二直流电压转换芯片(r4)分别设置为为WKUP域唤醒处理单元域(3223)提供一路供电。
  6. 根据权利要求1所述的系统，其中，行车处理电路(40)包括：直流电压转换电路(41)和行车控制处理模块(42)；行车控制处理模块(42)包括：电源管理单元(421)和行车控制处理单元(422)；其中，电源管理单元(421)包括：第三电源管理芯片(t1)、第四电源管理芯片(t2)和第三直流电压转换芯片(t3)；行车控制处理单元(422)包括：行车控制处理芯片(4221)和视频编解码电路(4222)；行车控制处理芯片(4221)包括：MCU域微处理单元域(42211)和CPU域计算处理单元域(42222)；
    第三电源管理芯片(t1)，设置为为MCU域微处理单元域(42211)提供N路供电，N为大于1的自然数；
    第四电源管理芯片(t2)，设置为为CPU域计算处理单元域(42222)提供N路供电，N为大于1的自然数；
    第三直流电压转换芯片(t3)，设置为为视频编解码电路(4222)提供一路供电。
  7. 根据权利要求1所述的系统，其中，泊车处理电路(50)包括：直流电压转换电路(51)和泊车控制处理模块(52)；泊车控制处理模块(52)包括：电源管理单元(521)和泊车控制处理单元(522)；电源管理模块(521)包括：第五电源管理芯片(y1)、第六电源管理芯片(y2)和第四直流电压转换芯片(y3)；泊车控制处理单元(522)包括：泊车控制处理芯片(5221)和视频编解码电路(5222)；泊车控制处理芯片(5221)包括：MCU域微处理单元域(52211) 和CPU域计算处理单元域(52212)；
    第五电源管理芯片(y1)，设置为为MCU域微处理单元域(52211)提供N路供电，N为大于1的自然数；
    第六电源管理芯片(y2)，设置为为CPU域计算处理单元域(52212)提供N路供电，N为大于1的自然数；
    第四直流电压转换芯片(y3)，设置为为视频编解码电路(5222)提供一路供电。
  8. 根据权利要求1所述的系统，其中，唤醒电路(60)包括：第一唤醒电路(61)和第二唤醒电路(62)；
    其中，第一唤醒电路(61)，设置为为微处理器电路(20)提供控制信号e1；
    第二唤醒电路(62)，设置为为主控处理电路(30)提供唤醒信号。
  9. 一种电子设备，包括：
    至少一个处理器；
    存储器，设置为存储至少一个程序；
    当所述至少一个程序被所述至少一个处理器执行，使得所述至少一个处理器实现如权利要求1至8中任一项所述的控制器供电系统。
  10. 一种存储介质，其上存储有计算机程序，该程序被处理器执行时实现如权利要求1至8中任一项所述的控制器供电系统。
PCT/CN2023/103798 2022-06-29 2023-06-29 控制器供电系统、电子设备及存储介质 WO2024002231A1 (zh)

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