WO2024002171A1 - Procédé et appareil de codage, et support de stockage - Google Patents

Procédé et appareil de codage, et support de stockage Download PDF

Info

Publication number
WO2024002171A1
WO2024002171A1 PCT/CN2023/103244 CN2023103244W WO2024002171A1 WO 2024002171 A1 WO2024002171 A1 WO 2024002171A1 CN 2023103244 W CN2023103244 W CN 2023103244W WO 2024002171 A1 WO2024002171 A1 WO 2024002171A1
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
constraint
ldpc
encoding
rate
Prior art date
Application number
PCT/CN2023/103244
Other languages
English (en)
Chinese (zh)
Inventor
金立强
刘敬泽
Original Assignee
大唐移动通信设备有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大唐移动通信设备有限公司 filed Critical 大唐移动通信设备有限公司
Publication of WO2024002171A1 publication Critical patent/WO2024002171A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]

Definitions

  • the present disclosure relates to the field of communication technology, and in particular, to an encoding method, device and storage medium.
  • the data channel of the 5th generation mobile communication (5G) New Radio (NR) Low Density Parity Check Code (LDPC) adopts spatially coupled low density parity check code (LDPC). Spatially Coupled Low Density Parity Check Code, SC-LDPC).
  • 5G New Radio
  • NR Low Density Parity Check Code
  • SC-LDPC Spatially Coupled Low Density Parity Check Code
  • SC-LDPC cannot meet the rate compatibility requirements and cannot support the Incremental Redundancy Hybrid Automatic Repeat Request (IR-HARQ) in the next generation of mobile communications systems.
  • IR-HARQ Incremental Redundancy Hybrid Automatic Repeat Request
  • Embodiments of the present disclosure provide an encoding method, device, and storage medium to solve the technical problem that SC-LDPC in the prior art cannot meet rate compatibility requirements.
  • an embodiment of the present disclosure provides an encoding method, including:
  • the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;
  • Encoding is performed based on the basis matrix.
  • encoding based on the basis matrix includes:
  • Rate matching is performed on the mother code codeword to determine the encoded codeword.
  • performing rate matching on the mother code codeword to determine the encoded codeword includes:
  • the method before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:
  • the cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;
  • the cyclic shift matrix is periodic.
  • the first constraint block of each coupling segment adopts a Raptor-like structure.
  • the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality
  • the adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality
  • embodiments of the present disclosure provide an electronic device, including a memory, a transceiver, and a processor;
  • Memory used to store computer programs
  • transceiver used to send and receive data under the control of the processor
  • processor used to read the computer program in the memory and perform the following operations:
  • the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;
  • Encoding is performed based on the basis matrix.
  • encoding based on the basis matrix includes:
  • Rate matching is performed on the mother code codeword to determine the encoded codeword.
  • performing rate matching on the mother code codeword to determine the encoded codeword includes:
  • the method before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:
  • the cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;
  • the cyclic shift matrix is periodic.
  • the first constraint block of each coupling segment adopts a Raptor-like structure.
  • the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality
  • the adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality
  • an encoding device including:
  • a generation module used to generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;
  • An encoding module used for encoding based on the base matrix.
  • the encoding module includes a first determining sub-module, a second determining sub-module, a third determining sub-module and a rate matching sub-module;
  • the first determination sub-module is used to determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix
  • the second determination sub-module is used to determine the verification constraint relationship according to the verification matrix
  • the third determination sub-module is used to determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;
  • the rate matching sub-module is used to perform rate matching on the mother code codeword to determine the encoding codeword.
  • the rate matching sub-module includes a writing unit and a reading unit
  • the writing unit is used to write the mother code codeword into a row of coded bits in each coupling segment into a circular buffer of the rate matcher;
  • the reading unit is configured to read required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched codewords.
  • the device further includes a determination module
  • the determination module is configured to determine the cyclic shift matrix based on a target criterion; the target criterion includes one or more of the following criteria;
  • the cyclic shift matrix is periodic.
  • the first constraint block of each coupling segment adopts a Raptor-like structure.
  • the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality
  • the adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality
  • embodiments of the present disclosure also provide a processor-readable storage medium that stores a computer program, and the computer program is used to cause the processor to execute the process described in the first aspect. encoding method.
  • embodiments of the present disclosure further provide a computer-readable storage medium storing a computer program, the computer program being used to cause the computer to execute the encoding method described in the first aspect. .
  • embodiments of the present disclosure also provide a communication device readable storage medium, the communication device readable storage medium stores a computer program, the computer program is used to cause the communication device to execute the above described first aspect encoding method.
  • embodiments of the present disclosure also provide a chip product-readable storage medium.
  • the chip product-readable storage medium stores a computer program.
  • the computer program is used to cause the chip product to execute the above-described first aspect. encoding method.
  • the encoding method, device and storage medium provided by the embodiments of the present disclosure are designed to include L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a base matrix of a rate-compatible structure.
  • the check matrix determined based on this base matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility. Require.
  • Figure 1 is a schematic diagram of the construction method of QC-LDPC check matrix
  • Figure 2 is a schematic diagram of the SC-LDPC check matrix
  • Figure 3 is a schematic diagram of the TB-SC-LDPC check matrix
  • Figure 4 is a schematic flowchart of an encoding method provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of the basis matrix of SC-LDPC provided by an embodiment of the present disclosure.
  • Figure 6 is one of the structural schematic diagrams of a constraint block provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of the basis matrix of TB-SC-LDPC provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the rate matching principle provided by an embodiment of the present disclosure.
  • Figure 9 is the second structural schematic diagram of a constraint block provided by an embodiment of the present disclosure.
  • Figure 10 is a third schematic structural diagram of a constraint block provided by an embodiment of the present disclosure.
  • Figure 11 is the fourth structural schematic diagram of a constraint block provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic structural diagram of an encoding device provided by an embodiment of the present disclosure.
  • LDPC is a type of linear block code that can approach the Shannon channel capacity.
  • the code is defined by an m ⁇ n binary check matrix H.
  • the data channel of 5G NR uses structured Quasi Cyclic Low Density Parity Check Code (QC-LDPC).
  • QC-LDPC Quasi Cyclic Low Density Parity Check Code
  • the granularity of information bits can reach 1 bit, and the code rate range covers 1/3 ⁇ 8/9.
  • the flexible coding parameters of NR LDPC can allow channel coding to better adapt to dynamic changes in the wireless communication environment and thereby improve spectral efficiency.
  • the structured QC-LDPC greatly reduces the hardware implementation complexity and algorithm complexity of the encoder and decoder. , and improve the parallelism of decoder decoding.
  • Figure 1 is a schematic diagram of the construction method of the QC-LDPC check matrix.
  • the check matrix H of QC-LDPC can be uniquely determined by the base matrix (Base Graph, BG) and the cyclic shift matrix PM.
  • Base Graph, BG Base Graph
  • PM cyclic shift matrix
  • NR LDPC coding Single-sided QC-LDPC is used, and each block is a Z ⁇ Z unit cyclic shift matrix Q(), or a Z ⁇ Z all-zero matrix.
  • FIG. 2 is a schematic diagram of the SC-LDPC check matrix.
  • the check matrix H of SC-LDPC has a strip structure on the diagonal.
  • the sub-matrix H The sizes of 1 , H 2 and H 3 are all m ⁇ n, the code length is n ⁇ L, and L is the number of coupling segments.
  • SC-LDPC code rate Compared to the code rate of LDPC There is a certain bit rate loss.
  • SC-LDPC code can also adopt a Quasi Cyclic (QC) structure: first design the BG of the spatial coupling structure, and then obtain the check matrix through hashing (Dispersion, a cyclic shift matrix filling method) H.
  • SC-LDPC is usually designed as a QC structure, and the basis matrix BG is regular (the number of 1s in each row is the same, and the number of 1s in each column is also the same). This structure cannot meet the rate compatibility requirements.
  • SC-LDPC can also achieve rate compatibility through hole punching, the decoding performance after hole punching is poor and cannot meet high-performance communication needs.
  • FIG. 3 is a schematic diagram of the TB-SC-LDPC check matrix.
  • the check matrix H of TB-SC-LDPC is usually full row rank, and the code rate satisfies Therefore there is no bitrate loss.
  • TB-SC-LDPC does not have a threshold saturation effect during decoding, and requires additional special design to indirectly trigger the threshold saturation effect to improve decoding performance.
  • the bits in some coupling segments can be shortened or the bits in some coupling segments can be mapped to
  • the more reliable bits of high-order modulation indirectly trigger the threshold saturation effect to achieve wave decoding.
  • TB-SC-LDPC is usually designed as a QC structure, BG is also regular, and lacks an effective rate-compatible encoding scheme.
  • the existing rate-compatible LDPC construction methods can be divided into the following two types:
  • Combination of shortening and puncturing first construct a low code rate LDPC mother code, encode the information bits by filling some known bits (the filling bits are not transmitted on the channel), and encode some bits in the mother code codeword Punching (some bits are not transmitted over the channel), thereby obtaining LDPC and QC-LDPC codes with a larger code rate range.
  • QC-LDPC has lower decoding parallelism, resulting in lower decoding throughput.
  • SC-LDPC and TB-SC-LDPC are usually designed as regular BGs or lack effective rate-compatible coding schemes, which are oriented to In the next generation of mobile communications, QC-LDPC, SC-LDPC and TB-SC-LDPC are unable to meet the rate compatibility requirements and support the Incremental Redundancy Hybrid Automatic Repeat Request (IR) in the next generation mobile communications system. -HARQ) requirements.
  • IR Incremental Redundancy Hybrid Automatic Repeat Request
  • the embodiment of the present disclosure designs a base matrix that includes L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a rate-compatible structure, so that the base matrix can be determined according to the base matrix.
  • the check matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility requirements.
  • FIG. 4 is a schematic flowchart of an encoding method provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides an encoding method
  • the execution subject may be a terminal, such as a mobile phone. It can also be network equipment, such as base stations, core networks, etc.
  • the method includes:
  • Step 401 Generate a base matrix of the spatially coupled low-density parity check code SC-LDPC; the base matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure, L is an integer greater than or equal to 2.
  • the BG of SC-LDPC is first divided into multiple coupling sections, and each coupling section is designed with a rate-compatible structure, that is, each coupling section contains at least two constraint blocks, and each constraint block All are rate compatible structures.
  • the coupling segment is composed of multiple columns of BG, and each coupling segment is a sub-matrix of BG.
  • the constraint block consists of multiple rows of the coupling segment, and each constraint block is a sub-matrix of the coupling segment.
  • the rate-compatible structure is a matrix containing lower triangular submatrices.
  • the structure of this base matrix is equivalent to a high code rate LDPC and many single check codes, and as the number of rows and columns of the extended matrix increases, an LDPC check matrix with an arbitrarily low code rate can be obtained. For example, first Construct a kernel matrix with a code rate of 8/9, and then gradually expand downward to obtain code rates of 7/8, 5/6, 3/4, 1/2, 2/5, 1/3, 1/4, 1/5 of the check matrix, thus ensuring that the rate compatibility/redundant incremental structure of the check matrix will not be destroyed after spatial coupling expansion.
  • the first constraint block A in the coupling section is used for recursive coding of SC-LDPC.
  • the constraint blocks (constraint block B, etc.) within the coupling section except the first constraint block A are used for syndrome calculation.
  • Figure 5 is a schematic structural diagram of the basis matrix of SC-LDPC provided by an embodiment of the present disclosure.
  • the BG of SC-LDPC includes 3 coupling segments.
  • the memory length of the prefix syndrome is 1, and each A coupling section contains two constraint blocks (constraint block A and constraint block B), and each constraint block is a rate-compatible structure.
  • Figure 6 is one of the structural schematic diagrams of the constraint block provided by the embodiment of the present disclosure.
  • the rate compatible structure provided by the embodiment of the present disclosure includes sub-matrix A, sub-matrix C, sub-matrix D and zero matrix.
  • submatrix D is a lower triangular matrix.
  • TB-SC-LDPC is a special SC-LDPC.
  • Figure 7 is a schematic structural diagram of the basis matrix of TB-SC-LDPC provided by the embodiment of the present disclosure. As shown in Figure 7, the BG of TB-SC-LDPC includes 3 Each coupling segment has a memory length of 1. Each coupling segment contains two constraint blocks (constraint block A and constraint block B). Each constraint block is a rate-compatible structure.
  • the memory length of the prefix syndrome indicates the number of constraint blocks before the origin (the first constraint block) of the submatrix formed by splicing at least two constraint blocks in each coupling segment in columns.
  • the memory length of the prefix syndrome is 1. Therefore, each coupling segment contains two constraint blocks.
  • the memory length is greater than 1, more constraint blocks may be included.
  • Step 402 Encode based on the base matrix.
  • encoding based on the basis matrix includes:
  • the check matrix of the SC-LDPC is determined according to the base matrix and a predetermined cyclic shift matrix.
  • the terminal or base station after determining the base matrix, the terminal or base station first performs a hash operation on the base matrix with the lifting factor Z to obtain the check matrix H of SC-LDPC, that is, determine the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix.
  • Check matrix H of LDPC After determining the base matrix, the terminal or base station first performs a hash operation on the base matrix with the lifting factor Z to obtain the check matrix H of SC-LDPC, that is, determine the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix.
  • Check matrix H of LDPC Check matrix H of LDPC.
  • the verification constraint relationship can be determined based on the verification matrix H.
  • H is the check matrix
  • x is the mother code codeword
  • the mother code codeword is determined according to the relationship between the bits to be transmitted and the check constraint.
  • Rate matching is performed on the mother code codeword to determine the encoded codeword.
  • the rate matcher performs rate matching on the mother code code word to obtain the final encoded code word.
  • the encoding method provided by the embodiment of the present disclosure is designed to include L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a base matrix of a rate-compatible structure, so that the base matrix can be determined according to the base matrix.
  • the check matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility requirements.
  • performing rate matching on the mother code codeword to determine the encoded codeword includes:
  • the mother code codeword is written into a circular buffer of the rate matcher according to the coded bits in each coupling section as one row.
  • Figure 8 is a schematic diagram of the rate matching principle provided by an embodiment of the present disclosure.
  • the terminal or base station sends the mother code word x into the rate matching in the "coupling section interleaving" method.
  • the shortened or punctured bits in each coupling segment are skipped directly and are not sent to the circular buffer.
  • the length of the code word after rate matching is determined according to the target code rate or the size of the allocated transmission resource block (RE), and the code word length is obtained from the buffer in a first-in, first-out manner. Read the required bits from the processor to obtain the coded code after rate matching. Code words.
  • the encoding method provided by the embodiment of the present disclosure is designed to include L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a base matrix of a rate-compatible structure, so that the base matrix can be determined according to the base matrix.
  • the check matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility requirements.
  • a screening step of the basis matrix is also included.
  • Search to obtain the optimal basis matrix that meets the structural requirements based on a certain criterion for example, select the optimal basis matrix based on the decoding threshold criterion.
  • the encoding method provided by the embodiments of the present disclosure further improves rate compatibility by screening the optimal basis matrix.
  • the method before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:
  • the cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;
  • the cycle before determining the check matrix, it is necessary to determine the cycle based on one or more criteria such as maximizing the girth of the check matrix, optimizing the ring distribution of the check matrix, and the cyclic differential family. Shift matrix PM.
  • a ring refers to a closed loop formed in the Tanner graph corresponding to the LDPC check matrix, and the length of the closed loop becomes the ring length.
  • the proportional distribution of ring lengths is the ring distribution. For example, 70% of the rings have a ring length of 8 and 30% of the rings have a ring length of 6.
  • the girth, or girth refers to the length of the shortest ring in the Tanner graph corresponding to the LDPC check matrix.
  • each base block contains k elements, t base block representation
  • CDF Cyclic Difference Family
  • the cyclic shift matrix is periodic.
  • the cyclic shift values corresponding to blocks A, B... are equal.
  • the encoding method provided by the embodiments of the present disclosure further reduces the storage overhead of the codec through a periodic cyclic shift matrix.
  • the first constraint block of each coupling segment adopts a Raptor-like structure.
  • the Raptor-like structure is a special rate-compatible structure.
  • the first constraint block A in the coupling section is used for recursive coding of SC-LDPC.
  • the high bit rate part of constraint block A needs to adopt a Raptor-like double diagonal structure to reduce coding complexity while ensuring high bit rate performance.
  • Figure 9 is a second structural schematic diagram of a constraint block provided by an embodiment of the present disclosure.
  • the Raptor-like structure provided by an embodiment of the present disclosure includes sub-matrix A, sub-matrix B, sub-matrix C, sub-matrix D and Zero matrix, where sub-matrix B is a bi-diagonal matrix and sub-matrix D is a single-diagonal matrix.
  • Constraint block A can be obtained based on the basis matrix of the existing designed Raptor-like structure.
  • constraint block A can use the basis matrix BG1 or BG2 of 5G NR LDPC.
  • constraint blocks (constraint block B, etc.) in the coupling section except the first constraint block A are used for syndrome calculation and do not involve coding calculation, so there is no need for a double-diagonal or single-diagonal structure, so Just use a general rate-compatible structure.
  • the constraint block A adopts a Raptor-like structure, which further improves the rate compatibility.
  • the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality
  • the adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality
  • the row of the bidiagonal structure of constraint block A can adopt a non-orthogonal structure, that is, the adjacent row vectors of rows 1 to n of BG_sub satisfy the non-orthogonal structure. pay.
  • the row of the single diagonal structure of constraint block A can adopt a quasi-orthogonal or completely orthogonal structure, that is, the adjacent row vectors of the n+1 to mth rows of BG_sub satisfy quasi-orthogonal, and the m+1 to last row of BG_sub The adjacent row vectors of are completely orthogonal.
  • constraint blocks A, B, C... need to be optimized so that the BG_sub rows spliced into them satisfy quasi-orthogonal and completely orthogonal.
  • BG sub [...,C,B,A]
  • the non-orthogonality of high code rate bi-diagonal rows can improve decoding performance
  • the single diagonal medium code rate row corresponding to n+1 to n
  • the quasi-orthogonality of m rows and the complete orthogonality of single diagonal low code rate rows corresponding to m+1 to the last row
  • Example 1 The memory length of the prefix syndrome is 1.
  • the prefix syndrome constraint of SC-LDPC is 1.
  • Each coupling section includes constraint block A and constraint block B.
  • constraint block A is the existing 5G NR LDPC BG1 base matrix
  • constraint block B (coupling extension block, size 46 ⁇ 68) is obtained based on greedy algorithm and PEXIT decoding threshold index search.
  • Figure 10 is a third schematic structural diagram of a constraint block provided by an embodiment of the present disclosure. As shown in Figure 10, only the first 13 columns in constraint block B contain 1, and the remaining columns are all 0 (shown in the form of a table in Figure 10).
  • the transmitter terminal, base station, etc.
  • encodes the mother code word x according to the bits to be sent and the check constraint relationship Hx T 0, and sends it to the rate matcher.
  • Example 2 The memory length of the prefix syndrome is 2.
  • the prefix syndrome constraint of SC-LDPC is 2, and the coupling section L is 30.
  • Each coupling section includes constraint block A, constraint block B and constraint block C.
  • Constraint block A is the existing 5G NR LDPC BG1 basis matrix.
  • Constraint block B and constraint block C are obtained based on greedy algorithm and PEXIT decoding threshold index search.
  • Constraint block B has a size of 46 ⁇ 68. Only the first 13 columns contain 1, and the remaining columns are all 0.
  • Figure 11 is the fourth structural schematic diagram of the constraint block provided by the embodiment of the present disclosure. As shown in Figure 11, constraint block C (size is 46 ⁇ 68), only the first column contains 1 (shown in the form of a table in Figure 11, Only some columns are shown).
  • Example 3 The period is 2, and the memory length of the prefix syndrome is 1.
  • each coupling section includes constraint block A and constraint block B, and the coupling section L is 30.
  • constraint block A is the existing 5G NR LDPC BG1 base matrix
  • constraint block B (size 46 ⁇ 68) is obtained based on greedy algorithm and PEXIT decoding threshold index search. Only the first 13 columns in constraint block B contain 1, and the rest The columns are all 0.
  • Hash BG with a lifting factor Z 64 to obtain the SC-LDPC check matrix H.
  • the base matrix BG is the same, but the cyclic shift matrix PM corresponding to the constraint blocks A and B is repeated in 2 periods. .
  • the cyclic shift value in PM is taken from the cyclic difference family, and the formula of the submatrix BG sub is described as follows:
  • PM sub (i, j) ⁇ i + ⁇ i + j
  • PM sub (i, j) represents the i-th row and j-th column of PM sub
  • ⁇ is the primitive element of the finite field F 769
  • Example 4 The period is 2, and the memory length of the prefix syndrome is 2.
  • the prefix syndrome constraint of SC-LDPC is 1.
  • Each coupling section includes constraint block A, constraint block B and constraint block C.
  • the coupling section L is 30.
  • constraint block A is the existing 5G NR LDPC BG1 base matrix
  • constraint block B size is 46 ⁇ 68
  • constraint block C size is 46 ⁇ 68
  • Hash BG with a lifting factor Z 64 to obtain the SC-LDPC check matrix H.
  • the base matrix BG is the same, but the cyclic shift matrix PM corresponding to the constraint blocks A, B, and C is 2 periods. Repeated.
  • the cyclic shift value in PM is taken from the cyclic difference family, and the formula of the submatrix BG sub is described as follows:
  • PM sub (i, j) ⁇ i + ⁇ i + j
  • PM sub (i, j) represents the i-th row and j-th column of PM sub
  • ⁇ is the primitive element of the finite field F 769
  • Figure 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. As shown in Figure 12, the electronic device includes a memory 1220, a transceiver 1200, and a processor 1210, where:
  • Memory 1220 is used to store computer programs; transceiver 1200 is used to send and receive data under the control of the processor 1210; processor 1210 is used to read the computer program in the memory 1220 and perform the following operations:
  • the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;
  • Encoding is performed based on the basis matrix.
  • the transceiver 1200 is used to receive and transmit data under the control of the processor 1210.
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1210 and various circuits of the memory represented by memory 1220 are linked together.
  • the bus architecture can also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are all well known in the art and therefore will not be described further herein.
  • the bus interface provides the interface.
  • the transceiver 1200 may be a plurality of components, including a transmitter and a receiver, providing a unit for communicating with various other devices over transmission media, including wireless channels, wired channels, optical cables, and other transmission media.
  • the processor 1210 is responsible for managing the bus architecture and general processing, and the memory 1220 can store data used by the processor 1210 when performing operations.
  • the processor 1210 may be a central processing unit (CPU), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA) or a complex programmable logic device (Complex Programmable Logic Device, CPLD), the processor can also adopt a multi-core architecture.
  • CPU central processing unit
  • ASIC Application Specific Integrated Circuit
  • FPGA field programmable gate array
  • CPLD Complex Programmable Logic Device
  • encoding based on the basis matrix includes:
  • Rate matching is performed on the mother code codeword to determine the encoded codeword.
  • performing rate matching on the mother code codeword to determine the encoded codeword includes:
  • the method before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:
  • the cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;
  • the cyclic shift matrix is periodic.
  • the first constraint block of each coupling segment adopts a Raptor-like structure.
  • the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality
  • the adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality
  • the above-mentioned electronic equipment provided by the embodiments of the present disclosure may be a terminal, a base station, Core network, etc.
  • the above-mentioned electronic device provided by the embodiment of the present disclosure can implement all the method steps implemented by the above-mentioned method embodiment in which the execution subject is the electronic device, and can achieve the same technical effect.
  • the same as the method embodiment in this embodiment will no longer be used.
  • the parts and beneficial effects will be described in detail.
  • Figure 13 is a schematic structural diagram of an encoding device provided by an embodiment of the present disclosure. As shown in Figure 13, an embodiment of the present disclosure provides an encoding device, including a generation module 1301 and an encoding module 1302, wherein:
  • the generation module 1301 is used to generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure; the encoding module 1302 is used based on The basis matrix is encoded.
  • the encoding module includes a first determining sub-module, a second determining sub-module, a third determining sub-module and a rate matching sub-module;
  • the first determination sub-module is used to determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix
  • the second determination sub-module is used to determine the verification constraint relationship according to the verification matrix
  • the third determination sub-module is used to determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;
  • the rate matching sub-module is used to perform rate matching on the mother code codeword to determine the encoding codeword.
  • the rate matching sub-module includes a writing unit and a reading unit
  • the writing unit is used to write the mother code codeword into a row of coded bits in each coupling segment into a circular buffer of the rate matcher;
  • the reading unit is configured to read required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched codewords.
  • the device further includes a determination module
  • the determination module is used to determine the cyclic shift matrix based on a target criterion;
  • the target Standards include one or more of the following criteria;
  • the cyclic shift matrix is periodic.
  • the first constraint block of each coupling segment adopts a Raptor-like structure.
  • the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality
  • the adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality
  • the above-mentioned encoding device provided by the embodiment of the present disclosure can implement all the method steps implemented by the above-mentioned method embodiment in which the execution subject is an electronic device, and can achieve the same technical effect.
  • the method in this embodiment will no longer be compared.
  • the same parts and beneficial effects of the embodiments will be described in detail.
  • each functional unit in various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a processor-readable storage medium.
  • the technical solution of the present disclosure is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, It includes several instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code. .
  • a computer-readable storage medium is also provided, and the computer-readable storage medium stores a computer program.
  • the computer program is used to cause the computer to execute the encoding method provided by the above method embodiments.
  • the above-mentioned computer-readable storage medium provided by the embodiments of the present disclosure can implement all the method steps implemented by the above-mentioned method embodiments, and can achieve the same technical effect. No further reference will be made here to the method embodiments in this embodiment. The same parts and beneficial effects will be described in detail.
  • the computer-readable storage medium may be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (such as floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), Optical memory (such as CD, DVD, BD, HVD, etc.), and semiconductor memory (such as ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid state drive (SSD)), etc.
  • magnetic memory such as floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.
  • Optical memory such as CD, DVD, BD, HVD, etc.
  • semiconductor memory such as ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid state drive (SSD)
  • first, second, etc. are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances so that embodiments of the present disclosure can be practiced in sequences other than those illustrated or described herein, and that "first" and “second” are distinguished objects It is usually one type, and the number of objects is not limited.
  • the first object can be one or multiple.
  • the term "and/or” describes the association relationship of associated objects, indicating that The existence of three relationships, for example, A and/or B, can mean: A exists alone, A and B exist simultaneously, and B exists alone.
  • the character "/" generally indicates that the related objects are in an "or” relationship.
  • the term “plurality” refers to two or more than two, and other quantifiers are similar to it.
  • GSM global system of mobile communication
  • CDMA code division multiple access
  • WCDMA wideband code division multiple access
  • GPRS general packet Wireless service
  • LTE long term evolution
  • FDD frequency division duplex
  • TDD LTE time division duplex
  • UMTS Universal mobile telecommunication system
  • WiMAX microwave access
  • 5G New Radio, NR 5G New Radio
  • EPS Evolved Packet System
  • 5GS 5G system
  • EPS Evolved Packet System
  • 5GS 5G system
  • the terminal device involved in the embodiments of the present disclosure may be a device that provides voice and/or data connectivity to users, a handheld device with a wireless connection function, or other processing devices connected to a wireless modem, etc.
  • the names of terminal equipment may also be different.
  • the terminal equipment may be called User Equipment (UE).
  • UE User Equipment
  • Wireless terminal equipment can communicate with one or more core networks (Core Network, CN) via a Radio Access Network (RAN).
  • RAN Radio Access Network
  • the wireless terminal equipment can be a mobile terminal equipment, such as a mobile phone (also known as a "cellular phone").
  • Wireless terminal equipment may also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, or an access point.
  • remote terminal equipment remote terminal equipment
  • access terminal equipment access terminal
  • user terminal user terminal
  • user agent user agent
  • user device user device
  • the network device involved in the embodiment of the present disclosure may be a base station, and the base station may include multiple cells that provide services for terminals.
  • a base station can also be called an access point, or it can be a device in the access network that communicates with wireless terminal equipment through one or more sectors on the air interface, or it can be named by another name.
  • the network device may be used to exchange received air frames with Internet Protocol (IP) packets and act as a router between the wireless terminal device and the rest of the access network, where the remainder of the access network may include the Internet Protocol (IP) communication network.
  • IP Internet Protocol
  • Network devices also coordinate attribute management of the air interface.
  • the network equipment involved in the embodiments of the present disclosure may be a network equipment (Base Transceiver Station, BTS) in Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA). ), or it can be a network device (NodeB) in a Wide-band Code Division Multiple Access (WCDMA), or an evolutionary network device in a long term evolution (LTE) system (evolutional Node B, eNB or e-NodeB), 5G base station (gNB) in the 5G network architecture (next generation system), or Home evolved Node B (HeNB), relay node (relay node) , home base station (femto), pico base station (pico), etc., are not limited in the embodiments of the present disclosure.
  • the network device may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and the distributed unit may also be arranged geographically separately.
  • CU centralized unit
  • DU distributed unit
  • Determining B based on A in this disclosure means that the factor A should be considered when determining B. It is not limited to “B can be determined based on A alone", but also includes: “B is determined based on A and C", “B is determined based on A, C and E", "C is determined based on A, and B is further determined based on C" wait. In addition, it can also include taking A as a condition for determining B, for example, "When A meets the first condition, use the first method to determine B"; another example, "When A meets the second condition, determine B", etc.; another example , "When A meets the third condition, determine B based on the first parameter" and so on. Of course, it can also be a condition that uses A as a factor to determine B, for example, "when A meets the first condition, use the first method to determine C, and further determine B based on C" and so on.
  • Network equipment and terminal equipment can each use one or more antennas for multi-input multi-output (MIMO) transmission.
  • MIMO transmission can be single-user MIMO (Single User MIMO, SU-MIMO) or multi-user MIMO. (Multiple User MIMO,MU-MIMO).
  • MIMO transmission can be 2D-MIMO, 3D-MIMO, FD-MIMO or massive-MIMO, or it can be diversity transmission, precoding transmission or beamforming transmission, etc.
  • embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) embodying computer-usable program code therein.
  • a computer-usable storage media including, but not limited to, magnetic disk storage, optical storage, and the like
  • processor-executable instructions may also be stored in a processor-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the generation of instructions stored in the processor-readable memory includes the manufacture of the instruction means product, the instruction device implements the function specified in one process or multiple processes in the flow chart and/or one block or multiple blocks in the block diagram.
  • processor-executable instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby causing the computer or other programmable device to
  • the instructions that are executed provide steps for implementing the functions specified in a process or processes of the flowchart diagrams and/or a block or blocks of the block diagrams.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)

Abstract

Les modes de réalisation de la présente divulgation concernent un procédé et un appareil de codage, et un support de stockage. Le procédé comprend : la génération d'une matrice de base d'un code de contrôle de parité à faible densité couplé spatialement (SC-LDPC), la matrice de base comprenant L segments de couplage, chaque segment de couplage comprenant au moins deux blocs de contrainte, et chaque bloc de contrainte étant d'une structure compatible avec le débit ; et la réalisation d'un codage sur la base de la matrice de base. Au moyen du procédé et de l'appareil de codage, et du support de stockage fourni dans les modes de réalisation de la présente divulgation, une matrice de base est conçue, dans laquelle L segments de couplage sont compris, chaque segment de couplage comprend au moins deux blocs de contrainte, et chaque bloc de contrainte est d'une structure compatible avec le débit, de telle sorte que le SC-LDPC peut avoir une performance relativement bonne à différents débits de code, dans des régions de chute d'eau et dans des régions de seuil de décodage, et par conséquent non seulement une retransmission IR-HARQ peut être prise en charge, mais l'exigence de compatibilité de débit peut également être satisfaite.
PCT/CN2023/103244 2022-06-30 2023-06-28 Procédé et appareil de codage, et support de stockage WO2024002171A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210772643.2 2022-06-30
CN202210772643.2A CN117394950A (zh) 2022-06-30 2022-06-30 编码方法、装置及存储介质

Publications (1)

Publication Number Publication Date
WO2024002171A1 true WO2024002171A1 (fr) 2024-01-04

Family

ID=89383103

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103244 WO2024002171A1 (fr) 2022-06-30 2023-06-28 Procédé et appareil de codage, et support de stockage

Country Status (2)

Country Link
CN (1) CN117394950A (fr)
WO (1) WO2024002171A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047387A (zh) * 2007-03-23 2007-10-03 北京大学 一种多码率兼容ldpc码的构造方法及其译码器
US20150155884A1 (en) * 2013-12-03 2015-06-04 Samsung Electronics Co., Ltd. Method of and apparatus for generating spatially-coupled low-density parity-check code
CN106059595A (zh) * 2016-05-26 2016-10-26 北京邮电大学 空间耦合低密度奇偶校验码的通用递归编码方法
CN109379086A (zh) * 2018-10-11 2019-02-22 西安电子科技大学 低复杂度的码率兼容的5g ldpc编码方法和编码器
US20190334559A1 (en) * 2017-01-09 2019-10-31 Huawei Technologies Co., Ltd. Efficiently decodable qc-ldpc code
CN111162797A (zh) * 2020-01-21 2020-05-15 华侨大学 一种速率兼容的5g ldpc码的编码装置及编码方法
CN114285417A (zh) * 2021-12-21 2022-04-05 包滨豪 一种全局耦合低密度奇偶校验码的编码方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047387A (zh) * 2007-03-23 2007-10-03 北京大学 一种多码率兼容ldpc码的构造方法及其译码器
US20150155884A1 (en) * 2013-12-03 2015-06-04 Samsung Electronics Co., Ltd. Method of and apparatus for generating spatially-coupled low-density parity-check code
CN106059595A (zh) * 2016-05-26 2016-10-26 北京邮电大学 空间耦合低密度奇偶校验码的通用递归编码方法
US20190334559A1 (en) * 2017-01-09 2019-10-31 Huawei Technologies Co., Ltd. Efficiently decodable qc-ldpc code
CN109379086A (zh) * 2018-10-11 2019-02-22 西安电子科技大学 低复杂度的码率兼容的5g ldpc编码方法和编码器
CN111162797A (zh) * 2020-01-21 2020-05-15 华侨大学 一种速率兼容的5g ldpc码的编码装置及编码方法
CN114285417A (zh) * 2021-12-21 2022-04-05 包滨豪 一种全局耦合低密度奇偶校验码的编码方法

Also Published As

Publication number Publication date
CN117394950A (zh) 2024-01-12

Similar Documents

Publication Publication Date Title
US10594339B2 (en) Method for generating parity check matrix for low density parity check coding
US11374591B2 (en) Apparatus and method for channel coding in communication system
WO2017101631A1 (fr) Procédé et dispositif de communication pour traiter un code polaire
WO2019158031A1 (fr) Procédé de codage, procédé de décodage, dispositif de codage, et dispositif de décodage
US11664928B2 (en) Multi-label offset lifting method
US10879927B2 (en) Compact low density parity check (LDPC) base graph
US20230361787A1 (en) Method and apparatus for low density parity check channel coding in wireless communication system
WO2018219064A1 (fr) Procédé et dispositif de détermination de matrice de contrôle et support d'enregistrement informatique
WO2021136540A1 (fr) Procédé de codage en code ldpc et dispositif de communication
WO2020077596A1 (fr) Procédé et appareil de décodage pour codes ldpc
CN109391367B (zh) 通信方法和装置
WO2020098461A1 (fr) Procédé et dispositif de codage de codes polaires
US11463108B2 (en) Information processing method and communications apparatus
US10979084B2 (en) Method and apparatus for vector based LDPC base matrix usage and generation
CN107733439B (zh) 一种ldpc编码方法、编码装置及通信设备
WO2024002171A1 (fr) Procédé et appareil de codage, et support de stockage
WO2022268130A1 (fr) Procédé et appareil de codage de réseau
WO2021213227A1 (fr) Procédé, système et dispositif de transmission de données
EP3673581B1 (fr) Séquences d'informations conformes à upo pour codes polaires
WO2018141270A1 (fr) Procédé de codage, et procédé et dispositif de communication
WO2024055934A1 (fr) Procédé de codage, procédé de décodage, dispositif de communication et support de stockage lisible par ordinateur
WO2024067350A1 (fr) Procédé de codage et de décodage de code concaténé, et appareil de communication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23830343

Country of ref document: EP

Kind code of ref document: A1