WO2024002171A1 - Encoding method and apparatus, and storage medium - Google Patents

Abstract

Provided in the embodiments of the present disclosure are an encoding method and apparatus, and a storage medium. The method comprises: generating a basis matrix of a spatially coupled low-density parity check code (SC-LDPC), wherein the basis matrix comprises L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is of a rate-compatible structure; and performing encoding on the basis of the basis matrix. By means of the encoding method and apparatus, and the storage medium provided in the embodiments of the present disclosure, a basis matrix is designed, in which L coupling segments are comprised, each coupling segment includes at least two constraint blocks, and each constraint block is of a rate-compatible structure, such that the SC-LDPC can have relatively good performance at different code rates, in waterfall regions and in decoding threshold regions, and therefore not only can IR-HARQ retransmission be supported, but the rate compatibility requirement can also be met.

Description

Encoding method, device and storage medium

Cross-references to related applications

This application claims priority to the Chinese patent application with application number 2022107726432 and the invention title "Encoding Method, Device and Storage Medium" submitted on June 30, 2022, which is fully incorporated herein by reference.

Technical field

The present disclosure relates to the field of communication technology, and in particular, to an encoding method, device and storage medium.

Background technique

The data channel of the 5th generation mobile communication (5G) New Radio (NR) Low Density Parity Check Code (LDPC) adopts spatially coupled low density parity check code (LDPC). Spatially Coupled Low Density Parity Check Code, SC-LDPC).

However, for the next generation of mobile communications, SC-LDPC cannot meet the rate compatibility requirements and cannot support the Incremental Redundancy Hybrid Automatic Repeat Request (IR-HARQ) in the next generation of mobile communications systems.

Contents of the invention

Embodiments of the present disclosure provide an encoding method, device, and storage medium to solve the technical problem that SC-LDPC in the prior art cannot meet rate compatibility requirements.

In a first aspect, an embodiment of the present disclosure provides an encoding method, including:

Generate a basis matrix for the spatially coupled low-density parity check code SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

Encoding is performed based on the basis matrix.

In some embodiments, encoding based on the basis matrix includes:

Determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

Determine the verification constraint relationship according to the verification matrix;

Determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

Rate matching is performed on the mother code codeword to determine the encoded codeword.

In some embodiments, performing rate matching on the mother code codeword to determine the encoded codeword includes:

Write the mother code codeword into a row according to the coded bits in each coupling section, and write it into the circular buffer of the rate matcher;

Read the required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched encoded codewords.

In some embodiments, before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:

The cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;

Maximize the girth of the check matrix;

Optimize the ring distribution of the check matrix;

Cyclic differential family.

In some embodiments, the cyclic shift matrix is periodic.

In some embodiments, the first constraint block of each coupling segment adopts a Raptor-like structure.

In some embodiments, the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality;

or,

The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

or,

The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

Among them, m>n≥2.

In a second aspect, embodiments of the present disclosure provide an electronic device, including a memory, a transceiver, and a processor;

Memory, used to store computer programs; transceiver, used to send and receive data under the control of the processor; processor, used to read the computer program in the memory and perform the following operations:

Generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

Encoding is performed based on the basis matrix.

In some embodiments, encoding based on the basis matrix includes:

Determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

Determine the verification constraint relationship according to the verification matrix;

Determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

Rate matching is performed on the mother code codeword to determine the encoded codeword.

In some embodiments, performing rate matching on the mother code codeword to determine the encoded codeword includes:

Write the mother code codeword into a row according to the coded bits in each coupling section, and write it into the circular buffer of the rate matcher;

Read the required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched encoded codewords.

In some embodiments, before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:

The cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;

Maximize the girth of the check matrix;

Optimize the ring distribution of the check matrix;

Cyclic differential family.

In some embodiments, the cyclic shift matrix is periodic.

In some embodiments, the first constraint block of each coupling segment adopts a Raptor-like structure.

In some embodiments, the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality;

or,

The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

or,

The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

Among them, m>n≥2.

In a third aspect, an embodiment of the present disclosure provides an encoding device, including:

A generation module, used to generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

An encoding module, used for encoding based on the base matrix.

In some embodiments, the encoding module includes a first determining sub-module, a second determining sub-module, a third determining sub-module and a rate matching sub-module;

The first determination sub-module is used to determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

The second determination sub-module is used to determine the verification constraint relationship according to the verification matrix;

The third determination sub-module is used to determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

The rate matching sub-module is used to perform rate matching on the mother code codeword to determine the encoding codeword.

In some embodiments, the rate matching sub-module includes a writing unit and a reading unit;

The writing unit is used to write the mother code codeword into a row of coded bits in each coupling segment into a circular buffer of the rate matcher;

The reading unit is configured to read required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched codewords.

In some embodiments, the device further includes a determination module;

The determination module is configured to determine the cyclic shift matrix based on a target criterion; the target criterion includes one or more of the following criteria;

Maximize the girth of the check matrix;

Optimize the ring distribution of the check matrix;

Cyclic differential family.

In some embodiments, the cyclic shift matrix is periodic.

In some embodiments, the first constraint block of each coupling segment adopts a Raptor-like structure.

In some embodiments, the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality;

or,

The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

or,

The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

Among them, m>n≥2.

In a fourth aspect, embodiments of the present disclosure also provide a processor-readable storage medium that stores a computer program, and the computer program is used to cause the processor to execute the process described in the first aspect. encoding method.

In a fifth aspect, embodiments of the present disclosure further provide a computer-readable storage medium storing a computer program, the computer program being used to cause the computer to execute the encoding method described in the first aspect. .

In a sixth aspect, embodiments of the present disclosure also provide a communication device readable storage medium, the communication device readable storage medium stores a computer program, the computer program is used to cause the communication device to execute the above described first aspect encoding method.

In a seventh aspect, embodiments of the present disclosure also provide a chip product-readable storage medium. The chip product-readable storage medium stores a computer program. The computer program is used to cause the chip product to execute the above-described first aspect. encoding method.

The encoding method, device and storage medium provided by the embodiments of the present disclosure are designed to include L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a base matrix of a rate-compatible structure. The check matrix determined based on this base matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility. Require.

Description of drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be made below to the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the construction method of QC-LDPC check matrix;

Figure 2 is a schematic diagram of the SC-LDPC check matrix;

Figure 3 is a schematic diagram of the TB-SC-LDPC check matrix;

Figure 4 is a schematic flowchart of an encoding method provided by an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram of the basis matrix of SC-LDPC provided by an embodiment of the present disclosure;

Figure 6 is one of the structural schematic diagrams of a constraint block provided by an embodiment of the present disclosure;

Figure 7 is a schematic structural diagram of the basis matrix of TB-SC-LDPC provided by an embodiment of the present disclosure;

Figure 8 is a schematic diagram of the rate matching principle provided by an embodiment of the present disclosure;

Figure 9 is the second structural schematic diagram of a constraint block provided by an embodiment of the present disclosure;

Figure 10 is a third schematic structural diagram of a constraint block provided by an embodiment of the present disclosure;

Figure 11 is the fourth structural schematic diagram of a constraint block provided by an embodiment of the present disclosure;

Figure 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure;

Figure 13 is a schematic structural diagram of an encoding device provided by an embodiment of the present disclosure.

Detailed ways

LDPC is a type of linear block code that can approach the Shannon channel capacity. The code is defined by an m×n binary check matrix H. The encoded codeword c is a binary vector of length n, satisfying cH ^T =0, and the code rate for The data channel of 5G NR uses structured Quasi Cyclic Low Density Parity Check Code (QC-LDPC). The granularity of information bits can reach 1 bit, and the code rate range covers 1/3 ~8/9. The flexible coding parameters of NR LDPC can allow channel coding to better adapt to dynamic changes in the wireless communication environment and thereby improve spectral efficiency. The structured QC-LDPC greatly reduces the hardware implementation complexity and algorithm complexity of the encoder and decoder. , and improve the parallelism of decoder decoding.

Figure 1 is a schematic diagram of the construction method of the QC-LDPC check matrix. As shown in Figure 1, the check matrix H of QC-LDPC can be uniquely determined by the base matrix (Base Graph, BG) and the cyclic shift matrix PM. NR LDPC coding Single-sided QC-LDPC is used, and each block is a Z×Z unit cyclic shift matrix Q(), or a Z×Z all-zero matrix. circular shift The bit value is the set of integers Z∈{-1,0,…,Z-1}, where Z=-1 represents an all-zero matrix.

SC-LDPC coding constructs a check matrix by coupling the edges of adjacent codewords (adjacent coupling segments) in the Tanner graph. This spatial coupling connection structure causes SC-LDPC to produce a threshold saturation effect during decoding. , and the decoding performance will be greatly improved compared to the performance of uncoupled LDPC codes. Figure 2 is a schematic diagram of the SC-LDPC check matrix. As shown in Figure 2, the check matrix H of SC-LDPC has a strip structure on the diagonal. When the memory length of the pre-check submatrix is 2, the sub-matrix H The sizes of ₁ , H ₂ and H ₃ are all m×n, the code length is n×L, and L is the number of coupling segments. SC-LDPC code rate Compared to the code rate of LDPC There is a certain bit rate loss. It should be noted that the SC-LDPC code can also adopt a Quasi Cyclic (QC) structure: first design the BG of the spatial coupling structure, and then obtain the check matrix through hashing (Dispersion, a cyclic shift matrix filling method) H. SC-LDPC is usually designed as a QC structure, and the basis matrix BG is regular (the number of 1s in each row is the same, and the number of 1s in each column is also the same). This structure cannot meet the rate compatibility requirements. Although SC-LDPC can also achieve rate compatibility through hole punching, the decoding performance after hole punching is poor and cannot meet high-performance communication needs.

When the number of coupling segments L is small or the code length is short, the code rate loss of SC-LDPC is large, which greatly affects the transmission efficiency. The emergence of Tail Biting Spatially Coupled Low Density Parity Check Code (TB-SC-LDPC) solves the problem of code rate loss. Figure 3 is a schematic diagram of the TB-SC-LDPC check matrix. As shown in Figure 3, the check matrix H of TB-SC-LDPC is usually full row rank, and the code rate satisfies Therefore there is no bitrate loss. However, TB-SC-LDPC does not have a threshold saturation effect during decoding, and requires additional special design to indirectly trigger the threshold saturation effect to improve decoding performance. Specifically, the bits in some coupling segments can be shortened or the bits in some coupling segments can be mapped to The more reliable bits of high-order modulation indirectly trigger the threshold saturation effect to achieve wave decoding. Similar to SC-LDPC, TB-SC-LDPC is usually designed as a QC structure, BG is also regular, and lacks an effective rate-compatible encoding scheme.

For LDPC and QC-LDPC, the existing rate-compatible LDPC construction methods can be divided into the following two types:

1. Combination of shortening and puncturing: first construct a low code rate LDPC mother code, encode the information bits by filling some known bits (the filling bits are not transmitted on the channel), and encode some bits in the mother code codeword Punching (some bits are not transmitted over the channel), thereby obtaining LDPC and QC-LDPC codes with a larger code rate range.

2. Extension: First construct a high code rate LDPC and QC-LDPC mother code, and then generate new check bits based on the current mother code codeword to obtain a lower code rate.

In summary, QC-LDPC has lower decoding parallelism, resulting in lower decoding throughput. SC-LDPC and TB-SC-LDPC are usually designed as regular BGs or lack effective rate-compatible coding schemes, which are oriented to In the next generation of mobile communications, QC-LDPC, SC-LDPC and TB-SC-LDPC are unable to meet the rate compatibility requirements and support the Incremental Redundancy Hybrid Automatic Repeat Request (IR) in the next generation mobile communications system. -HARQ) requirements.

Based on the above technical problems, the embodiment of the present disclosure designs a base matrix that includes L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a rate-compatible structure, so that the base matrix can be determined according to the base matrix. The check matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility requirements.

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments These are only some of the embodiments of the present disclosure, but not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to this disclosure. scope of protection.

FIG. 4 is a schematic flowchart of an encoding method provided by an embodiment of the present disclosure. As shown in FIG. 4 , an embodiment of the present disclosure provides an encoding method, and the execution subject may be a terminal, such as a mobile phone. It can also be network equipment, such as base stations, core networks, etc. The method includes:

Step 401: Generate a base matrix of the spatially coupled low-density parity check code SC-LDPC; the base matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure, L is an integer greater than or equal to 2.

Specifically, since SC-LDPC has a spatial coupling structure and the entire check matrix has a strip-like structure on the diagonal, it is impossible to directly design the SC-LDPC check matrix as a whole into a rate-compatible structure. Therefore, in the embodiment of the present disclosure, the BG of SC-LDPC is first divided into multiple coupling sections, and each coupling section is designed with a rate-compatible structure, that is, each coupling section contains at least two constraint blocks, and each constraint block All are rate compatible structures.

The coupling segment is composed of multiple columns of BG, and each coupling segment is a sub-matrix of BG. The constraint block consists of multiple rows of the coupling segment, and each constraint block is a sub-matrix of the coupling segment. The rate-compatible structure is a matrix containing lower triangular submatrices.

The structure of this base matrix is equivalent to a high code rate LDPC and many single check codes, and as the number of rows and columns of the extended matrix increases, an LDPC check matrix with an arbitrarily low code rate can be obtained. For example, first Construct a kernel matrix with a code rate of 8/9, and then gradually expand downward to obtain code rates of 7/8, 5/6, 3/4, 1/2, 2/5, 1/3, 1/4, 1/5 of the check matrix, thus ensuring that the rate compatibility/redundant incremental structure of the check matrix will not be destroyed after spatial coupling expansion.

The first constraint block A in the coupling section is used for recursive coding of SC-LDPC. The constraint blocks (constraint block B, etc.) within the coupling section except the first constraint block A are used for syndrome calculation.

For example, Figure 5 is a schematic structural diagram of the basis matrix of SC-LDPC provided by an embodiment of the present disclosure. As shown in Figure 5, the BG of SC-LDPC includes 3 coupling segments. The memory length of the prefix syndrome is 1, and each A coupling section contains two constraint blocks (constraint block A and constraint block B), and each constraint block is a rate-compatible structure.

For example, Figure 6 is one of the structural schematic diagrams of the constraint block provided by the embodiment of the present disclosure. As shown in Figure 6, the rate compatible structure provided by the embodiment of the present disclosure includes sub-matrix A, sub-matrix C, sub-matrix D and zero matrix. Among them, submatrix D is a lower triangular matrix.

TB-SC-LDPC is a special SC-LDPC. Figure 7 is a schematic structural diagram of the basis matrix of TB-SC-LDPC provided by the embodiment of the present disclosure. As shown in Figure 7, the BG of TB-SC-LDPC includes 3 Each coupling segment has a memory length of 1. Each coupling segment contains two constraint blocks (constraint block A and constraint block B). Each constraint block is a rate-compatible structure.

It should be noted that: the memory length of the prefix syndrome indicates the number of constraint blocks before the origin (the first constraint block) of the submatrix formed by splicing at least two constraint blocks in each coupling segment in columns. For example, in Figure 6 and Figure 7, the memory length of the prefix syndrome is 1. Therefore, each coupling segment contains two constraint blocks. The constraint blocks contained in each coupling segment are spliced in columns into a submatrix BG. _sub =[B,A], that is, there is a constraint block B before and after the first constraint block A of the submatrix BG _sub . When the memory length is greater than 1, more constraint blocks may be included.

Step 402: Encode based on the base matrix.

In some embodiments, encoding based on the basis matrix includes:

The check matrix of the SC-LDPC is determined according to the base matrix and a predetermined cyclic shift matrix.

Specifically, after determining the base matrix, the terminal or base station first performs a hash operation on the base matrix with the lifting factor Z to obtain the check matrix H of SC-LDPC, that is, determine the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix. Check matrix H of LDPC.

Determine the verification constraint relationship according to the verification matrix.

Specifically, the verification constraint relationship can be determined based on the verification matrix H. The formula of the verification constraint relationship is described as follows:
^HxT ＝0

Among them, H is the check matrix, and x is the mother code codeword.

The mother code codeword is determined according to the relationship between the bits to be transmitted and the check constraint.

Specifically, the terminal or base station performs encoding to obtain the mother code word x according to the bits to be transmitted and the check constraint relationship Hx ^T =0.

Rate matching is performed on the mother code codeword to determine the encoded codeword.

Specifically, after the terminal or base station determines the mother code code word x, the rate matcher performs rate matching on the mother code code word to obtain the final encoded code word.

The encoding method provided by the embodiment of the present disclosure is designed to include L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a base matrix of a rate-compatible structure, so that the base matrix can be determined according to the base matrix. The check matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility requirements.

In some embodiments, performing rate matching on the mother code codeword to determine the encoded codeword includes:

The mother code codeword is written into a circular buffer of the rate matcher according to the coded bits in each coupling section as one row.

Specifically, Figure 8 is a schematic diagram of the rate matching principle provided by an embodiment of the present disclosure. As shown in Figure 8, in the embodiment of the present disclosure, the terminal or base station sends the mother code word x into the rate matching in the "coupling section interleaving" method. In the circular buffer of the processor, the shortened or punctured bits in each coupling segment are skipped directly and are not sent to the circular buffer. "Coupled segment interleaving" can be implemented by row writing and column reading. The formula is described as follows:
v _l+(i-1)·L =x _i+(l-1)·N

Among them, v _i+(i-1)·L is the rearranged codeword, i=1,2,3,…N, l=1,2,3,…L, x _i+(l-1)·N represents the i-th bit in the l-1th coupling segment, N represents the number of bits in a coupling segment, and L represents the total number of coupling segments.

Read the required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched encoded codewords.

Specifically, after the mother code word is written into the circular buffer of the rate matcher, the length of the code word after rate matching is determined according to the target code rate or the size of the allocated transmission resource block (RE), and the code word length is obtained from the buffer in a first-in, first-out manner. Read the required bits from the processor to obtain the coded code after rate matching. Code words.

The encoding method provided by the embodiment of the present disclosure is designed to include L coupling segments, each coupling segment includes at least two constraint blocks, and each constraint block is a base matrix of a rate-compatible structure, so that the base matrix can be determined according to the base matrix. The check matrix satisfies the lower triangular structure, so that SC-LDPC has better performance in different code rates, waterfall areas, and decoding threshold areas. It can not only support IR-HARQ retransmission, but also meet rate compatibility requirements.

In some embodiments, a screening step of the basis matrix is also included.

Search to obtain the optimal basis matrix that meets the structural requirements based on a certain criterion, for example, select the optimal basis matrix based on the decoding threshold criterion.

The encoding method provided by the embodiments of the present disclosure further improves rate compatibility by screening the optimal basis matrix.

Specifically, in the embodiment of the present disclosure, before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:

The cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;

Maximize the girth of the check matrix;

Optimize the ring distribution of the check matrix;

Cyclic differential family.

Specifically, in the embodiment of the present disclosure, before determining the check matrix, it is necessary to determine the cycle based on one or more criteria such as maximizing the girth of the check matrix, optimizing the ring distribution of the check matrix, and the cyclic differential family. Shift matrix PM.

A ring refers to a closed loop formed in the Tanner graph corresponding to the LDPC check matrix, and the length of the closed loop becomes the ring length. The proportional distribution of ring lengths is the ring distribution. For example, 70% of the rings have a ring length of 8 and 30% of the rings have a ring length of 6. The girth, or girth, refers to the length of the shortest ring in the Tanner graph corresponding to the LDPC check matrix.

Assume v is a positive integer. For an additive group Z _v = {0,1,...v-1}, take t subsets in Z _v as base blocks. Each base block contains k elements, t base block representation For D _i ={d _i1 ,d _i2 ,…,d _ik }, d _i1 <d _i2 <…<d _ik , i=1,2…t, each non-zero element in Z _v is in the difference set operation ( d _im -d _in ) modv all appear λ times in the results, where m≠n and m, n=1,2,...k, then define such base block group D _i as a group of t-(v,k, 1) Cyclic Difference Family (CDF).

In some embodiments, the cyclic shift matrix is periodic.

Specifically, in the embodiment of the present disclosure, within each coupling segment l=1,2,...,L, the cyclic shift values corresponding to the positions of constraint blocks A, B... are repeated with a certain period.

For example, when the period is 2, the cyclic shift values corresponding to the constraint blocks A, B... in the coupling section l = 1, 3, 5, 7... are equal, and the constraints in the coupling section l = 2, 4, 6, 8... The cyclic shift values corresponding to blocks A, B... are equal.

Specially, when the period is 1, in each coupling segment l=1,2,...,L, the cyclic shift values corresponding to the positions of constraint blocks A, B... are completely equal.

The encoding method provided by the embodiments of the present disclosure further reduces the storage overhead of the codec through a periodic cyclic shift matrix.

In some embodiments, the first constraint block of each coupling segment adopts a Raptor-like structure.

Specifically, the Raptor-like structure is a special rate-compatible structure. In the embodiment of the present disclosure, the first constraint block A in the coupling section is used for recursive coding of SC-LDPC. The high bit rate part of constraint block A needs to adopt a Raptor-like double diagonal structure to reduce coding complexity while ensuring high bit rate performance.

Figure 9 is a second structural schematic diagram of a constraint block provided by an embodiment of the present disclosure. As shown in Figure 9, the Raptor-like structure provided by an embodiment of the present disclosure includes sub-matrix A, sub-matrix B, sub-matrix C, sub-matrix D and Zero matrix, where sub-matrix B is a bi-diagonal matrix and sub-matrix D is a single-diagonal matrix.

Constraint block A can be obtained based on the basis matrix of the existing designed Raptor-like structure. For example, constraint block A can use the basis matrix BG1 or BG2 of 5G NR LDPC.

The constraint blocks (constraint block B, etc.) in the coupling section except the first constraint block A are used for syndrome calculation and do not involve coding calculation, so there is no need for a double-diagonal or single-diagonal structure, so Just use a general rate-compatible structure.

In the encoding method provided by the embodiment of the present disclosure, the constraint block A adopts a Raptor-like structure, which further improves the rate compatibility.

In some embodiments, the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality;

or,

The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

or,

The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

Among them, m>n≥2.

Specifically, in the embodiment of the present disclosure, at least two constraint blocks A, B, C... contained in each coupling section are spliced in columns into a sub-matrix BG _sub = [..., C, B, A].

When the constraint block is a Raptor-like structure, for BG_sub, the row of the bidiagonal structure of constraint block A can adopt a non-orthogonal structure, that is, the adjacent row vectors of rows 1 to n of BG_sub satisfy the non-orthogonal structure. pay.

The row of the single diagonal structure of constraint block A can adopt a quasi-orthogonal or completely orthogonal structure, that is, the adjacent row vectors of the n+1 to mth rows of BG_sub satisfy quasi-orthogonal, and the m+1 to last row of BG_sub The adjacent row vectors of are completely orthogonal.

That is, constraint blocks A, B, C... need to be optimized so that the BG_sub rows spliced into them satisfy quasi-orthogonal and completely orthogonal.

BG _sub = […,C,B,A] The non-orthogonality of high code rate bi-diagonal rows (corresponding to lines 1 to n) can improve decoding performance, and the single diagonal medium code rate row (corresponding to n+1 to n The quasi-orthogonality of m rows) and the complete orthogonality of single diagonal low code rate rows (corresponding to m+1 to the last row) can greatly improve decoding throughput.

The methods in the above embodiments will be further described below with several specific examples.

Example 1: The memory length of the prefix syndrome is 1.

The prefix syndrome constraint of SC-LDPC is 1. Each coupling section includes constraint block A and constraint block B. The coupling section L is L=30. Among them, constraint block A is the existing 5G NR LDPC BG1 base matrix, and constraint block B (coupling extension block, size 46×68) is obtained based on greedy algorithm and PEXIT decoding threshold index search. Figure 10 is a third schematic structural diagram of a constraint block provided by an embodiment of the present disclosure. As shown in Figure 10, only the first 13 columns in constraint block B contain 1, and the remaining columns are all 0 (shown in the form of a table in Figure 10). The SC-LDPC check matrix H is obtained by hashing BG with a lifting factor Z=64. Within each coupling segment, the base matrix BG and the cyclic shift matrices PM corresponding to constraint blocks A and B are the same.

The cyclic shift value in PM is taken from the cyclic difference family. Specifically, the cyclic shift matrix corresponding to BG _sub =[B A] is PM _sub =[PM _B PM _A ], PM _sub (i,j)=α ⁱ +α ^i+j , where PM _sub (i, j) represents the i-th row and j-th column of PM _sub , and α is the primitive element of the finite field F ₇₆₉ . The target code rate is R=0.5. The transmitter (terminal, base station, etc.) encodes the mother code word x according to the bits to be sent and the check constraint relationship Hx ^T =0, and sends it to the rate matcher. Then, k=L*22*Z*R=21120 encoded bits are read from the circular buffer to obtain the final encoded codeword.

Example 2: The memory length of the prefix syndrome is 2.

The prefix syndrome constraint of SC-LDPC is 2, and the coupling section L is 30. Each coupling section includes constraint block A, constraint block B and constraint block C. Constraint block A is the existing 5G NR LDPC BG1 basis matrix. Constraint block B and constraint block C are obtained based on greedy algorithm and PEXIT decoding threshold index search. Constraint block B has a size of 46×68. Only the first 13 columns contain 1, and the remaining columns are all 0. Figure 11 is the fourth structural schematic diagram of the constraint block provided by the embodiment of the present disclosure. As shown in Figure 11, constraint block C (size is 46×68), only the first column contains 1 (shown in the form of a table in Figure 11, Only some columns are shown). The SC-LDPC check matrix H is obtained by hashing BG with a lifting factor Z=64. Within each coupling segment, the base matrix BG and the cyclic shift matrix PM corresponding to the constraint blocks A, B, and C are the same.

The cyclic shift value in PM is taken from the cyclic differential family, specifically BG _sub =[C B A] pair The corresponding cyclic shift matrix is PM _sub = [PM _C PM _B PM _A ], PM _sub (i, j) = α ⁱ + α ^{i + j} , where PM _sub (i, j) represents the i-th row of PM _sub In column j, α is the primitive element of finite field F ₇₆₉ . The target code rate is R=0.5. The transmitter encodes the mother code word x according to the bits to be sent and the check constraint relationship Hx ^T =0, and sends it to the rate matcher. Then, k=L*22*Z*R=21120 encoded bits are read from the circular buffer to obtain the final encoded codeword.

Example 3: The period is 2, and the memory length of the prefix syndrome is 1.

The prefix syndrome constraint of SC-LDPC is 1, each coupling section includes constraint block A and constraint block B, and the coupling section L is 30. Among them, constraint block A is the existing 5G NR LDPC BG1 base matrix, and constraint block B (size 46×68) is obtained based on greedy algorithm and PEXIT decoding threshold index search. Only the first 13 columns in constraint block B contain 1, and the rest The columns are all 0. Hash BG with a lifting factor Z=64 to obtain the SC-LDPC check matrix H. In different coupling segments, the base matrix BG is the same, but the cyclic shift matrix PM corresponding to the constraint blocks A and B is repeated in 2 periods. .

The cyclic shift value in PM is taken from the cyclic difference family, and the formula of the submatrix BG _sub is described as follows:

The formula of the cyclic shift matrix PM _{sub corresponding to the sub-matrix BG sub is} described as follows:

Among them, PM _sub (i, j) = α ⁱ + α ^{i + j} , PM _sub (i, j) represents the i-th row and j-th column of PM _sub , α is the primitive element of the finite field F ₇₆₉ , PM _A1 and PM _B1 corresponds to the cyclic shift value corresponding to the constraint block A and B in the odd coupling section l=1, 3, 5,..., M _A2 and PM _B2 correspond to the constraints in the even coupling section l=2, 4, 6,... The cyclic shift values corresponding to blocks A and B. The target code rate is R=0.5. The transmitter encodes the mother code word x according to the bits to be sent and the check constraint relationship Hx ^T =0, and sends it to the rate matcher. Then, k=L*22*Z*R=21120 encoded bits are read from the circular buffer to obtain the final encoded codeword.

Example 4: The period is 2, and the memory length of the prefix syndrome is 2.

The prefix syndrome constraint of SC-LDPC is 1. Each coupling section includes constraint block A, constraint block B and constraint block C. The coupling section L is 30. Among them, constraint block A is the existing 5G NR LDPC BG1 base matrix, constraint block B (size is 46×68) and constraint block C (size is 46×68) are obtained based on greedy algorithm and PEXIT decoding threshold index search. Constraint block Only the first 13 columns in block B contain 1, the remaining columns are all 0, and only the 1st column of constraint block C contains 1. Hash BG with a lifting factor Z=64 to obtain the SC-LDPC check matrix H. In different coupling segments, the base matrix BG is the same, but the cyclic shift matrix PM corresponding to the constraint blocks A, B, and C is 2 periods. Repeated. The cyclic shift value in PM is taken from the cyclic difference family, and the formula of the submatrix BG _sub is described as follows:

The formula of the cyclic shift matrix PM _{sub corresponding to the sub-matrix BG sub is} described as follows:

Among them, PM _sub (i, j) = α ⁱ + α ^{i + j} , PM _sub (i, j) represents the i-th row and j-th column of PM _sub , α is the primitive element of the finite field F ₇₆₉ , PM _A1 , PM _B1 and PM _C1 correspond to the cyclic shift values corresponding to the constraint blocks A, B, and C in the coupling section l=1,4,7,..., _MA2 , PM _B2 , and PM _C2 correspond to the coupling section l=2,5 ,8,...The cyclic shift values corresponding to the constraint blocks A, B, and C, M _A3 , PM _B3 , and PM _C3 correspond to the cyclic shift values corresponding to the constraint blocks A, B, and C within the coupling section l=3,6,9,... The corresponding circular shift value. The target code rate is R=0.5. The transmitter encodes the mother code word x according to the bits to be sent and the check constraint relationship Hx ^T =0, and sends it to the rate matcher. Then, k=L*22*Z*R=21120 encoded bits are read from the circular buffer to obtain the final encoded codeword.

Figure 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. As shown in Figure 12, the electronic device includes a memory 1220, a transceiver 1200, and a processor 1210, where:

Memory 1220 is used to store computer programs; transceiver 1200 is used to send and receive data under the control of the processor 1210; processor 1210 is used to read the computer program in the memory 1220 and perform the following operations:

Generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

Encoding is performed based on the basis matrix.

Specifically, the transceiver 1200 is used to receive and transmit data under the control of the processor 1210.

In FIG. 12 , the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1210 and various circuits of the memory represented by memory 1220 are linked together. The bus architecture can also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are all well known in the art and therefore will not be described further herein. The bus interface provides the interface. The transceiver 1200 may be a plurality of components, including a transmitter and a receiver, providing a unit for communicating with various other devices over transmission media, including wireless channels, wired channels, optical cables, and other transmission media. The processor 1210 is responsible for managing the bus architecture and general processing, and the memory 1220 can store data used by the processor 1210 when performing operations.

The processor 1210 may be a central processing unit (CPU), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA) or a complex programmable logic device (Complex Programmable Logic Device, CPLD), the processor can also adopt a multi-core architecture.

In some embodiments, encoding based on the basis matrix includes:

Determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

Determine the verification constraint relationship according to the verification matrix;

Determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

Rate matching is performed on the mother code codeword to determine the encoded codeword.

In some embodiments, performing rate matching on the mother code codeword to determine the encoded codeword includes:

Write the mother code codeword into a row according to the coded bits in each coupling section, and write it into the circular buffer of the rate matcher;

Read the required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched encoded codewords.

In some embodiments, before determining the check matrix of the SC-LDPC based on the base matrix and the predetermined cyclic shift matrix, the method further includes:

The cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;

Maximize the girth of the check matrix;

Optimize the ring distribution of the check matrix;

Cyclic differential family.

In some embodiments, the cyclic shift matrix is periodic.

In some embodiments, the first constraint block of each coupling segment adopts a Raptor-like structure.

In some embodiments, the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality;

or,

The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

or,

The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

Among them, m>n≥2.

Specifically, the above-mentioned electronic equipment provided by the embodiments of the present disclosure may be a terminal, a base station, Core network, etc.

The above-mentioned electronic device provided by the embodiment of the present disclosure can implement all the method steps implemented by the above-mentioned method embodiment in which the execution subject is the electronic device, and can achieve the same technical effect. The same as the method embodiment in this embodiment will no longer be used. The parts and beneficial effects will be described in detail.

Figure 13 is a schematic structural diagram of an encoding device provided by an embodiment of the present disclosure. As shown in Figure 13, an embodiment of the present disclosure provides an encoding device, including a generation module 1301 and an encoding module 1302, wherein:

The generation module 1301 is used to generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure; the encoding module 1302 is used based on The basis matrix is encoded.

In some embodiments, the encoding module includes a first determining sub-module, a second determining sub-module, a third determining sub-module and a rate matching sub-module;

The first determination sub-module is used to determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

The second determination sub-module is used to determine the verification constraint relationship according to the verification matrix;

The third determination sub-module is used to determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

The rate matching sub-module is used to perform rate matching on the mother code codeword to determine the encoding codeword.

In some embodiments, the rate matching sub-module includes a writing unit and a reading unit;

The writing unit is used to write the mother code codeword into a row of coded bits in each coupling segment into a circular buffer of the rate matcher;

The reading unit is configured to read required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched codewords.

In some embodiments, the device further includes a determination module;

The determination module is used to determine the cyclic shift matrix based on a target criterion; the target Standards include one or more of the following criteria;

Maximize the girth of the check matrix;

Optimize the ring distribution of the check matrix;

Cyclic differential family.

In some embodiments, the cyclic shift matrix is periodic.

In some embodiments, the first constraint block of each coupling segment adopts a Raptor-like structure.

In some embodiments, the adjacent row vectors of the 1st to nth rows of the submatrix formed by at least two constraint blocks concatenated by columns in each coupling segment satisfy non-orthogonality;

or,

The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

or,

The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

Among them, m>n≥2.

Specifically, the above-mentioned encoding device provided by the embodiment of the present disclosure can implement all the method steps implemented by the above-mentioned method embodiment in which the execution subject is an electronic device, and can achieve the same technical effect. The method in this embodiment will no longer be compared. The same parts and beneficial effects of the embodiments will be described in detail.

It should be noted that the division of units/modules in the above-mentioned embodiments of the present disclosure is schematic and is only a logical function division. In actual implementation, there may be other division methods. In addition, each functional unit in various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above integrated units can be implemented in the form of hardware or software functional units.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a processor-readable storage medium. based on With this understanding, the technical solution of the present disclosure is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, It includes several instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code. .

In some embodiments, a computer-readable storage medium is also provided, and the computer-readable storage medium stores a computer program. The computer program is used to cause the computer to execute the encoding method provided by the above method embodiments.

Specifically, the above-mentioned computer-readable storage medium provided by the embodiments of the present disclosure can implement all the method steps implemented by the above-mentioned method embodiments, and can achieve the same technical effect. No further reference will be made here to the method embodiments in this embodiment. The same parts and beneficial effects will be described in detail.

It should be noted that the computer-readable storage medium may be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (such as floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), Optical memory (such as CD, DVD, BD, HVD, etc.), and semiconductor memory (such as ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid state drive (SSD)), etc.

In addition, it should be noted that in the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances so that embodiments of the present disclosure can be practiced in sequences other than those illustrated or described herein, and that "first" and "second" are distinguished objects It is usually one type, and the number of objects is not limited. For example, the first object can be one or multiple.

In the embodiment of this disclosure, the term "and/or" describes the association relationship of associated objects, indicating that The existence of three relationships, for example, A and/or B, can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the related objects are in an "or" relationship.

In the embodiment of this disclosure, the term "plurality" refers to two or more than two, and other quantifiers are similar to it.

The technical solutions provided by the embodiments of the present disclosure can be applied to a variety of systems, especially 5G systems. For example, applicable systems can be global system of mobile communication (GSM) system, code division multiple access (code division multiple access, CDMA) system, wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) general packet Wireless service (general packet radio service, GPRS) system, long term evolution (long term evolution, LTE) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, Advanced long term evolution (long term evolution advanced, LTE-A) system, universal mobile telecommunication system (UMTS), global interoperability for microwave access (WiMAX) system, 5G New Radio, NR) system, etc. These various systems include terminal equipment and network equipment. The system can also include the core network part, such as the Evolved Packet System (EPS), 5G system (5GS), etc.

The terminal device involved in the embodiments of the present disclosure may be a device that provides voice and/or data connectivity to users, a handheld device with a wireless connection function, or other processing devices connected to a wireless modem, etc. In different systems, the names of terminal equipment may also be different. For example, in a 5G system, the terminal equipment may be called User Equipment (UE). Wireless terminal equipment can communicate with one or more core networks (Core Network, CN) via a Radio Access Network (RAN). The wireless terminal equipment can be a mobile terminal equipment, such as a mobile phone (also known as a "cellular phone"). ” telephone) and computers with mobile terminal devices, which may be, for example, portable, pocket-sized, handheld A mobile device built into a computer or vehicle that exchanges voice and/or data with a wireless access network. For example, Personal Communication Service (PCS) phones, cordless phones, Session Initiated Protocol (SIP) phones, Wireless Local Loop (WLL) stations, Personal Digital Assistants, PDA) and other equipment. Wireless terminal equipment may also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, or an access point. , remote terminal equipment (remote terminal), access terminal equipment (access terminal), user terminal equipment (user terminal), user agent (user agent), user device (user device), are not limited in the embodiments of the present disclosure.

The network device involved in the embodiment of the present disclosure may be a base station, and the base station may include multiple cells that provide services for terminals. Depending on the specific application, a base station can also be called an access point, or it can be a device in the access network that communicates with wireless terminal equipment through one or more sectors on the air interface, or it can be named by another name. The network device may be used to exchange received air frames with Internet Protocol (IP) packets and act as a router between the wireless terminal device and the rest of the access network, where the remainder of the access network may include the Internet Protocol (IP) communication network. Network devices also coordinate attribute management of the air interface. For example, the network equipment involved in the embodiments of the present disclosure may be a network equipment (Base Transceiver Station, BTS) in Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA). ), or it can be a network device (NodeB) in a Wide-band Code Division Multiple Access (WCDMA), or an evolutionary network device in a long term evolution (LTE) system (evolutional Node B, eNB or e-NodeB), 5G base station (gNB) in the 5G network architecture (next generation system), or Home evolved Node B (HeNB), relay node (relay node) , home base station (femto), pico base station (pico), etc., are not limited in the embodiments of the present disclosure. In some network structures, The network device may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and the distributed unit may also be arranged geographically separately.

“Determining B based on A” in this disclosure means that the factor A should be considered when determining B. It is not limited to "B can be determined based on A alone", but also includes: "B is determined based on A and C", "B is determined based on A, C and E", "C is determined based on A, and B is further determined based on C" wait. In addition, it can also include taking A as a condition for determining B, for example, "When A meets the first condition, use the first method to determine B"; another example, "When A meets the second condition, determine B", etc.; another example , "When A meets the third condition, determine B based on the first parameter" and so on. Of course, it can also be a condition that uses A as a factor to determine B, for example, "when A meets the first condition, use the first method to determine C, and further determine B based on C" and so on.

Network equipment and terminal equipment can each use one or more antennas for multi-input multi-output (MIMO) transmission. MIMO transmission can be single-user MIMO (Single User MIMO, SU-MIMO) or multi-user MIMO. (Multiple User MIMO,MU-MIMO). Depending on the shape and number of root antenna combinations, MIMO transmission can be 2D-MIMO, 3D-MIMO, FD-MIMO or massive-MIMO, or it can be diversity transmission, precoding transmission or beamforming transmission, etc.

Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) embodying computer-usable program code therein.

The disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and processes can be implemented by computer-executable instructions. The combination of processes and/or blocks in diagrams and/or block diagrams. These computer-executable instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a process or processes of a flowchart and/or a block or blocks of a block diagram.

These processor-executable instructions may also be stored in a processor-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the generation of instructions stored in the processor-readable memory includes the manufacture of the instruction means product, the instruction device implements the function specified in one process or multiple processes in the flow chart and/or one block or multiple blocks in the block diagram.

These processor-executable instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby causing the computer or other programmable device to The instructions that are executed provide steps for implementing the functions specified in a process or processes of the flowchart diagrams and/or a block or blocks of the block diagrams.

Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims (22)

1. A coding method that includes:

   Generate a basis matrix for the spatially coupled low-density parity check code SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

   Encoding is performed based on the basis matrix.
2. The encoding method according to claim 1, wherein the encoding based on the basis matrix includes:

   Determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

   Determine the verification constraint relationship according to the verification matrix;

   Determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

   Rate matching is performed on the mother code codeword to determine the encoded codeword.
3. The encoding method according to claim 2, wherein performing rate matching on the mother code codeword to determine the encoding codeword includes:

   Write the mother code codeword into a row according to the coded bits in each coupling section, and write it into the circular buffer of the rate matcher;

   Read the required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched encoded codewords.
4. The encoding method according to claim 2, wherein before determining the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix, it further includes:

   The cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;

   Maximize the girth of the check matrix;

   Optimize the ring distribution of the check matrix;

   Cyclic differential family.
5. The encoding method according to claim 4, wherein the cyclic shift matrix is periodic.
6. The encoding method according to claim 1, wherein the first constraint block of each coupling segment adopts a Raptor-like structure.
7. The encoding method according to claim 1, wherein the adjacent row vectors of the 1st to nth rows of the sub-matrix formed by splicing at least two constraint blocks in each coupling segment by columns satisfy non-orthogonality;

   or,

   The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

   or,

   The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

   Among them, m>n≥2.
8. An electronic device including a memory, a transceiver, and a processor;

   Memory, used to store computer programs; transceiver, used to send and receive data under the control of the processor; processor, used to read the computer program in the memory and perform the following operations:

   Generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

   Encoding is performed based on the basis matrix.
9. The electronic device according to claim 8, wherein the encoding based on the basis matrix includes:

   Determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

   Determine the verification constraint relationship according to the verification matrix;

   Determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

   Rate matching is performed on the mother code codeword to determine the encoded codeword.
10. The electronic device according to claim 9, wherein performing rate matching on the mother code codeword to determine the encoded codeword includes:

    Write the mother code codeword into a row according to the coded bits in each coupling section, and write it into the circular buffer of the rate matcher;

    Read the required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched encoded codewords.
11. The electronic device according to claim 9, wherein before determining the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix, the method further includes:

    The cyclic shift matrix is determined based on a target criterion; the target criterion includes one or more of the following criteria;

    Maximize the girth of the check matrix;

    Optimize the ring distribution of the check matrix;

    Cyclic differential family.
12. The electronic device of claim 11, wherein the cyclic shift matrix is periodic.
13. The electronic device according to claim 8, wherein the first constraint block of each coupling section adopts a Raptor-like structure.
14. The electronic device according to claim 8, wherein the adjacent row vectors of the 1st to nth rows of the sub-matrix formed by splicing the at least two constraint blocks in each coupling section by columns satisfy non-orthogonality;

    or,

    The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

    or,

    Each coupling segment contains at least two constraint blocks spliced into the submatrix by columns. The adjacent row vectors from m+1 to the last row satisfy complete orthogonality;

    Among them, m>n≥2.
15. An encoding device comprising:

    A generation module, used to generate a basis matrix of SC-LDPC; the basis matrix includes L coupling segments, each coupling segment includes at least two constraint blocks; each constraint block is a rate-compatible structure;

    An encoding module, used for encoding based on the base matrix.
16. The encoding device according to claim 15, wherein the encoding module includes a first determining sub-module, a second determining sub-module, a third determining sub-module and a rate matching sub-module;

    The first determination sub-module is used to determine the check matrix of the SC-LDPC according to the base matrix and a predetermined cyclic shift matrix;

    The second determination sub-module is used to determine the verification constraint relationship according to the verification matrix;

    The third determination sub-module is used to determine the mother code codeword according to the relationship between the bits to be transmitted and the check constraint;

    The rate matching sub-module is used to perform rate matching on the mother code codeword to determine the encoding codeword.
17. The encoding device according to claim 16, wherein the rate matching sub-module includes a writing unit and a reading unit;

    The writing unit is used to write the mother code codeword into a row of coded bits in each coupling segment into a circular buffer of the rate matcher;

    The reading unit is configured to read required bits from the circular buffer in a first-in-first-out and column-reading manner to obtain rate-matched codewords.
18. The encoding device according to claim 16, wherein the device further comprises a determination module;

    The determination module is configured to determine the cyclic shift matrix based on a target criterion; the target criterion includes one or more of the following criteria;

    Maximize the girth of the check matrix;

    Optimize the ring distribution of the check matrix;

    Cyclic differential family.
19. The encoding device according to claim 18, wherein the cyclic shift matrix is periodic.
20. The encoding device according to claim 15, wherein the first constraint block of each coupling section adopts a Raptor-like structure.
21. The encoding device according to claim 15, wherein the adjacent row vectors of the 1st to nth rows of the sub-matrix formed by splicing at least two constraint blocks in each coupling section by columns satisfy non-orthogonality;

    or,

    The adjacent row vectors of the n+1 to mth rows of the submatrix formed by concatenating at least two constraint blocks in each coupling section satisfy quasi-orthogonality;

    or,

    The adjacent row vectors from the m+1th to the last row of the submatrix formed by splicing at least two constraint blocks in each coupling segment satisfy complete orthogonality;

    Among them, m>n≥2.
22. A computer-readable storage medium stores a computer program, and the computer program is used to cause a computer to execute the encoding method described in any one of claims 1 to 7.