WO2024000324A1 - 铁电存储阵列及其制备方法、存储器、电子设备 - Google Patents

铁电存储阵列及其制备方法、存储器、电子设备 Download PDF

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WO2024000324A1
WO2024000324A1 PCT/CN2022/102541 CN2022102541W WO2024000324A1 WO 2024000324 A1 WO2024000324 A1 WO 2024000324A1 CN 2022102541 W CN2022102541 W CN 2022102541W WO 2024000324 A1 WO2024000324 A1 WO 2024000324A1
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ferroelectric
electrode
layer
resistive
memory array
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PCT/CN2022/102541
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English (en)
French (fr)
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谭万良
许俊豪
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华为技术有限公司
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Priority to PCT/CN2022/102541 priority Critical patent/WO2024000324A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

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  • the present application relates to the field of semiconductor technology, and in particular to a ferroelectric memory array and its preparation method, memory, and electronic equipment.
  • Ferroelectric Random Access Memory (Ferroelectric Random Access Memory, English abbreviation: FeRAM, Chinese abbreviation: Ferroelectric Memory) is widely used in memory chips due to its non-volatile data storage and fast access rate.
  • a ferroelectric memory has a plurality of memory cells, and each memory cell includes a ferroelectric capacitor.
  • the ferroelectric capacitor includes two electrodes disposed oppositely, and a ferroelectric material disposed between the two electrodes, that is, the ferroelectric capacitor
  • the capacitor has a metal-ferroelectric-metal (MFM) structure.
  • Ferroelectric materials have a ferroelectric effect, that is, the electric field generated by two electrodes is applied to the ferroelectric material, and the ferroelectric domains in the ferroelectric material form polarization charges under the action of the electric field. When the electric field is reversed, the ferroelectric domain undergoes directional flipping. The polarization charge energy formed by the ferroelectric domain before and after the electric field is reversed is different. This binary stable state (positive and negative polarization state) will make the ferroelectric domain
  • SA external sense amplifier
  • ferroelectric materials are also pyroelectric materials. That is, as the temperature increases, the phonons generated in the ferroelectric material will interfere with the directional flipping of the ferroelectric domain. Under the same operating voltage, the ferroelectric material The residual polarization (Remnant Polarization, Pr for short) will gradually decrease, and the two states of "0" or "1" will become closer and closer, resulting in a reduction in the distinction between the positive and negative polarization states of ferroelectric materials, and finally it will become difficult to The difference increases the error rate of reading and writing data in the ferroelectric memory, that is, the ferroelectric memory has a thermal stability problem.
  • Embodiments of the present application provide a ferroelectric memory array and its preparation method, memory, and electronic equipment, which are used to improve the thermal stability of the memory.
  • a ferroelectric memory array in the first aspect, can have a two-dimensional structure or a three-dimensional structure. Moreover, the ferroelectric memory array can be applied to ferroelectric memory or ferroelectric field-effect transistor (FeFET) memory to achieve reading and writing of data.
  • FeFET ferroelectric field-effect transistor
  • the above-mentioned ferroelectric memory array includes a plurality of memory cells arranged in an array, and each memory unit includes a ferroelectric capacitor and a transistor.
  • the ferroelectric capacitor includes a first electrode and a second electrode arranged oppositely, and a ferroelectric layer arranged between the first electrode and the second electrode.
  • the ferroelectric capacitor further includes at least one resistive switching layer disposed between the ferroelectric layer and the first electrode, and/or between the ferroelectric layer and the second electrode. The resistivity of the material of the resistive layer decreases as the temperature increases.
  • a resistive switching layer is provided between the ferroelectric layer and the electrode (the first electrode and/or the second electrode), and the ferroelectric layer and the resistive switching layer form a series circuit. Since the resistivity of the material of the resistive variable layer decreases with the increase of temperature, the resistance of the resistive variable layer decreases with the increase of temperature.
  • the resistance of the resistive layer is larger. According to the principle of series voltage division, the operating voltage applied to the ferroelectric layer is smaller. In this case, the remaining electrodes of the ferroelectric material of the ferroelectric layer The strength is enough to distinguish the storage state of "0" or "1", ensuring the normal operation of the ferroelectric memory.
  • the resistance of the resistive layer decreases.
  • the operating voltage applied to the ferroelectric layer increases, which can increase the ferroelectric layer.
  • the polarization intensity and residual polarization intensity of electrical materials compensate for the decrease in polarization intensity and residual polarization intensity of ferroelectric materials as the temperature increases, thereby improving the positive performance of ferroelectric materials at higher operating temperatures. Differentiation of negative polarization states to improve the thermal stability of ferroelectric memories.
  • the material of the resistive layer includes at least one of amorphous silicon, amorphous carbon, and germanium. These materials all have the characteristic that the resistivity decreases with increasing temperature.
  • the material of the resistive layer includes doping elements, and the doping elements are at least one of boron ions, gallium ions, nitrogen ions, phosphorus ions, arsenic ions, beryllium ions, and calcium ions.
  • the resistivity of the material of the resistive switching layer is adjusted to adjust the change rate of the resistance of the resistive switching layer as the temperature increases, thereby adjusting the operating voltage as the temperature increases.
  • the increased rate of change matches the rate of change in which the remnant polarization intensity of ferroelectric materials decreases with increasing temperature, so that the remnant polarization intensity of ferroelectric materials remains approximately unchanged or floats within the allowable value range. , to ensure the thermal stability of ferroelectric memory.
  • the concentration of the doping element in the material of the resistive layer ranges from 1 ⁇ 10 15 to 1 ⁇ 10 21 .
  • the resistivity of the material of the resistive variable layer can be determined by controlling the concentration of the doping element, thereby determining the rate of change of the resistance of the resistive variable layer with temperature.
  • the change in operating voltage can compensate for the change in the residual polarization intensity of the ferroelectric material, ensuring that the residual polarization intensity of the ferroelectric material remains roughly unchanged or floats within the allowable value range, thereby ensuring the thermal stability of the ferroelectric memory.
  • the material of the resistive layer has metal-insulator phase change characteristics. At a lower operating temperature, this type of material has insulator characteristics, that is, its resistivity is larger; at a higher operating temperature, the material has insulator characteristics. Similar materials have metallic properties, that is, their resistivity is small. Utilizing this phase change characteristic, the operating voltage applied to the ferroelectric layer can be regulated through the resistance change of the resistive layer.
  • the material of the resistive layer includes at least one of vanadium oxide, perovskite transition metal oxide, and germanium antimony tellurium alloy.
  • the thickness of the resistive switching layer ranges from 0.5 nm to 10 nm.
  • the ferroelectric capacitor further includes a barrier layer disposed between the resistive layer and the ferroelectric layer.
  • the barrier layer when ions are doped in the resistive layer, can play the role of blocking isolators, inhibiting the diffusion of ions in the resistive layer into the ferroelectric layer, and preventing ions from accumulating in the ferroelectric layer to form metal.
  • Thin wires are beneficial to reducing leakage current in ferroelectric capacitors and preventing breakdown of ferroelectric capacitors.
  • the material of the barrier layer includes at least one of titanium nitride, tantalum nitride, and tungsten.
  • the barrier layer is in contact with the ferroelectric layer, and the material of the barrier layer should have good compatibility with the material of the ferroelectric layer, that is, the selection of the material of the barrier layer will not affect the directional flipping of the ferroelectric domains in the ferroelectric layer. .
  • the first electrode and the second electrode are planar electrodes, and the first electrode, the ferroelectric layer, the resistive layer and the second electrode are stacked. That is, the structure of the ferroelectric capacitor is a two-dimensional planar structure, which is simple and easy to prepare.
  • the first electrode is a planar electrode
  • the second electrode is a columnar electrode
  • the second electrode penetrates the first electrode
  • the ferroelectric layer and the resistive layer are arranged around the second electrode.
  • the ferroelectric capacitor adopts a three-dimensional vertical structural design, which can reduce its occupied area in the plane, thereby increasing the number of ferroelectric capacitors per unit area in the plane, so as to increase the efficiency of the memory unit per unit area. Setting the number will help improve the storage density of the memory.
  • the first electrode and the second electrode are planar electrodes, and one of the first electrode and the second electrode is electrically connected to the transistor to form a memory cell.
  • the first electrode is a planar electrode
  • the second electrode is a columnar electrode
  • the second electrode is electrically connected to the transistor to form a memory cell.
  • a method for preparing a ferroelectric memory array includes: sequentially forming a first electrode, a ferroelectric layer and a second electrode. After forming the first electrode and before forming the ferroelectric layer, the method further includes forming a resistive switching layer. And/or, after forming the ferroelectric layer and before forming the second electrode, the method further includes: forming a resistive switching layer. The resistivity of the material of the resistive layer decreases as the temperature increases.
  • a resistive switching layer is inserted between the ferroelectric layer and the electrode (the first electrode and/or the second electrode), and the ferroelectric layer and the resistive switching layer form a series circuit. Since the resistivity of the material of the resistive variable layer decreases with the increase of temperature, the resistance of the resistive variable layer decreases with the increase of temperature.
  • the resistance of the resistive layer decreases.
  • the operating voltage applied to the ferroelectric layer increases, which can increase the ferroelectric layer.
  • the polarization intensity and residual polarization intensity of electrical materials compensate for the decrease in polarization intensity and residual polarization intensity of ferroelectric materials as the temperature increases, thereby improving the positive performance of ferroelectric materials at higher operating temperatures. Differentiation of negative polarization states to improve the thermal stability of ferroelectric memories.
  • sequentially forming the first electrode, the ferroelectric layer, and the second electrode includes: forming a stacked first electrode, the ferroelectric layer, and the second electrode to form a two-dimensional planar structure ferroelectric capacitor.
  • sequentially forming the first electrode, the ferroelectric layer and the second electrode includes: forming the first electrode.
  • a via hole is formed through the first electrode.
  • a ferroelectric layer is formed on the sidewalls of the via.
  • a second electrode is formed inside the ferroelectric layer to form a ferroelectric capacitor with a three-dimensional vertical structure.
  • forming the resistive switching layer includes: using a deposition process to form the resistive switching layer.
  • the method further includes: performing an in-situ doping process or an ion implantation process on the resistive variable layer to dope elements in the resistive variable layer to adjust the resistivity of the material of the resistive variable layer.
  • a barrier layer is formed between the resistive layer and the ferroelectric layer.
  • the barrier layer can inhibit the diffusion of ions in the resistive layer into the ferroelectric layer, preventing ions from accumulating in the ferroelectric layer to form metal filaments, which is beneficial to reducing leakage current in the ferroelectric capacitor and preventing the occurrence of defects in the ferroelectric capacitor. breakdown.
  • a memory which includes the ferroelectric memory array described in any of the above embodiments, and a controller electrically connected to the ferroelectric memory array.
  • an electronic device is provided.
  • the electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product.
  • the electronic device includes a circuit board and the memory described in the above embodiment.
  • the memory is disposed on the circuit board and is electrically connected to the circuit board.
  • Figure 1 is an architectural diagram of an electronic device according to some embodiments.
  • Figure 2 is an exploded view of an electronic device according to some embodiments.
  • Figure 3 is an architectural diagram of a ferroelectric memory according to some embodiments.
  • Figure 4 is a circuit diagram of a memory cell according to some embodiments.
  • Figure 5 is a structural diagram of a ferroelectric capacitor in the related art
  • Figure 6 is a schematic diagram of the directional flipping of ferroelectric domains in the ferroelectric layer of a ferroelectric capacitor
  • Figure 7 is a graph showing the relationship between the PV hysteresis loop of the ferroelectric layer and temperature
  • Figure 8 is a schematic diagram of the thermal annealing process of the ferroelectric layer
  • Figure 9 is a schematic diagram of generating metal filaments in the ferroelectric layer
  • Figure 10 is a schematic diagram of the generation of oxygen vacancies in the ferroelectric layer
  • Figure 11 is a schematic diagram of the conductive path formed by oxygen vacancies in the ferroelectric layer
  • Figures 12A to 12C are structural diagrams of various ferroelectric capacitors according to some embodiments.
  • Figure 13 is an equivalent circuit diagram of the ferroelectric capacitor in Figure 12A;
  • Figure 14 shows a graph of resistivity versus temperature of vanadium oxide
  • Figures 15A to 15C are structural diagrams of various ferroelectric capacitors according to some embodiments.
  • Figures 16A to 16F are diagrams of steps for preparing a ferroelectric capacitor according to some embodiments.
  • Figure 17 is a three-dimensional vertical structural diagram of a ferroelectric capacitor according to some embodiments.
  • 18A to 18D are diagrams of various steps of preparing a ferroelectric capacitor according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of this application, unless otherwise specified, "plurality” means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A Combinations with B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • “approximately” includes the stated value as well as an average within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the relationship between Determined by the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system).
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Unit cell It is a structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.
  • Ferroelectric phase crystal The structure of the unit cell causes the positive and negative charge centers to not overlap and an electric dipole moment appears, resulting in an electric polarization intensity that is not equal to zero, making the crystal spontaneously polarized, and the direction of the electric dipole moment can be changed by an external electric field. , showing characteristics similar to ferromagnets.
  • Crystal lattice The atoms inside the crystal are arranged according to certain geometric rules.
  • the spatial grid in which the atoms are arranged regularly is called a crystal lattice.
  • Phonons Normal mode energy quanta of lattice vibrations.
  • Ferroelectric materials They can maintain spontaneous polarization by aligning their internal electric dipole moments with an applied electric field, even when the externally applied electric field is removed.
  • a ferroelectric is a material in which the polarization value (or electric field) remains semi-permanently, even after a constant voltage is applied and the voltage returns to zero volts.
  • Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (Personal Digital Assistant, PDA for short), a television, a smart wearable product (for example, a smart watch, a smart bracelet) ), Virtual Reality (VR) terminal equipment, Augmented Reality (AR) terminal equipment, rechargeable small household appliances (such as soymilk machines, sweeping robots), drones, radars, aerospace equipment and vehicle-mounted Different types of user equipment or terminal equipment such as equipment; the electronic equipment can also be network equipment such as base stations.
  • PDA Personal Digital Assistant
  • PDA Personal Digital Assistant
  • TV a smart wearable product
  • AR Augmented Reality
  • portable small household appliances such as soymilk machines, sweeping robots
  • drones radars
  • aerospace equipment aerospace equipment and vehicle-mounted
  • the embodiments of the present application do not place any special restrictions on the specific form of the electronic device.
  • Figure 1 is an architectural diagram of an electronic device according to some embodiments.
  • the electronic device 1 includes: a storage device 11 , a processor 12 , an input device 13 , an output device 14 and other components.
  • a storage device 11 the electronic device 1 includes: a storage device 11 , a processor 12 , an input device 13 , an output device 14 and other components.
  • the architecture of the electronic device 1 shown in Figure 1 does not constitute a limitation on the electronic device 1, and the electronic device 1 may include more or less components than those shown in Figure 1 , or some of the components shown in Figure 1 may be combined, or may be arranged differently from the components shown in Figure 1 .
  • the storage device 11 is used to store software programs and modules.
  • the storage device 11 mainly includes a storage program area and a storage data area, wherein the storage program area can store and back up an operating system, at least one application program required for a function (such as a sound playback function, an image playback function, etc.), etc.; the storage data area can store Data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.) and the like are stored.
  • the storage device 11 includes an external memory 111 and an internal memory 112 . Data stored in the external memory 111 and the internal memory 112 can be transferred to each other.
  • the external memory 111 may include, for example, a hard disk, a USB disk, a floppy disk, etc.
  • the internal memory 112 may include, for example, random access memory (Random Access Memory, RAM for short), read-only memory (Read-Only Memory, ROM for short), etc., wherein the random access memory may include, for example, ferroelectric memory, phase change memory, or Magnetic memory, etc.
  • the processor 12 is the control center of the electronic device 1, using various interfaces and lines to connect various parts of the entire electronic device 1, by running or executing software programs and/or modules stored in the storage device 11, and by calling the software programs and/or modules stored in the storage device 11.
  • the data in the device 11 executes various functions of the electronic device 1 and processes data, thereby overall monitoring the electronic device 1 .
  • the processor 12 may include one or more processing units.
  • the processor 12 may include an application processor (Application Processor, AP for short), a modem processor, a graphics processor (Graphics Processing Unit, GPU for short), etc. Among them, different processing units can be independent devices or integrated in one or more processors.
  • the processor 12 can integrate an application processor and a modem processor, where the application processor mainly processes operating systems, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 12 .
  • the above-mentioned application processor may be, for example, a central processing unit (Central Processing Unit, CPU for short).
  • the processor 12 is a CPU as an example.
  • the CPU may include a calculator 121 and a controller 122 .
  • the arithmetic unit 121 obtains the data stored in the internal memory 112 and processes the data stored in the internal memory 112. The processed result is usually sent back to the internal memory 112.
  • the controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory 111 and the internal memory 112 to read or write data.
  • the input device 13 is used to receive input numeric or character information and generate key signal input related to user settings and function control of the electronic device.
  • the input device 13 may include a touch screen and other input devices.
  • the touch screen also known as the touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen using fingers, stylus, or any suitable objects or accessories), and perform operations based on preset settings.
  • the program drives the corresponding connection device.
  • the controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive the input signal or not to receive the input signal.
  • the input numeric or character information received by the input device 13 and the key signal input generated related to user settings and function control of the electronic device may be stored in the internal memory 112 .
  • the output device 14 is used to output the input of the input device 13 and store signals corresponding to the data in the internal memory 112 .
  • the output device 14 outputs a sound signal or a video signal.
  • the controller 122 in the above-mentioned processor 12 can also control the output device 14 to output a signal or not to output a signal.
  • the thick arrows in Figure 1 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission.
  • a single arrow between the input device 13 and the internal memory 112 indicates that data received by the input device 13 is transmitted to the internal memory 112 .
  • the double arrow between the operator 121 and the internal memory 112 indicates that the data stored in the internal memory 112 can be transferred to the operator 121 , and the data processed by the operator 121 can be transferred to the internal memory 112 .
  • the thin arrows in Figure 1 indicate components that controller 122 can control.
  • the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.
  • the following is an exemplary introduction taking the electronic device 1 as a mobile phone.
  • Figure 2 is an exploded view of an electronic device according to some embodiments.
  • the electronic device 1 may also include a middle frame 15 , a rear case 16 and a display screen 17 .
  • the back shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are disposed in the back shell 16 .
  • the middle frame 15 includes a bearing plate 150 for bearing the display screen 17 and a frame 151 surrounding the bearing plate 150 .
  • the electronic device 1 may further include a circuit board 18 , which is disposed on a side of the carrier plate 150 close to the rear case 16 .
  • the internal memory 112 in the electronic device 1 may be disposed on the circuit board 18 .
  • the memory 112 is electrically connected to the circuit board 18 .
  • ferroelectric memory As a new type of memory, ferroelectric memory has become one of the mainstream internal memories due to its non-volatile data storage, fast access rate, low read and write voltage, low power consumption, small device size, good cycle performance and radiation resistance. one.
  • the internal memory 112 involved in this application is not limited to a ferroelectric memory, and may also be a ferroelectric field effect transistor memory.
  • FIG. 3 is an architectural diagram of a ferroelectric memory according to some embodiments.
  • the internal memory 112 includes a ferroelectric memory array 210 , a decoder 220 , a driver 230 , a controller (timing controller) 240 , a buffer 250 and an input/output interface 260 .
  • the ferroelectric memory array 210 includes a plurality of memory cells 200 arranged in an array.
  • Figure 4 is a circuit diagram of a memory cell according to some embodiments.
  • the memory unit 200 includes a circuit architecture based on a ferroelectric capacitor.
  • the memory unit 200 has a 1T1C (1-transistor-1-capacitor) structure, that is, the memory unit 200 includes a transistor T and a ferroelectric capacitor C.
  • the transistor T The source is electrically connected to the Bit Line (BL), the drain is electrically connected to one electrode of the ferroelectric capacitor C, the gate is electrically connected to the Word Line (WL), and the other electrode of the ferroelectric capacitor C One electrode is electrically connected to a plate line (PL).
  • the circuit architecture of the memory unit 200 in the embodiment of the present application is not limited to this.
  • the above-described decoder 220 can decode according to the received address to determine the memory unit 200 in the ferroelectric memory array 210 that needs to be accessed.
  • the driver 230 is used to generate a control signal according to the decoding result output by the decoder 220.
  • the control signal is transmitted to the gate of the transistor T in the memory unit 200 through the word line WL to control the transistor T to turn on or off, thereby achieving the specified Access to storage unit 200.
  • the buffer 250 receives the data signal output by the memory unit 200 through the board line PL, and is used to buffer the data signal. For example, First-In First-Out (FIFO) may be used for buffering.
  • the timing controller 240 is used to control the timing of the buffer 250 and control the driver 230 to drive the ferroelectric memory array 210 .
  • the input/output interface 260 is used to transmit data signals, such as receiving data signals or sending data signals.
  • the above-mentioned ferroelectric memory array 210, decoder 220, driver 230, timing controller 240, buffer 250 and input/output interface 260 can be integrated into one chip, or can be integrated into multiple chips respectively.
  • Figure 5 is a structural diagram of a ferroelectric capacitor in the related art
  • Figure 6 is a schematic diagram of directional flipping of ferroelectric domains in the ferroelectric layer of the ferroelectric capacitor.
  • the ferroelectric capacitor C' includes a first electrode 01' and a second electrode 02' arranged oppositely, and a ferroelectric layer 03' disposed between the first electrode 01' and the second electrode 02'.
  • the ferroelectric capacitor C' has an MFM structure.
  • the ferroelectric layer 03' includes ferroelectric material, and the ferroelectric material has spontaneous polarization characteristics.
  • the ferroelectric material has a ferroelectric phase crystal.
  • the electric field is applied to the ferroelectric layer 03'.
  • the central atom of the ferroelectric phase crystal in the ferroelectric material moves along the electric field and stops in a low energy state, which can be, for example, a "0" storage state.
  • the central atom moves in the crystal along the direction of the electric field and stops in another low energy state, which state is for example It can be a "1" storage state, that is, the ferroelectric domain is directionally flipped under the action of a reversing electric field.
  • FIG. 7 is a graph showing the relationship between the PV hysteresis loop of the ferroelectric layer and temperature, where the ordinate is the polarization intensity of the ferroelectric material ( Polarization), the unit is “ ⁇ C/cm 2 ”; the abscissa is the operating voltage (Voltage) applied to the ferroelectric material, the unit is “V”.
  • the polarization intensity and residual polarization intensity of ferroelectric materials are larger, which is enough to distinguish the storage state of "0" or "1".
  • the operating temperature increases, if the operating voltage remains unchanged, the residual polarization intensity of the ferroelectric material will gradually decrease, the coercive field will increase, and the two states of "0" or “1" will become closer and closer.
  • the distinction between the positive and negative polarization states of the ferroelectric material is reduced, and finally becomes difficult to distinguish, which increases the error rate of reading and writing data in the ferroelectric memory, that is, the ferroelectric memory has a thermal stability problem.
  • the usually defined operating temperature range of ferroelectric memory is 25°C ⁇ 125°C, which means that the ferroelectric memory should maintain normal operation at 125°C.
  • the residual polarization intensity of the ferroelectric material is small, resulting in the indistinguishability of the two states "0" or "1", resulting in errors in reading and writing data to the ferroelectric memory. rate increases, causing thermal stability problems.
  • a thermal annealing process can be used to change the phase composition of the system in the ferroelectric material of the ferroelectric layer 03', such as changing the crystal orientation of the ferroelectric phase crystal to make the system more stable, thereby improving the performance of the ferroelectric memory. Thermal stability.
  • Figure 8 is a schematic diagram of the thermal annealing process of the ferroelectric layer
  • Figure 9 is a schematic diagram of the generation of metal filaments in the ferroelectric layer
  • Figure 10 is a schematic diagram of the generation of oxygen vacancies in the ferroelectric layer
  • Figure 11 is the formation of oxygen vacancies in the ferroelectric layer Schematic diagram of a conductive path.
  • the crystallographic orientation of the ferroelectric phase crystal in the ferroelectric layer 03' is orthorhombic.
  • the ferroelectric layer 03' will produce tetragonal and monoclinic phases.
  • Ferroelectric phase crystals of the Monoclinic phase that is, the ferroelectric layer 03' includes ferroelectric phase crystals such as orthorhombic phase, tetragonal phase and monoclinic phase, and the ferroelectric material is in the form of polycrystalline.
  • a common method in the field is to increase the temperature of the thermal annealing process, so that in the crystallized ferroelectric materials, the number of orthorhombic ferroelectric phase crystals accounts for a larger proportion, and the number of tetragonal and monoclinic ferroelectric phase crystals accounts for a larger proportion.
  • the quantity ratio is small, so that as the temperature increases, the phenomenon of the reduction of the residual polarization intensity of the ferroelectric material is improved, so as to improve the thermal stability of the ferroelectric memory.
  • the inventor of this application found that it is theoretically feasible to promote the crystallization of orthorhombic ferroelectric phase crystals by increasing the temperature of the thermal annealing process.
  • the crystallization of ferroelectric materials is based on the interaction between thermodynamics and kinetics.
  • the crystallization process conditions should meet both thermodynamic and kinetic requirements, which increases the process difficulty for crystallizing orthorhombic ferroelectric phase crystals.
  • the ferroelectric layer 03' is formed on the first electrode 01'.
  • the first electrode 01' The metal ions will move and diffuse into the ferroelectric layer 03'.
  • the metal ions will accumulate in the ferroelectric layer 03' to form "metal filaments" (also called conductive paths), which will eventually form a ferroelectric capacitor.
  • the increase in leakage current in C' can easily lead to breakdown of the ferroelectric capacitor C', thereby reducing the service life of the ferroelectric memory.
  • the ferroelectric material of the ferroelectric layer 03' includes oxygen-containing compounds.
  • the oxygen ions in the ferroelectric layer 03' will move and move towards the first electrode 01 'Medium diffusion, that is, the ferroelectric layer 03' acts as an oxygen ion donor, and the first electrode 01' acts as an oxygen ion acceptor, causing positively charged oxygen vacancies to be generated inside the ferroelectric layer 03'.
  • the gradual accumulation of oxygen vacancies will also form a conductive path, which will lead to an increase in the leakage current in the final ferroelectric capacitor C', which will easily lead to the breakdown of the ferroelectric capacitor C', thus leading to the use of ferroelectric memory. Lifespan is reduced.
  • a compensation method for operating voltage is also provided, as follows:
  • a temperature sensor is used to monitor changes in the operating temperature and the monitoring results are fed back to the driver.
  • the driver can adjust the size and pulse width of the operating voltage according to changes in the operating temperature to improve the performance of the ferroelectric memory.
  • Thermal stability issues However, the introduction of temperature sensors will occupy the chip area, which is not conducive to chip size reduction, thereby affecting the chip's product competitiveness.
  • Figures 12A to 12C are structural diagrams of various ferroelectric capacitors according to some embodiments;
  • Figure 13 is the equivalent of the ferroelectric capacitor in Figure 12A Circuit diagram.
  • the ferroelectric capacitor C includes a first electrode 01 and a second electrode 02 arranged opposite each other, and a ferroelectric layer 03 and a resistive layer 04 located between the first electrode 01 and the second electrode 02 .
  • the material of the first electrode 01 and the second electrode 02 includes at least one of titanium nitride, tantalum nitride, and tungsten.
  • the material of the ferroelectric layer 03 includes hafnium oxide-based materials.
  • the hafnium oxide-based materials may include Hafnium Zirconium Oxide (HZO), Hafnium Silicon Oxide (HSO), Hafnium Aluminum Oxide, and Hafnium Lanthanum.
  • HZO Hafnium Zirconium Oxide
  • HSO Hafnium Silicon Oxide
  • Hfnium Aluminum Oxide Hafnium Lanthanum.
  • hafnium oxide-based materials have stable ferroelectric flipping properties, which can improve the charge and discharge performance of the ferroelectric capacitor C.
  • the thickness of the ferroelectric layer 03 can be reduced to ten nanometers or even sub-ten nanometers to realize the size reduction of the ferroelectric capacitor C, thereby achieving high-density integration or three-dimensional ferroelectric memory. Integration is conducive to building ultra-high-density memory chips.
  • the preparation process of ferroelectric capacitor C using hafnium oxide-based ferroelectric material has good compatibility with the preparation process of complementary metal oxide semiconductor (CMOS), and the preparation process of ferroelectric capacitor C is low. .
  • CMOS complementary metal oxide semiconductor
  • At least one resistive variable layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01 , which is equivalent to inserting the resistive variable layer 04 between the ferroelectric layer 03 and the first electrode 01 .
  • a resistive layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01 .
  • At least one resistive switching layer 04 is disposed between the ferroelectric layer 03 and the second electrode 02 , which is equivalent to inserting the resistive switching layer 04 between the ferroelectric layer 03 and the second electrode 02 .
  • a resistive layer 04 is disposed between the ferroelectric layer 03 and the second electrode 02 .
  • At least one resistive switching layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01 , and at least one resistive switching layer 04 is disposed between the ferroelectric layer 03 and the second electrode 02 . Equivalently, the resistive switching layer 04 is inserted between the ferroelectric layer 03 and the first electrode 01 , and the resistive switching layer 04 is inserted between the ferroelectric layer 03 and the second electrode 02 .
  • a resistive switching layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01
  • a resistive switching layer 04 is disposed between the ferroelectric layer 03 and the second electrode 02 .
  • the resistivity of the material of the resistive layer 04 decreases as the temperature increases.
  • the material of the resistive layer 04 has the characteristic that the resistivity decreases as the temperature increases.
  • "Operating temperature range” can be understood as the temperature range of scenarios in which ferroelectric memories are typically used.
  • the operating temperature range of ferroelectric memories is -10°C to 125°C.
  • the operating temperature of ferroelectric memories is -10°C. °C, 25°C, 50°C, 75°C, 95°C, 120°C or 125°C.
  • the ferroelectric capacitor C provided in the above embodiment of the application has a resistive layer 04 inserted between the ferroelectric layer 03 and the electrode (the first electrode 01 and/or the second electrode 02).
  • the ferroelectric capacitor C The electrical layer 03 and the resistive layer 04 form a series circuit.
  • the resistance of the ferroelectric layer 03 is R 1
  • the resistance of the resistive layer 04 is R 2
  • the total voltage applied between the first electrode 01 and the second electrode 02 is V.
  • the resistance R 2 of the resistive variable layer 04 decreases as the temperature increases.
  • the resistance R 2 of the resistive layer 04 is larger. According to the above formula It can be seen that the operating voltage V 1 applied to the ferroelectric layer 03 is small. In this case, the polarization intensity and residual polarization intensity of the ferroelectric material of the ferroelectric layer 03 are large enough to distinguish "0" or The storage state of "1" ensures the normal operation of the ferroelectric memory.
  • the resistive switching layer 04 is located between the ferroelectric layer 03 and the electrode, additional hardware (temperature sensor) is avoided, the cost of the product can be reduced, and no It will occupy the area of the chip and is conducive to shrinking the size of the chip.
  • the material of the resistive layer 04 includes at least one of amorphous silicon (amorphous silicon, a-Si for short), amorphous carbon (a-C for short), and germanium. These materials all have resistivity. Characteristics that decrease with increasing temperature.
  • the materials of the resistive layer 04 may also include Group III-V compounds (such as gallium arsenide, gallium phosphide, etc.), Group II-VI compounds (such as cadmium sulfide, zinc sulfide, etc.), metal oxides (such as manganese oxide) , chromium oxide, iron oxide, copper oxide, etc.), at least one of a solid solution composed of a III-V group compound and a II-VI group compound (such as gallium aluminum arsenic, gallium arsenic phosphorus, etc.).
  • Group III-V compounds such as gallium arsenide, gallium phosphide, etc.
  • Group II-VI compounds such as cadmium sulfide, zinc sulfide, etc.
  • metal oxides such as manganese oxide
  • chromium oxide iron oxide
  • copper oxide copper oxide
  • at least one of a solid solution composed of a III-V group compound and a II-VI group compound such as gallium aluminum
  • the material of the resistive switching layer 04 includes doping elements, that is, by doping elements in the resistive switching layer 04 , the resistivity of the material of the resistive switching layer 04 is adjusted to adjust the resistive switching layer 04
  • the change rate of the resistance of the ferroelectric material decreases with the increase of temperature, thereby adjusting the change rate of the operating voltage V 1 with the increase of temperature, so that it matches the change rate of the residual polarization intensity of the ferroelectric material that decreases with the increase of temperature.
  • the resistance of the resistive layer 04 decreases, the operating voltage applied to the ferroelectric layer 03 increases, and the residual polarization intensity of the ferroelectric material remains approximately unchanged, or Float within the allowed value range to ensure the thermal stability of the ferroelectric memory.
  • the doping elements in the material of the resistive layer 04 may be at least one of boron ions, gallium ions, nitrogen ions, phosphorus ions, arsenic ions, beryllium ions, and calcium ions.
  • the doping elements may be these.
  • the resistivity of the material of the resistive variable layer 04 is different, so that the resistance of the resistive variable layer 04 decreases with different change rates as the temperature increases.
  • the resistivity of the material of the resistive variable layer 04 can be determined by controlling the concentration of the doping element, thereby determining the change of the resistance R 2 of the resistive variable layer 04 with temperature. rate, so that the change in the operating voltage V 1 can compensate for the change in the residual polarization intensity of the ferroelectric material, ensuring that the residual polarization intensity of the ferroelectric material remains roughly unchanged, or floats within the allowed value range, thereby ensuring that the ferroelectric memory thermal stability.
  • the concentration range of the doping element in the material of the resistive layer 04 is 1 ⁇ 10 15 ⁇ 1 ⁇ 10 21 , for example, the concentration of the doping element is 1 ⁇ 10 15 , 1 ⁇ 10 16 , 1 ⁇ 10 18 , 1 ⁇ 10 20 or 1 ⁇ 10 21 .
  • the resistance R 2 of the resistive layer 04 can also be determined by controlling the thickness of the resistive layer 04 to change the operating voltage V 1 It can compensate for changes in the residual polarization intensity of the ferroelectric material, ensuring that the residual polarization intensity of the ferroelectric material remains roughly unchanged, or floats within an allowed value range, thereby ensuring the thermal stability of the ferroelectric memory.
  • the thickness of the resistive variable layer 04 ranges from 0.5 nm to 10 nm.
  • the thickness of the resistive variable layer 04 is 0.5 nm, 2 nm, 5 nm, 8 nm or 10 nm.
  • the material of the resistive layer 04 can also be made of materials with metal-insulator phase change characteristics. At lower operating temperatures, such materials have insulator characteristics, that is, their resistivity is larger; At high operating temperatures, this type of material has metallic properties, that is, its resistivity is small.
  • the operating voltage V 1 applied to the ferroelectric layer 03 can be adjusted through the resistance change of the resistive layer 04 .
  • the resistance R 2 of the resistive layer 04 is large, and the operating voltage V 1 applied to the ferroelectric layer 03 is small, but the residual polarization strength of the ferroelectric material is enough to distinguish "0" or "1" storage status.
  • the resistance R 2 of the resistive layer 04 is smaller, and the operating voltage V 1 applied to the ferroelectric layer 03 is larger, making the residual polarization intensity of the ferroelectric material larger, ensuring that " The storage state of 0" or "1" ensures the distinction between positive and negative polarization states to improve the thermal stability of ferroelectric memory.
  • the material of the resistive layer 04 may include at least one of vanadium oxide (chemical formula: VO x ), perovskite transition metal oxide, and germanium antimony tellurium alloy.
  • Figure 14 shows the relationship between the resistivity of vanadium oxide and temperature.
  • the ordinate is the resistivity of vanadium oxide (Resistivity), the unit is " ⁇ cm”; the abscissa is the temperature (Temperature), the unit is " °C”.
  • the "solid line” represents the change curve of the resistivity of vanadium oxide with increasing temperature under the temperature change condition of 1.3°C/min (increase of 1.3°C per minute). It can be seen that the resistivity of vanadium oxide decreases with the increase of temperature, and when the temperature reaches 79.2°C, the resistivity of vanadium oxide decreases fastest.
  • the “dashed line” represents the change curve of the resistivity of vanadium oxide with temperature increase under the temperature change condition of 5.3°C/min (increase of 5.3°C per minute). It can be seen that the resistivity of vanadium oxide decreases with the increase of temperature, and when the temperature reaches 82.6°C, the resistivity of vanadium oxide decreases fastest.
  • FIGS. 15A to 15C are structural diagrams of various ferroelectric capacitors according to some embodiments.
  • the ferroelectric capacitor C further includes a barrier layer 05 , which is disposed between the resistive layer 04 and the ferroelectric layer 03 .
  • the barrier layer 05 can play the role of blocking isolators, inhibiting the diffusion of ions in the resistive layer 04 into the ferroelectric layer 03, and preventing ions from diffusing in the ferroelectric layer.
  • the accumulation of metal filaments in 03 is beneficial to reducing the leakage current in the ferroelectric capacitor C and preventing the breakdown of the ferroelectric capacitor C.
  • a resistive switching layer 04 is provided between the ferroelectric layer 03 and the first electrode 01.
  • the barrier layer 05 is provided between the resistive switching layer 04 and the ferroelectric layer 03. . Equivalently, the barrier layer 05 is inserted between the ferroelectric layer 03 and the resistive layer 04 .
  • a resistive switching layer 04 is provided between the ferroelectric layer 03 and the second electrode 02.
  • the barrier layer 05 is provided between the resistive switching layer 04 and the ferroelectric layer 03.
  • the barrier layer 05 is inserted between the ferroelectric layer 03 and the resistive layer 04 .
  • the first electrode 01, the ferroelectric layer 03, the barrier layer 05, the resistive switching layer 04 and the second electrode 02 are formed in sequence.
  • a chemical vapor deposition (CVD) process is used in the process of forming the resistive layer 04.
  • the temperature of this process is relatively high. Therefore, a barrier layer 05 is inserted between the ferroelectric layer 03 and the resistive layer 04.
  • the barrier layer 05 can protect the ferroelectric layer 03 and prevent the ferroelectric layer 03 from being damaged by high temperature.
  • a resistive switching layer 04 is provided between the ferroelectric layer 03 and the first electrode 01 , and a barrier layer 05 is provided between the resistive switching layer 04 and the ferroelectric layer 03 . Furthermore, a resistive switching layer 04 is provided between the ferroelectric layer 03 and the second electrode 02 , and a barrier layer 05 is provided between the resistive switching layer 04 and the ferroelectric layer 03 .
  • the material of the barrier layer 05 should have good compatibility with the material of the ferroelectric layer 03 , that is, the material selection of the barrier layer 05 will not affect the ferroelectric layer.
  • the directional flipping of ferroelectric domains in 03 has an impact.
  • the material of the barrier layer 05 may include at least one of titanium nitride, tantalum nitride, and tungsten.
  • the material of the barrier layer 05 may be the same as the material of the first electrode 01 or the second electrode 02 , or may be different from the material of the first electrode 01 or the second electrode 02 , which is not the case in the embodiments of the present application. limited.
  • the structure of the ferroelectric capacitor C may be a two-dimensional planar structure. For example, see Figures 12A to 12C and 15A to 15C.
  • the first electrode 01 and the second electrode 02 are planar.
  • the electrodes, the first electrode 01, the ferroelectric layer 03, the resistive layer 04 and the second electrode 02 are stacked.
  • the ferroelectric capacitor C has a simple structure and is easy to prepare.
  • the memory unit 200 includes a ferroelectric capacitor C and a transistor T.
  • the first electrode 01 and the second electrode 02 of the ferroelectric capacitor C are planar electrodes.
  • the first electrode 01 and the second electrode 02 are planar electrodes.
  • One of the electrodes 02 is electrically connected to the transistor T to form the memory cell 200 .
  • Some embodiments of the present application provide a method for preparing the ferroelectric capacitor C shown in Figure 15C, and Figures 16A to 16F are diagrams of steps for preparing a ferroelectric capacitor according to some embodiments.
  • a first electrode 01 is formed, and a resistive switching layer 04 is formed on the first electrode 01 .
  • a deposition process such as a chemical vapor deposition process, is used to form the resistive switching layer 04 on the first electrode 01 .
  • the resistive switching layer 04 is subjected to an in-situ doping process or an ion implantation process to dope the resistive switching layer 04 with elements to adjust the material of the resistive switching layer 04 . Resistivity.
  • a barrier layer 05 is formed on the side of the resistive layer 04 away from the first electrode 01 .
  • the barrier layer 05 can play the role of blocking isolators.
  • the barrier layer 05 can inhibit the diffusion of ions in the resistive layer 04 into the ferroelectric layer 03 , to prevent ions from accumulating in the ferroelectric layer 03 to form metal filaments, which is beneficial to reducing the leakage current in the ferroelectric capacitor C and avoiding breakdown of the ferroelectric capacitor C.
  • a ferroelectric layer 03 is formed on the side of the barrier layer 05 away from the first electrode 01 .
  • a barrier layer 05 is formed on the side of the ferroelectric layer 03 away from the first electrode 01 , and then a resistive layer 04 is formed on the side of the barrier layer 05 away from the first electrode 01 .
  • the barrier layer 05 is first formed on the surface of the ferroelectric layer 03, and then the resistive switching layer 04 is formed to block the ferroelectric layer 03.
  • Layer 05 can protect the ferroelectric layer 03 and avoid damage to the ferroelectric layer 03 caused by high temperature.
  • a second electrode 02 is formed on the side of the resistive layer 04 away from the first electrode 01 to complete the preparation of the ferroelectric capacitor C.
  • the above preparation method of the present application forms the first electrode 01, the ferroelectric layer 03 and the second electrode 02 arranged in a stack, that is, a ferroelectric capacitor C with a two-dimensional planar structure is formed.
  • the structure of the ferroelectric capacitor C provided by some embodiments of the present application can also be a three-dimensional vertical structure.
  • Figure 17 is a three-dimensional vertical structure diagram of the ferroelectric capacitor according to some embodiments.
  • the first electrode 01 of the ferroelectric capacitor C is a planar electrode
  • the second electrode 02 is a columnar electrode
  • the second electrode 02 penetrates the first electrode 01
  • the ferroelectric layer 03 and the resistive layer 04 surround the second electrode 02 arranged to separate the first electrode 01 from the second electrode 02 .
  • the ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structural design, which can reduce its occupied area in the X-Y plane, thereby increasing the number of ferroelectric capacitors C per unit area in the X-Y plane, thereby increasing the memory unit 200 per unit area.
  • the number of settings is beneficial to improving the storage density of ferroelectric memory.
  • the memory unit 200 includes a ferroelectric capacitor C and a transistor T.
  • the first electrode 01 of the ferroelectric capacitor C is a planar electrode
  • the second electrode 02 is a columnar electrode.
  • the second electrode 02 and The transistor T is electrically connected, that is, the columnar electrode of the ferroelectric capacitor C is electrically connected to the transistor T to form the memory cell 200 .
  • FIGS. 18A to 18D are diagrams of steps for preparing the ferroelectric capacitor according to some embodiments.
  • the stacked layer includes alternately arranged first electrodes 01 (planar electrodes) and a dielectric layer 06 .
  • the dielectric layer 06 can separate two first electrodes 01 that are adjacent along the direction Z. , so as to insulate between two adjacent first electrodes 01 .
  • a via H is formed that penetrates the stacked layer, and the via H penetrates the first electrode 01 and the dielectric layer 06 in the stacked layer.
  • a resistive switching layer 04 and a ferroelectric layer 03 are formed on the side walls of the via hole H.
  • a resistive switching layer 04, a ferroelectric layer 03 and a resistive switching layer 04 are formed on the sidewall of the via hole H in sequence.
  • the second electrode 02 is formed inside the ferroelectric layer 03 .
  • the second electrode 02 is formed on the inner side of the resistive layer 04 .
  • the above preparation method of the present application forms a ferroelectric capacitor C with a three-dimensional vertical structure.
  • the memory and electronic equipment provided by some embodiments of the present application include the ferroelectric capacitor C provided by any of the above embodiments.
  • the beneficial effects it can achieve can be referred to the beneficial effects of the ferroelectric capacitor C mentioned above, which are not mentioned here. Again.

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Abstract

本申请的一些实施例提供了一种铁电存储阵列及其制备方法、存储器、电子设备，涉及半导体技术领域，旨在提高存储器的热稳定性。该铁电存储阵列可以为二维结构，还可以为三维结构，其包括阵列式排布的多个存储单元，每个存储单元包括铁电电容器和晶体管。其中，铁电电容器包括相对设置的第一电极和第二电极，以及设置于第一电极与第二电极之间的铁电层。该铁电电容器还包括至少一个阻变层，该阻变层设置于铁电层与第一电极之间，和/或铁电层与第二电极之间。阻变层的材料的电阻率随温度的升高而降低。该铁电存储阵列可应用于铁电存储器，也可以应用于铁电场效应晶体管存储器，以实现对数据的读取和写入。

Description

铁电存储阵列及其制备方法、存储器、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种铁电存储阵列及其制备方法、存储器、电子设备。
背景技术
目前，铁电随机存取存储器(Ferroelectric Random Access Memory，英文简称：FeRAM，中文简称：铁电存储器)凭借其存储数据非易失性、存取速率快等特点，广泛应用于存储芯片之中。
通常，铁电存储器具有多个存储单元，每个存储单元包括铁电电容器，该铁电电容器包括相对设置的两个电极，以及设置于两个电极之间的铁电材料，即，该铁电电容器具有金属-铁电材料-金属(Metal-Ferroelectric-Metal，简称MFM)结构。铁电材料具有铁电效应，即两个电极所产生的电场施加在铁电材料上，铁电材料中铁电畴在电场作用下形成极化电荷。在电场反转的情况下，铁电畴发生定向翻转，铁电畴在电场反转前后所形成的极化电荷能量高低不同，这种二元稳定状态(正负极化状态)会使得铁电电容器发生充放电，进而能够被外部的感测放大器(Sense Amplifier，简称SA)所识别，来判别铁电存储器处于“0”或“1”的存储状态。
然而，根据材料科学的理论，铁电材料也属于热释电材料，即随着温度升高，铁电材料中产生声子会干扰铁电畴发生定向翻转，在相同的操作电压下铁电材料的剩余极化强度(Remnant Polarization，简称Pr)会逐渐减小，“0”或“1”两态越来越接近，导致铁电材料的正负极化状态的区分度降低，最后变得难以区分，增加了铁电存储器读写数据的错误率，即铁电存储器产生了热稳定性问题。
发明内容
本申请实施例提供一种铁电存储阵列及其制备方法、存储器、电子设备，用于提高存储器的热稳定性。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种铁电存储阵列，该铁电存储阵列可以为二维结构，还可以为三维结构。并且，该铁电存储阵列可应用于铁电存储器，也可以应用于铁电场效应晶体管(Ferroelectric Filed-Effect-Transistor，简称FeFET)存储器，以实现对数据的读取和写入。
上述铁电存储阵列包括阵列式排布的多个存储单元，每个存储单元包括铁电电容器和晶体管。其中，铁电电容器包括相对设置的第一电极和第二电极，以及设置于第一电极与第二电极之间的铁电层。该铁电电容器还包括至少一个阻变层，阻变层设置于铁电层与第一电极之间，和/或铁电层与第二电极之间。阻变层的材料的电阻率随温度的升高而降低。
本申请的上述实施例所提供的铁电电容器，铁电层与电极(第一电极和/或第二电极)之间设置有阻变层，铁电层与阻变层形成串联电路。由于阻变层的材料的电阻率随温度的升高而降低，使得阻变层的电阻随温度的升高而减小。
在较低的工作温度下，阻变层的电阻较大，根据串联分压的原理，施加在铁电层上的操作电压较小，在此情况下，铁电层的铁电材料的剩余极化强度足以判别“0”或“1”的存储状态，保证了铁电存储器的正常工作。
随着工作温度的升高，阻变层的电阻减小，在第一电极与第二电极之间的总电压不变的情况下，施加在铁电层上的操作电压增大，可增加铁电材料的极化强度和剩余极化强度，补偿铁电材料的极化强度和剩余极化强度随温度升高而减小的数值，从而在较高的工作温度下，提高铁电材料的正负极化状态的区分度，以提高铁电存储器的热稳定性。
在一些实施例中，阻变层的材料包括非晶硅、无定形碳、锗中的至少一种，这些材料均具有电阻率随温度的升高而降低的特性。
在一些实施例中，阻变层的材料中包括掺杂元素，掺杂元素为硼离子、镓离子、氮离子、磷离子、砷离子、铍离子、钙离子中的至少一种。
通过在阻变层中掺杂元素的方式，来调节阻变层的材料的电阻率，以调节阻变层的电阻随温度升高而减小的变化率，从而调节操作电压随温度升高而增加的变化率，使其匹配铁电材料的剩余极化强度随温度升高而减小的变化率，从而使铁电材料的剩余极化强度大致保持不变，或者在允许的数值范围内浮动，以保证铁电存储器的热稳定性。
在一些实施例中，阻变层的材料中的掺杂元素的浓度范围为1×10 15～1×10 21。
上述实施例中，在已知铁电层的电阻的情况下，可通过控制掺杂元素的浓度，来确定阻变层的材料的电阻率，从而确定阻变层的电阻随温度的变化率，使操作电压的变化可以补偿铁电材料的剩余极化强度的变化，保证铁电材料的剩余极化强度大致保持不变，或者在允许的数值范围内浮动，从而保证铁电存储器的热稳定性。
在一些实施例中，阻变层的材料具有金属-绝缘体相变特性，在较低的工作温度下，该类材料具有绝缘体特性，即其电阻率较大；在较高的工作温度下，该类材料具有金属特性，即其电阻率较小。利用这一相变特性，通过阻变层的电阻变化，可调控施加在铁电层上的操作电压。
在一些实施例中，阻变层的材料包括氧化钒、钙钛矿型过渡金属氧化物、锗锑碲合金中的至少一种。
在一些实施例中，阻变层的厚度范围为0.5nm～10nm。
在一些实施例中，铁电电容器还包括阻隔层，该阻隔层设置于阻变层与铁电层之间。
上述实施例中，在阻变层中掺杂离子的情况下，阻隔层可起到阻隔离子的作用，抑制阻变层中离子向铁电层中扩散，避免离子在铁电层中累积形成金属细丝，有利于降低铁电电容器中的漏电流，避免铁电电容器发生击穿。
在一些实施例中，阻隔层的材料包括氮化钛、氮化钽、钨中的至少一者。
上述实施例中，阻隔层与铁电层相接触，阻隔层的材料与铁电层的材料应具有良好的兼容性，即阻隔层的选材不会对铁电层中铁电畴的定向翻转造成影响。
在一些实施例中，第一电极和第二电极为面状电极，第一电极、铁电层、阻变层和第二电极层叠设置。即铁电电容器的结构为二维平面结构，该结构简单，易于制备。
在一些实施例中，第一电极为面状电极，第二电极为柱状电极，第二电极贯穿第一电极，铁电层和阻变层围绕第二电极设置。
上述实施例中，铁电电容器采用三维立式的结构设计，可减小其在平面内的占用面积，从而可提高平面内单位面积的铁电电容器的设置数量，以提高单位面积的存储单元的设置数量，有利于提高存储器的存储密度。
在一些实施例中，第一电极和第二电极为面状电极，第一电极和第二电极中的一者与晶体管电连接，以形成存储单元。或，第一电极为面状电极，第二电极为柱状电极，第二电极与晶体管电连接，以形成存储单元。
第二方面，提供了一种铁电存储阵列的制备方法，该制备方法包括：依次形成第一电极、铁电层和第二电极。其中，形成第一电极之后，形成铁电层之前，还包括：形成阻变层。和/或，形成铁电层之后，形成第二电极之前，还包括：形成阻变层。阻变层的材料的电阻率随温度的升高而降低。
本申请的上述实施例所提供的制备方法，在铁电层与电极(第一电极和/或第二电极)之间插入阻变层，铁电层与阻变层形成串联电路。由于阻变层的材料的电阻率随温度的升高而降低，因此，阻变层的电阻随温度的升高而减小。
随着工作温度的升高，阻变层的电阻减小，在第一电极与第二电极之间的总电压不变的情况下，施加在铁电层上的操作电压增大，可增加铁电材料的极化强度和剩余极化强度，补偿铁电材料的极化强度和剩余极化强度随温度升高而减小的数值，从而在较高的工作温度下，提高铁电材料的正负极化状态的区分度，以提高铁电存储器的热稳定性。
在一些实施例中，依次形成第一电极、铁电层和第二电极，包括：形成层叠设置的第一电极、铁电层和第二电极，以形成二维平面结构的铁电电容器。
在一些实施例中，依次形成第一电极、铁电层和第二电极，包括：形成第一电极。形成贯穿第一电极的过孔。在过孔的侧壁上形成铁电层。在铁电层的内侧形成第二电极，以形成三维立式结构的铁电电容器。
在一些实施例中，形成阻变层，包括：采用沉积工艺，形成阻变层。
在一些实施例中，形成阻变层之后，还包括：对阻变层进行原位掺杂处理或离子注入处理，以在阻变层中掺杂元素，来调节阻变层的材料的电阻率。
在一些实施例中，在阻变层与铁电层之间形成阻隔层。
上述实施例中，阻隔层可抑制阻变层中离子向铁电层中扩散，避免离子在铁电层中累积形成金属细丝，有利于降低铁电电容器中的漏电流，避免铁电电容器发生击穿。
第三方面，提供了一种存储器，该存储器包括上述任一实施例所述的铁电存储阵列，以及与铁电存储阵列电连接的控制器。
第四方面，提供了一种电子设备，该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。该电子设备包括电路板，以及上述实施例所述的存储器，该存储器设置于电路板上，且与电路板电连接。
可以理解地，本申请的上述实施例所提供的存储器和电子设备，其所能达到的有益效果可参考上文中铁电存储阵列的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本申请中的技术方案，下面将对本申请一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本申请实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的电子设备的架构图；
图2为根据一些实施例的电子设备的爆炸图；
图3为根据一些实施例的铁电存储器的架构图；
图4为根据一些实施例的存储单元的电路图；
图5为相关技术中的铁电电容器的结构图；
图6为铁电电容器的铁电层中铁电畴发生定向翻转的示意图；
图7为铁电层的PV电滞回线与温度的关系曲线图；
图8为铁电层的热退火工艺的示意图；
图9为铁电层中产生金属细丝的示意图；
图10为铁电层中产生氧空位的示意图；
图11为铁电层中氧空位形成导电通路的示意图；
图12A～图12C为根据一些实施例的多种铁电电容器的结构图；
图13为图12A中铁电电容器的等效电路图；
图14示出了氧化钒的电阻率与温度的关系曲线图；
图15A～图15C为根据一些实施例的多种铁电电容器的结构图；
图16A～图16F为根据一些实施例的制备铁电电容器的各步骤图；
图17为根据一些实施例的铁电电容器的三维立式结构图；
图18A～图18D为根据一些实施例的制备铁电电容器的各步骤图。
具体实施方式
下面将结合附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例 或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所申请的实施例并不必然限制于本文内容。
“A、B和C中的至少一者”与“A、B或C中的至少一者”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
在本申请的内容中，“在……上”、“上方”、和“之上”的含义应当以最宽泛的方式解释，使得“在...上”不仅意味着“直接在某物上”，而且还包括其间具有中间特征或层的“在某物上”的含义，并且“上方”或“之上”不仅意味着在某物“上方”或“之上”，还包括其间没有中间特征或层的在某物“上方”或“之上”的含义(即，直接在某物上)。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请的一些实施例所涉及的技术术语，具体如下：
晶胞：是由大量微观物质单位(原子、离子、分子等)按一定规则有序排列的结构。
铁电相晶体：晶胞的结构使正负电荷中心不重合而出现电偶极矩，产生不等于零的电极化强度，使晶体具有自发极化，且电偶极矩方向可以因外电场而改变，呈现出 类似于铁磁体的特点。
晶格：晶体内部的原子是按一定的几何规律排列，该原子排列规律的空间格架叫做晶格。
声子：晶格振动的简正模能量量子。
铁电材料：其可通过施加电场排列内部电偶极矩而保持自发极化，即使撤去外部施加电场时亦然。换句话说，铁电体是如下的材料：其中极化强度(极化)值(或电场)半永久地保留在其中，即使在施加恒定的电压并且使电压恢复到零伏之后亦然。
本申请的一些实施例提供了一种电子设备，该电子设备例如可以为手机、平板电脑、个人数字助理(Personal Digital Assistant，简称PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(Virtual Reality，简称VR)终端设备、增强现实(Augmented Reality，简称AR)终端设备、充电家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。本申请的实施例对电子设备的具体形式不作特殊限制。
图1为根据一些实施例的电子设备的架构图。
如图1所示，电子设备1包括：存储装置11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图1中示出的电子设备1的架构并不构成对该电子设备1的限定，该电子设备1可以包括比如图1所示的部件更多或更少的部件，或者可以组合如图1所示的部件中的某些部件，或者可以与如图1所示的部件布置不同。
其中，存储装置11用于存储软件程序以及模块。存储装置11主要包括存储程序区和存储数据区，其中，存储程序区可存储和备份操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备1的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储装置11包括外存储器111和内存储器112。外存储器111和内存储器112存储的数据可以相互传输。外存储器111例如可以包括硬盘、U盘、软盘等。内存储器112例如可以包括随机存取存储器(Random Access Memory，简称RAM)、只读存储器(Read-Only Memory，简称ROM)等，其中，随机存取存储器例如可以包括铁电存储器、相变存储器或磁性存储器等。
处理器12是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备1的各个部分，通过运行或执行存储在存储装置11内的软件程序和/或模块，以及调用存储在存储装置11内的数据，执行电子设备1的各种功能和处理数据，从而对电子设备1进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(Application Processor，简称AP)，调制解调处理器，图形处理器(Graphics Processing Unit，简称GPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如，处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(Central Processing Unit，简称CPU)。 图1中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器置111和内存储器112读取或写入数据。
输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。上述处理器12中的控制器122还可以控制输入设备13接收输入的信号或不接收输入的信号。此外，输入设备13接收到的输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入可以存储在内存储器112中。
输出设备14用于输出输入设备13的输入，并存储在内存储器112中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。
需要说明的是，图1中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图1中的细箭头表示控制器122可以控制的部件。示例性地，控制器122可以对外存储器置111、内存储器112、运算器121、输入设备13和输出设备14等进行控制。
为了方便进一步对电子设备1的结构进行说明，以下以电子设备1为手机为例进行示例性介绍。
图2为根据一些实施例的电子设备的爆炸图。
参见图2，电子设备1还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分别位于中框15的相对两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。
继续参见图2，电子设备1还可以包括电路板18，该电路板18设置于承载板150的靠近后壳16的一侧，电子设备1中的内存储器112可以设置于电路板18上，内存储器112与电路板18电连接。
目前，摩尔定律的持续发展使得电子器件的尺寸持续微缩，并达到了物理尺寸的极限，摩尔定律的发展遇到了技术瓶颈，领域内亟需开发一种高存储容量、可微缩、低能耗以及具有足够多读写次数(大于1×10 15次)的高性能通用存储器，来替代传统的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)，以提高搭载存储器的芯片的运算能力，节省芯片的面积，并降低芯片的成本。
铁电存储器作为新型存储器，凭借其存储数据非易失性、存取速率快、读写电压低、功耗低、器件尺寸小、循环性能好和抗辐照等特点，成为主流的内存储器之一。本申请涉及的内存储器112不限于铁电存储器，其也可以是铁电场效应晶体管存储器。
以下实施例以内存储器112为铁电存储器为例进行介绍，图3为根据一些实施例的铁电存储器的架构图。
参见图3，内存储器112包括铁电存储阵列210、译码器220、驱动器230、控制器(时序控制器)240、缓存器250和输入输出接口260。铁电存储阵列210包括阵列式排布的多个存储单元200。
图4为根据一些实施例的存储单元的电路图。
参见图4，存储单元200包括基于铁电电容器的电路架构，该存储单元200具有1T1C(1-transistor-1-capacitor)结构，即存储单元200包括一个晶体管T和一个铁电电容器C，晶体管T的源极与位线(Bit Line，简称BL)电连接，漏极与铁电电容器C的一个电极电连接，栅极与字线(Word Line，简称WL)电连接，铁电电容器C的另一个电极与板线(Plate Line，简称PL)电连接，本申请的实施例中的存储单元200的电路架构不限于此。
基于此，上述译码器220可根据接收到的地址进行译码，以确定需要访问的铁电存储阵列210中的存储单元200。驱动器230用于根据译码器220输出的译码结果生成控制信号，该控制信号通过字线WL传输至存储单元200中晶体管T的栅极，以控制晶体管T导通或截止，从而实现对指定存储单元200的访问。缓存器250通过板线PL接收存储单元200输出的数据信号，用于将数据信号进行缓存，例如可以采用先入先出(First-In First-Out，简称FIFO)来进行缓存。时序控制器240用于控制缓存器250的时序，以及控制驱动器230驱动铁电存储阵列210。输入输出接口260用于传输数据信号，例如接收数据信号或发送数据信号。
上述铁电存储阵列210、译码器220、驱动器230、时序控制器240、缓存器250和输入输出接口260可以集成于一个芯片中，也可以分别集成于多个芯片中。
下面结合铁电电容器的结构，对铁电存储器的工作原理进行介绍。
图5为相关技术中的铁电电容器的结构图；图6为铁电电容器的铁电层中铁电畴发生定向翻转的示意图。
参见图5，该铁电电容器C＇包括相对设置的第一电极01＇和第二电极02＇，以及设置于第一电极01＇和第二电极02＇之间的铁电层03＇，该铁电电容器C＇具有MFM结构。铁电层03＇包括铁电材料，铁电材料具有自发极化特性。
具体地，参见图6，铁电材料中具有铁电相晶体，在第一电极01＇和第二电极02＇接收电压信号并产生电场的情况下，该电场施加在铁电层03＇上，铁电材料中铁电相晶体的中心原子顺着电场移动并停在低能量状态，该状态例如可以为“0”存储状态。
需要说明的是，大量中心原子在晶体单胞中移动耦合形成铁电畴，铁电畴在电场作用下会形成极化电荷。
继续参见图6，在第一电极01＇和第二电极02＇所产生的电场反转的情况下，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态，该状态例如可以为“1”存储状态，即铁电畴在反转电场的作用下定向翻转。
需要说明的是，铁电畴在电场反转前后所形成的极化电荷能量高低不同，这种正负极化状态会使得铁电电容器C＇发生充放电，进而能够被外部的感测放大器所识别，来判别存储单元200处于“0”或“1”的存储状态，进而实现铁电存储器对数据的读 取或写入。
然而，根据材料科学的理论，铁电材料也属于热释电材料，图7为铁电层的PV电滞回线与温度的关系曲线图，其中，纵坐标为铁电材料的极化强度(Polarization)，单位为“μC/cm 2”；横坐标为施加在铁电材料上的操作电压(Voltage)，单位为“V”。
参见图7，随着工作温度的升高，铁电材料在相同的操作电压下的极化强度会逐渐减小，剩余极化强度也会逐渐减小。这是因为，随着工作温度的升高，铁电材料内产生声子扰动现象，使得铁电畴发生定向翻转，导致其极化强度减小、剩余极化强度减小，即造成铁电畴的极化疲劳。
基于上述情况，在较低的工作温度，及较小的操作电压下，铁电材料的极化强度较大、剩余极化强度较大，足以判别“0”或“1”的存储状态。但是，随着工作温度的升高，若操作电压保持不变，铁电材料的剩余极化强度会逐渐减小，矫顽场增大，“0”或“1”两态越来越接近，导致铁电材料的正负极化状态的区分度降低，最后变得难以区分，增加了铁电存储器读写数据的错误率，即铁电存储器产生了热稳定性问题。
例如，铁电存储器通常定义的工作温度范围为25℃～125℃，也就是说，铁电存储器在125℃下应保持正常的工作。但是，在125℃下，且操作电压保持不变的情况下，铁电材料的剩余极化强度较小，导致“0”或“1”两态无法区分开，铁电存储器读写数据的错误率升高，产生热稳定性问题。
在相关技术中，可采用热退火工艺，改变铁电层03＇的铁电材料中体系的相组成成分，例如改变铁电相晶体的晶向，以使体系更加稳定，从而提高铁电存储器的热稳定性。
图8为铁电层的热退火工艺的示意图；图9为铁电层中产生金属细丝的示意图；图10为铁电层中产生氧空位的示意图；图11为铁电层中氧空位形成导电通路的示意图。
参见图8，通常铁电层03＇中铁电相晶体的晶向是正交相(Orthorhombic)，但是在经过热退火工艺结晶之后，铁电层03＇中会产生四方相(Tetragonal)和单斜相(Monoclinic)的铁电相晶体，即铁电层03＇中包括正交相、四方相和单斜相等铁电相晶体，铁电材料呈多晶的形式。
然而，除正交相的铁电相晶体以外，四方相和单斜相的铁电相晶体的存在会严重影响铁电存储器的热稳定性。因此，领域内通用的方法是提高热退火工艺的温度，促使结晶出来的铁电材料中，正交相的铁电相晶体的数量占比较大，四方相和单斜相的铁电相晶体的数量占比较小，这样，随着温度的升高，铁电材料的剩余极化强度减小的现象得到改善，以提高铁电存储器的热稳定性。
本申请的发明人发现，理论上通过提高热退火工艺的温度，促使结晶出正交相的铁电相晶体是可行的，但在实践过程中，铁电材料的结晶基于热力学和动力学的相互作用，结晶的工艺条件应同时满足热力学和动力学的要求，这给结晶出正交相的铁电相晶体增加了工艺难度。
并且，参见图9，铁电层03＇形成在第一电极01＇上，在对铁电层03＇进行热退火工艺的过程中，在较高的热退火温度下，第一电极01＇中的金属离子会发生移动， 并向铁电层03＇中扩散，金属离子在铁电层03＇中会累积形成“金属细丝”(也称导电通路)，这会导致最终形成的铁电电容器C＇中的漏电流增加，容易导致铁电电容器C＇击穿(breakdown)，进而导致铁电存储器的使用寿命降低。
参见图10和图11，铁电层03＇的铁电材料中包括含氧化合物，在较高的热退火温度下，铁电层03＇中的氧离子会发生移动，并向第一电极01＇中扩散，即铁电层03＇作为氧离子施体，第一电极01＇作为氧离子受体，使得在铁电层03＇内部产生带正电的氧空位。在铁电层03＇中，氧空位逐渐累积也会形成导电通路，导致最终形成的铁电电容器C＇中的漏电流增加，容易导致铁电电容器C＇击穿，进而导致铁电存储器的使用寿命降低。
此外，根据前文所述，四方相的铁电相晶体的存在，虽然会影响铁电存储器的热稳定性，但其有利于提高铁电材料的耐用性。因此，通过提高热退火工艺的温度，来减小四方相的铁电相晶体的数量占比，可适当改善铁电存储器的热稳定性问题，但不利于提高铁电存储器的使用寿命。
综上，通过提高热退火工艺的温度，来提高铁电存储器的热稳定性，其所达到的实际效果并不理想。
在相关技术中，还提供了一种操作电压的补偿方法，具体如下：
根据前文所述，结合图7，在相同的操作电压下，随着工作温度的升高，铁电材料的极化强度会逐渐减小，剩余极化强度也会逐渐减小。从图7还可以得出，在相同的工作温度下，随着操作电压的升高，铁电材料的极化强度会逐渐增加，剩余极化强度也会逐渐增加。因此，随着工作温度的升高，可通过将施加在铁电材料上的操作电压升高，或增大操作电压(操作电压为脉冲信号)的脉宽，以减弱铁电材料的极化强度减小的趋势，以及剩余极化强度减小的趋势，以此方法来改善铁电存储器的热稳定性问题。
上述补偿方法需要通过硬件实现，例如，采用温度传感器来监测工作温度的变化，并将监测结果反馈至驱动器，驱动器可根据工作温度的变化调整操作电压的大小及脉宽，以改善铁电存储器的热稳定性问题。但是，温度传感器的引入会占用芯片的面积，不利于芯片的尺寸微缩，进而影响芯片的产品竞争力。
为解决上述问题，本申请的一些实施例提供了一种铁电电容器，图12A～图12C为根据一些实施例的多种铁电电容器的结构图；图13为图12A中铁电电容器的等效电路图。
参见图12A～图12C，铁电电容器C包括相对设置的第一电极01和第二电极02，以及位于第一电极01与第二电极02之间的铁电层03和阻变层04。
需要说明的是，第一电极01和第二电极02的材料包括氮化钛、氮化钽、钨中的至少一者。
铁电层03的材料包括氧化铪基材料，例如，氧化铪基材料可包括铪锆氧(Hafnium Zirconium Oxide，简称HZO)、铪硅氧(Hafnium Silicon Oxide，简称HSO)、铪铝氧、铪镧氧、铪锆镧氧、铪锆铈氧、铪钇氧、铪锆钆氧等。与传统的铁电材料相比，氧化铪基材料具有稳定的铁电翻转性质，可提高该铁电电容器C的充放电性能。
并且，采用氧化铪基铁电材料，可实现将铁电层03的厚度缩小至十纳米、乃至亚 十纳米，以实现铁电电容器C的尺寸微缩，从而实现铁电存储器的高密度集成或三维集成，有利于构建超高密度的存储芯片。
此外，采用氧化铪基铁电材料的铁电电容器C的制备工艺，与互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)的制备工艺具有良好的兼容性，铁电电容器C的制备难度低。
如图12A所示，至少一个阻变层04设置于铁电层03与第一电极01之间，相当于，在铁电层03与第一电极01之间插入阻变层04。
示例性地，铁电层03与第一电极01之间设置有一个阻变层04。
如图12B所示，至少一个阻变层04设置于铁电层03与第二电极02之间，相当于，在铁电层03与第二电极02之间插入阻变层04。
示例性地，铁电层03与第二电极02之间设置有一个阻变层04。
如图12C所示，至少一个阻变层04设置于铁电层03与第一电极01之间，且至少一个阻变层04设置于铁电层03与第二电极02之间。相当于，在铁电层03与第一电极01之间插入阻变层04，且在铁电层03与第二电极02之间插入阻变层04。
示例性地，铁电层03与第一电极01之间设置有一个阻变层04，且铁电层03与第二电极02之间设置有一个阻变层04。
上述阻变层04的材料的电阻率随温度的升高而降低。
需要说明的是，至少在“工作温度范围”内，阻变层04的材料具有电阻率随温度的升高而降低的特性。“工作温度范围”可理解为铁电存储器通常所应用的场景的温度范围，示例性地，铁电存储器的工作温度范围为-10℃～125℃，例如，铁电存储器的工作温度为-10℃、25℃、50℃、75℃、95℃、120℃或125℃。
本申请的上述实施例所提供的铁电电容器C，在铁电层03与电极(第一电极01和/或第二电极02)之间插入阻变层04，结合图12A和图13，铁电层03与阻变层04形成串联电路，铁电层03的电阻为R 1，阻变层04的电阻为R 2，施加在第一电极01与第二电极02之间的总电压为V，根据串联分压的原理，得出施加在铁电层03上的操作电压
Figure PCTCN2022102541-appb-000001
由于阻变层04的材料的电阻率随温度的升高而降低，因此，阻变层04的电阻R 2随温度的升高而减小。在较低的工作温度下，例如工作温度为25℃，阻变层04的电阻R 2较大，根据上述公式
Figure PCTCN2022102541-appb-000002
可见，施加在铁电层03上的操作电压V 1较小，在此情况下，铁电层03的铁电材料的极化强度较大、剩余极化强度较大，足以判别“0”或“1”的存储状态，保证了铁电存储器的正常工作。
随着工作温度的升高，阻变层04的电阻R 2减小，在第一电极01与第二电极02之间的总电压V不变的情况下，根据上述公式
Figure PCTCN2022102541-appb-000003
可见，施加在铁电层03上的操作电压V 1增大，可增加铁电材料的极化强度和剩余极化强度，补偿铁电材料的极化强度和剩余极化强度随温度升高而减小的数值，从而在较高的工作温度下，提高铁电材料的正负极化状态的区分度，以提高铁电存储器的热稳定性。
相较于相关技术，上述铁电电容器C在制备的过程中，不需要通过提高铁电层03的热退火工艺的温度，来提高铁电存储器的热稳定性，其工艺难度较低。
并且，通过在铁电电容器C内部插入阻变层04的方式，且阻变层04位于铁电层03与电极之间，避免采用额外的硬件(温度传感器)，可降低产品的成本，且不会占用芯片的面积，有利于芯片的尺寸微缩。
在一些实施例中，阻变层04的材料包括非晶硅(amorphous silicon，简称a-Si)、无定形碳(amorphous carbon，简称a-C)、锗中的至少一种，这些材料均具有电阻率随温度的升高而降低的特性。
此外，阻变层04的材料还可包括Ⅲ-Ⅴ族化合物(例如砷化镓、磷化镓等)、Ⅱ-Ⅵ族化合物(例如硫化镉、硫化锌等)、金属氧化物(例如氧化锰、氧化铬、氧化铁、氧化铜等)、由Ⅲ-Ⅴ族化合物和Ⅱ-Ⅵ族化合物组成的固溶体(例如镓铝砷、镓砷磷等)中的至少一种。
在一些实施例中，阻变层04的材料中包括掺杂元素，即通过在阻变层04中掺杂元素的方式，来调节阻变层04的材料的电阻率，以调节阻变层04的电阻随温度升高而减小的变化率，从而调节操作电压V 1随温度升高而增加的变化率，使其匹配铁电材料的剩余极化强度随温度升高而减小的变化率。
通过上述设置方式，随着工作温度的升高，阻变层04的电阻减小，施加在铁电层03上的操作电压增大，且铁电材料的剩余极化强度大致保持不变，或者在允许的数值范围内浮动，以保证铁电存储器的热稳定性。
示例性地，阻变层04的材料中掺杂元素可以为硼离子、镓离子、氮离子、磷离子、砷离子、铍离子、钙离子中的至少一种，例如，掺杂元素可以为这些元素中的一种或多种。
在一些实施例中，在掺杂元素的浓度不同的情况下，阻变层04的材料的电阻率不同，使阻变层04的电阻随温度升高而减小的变化率不同。
基于此，根据上述公式
Figure PCTCN2022102541-appb-000004
在已知铁电层03的电阻R 1的情况下，可通过控制掺杂元素的浓度，来确定阻变层04的材料的电阻率，从而确定阻变层04的电阻R 2随温度的变化率，使操作电压V 1的变化可以补偿铁电材料的剩余极化强度的变化，保证铁电材料的剩余极化强度大致保持不变，或者在允许的数值范围内浮动，从而保证铁电存储器的热稳定性。
示例性地，阻变层04的材料中的掺杂元素的浓度范围为1×10 15～1×10 21，例如，掺杂元素的浓度为1×10 15、1×10 16、1×10 18、1×10 20或1×10 21。
在一些实施例中，在已知铁电层03的电阻R 1的情况下，还可通过控制阻变层04的厚度，来确定阻变层04的电阻R 2，使操作电压V 1的变化可以补偿铁电材料的剩余极化强度的变化，保证铁电材料的剩余极化强度大致保持不变，或者在允许的数值范围内浮动，从而保证铁电存储器的热稳定性。
示例性地，阻变层04的厚度范围为0.5nm～10nm，例如，阻变层04的厚度为0.5nm、2nm、5nm、8nm或10nm。
在另一些实施例中，阻变层04的材料还可采用具有金属-绝缘体相变特性的材料，在较低的工作温度下，该类材料具有绝缘体特性，即其电阻率较大；在较高的工作温度下，该类材料具有金属特性，即其电阻率较小。
利用上述相变特性，通过阻变层04的电阻变化，可调控施加在铁电层03上的操 作电压V 1。在较低的工作温度下，阻变层04的电阻R 2较大，施加在铁电层03上的操作电压V 1较小，但铁电材料的剩余极化强度足以判别“0”或“1”的存储状态。
在较高的工作温度下，阻变层04的电阻R 2较小，施加在铁电层03上的操作电压V 1较大，使得铁电材料的剩余极化强度较大，确保可以判别“0”或“1”的存储状态，保证正负极化状态的区分度，以提高铁电存储器的热稳定性。
示例性地，阻变层04的材料可包括氧化钒(化学式：VO x)、钙钛矿型过渡金属氧化物、锗锑碲合金中的至少一种。
图14示出了氧化钒的电阻率与温度的关系曲线图，其中，纵坐标为氧化钒的电阻率(Resistivity)，单位为“Ω·cm”；横坐标为温度(Temperature)，单位为“℃”。
图14中给出了两条关系曲线，“实线”表示在1.3℃/min(每分钟升高1.3℃)的温度变化条件下，氧化钒的电阻率随温度升高的变化曲线。可见，氧化钒的电阻率随温度的升高而降低，且在温度达到79.2℃时，氧化钒的电阻率下降的最快。
“虚线”表示在5.3℃/min(每分钟升高5.3℃)的温度变化条件下，氧化钒的电阻率随温度升高的变化曲线。可见，氧化钒的电阻率随温度的升高而降低，且在温度达到82.6℃时，氧化钒的电阻率下降的最快。
本申请的一些实施例还提供了多种铁电电容器，图15A～图15C为根据一些实施例的多种铁电电容器的结构图。
参见图15A～图15C，铁电电容器C还包括阻隔层05，该阻隔层05设置于阻变层04与铁电层03之间。
可以理解的是，在阻变层04中掺杂离子的情况下，阻隔层05可起到阻隔离子的作用，抑制阻变层04中离子向铁电层03中扩散，避免离子在铁电层03中累积形成金属细丝，有利于降低铁电电容器C中的漏电流，避免铁电电容器C发生击穿。
示例性地，如图15A所示，铁电层03与第一电极01之间设置有阻变层04，在此情况下，阻隔层05设置于该阻变层04与铁电层03之间。相当于，在铁电层03与阻变层04之间插入阻隔层05。
示例性地，如图15B所示，铁电层03与第二电极02之间设置有阻变层04，在此情况下，阻隔层05设置于该阻变层04与铁电层03之间。相当于，在铁电层03与阻变层04之间插入阻隔层05。
需要说明的是，在制备上述铁电电容器C的过程中，依次形成第一电极01、铁电层03、阻隔层05、阻变层04和第二电极02。在形成阻变层04的过程中，采用化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺，该工艺的温度较高，因此，在铁电层03与阻变层04之间插入阻隔层05，阻隔层05可起到保护铁电层03的作用，避免高温对铁电层03造成损伤。
示例性地，如图15C所示，铁电层03与第一电极01之间设置有阻变层04，该阻变层04与铁电层03之间设置有阻隔层05。并且，铁电层03与第二电极02之间设置有阻变层04，该阻变层04与铁电层03之间设置有阻隔层05。
在一些实施例中，由于阻隔层05与铁电层03相接触，所以阻隔层05的材料与铁电层03的材料应具有良好的兼容性，即阻隔层05的选材不会对铁电层03中铁电畴的定向翻转造成影响。例如，阻隔层05的材料可包括氮化钛、氮化钽、钨中的至少一者。
需要说明的是，阻隔层05的材料可与第一电极01或第二电极02的材料相同，也可以与第一电极01或第二电极02的材料不同，本申请的实施例对此不做限定。
本申请的一些实施例所提供的铁电电容器C，其结构可以是二维平面结构，例如，参见图12A～图12C、图15A～图15C，第一电极01和第二电极02为面状电极，第一电极01、铁电层03、阻变层04和第二电极02层叠设置，该铁电电容器C的结构简单，易于制备。
示例性地，存储单元200包括一个铁电电容器C和一个晶体管T，铁电电容器C的第一电极01和第二电极02均为面状电极，在此情况下，第一电极01和第二电极02中的一者与晶体管T电连接，以形成存储单元200。
本申请的一些实施例提供了图15C示出的铁电电容器C的制备方法，图16A～图16F为根据一些实施例的制备铁电电容器的各步骤图。
如图16A所示，形成第一电极01，并在第一电极01上形成阻变层04。
示例性地，采用沉积工艺，例如采用化学气相沉积工艺，在第一电极01上形成阻变层04。
如图16B所示，在形成阻变层04之后，对阻变层04进行原位掺杂处理或离子注入处理，以在阻变层04中掺杂元素，来调节阻变层04的材料的电阻率。
如图16C所示，在阻变层04远离第一电极01的一侧形成阻隔层05。在阻变层04中掺杂离子的情况下，阻隔层05可起到阻隔离子的作用，后续形成铁电层03之后，阻隔层05可抑制阻变层04中离子向铁电层03中扩散，避免离子在铁电层03中累积形成金属细丝，有利于降低铁电电容器C中的漏电流，避免铁电电容器C发生击穿。
如图16D所示，在阻隔层05远离第一电极01的一侧形成铁电层03。
如图16E所示，在铁电层03远离第一电极01的一侧形成阻隔层05，然后再在阻隔层05远离第一电极01的一侧形成阻变层04。
需要说明的是，采用化学气相沉积工艺，形成阻变层04的过程中，该工艺的温度较高，因此，先在铁电层03表面形成阻隔层05，然后再形成阻变层04，阻隔层05可起到保护铁电层03的作用，避免高温对铁电层03造成损伤。
如图16F所示，在阻变层04远离第一电极01的一侧形成第二电极02，以完成铁电电容器C的制备。
本申请的上述制备方法，形成了层叠设置的第一电极01、铁电层03和第二电极02，即，形成了二维平面结构的铁电电容器C。
本申请的一些实施例所提供的铁电电容器C，其结构还可以是三维立式结构，图17为根据一些实施例的铁电电容器的三维立式结构图。
参见图17，铁电电容器C的第一电极01为面状电极，第二电极02为柱状电极，第二电极02贯穿第一电极01，铁电层03和阻变层04围绕第二电极02设置，以将第一电极01与第二电极02隔开。
铁电电容器C采用上述三维立式的结构设计，可减小其在X-Y平面内的占用面积，从而可提高X-Y平面内单位面积的铁电电容器C的设置数量，以提高单位面积的存储单元200的设置数量，有利于提高铁电存储器的存储密度。
示例性地，存储单元200包括一个铁电电容器C和一个晶体管T，铁电电容器C 的第一电极01为面状电极，第二电极02为柱状电极，在此情况下，第二电极02与晶体管T电连接，即铁电电容器C的柱状电极与晶体管T电连接，以形成存储单元200。
本申请的一些实施例提供了图17示出的铁电电容器C的制备方法，图18A～图18D为根据一些实施例的制备铁电电容器的各步骤图。
如图18A所示，形成堆叠层，该堆叠层包括交替设置的第一电极01(面状电极)和介质层06，介质层06可将沿方向Z相邻的两个第一电极01隔开，以使相邻两个第一电极01之间绝缘。
如图18B所示，形成贯穿堆叠层的过孔H，该过孔H贯穿堆叠层中的第一电极01和介质层06。
如图18C所示，在过孔H的侧壁上形成阻变层04和铁电层03。
示例性地，在过孔H的侧壁上依次形成阻变层04、铁电层03和阻变层04。
如图18D所示，在铁电层03的内侧形成第二电极02。
示例性地，在铁电层03的内侧形成有阻变层04的情况下，第二电极02形成于该阻变层04的内测。
本申请的上述制备方法，形成了三维立式结构的铁电电容器C。
本申请的一些实施例所提供的存储器及电子设备，包括上述任一实施例所提供的铁电电容器C，其所能达到的有益效果可参考上文中铁电电容器C的有益效果，此处不再赘述。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种铁电存储阵列，其特征在于，包括阵列式排布的多个存储单元，所述存储单元包括铁电电容器和晶体管；
    所述铁电电容器包括：
    相对设置的第一电极和第二电极；
    铁电层，设置于所述第一电极与所述第二电极之间；
    至少一个阻变层，设置于所述铁电层与所述第一电极之间，和/或所述铁电层与所述第二电极之间；所述阻变层的材料的电阻率随温度的升高而降低。
  2. 根据权利要求1所述的铁电存储阵列，其特征在于，所述阻变层的材料包括非晶硅、无定形碳、锗中的至少一种。
  3. 根据权利要求2所述的铁电存储阵列，其特征在于，所述阻变层的材料中包括掺杂元素，所述掺杂元素为硼离子、镓离子、氮离子、磷离子、砷离子、铍离子、钙离子中的至少一种。
  4. 根据权利要求3所述的铁电存储阵列，其特征在于，所述阻变层的材料中的掺杂元素的浓度范围为1×10 15～1×10 21。
  5. 根据权利要求1所述的铁电存储阵列，其特征在于，所述阻变层的材料具有金属-绝缘体相变特性。
  6. 根据权利要求5所述的铁电存储阵列，其特征在于，所述阻变层的材料包括氧化钒、钙钛矿型过渡金属氧化物、锗锑碲合金中的至少一种。
  7. 根据权利要求1～6中任一项所述的铁电存储阵列，其特征在于，所述阻变层的厚度范围为0.5nm～10nm。
  8. 根据权利要求1～7中任一项所述的铁电存储阵列，其特征在于，所述铁电电容器还包括阻隔层，所述阻隔层设置于所述阻变层与所述铁电层之间。
  9. 根据权利要求8所述的铁电存储阵列，其特征在于，所述阻隔层的材料包括氮化钛、氮化钽、钨中的至少一者。
  10. 根据权利要求1～9中任一项所述的铁电存储阵列，其特征在于，所述第一电极和所述第二电极为面状电极，所述第一电极、所述铁电层、所述阻变层和所述第二电极层叠设置。
  11. 根据权利要求1～9中任一项所述的铁电存储阵列，其特征在于，所述第一电极为面状电极，所述第二电极为柱状电极；
    所述第二电极贯穿所述第一电极，所述铁电层和所述阻变层围绕所述第二电极设置。
  12. 根据权利要求1～11中任一项所述的铁电存储阵列，其特征在于，所述第一电极和所述第二电极为面状电极，所述第一电极和所述第二电极中的一者与所述晶体管电连接；或，
    所述第一电极为面状电极，所述第二电极为柱状电极，所述第二电极与所述晶体管电连接。
  13. 一种铁电存储阵列的制备方法，其特征在于，包括：
    依次形成第一电极、铁电层和第二电极；
    其中，形成所述第一电极之后，形成所述铁电层之前，所述制备方法还包括：形成阻变层；和/或，形成所述铁电层之后，形成所述第二电极之前，所述制备方法还包括：形成阻变层；
    所述阻变层的材料的电阻率随温度的升高而降低。
  14. 根据权利要求13所述的制备方法，其特征在于，所述依次形成第一电极、铁电层和第二电极，包括：
    形成层叠设置的所述第一电极、所述铁电层和所述第二电极。
  15. 根据权利要求13所述的制备方法，其特征在于，所述依次形成第一电极、铁电层和第二电极，包括：
    形成所述第一电极；
    形成贯穿所述第一电极的过孔；
    在所述过孔的侧壁上形成所述铁电层；
    在所述铁电层的内侧形成所述第二电极。
  16. 根据权利要求13～15中任一项所述的制备方法，其特征在于，所述形成阻变层，包括：
    采用沉积工艺，形成所述阻变层。
  17. 根据权利要求13～16中任一项所述的制备方法，其特征在于，所述形成阻变层之后，还包括：
    对所述阻变层进行原位掺杂处理或离子注入处理。
  18. 根据权利要求13～17中任一项所述的制备方法，其特征在于，还包括：
    形成阻隔层，所述阻隔层位于所述阻变层与所述铁电层之间。
  19. 一种存储器，其特征在于，包括：
    如权利要求1～12中任一项所述的铁电存储阵列；
    控制器，与所述铁电存储阵列电连接。
  20. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求19所述的存储器，所述存储器设置于所述电路板上，且与所述电路板电连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105762197A (zh) * 2016-04-08 2016-07-13 中国科学院上海硅酸盐研究所 基于铌镁酸铅钛酸铅单晶的半导体铁电场效应异质结构及其制备方法和应用
CN106992250A (zh) * 2017-04-11 2017-07-28 中国石油大学(华东) 一种基于铁电异质结的具有多值存储特性的非易失性阻变存储单元及其制备方法
CN113113536A (zh) * 2021-04-07 2021-07-13 中国石油大学(华东) 一种透明多值非易失阻变存储单元及其制备方法
CN113130749A (zh) * 2019-12-30 2021-07-16 三星电子株式会社 铁电电容器、晶体管、存储器件以及制造铁电器件的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105762197A (zh) * 2016-04-08 2016-07-13 中国科学院上海硅酸盐研究所 基于铌镁酸铅钛酸铅单晶的半导体铁电场效应异质结构及其制备方法和应用
CN106992250A (zh) * 2017-04-11 2017-07-28 中国石油大学(华东) 一种基于铁电异质结的具有多值存储特性的非易失性阻变存储单元及其制备方法
CN113130749A (zh) * 2019-12-30 2021-07-16 三星电子株式会社 铁电电容器、晶体管、存储器件以及制造铁电器件的方法
CN113113536A (zh) * 2021-04-07 2021-07-13 中国石油大学(华东) 一种透明多值非易失阻变存储单元及其制备方法

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