WO2024000271A1 - 信号选择器及其驱动方法、显示面板、显示装置 - Google Patents

信号选择器及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2024000271A1
WO2024000271A1 PCT/CN2022/102368 CN2022102368W WO2024000271A1 WO 2024000271 A1 WO2024000271 A1 WO 2024000271A1 CN 2022102368 W CN2022102368 W CN 2022102368W WO 2024000271 A1 WO2024000271 A1 WO 2024000271A1
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WIPO (PCT)
Prior art keywords
sub
signal
base substrate
line
conductive structure
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PCT/CN2022/102368
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English (en)
French (fr)
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WO2024000271A9 (zh
Inventor
梁朝
徐敬义
霍培荣
李志明
黄波
韩帅
王国栋
刘建涛
李必奇
谢建云
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/102368 priority Critical patent/WO2024000271A1/zh
Priority to CN202280002002.7A priority patent/CN117642808A/zh
Publication of WO2024000271A1 publication Critical patent/WO2024000271A1/zh
Publication of WO2024000271A9 publication Critical patent/WO2024000271A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors

Definitions

  • the present disclosure relates to the field of display technology, and specifically, to a signal selector and a driving method thereof, a display panel, and a display device.
  • the present disclosure provides a signal selector and a driving method thereof, a display panel, and a display device.
  • a signal selector for allocating signals on an input data line to different output data lines.
  • the output data lines are used to drive sub-pixels of a display panel.
  • the signal selector includes a plurality of Switch unit. Any switch unit includes a switch circuit and a boost circuit.
  • the switch circuit is connected to an input data line and an output data line.
  • the switch circuit is used to conduct in response to a write signal loaded on its control end.
  • the boost circuit The first end is electrically connected to the output end of the switch circuit; the boost circuit is used to increase the voltage of the output end of the switch circuit in response to a boost control signal loaded on its control end.
  • the boost circuit includes a boost transistor, and the first terminal and/or the second terminal of the boost transistor serve as the first terminal of the boost circuit and are electrically connected to the output terminal of the switching circuit;
  • the control terminal of the voltage transistor serves as the second terminal for loading the boost control signal.
  • the boost circuit includes a boost capacitor, one electrode plate of the boost capacitor serves as a first end of the boost circuit and is electrically connected to the output end of the switching unit; the other electrode plate of the boost capacitor As the second end, it is used to load the boost control signal.
  • multiple switch units are divided into multiple switch unit groups, each switch unit group includes at least three switch units, and output data lines connected to different switch units are respectively connected to sub-pixels of different colors. .
  • the signal selector includes a plurality of input data lines, and one input data line is connected to one switch unit group.
  • the switching circuit is a switching transistor
  • the first terminal of the switching circuit is the source of the switching transistor
  • the second terminal of the switching circuit is the drain of the boost transistor
  • the control terminal of the switching circuit is the boost transistor.
  • the gate of the transistor is the first terminal of the switching circuit.
  • a display panel including the signal selector of any of the above items.
  • a display panel including a base substrate and a driving circuit layer provided on one side of the base substrate.
  • the driving circuit layer includes a plurality of switching circuit areas, and the switching circuit area includes an active layer, a gate
  • the electrode layer and the source and drain metal layer, the active layer is provided on one side of the base substrate, and the active layer includes a first active part, a second active part, a third active part, a fourth active part and a fifth active part.
  • Active part; the gate layer is provided on the side of the active layer away from the base substrate.
  • the gate layer includes a first control lead, a second control lead and a first input data line arranged along the second direction.
  • the first control lead The orthographic projection of the first active portion on the base substrate overlaps the orthographic projection of the second control lead on the base substrate and the orthographic projection of the second active portion on the base substrate.
  • the source-drain metal layer is provided on the side of the gate layer away from the base substrate.
  • the source-drain metal layer includes a first signal line and a second signal line arranged along the first direction, and a first signal line arranged along the second direction.
  • the conductive structure, the second conductive structure, the third conductive structure and the output data line, the second signal line is connected to the first control lead, the first signal line is connected to the second control lead; the first conductive structure is connected to the first input data Line transfer, the orthographic projection of the first conductive structure on the base substrate overlaps with the orthographic projection of the third active part on the base substrate, the first conductive structure is connected to the third active part, and the second conductive structure is on The orthographic projection on the base substrate overlaps with the orthographic projection of the fourth active part on the base substrate, the second conductive structure is connected to the fourth active part, and the orthographic projection of the third conductive structure on the base substrate overlaps with the orthographic projection of the third conductive structure on the base substrate.
  • the orthographic projections of the five active parts on the base substrate overlap, the third conductive structure is connected to the fifth active part, the third conductive structure is connected to the second conductive structure, the second conductive structure and the third conductive structure are connected to the output data line connection.
  • an orthographic projection of the second conductive structure on the substrate is located between an orthographic projection of the first control lead on the substrate and the second control lead on the substrate. Between the orthographic projections of the second conductive structure on the base substrate, the orthographic projection of the second conductive structure on the base substrate is located outside the orthographic projection of the first control lead on the base substrate, and the orthographic projection of the third conductive structure on the base substrate is located on the second The control leads are outside the orthographic projection on the base substrate.
  • the display panel includes a plurality of switch circuit area groups, each group of switch circuit areas includes at least three switch circuit areas, and the at least three switch circuit areas are spaced apart along the first direction, and each switch circuit area
  • the connected output data line connects sub-pixels of one color, and the positive and negative polarities of the driving terminals of two adjacent different sub-pixels are different.
  • the plurality of switch circuit areas are divided into multiple switch circuit block groups, each switch circuit block group includes at least three switch circuit areas, and the source-drain metal layer further includes at least one strip arranged along the first direction.
  • a first transfer line is connected to each first conductive structure in a switch circuit block, and the first input data line is connected to the first transfer line.
  • the first input data line includes a first sub-input data line and a second sub-input data line, the first sub-input data line inputs a positive total data signal, and the second sub-input data line inputs a negative
  • the total data signal, the sub-pixels include a first red sub-pixel, a first green sub-pixel, a first blue sub-pixel, a second red sub-pixel, a second green sub-pixel and a third blue sub-pixel sequentially distributed along the first direction.
  • the display panel also includes a third transfer line and a fourth transfer line.
  • the second output data line corresponding to the first input data line is connected to the third The transfer line is connected, the third transfer line is connected to the second green sub-pixel, the second output data line corresponding to the second input data line is connected to the fourth transfer line, and the fourth transfer line is connected to the first green sub-pixel.
  • the first signal line includes a first sub-signal line, a third sub-signal line and a fifth sub-signal line
  • the second signal line includes a second sub-signal line, a fourth sub-signal line and a fifth sub-signal line.
  • Six sub-signal lines, each switch circuit block group includes three switch circuit areas, the second control lead of the first switch circuit area is connected to the first sub-signal line, and the second control lead of the second switch circuit area is connected to the first sub-signal line.
  • the three sub-signal lines are connected, the second control lead of the third switch circuit area is connected to the fifth sub-signal line, the first control lead of the first switch circuit area is connected to the second sub-signal line, the second switch circuit area The first control lead of the third switching circuit area is connected to the fourth sub-signal line, and the first control lead of the third switch circuit area is connected to the sixth sub-signal line.
  • the gate layer further includes a second input data line, a second transfer line and a touch signal line, the second transfer line is arranged along the first direction, the second input data line and the touch signal line Arranged along the second direction, the second transfer line connects the second input data line and the touch signal line.
  • the touch signal on the second input data line is distributed to different touch signal lines.
  • the touch signal line is used to drive the display.
  • the touch electrodes of the panel are used to drive the display.
  • a display device including the display panel according to any one of the above.
  • a display panel including a base substrate and a driving circuit layer provided on one side of the base substrate.
  • the driving circuit layer includes a plurality of switching circuit areas, and the switching circuit area includes an active layer, a gate
  • the electrode layer and the source and drain metal layer, the active layer is located on one side of the base substrate, the active layer includes a first active part, a second active part and a third active part; the gate layer is located on the active layer
  • the gate layer includes a first control lead, a second control lead and an input data line.
  • the orthogonal projection of the first control lead on the base substrate is consistent with the orthogonal projection of the first active part on the base substrate.
  • the orthographic projection overlaps; the source-drain metal layer is provided on the side of the gate layer away from the base substrate.
  • the source-drain metal layer includes a first signal line and a second signal line arranged along the first direction, and a second signal line arranged along the second direction.
  • the first conductive structure, the second conductive structure, the third conductive structure and the output data line, the second signal line is connected to the first control lead, the first signal line is connected to the second control lead; the first conductive structure is connected to the first control lead.
  • the input data line is switched, the orthographic projection of the first conductive structure on the base substrate overlaps the orthographic projection of the third active part on the base substrate, the first conductive structure is connected to the source of the switching transistor, and the second conductive structure
  • the orthographic projection of the structure on the base substrate overlaps with the orthographic projection of the fourth active part on the base substrate, the second conductive structure is connected to the drain of the switching transistor, and the orthographic projection of the third conductive structure on the base substrate
  • Overlapping with the orthographic projection of the second control line on the base substrate, the third conductive structure and the second control line form a storage capacitor, the third conductive structure is connected to the second conductive structure, and the second conductive structure and the third conductive structure are Output data cable connection.
  • the second conductive structure is provided with a plurality of first through holes
  • the third conductive structure is provided with a plurality of second through holes
  • the orthographic projection of the second through holes on the substrate is located at The first through hole is in an orthographic projection on the base substrate.
  • a method of driving a signal selector comprising:
  • a write signal is loaded to the control end of the switch circuit
  • the boost control signal is loaded to the control terminal of the boost circuit.
  • the boost circuit includes a boost transistor; the driving method further includes: in a preparation period before the data writing period, loading a preliminary voltage to the gate of the boost transistor, so that the voltage of the boost transistor Vgs is not less than the Vth of the boost transistor.
  • the lag time of the falling edge of the writing signal relative to the falling edge of the boost signal is at least greater than one pulse width of the writing signal.
  • FIG. 1 is a circuit connection diagram of a signal selector according to an embodiment of the present disclosure.
  • FIG. 2 is a simulation waveform diagram of the first red sub-pixel R1, the second green sub-pixel G2, and the first blue sub-pixel B1 of a signal selector according to an embodiment of the present disclosure.
  • FIG. 3 is a simulation diagram of a charging process of a signal selector according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit connection diagram of another signal selector according to an embodiment of the present disclosure.
  • FIG. 5 is a circuit connection diagram of the first red sub-pixel R1 of another signal selector when the boost circuit according to the embodiment of the present disclosure is a boost transistor.
  • FIG. 6 is a schematic circuit diagram of the first red sub-pixel R1 of another signal selector according to an embodiment of the present disclosure.
  • FIG. 7 is a circuit connection diagram of the first red sub-pixel R1 of another signal selector when the boost circuit according to the embodiment of the present disclosure is a boost transistor.
  • FIG. 8 is a flowchart of a driving method of a signal selector according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a coupling process of another signal selector according to an embodiment of the present disclosure.
  • FIG. 10 is a graph showing the relationship between the gate voltage of the boost transistor and the capacitance when the boost circuit according to the embodiment of the present disclosure is a boost transistor.
  • FIG. 11 is a schematic diagram of another coupling process of another signal selector according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of an active layer of a display panel in a non-display area according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a gate layer in a non-display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a source and drain metal layer in a non-display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 16 is a layout of a display panel according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of an active layer in a non-display area of another display panel according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a gate layer in a non-display area of another display panel according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of the source and drain metal layers in the non-display area of another display panel according to an embodiment of the present disclosure.
  • FIG. 20 is a layout of another display panel according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings represent the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the signal selector (MUX) can control the opening or closing of the MOS tube through the level changes of the gate control signal in different periods, so that the driving signal of the driving chip (IC) can be input to the display area, thereby controlling the different colors.
  • one of the source and drain of the existing switching transistor T1 is electrically connected to the first sub-input data line S1 or the input data line S2.
  • the first input data line is electrically connected to the pin end of the driver chip
  • the other one of the source and drain of the switching transistor T1 is electrically connected to the sub-pixels of different colors in the display area through the output data line Source, such as: the first red Sub-pixel R1, first green sub-pixel G2 and first blue sub-pixel B1.
  • the gate of the switching transistor T1 is controlled by the corresponding first signal line.
  • the first input data line includes a first sub-input data line S1 and a second sub-input data line S2.
  • the first sub-input data line S1 can provide the first red sub-pixel R1, the second green sub-pixel G2,
  • the first blue sub-pixel B1 provides a signal
  • the second sub-input data line S2 can provide a signal to the second red sub-pixel R2, the first green sub-pixel G1 and the second red sub-pixel B2 in the display area.
  • the gates of different switching transistors T1 corresponding to sub-pixels of different colors are controlled by corresponding first signal lines.
  • the first red sub-pixel R1 is controlled by the first sub-signal line MUX1
  • the second green sub-pixel G2 is controlled by the first sub-signal line MUX1.
  • the second sub-signal line MUX2 is controlled
  • the first blue sub-pixel B1 is controlled by the third sub-signal line MUX2.
  • Figure 2 is a simulation waveform diagram of the first red sub-pixel R1, the second green sub-pixel G2, and the second blue sub-pixel B1.
  • the output data line Source of the sub-pixels of different colors is connected to the gate of the driving transistor. A certain color
  • the gate signal Gate of the driving transistor of the sub-pixel overlaps with the data signal controlled by the first signal line
  • the sub-pixel is lit.
  • the gate signal Gate of the driving transistor of the red sub-pixel R1 overlaps with the data signal controlled by the first sub-signal line MUX1
  • the red sub-pixel R1 is lit, and the second green sub-pixel G2 and the blue sub-pixel R1 are illuminated.
  • the lighting method of the pixel B1 and the red sub-pixel is similar, and will not be described in detail here. It can be understood that the signal selector only plays the role of circuit selection in the display.
  • the opening time of the signal selector is sufficient or the internal resistance voltage drop (RC Loading) is small, the final voltage at the far end of the output data line Source can be charged to the same voltage as the first input data line.
  • the turn-on time of the MUX is greatly reduced, and at the same time, the internal resistance voltage drop of the output data line Source increases, causing the final voltage at the far end of the output line to be lower than the first The voltage on the input data line will cause vertical lines, horizontal lines, split screens and other defects on the display panel.
  • the charging simulation of the display panel using the above signal selector is shown in Figure 3.
  • the driving voltage provided by the first sub-signal line MUX1 is 5.3V
  • the maximum voltage that can be charged on the output data line Source of the first red sub-pixel R1 is 4.984V
  • the present disclosure provides a signal selector.
  • the signal selector is used to distribute the signal on the first input data line to different output data lines Source, and the output data line Source is used to drive the sub-pixels of the display panel.
  • the signal selector includes a plurality of switch units. Each switch unit includes a switch circuit and a boost circuit. The switch circuit is connected to a first input data line and an output data line Source. The switch circuit is used to respond to the writing loaded on its control end.
  • the first end of the boost circuit is electrically connected to the output end of the switching circuit; the boost circuit is used to increase the voltage of the output end of the switching circuit in response to the boost control signal loaded on its control end.
  • the signal selector loads a write signal to the control end of the switch circuit.
  • the switch circuit turns on in response to the write signal loaded on its control end, so that the write signal is loaded to the far end of the output signal line.
  • a boost control signal is loaded to the control terminal of the boost circuit, and the boost circuit pulls up the voltage of the output terminal of the switching circuit in response to the boost control signal loaded on its control terminal. Therefore, the signal selector of the present disclosure can realize the rapid rise and fall of the voltage at the far end of the output data line Source, thereby achieving the charging specifications of medium to large size and high resolution display panels.
  • each switch unit may also include a first signal line and a second signal line, where the first signal line is electrically connected to the control end of the boost circuit and is used to load the boost control signal to the boost circuit.
  • the second signal line is electrically connected to the control end of the switch circuit and is used to load the write signal to the switch circuit.
  • the signal selector may include N first input data lines, one first input data line is connected to a switch unit group, each switch unit group includes up to M switch units, and the N switch unit groups include a total of M ⁇ N switch units. .
  • the M switch units include M switch circuits, the M switch circuits are connected to M output data lines, and the M output data lines are respectively connected to M sub-pixels of different colors. It should be noted that M is greater than or equal to 3.
  • the control terminals of the boost circuits of the M color sub-pixels are loaded with M different boost signals. Therefore, M first signal lines are usually provided, and the control terminals of the switch circuits of the M color sub-pixels are loaded with M different write signals. input signal, so M second signal lines are usually provided. Therefore, the number of signal lines is usually set to 2M.
  • the signal selector may include two switch unit groups, and the two switch unit groups include six switch units, where three switch units drive the first red sub-pixel R1, the second green sub-pixel G2, the first The blue sub-pixel B1 and the other three switch units drive the second red sub-pixel R2, the first green sub-pixel G1 and the first blue sub-pixel B2.
  • the first signal line includes a first sub-signal line MUX1, a third sub-signal line MUX3 and a fifth sub-signal line MUX5.
  • the second signal line includes a second sub-signal line MUX2, the fourth sub-signal line MUX4 and the sixth sub-signal line.
  • MUX6 the first sub-signal line MUX1
  • MUX3 a third sub-signal line MUX3
  • MUX5 the fourth sub-signal line MUX4 and the sixth sub-signal line.
  • the six switching units include six switching circuits.
  • the control terminals of the switch circuit corresponding to the first red sub-pixel R1 and the second red sub-pixel R2 are electrically connected to the second sub-signal line MUX2, and the control terminals of the switch circuit corresponding to the first green sub-pixel G1 and the second green sub-pixel G2
  • the fourth sub-signal line MUX4 is electrically connected, and the control end of the switch circuit corresponding to the first blue sub-pixel B1 and the first blue sub-pixel B2 is electrically connected to the sixth sub-signal line MUX6.
  • the two first input data lines include a first sub-input data line S1 and a second sub-input data line S2.
  • the first sub-input data line S1 can be connected to the first red sub-pixel R1
  • the input terminals of the switch circuits of the second green sub-pixel G2 and the first blue sub-pixel B1 are electrically connected to provide a total input to the first red sub-pixel R1, the second green sub-pixel G2 and the first blue sub-pixel B1 of the display area.
  • the data signal, the second sub-input data line S2 may be electrically connected to the input end of the switch circuit of the second red sub-pixel R2, the first green sub-pixel G1, and the first blue sub-pixel B2, to provide the second red sub-pixel of the display area.
  • the pixel R2, the first green sub-pixel G1, and the first blue sub-pixel B2 input a total data signal.
  • output data lines Source There are six output data lines Source, of which three output data lines Source are respectively connected to the first red sub-pixel R1, the second green sub-pixel G2, and the first blue sub-pixel B1, and provide the first red sub-pixel R1 and the first blue sub-pixel B1 in the display area.
  • the two green sub-pixels G2 and the first blue sub-pixel B1 input sub-data signals, and the other three output data lines Source are respectively connected to the second red sub-pixel R2, the first green sub-pixel G1 and the first blue sub-pixel B2 for display.
  • Six switching units include six boost circuits.
  • the first end of the boost circuit of the first red sub-pixel R1 is electrically connected to the output end of the switch circuit of the first red sub-pixel R1
  • the first end of the boost circuit of the second red sub-pixel R2 is electrically connected to the output end of the switch circuit of the first red sub-pixel R1.
  • the output end of the switch circuit of R2 is electrically connected; the first end of the boost circuit of the first green sub-pixel G1 is electrically connected to the output end of the switch circuit of the first green sub-pixel G1, and the boost circuit of the second green sub-pixel G2
  • the first end of the boost circuit of the first blue sub-pixel B1 is electrically connected to the output end of the switch circuit of the second green sub-pixel G2; the first end of the boost circuit of the first blue sub-pixel B1 is electrically connected to the output end of the switch circuit of the first blue sub-pixel B1.
  • the first end of the boost circuit of the first blue sub-pixel B2 is electrically connected to the output end of the switch circuit of the first blue sub-pixel B2.
  • the control terminal of the boost circuit of the first red sub-pixel R1 is electrically connected to the first sub-signal line MUX1
  • the control terminal of the boost circuit of the second red sub-pixel R2 is electrically connected to the first sub-signal line MUX1
  • the first green sub-pixel R2 is electrically connected to the first sub-signal line MUX1.
  • the control terminal of the boost circuit of the pixel G1 is electrically connected to the third sub-signal line MUX3
  • the control terminal of the boost circuit of the second green sub-pixel G2 is electrically connected to the third sub-signal line MUX3
  • the control terminal of the first blue sub-pixel B1 is electrically connected to the third sub-signal line MUX3.
  • the control end of the boost circuit is electrically connected to the fifth sub-signal line MUX5, and the control end of the boost circuit of the first blue sub-pixel B2 is electrically connected to the fifth sub-signal line MUX5.
  • the switching circuit may include a switching transistor T1.
  • the source of the switching transistor T1 is the first end of the switching circuit.
  • the drain of the switching transistor T1 is the second end of the switching circuit.
  • the gate of the switching transistor T1 is the control of the switching circuit. terminal, the control terminal of the switch circuit is electrically connected to the second signal line.
  • the boost circuit may include a boost transistor T2, the first end and the second end of the boost transistor T2 are short-circuited as the first end of the boost circuit, and the first end of the boost circuit is electrically connected to the second end of the switching circuit;
  • the gate of the boost transistor T2 serves as the control terminal of the boost circuit.
  • the control terminal of the boost circuit is used to load the boost control signal.
  • the control terminal of the boost circuit is electrically connected to the first signal line.
  • the voltage at the far end of the output data line Source can be quickly increased and decreased, thereby achieving the charging specifications of medium to large size and high resolution display panels.
  • the advantage of the boost transistor T2 is that the capacitance of the boost transistor T2 can be adjusted by adjusting the gate voltage.
  • the boost transistor T2 and the surrounding switching transistor T1 do not affect each other and are more convenient to use.
  • the boost transistor T2 can be placed on the same layer as the switching transistor T1 without increasing the thickness of the display panel.
  • the capacitor C1 is the capacitance of the boost transistor, and the capacitor C2 is the same as the first red sub-pixel R1.
  • the capacitance on the output data line Source connected to the sub-pixel R1 UA is the voltage of the boost transistor T2
  • UB is the voltage of the first sub-input data line S1
  • U0 is the output data line Source connected to the first red sub-pixel R1.
  • the switching circuit may include a boost capacitor C3, and one electrode plate of the boost capacitor C3 serves as the first end of the boost circuit and is electrically connected to the output end of the switching circuit;
  • the other electrode plate of the boost capacitor serves as the second terminal of the boost circuit and is used to load the boost control signal.
  • the present disclosure also provides a driving method of a signal selector.
  • the driving method may include:
  • Step S10 During the preparation period, a preliminary voltage is applied to the gate of the boost transistor so that the Vgs of the boost transistor is not less than the Vth of the boost transistor.
  • Step S20 In the data writing period after the preparation period, a writing signal is loaded to the control end of the switch circuit.
  • Step S30 In the pull-up period after the data writing period, a boost control signal is loaded to the control terminal of the boost transistor.
  • the gate voltage Vg of the boost transistor T2 increases from -8V to 0V.
  • the Vgs voltage of the boost transistor T2 is greater than Vth, and the capacitance value of the boost transistor T2 reaches the maximum value.
  • the voltage on the output data line Source connected to the first red sub-pixel R1 is driven by the driver chip electrically connected to the first sub-input data line S1 to increase from 0V to 0.4V.
  • the relationship between the capacitance C1 of the boost transistor T2 and the gate voltage Vg is shown in Figure 10. It can be seen that when Vgs is greater than Vth, the capacitance C1 of the boost transistor T2 reaches the maximum value; during the pull-up period, the gate voltage of the boost transistor T2 The pole voltage Vg increases from 0V to +8V, and the voltage on the output data line Source connected to the first red sub-pixel R1 increases from 4V to 5.26V. The coupling effect of the boost transistor T2 mainly occurs at this stage.
  • the maximum voltage that can be charged on the output data line Source connected to the first red sub-pixel R1 is 5.26V
  • the lag time of the falling edge of the writing signal relative to the falling edge of the boost signal is at least greater than one pulse width of the writing signal to prevent the falling edge of the boost signal from affecting the pixels.
  • the voltage creates a pull-down effect.
  • one pulse width of the write signal is approximately 0.65 ⁇ s.
  • Vgs is the voltage difference between the control terminal and the first terminal of the boost transistor T2
  • Vth is the threshold voltage
  • the threshold voltage is usually 0V.
  • the control terminal is the gate of the boost transistor T2
  • the first terminal is the source of the boost transistor T2.
  • the boost circuit when the boost circuit includes a boost transistor, in the driving method of the signal selector in other embodiments of the present disclosure, the first sub-signal line MUX1 is turned on lagging behind the second sub-signal line MUX2 .
  • the driving method first increases the voltage loaded on the second sub-signal line MUX2 from -8V to 8V.
  • the voltage of the output data line Source connected to the first red sub-pixel R1 is electrically connected to the first sub-input data line S1.
  • the drive of the driver chip rises from 0V to 4.9V.
  • the voltage loaded on the first sub-signal line MUX1 increases from -8V to 8V.
  • the voltage of the output data line Source connected to the first red sub-pixel R1 rises from 4.9V. to 5.02V, which is only 0.04V higher than the 4.98V of the signal selector in the figure.
  • the improvement effect is not obvious. The reason is that when the first sub-signal line MUX1 increases from -8V to 8V, the capacitance value of the boost transistor reaches The maximum value, so the coupling effect is poor.
  • the display panel includes a base substrate BP, a driving circuit layer and a color filter layer that are stacked in sequence.
  • the color filter layer is provided with a filter portion distributed in an array
  • the drive circuit layer is provided with drive circuits corresponding to each sub-pixel; each sub-pixel is driven by the corresponding drive circuit to change to control the rotation direction of the liquid crystal molecules. , to achieve the purpose of display by controlling whether the polarized light of each sub-pixel point is emitted, thereby displaying the corresponding image.
  • the display panel may be provided with scan lines extending along the first direction and data lines extending along the second direction; the display panel may implement progressive scanning to display images.
  • first direction is generally regarded as the row direction
  • second direction is generally regarded as the column direction.
  • the display panel of the present disclosure may include a base substrate BP, a buffer layer Buffer and a drive circuit layer that are stacked in sequence.
  • the base substrate BP is provided with a buffer layer Buffer on one side.
  • a driving circuit layer is provided on the side of the Buffer away from the base substrate BP.
  • the base substrate BP11 may be a base substrate BP of inorganic material or a base substrate BP of organic material.
  • the material of the substrate BP may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the substrate BP may be polymethyl methacrylate (PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or combinations thereof.
  • PMMA polymethyl methacrylate
  • PMMA polyvinyl alcohol
  • PVA polyvinyl alcohol
  • PVP polyvinyl phenol
  • PES polyether sulfone
  • polyimide polyamide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PEN Polyethylene naphthalate
  • the base substrate BP may also be a flexible base substrate BP.
  • the material of the base substrate BP may be polyimide (PI).
  • the base substrate BP can also be a composite of multiple layers of materials.
  • the base substrate BP can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, and a pressure-sensitive adhesive layer that are stacked in sequence. A first polyimide layer and a second polyimide layer.
  • the driving circuit layer includes a plurality of driving circuit regions. Any driver circuit area may include transistors and storage capacitors.
  • the transistor may be a thin film transistor, and the thin film transistor may be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a dual gate thin film transistor.
  • the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material or other types of semiconductor materials; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. .
  • the transistor may have a first terminal, a second terminal, and a control terminal.
  • One of the first terminal and the second terminal may be a source of the transistor and the other may be a drain of the transistor.
  • the control terminal may be a gate of the transistor. It can be understood that the source and drain of a transistor are two opposite and interchangeable concepts; when the working state of the transistor changes, for example, the direction of the current changes, the source and drain of the transistor can be interchanged.
  • the driving circuit layer may include a transistor layer, an interlayer dielectric layer ILD, and a source-drain metal layer LSD that are sequentially stacked on the base substrate BP.
  • the transistor layer is provided with an active layer and a gate electrode of the transistor, and the source-drain metal layer LSD is electrically connected to the source electrode and drain electrode of the transistor.
  • the transistor layer may include an active layer Lpoly, a gate insulating layer GI, and a gate layer LG stacked between the base substrate BP and the interlayer dielectric layer ILD. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the active layer Lpoly can be used to form an active layer of a transistor.
  • the active layer of a semiconductor includes a channel region and source and drain electrodes located on both sides of the channel region; wherein, the channel region can remain Semiconductor properties, the semiconductor materials of the source and drain are partially or completely conductive.
  • the gate layer LG can be used to form gate layer wiring such as scanning wiring, can also be used to form the gate of a transistor, and can also be used to form part or all of the electrode plates of the storage capacitor.
  • Source-drain metal layer LSD can be used to form source-drain metal layer traces such as data traces and power traces.
  • the driving circuit layer may include an active layer Lpoly, a gate insulating layer GI, a gate layer LG, an interlayer dielectric layer ILD and a source layer that are stacked in sequence. Drain metal layer LSD.
  • the display panel has a display area AA and a non-display area BB located around the display area AA.
  • Each drive circuit area includes a switch circuit area and a drive transistor.
  • the switch circuit area is located in the non-display area BB.
  • the drive transistor is located in the display area AA.
  • the switch circuit The region includes a switching transistor, and a control terminal of the driving transistor may be connected to a second terminal of the switching transistor.
  • the driving circuit layer of the display area AA of the display panel may also include a planarization layer PLN.
  • the planarization layer PLN may be one layer or multiple layers.
  • the planarization layer PLN may be provided on the side of the source-drain metal layer LSD of the driving transistor away from the base substrate BP, and the surface of the planarization layer PLN away from the base substrate BP is flat.
  • the planarization layer PLN is provided with a plurality of first via holes at intervals to expose the source and drain metal layers LSD of the driving transistor.
  • a common electrode LCOM can be provided on the side of the planarization layer PLN away from the base substrate BP.
  • the common electrode LCOM is provided with a plurality of second via holes at intervals.
  • the orthographic projection of the second via hole on the base substrate BP is located at the first via hole. within the orthographic projection on the base substrate BP.
  • a protective layer PVX is provided on the side of the common electrode LCOM away from the base substrate BP.
  • the protective layer PVX covers the side of the common electrode LCOM away from the base substrate BP.
  • the protective layer PVX extends from the position where the common electrode LCOM is provided with the second via hole and is flat.
  • the protective layer PLN is provided with the first via hole and extends to the source-drain metal layer LSD of the driving transistor.
  • One end of the protective layer PVX close to the base substrate BP partially covers the source-drain metal layer LSD of the driving transistor, forming an exposed part of the driving transistor. Openings of the source-drain metal layer LSD.
  • a plurality of pixel electrodes LAn are provided on the side of the protective layer PVX away from the base substrate BP.
  • the pixel electrodes LAn are provided in the openings and connected to the source-drain metal layer LSD of the driving transistor.
  • a liquid crystal layer LCL is provided on the side of the pixel electrode LAn away from the source-drain metal layer LSD of the driving transistor.
  • the liquid crystal layer LCL covers the protective layer PVX and the source-drain metal layer LSD of the driving transistor. Since there is a protective layer PVX between the pixel electrode LAn and the common electrode LCOM, and both the pixel electrode LAn and the common electrode LCOM have driving surfaces, the liquid crystal layer LCL can be considered to be located between the pixel electrode LAn and the common electrode LCOM.
  • a color filter layer CF is provided on the side of the liquid crystal layer LCL away from the base substrate.
  • An insulating layer IL can be provided on the side of the color filter layer CF in the display area AA and the planarization layer PLN in the non-display area BB away from the base substrate BP.
  • the insulating layer IL extends from the surface of the color filter layer CF away from the surface of the base substrate BP, to the side of the color filter layer CF, the side of the liquid crystal layer LCL, the side of the protective layer PVX and the side of the common electrode LCOM, and covers the flat non-display area BB The side of the PLN layer away from the base substrate.
  • the active layer Lpoly includes a first active part T1A, a third active part T1S, and a fourth active part T1D.
  • the gate layer LG includes a first control lead GL1 and a first input data line arranged along the first direction H1.
  • An orthographic projection of the first control lead GL1 on the base substrate BP is consistent with the first active portion T1A on the base substrate BP.
  • the orthographic projections overlap to form the gate of the switching transistor.
  • the source-drain metal layer LSD includes a first conductive structure ML1, a second conductive structure ML2 and an output data line Source arranged along the first direction H1.
  • the first conductive structure ML1 is connected to the first input data line.
  • the first conductive structure ML1 is in The orthographic projection on the base substrate BP and the orthographic projection of the third active part T1S on the base substrate BP overlap and are connected to form the source of the switching transistor.
  • the orthographic projection of the second conductive structure ML2 on the base substrate BP overlaps and is connected with the orthographic projection of the fourth active part T1D on the base substrate BP, forming the drain of the switching transistor and the drain of the boost transistor.
  • the second conductive structure ML2 is connected to the output data line Source.
  • the switch circuit area CC also includes a boost circuit.
  • the boost circuit of the display panel is a boost transistor
  • the active layer Lpoly also includes a second active part T2A and a fifth active part T2S.
  • the gate layer LG also includes a second control lead GL2. The orthographic projection of the second control lead GL2 on the base substrate BP overlaps with the orthographic projection of the second active part T2A on the base substrate BP to form a boost transistor. gate.
  • the source-drain metal layer LSD also includes a third conductive structure ML3.
  • the orthographic projection of the third conductive structure ML3 on the base substrate BP overlaps with the orthographic projection of the fifth active part T2S on the base substrate BP.
  • the third conductive structure It is connected to the fifth active part T2S and forms the source of the boost transistor.
  • the third conductive structure ML3 is connected to the second conductive structure ML2, and both the third conductive structure ML3 and the second conductive structure ML2 are connected to the output data line Source.
  • the orthographic projection of the second conductive structure ML2 on the substrate BP is located between the orthographic projection of the first conductive structure ML1 on the substrate BP and the orthographic projection of the third conductive structure ML3 on the substrate. between orthographic projections on substrate BP.
  • the orthographic projection of the second conductive structure ML2 on the base substrate BP is located outside the orthographic projection of the first control lead GL1 on the base substrate BP, and the orthographic projection of the third conductive structure ML3 on the base substrate BP is located on the second control
  • the lead GL2 is outside the orthogonal projection on the base substrate BP.
  • the source-drain metal layer LSD may also include a first signal line and a second signal line arranged along the second direction H2.
  • the second signal line is connected to the first control lead GL1, and the first signal line is connected to the second control lead. catch.
  • the number of switch circuit areas CC is six.
  • the six switch circuit areas CC are divided into two switch circuit area groups.
  • Each switch circuit area group forms a switch circuit island.
  • Each switch circuit island includes three switch circuit areas CC.
  • the three switch circuit areas CC are along the first direction. H1 is set in sequence, and the output data lines Source of the three switch circuit areas CC are connected to red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • the output data line Source of the first switch circuit area CC is connected to the control end of the drive transistor corresponding to the red sub-pixel, and the output of the second switch circuit area CC
  • the data line Source is connected to the control end of the driving transistor corresponding to the green sub-pixel, and the output data line Source of the third switching circuit area CC is connected to the control end of the driving transistor corresponding to the blue sub-pixel.
  • the source-drain metal layer LSD also includes a first transfer line TR1, which is connected to each first conductive structure ML1 in a switch circuit block, and the first sub-input data line S1 is connected to the first transfer line TR1. .
  • Another first transfer line TR1 is connected to each first conductive structure ML1 in another switch circuit block, and the second sub-input data line S2 is connected to the second transfer line TR2.
  • the gate layer LG may also include a second input data line S3, a touch signal line TX and a second transfer line TR2.
  • the second transfer line TR2 extends along the first direction H1.
  • the second input data line S3 and the touch signal line TX Extending along the second direction H2, the second input data line S3 is located on the side of the second adapter line TR2 close to the signal line, and the touch signal line TX is located on the side of the second adapter line TR2 away from the signal line.
  • the second input data line S3 and the touch signal line TX are both connected to the second transfer line TR2.
  • the number of touch signal lines TX can be set to two, and the two touch signal lines TX are distributed along the first direction H1. on both sides of the second input data line S3.
  • the touch signal on the second input data line S3 is distributed to different touch signal lines TX, and the touch signal line TX is used to drive the touch electrodes of the display panel.
  • the first sub-input data line S1 and the second sub-input data line S2 input the positive total data signal and the negative total data signal respectively.
  • a pair of adapter lines needs to be set. The positive and negative polarities of individual output sub-data signals are adjusted.
  • the first sub-input data line S1 inputs a positive total data signal
  • the second sub-input data line S2 inputs a negative total data signal
  • the sub-pixels include a first red sub-pixel R1, a first green sub-pixel R1, and a first green sub-pixel R1, which are sequentially distributed along the first direction.
  • the output data lines Source include a first output data line, a second output data line and a third output data line.
  • the first output data line corresponding to the first input data line S1 is connected to the first red sub-pixel R1
  • the third output data line corresponding to the first input data line S1 is connected to the first blue sub-pixel
  • the first output data line corresponding to S2 is connected to the second red sub-pixel
  • the third output data line corresponding to the second input data line S2 is connected to the second blue sub-pixel.
  • the display panel also includes a third transfer line TR3 and a fourth transfer line TR4.
  • the second output data line corresponding to the first input data line S1 is connected to the third transfer line TR3.
  • the third transfer line TR3 is connected to the second green sub-pixel G2.
  • the second output data line corresponding to the second input data line S2 is connected to the fourth transfer line TR4, and the fourth transfer line TR4 is connected to the first green sub-pixel G1.
  • the third transfer line TR3 may include a first transfer section TR31 and a second transfer section TR32.
  • the first transfer section TR31 is connected to the output data line Source connected to the first green sub-pixel G1, and is connected to the second transfer section TR32.
  • the second transition section TR32 is connected to the source of the driving transistor of the second green sub-pixel G2.
  • the fourth transfer line TR4 may include a third transfer section TR41 and a fourth transfer section TR42.
  • the third transfer section TR41 is connected to the output data line Source connected to the second green sub-pixel G2, and is connected to the fourth transfer section TR52. connection, the fourth transition section TR52 is connected to the source of the driving transistor of the first green sub-pixel G1.
  • the sub-data of the first red sub-pixel R1, the second green sub-pixel G2, the first blue sub-pixel B1, the second red sub-pixel R2, the first green sub-pixel G1 and the second blue sub-pixel B2 The signals are "positive, negative, positive, negative, positive, negative" in order, meeting the display requirements of the display panel.
  • the present disclosure provides another display panel.
  • the difference between this display panel and the display panel in FIGS. 13 to 16 is that the boost circuit is a boost capacitor.
  • the active layer Lpoly only includes the source T1S, the drain T1D, and the first active part T1A of the switching transistor.
  • the gate layer LG includes a first control lead GL1, a second control lead GL2 and an input data line arranged along the first direction H1.
  • the orthographic projection of the first control lead GL1 on the base substrate BP intersects the first active part T1A. stacked to form the gate of the switching transistor.
  • the source-drain metal layer LSD includes a first conductive structure ML1, a second conductive structure ML2, a third conductive structure ML3 and an output data line Source arranged along the first direction H1.
  • the second conductive structure ML2 is located at the Between the first conductive structure ML1 and the third conductive structure ML3, the second conductive structure ML2 and the third conductive structure ML3 are connected to the output data line Source.
  • the first conductive structure ML1 is connected to the input data line.
  • the orthographic projection of the first conductive structure ML1 on the base substrate BP overlaps and connects the orthographic projection of the third active part T1S on the base substrate BP to form a switching transistor.
  • the orthographic projection of the second conductive structure ML2 on the base substrate BP overlaps and is connected with the orthographic projection of the fourth active part T1D on the base substrate BP, forming the drain of the switching transistor and the drain of the boost transistor.
  • the source-drain metal layer LSD may also include a first signal line and a second signal line arranged along the second direction H2.
  • the second signal line is connected to the first control lead GL1, and the first signal line is connected to the two control leads. .
  • the areas of the second control lead GL2 and the third conductive structure ML3 are usually not too small.
  • the second conductive structure is provided with a plurality of first through holes HA1 along the second direction H2.
  • the third conductive structure is provided with a plurality of second through holes HA2 along the second direction H2, and the orthographic projection of the second through hole HA2 on the substrate BP is located at the orthographic projection of the first through hole HA1 on the substrate BP.
  • the orthographic projection of the second through hole HA2 on the base substrate BP may coincide with the orthographic projection of the first through hole HA1 on the base substrate BP.
  • the edge between the driving backplane and the color filter layer is usually cured by optical curing glue.
  • Light passes through the first through hole HA1 and the second through hole HA2, improving the curing effect of the optical curing glue, thereby affecting the driving backplane.
  • the optically curable glue can be UV glue.
  • Embodiments of the present disclosure provide a display device.
  • the display device includes the display panel described in any one of the above embodiments of the present disclosure.
  • the display device can also refer to the specific structure and beneficial effects of the display panel, which will not be described again here.
  • the display device can be a traditional electronic device, such as a mobile phone, a computer, a television, or a camcorder, or it can be an emerging wearable device, such as a virtual reality device and an augmented reality device, which are not listed here.
  • the display device also includes other necessary components and components, taking a mobile phone as an example, such as a casing, a circuit board, etc. Those skilled in the art can determine the specific use requirements of the display device according to Supplement accordingly and will not go into details here.

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Abstract

本公开是关于一种信号选择器及其驱动方法、显示面板、显示装置，信号选择器在数据写入时段，向开关电路的控制端加载写入信号，开关电路响应加载于其控制端上的写入信号而导通，使得写入信号被加载至输出信号线的远端。在数据写入时段之后的拉升时段，向升压电路的控制端加载升压控制信号，升压电路响应加载于其第二端的升压控制信号而拉高开关电路的输出端的电压。因此，本公开的信号选择器可以实现输出数据线(Source)远端的电压快速上升和快速下降，从而可以达成中大尺寸和高分辨率的显示面板的充电规格。

Description

信号选择器及其驱动方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种信号选择器及其驱动方法、显示面板、显示装置。
背景技术
目前，大尺寸化和高分辨率的显示面板逐渐成为发展趋势，但随之带来了中大尺寸和高分辨率的显示面板充电难以达成充电规格的问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种信号选择器及其驱动方法、显示面板、显示装置。
根据本公开的一个方面，提供一种信号选择器，用于将输入数据线上的信号分配至不同的输出数据线上，输出数据线用于驱动显示面板的子像素，信号选择器包括多个开关单元，任意一个开关单元包括开关电路和升压电路，开关电路连接输入数据线和一个输出数据线，开关电路用于响应加载于其控制端上的写入信号而导通，升压电路的第一端与开关电路的输出端电连接；升压电路用于，响应加载于其控制端的升压控制信号而拉高开关电路的输出端的电压。
在本公开的一个实施例中，升压电路包括一个升压晶体管，升压晶体管的第一端和/或第二端作为升压电路的第一端而与开关电路的输出端电连接；升压晶体管的控制端作为第二端用于加载升压控制信号。
在本公开的一个实施例中，升压电路包括升压电容，升压电容的一个电极板作为升压电路的第一端而与开关单元的输出端电连接；升压电容的另一个电极板作为第二端用于加载升压控制信号。
在本公开的一个实施例中，多个开关单元分为多个开关单元组，每 个开关单元组包括至少三个开关单元，不同开关单元所连接的输出数据线分别与不同颜色的子像素连接。
在本公开的一个实施例中，信号选择器包括多条输入数据线，一条输入数据线连接一个开关单元组。
在本公开的一个实施例中，开关电路为开关晶体管，开关电路的第一端为开关晶体管的源极，开关电路的第二端为升压晶体管的漏极，开关电路的控制端为升压晶体管的栅极。
根据本公开的又一个方面，提供一种显示面板，包括上面任一项的信号选择器。
根据本公开的再一个方面，提供一种显示面板，包括衬底基板和设于衬底基板一侧的驱动电路层，驱动电路层包括多个开关电路区，开关电路区包括有源层、栅极层和源漏金属层，有源层设于衬底基板的一侧，有源层包括第一有源部、第二有源部、第三有源部、第四有源部和第五有源部；栅极层设于有源层远离衬底基板的一侧，栅极层包括沿第二方向设置的第一控制引线、第二控制引线和第一输入数据线，第一控制引线在衬底基板上的正投影与第一有源部在衬底基板上的正投影交叠第二控制引线在衬底基板上的正投影与第二有源部在衬底基板上的正投影交叠；源漏金属层设于栅极层远离衬底基板的一侧，源漏金属层包括沿第一方向设置的第一信号线、第二信号线，以及沿第二方向设置的第一导电结构、第二导电结构、第三导电结构和输出数据线，第二信号线与第一控制引线转接，第一信号线与第二控制引线转接；第一导电结构与第一输入数据线转接，第一导电结构在衬底基板上的正投影与第三有源部在衬底基板上的正投影交叠，第一导电结构与第三有源部连接，第二导电结构在衬底基板上的正投影与第四有源部在衬底基板上的正投影交叠，第二导电结构与第四有源部连接，第三导电结构在衬底基板上的正投影与第五有源部在衬底基板上的正投影交叠，第三导电结构与第五有源部连接，第三导电结构与第二导电结构连接，第二导电结构和第三导电结构与输出数据线连接。
在本公开的一个实施例中，在第一方向上，第二导电结构在衬底基板上的正投影，位于第一控制引线在衬底基板上的正投影与第二控制引 线在衬底基板上的正投影之间，第二导电结构在衬底基板上的正投影位于第一控制引线在衬底基板上的正投影的外侧，第三导电结构在衬底基板上的正投影位于第二控制引线在衬底基板上的正投影的外侧。
在本公开的一个实施例中，显示面板包括多个开关电路区组，每组开关电路区包括至少三个开关电路区，至少三个开关电路区沿第一方向间隔设置，每个开关电路区连接的输出数据线连接一种颜色的子像素，相邻两个不同子像素的驱动端的正负极性不同。
在本公开的一个实施例中，多个开关电路区分为多个开关电路区组，每个开关电路区组包括至少三个开关电路区，源漏金属层还包括沿第一方向设置的至少一条第一转接线，一条第一转接线与一个开关电路区组中的各第一导电结构连接，且第一输入数据线与第一转接线转接。
在本公开的一个实施例中，第一输入数据线包括第一子输入数据线和第二子输入数据线，第一子输入数据线输入正的总数据信号，第二子输入数据线输入负的总数据信号，子像素包括沿第一方向依次分布的第一红色子像素、第一绿色子像素、第一蓝色子像素、第二红色子像素、第二绿色子像素和第三蓝色子像素；第一子输入数据线和第二子输入数据线分别对应一组第一输出数据线、第二输出数据线和第三输出数据线，与第一输入数据线对应的第一输出数据线连接第一红色子像素，与第一输入数据线对应的第三输出数据线连接第一蓝色子像素，与第二输入数据线对应的第一输出数据线连接第二红色子像素，与第二输入数据线对应的第三输出数据线连接第二蓝色子像素，显示面板还包第三转接线和第四转接线，与第一输入数据线对应的第二输出数据线与第三转接线连接，第三转接线连接第二绿色子像素，与第二输入数据线对应的第二输出数据线与第四转接线连接，第四转接线连接第一绿色子像素。
在本公开的一个实施例中，第一信号线包括第一子信号线、第三子信号线和第五子信号线，第二信号线包括第二子信号线、第四子信号线和第六子信号线，每个开关电路区组包括三个开关电路区，第一个开关电路区的第二控制引线与第一子信号线连接，第二个开关电路区的第二控制引线与第三子信号线连接，第三个开关电路区的第二控制引线与第五子信号线连接，第一个开关电路区的第一控制引线与第二子信号线连 接，第二个开关电路区的第一控制引线与第四子信号线连接，第三个开关电路区的第一控制引线与第六子信号线连接。
在本公开的一个实施例中，栅极层还包括第二输入数据线、第二转接线和触控信号线，第二转接线沿第一方向设置，第二输入数据线和触控信号线沿第二方向设置，第二转接线连接第二输入数据线和触控信号线，第二输入数据线上的触控信号分配至不同的触控信号线上，触控信号线用于驱动显示面板的触控电极。
根据本公开的再一个方面，提供一种显示装置，包括上面任一项所述的显示面板。
根据本公开的再一个方面，提供一种显示面板，包括衬底基板和设于衬底基板一侧的驱动电路层，驱动电路层包括多个开关电路区，开关电路区包括有源层、栅极层和源漏金属层，有源层设于衬底基板的一侧，有源层包括第一有源部、第二有源部和第三有源部；栅极层设于有源层远离衬底基板的一侧，栅极层包括第一控制引线、第二控制引线和输入数据线，第一控制引线在衬底基板上的正投影与第一有源部在衬底基板上的正投影交叠；源漏金属层设于栅极层远离衬底基板的一侧，源漏金属层包括沿第一方向设置的第一信号线、第二信号线，以及沿第二方向设置的第一导电结构、第二导电结构、第三导电结构和输出数据线，第二信号线与第一控制引线转接，第一信号线与第二控制引线转接；第一导电结构与第一输入数据线转接，第一导电结构在衬底基板上的正投影与第三有源部在衬底基板上的正投影交叠，第一导电结构与开关晶体管的源极连接，第二导电结构在衬底基板上的正投影与第四有源部在衬底基板上的正投影交叠，第二导电结构与开关晶体管的漏极连接，第三导电结构在衬底基板上的正投影与第二控制线在衬底基板上的正投影交叠，第三导电结构与第二控制线构成存储电容，第三导电结构与第二导电结构连接，第二导电结构和第三导电结构与输出数据线连接。
在本公开的一个实施例中，第二导电结构上设有多个第一通孔，第三导电结构上设有多个第二通孔，第二通孔在衬底基板上的正投影位于第一通孔在衬底基板上的正投影内。
根据本公开的再一个方面，提供一种信号选择器的驱动方法，所述 方法包括：
在数据写入时段，向开关电路的控制端加载写入信号；
在数据写入时段之后的拉升时段，向升压电路的控制端加载升压控制信号。
在本公开的一个实施例中，升压电路包括升压晶体管；所述驱动方法还包括：在数据写入时段之前的预备时段，向升压晶体管的栅极加载预备电压，使得升压晶体管的Vgs不小于升压晶体管的Vth。
在本公开的一个实施例中，写入信号的下降沿相对于升压信号的下降沿的滞后时长至少大于写入信号的一个脉冲宽度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例涉及的一种信号选择器的电路连接图。
图2为本公开实施例涉及一种信号选择器的第一红色子像素R1、第二绿色子像素G2、和第一蓝色子像素B1的仿真波形图。
图3为本公开实施例涉及一种信号选择器的充电过程仿真图。
图4为本公开实施例涉及的另一种信号选择器的电路连接图。
图5为本公开实施例涉及的升压电路为升压晶体管时，另一种信号选择器的第一红色子像素R1的电路连接图。
图6为本公开实施例涉及另一种信号选择器的第一红色子像素R1的电路原理图。
图7为本公开实施例涉及的升压电路为升压晶体管时，另一种信号选择器的第一红色子像素R1的电路连接图。
图8为本公开实施例涉及的信号选择器的其驱动方法的流程图。
图9为本公开实施例涉及的另一种信号选择器的一种耦合过程示意图。
图10为本公开实施例涉及的升压电路为升压晶体管时，升压晶体管的栅极电压与电容的关系曲线。
图11为本公开实施例涉及的另一种信号选择器的另一种耦合过程示意图。
图12为本公开实施例涉及的显示面板的截面示意图。
图13为本公开实施例涉及的一种显示面板的有源层在非显示区的结构示意图。
图14为本公开实施例涉及的一种显示面板的栅极层在非显示区的结构示意图。
图15为本公开实施例涉及的一种显示面板的源漏金属层在非显示区的结构示意图。
图16为本公开实施例涉及的一种显示面板的版图。
图17为本公开实施例涉及的另一种显示面板的有源层在非显示区的结构示意图。
图18为本公开实施例涉及的另一种显示面板的栅极层在非显示区的结构示意图。
图19为本公开实施例涉及的另一种显示面板的源漏金属层在非显示区的结构示意图。
图20为本公开实施例涉及的另一种显示面板的版图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标 的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
信号选择器(MUX)可以通过栅极的控制信号在不同时段的电平变化，来控制MOS管的打开或关断，实现驱动芯片(IC)的驱动信号输入到显示区，从而控制不同颜色的子像素的亮暗。
如图1所示，以2/6的信号选择器(MUX)为例，现有的开关晶体管T1的源极和漏极中的一个与第一子输入数据线S1或输入数据线S2电连接，第一输入数据线电连接驱动芯片的引脚端，开关晶体管T1的源极和漏极中的另一个通过输出数据线Source电连接显示区的的不同颜色的子像素，如：第一红色子像素R1、第一绿色子像素G2和第一蓝色子像素B1。开关晶体管T1的栅极由相应的第一信号线控制。
其中，第一输入数据线包括第一子输入数据线S1和第二子输入数据线S2，第一子输入数据线S1可以给显示区的第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1提供信号，第二子输入数据线S2可以给显示区的第二红色子像素R2、第一绿色子像素G1、第二红色子像素B2提供信号。不同颜色的子像素所对应的不同开关晶体管T1的栅极由相应的第一信号线控制，具体可以是第一红色子像素R1由第一子信号线MUX1控制，第二绿色子像素G2由第二子信号线MUX2控制，第一蓝色子像素B1由第三子信号线MUX2控制。
图2为第一红色子像素R1、第二绿色子像素G2、第二蓝色子像素B1的仿真波形图，其中不同颜色的子像素的输出数据线Source连接驱 动晶体管的栅极，某一颜色的子像素的驱动晶体管的栅极信号Gate与第一信号线控制输出的数据信号交叠时，该子像素被点亮。具体可以是，红色子像素R1的驱动晶体管的栅极信号Gate与第一子信号线MUX1控制输出的数据信号交叠时，红色子像素R1被点亮，第二绿色子像素G2和蓝色子像素B1与红色子像素的点亮方式类似，在此不再进行一一赘述。可以理解的是，信号选择器在显示中仅起着电路选择的作用。
若信号选择器的打开时间足够或内阻压降(RC Loading)较小的情况下，输出数据线Source远端的最终电压可以充到与第一输入数据线相同的电压。但对于中大尺寸、高分辨率和高刷新率的显示面板，MUX的打开时间大幅减小，同时输出数据线Source的内阻压降增大，导致输出线远端的最终电压低于第一输入数据线上的电压，从而显示面板就会出现竖线、横线、分屏等不良。
以尺寸为17D6，分辨率为1600x2560、MUX3的显示面板为例，进一步说明信号选择器在显示面板充电过程中的作用。由于17D6的显示面板分辨率较高且尺寸较大，采用现有的信号选择器难以达成显示面板的充电规格要求。
以红色子像素R1为例进行说明。采用上述信号选择器的显示面板的充电仿真如图3所示，第一子信号线MUX1所提供的驱动电压为5.3V，第一红色子像素R1的输出数据线Source上能充到的最大电压为4.984V，显示面板的充电率为4.984/5.3＝0.94，小于该显示面板所要求的0.99的充电率规格，因而该显示面板会出现横纹，竖线等显示不良。
基于此，本公开提供一种信号选择器。如图4至图7所示，该信号选择器用于将第一输入数据线上的信号分配至不同的输出数据线Source上，输出数据线Source用于驱动显示面板的子像素。信号选择器包括多个开关单元，任意一个开关单元包括开关电路和升压电路，开关电路连接第一输入数据线和一个输出数据线Source，开关电路用于响应加载于其控制端上的写入信号而导通；升压电路的第一端与开关电路的输出端电连接；升压电路用于，响应加载于其控制端的升压控制信号而拉高开关电路的输出端的电压。
信号选择器在数据写入时段，向开关电路的控制端加载写入信号， 开关电路响应加载于其控制端上的写入信号而导通，使得写入信号被加载至输出信号线的远端。在数据写入时段之后的拉升时段，向升压电路的控制端加载升压控制信号，升压电路响应加载于其控制端的升压控制信号而拉高开关电路的输出端的电压。因此，本公开的信号选择器可以实现输出数据线Source远端的电压快速上升和快速下降，从而可以达成中大尺寸和高分辨率的显示面板的充电规格。
需要说明的是，每个开关单元还可以包括第一信号线和第二信号线，其中第一信号线与升压电路的控制端电连接，用于向升压电路加载升压控制信号，第二信号线与开关电路的控制端电连接，用于向开关电路加载写入信号。
信号选择器可以包括N条第一输入数据线，一条第一输入数据线连接一个开关单元组，每个开关单元组包括至M个开关单元，N个开关单元组共包括M×N个开关单元。
M个开关单元包括M个开关电路，M个开关电路连接M条输出数据线，M条输出数据线分别与M种不同颜色的子像素连接。要说明的是，M大于等于3。
M个颜色的子像素的升压电路的控制端加载M个不同的升压信号，因此通常设置M条第一信号线，M个颜色的子像素的开关电路的控制端加载M个不同的写入信号，因此通常设置M条第二信号线。因此，信号线的数量通常设为2M条。
如图4所示，信号选择器可以包括两个开关单元组，两个开关单元组包括六个开关单元，其中三个开关单元驱动第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1，另外三个开关单元驱动第二红色子像素R2、第一绿色子像素G1、第一蓝色子像素B2。第一信号线包括第一子信号线MUX1、第三子信号线MUX3和第五子信号线MUX5，第二信号线包括第二子信号线MUX2、第四子信号线MUX4和第六子信号线MUX6。
六个开关单元包括六个开关电路。第一红色子像素R1和第二红色子像素R2对应的开关电路的控制端与第二子信号线MUX2电连接，第一绿色子像素G1和第二绿色子像素G2对应的开关电路的控制端与第四 子信号线MUX4电连接，第一蓝色子像素B1和第一蓝色子像素B2对应的开关电路的控制端与第六子信号线MUX6电连接。
第一输入数据线设为两条，两条第一输入数据线包括第一子输入数据线S1和第二子输入数据线S2，第一子输入数据线S1可以与第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1的开关电路的输入端电连接，给显示区的第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1输入总数据信号，第二子输入数据线S2可以与第二红色子像素R2、第一绿色子像素G1、第一蓝色子像素B2的开关电路的输入端电连接，给显示区的第二红色子像素R2、第一绿色子像素G1、第一蓝色子像素B2输入总数据信号。
输出数据线Source设为六条，其中三条输出数据线Source分别连接第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1，给显示区的第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1输入子数据信号，另外三条输出数据线Source分别连接第二红色子像素R2、第一绿色子像素G1、第一蓝色子像素B2，给显示区的第二红色子像素R2、第一绿色子像素G1、第一蓝色子像素B2输入子数据信号。
六个开关单元包括六个升压电路。第一红色子像素R1的升压电路的第一端与第一红色子像素R1的开关电路的输出端电连接，第二红色子像素R2的升压电路的第一端与第二红色子像素R2的开关电路的输出端电连接；第一绿色子像素G1的升压电路的第一端与第一绿色子像素G1的开关电路的输出端电连接，第二绿色子像素G2的升压电路的第一端与第二绿色子像素G2的开关电路的输出端电连接；第一蓝色子像素B1的升压电路的第一端与第一蓝色子像素B1的开关电路的输出端电连接，第一蓝色子像素B2的升压电路的第一端与第一蓝色子像素B2的开关电路的输出端电连接。
第一红色子像素R1的升压电路的控制端与第一子信号线MUX1电连接，第二红色子像素R2的升压电路的控制端与第一子信号线MUX1电连接，第一绿色子像素G1的升压电路的控制端与第三子信号线MUX3电连接，第二绿色子像素G2的升压电路的控制端与第三子信号线MUX3电连接，第一蓝色子像素B1的升压电路的控制端与第五子信号线MUX5 电连接，第一蓝色子像素B2的升压电路的控制端与第五子信号线MUX5电连接。
如图5所示，开关电路可以包括开关晶体管T1，开关晶体管T1的源极为开关电路的第一端，开关晶体管T1的漏极为开关电路的第二端，开关晶体管T1的栅极为开关电路的控制端，开关电路的控制端与第二信号线电连接。升压电路可以包括升压晶体管T2，升压晶体管T2的第一端和第二端短接作为升压电路的第一端，升压电路的第一端与开关电路的第二端电连接；升压晶体管T2的栅极作为升压电路的控制端，升压电路的控制端用于加载升压控制信号，升压电路的控制端与第一信号线电连接。
利用升压晶体管T2产生的电容耦合效应，可以实现输出数据线Source远端电压的快速上升和快速下降，从而可以达成中大尺寸和高分辨率的显示面板的充电规格。升压晶体管T2的优点是可以通过调节栅极电压大小来调节升压晶体管T2电容的大小，升压晶体管T2与周边的开关晶体管T1互不影响，使用上比较方便。升压晶体管T2可以与开关晶体管T1同层设置，不会增加显示面板的厚度。
如图6所示，以控制第一红色子像素R1输出的第一子信号线MUX1为例，来说明信号选择器的工作原理，电容C1为升压晶体管的电容，电容C2为与第一红色子像素R1连接的输出数据线Source上的电容，UA为升压晶体管T2的电压，UB为第一子输入数据线S1的电压，U0为与第一红色子像素R1连接的输出数据线Source的电压。当UA电压突然增加ΔU时，由于电容C1两端的电压不能突变，则电容C1另一端电压也增加ΔU，由于电容C1与电容C2连接在一起，则电容C1与电容C2之间存在电荷的流通，最终电容C1与电容C2的电压一致，达到平衡后U1的电压值为：
Figure PCTCN2022102368-appb-000001
如图7所示，在本公开的其它实施例中，开关电路可以包括升压电容C3，升压电容C3的一个电极板作为升压电路的第一端而与开关电路的输出端电连接；升压电容的另一个电极板作为升压电路的第二端用于 加载升压控制信号。
如图8所示，本公开还提供一种信号选择器的驱动方法。当升压电路包括升压晶体管时，该驱动方法可以包括：
步骤S10，在预备时段，向升压晶体管的栅极加载预备电压，使得升压晶体管的Vgs不小于升压晶体管的Vth。
步骤S20，在预备时段之后的数据写入时段，向开关电路的控制端加载写入信号。
步骤S30，在数据写入时段之后的拉升时段，向升压晶体管的控制端加载升压控制信号。
如图9所示，在预备时段，升压晶体管T2的栅极电压Vg由-8V增大到0V，此时升压晶体管T2的Vgs电压大于Vth，升压晶体管T2的电容值达到最大值，与第一红色子像素R1连接的输出数据线Source上的电压，受到与第一子输入数据线S1电连接的驱动芯片的驱动由0V增至0.4V。
升压晶体管T2的电容C1与栅极电压Vg的关系曲线如图10所示，可见当Vgs大于Vth时，升压晶体管T2的电容C1到达最大值；在拉升时段，升压晶体管T2的栅极电压Vg由0V增大到+8V，与第一红色子像素R1连接的输出数据线Source上的电压由4V增大到5.26V，升压晶体管T2的耦合作用主要发生在这个阶段。
可以理解的是，由于升压晶体管T2的耦合作用的存在，与第一红色子像素R1连接的输出数据线Source上能充到的最大电压为5.26V，该显示面板的充电率为5.26/5.3＝0.9924，满足该显示面板所要求的0.99的充电率规格。
需要强调的是，在信号选择器的驱动过程中，写入信号的下降沿相对于升压信号的下降沿的滞后时长至少大于写入信号的一个脉冲宽度，防止升压信号的下降沿对像素电压产生下拉作用。通常，写入信号的一个脉冲宽度大约为0.65μs。
需要说明的是，Vgs为升压晶体管T2的控制端与第一端之间的电压差，Vth为阈值电压，阈值电压的大小通常为0V。控制端为升压晶体管T2的栅极，第一端为升压晶体管T2的源极。
如图11所示，当升压电路包括升压晶体管时，在本公开的其它实施例的信号选择器的驱动方法中，第一子信号线MUX1滞后于第二子信号线MUX2导通。该驱动方法首先将加载于第二子信号线MUX2的电压由-8V增大到8V，与第一红色子像素R1连接的输出数据线Source的电压，受到与第一子输入数据线S1电连接的驱动芯片的驱动由0V上升到4.9V。
然后将加载于第一子信号线MUX1上的电压由-8V增大到8V，在升压晶体管的电容耦合作用下，与第一红色子像素R1连接的输出数据线Source的电压由4.9V上升到5.02V，相较于图中信号选择器的4.98V仅提升0.04V，提升效果不明显，原因是由于第一子信号线MUX1由-8V增大到8V时，升压晶体管的电容值达到最大值，所以耦合效果较差。
本公开提供一种显示面板。如图12至图20所示，显示面板包括依次层叠设置的衬底基板BP、驱动电路层和彩膜层。其中，彩膜层设置有阵列分布的滤光部，驱动电路层设置有与各个子像素一一对应的驱动电路；各个子像素在对应的驱动电路的驱动下，改变来控制液晶分子的转动方向，达到控制每个子像素点偏振光出射与否而达到显示目的，从而实现显示相应的图像。
在驱动电路层中，显示面板可以设置有沿第一方向延伸的扫描走线和沿第二方向延伸的数据走线；该显示面板可以实现逐行扫描以显示画面。需要说明的是，第一方向一般作为行方向，第二方向一般作为列方向。
参见图12，从膜层层叠的角度，本公开的显示面板可以包括依次层叠设置的衬底基板BP、缓冲层Buffer和驱动电路层，衬底基板BP的一侧设有缓冲层Buffer，缓冲层Buffer远离衬底基板BP的一侧设驱动电路层。
衬底基板BP11可以为无机材料的衬底基板BP，也可以为有机材料的衬底基板BP。举例而言，在本公开的一种实施方式中，衬底基板BP的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。
在本公开的另一种实施方式中，衬底基板BP的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl  alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。
在本公开的另一种实施方式中，衬底基板BP也可以为柔性衬底基板BP，例如衬底基板BP的材料可以为聚酰亚胺(polyimide，PI)。衬底基板BP还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板BP可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
驱动电路层包括多个驱动电路区。任意一个驱动电路区可以包括晶体管和存储电容。晶体管可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管。
薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
晶体管可以具有第一端、第二端和控制端，第一端和第二端中的一个可以为晶体管的源极且另一个可以为晶体管的漏极，控制端可以为晶体管的栅极。可以理解的是，晶体管的源极和漏极为两个相对且可以相互转换的概念；当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
在本公开中，驱动电路层可以包括依次层叠于衬底基板BP的晶体管层、层间电介质层ILD和源漏金属层LSD。其中，晶体管层中设置有晶体管的有源层和栅极，源漏金属层LSD与晶体管的源极和漏极电连接。可选地，晶体管层可以包括层叠于衬底基板BP和层间电介质层ILD之间的有源层Lpoly、栅极绝缘层GI、栅极层LG。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。
在一些实施方式中，有源层Lpoly可以用于形成晶体管的有源层，半导体的有源层包括沟道区和位于沟道区两侧的源极、漏极；其中，沟道区可以保持半导体特性，源极和漏极的半导体材料被局部或者全部导体化。栅极层LG可以用于形成扫描走线等栅极层走线，也可以用于形成晶体管 的栅极，还可以用于形成存储电容的部分或者全部电极板。源漏金属层LSD可以用于形成数据走线、电源走线等源漏金属层走线。
以顶栅型薄膜晶体管为例，在本公开的一些实施方式中，驱动电路层可以包括依次层叠设置的有源层Lpoly、栅极绝缘层GI、栅极层LG、层间电介质层ILD和源漏金属层LSD。
显示面板具有显示区AA和设于显示区AA外围的非显示区BB，每个驱动电路区包括开关电路区和驱动晶体管，开关电路区位于非显示区BB，驱动晶体管位于显示区AA，开关电路区包括开关晶体管，驱动晶体管的控制端可以与开关晶体管的第二端连接。
当显示面板为LCD时，在上述基础上，显示面板显示区AA的驱动电路层还可以包括平坦化层PLN，根据不同情况，平坦化层PLN可以设为一层或者多层。平坦化层PLN可以设于驱动晶体管的源漏金属层LSD远离衬底基板BP的一侧，且平坦化层PLN远离衬底基板BP的表面为平面。平坦化层PLN间隔设有露出驱动晶体管的源漏金属层LSD的多个第一过孔。平坦化层PLN远离衬底基板BP的一侧可以设有公共电极LCOM，公共电极LCOM间隔设有多个第二过孔，第二过孔在衬底基板BP上的正投影位于第一过孔在衬底基板BP上的正投影内。
公共电极LCOM远离衬底基板BP的一侧设有保护层PVX，保护层PVX覆盖公共电极LCOM远离衬底基板BP的一侧，保护层PVX自公共电极LCOM设有第二过孔的部位及平坦化层PLN设有第一过孔的部位，延伸至驱动晶体管的源漏金属层LSD，保护层PVX靠近衬底基板BP的一端部分覆盖驱动晶体管的源漏金属层LSD，形成露出部分驱动晶体管的源漏金属层LSD的开口。保护层PVX远离衬底基板BP的一侧设有多个像素电极LAn，像素电极LAn设于开口内且与驱动晶体管的源漏金属层LSD连接。
在像素电极LAn远离驱动晶体管的源漏金属层LSD的一侧设有液晶层LCL，液晶层LCL覆盖保护层PVX和驱动晶体管的源漏金属层LSD。因像素电极LAn和公共电极LCOM之间设有保护层PVX，像素电极LAn和公共电极LCOM都具有驱动面，所以可认为液晶层LCL位于像素电极LAn和公共电极LCOM之间。
液晶层LCL远离衬底基板的一侧设有彩膜层CF，可以在显示区AA的彩膜层CF和非显示区BB的平坦化层PLN远离衬底基板BP的一侧设置绝缘层IL，绝缘层IL自彩膜层CF远离衬底基板BP的表面，延伸至彩膜层CF的侧面、液晶层LCL的侧面、保护层PVX的侧面及公共电极LCOM的侧面，并且覆盖非显示区BB平坦化层PLN远离衬底基板的一面。
如图13至图16所示，在显示面板的非显示区，有源层Lpoly包括第一有源部T1A、第三有源部T1S、第四有源部T1D。
栅极层LG包括沿第一方向H1设置的第一控制引线GL1和第一输入数据线，第一控制引线GL1在衬底基板BP上的正投影与第一有源部T1A在衬底基板BP上的正投影交叠，构成开关晶体管的栅极。
源漏金属层LSD包括沿第一方向H1设置的第一导电结构ML1、第二导电结构ML2和输出数据线Source，第一导电结构ML1与第一输入数据线转接，第一导电结构ML1在衬底基板BP上的正投影与第三有源部T1S在衬底基板BP上的正投影交叠且连接，构成开关晶体管的源极。第二导电结构ML2在衬底基板BP上的正投影与第四有源部T1D在衬底基板BP上的正投影交叠且连接，构成开关晶体管的漏极和升压晶体管的漏极。第二导电结构ML2与输出数据线Source连接。
开关电路区CC还包括升压电路，当该显示面板的升压电路为升压晶体管时，有源层Lpoly还包括第二有源部T2A和第五有源部T2S。栅极层LG还包括第二控制引线GL2，第二控制引线GL2在衬底基板BP上的正投影与第二有源部T2A在衬底基板BP上的正投影交叠，构成升压晶体管的栅极。
源漏金属层LSD还包括第三导电结构ML3，第三导电结构ML3在衬底基板BP上的正投影与第五有源部T2S在衬底基板BP上的正投影交叠，第三导电结构与第五有源部T2S连接，构成升压晶体管的源极。第三导电结构ML3与第二导电结构ML2连接，第三导电结构ML3和第二导电结构ML2均与输出数据线Source连接。
需要说明的是，在第一方向H1上，第二导电结构ML2在衬底基板BP上的正投影位于第一导电结构ML1在衬底基板BP上的正投影和第三 导电结构ML3在衬底基板BP上的正投影之间。第二导电结构ML2在衬底基板BP上的正投影位于第一控制引线GL1在衬底基板BP上的正投影的外侧，第三导电结构ML3在衬底基板BP上的正投影位于第二控制引线GL2在衬底基板BP上的正投影的外侧。
另外，源漏金属层LSD还可以包括沿第二方向H2设置的第一信号线、第二信号线，第二信号线与第一控制引线GL1转接，第一信号线与第二控制引线转接。
以六个子信号线的信号选择器为例进行说明，开关电路区CC的数量为六个。六个开关电路区CC分为两个开关电路区组，每个开关电路区组形成一个开关电路岛，每个开关电路岛包括三个开关电路区CC，三个开关电路区CC沿第一方向H1依次设置，三个开关电路区CC的输出数据线Source分别连接红色子像素、绿色子像素和蓝色子像素。
具体地，一个开关电路岛中的三个开关电路区CC，第一个开关电路区CC的输出数据线Source连接红色子像素所对应的驱动晶体管的控制端，第二个开关电路区CC的输出数据线Source连接绿色子像素所对应的驱动晶体管的控制端，第三个开关电路区CC的输出数据线Source连接蓝色子像素所对应的驱动晶体管的控制端。
源漏金属层LSD还包括第一转接线TR1，一根第一转接线TR1与一开关电路区组中的各第一导电结构ML1连接，第一子输入数据线S1与第一转接线TR1连接。另一根第一转接线TR1与另一个开关电路区组中的各第一导电结构ML1连接，第二子输入数据线S2与第二转接线TR2连接。
栅极层LG还可以包括第二输入数据线S3、触控信号线TX和第二转接线TR2，第二转接线TR2沿第一方向H1延伸，第二输入数据线S3和触控信号线TX沿第二方向H2延伸，第二输入数据线S3位于第二转接线TR2靠近信号线的一侧，触控信号线TX位于第二转接线TR2远离信号线的一侧。在第二方向上第二输入数据线S3和触控信号线TX均与第二转接线TR2连接，触控信号线TX可以设为两条，两条触控信号线TX沿第一方向H1分布于第二输入数据线S3的两侧。第二输入数据线S3上的触控信号分配至不同的触控信号线TX上，触控信号线TX用于 驱动显示面板的触控电极。
为了保证显示面板的正常显示，通常需保证相邻子像素的数据信号的正负极性不同。通常第一子输入数据线S1和第二子输入数据线S2分别输入正的总数据信号和负的总数据信号，为了保证相邻输出子数据信号的正负极性不同，需要设置转接线对个别输出子数据信号的正负极性进行调整。
例如，第一子输入数据线S1输入正的总数据信号，第二子输入数据线S2输入负的总数据信号，子像素包括沿第一方向依次分布的第一红色子像素R1、第一绿色子像素G1、第一蓝色子像素B1、第二红色子像素R2、第二绿色子像素G2和第三蓝色子像素B2；第一子输入数据线S1和第二子输入数据线S2分别对应一组输出数据线Source，输出数据线Source包括第一输出数据线、第二输出数据线和第三输出数据线。
与第一输入数据线S1对应的第一输出数据线连接第一红色子像素R1，与第一输入数据线S1对应的第三输出数据线连接第一蓝色子像素，与第二输入数据线S2对应的第一输出数据线连接第二红色子像素，与第二输入数据线S2对应的第三输出数据线连接第二蓝色子像素。
显示面板还包第三转接线TR3和第四转接线TR4，与第一输入数据线S1对应的第二输出数据线与第三转接线TR3连接，第三转接线TR3连接第二绿色子像素G2，与第二输入数据线S2对应的第二输出数据线与第四转接线TR4连接，第四转接线TR4连接第一绿色子像素G1。
第三转接线TR3可以包括第一转接段TR31和第二转接段TR32，第一转接段TR31与第一绿色子像素G1连接的输出数据线Source连接，且与第二转接段TR32连接，第二转接段TR32与第二绿色子像素G2的驱动晶体管的源极连接。第四转接线TR4可以包括第三转接段TR41和第四转接段TR42，第三转接段TR41与第二绿色子像素G2连接的输出数据线Source连接，且与第四转接段TR52连接，第四转接段TR52与第一绿色子像素G1的驱动晶体管的源极连接。
这样一来，第一红色子像素R1、第二绿色子像素G2、第一蓝色子像素B1、第二红色子像素R2、第一绿色子像素G1和第二蓝色子像素B2的子数据信号依次为“正、负、正、负、正、负”，满足显示面板的 显示要求。
如图17至图20所示，本公开提供另一种显示面板。该显示面板与图13至图16中显示面板的不同之处在于，升压电路为升压电容。
当升压电路为升压电容时，有源层Lpoly仅包括开关晶体管的源极T1S、漏极T1D、第一有源部T1A。
栅极层LG包括沿第一方向H1设置的第一控制引线GL1、第二控制引线GL2和输入数据线，第一控制引线GL1在衬底基板BP上的正投影与第一有源部T1A交叠，构成开关晶体管的栅极。
源漏金属层LSD包括沿第一方向H1设置的第一导电结构ML1、第二导电结构ML2、第三导电结构ML3和输出数据线Source，在第一方向H1上，第二导电结构ML2位于第一导电结构ML1和第三导电结构ML3之间，第二导电结构ML2和第三导电结构ML3与输出数据线Source连接。
第一导电结构ML1与输入数据线转接，第一导电结构ML1在衬底基板BP上的正投影与第三有源部T1S在衬底基板BP上的正投影交叠且连接，构成开关晶体管的源极。第二导电结构ML2在衬底基板BP上的正投影与第四有源部T1D在衬底基板BP上的正投影交叠且连接，构成开关晶体管的漏极和升压晶体管的漏极。
另外，源漏金属层LSD还可以包括沿第二方向H2设置的第一信号线、第二信号线，第二信号线与第一控制引线GL1转接，第一信号线与二控制引线转接。
为了保证电容的大小，第二控制引线GL2和第三导电结构ML3的面积通常不会太小，为了防止形成大片金属，第二导电结构上沿第二方向H2设有多个第一通孔HA1，第三导电结构上沿第二方向H2设有多个第二通孔HA2，第二通孔HA2在衬底基板BP上的正投影位于第一通孔HA1在衬底基板BP上的正投影内，更为具体地，可以是第二通孔HA2在衬底基板BP上的正投影与第一通孔HA1在衬底基板BP上的正投影重合。
驱动背板与彩膜层之间的边缘通常通过光学固化胶进行固化，光线从第一通孔HA1和第二通孔HA2透过，改善对光学固化胶的固化效果，从而影响从而影响驱动背板与彩膜层CF之间的固定强度。需要说明的是， 光学固化胶可以为UV胶。
本公开实施方式提供了一种显示装置。该显示装置包括本公开实施方式上面任一项所述的显示面板。该显示装置同样可参考显示面板的具体结构和有益效果，在此不再进行赘述。
显示装置可以是传统电子设备，例如：手机、电脑、电视和摄录放影机，也可以是新兴的穿戴设备，例如：虚拟现实设备和增强现实设备，在此不一一进行列举。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以手机为例，具体例如外壳、电路板，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
需要说明的是，尽管在附图中以特定顺序描述了本公开中显示面板的制作方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种信号选择器，用于将输入数据线上的信号分配至不同的输出数据线上，所述输出数据线用于驱动显示面板的子像素，其中，
    所述信号选择器包括多个开关单元，任意一个所述开关单元包括：
    开关电路，所述开关电路连接所述输入数据线和一个所述输出数据线，所述开关电路用于响应加载于其控制端上的写入信号而导通；
    升压电路，所述升压电路的第一端与开关电路的输出端电连接；所述升压电路用于，响应加载于其控制端的升压控制信号而拉高开关电路的输出端的电压。
  2. 根据权利要求1所述的信号选择器，其中，所述升压电路包括一个升压晶体管，升压晶体管的第一端和/或第二端作为所述升压电路的第一端而与开关电路的输出端电连接；升压晶体管的控制端作为所述升压电路的第二端用于加载升压控制信号。
  3. 根据权利要求1所述的信号选择器，其中，所述升压电路包括升压电容，升压电容的一个电极板作为升压电路的第一端而与开关单元的输出端电连接；升压电容的另一个电极板作为第二端用于加载升压控制信号。
  4. 根据权利要求1所述的信号选择器，其中，多个所述开关单元分为多个开关单元组，每个所述开关单元组包括至少三个开关单元，不同所述开关单元所连接的输出数据线分别与不同颜色的子像素连接。
  5. 根据权利要求1所述的信号选择器，其中，所述信号选择器包括多条输入数据线，一条所述输入数据线连接一个所述开关单组元。
  6. 根据权利要求1所述的信号选择器，其中，所述开关电路为开关晶体管，所述开关电路的第一端为所述开关晶体管的源极，所述开关电路的第二端为所述升压晶体管的漏极，所述开关电路的控制端为所述升压晶体管的栅极。
  7. 一种显示面板，其中，包括权利要求1至6任一项所述的信号选择器。
  8. 一种显示面板，其中，包括衬底基板和设于衬底基板一侧的驱动电路层，所述驱动电路层包括多个开关电路区，所述开关电路区包括：
    有源层，设于所述衬底基板的一侧，所述有源层包括第一有源部、第二有源部、第三有源部、第四有源部和第五有源部；
    栅极层，设于所述有源层远离所述衬底基板的一侧，所述栅极层包括沿第二方向设置的第一控制引线、第二控制引线和第一输入数据线，所述第一控制引线在所述衬底基板上的正投影与所述第一有源部在所述衬底基板上的正投影交叠，所述第二控制引线在所述衬底基板上的正投影与所述第二有源部在所述衬底基板上的正投影交叠；
    源漏金属层，设于所述栅极层远离所述衬底基板的一侧，所述源漏金属层包括沿第一方向设置的第一信号线、第二信号线，以及沿第二方向设置的第一导电结构、第二导电结构、第三导电结构和输出数据线，所述第二信号线与所述第一控制引线转接，所述第一信号线与所述第二控制引线转接；所述第一导电结构与所述第一输入数据线转接，所述第一导电结构在衬底基板上的正投影与所述第三有源部在所述衬底基板上的正投影交叠，所述第一导电结构与所述第三有源部连接，所述第二导电结构在衬底基板上的正投影与所述第四有源部在衬底基板上的正投影交叠，所述第二导电结构与所述第四有源部连接，所述第三导电结构在衬底基板上的正投影与所述第五有源部在衬底基板上的正投影交叠，所述第三导电结构与所述第五有源部连接，所述第三导电结构与所述第二导电结构连接，所述第二导电结构和所述第三导电结构与所述输出数据线连接。
  9. 根据权利要求8所述的显示面板，其中，在第一方向上，第二导电结构在所述衬底基板上的正投影，位于所述第一控制引线在所述衬底基板上的正投影与第二控制引线在所述衬底基板上的正投影之间，所述第二导电结构在所述衬底基板上的正投影位于所述第一控制引线在所述衬底基板上的正投影的外侧，所述第三导电结构在所述衬底基板上的正投影位于所述第二控制引线在所述衬底基板上的正投影的外侧。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板包括多个开关电路区组，每组所述开关电路区包括至少三个开关电路区，至少三个所述开关电路区沿第一方向间隔设置，每个所述开关电路区连接的输出数据线连接一种颜色的子像素，相邻两个不同子像素的驱动端的正负极性不同。
  11. 根据权利要求8所述的显示面板，其中，多个所述开关电路区分为多个开关电路区组，每个开关电路区组包括至少三个开关电路区，所述源漏金属层还包括沿第一方向设置的至少一条第一转接线，一条所述第一转接线与一个所述开关电路区组中的各所述第一导电结构连接，且所述第一输入数据线与所述第一转接线转接。
  12. 根据权利要求11所述的显示面板，其中，所述第一输入数据线包括第一子输入数据线和第二子输入数据线，所述第一子输入数据线输入正的总数据信号，第二子输入数据线输入负的总数据信号，所述子像素包括沿第一方向依次分布的第一红色子像素、第一绿色子像素、第一蓝色子像素、第二红色子像素、第二绿色子像素和第三蓝色子像素；所述第一子输入数据线和所述第二子输入数据线分别对应一组第一输出数据线、第二输出数据线和第三输出数据线，与所述第一输入数据线对应的所述第一输出数据线连接第一红色子像素，与所述第一输入数据线对应的所述第三输出数据线连接第一蓝色子像素，与所述第二输入数据线对应的所述第一输出数据线连接第二红色子像素，与所述第二输入数据线对应的所述第三输出数据线连接第二蓝色子像素，所述显示面板还包第三转接线和第四转接线，与所述第一输入数据线对应的第二输出数据线与第三转接线连接，所述第三转接线连接第二绿色子像素，与所述第二输入数据线对应的第二输出数据线与第四转接线连接，所述第四转接线连接第一绿色子像素。
  13. 根据权利要求8所述的显示面板，其中，所述第一信号线包括第一子信号线、第三子信号线和第五子信号线，所述第二信号线包括第二子信号线、第四子信号线和第六子信号线，每个所述开关电路区组包括三个开关电路区，第一个开关电路区的第二控制引线与所述第一子信号线连接，第二个开关电路区的第二控制引线与所述第三子信号线连接，第三个开关电路区的第二控制引线与所述第五子信号线连接，第一个开关电路区的第一控制引线与所述第二子信号线连接，第二个开关电路区的第一控制引线与所述第四子信号线连接，第三个开关电路区的第一控制引线与所述第六子信号线连接。
  14. 根据权利要求8所述的显示面板，其中，所述栅极层还包括第 二输入数据线、第二转接线和触控信号线，所述第二转接线沿第一方向设置，所述第二输入数据线和所述触控信号线沿第二方向设置，所述第二转接线连接所述第二输入数据线和所述触控信号线，所述第二输入数据线上的触控信号分配至不同的触控信号线上，所述触控信号线用于驱动显示面板的触控电极。
  15. 一种显示面板，其中，包括衬底基板和设于衬底基板一侧的驱动电路层，所述驱动电路层包括多个开关电路区，所述开关电路区包括：
    有源层，设于所述衬底基板的一侧，所述有源层包括第一有源部、第二有源部和第三有源部；
    栅极层，设于所述有源层远离所述衬底基板的一侧，所述栅极层包括第一控制引线、第二控制引线和输入数据线，所述第一控制引线在所述衬底基板上的正投影与所述第一有源部在所述衬底基板上的正投影交叠；
    源漏金属层，设于所述栅极层远离所述衬底基板的一侧，所述源漏金属层包括沿第一方向设置的第一信号线、第二信号线，以及沿第二方向设置的第一导电结构、第二导电结构、第三导电结构和输出数据线，所述第二信号线与所述第一控制引线转接，所述第一信号线与所述第二控制引线转接；所述第一导电结构与第一所述输入数据线转接，所述第一导电结构在所述衬底基板上的正投影与所述第三有源部在所述衬底基板上的正投影交叠，所述第一导电结构与所述开关晶体管的源极连接，所述第二导电结构在所述衬底基板上的正投影与所述第四有源部在所述衬底基板上的正投影交叠，所述第二导电结构与所述开关晶体管的漏极连接，所述第三导电结构在所述衬底基板上的正投影与所述第二控制线在所述衬底基板上的正投影交叠，所述第三导电结构与所述第二控制线构成存储电容，所述第三导电结构与所述第二导电结构连接，所述第二导电结构和所述第三导电结构与所述输出数据线连接。
  16. 根据权利15所述的显示面板，其中，所述第二导电结构上设有多个第一通孔，所述第三导电结构上设有多个第二通孔，所述第二通孔在所述衬底基板上的正投影位于所述第一通孔在所述衬底基板上的正投影内。
  17. 一种显示装置，其中，包括权利要求7至16任一项所述的显示面板。
  18. 一种权利要求1所述的信号选择器的驱动方法，其中，所述方法包括：
    在数据写入时段，向开关电路的控制端加载写入信号；
    在数据写入时段之后的拉升时段，向升压电路的控制端加载升压控制信号。
  19. 根据权利要求18所述的信号选择器的驱动方法，其中，所述升压电路包括升压晶体管；
    所述驱动方法还包括：
    在数据写入时段之前的预备时段，向升压晶体管的栅极加载预备电压，使得升压晶体管的Vgs不小于升压晶体管的Vth。
  20. 根据权利要求19所述的信号选择器的驱动方法，其中，所述写入信号的下降沿相对于所述升压信号的下降沿的滞后时长至少大于所述写入信号的一个脉冲宽度。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05232508A (ja) * 1992-02-21 1993-09-10 Hitachi Ltd 液晶表示装置
CN110136668A (zh) * 2018-11-09 2019-08-16 友达光电股份有限公司 驱动电路以及驱动方法
TW202020850A (zh) * 2018-11-23 2020-06-01 友達光電股份有限公司 顯示裝置
CN112712778A (zh) * 2019-10-25 2021-04-27 夏普株式会社 显示装置及其驱动方法
US20210241709A1 (en) * 2020-01-31 2021-08-05 Sharp Kabushiki Kaisha Display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05232508A (ja) * 1992-02-21 1993-09-10 Hitachi Ltd 液晶表示装置
CN110136668A (zh) * 2018-11-09 2019-08-16 友达光电股份有限公司 驱动电路以及驱动方法
TW202020850A (zh) * 2018-11-23 2020-06-01 友達光電股份有限公司 顯示裝置
CN112712778A (zh) * 2019-10-25 2021-04-27 夏普株式会社 显示装置及其驱动方法
US20210241709A1 (en) * 2020-01-31 2021-08-05 Sharp Kabushiki Kaisha Display device

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