WO2023280097A1 - 一种缺页异常的处理方法及相应装置 - Google Patents

一种缺页异常的处理方法及相应装置 Download PDF

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Publication number
WO2023280097A1
WO2023280097A1 PCT/CN2022/103611 CN2022103611W WO2023280097A1 WO 2023280097 A1 WO2023280097 A1 WO 2023280097A1 CN 2022103611 W CN2022103611 W CN 2022103611W WO 2023280097 A1 WO2023280097 A1 WO 2023280097A1
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coroutine
thread
context
page
shared memory
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PCT/CN2022/103611
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English (en)
French (fr)
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林妙和
严晓丹
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华为技术有限公司
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Priority to EP22836848.6A priority Critical patent/EP4336359A1/en
Publication of WO2023280097A1 publication Critical patent/WO2023280097A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/545—Interprogram communication where tasks reside in different layers, e.g. user- and kernel-space

Definitions

  • the present application relates to the field of computer technology, in particular to a page fault processing method and a corresponding device.
  • LWT lightweight threads
  • PF page fault
  • PF page fault
  • the current method of handling page fault exceptions will cause the LWT task that has a page fault to block the entire thread, resulting in a decrease in business throughput and long-tail delays for the thread.
  • An embodiment of the present application provides a method for processing a page fault exception, which is used to reduce the delay in processing the page fault exception and improve service throughput.
  • Embodiments of the present application also provide corresponding devices, computer equipment, computer-readable storage media, computer program products, and the like.
  • the first aspect of the present application provides a page fault processing method, the method is applied to a computer system, and the computer system can be a server, a terminal device, a virtual machine (virtual machine, VM) or a container (container).
  • the method includes: saving the context of the first coroutine that triggers the page fault exception into a shared memory, the first coroutine belongs to the first thread, and the shared memory is the memory that the first thread can access in both the kernel mode and the user mode; Switch from the context of the first coroutine to the context of the first thread.
  • the context of the first thread is configured to the shared memory when the first thread is initialized; switch from kernel mode to user mode; obtain the second thread from the shared memory by running the first thread A coroutine context to trigger the page swap process.
  • a page fault can also be referred to as a page fault, which usually occurs in the kernel state of an operating system (OS).
  • OS operating system
  • the processing will involve kernel mode and user mode.
  • the kernel mode and the user mode are two modes or states of the OS.
  • the kernel mode is usually also called a privileged state, and the user mode is usually also called a non-privileged state.
  • a thread is the smallest unit of operating system scheduling (processor scheduling).
  • a coroutine is a lightweight thread.
  • a thread can include multiple coroutines, and each coroutine can correspond to a task. Sometimes a coroutine is called a coroutine task.
  • the "first" in the first thread has no substantive meaning, and is just a thread that has a page fault exception during operation.
  • the first thread may also be called a service thread or an application thread.
  • the context of the first coroutine includes data in registers of the processor when the first coroutine is running.
  • the context of the first thread includes reading data written into registers from shared memory. Switching from the context of the first coroutine to the context of the first thread refers to writing the context of the first thread into a register of the processor.
  • the above registers may include any one or more of a general register, a program counter (program counter, PC), a program state register (program state, PS) and the like.
  • the context of the first coroutine is saved in the shared memory in the kernel mode, and after returning to the user mode from the kernel mode, the context of the first coroutine can be obtained from the shared memory by running the first thread , and then execute the page swap process according to the context of the first coroutine.
  • the monitor thread when a coroutine of the thread triggers a page fault exception, the monitor thread should be notified in the kernel state, and then the thread enters the Sleep state, until the monitor thread completes the page swap through the swap in thread, then send a notification message to the kernel state, wake up the thread, and then continue to execute the coroutine.
  • the time delay of abnormal page fault processing can be shortened, thereby reducing the long-tail delay of the first thread, shortening the time delay and correspondingly improving the service throughput.
  • the long-tail delay refers to: in the process of running a thread in a computer system, there will always be a small number of response delays of operations corresponding to the thread that are higher than the average delay of the computer system.
  • the delay is called the long-tail delay.
  • the long-tail delay For example: there are 100 responses in the computer system, and the average delay of these 100 responses is 10 microseconds, among them, the delay of one response is 50 milliseconds, then, the delay of this response is the long-tail delay.
  • P99 standard for business delays there is a commonly used P99 standard for business delays.
  • long-tail delay in this P99 standard is: the delay of 99% of the responses in the computer system should be controlled within a certain time-consuming period, and only 1% of the response delays can be allowed to exceed The certain time-consuming, and the delay of the response exceeding the certain time-consuming is called long-tail delay.
  • the long-tail delay of a thread can be understood as the long-tail delay when the thread performs an input/output (IO) operation. If no page fault occurs during the running of the thread, it is completed once The IO operation may take 10 microseconds. If a page fault occurs, it will take hundreds of microseconds to process the page fault according to the existing technology, which causes the long-tail delay of the thread executing this IO.
  • the solution provided by the application is used to handle page fault exceptions, and it usually only takes a few microseconds to handle page fault exceptions, thus greatly reducing the long-tail delay of the thread.
  • the method further includes: when executing the page swap process, running a second coroutine belonging to the first thread to execute a task corresponding to the second coroutine.
  • running the second coroutine when the page swapping process is executed may be understood as running the second coroutine during the execution of the page swapping process, that is: the page swapping process
  • the second coroutine can start at the same time as the page swap process, or it can start at the page swap process Start later.
  • the second coroutine when the page switching process is executed, the second coroutine can also be run asynchronously, which can further improve the service throughput.
  • the above step: switching from the context of the first coroutine to the context of the first thread includes: writing the context of the first thread into a register of the computer system through a hook function, to replace the context of the first coroutine in registers.
  • the operating system may perform context switching through a hook function, and write the context of the first thread into a register of the computer system, thereby overwriting the context of the first coroutine originally stored in the register.
  • the above steps: obtaining the context of the first coroutine from the shared memory by running the first thread to trigger the page swap process include: obtaining the context of the first coroutine from the shared memory by running the first thread The context of the first coroutine, and obtain the destination address from the context of the first coroutine, the destination address is the address of the physical page to be accessed when the first coroutine triggers a page fault exception; according to the destination address, perform the swap of the corresponding physical page into the process.
  • the context of the first coroutine includes the address of the physical page to be accessed when the first coroutine triggers a page fault exception, that is, the destination address, so that the computer system can swap in the page from the disk.
  • the physical page corresponding to the destination address. This method of directly swapping in the physical page through the destination address can increase the speed of swapping in the physical page, thereby further reducing the time delay of page fault exception processing.
  • the method further includes: after the physical page is swapped into the memory, adding the first coroutine to the coroutine waiting queue, and the coroutines in the coroutine waiting queue are in a state to be scheduled .
  • the first coroutine can be re-executed, and the execution order can be that the first coroutine is put into the coroutine waiting queue for scheduling.
  • the execution order can be that the first coroutine is put into the coroutine waiting queue for scheduling.
  • One or more coroutines are placed in order in the coroutine waiting queue, and the computer system will schedule and execute the coroutines in sequence according to the order in the coroutine waiting queue.
  • the shared memory is configured for the first thread when the first thread is initialized.
  • the page fault exception is triggered when the first coroutine accesses the swapped out physical page in the memory.
  • the shared memory is configured through a kernel virtual machine (extended berkeley packet filter, ebpf).
  • ebpf extended berkeley packet filter
  • ebpf is a brand-new design introduced in kernel (kernel) 3.15, which develops the original BPF into a "kernel virtual machine” with a more complex instruction set and a wider application range.
  • the second aspect of the present application provides an apparatus for processing page fault exceptions, and the apparatus for processing page fault exceptions has the function of implementing the method of the above-mentioned first aspect or any possible implementation manner of the first aspect.
  • This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware.
  • the hardware or software includes one or more modules corresponding to the above-mentioned functions, for example: a first processing unit, a second processing unit, a third processing unit, and a fourth processing unit. These four processing units can be processed by one processing unit or Multiple processing units are implemented.
  • a third aspect of the present application provides a computer device, the computer device includes at least one processor, a memory, an input/output (input/output, I/O) interface, and a computer executable program stored in the memory and operable on the processor Instructions, when the computer-executed instructions are executed by the processor, the processor executes the method according to the above first aspect or any possible implementation manner of the first aspect.
  • the fourth aspect of the present application provides a computer-readable storage medium that stores one or more computer-executable instructions.
  • the computer-executable instructions are executed by a processor, one or more processors execute any of the above-mentioned first aspect or first aspect.
  • the fifth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the computer-executable instructions are executed by one or more processors, one or more processors execute the above-mentioned first aspect or first A method for any one of the possible implementations of the aspect.
  • the sixth aspect of the present application provides a chip system, the chip system includes at least one processor, and the at least one processor is used to support the page fault exception processing device to implement the above-mentioned first aspect or any possible implementation of the first aspect the functions involved.
  • the system-on-a-chip may further include a memory, and the memory is used to store necessary program instructions and data of the page fault processing device.
  • the system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • the context of the first coroutine is saved in the shared memory in the kernel mode, and after the OS returns to the user mode from the kernel mode, the first thread can be run from the Obtain the context of the first coroutine in the shared memory, and then execute the page swap process according to the context of the first coroutine.
  • the monitoring (monitor) thread is notified in the kernel state, and then the first thread enters Sleep state, until the monitor thread completes the page swap through the swap in thread, then send a notification message to the kernel, wake up the first thread, and then continue to execute the page fault exception handling process of the first thread to shorten the page fault
  • the delay of abnormal processing shortens the delay and improves the service throughput accordingly.
  • FIG. 1 is a schematic diagram of an embodiment of a computer system provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a page fault exception processing architecture provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of an embodiment of a page fault processing method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another embodiment of the page fault processing method provided by the embodiment of the present application.
  • Fig. 5 is a schematic diagram of another embodiment of the method for processing a page fault provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of another embodiment of the page fault processing method provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of another embodiment of the method for processing a page fault provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of another embodiment of the method for processing a page fault provided by the embodiment of the present application.
  • FIG. 9 is a schematic diagram of an embodiment of a page fault processing device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • An embodiment of the present application provides a method for processing a page fault exception, which is used to reduce the delay in processing the page fault exception and improve service throughput.
  • Embodiments of the present application also provide corresponding devices, computer equipment, computer-readable storage media, computer program products, and the like. Each will be described in detail below.
  • the page fault exception handling method provided in the embodiment of the present application is applied to a computer system, and the computer system may be a server, a terminal device or a virtual machine (virtual machine, VM).
  • the computer system may be a server, a terminal device or a virtual machine (virtual machine, VM).
  • Terminal equipment also called user equipment (UE) is a device with wireless transceiver function, which can be deployed on land, including indoor or outdoor, handheld or vehicle-mounted; it can also be deployed on water (such as ships etc.); can also be deployed in the air (such as aircraft, balloons and satellites, etc.).
  • the terminal may be a mobile phone, a tablet computer (pad), a computer with a wireless transceiver function, a virtual reality (virtual reality, VR) terminal, an augmented reality (augmented reality, AR) terminal, an industrial control (industrial control) Wireless terminals in self driving, wireless terminals in remote medical, wireless terminals in smart grid, wireless terminals in transportation safety, Wireless terminals in smart cities, wireless terminals in smart homes, etc.
  • FIG. 1 is a schematic diagram of an architecture of a computer system.
  • the architecture of the computer system includes a user layer 10 , a kernel 20 and a hardware layer 30 .
  • the user layer 10 includes multiple applications, each of which corresponds to a thread, and a thread is the smallest unit for scheduling by an operating system (operating system, OS).
  • a thread can include multiple coroutines, and a coroutine is a lightweight thread. Each coroutine can correspond to a task, and the coroutine is sometimes called a coroutine task.
  • a thread may also be called a business thread or an application thread.
  • Kernel 20 is the OS responsible for managing key resources, and provides OS call entry for user-mode threads and then provides services in the kernel, such as: page fault (page fault, PF) processing, page table management, and interrupt control services.
  • the kernel 20 also handles a page fault (PF) that occurs in the OS.
  • PF page fault
  • a page fault (PF) can also be called a page fault, which usually occurs in the kernel mode of the operating system. After a page fault occurs, the page fault exception needs to be processed.
  • the processing process will involve the kernel mode and the user mode. .
  • the kernel mode and the user mode are two modes or states of the OS.
  • the kernel mode is usually also called a privileged state, and the user mode is usually also called a non-privileged state.
  • the hardware layer 30 includes the hardware resources that the kernel 20 runs on, such as: processor, memory (comprising the shared memory configured for the thread in this memory, in this application, the shared memory refers to the thread that can be used in both the kernel state and the user state. Accessed memory), memory management unit (memory management unit, MMU), and input/output (input/output, I/O) devices and disks (disk).
  • the processor may include a register set, and the register set may include multiple types of registers, such as stack frame registers, general registers, and non-volatile (callee-saved) registers.
  • the corresponding physical page can be swapped in (swap in) from the disk through the page fault processing mechanism, thereby solving the page fault problem.
  • An MMU is a piece of computer hardware responsible for handling memory access requests from a central processing unit (CPU). Its functions include translation from virtual address to physical address, memory protection, control of CPU cache, etc.
  • an application is usually bound to a thread, and a thread includes multiple lightweight threads (LWT), which are also called coroutines.
  • LWT lightweight threads
  • This thread will execute the tasks corresponding to the included multiple coroutines, and the tasks corresponding to the coroutines may also be called coroutine tasks.
  • Threads will execute coroutine tasks one by one.
  • the current page fault exception handling scheme will notify the monitoring (monitor) thread in the kernel state, and then the thread will go to sleep until the monitor After the thread completes the page swap through the swap in thread, it sends a notification message to the kernel state, wakes up the thread, and then continues to execute the coroutine task.
  • the coroutine task that triggers the page fault will block the entire thread, resulting in a decrease in business throughput and a long tail delay for the thread.
  • the long-tail delay refers to: in the process of running a thread in a computer system, there will always be a small number of response delays of operations corresponding to the thread that are higher than the average delay of the computer system.
  • the delay is called the long-tail delay.
  • the long-tail delay For example: there are 100 responses in the computer system, and the average delay of these 100 responses is 10 microseconds, among them, the delay of one response is 50 milliseconds, then, the delay of this response is the long-tail delay.
  • P99 standard for business delays there is a commonly used P99 standard for business delays.
  • long-tail delay in this P99 standard is: the delay of 99% of the responses in the computer system should be controlled within a certain time-consuming period, and only 1% of the response delays can be allowed to exceed The certain time-consuming, and the delay of the response exceeding the certain time-consuming is called long-tail delay.
  • the long-tail delay of a thread can be understood as the long-tail delay when the thread performs an input/output (IO) operation. If no page fault occurs during the running of the thread, it is completed once The IO operation may take 10 microseconds. If a page fault occurs, it will take hundreds of microseconds to process the page fault according to the existing technology, which causes the long-tail delay of the thread executing this IO.
  • the solution provided by the application is used to handle page fault exceptions, and it usually only takes a few microseconds to handle page fault exceptions, thus greatly reducing the long-tail delay of the thread.
  • the embodiment of the present application provides a page fault exception processing architecture as shown in FIG. 2 .
  • the page fault exception processing architecture includes:
  • each thread can include multiple coroutines, for example: thread 1 includes coroutine 1, coroutine 2 to coroutine M, thread N includes coroutine 1, coroutine 2 To coroutine P, where N, M and P are all positive integers, which may or may not be equal.
  • each coroutine corresponds to a task.
  • a page fault exception response task can be configured in each thread. The page fault exception response task is used to realize the preservation of the context of the coroutine that generates the page fault exception and the scheduling of the page swapping thread.
  • the kernel mode memory page fault processing mechanism is used to trigger the kernel page fault notification mechanism when a page fault exception occurs in the kernel mode.
  • the kernel page fault notification mechanism is used to quickly switch to the context of the user-mode thread where the coroutine that generated the page fault is located in the kernel-mode page fault exception handling process.
  • the page swap thread is used to respond to tasks based on page fault exceptions, and swap in corresponding physical pages from disk to memory.
  • an embodiment of the page fault processing method provided by the embodiment of the present application includes:
  • the computer system saves the context of the first coroutine that triggers the page fault exception into the shared memory, the first coroutine belongs to the first thread, and the shared memory is the memory that the first thread can access in both the kernel mode and the user mode.
  • the context of the first coroutine refers to data in registers of the processor when the first coroutine is running.
  • the relationship between the first coroutine and the first thread can be understood by referring to thread 1 and coroutine 1, coroutine 2...coroutine M in Figure 2.
  • the first coroutine can be one of the multiple coroutines contained in the first thread. anyone.
  • Each thread can have a dedicated block of shared memory.
  • the shared memory may be configured for the first thread when the first thread is initialized.
  • the page fault exception may be triggered when the first coroutine accesses the swapped out physical page in the memory.
  • the computer system switches from the context of the first coroutine to the context of the first thread, and the context of the first thread is configured in the shared memory when the first thread is initialized.
  • the context of the first thread includes data read from shared memory and written to registers. Switching from the context of the first coroutine to the context of the first thread refers to writing the context of the first thread into a register of the processor.
  • the above registers may include any one or more of a general register, a program counter (program counter, PC), a program state register (program state, PS) and the like.
  • the computer system switches from the kernel state to the user state.
  • the computer system acquires the context of the first coroutine from the shared memory by running the first thread, so as to trigger the page swap process.
  • the subsequent page swap can be performed according to the context of the first coroutine. into the process.
  • the context of the first coroutine is saved in the shared memory in the kernel mode, and after returning to the user mode from the kernel mode, the first coroutine can be obtained from the shared memory by running the first thread context, and then execute the page swap process according to the context of the first coroutine.
  • the monitoring (monitor) thread should be notified in the kernel state, and then the first The thread enters the sleep state until the monitor thread completes the page swap through the swap in thread, then sends a notification message to the kernel state, wakes up the first thread, and then continues to execute the coroutine.
  • the missing page The exception handling process can shorten the delay of page fault exception handling, thereby reducing the input/output (input/output, IO) long-tail delay of the first thread, shortening the delay and correspondingly improving the service throughput.
  • the page fault handling method provided in the embodiment of the present application may further include: when executing the page swap process, running a second coroutine belonging to the first thread to execute a task corresponding to the second coroutine.
  • running the second coroutine when the page swapping process is executed may be understood as running the second coroutine during the execution of the page swapping process, that is: the page swapping process
  • the second coroutine can start at the same time as the page swap process, or it can start at the page swap process Start later.
  • the solution provided by the embodiment of the present application to run the second coroutine asynchronously when executing the page switching process can further improve the service throughput.
  • the page fault processing method provided by the embodiment of the present application can be understood by referring to FIG. 4 .
  • the first thread after the first thread is initialized, it will execute the task corresponding to the first coroutine.
  • the first coroutine triggers a page fault exception during the running process, and then executes the processing flow of the page fault exception, and processes the fault
  • the task of the second coroutine will also be executed.
  • the content described in FIG. 4 may include three stages, which are: 1. Initialization stage; 2. Kernel mode processing page fault exception; 3. User mode processing page fault exception. Introduce respectively below in conjunction with accompanying drawing.
  • Kernel mode handles page fault exceptions.
  • the process includes the following steps:
  • the first coroutine running accesses a physical page that does not exist in the memory and triggers a page fault exception.
  • the process includes the following steps:
  • the process may be: obtaining a destination address from the context of the first coroutine, and the destination address is the address of the physical page to be accessed when the first coroutine triggers a page fault exception; according to the destination address, execute the swap-in process of the corresponding physical page.
  • the context of the first coroutine contains the address of the physical page to be accessed when the first coroutine triggers a page fault exception, that is, the destination address.
  • the computer system can swap in the page corresponding to the destination address from the disk. physical page. This method of directly swapping in the physical page through the destination address can increase the speed of swapping in the physical page, thereby further reducing the time delay of page fault exception processing.
  • the second coroutine of the first thread can also be scheduled, and the task corresponding to the second coroutine can be executed, so that the service throughput can be further improved.
  • the first coroutine is added to the coroutine waiting queue, and the coroutines in the coroutine waiting queue are in a state to be scheduled.
  • the first coroutine can be re-executed, and the execution sequence can be to put the first coroutine into the coroutine waiting queue for scheduling.
  • One or more coroutines are placed in order in the coroutine waiting queue, and the computer system will schedule and execute the coroutines in sequence according to the order in the coroutine waiting queue.
  • the processing process of the page fault exception provided by the embodiment of the present application can be realized by the kernel virtual machine (extended berkeley packet filter, ebpf) mechanism, and the shared memory created by the ebpf mechanism can be called ebpf map.
  • kernel virtual machine extended berkeley packet filter, ebpf
  • ebpf map shared memory created by the ebpf mechanism
  • ebpf is a brand-new design introduced in kernel (kernel) 3.15, which develops the original BPF into a "kernel virtual machine” with a more complex instruction set and a wider application range.
  • the process includes the following steps:
  • the ebpf map includes a map for storing the context of the first thread and a map for storing the context of the coroutine that triggered the page fault exception.
  • the first thread triggers a page fault exception during execution in kernel mode.
  • the ebpf execution function injected in step 501 will be executed, the context of the coroutine that triggered the page fault exception will be saved to the map used to store the context of the coroutine that triggered the page fault exception, and the ebpf The context in the execution function is changed to the context of the first thread saved in step 503 .
  • the user state receives the kernel page fault notification, obtains the context of the coroutine that triggers the page fault from the map used to store the context of the coroutine that triggered the page fault, executes the page swap process, and schedules other coroutines implement.
  • the coroutine that triggered the page fault exception re-enqueues and waits for scheduling.
  • the page fault processing method provided by the embodiment of the present application is particularly effective for scenarios where multiple page fault exceptions are generated concurrently. Even if hundreds of cores trigger page fault exceptions at the same time, the page fault can be completed within a few microseconds (us) For exception handling, compared with the current multi-core concurrent page fault exception scenario, which takes hundreds of microseconds to complete the page fault exception processing process, the processing speed of the solution in this application is much improved, and the delay is greatly reduced. Throughput is increased, thereby also increasing the performance of the computer system.
  • the synchronous swap in feature of Userfaultfd also makes its basic latency no less than 210+us (that is, the latency of SSD media swapping into physical pages).
  • 210+us that is, the latency of SSD media swapping into physical pages.
  • an embodiment of the page fault processing device 60 provided in the embodiment of the present application includes:
  • the first processing unit 601 is configured to save the context of the first coroutine that triggers the page fault exception into the shared memory, the first coroutine belongs to the first thread, and the shared memory is available for the first thread in both the kernel mode and the user mode Accessed memory; the first processing unit 601 may execute step 101 in the above method embodiment.
  • the second processing unit 602 is configured to switch from the context of the first coroutine to the context of the first thread after the first processing unit 601 saves the context of the first coroutine to the shared memory, and the context of the first thread is the first
  • the thread is configured to the shared memory during initialization; the second processing unit 602 can execute step 102 in the above method embodiment.
  • the third processing unit 603 is configured to switch from the kernel mode to the user mode after the second processing unit 602 switches the context; the third processing unit 603 can execute step 103 in the above method embodiment.
  • the fourth processing unit 604 is configured to obtain the context of the first coroutine from the shared memory by running the first thread after the third processing unit 603 switches from the kernel mode to the user mode, so as to trigger a page swap process.
  • the fourth processing unit 604 may execute step 104 in the above method embodiment.
  • the context of the first coroutine is saved in the shared memory in the kernel mode, and after returning to the user mode from the kernel mode, the first coroutine can be obtained from the shared memory by running the first thread context, and then execute the page swap process according to the context of the first coroutine.
  • the monitoring (monitor) thread should be notified in the kernel state, and then the first The thread enters the sleep state until the monitor thread completes the page swap through the swap in thread, then sends a notification message to the kernel state, wakes up the first thread, and then continues to execute the coroutine.
  • the missing page The exception handling process can shorten the delay of page fault exception handling, thereby reducing the input/output (input/output, IO) long-tail delay of the first thread, shortening the delay and correspondingly improving the service throughput.
  • the fourth processing unit 604 is further configured to run a second coroutine belonging to the first thread to execute a task corresponding to the second coroutine when executing the page swap process.
  • the second processing unit 602 is configured to write the context of the first thread into a register of the computer system through the hook function, so as to replace the context of the first coroutine in the register.
  • the fourth processing unit 604 is configured to obtain the context of the first coroutine from the shared memory by running the first thread, and obtain the destination address from the context of the first coroutine, where the destination address is The address of the physical page to be accessed when the page is abnormal; according to the destination address, execute the swap-in process of the corresponding physical page.
  • the fourth processing unit 604 is further configured to add the first coroutine to the coroutine waiting queue after the physical page is swapped into the memory, and the coroutines in the coroutine waiting queue are in a state to be scheduled.
  • the shared memory is configured for the first thread when the first thread is initialized.
  • the page fault exception is triggered when the first coroutine accesses the swapped out physical page in the memory.
  • shared memory is configured through the kernel virtual machine ebpf.
  • FIG. 10 is a schematic diagram of a possible logical structure of a computer device 70 provided by an embodiment of the present application.
  • the computer device 70 includes: a processor 701 , a communication interface 702 , a memory 703 , a disk 704 and a bus 705 .
  • the processor 701 , communication interface 702 , memory 703 and disk 704 are connected to each other through a bus 705 .
  • the processor 701 is used to control and manage the actions of the computer device 70 , for example, the processor 701 is used to execute the steps in the method embodiments in FIGS. 3 to 8 .
  • the communication interface 702 is used to support the computer device 70 to communicate.
  • the memory 703 is used to store program codes and data of the computer device 70 and provide memory space for threads.
  • the memory also includes shared memory. The function of the shared memory can be understood by referring to the shared memory in the foregoing method embodiments. Disk user stores physical pages swapped out from memory.
  • the processor 701 may be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor 701 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.
  • the bus 705 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus or the like.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • a computer-readable storage medium is also provided, and computer-executable instructions are stored in the computer-readable storage medium.
  • the processor of the device executes the computer-executable instructions
  • the device executes the above-mentioned FIG. Steps performed by the processor in FIG. 8 .
  • a computer program product includes computer-executable instructions stored in a computer-readable storage medium; when the processor of the device executes the computer-executable instructions , the device executes the steps executed by the processor in FIG. 3 to FIG. 8 above.
  • a system-on-a-chip in another embodiment of the present application, is also provided, the system on-a-chip includes a processor, and the processor is configured to support the device for processing a page fault exception to implement the steps performed by the processor in FIG. 3 to FIG. 8 above.
  • the system-on-a-chip may further include a memory, and the memory is used for storing necessary program instructions and data of the device for writing data.
  • the system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

Abstract

本申请公开了一种缺页异常的处理方法，应用于计算机系统。该方法包括：将触发缺页异常的第一协程的上下文保存到共享内存中，第一协程归属于第一线程，共享内存为第一线程在内核态和用户态均能访问的内存；从第一协程的上下文切换到第一线程的上下文，第一线程的上下文为第一线程初始化时配置到共享内存的；从内核态切换到用户态；通过运行第一线程从共享内存获取第一协程的上下文，以触发页面换入流程。本申请提供的方案，可以降低缺页异常的处理时延，从而降低了第一线程的IO时延，提高了业务吞吐量。

Description

一种缺页异常的处理方法及相应装置
本申请要求于2021年7月8日提交中国专利局、申请号为202110774711.4、发明名称为“一种缺页异常的处理方法及相应装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，具体涉及一种缺页异常的处理方法及相应装置。
背景技术
主流存储的调度主要采用轻量级线程(lightweight thread,LWT)，该LWT也称为协程。当LWT访问的内存被换出(swap out)时会触发缺页异常(page fault，PF)，需要换入(swap in)页面。由于每个处理器只绑定一个线程，每个线程上执行多个LWT任务，当某个LWT任务触发缺页异常后，需要通过缺页异常处理机制将缺页异常事件通知给用户态，并等待用户态换入页面后才能继续执行该LWT任务。
当前这种缺页异常的处理方式，会导致发生缺页的LWT任务阻塞整个线程，从而导致业务吞吐量下降以及造成该线程的长尾时延。
发明内容
本申请实施例提供一种缺页异常的处理方法，用于降低缺页异常处理的时延以及提高业务吞吐量。本申请实施例还提供了相应的装置、计算机设备、计算机可读存储介质和计算机程序产品等。
本申请第一方面提供一种缺页异常的处理方法，该方法应用于计算机系统，该计算机系统可以为服务器、终端设备、虚拟机(virtual machine，VM)或容器(container)等。该方法包括：将触发缺页异常的第一协程的上下文保存到共享内存中，第一协程归属于第一线程，共享内存为第一线程在内核态和用户态均能访问的内存；从第一协程的上下文切换到第一线程的上下文，第一线程的上下文为第一线程初始化时配置到共享内存的；从内核态切换到用户态；通过运行第一线程从共享内存获取第一协程的上下文，以触发页面换入流程。
本申请中，缺页异常(page fault，PF)也可以称为缺页，通常发生在操作系统(operating system，OS)的内核态，缺页异常发生后，需要对缺页异常进行处理，该处理过程会涉及到内核态和用户态。内核态和用户态是OS的两种模式或两种状态，内核态通常也称为特权状态，用户态通常也称为非特权状态。线程是操作系统调度(处理器调度)的最小单位。协程是一种轻量级线程。一个线程可以包括多个协程，每个协程可以对应一个任务，有时也将协程称为协程任务。
本申请中，第一线程中的“第一”没有实质含义，只是一个在运行时发生了缺页异常的线程，该第一线程也可以被称为业务线程或应用线程。
本申请中，第一协程的上下文包括运行第一协程时处理器的寄存器中的数据。第一线程的上下文包括从共享内存中读出写入到寄存器中的数据。从第一协程的上下文切换到第一线程的上下文指的是将第一线程的上下文写入处理器的寄存器中。以上寄存器可以包括通用寄存器、程序计数器(program counter，PC)、程序状态寄存器(program state，PS) 等任意一个或多个。
该第一方面中，在内核态将第一协程的上下文保存到共享内存中，在从内核态返回用户态后，通过运行第一线程就可以从共享内存中获取该第一协程的上下文，然后依据该第一协程的上下文执行页面换入流程，相比于现有技术中当线程的某一协程触发缺页异常后，要在内核态通知监控(monitor)线程，然后线程进入睡眠状态，直到monitor线程通过页面换入(swap in)线程完成页面换入后，再发通知消息给内核态，唤醒该线程，再继续执行该协程相比，本申请的缺页异常处理过程可以缩短缺页异常处理的时延，从而降低了该第一线程的长尾时延，缩短了时延相应的也提高了业务吞吐量。
本申请中，长尾时延指的是：在计算机系统中，运行线程的过程中，总会有少量该线程所对应的操作的响应的时延高于计算机系统的时延平均值，这些少量响应的时延被称为长尾时延。如：计算机系统中有100个响应，这100个响应的时延平均值为10微秒，其中，有一个响应的时延是50毫秒，那么，这个响应的时延就是长尾时延。另外，业务关于延迟有个常用的P99标准，该P99标准中对长尾时延的定义是：计算机系统中99％响应的延迟要控制在一定耗时以内，只能允许1％响应的延迟超过该一定耗时，超过该一定耗时的响应的时延被称为长尾时延。
本申请中，线程的长尾时延可以理解为是该线程执行输入/输出(input/output，IO)操作时的长尾时延，如果该线程运行过程中没有发生缺页异常，则完成一次IO操作可能需要10微秒，若发生缺页异常，按照现有技术的方案需要几百微秒来处理缺页异常，这就造成了该线程执行本次IO的长尾时延，如果按照本申请所提供的方案来处理缺页异常，通常只需要几微秒就可以处理完缺页异常，这样，极大的降低了该线程的长尾时延。
在第一方面的一种可能的实现方式中，该方法还包括：在执行页面换入流程时，运行归属于第一线程的第二协程以执行第二协程对应的任务。
应理解的是，在执行所述页面换入流程时运行所述第二协程可以理解为在执行所述页面换入流程的过程中运行所述第二协程，即：页面换入流程的执行和第二协程的运行存在时间交叠，但是第二协程开始运行的开始时间点并不做限定，第二协程可以与页面换入流程同时开始，也可以在页面换入流程开始之后再开始。
该种可能的实现方式中，在执行页面换入流程时，还可以异步运行第二协程，这样可以进一步提高业务吞吐量。
在第一方面的一种可能的实现方式中，上述步骤：从第一协程的上下文切换到第一线程的上下文，包括：通过钩子函数将第一线程的上下文写入计算机系统的寄存器中，以替换寄存器中的第一协程的上下文。
该种可能的实现方式中，操作系统可以通过钩子(hook)函数进行上下文切换，将第一线程的上下文写入计算机系统的寄存器中，从而覆盖寄存器中原来存储的第一协程的上下文。
在第一方面的一种可能的实现方式中，上述步骤：通过运行第一线程从共享内存获取第一协程的上下文，以触发页面换入流程，包括：通过运行第一线程从共享内存获取第一协程的上下文，并从第一协程的上下文中获取目的地址，目的地址为第一协程触发缺页异 常时所要访问的物理页的地址；根据目的地址，执行对应物理页的换入流程。
该种可能的实现方式中，第一协程的上下文中包含第一协程触发缺页异常时所要访问的物理页的地址，也就是目的地址，这样，计算机系统就可以从磁盘中换入该目的地址对应的物理页。该种通过目的地址直接换入物理页的方式，可以提高物理页的换入速度，从而进一步减小了缺页异常处理的时延。
在第一方面的一种可能的实现方式中，该方法还包括：当物理页换入内存后，将第一协程添加到协程等待队列，协程等待队列中的协程处于待调度状态。
该种可能的实现方式中，物理页换入后，就可以再重新执行第一协程了，执行顺序可以是将该第一协程放入协程等待队列中等待调度。协程等待队列中按顺序放置有一个或多个协程，计算机系统会按照协程等待队列中的顺序依次调度其中的协程并执行。
在第一方面的一种可能的实现方式中，共享内存是第一线程初始化时为第一线程配置的。
在第一方面的一种可能的实现方式中，缺页异常是通过运行第一协程访问内存中被换出的物理页时触发的。
在第一方面的一种可能的实现方式中，共享内存通过内核虚拟机(extended berkeley packet filter，ebpf)配置。当然，本申请不限于通过ebpf配置，也可以是通过其他方式配置该共享内存。
本申请中，ebpf是内核(kernel)3.15中引入的全新设计，将原先的BPF发展成一个指令集更复杂、应用范围更广泛的“内核虚拟机”。
本申请第二方面提供一种缺页异常的处理装置，该缺页异常的处理装置具有实现上述第一方面或第一方面任意一种可能实现方式的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块，例如：第一处理单元、第二处理单元、第三处理单元和第四处理单元，这四个处理单元可以通过一个处理单元或多个处理单元来实现。
本申请第三方面提供一种计算机设备，该计算机设备包括至少一个处理器、存储器、输入/输出(input/output，I/O)接口以及存储在存储器中并可在处理器上运行的计算机执行指令，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第四方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，一个或多个处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第五方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被一个或多个处理器执行时，一个或多个处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第六方面提供了一种芯片系统，该芯片系统包括至少一个处理器，至少一个处理器用于支持缺页异常的处理装置实现上述第一方面或第一方面任意一种可能的实现方式中所涉及的功能。在一种可能的设计中，芯片系统还可以包括存储器，存储器，用于保存 缺页异常的处理装置必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本申请实施例中，在第一协程触发缺页异常后，在内核态将第一协程的上下文保存到共享内存中，OS从内核态返回用户态后，通过运行第一线程就可以从共享内存中获取该第一协程的上下文，然后依据该第一协程的上下文执行页面换入流程，相比于现有技术中要在内核态通知监控(monitor)线程，然后第一线程进入睡眠状态，直到monitor线程通过页面换入(swap in)线程完成页面换入后，再发通知消息给内核，唤醒第一线程，再继续执行该第一线程的缺页异常处理过程可以缩短缺页异常处理的时延，缩短了时延相应的也提高了业务吞吐量。
附图说明
图1是本申请实施例提供的计算机系统的一实施例示意图；
图2是本申请实施例提供的缺页异常处理架构的一示意图；
图3是本申请实施例提供的缺页异常的处理方法的一实施例示意图；
图4是本申请实施例提供的缺页异常的处理方法的另一实施例示意图；
图5是本申请实施例提供的缺页异常的处理方法的另一实施例示意图；
图6是本申请实施例提供的缺页异常的处理方法的另一实施例示意图；
图7是本申请实施例提供的缺页异常的处理方法的另一实施例示意图；
图8是本申请实施例提供的缺页异常的处理方法的另一实施例示意图；
图9是本申请实施例提供的缺页异常的处理装置的一实施例示意图；
图10是本申请实施例提供的计算机设备的一结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供一种缺页异常的处理方法，用于降低缺页异常处理的时延以及提高业务吞吐量。本申请实施例还提供了相应的装置、计算机设备、计算机可读存储介质和计算机程序产品等。以下分别进行详细说明。
本申请实施例提供的缺页异常处理的方法应用于计算机系统，该计算机系统可以为服务器、终端设备或虚拟机(virtual machine，VM)。
终端设备(也可以称为用户设备(user equipment，UE))是一种具有无线收发功能的 设备，可以部署在陆地上，包括室内或室外、手持或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。所述终端可以是手机(mobile phone)、平板电脑(pad)、带无线收发功能的电脑、虚拟现实(virtual reality，VR)终端、增强现实(augmented reality，AR)终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。
该计算机系统的架构可以参阅图1进行理解。图1为计算机系统的一架构示意图。
如图1所示，该计算机系统的架构包括用户层10、内核20和硬件层30。
该用户层10包括多个应用，每个应用都会对应一个线程，线程是操作系统(operating system，OS)调度的最小单位。一个线程可以包括多个协程，协程是一种轻量级线程。每个协程可以对应一个任务，有时也将协程称为协程任务。本申请中，线程也可以称为业务线程或应用线程等。
内核20是OS负责管理关键资源，并为用户态的线程提供OS调用入口进而在内核提供服务，如：缺页异常(page fault，PF)处理，页表管理以及中断控制等服务。另外，内核20还会处理OS发生的缺页异常(page fault，PF)。缺页异常(page fault，PF)也可以称为缺页，通常发生在操作系统的内核态，缺页异常发生后，需要对缺页异常进行处理，该处理过程会涉及到内核态和用户态。内核态和用户态是OS的两种模式或两种状态，内核态通常也称为特权状态，用户态通常也称为非特权状态。
硬件层30包括内核20运行所依赖的硬件资源，如：处理器、内存(该内存中包括为线程配置的共享内存，本申请中，共享内存指的是为线程在内核态和用户态均能访问的内存)、内存管理单元(memory management unit，MMU)，以及输入/输出(input/output,I/O)设备和磁盘(disk)等。处理器中可以包括寄存器组，该寄存器组可以包括多种类型的寄存器，如：栈帧寄存器、通用寄存器，以及非易失性(callee-saved)寄存器等。寄存器中用于存储线程的上下文或该线程的协程的上下文。
在线程访问内存时若发生缺页异常，则可以通过缺页异常处理机制从磁盘换入(swap in)相应的物理页，从而解决该缺页异常问题。
MMU是一种负责处理中央处理器(central processing unit，CPU)的内存访问请求的计算机硬件。它的功能包括虚拟地址到物理地址的转换、内存保护、CPU高速缓存的控制等。
在计算机系统中，通常一个应用就绑定一个线程，一个线程上会包括多个轻量级线程(lightweight thread,LWT)，该LWT也称为协程。这一个线程会执行所包括的多个协程对应的任务，协程对应的任务也可以称为协程任务。
线程会逐个执行协程任务，当执行任一协程任务时，若发生缺页异常，则当前的缺页异常处理方案会在内核态通知监控(monitor)线程，然后线程进入睡眠状态，直到monitor线程通过页面换入(swap in)线程完成页面换入后，再发通知消息给内核态，唤醒线程，再继续执行该协程任务。当前这种缺页异常处理的方案在缺页异常发生后，该触发缺页异 常的协程任务会阻塞整个线程，从而导致业务吞吐量下降以及造成该线程的长尾时延。
本申请中，长尾时延指的是：在计算机系统中，运行线程的过程中，总会有少量该线程所对应的操作的响应的时延高于计算机系统的时延平均值，这些少量响应的时延被称为长尾时延。如：计算机系统中有100个响应，这100个响应的时延平均值为10微秒，其中，有一个响应的时延是50毫秒，那么，这个响应的时延就是长尾时延。另外，业务关于延迟有个常用的P99标准，该P99标准中对长尾时延的定义是：计算机系统中99％响应的延迟要控制在一定耗时以内，只能允许1％响应的延迟超过该一定耗时，超过该一定耗时的响应的时延被称为长尾时延。
本申请中，线程的长尾时延可以理解为是该线程执行输入/输出(input/output，IO)操作时的长尾时延，如果该线程运行过程中没有发生缺页异常，则完成一次IO操作可能需要10微秒，若发生缺页异常，按照现有技术的方案需要几百微秒来处理缺页异常，这就造成了该线程执行本次IO的长尾时延，如果按照本申请所提供的方案来处理缺页异常，通常只需要几微秒就可以处理完缺页异常，这样，极大的降低了该线程的长尾时延。
为了加快缺页异常处理的速度，本申请实施例提供一种如图2所示的缺页异常处理架构，如图2所示，该缺页异常处理架构包括：
多个线程，如线程1至线程N，每个线程中都可以包括多个协程，如：线程1包括协程1、协程2至协程M，线程N包括协程1、协程2至协程P，其中，N、M和P都为正整数，可以相等，也可以不相等。其中，每个协程对应一个任务。每个线程中都可以配置一个缺页异常响应任务。该缺页异常响应任务用于实现产生缺页异常的协程上下文的保存以及页面换入线程的调度。
内核态内存缺页处理机制，用于在内核态发生缺页异常时，触发内核缺页通知机制。
内核缺页通知机制，用于实现在内核态缺页异常处理流程中快速切换到产生缺页的协程所在的用户态的线程的上下文。
页面换入线程，用于基于缺页异常响应任务，从磁盘换入相应的物理页到内存。
基于上述图1的计算机系统和图2所示的缺页异常处理架构，下面结合附图介绍本申请实施例提供的缺页异常的处理方法。
如图3所示，本申请实施例提供的缺页异常的处理方法的一实施例包括：
101.计算机系统将触发缺页异常的第一协程的上下文保存到共享内存中，第一协程归属于第一线程，共享内存为第一线程在内核态和用户态均能访问的内存。
第一协程的上下文指的是运行第一协程时处理器的寄存器中的数据。
第一协程与第一线程的关系可以参阅图2中线程1与协程1、协程2…协程M进行理解，第一协程可以是第一线程所包含的多个协程中的任意一个。
每个线程都可以有一块专用的共享内存。
可选地，该共享内存可以是第一线程初始化时为第一线程配置的。
可选地，缺页异常可以是通过运行第一协程访问内存中被换出的物理页时触发的。
102.计算机系统从第一协程的上下文切换到第一线程的上下文，第一线程的上下文为第一线程初始化时配置到共享内存的。
第一线程的上下文包括从共享内存中读出然后写入到寄存器中的数据。从第一协程的上下文切换到第一线程的上下文指的是将第一线程的上下文写入处理器的寄存器中。以上寄存器可以包括通用寄存器、程序计数器(program counter，PC)、程序状态寄存器(program state，PS)等任意一个或多个。
103.计算机系统从内核态切换到用户态。
104.计算机系统通过运行第一线程从共享内存获取第一协程的上下文，以触发页面换入流程。
因为第一协程触发了缺页异常，所以，在用户态通过运行第一线程从共享内存获取该第一协程的上下文后，就可以根据该第一协程的上下文，执行后续的页面换入流程。
本申请实施例提供的方案，在内核态将第一协程的上下文保存到共享内存中，在从内核态返回用户态后，通过运行第一线程就可以从共享内存中获取该第一协程的上下文，然后依据该第一协程的上下文执行页面换入流程，相比于现有技术中当某一协程触发缺页异常后，要在内核态通知监控(monitor)线程，然后第一线程进入睡眠状态，直到monitor线程通过页面换入(swap in)线程完成页面换入后，再发通知消息给内核态，唤醒第一线程，再继续执行该协程相比，本申请的缺页异常处理过程可以缩短缺页异常处理的时延，从而降低了该第一线程的输入/输出(input/output，IO)长尾时延，缩短了时延相应的也提高了业务吞吐量。
可选地，本申请实施例所提供的缺页异常的处理方法还可以包括：在执行页面换入流程时，运行归属于第一线程的第二协程以执行第二协程对应的任务。
应理解的是，在执行所述页面换入流程时运行所述第二协程可以理解为在执行所述页面换入流程的过程中运行所述第二协程，即：页面换入流程的执行和第二协程的运行存在时间交叠，但是第二协程开始运行的开始时间点并不做限定，第二协程可以与页面换入流程同时开始，也可以在页面换入流程开始之后再开始。
本申请实施例提供的这种在执行页面换入流程时，异步运行第二协程的方案，可以进一步提高业务吞吐量。
总体上来说，本申请实施例提供的缺页异常的处理方法可以参阅图4进行理解。
如图4所示，第一线程初始化后，会执行第一协程对应的任务，该第一协程在运行过程中触发缺页异常，然后会执行缺页异常的处理流程，并在处理缺页异常时还会执行第二协程的任务。
图4所描述的内容可以包括三个阶段，分别为：1.初始化阶段；2.内核态处理缺页异常；3.用户态处理缺页异常。下面分别结合附图进行介绍。
1.初始化阶段。
如图5所示，运行第一线程的主函数，执行如下步骤：
201.初始化共享内存，也就是为该第一线程分配共享内存。
202.通过上下文获取函数(getcontext)获取初始化时该第一线程的上下文。
203.将初始化时第一线程的上下文设置到共享内存中。
2.内核态处理缺页异常。
如图6所示，该过程包括如下步骤：
301.在内核态，运行第一协程访问内存中不存在的物理页触发缺页异常。
302.通过钩子(hook)函数，保存第一协程的上下文到共享内存中。
303.通过钩子(hook)函数进行上下文切换，将共享内存中的第一线程的上下文写入到计算机系统的寄存器中。
也就是：通过钩子函数将第一线程的上下文写入计算机系统的寄存器中，以替换寄存器中的第一协程的上下文。
304.从内核态返回用户态。
3.用户态处理缺页异常。
如图7所示，该过程包括如下步骤：
由上述图6的过程描述可知，内核态缺页异常处理结束后，会返回用户态，从而在用户态执行缺页异常处理。
401.在用户态，通过运行第一线程从共享内存中获取其中保存的第一协程的上下文。
402.在第一线程上保存该第一协程的上下文。
403.根据该第一协程的上下文，触发页面换入流程。
该过程可以是：从第一协程的上下文中获取目的地址，目的地址为第一协程触发缺页异常时所要访问的物理页的地址；根据目的地址，执行对应物理页的换入流程。
也就是说：第一协程的上下文中包含第一协程触发缺页异常时所要访问的物理页的地址，也就是目的地址，这样，计算机系统就可以从磁盘中换入该目的地址对应的物理页。该种通过目的地址直接换入物理页的方式，可以提高物理页的换入速度，从而进一步减小了缺页异常处理的时延。
另外，执行页面换入流程时，还可以调度该第一线程的第二协程，并执行该第二协程对应的任务，这样可以进一步提高业务吞吐量。
页面换入流程结束后，也就是当物理页换入内存后，将第一协程添加到协程等待队列，协程等待队列中的协程处于待调度状态。
也就是说，物理页换入后，就可以再重新执行第一协程了，执行顺序可以是将该第一协程放入协程等待队列中等待调度。协程等待队列中按顺序放置有一个或多个协程，计算机系统会按照协程等待队列中的顺序依次调度其中的协程并执行。
本申请实施例提供的缺页异常的处理过程可以通过内核虚拟机(extended berkeley packet filter，ebpf)机制来实现，通过ebpf机制创建的共享内存可以称为ebpf map。
本申请中，ebpf是内核(kernel)3.15中引入的全新设计，将原先的BPF发展成一个指令集更复杂、应用范围更广泛的“内核虚拟机”。
通过ebpf机制来实现时，该缺页异常的处理过程可以参阅图8进行理解。
如图8所示，该过程包括如下步骤：
501.在第一线程中注入ebpf执行函数，创建ebpf map。
该ebpf map包括用于存储第一线程的上下文的map和用于存储触发缺页异常的协程的上下文的map。
502.获取第一线程的上下文。
503.将第一线程的上下文保存到用于存储第一线程的上下文的map。
504.第一线程在内核态执行过程中触发缺页异常。
505.在内核的Page fault处理流程中，会执行步骤501注入的ebpf执行函数，保存触发缺页异常的协程的上下文到用于存储触发缺页异常的协程的上下文的map，并将ebpf执行函数中的上下文修改为步骤503中保存的第一线程的上下文。
506.内核态缺页异常处理完成，返回用户态，程序跳转到缺页异常处理函数处执行。
507.用户态接收到内核缺页异常通知，从用于存储触发缺页异常的协程的上下文的map中获取触发缺页异常的协程的上下文，执行页面换入流程，并调度其他协程执行。
页面换入流程完成后，触发缺页异常的协程重新入队等待调度。
本申请实施例提供的缺页异常的处理方法，对于多个并发产生缺页异常的场景效果尤为明显，即使上百核同时触发缺页异常，在几个微秒(us)也可以完成缺页异常的处理，相对于当前多核并发缺页异常的场景下要几百微秒才能完成缺页异常的处理过程相比，本申请的方案的处理速度提高了很多，极大的降低了时延，提高了吞吐量，从而也提高了计算机系统的性能。
为了便于说明本申请的效果，以144核并发产生缺页异常的场景为例，下面通过表1来介绍采用现有的缺页异常处理机制和本申请提供的缺页异常处理机制在缺页异常处理和线程阻塞方面的时延。
表1：时延对比
Figure PCTCN2022103611-appb-000001
由表1第二列和第三列的对比可知，本申请提供的方案，在缺页异常处理和线程阻塞方面的时延相对于现有技术都缩短了很多。在大规格高并发的环境下，现有的Userfaultfd中，缺页异常通知到用户态的时延已经超过600微秒，对于业务根本无法接受。通过分析可知，缺页异常通知到用户态的时延在高并发的场景下，对文件句柄的竞争异常激烈，并且随着核数的增加，竞争会愈发激烈。Userfaultfd的同步swap in特性也使得其基础时延不低于210+us(即SSD介质换入物理页面的时延)。而通过使用本申请，可以在上百核并发产生缺页异常的场景下，仍能达到微秒级的通知时延。随着主机核数的增加，收益越明显。
以上介绍了缺页异常的处理方法，下面结合附图介绍本申请实施例提供的缺页异常的处理装置。
如图9所示，本申请实施例提供的缺页异常的处理装置60的一实施例包括：
第一处理单元601，用于将触发缺页异常的第一协程的上下文保存到共享内存中，第一 协程归属于第一线程，共享内存为第一线程在内核态和用户态均能访问的内存；该第一处理单元601可执行上述方法实施例中的步骤101。
第二处理单元602，用于在第一处理单元601将第一协程的上下文保存到共享内存后，从第一协程的上下文切换到第一线程的上下文，第一线程的上下文为第一线程初始化时配置到共享内存的；该第二处理单元602可执行上述方法实施例中的步骤102。
第三处理单元603，用于在第二处理单元602切换上下文后，从内核态切换到用户态；该第三处理单元603可执行上述方法实施例中的步骤103。
第四处理单元604，用于在第三处理单元603从内核态切换到用户态后，通过运行第一线程从共享内存获取第一协程的上下文，以触发页面换入流程。该第四处理单元604可执行上述方法实施例中的步骤104。
本申请实施例提供的方案，在内核态将第一协程的上下文保存到共享内存中，在从内核态返回用户态后，通过运行第一线程就可以从共享内存中获取该第一协程的上下文，然后依据该第一协程的上下文执行页面换入流程，相比于现有技术中当某一协程触发缺页异常后，要在内核态通知监控(monitor)线程，然后第一线程进入睡眠状态，直到monitor线程通过页面换入(swap in)线程完成页面换入后，再发通知消息给内核态，唤醒第一线程，再继续执行该协程相比，本申请的缺页异常处理过程可以缩短缺页异常处理的时延，从而降低了该第一线程的输入/输出(input/output，IO)长尾时延，缩短了时延相应的也提高了业务吞吐量。
可选地，第四处理单元604，还用于在执行页面换入流程时，运行归属于第一线程的第二协程以执行第二协程对应的任务。
可选地，第二处理单元602，用于通过钩子函数将第一线程的上下文写入计算机系统的寄存器中，以替换寄存器中的第一协程的上下文。
可选地，第四处理单元604，用于通过运行第一线程从共享内存获取第一协程的上下文，并从第一协程的上下文中获取目的地址，目的地址为第一协程触发缺页异常时所要访问的物理页的地址；根据目的地址，执行对应物理页的换入流程。
可选地，第四处理单元604，还用于当物理页换入内存后，将第一协程添加到协程等待队列，协程等待队列中的协程处于待调度状态。
可选地，共享内存是第一线程初始化时为第一线程配置的。
可选地，缺页异常是通过运行第一协程访问内存中被换出的物理页时触发的。
可选地，共享内存通过内核虚拟机ebpf配置。
以上，本申请实施例所提供的缺页异常的处理装置60的相关内容可以参阅前述方法实施例部分的相应内容进行理解，此处不再重复赘述。
图10所示，为本申请的实施例提供的计算机设备70的一种可能的逻辑结构示意图。计算机设备70包括：处理器701、通信接口702、内存703、磁盘704以及总线705。处理器701、通信接口702、内存703以及磁盘704通过总线705相互连接。在本申请的实施例中，处理器701用于对计算机设备70的动作进行控制管理，例如，处理器701用于执行图3至图8的方法实施例中的步骤。通信接口702用于支持计算机设备70进行通信。内存703，用于存储计算 机设备70的程序代码和数据，并为线程提供内存空间，内存中还包括共享内存，共享内存的作用可以参阅前述方法实施例部分共享内存进行理解。磁盘用户存储从内存换出的物理页。
其中，处理器701可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器701也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线705可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的处理器执行该计算机执行指令时，设备执行上述图3至图8中处理器所执行的步骤。
在本申请的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；当设备的处理器执行该计算机执行指令时，设备执行上述图3至图8中处理器所执行的步骤。
在本申请的另一实施例中，还提供一种芯片系统，该芯片系统包括处理器，该处理器用于支持缺页异常的处理装置实现上述图3至图8中处理器所执行的步骤。在一种可能的设计中，芯片系统还可以包括存储器，存储器，用于保存数据写入的装置必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请实施例各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请实施例各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (17)

  1. 一种缺页异常的处理方法，所述方法应用于计算机系统，其特征在于，所述方法包括：
    将触发缺页异常的第一协程的上下文保存到共享内存中，所述第一协程归属于第一线程，所述共享内存为所述第一线程在内核态和用户态均能访问的内存；
    从所述第一协程的上下文切换到第一线程的上下文，所述第一线程的上下文为所述第一线程初始化时配置到所述共享内存的；
    从所述内核态切换到所述用户态；
    通过运行所述第一线程从所述共享内存获取所述第一协程的上下文，以触发页面换入流程。
  2. 根据权利要求1所述的处理方法，其特征在于，所述方法还包括：
    在执行所述页面换入流程时，运行归属于所述第一线程的第二协程以执行所述第二协程对应的任务。
  3. 根据权利要求1或2所述的处理方法，其特征在于，所述从所述第一协程的上下文切换到第一线程的上下文，包括：
    通过钩子函数将所述第一线程的上下文写入所述计算机系统的寄存器中，以替换所述寄存器中的所述第一协程的上下文。
  4. 根据权利要求1-3任一项所述的处理方法，其特征在于，所述通过运行所述第一线程从所述共享内存获取所述第一协程的上下文，以触发页面换入流程，包括：
    通过运行所述第一线程从所述共享内存获取所述第一协程的上下文，并从所述第一协程的上下文中获取目的地址，所述目的地址为所述第一协程触发所述缺页异常时所要访问的物理页的地址；
    根据所述目的地址，执行对应物理页的换入流程。
  5. 根据权利要求4所述的处理方法，其特征在于，所述方法还包括：
    当所述物理页换入内存后，将所述第一协程添加到协程等待队列，所述协程等待队列中的协程处于待调度状态。
  6. 根据权利要求1-5任一项所述的处理方法，其特征在于，所述共享内存是所述第一线程初始化时为所述第一线程配置的。
  7. 根据权利要求1-6任一项所述的处理方法，其特征在于，所述缺页异常是通过运行所述第一协程访问内存中被换出的物理页时触发的。
  8. 根据权利要求1-7任一项所述的处理方法，其特征在于，
    所述共享内存通过内核虚拟机ebpf配置。
  9. 一种缺页异常的处理装置，其特征在于，包括：
    第一处理单元，用于将触发缺页异常的第一协程的上下文保存到共享内存中，所述第一协程归属于第一线程，所述共享内存为所述第一线程在内核态和用户态均能访问的内存；
    第二处理单元，用于在所述第一处理单元将所述第一协程的上下文保存到共享内存后，从所述第一协程的上下文切换到第一线程的上下文，所述第一线程的上下文为所述第一线 程初始化时配置到所述共享内存的；
    第三处理单元，用于在第二处理单元切换上下文后，从所述内核态切换到所述用户态；
    第四处理单元，用于在第三处理单元从所述内核态切换到所述用户态后，通过运行所述第一线程从所述共享内存获取所述第一协程的上下文，以触发页面换入流程。
  10. 根据权利要求9所述的处理装置，其特征在于，
    所述第四处理单元，还用于在执行所述页面换入流程时，运行归属于所述第一线程的第二协程以执行所述第二协程对应的任务。
  11. 根据权利要求9或10所述的处理装置，其特征在于，
    所述第二处理单元，用于通过钩子函数将所述第一线程的上下文写入所述计算机系统的寄存器中，以替换所述寄存器中的所述第一协程的上下文。
  12. 根据权利要求9-11任一项所述的处理装置，其特征在于，
    所述第四处理单元，用于通过运行所述第一线程从所述共享内存获取所述第一协程的上下文，并从所述第一协程的上下文中获取目的地址，所述目的地址为所述第一协程触发所述缺页异常时所要访问的物理页的地址；根据所述目的地址，执行对应物理页的换入流程。
  13. 根据权利要求12所述的处理装置，其特征在于，
    所述第四处理单元，还用于当所述物理页换入内存后，将所述第一协程添加到协程等待队列，所述协程等待队列中的协程处于待调度状态。
  14. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被一个或多个处理器执行时实现如权利要求1-8任一项所述的方法。
  15. 一种计算设备，其特征在于，包括一个或多个处理器和存储有计算机程序的计算机可读存储介质；
    所述计算机程序被所述一个或多个处理器执行时实现如权利要求1-8任一项所述的方法。
  16. 一种芯片系统，其特征在于，包括一个或多个处理器，所述一个或多个处理器被调用用于执行如权利要求1-8任一项所述的方法。
  17. 一种计算机程序产品，其特征在于，包括计算机程序，所述计算机程序当被一个或多个处理器执行时用于实现如权利要求1-8任一项所述的方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116321276A (zh) * 2023-05-19 2023-06-23 阿里巴巴（中国）有限公司 时延确定方法、通信网络、设备和存储介质

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116069638B (zh) * 2023-01-19 2023-09-01 蔷薇大树科技有限公司 一种基于内核态模拟分布式异常状态的方法
CN117573418B (zh) * 2024-01-15 2024-04-23 北京趋动智能科技有限公司 针对显存访问异常的处理方法、系统、介质及设备
CN117573419B (zh) * 2024-01-16 2024-04-26 上海芯联芯智能科技有限公司 一种页面异常处理方法及装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102402487A (zh) * 2011-11-15 2012-04-04 北京天融信科技有限公司 一种零拷贝接收报文的方法和系统
US20170206169A1 (en) * 2016-01-15 2017-07-20 Stmicroelectronics (Grenoble 2) Sas Apparatus and methods implementing dispatch mechanisms for offloading executable functions
CN107168801A (zh) * 2017-05-12 2017-09-15 南京大学 基于多内核页表的内核动态数据隔离以及保护技术
CN109298922A (zh) * 2018-08-30 2019-02-01 百度在线网络技术（北京）有限公司 并行任务处理方法、协程框架、设备、介质和无人车
CN111338831A (zh) * 2020-02-10 2020-06-26 北京字节跳动网络技术有限公司 一种多线程运行性能的处理方法、装置、介质和电子设备
CN111767159A (zh) * 2020-06-24 2020-10-13 浙江大学 一种基于协程的异步系统调用系统
CN112613276A (zh) * 2020-12-28 2021-04-06 南京中孚信息技术有限公司 一种流式文档解析的并行执行方法及系统

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102402487A (zh) * 2011-11-15 2012-04-04 北京天融信科技有限公司 一种零拷贝接收报文的方法和系统
US20170206169A1 (en) * 2016-01-15 2017-07-20 Stmicroelectronics (Grenoble 2) Sas Apparatus and methods implementing dispatch mechanisms for offloading executable functions
CN107168801A (zh) * 2017-05-12 2017-09-15 南京大学 基于多内核页表的内核动态数据隔离以及保护技术
CN109298922A (zh) * 2018-08-30 2019-02-01 百度在线网络技术（北京）有限公司 并行任务处理方法、协程框架、设备、介质和无人车
CN111338831A (zh) * 2020-02-10 2020-06-26 北京字节跳动网络技术有限公司 一种多线程运行性能的处理方法、装置、介质和电子设备
CN111767159A (zh) * 2020-06-24 2020-10-13 浙江大学 一种基于协程的异步系统调用系统
CN112613276A (zh) * 2020-12-28 2021-04-06 南京中孚信息技术有限公司 一种流式文档解析的并行执行方法及系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116321276A (zh) * 2023-05-19 2023-06-23 阿里巴巴（中国）有限公司 时延确定方法、通信网络、设备和存储介质
CN116321276B (zh) * 2023-05-19 2023-10-31 阿里巴巴（中国）有限公司 时延确定方法、通信网络、设备和存储介质

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